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SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
GENERAL CHARACTERISTICS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
• pin and function compatible with
Architects of Modern Power™
product standards
• compact package, horizontal:
25.7 x 13.8 x 8.2 mm
• compact package, vertical:
26.3 x 7.6 x 15.60 mm
• 25 A output
• high efficiency
• auto compensation
• SMBus interface
• PMBus™ Compatible
input voltage
(Vdc)
4.5~14
output voltage
output current
output wattage
(Vdc)
max
(A)
max
(W)
0.6~3.3
25
82.5
SC
ON
T
NDM2Z-25
IN
MODEL
UE
D
4.5~14 V input range
0.6~3.3 V programmable output
voltage tracking
voltage margining
active current sharing
Snapshot™ parametric capture
voltage/current/temperature monitoring
synchronization and phase spreading
remote differential voltage sense
programmable soft start and soft stop
fault management
PART NUMBER KEY
NDM2Z-25 X - X - XXX
Base Number
DI
Module Orientation and Pin Style:
HS = horizontal, surface mount
HT = horizontal, through hole mount
V = vertical
Firmware Conguration:
000~ZZZ
Pin Conguration:
A = Both functions
present, 4.0 mm pin
length (V)
B = Both functions
present, 5.5 mm pin
length (V)
P = Power Good (H)
V = Voltage Track (H)
* HS and HT modules are delivered on tape and reel
* V modules are delivered in trays
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Example part number: NDM2Z-25V-A-001
vertical module
4.0 mm pin length
rmware conguration 001
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 2 of 32
ABSOLUTE MAXIMUM RATINGS
parameter
conditions/description
min
typ
max
units
operating temperature (see
thermal consideration section)
(TP1)
-40
125
°C
storage temperature (TS)
-40
125
°C
logic I/O voltage
CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC,
DDC, PG
ground voltage differential
-S, PREF, GND
analog pin voltage
VO, +S, VTRK
Notes:
UE
D
input voltage (see operating information section for input and
output voltage relations)(VI)
-0.3
16
V
-0.3
6.5
V
-0.3
0.3
V
-0.3
6.5
V
Stress in excess of Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are
normally tested with one parameter at a time exceeding the limits in the Electrical Specication. If exposed to stress above these limits, function and performance
may degrade in an unspecied manner.
Configuration File
IN
This product is designed with a digital control circuit. The control circuit uses a conguration le which determines the
functionality and performance of the product. The Electrical Specication table shows parameter values of functionality
and performance with the default conguration le, unless otherwise specied. The default conguration le is designed
to t most application needs with focus on high efciency. If different characteristics are required it is possible to change
the conguration le to optimize certain performance characteristics. Note that current sharing operation requires changed
conguration le.
SC
ON
T
PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL
TP1 = -30 to +95 °C, VI = 4.5 to 14 V, VI> VO + 1.0 V
Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specied under conditions.
External CIN = 470 NjF/10 mƻ, COUT = 470 NjF/10 mƻ. See Operating Information section for selection of capacitor types.
Sense pins are connected to the output pins.
parameter
conditions/description
input voltage rise time (VI)
monotonic
min
output voltage without
pin-strap (VO)
output voltage adjustment
range (VO)
output voltage adjustment
including margining (VO)
see note 17
units
2.4
V/ms
V
0.60
3.3
V
0.54
3.63
V
±0.025
%FS
including line, load, temp see note 14
-1
1
%
current sharing operation see note 15
-2
2
%
internal resistance +S/-S to
VOUT/GND (VO)
DI
max
1.2
output voltage set-point
resolution (VO)
output voltage accuracy (VO)
typ
47
ƻ
line regulation (VO)
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
2
2
2
3
mV
mV
mV
mV
load regulation (VO)
IO = 0~100%
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
2
2
2
3
mV
mV
mV
mV
output ripple & noise (Voac)
CO= 470 NjF (minimum external
capacitance) see note 11
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
20
30
40
60
mVp-p
mVp-p
mVp-p
mVp-p
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date 12/21/2015 Ϳ page 3 of 32
PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL (CONTINUED)
parameter
conditions/description
min
output current (IO)
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
27
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
50% of max IO
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
max IO
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
input idling power (no load)(Pli)
default conguration:
continues conduction
mode, CCM
input standby power (PCTRL)
turned off with CTRL-pin
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
SC
ON
T
power dissipation at max IO (Pd)
VO
VO
VO
VO
IN
RMS, hiccup mode,
see note 3
efciency (dž)
units
25
A
1.58
2.43
4.13
7.32
current limit threshold (Ilim)
short circuit current(ISC)
max
A
A
A
A
37.5
A
UE
D
static input current at max IO
(IS)
typ
0
default conguration:
monitoring enabled,
precise timing enabled
internal input capacitance (Ci)
internal output capacitance (Co)
8
6
5
4
A
A
A
A
84.4
89.4
93.1
95.2
%
%
%
%
79.2
85.7
90.8
93.9
%
%
%
%
3.93
4.17
4.55
5.34
W
W
W
W
0.56
0.57
0.67
0.92
W
W
W
W
170
mW
70
F
200
F
see note 9
300
15,000
F
ESR range of capacitors
(per single capacitor) (COUT)
see note 9
5
30
mƻ
load transient peak voltage
deviation (L to H/H to L) load
step 25-75-25% of max IO(Vtr1)
default conguration
di/dt = 2 A/Njs CO = 470
NjF (minimum external
capacitance)
see note 12
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
95
105
115
168
mV
mV
mV
mV
load transient recovery time
note 5 (L to H/H to L) load step
25-75-25% of max IO(ttr1)
default conguration
di/dt = 2 A/Njs CO = 470
NjF (minimum external
capacitance)
see note 12
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
74
85
122
140
Njs
Njs
Njs
Njs
320
kHz
200-640
kHz
DI
total external output
capacitance (COUT)
switching frequency (fs)
switching frequency range (fs)
PMBus congurable
switching frequency set-point
accuracy (fs)
-5
5
%
control circuit PWM duty cycle
5
95
%
minimum sync pulse width
input clock frequency drift
tolerance
150
external clock source
-13
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ns
13
%
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date 12/21/2015 Ϳ page 4 of 32
PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL (CONTINUED)
parameter
conditions/description
min
UVLO threshold
UVLO threshold range
PMBus congurable
set point accuracy
UVLO hysteresis range
PMBus congurable
delay
fault response
see note 3
IOVP threshold
IOVP threshold range
PMBus congurable
power good, PG, see note 2
PG hysteresis
PG delay
PG delay range
UVP threshold
output voltage over/under
voltage protection, OVP/UVP
PMBus congurable
V
2.5
Njs
16
V
4.2-16
V
150
mV
V
0-11.8
V
2.5
Njs
90
%Vo
5
%Vo
direct after DLC
ms
0-500
s
85
%Vo
%Vo
5
%Vo
OVP threshold
115
%Vo
100-115
%Vo
25
Njs
5-60
Njs
OVP threshold range
PMBus congurable
UVP/OVP
response time range
PMBus congurable
fault response
see note 3
automatic restart, 70 ms
OCP threshold range
PMBus congurable
protection delay
see note 4
protection delay range
PMBus congurable
fault response
see note 3
32
OTP threshold range
PMBus congurable
OTP hysteresis
OTP hysteresis range
PMBus congurable
fault response
see note 3
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A
0-32
A
32
TSW
1-32
TSW
automatic restart, 70 ms
OTP threshold
DI
0-10.15
0-100
OCP threshold
over temperature protection,
OTP at P2 see note 8
V
UVP hysteresis
UVP/OVP response time
over current protection, OCP
mV
automatic restart, 70 ms
PMBus congurable
SC
ON
T
UVP threshold range
see note 3
IN
PG threshold
150
0.35
1
delay
fault response
V
V
-150
IOVP hysteresis
IOVP hysteresis range
3.85
automatic restart, 70 ms
PMBus congurable
set point accuracy
input over voltage protection,
IOVP
units
3.85-14
-150
UVLO hysteresis
max
UE
D
input under voltage lockout,
UVLO
typ
120
-40
°C
125
°C
25
°C
0-165
°C
automatic restart, 240 ms
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 5 of 32
PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL (CONTINUED)
logic input low threshold(VIL)
logic input high threshold (VIH)
logic input low sink current(IIL)
conditions/description
min
SYNC, SA0, SA1, SCL, SDA, DDC, CTRL, VSET
logic output low sink current
(IOL)
see note 1
hold time, SMBus(thold)
see note 1
bus free time, SMBus(tfree)
see note 1
internal capacitance on logic
pins (CP)
initialization time
delay duration
delay duration range
delay accuracy turn-on
VTRK regulation accuracy
(VO - VVTRK)
current difference between
products in a current
sharing group
DI
0.4
V
V
V
4
mA
2
mA
ns
ns
2
ms
pF
see note 10
40
ms
see note 16
10
ms
5-500,000
ms
-0.25/+4
ms
-0.25/+4
ms
PMBus congurable
ramp duration range
PMBus congurable
ramp time accuracy
current sharing
operation
VVTRK = 5.5 V
100% tracking, see note 7
ms
ms
100
Njs
20
%
110
-100
current sharing operation 2 phases, 100% tracking
VO = 1.0 V, 10 ms ramp
200
NjA
100
mV
±100
100% Tracking
current sharing operation 100% Tracking
steady state operation
10
0-200
mV
-1
1
%
-2
2
%
Max 2 x READ_IOUT monitoring
accuracy
ramp-up
2
number of products in a current
sharing group
monitoring accuracy
mA
250
ramp duration
VTRK tracking ramp accuracy
(VO - VVTRK)
0.6
10
SC
ON
T
delay accuracy turn-off
VTRK input bias current
V
300
IN
setup time, SMBus(tSET)
output voltage ramp time
see note 13
units
0.8
2.25
SYNC, SCL, SDA, SALERT, DDC, PG
logic output high source current
(IOH)
output voltage delay time see
note 6
max
2
CTRL
logic output low signal level
(VOL)
logic output high signal level
(VOH)
typ
UE
D
parameter
A
7
READ_VIN vs VI
3
%
READ_VOUT vs VO
1
%
READ_IOUT vs IO
IO = 0-20 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 1.0 V
±1.7
A
READ_IOUT vs IO
IO = 0-20 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 0.6-3.3 V
±3
A
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 6 of 32
PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL (CONTINUED)
1: See section I2C/SMBus Setup and Hold Times – Denitions.
2: Monitorable over PMBus Interface.
3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart.
4: Tsw is the switching period.
5: Within +/-3% of VO
6: See section Soft-start Power Up.
7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth.
8: See section Over Temperature Protection (OTP).
9: See section External Capacitors.
10: See section Initialization Procedure.
11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.
12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.
13: Time for reaching 100% of nominal Vout.
14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.
15: Accuracy here means deviation from ideal output voltage level given by congured droop and actual load. Includes line, load and temperature variations.
16: For current sharing the Output Voltage Delay Time must be recongured to minimum 15 ms.
17: For steady state operation above 1.05 x 3.3 V, please contact your local CUI sales representative.
DI
SC
ON
T
IN
UE
D
Notes:
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 7 of 32
TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)
Power Dissipation vs. Output Current, VI = 5 V
[%]
[W]
100
6
95
5
4
90
0.6 V
80
75
0.6 V
3
1.0 V
85
0
5
10
15
20
UE
D
Efficiency vs. Output Current, VI = 5 V
1.8 V
2
3.3 V
1
0
25 [A]
1.0 V
1.8 V
3.3 V
0
10
15
20
25 [A]
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
IN
Efficiency vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
Efficiency vs. Output Current, VI = 12 V
Power Dissipation vs. Output Current, VI = 12 V
[%]
[W]
100
6
5
SC
ON
T
95
4
90
0.6 V
80
0
5
10
15
20
0.6 V
3
1.0 V
85
75
5
1.0 V
1.8 V
2
1.8 V
3.3 V
1
3.3 V
0
25 [A]
0
5
10
15
20
25 [A]
Efficiency vs. load current and output voltage at
TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
Efficiency vs. Output Current and
Switching Frequency
Power Dissipation vs. Output Current and
Switching frequency
[%]
[W]
95
6
5
90
DI
200
kHz
85
200
kHz
4
320
kHz
3
320
kHz
80
480
kHz
2
480
kHz
75
640
kHz
1
640
kHz
70
0
5
10
15
20
Efficiency vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ.
Default configuration except changed frequency
0
25 [A]
0
5
10
15
20
25 [A]
Dissipated power vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ.
Default configuration except changed frequency
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 8 of 32
TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)
[mV]
400
Load Transient vs. External Capacitance, VO = 3.3 V
Universal PID,
No NLR
DLC,
No NLR
300
300
Universal PID,
Default NLR
200
DLC,
Default NLR
Universal PID,
Opt. NLR
100
[mV]
400
200
100
DLC,
Opt. NLR
0
0
1
2
3
4
0
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step (6.25-18.75-6.25 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/µs
Universal PID,
No NLR
UE
D
Load Transient vs. External Capacitance, VO = 1.0 V
DLC,
No NLR
Universal PID,
Default NLR
DLC,
Default NLR
Universal PID,
Opt. NLR
DLC,
Opt. NLR
0
[mV]
400
SC
ON
T
DLC,
No NLR
Universal PID,
Default NLR
200
DLC,
Default NLR
Universal PID,
Opt. NLR
100
DLC,
Opt. NLR
300
400
500
3
4
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step (6.25-18.75-6.25 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25 °C, VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/µs
Universal PID,
No NLR
300
200
2
IN
Load transient vs. Switch Frequency
0
1
600 [kHz]
Load transient peak voltage deviation vs. frequency.
Step-change (6.25-18.75-6.25 A).
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ
DI
Note: For Universal PID, see section Dynamic Loop Compensation (DLC).
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date 12/21/2015 Ϳ page 9 of 32
TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)
Output Current Derating, VO = 1.0 V
[A]
[A]
30
30
3.0 m/s
25
25
2.0 m/s
20
20
1.0 m/s
15
15
0.5 m/s
10
10
Nat. Conv.
5
60
70
80
90
100
110
0
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 0.6 V, VI = 12 V. See Thermal Consideration section.
Output Current Derating, VO = 1.8 V
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
60
70
100
110
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 1.0 V, VI = 12 V. See Thermal Consideration section.
[A]
[A]
30
3.0 m/s
2.0 m/s
20
60
70
80
90
100
110
Nat. Conv.
5
0
50
0.5 m/s
10
Nat. Conv.
5
1.0 m/s
15
0.5 m/s
10
2.0 m/s
20
1.0 m/s
15
3.0 m/s
25
SC
ON
T
25
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 1.8 V, VI = 12 V. See Thermal Consideration section.
50
60
70
80
90
100
110
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 3.3 V, VI = 12 V. See Thermal Consideration section.
Current Limit Characteristics, VO = 1.0 V
Current Limit Characteristics, VO = 3.3 V
[V]
[V]
1,2
4,0
1,0
3,0
4.5 V
0,6
5.0 V
DI
0,8
VI = 5.0, 12, 14 V
0,4
VI = 4.5 V
25
27
29
31
14 V
33
35 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V.
Note: Output enters hiccup mode at current limit.
4.5 V
5.0 V
2,0
12 V
0,2
0,0
90
Output Current Derating, VO = 3.3 V
30
0
80
IN
0
5
3.0 m/s
UE
D
Output Current Derating, VO = 0.6 V
12 V
VI = 12, 14 V
VI = 4.5, 5.0 V
14 V
1,0
0,0
25
27
29
31
33
35 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V.
Note: Output enters hiccup mode at current limit.
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date 12/21/2015 Ϳ page 10 of 32
TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)
Output Ripple vs. Input Voltage
Output Ripple vs. Frequency
[mVpk-pk]
150
60
120
50
0.6 V
40
1.0 V
30
1.8 V
20
3.3 V
90
60
30
10
0
5
7
9
11
0
[V]
13
UE
D
[mVpk-pk]
70
200
300
400
500
600
0.6 V
1.0 V
1.8 V
3.3 V
[kHz]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 µF/10 mΩ,
IO = 25 A. Default configuration except changed frequency.
Output Ripple vs. External Capacitance
Load regulation, VO = 1.0 V
IN
Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 µF/10 mΩ, IO = 25 A
[mV]
[V]
70
SC
ON
T
1,010
60
50
0.6V
40
1.0 V
30
1.8 V
20
3.3 V
10
0
0
1
2
3
4
5 [mF]
4.5 V
5.0 V
1,000
12 V
14 V
0,995
0,990
0
5
10
15
20
25 [A]
Load regulation at Vo = 1.0 V, TP1 = +25 °C, CO = 470 µF/10 mΩ
DI
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V. IO = 25 A.
Parallel coupling of capacitors with 470 µF/10 mΩ
1,005
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 11 of 32
TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
Top trace: output voltage (0.5 V/div.).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (20 ms/div.).
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
DI
Start-up by enabling CTRL signal at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
Top trace: output voltage (0.5 V/div.).
Bottom trace: input voltage (5 V/div.).
Time scale: (2 ms/div.).
Shut-down by CTRL signal
SC
ON
T
Start-up by CTRL signal
Top trace: output voltage (0.5 V/div.).
Bottom trace: input voltage (5 V/div.).
Time scale: (20 ms/div.).
IN
Start-up enabled by connecting VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
Shut-down by input source
UE
D
Start-up by input source
cui.com
Top trace: output voltage (0.5 V/div).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (2 ms/div.).
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 12 of 32
PRODUCT ELECTRICAL SPECIFICATION, VERTICAL
TP1 = -30 to +95 °C, VI = 4.5 to 14 V, VI> VO + 1.0 V
Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specied under conditions.
External CIN = 470 NjF/10 mƻ, COUT = 470 NjF/10 mƻ. See Operating Information section for selection of capacitor types.
Sense pins are connected to the output pins.
conditions/description
input voltage rise time (VI)
monotonic
min
output voltage without
pin-strap (VO)
see note 17
output voltage set-point
resolution (VO)
including line, load, temp see note 14
current sharing operation see note 15
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
load regulation (VO)
IO = 0~100%
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
output ripple & noise (Voac)
CO= 470 NjF (minimum external
capacitance) see note 11
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
SC
ON
T
line regulation (VO)
VO
VO
VO
VO
output current (IO)
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
0.54
3.63
V
%FS
-1
1
%
-2
2
%
47
ƻ
2
2
2
3
mV
mV
mV
mV
2
2
2
3
mV
mV
mV
mV
20
30
40
60
mVp-p
mVp-p
mVp-p
mVp-p
0
20
1.61
2.46
4.17
7.35
27
A
A
A
A
A
37.5
A
RMS, hiccup mode,
see note 3
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
8
6
5
4
A
A
A
A
50% of max IO
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
83.6
89
92.8
95.1
%
%
%
%
max IO
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
77.4
84.6
90
93.5
%
%
%
%
4.37
4.54
5.01
5.77
W
W
W
W
0.56
0.57
0.67
0.92
W
W
W
W
efciency (dž)
DI
V/ms
3.3
V
V
V
V
current limit threshold (Ilim)
short circuit current(ISC)
2.4
±0.025
internal resistance +S/-S to
VOUT/GND (VO)
static input current at max IO
(IS)
units
0.60
IN
output voltage accuracy (VO)
max
1.2
output voltage adjustment
range (VO)
output voltage adjustment
including margining (VO)
typ
UE
D
parameter
power dissipation at max IO (Pd)
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
input idling power (no load)(Pli)
default conguration:
continues conduction
mode, CCM
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
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date 12/21/2015 Ϳ page 13 of 32
PRODUCT ELECTRICAL SPECIFICATION, VERTICAL (CONTINUED)
parameter
input standby power (PCTRL)
conditions/description
turned off with CTRL-pin
min
default conguration:
monitoring enabled,
precise timing enabled
internal output capacitance (Co)
see note 9
ESR range of capacitors
(per single capacitor) (COUT)
see note 9
load transient peak voltage
deviation (L to H/H to L) load
step 25-75-25% of max IO(Vtr1)
default conguration
di/dt = 2 A/Njs CO = 470
NjF (minimum external
capacitance)
see note 12
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
load transient recovery time
note 5 (L to H/H to L) load step
25-75-25% of max IO(ttr1)
default conguration
di/dt = 2 A/Njs CO = 470
NjF (minimum external
capacitance)
see note 12
VO
VO
VO
VO
=
=
=
=
0.6
1.0
1.8
3.3
V
V
V
V
switching frequency (fs)
switching frequency range (fs)
PMBus congurable
switching frequency set-point
accuracy (fs)
SC
ON
T
control circuit PWM duty cycle
minimum sync pulse width
input clock frequency drift
tolerance
external clock source
DI
power good, PG, see note 2
delay
fault response
see note 3
PG threshold
PG hysteresis
PG delay
PG delay range
PMBus congurable
cui.com
mV
mV
mV
mV
60
65
115
130
Njs
Njs
Njs
Njs
320
kHz
200-640
kHz
5
95
150
%
%
ns
-13
13
%
3.85
V
3.85-14
V
-150
150
0.35
mV
V
0-10.15
V
2.5
Njs
automatic restart, 70 ms
16
PMBus congurable
PMBus congurable
115
122
143
174
5
see note 3
IOVP hysteresis
IOVP hysteresis range
F
-5
PMBus congurable
set point accuracy
input over voltage protection,
IOVP
200
mƻ
IOVP threshold
IOVP threshold range
F
30
delay
fault response
70
5
UVLO hysteresis
UVLO hysteresis range
mW
F
PMBus congurable
set point accuracy
input under voltage lockout,
UVLO
170
15,000
UVLO threshold
UVLO threshold range
units
300
IN
total external output
capacitance (COUT)
max
UE
D
internal input capacitance (Ci)
typ
V
4.2-16
-150
V
150
mV
1
V
0-11.8
V
2.5
Njs
automatic restart, 70 ms
90
%Vo
5
%Vo
direct after DLC
ms
0-500
s
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 14 of 32
PRODUCT ELECTRICAL SPECIFICATION, VERTICAL (CONTINUED)
parameter
conditions/description
min
UVP threshold
UVP threshold range
PMBus congurable
UVP hysteresis
OVP threshold
OVP threshold range
PMBus congurable
UVP/OVP response time
UVP/OVP
response time range
PMBus congurable
fault response
see note 3
OCP threshold
OCP threshold range
PMBus congurable
protection delay
see note 4
protection delay range
PMBus congurable
fault response
see note 3
OTP threshold
over temperature protection,
OTP at P2 see note 8
OTP threshold range
OTP hysteresis
OTP hysteresis range
fault response
PMBus congurable
logic input high threshold (VIH)
logic input low sink current(IIL)
%Vo
0-100
%Vo
5
%Vo
115
%Vo
100-115
%Vo
25
Njs
5-60
Njs
A
A
32
TSW
1-32
TSW
120
-40
see note 3
SYNC, SA0, SA1, SCL, SDA, DDC, CTRL, VSET
32
0-32
automatic restart, 70 ms
PMBus congurable
SC
ON
T
logic input low threshold(VIL)
logic output low sink current
(IOL)
°C
125
°C
25
°C
0-165
°C
automatic restart, 240 ms
0.8
V
0.6
mA
0.4
V
2
V
CTRL
logic output low signal level
(VOL)
logic output high signal level
(VOH)
units
automatic restart, 70 ms
IN
over current protection, OCP
max
85
UE
D
output voltage over/under
voltage protection, OVP/UVP
typ
2.25
V
SYNC, SCL, SDA, SALERT, DDC, PG
logic output high source current
(IOH)
4
mA
2
mA
setup time, SMBus(tSET)
see note 1
300
hold time, SMBus(thold)
see note 1
250
ns
bus free time, SMBus(tfree)
see note 1
2
ms
internal capacitance on logic
pins (CP)
DI
initialization time
output voltage delay time see
note 6
output voltage ramp time
see note 13
ns
10
pF
see note 10
40
ms
delay duration
see note 16
10
ms
delay duration range
PMBus congurable
5-500,000
ms
delay accuracy turn-on
-0.25/+4
ms
delay accuracy turn-off
-0.25/+4
ms
ramp duration
ramp duration range
PMBus congurable
ramp time accuracy
current sharing
operation
cui.com
10
ms
0-200
ms
100
Njs
20
%
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 15 of 32
PRODUCT ELECTRICAL SPECIFICATION, VERTICAL (CONTINUED)
parameter
conditions/description
VTRK input bias current
VVTRK = 5.5 V
VTRK regulation accuracy
(VO - VVTRK)
current difference between
products in a current
sharing group
100% tracking, see note 7
100% Tracking
current sharing operation 100% Tracking
units
200
NjA
100
mV
±100
mV
-1
1
%
-2
2
%
Max 2 x READ_IOUT monitoring
accuracy
steady state operation
ramp-up
2
A
7
READ_VIN vs VI
READ_VOUT vs VO
3
%
1
%
IO = 0-20 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 1.0 V
±1.7
A
READ_IOUT vs IO
IO = 0-20 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 0.6-3.3 V
±3
A
IN
READ_IOUT vs IO
1: See section I2C/SMBus Setup and Hold Times – Denitions.
2: Monitorable over PMBus Interface.
3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart.
4: Tsw is the switching period.
5: Within +/-3% of VO
6: See section Soft-start Power Up.
7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth.
8: See section Over Temperature Protection (OTP).
9: See section External Capacitors.
10: See section Initialization Procedure.
11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.
12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.
13: Time for reaching 100% of nominal Vout.
14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.
15: Accuracy here means deviation from ideal output voltage level given by congured droop and actual load. Includes line, load and temperature variations.
16: For current sharing the Output Voltage Delay Time must be recongured to minimum 15 ms.
17: For steady state operation above 1.05 x 3.3 V, please contact your local CUI sales representative.
DI
SC
ON
T
Notes:
max
-100
current sharing operation 2 phases, 100% tracking
VO = 1.0 V, 10 ms ramp
number of products in a current
sharing group
monitoring accuracy
typ
110
UE
D
VTRK tracking ramp accuracy
(VO - VVTRK)
min
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 16 of 32
TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)
Power Dissipation vs. Output Current, VI = 5 V
[%]
[W]
100
6
5
95
4
90
0.6 V
1.0 V
85
80
75
3
0
5
10
15
20
1.8 V
2
3.3 V
1
0
25 [A]
UE
D
Efficiency vs. Output Current, VI = 5 V
0
10
15
20
1.0 V
1.8 V
3.3 V
25 [A]
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
IN
Efficiency vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
Efficiency vs. Output Current, VI = 12 V
Power Dissipation vs. Output Current, VI = 12 V
[%]
[W]
100
6
5
SC
ON
T
95
4
90
0.6 V
80
0
5
10
15
20
0.6 V
3
1.0 V
85
75
5
0.6 V
1.0 V
1.8 V
2
1.8 V
3.3 V
1
3.3 V
0
25 [A]
0
5
10
15
20
25 [A]
Efficiency vs. load current and output voltage at
TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.
Efficiency vs. Output Current and
Switching Frequency
Power Dissipation vs. Output Current and
Switching frequency
[%]
[W]
95
6
5
90
DI
200
kHz
85
200
kHz
4
320
kHz
3
320
kHz
80
480
kHz
2
480
kHz
75
640
kHz
1
640
kHz
70
0
5
10
15
20
Efficiency vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ.
Default configuration except changed frequency
0
25 [A]
0
5
10
15
20
25 [A]
Dissipated power vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ.
Default configuration except changed frequency
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 17 of 32
TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)
[mV]
350
Load Transient vs. External Capacitance, VO = 3.3 V
Universal PID,
No NLR
280
[mV]
350
DLC,
No NLR
280
210
Universal PID,
Default NLR
210
140
DLC,
Default NLR
140
Universal PID,
Opt. NLR
70
70
DLC,
Opt. NLR
0
0
1
2
3
4
0
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step (6.25-18.75-6.25 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
A µs
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/
Universal PID,
No NLR
UE
D
Load Transient vs. External Capacitance, VO = 1.0 V
DLC,
No NLR
Universal PID,
Default NLR
DLC,
Default NLR
Universal PID,
Opt. NLR
DLC,
Opt. NLR
0
[mV]
350
SC
ON
T
DLC,
No NLR
210
Universal PID,
Default NLR
140
DLC,
Default NLR
Universal PID,
Opt. NLR
70
DLC,
Opt. NLR
300
400
500
3
4
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step (6.25-18.75-6.25 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/µs
Universal PID,
No NLR
280
200
2
IN
Load transient vs. Switch Frequency
0
1
600 [kHz]
Load transient peak voltage deviation vs. frequency.
Step-change (6.25-18.75-6.25 A).
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ
DI
Note: For Universal PID, see section Dynamic Loop Compensation (DLC).
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 18 of 32
TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)
Output Current Derating, VO = 1.0 V
[A]
[A]
30
30
3.0 m/s
25
2.0 m/s
20
20
1.0 m/s
15
15
0.5 m/s
10
10
Nat. Conv.
5
50
60
70
80
90
100
110
5
0
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 0.6 V, VI = 12 V. See Thermal Consideration section.
Output Current Derating, VO = 1.8 V
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
50
60
[A]
90
100
110
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 1.0 V, VI = 12 V. See Thermal Consideration section.
[A]
30
3.0 m/s
2.0 m/s
20
1.0 m/s
15
0.5 m/s
10
2.0 m/s
20
1.0 m/s
15
3.0 m/s
25
SC
ON
T
25
Nat. Conv.
0.5 m/s
10
Nat. Conv.
5
5
30
40
50
60
70
80
90
0
100 110 120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 1.8 V, VI = 12 V. See Thermal Consideration section.
30
40
50
60
70
80
90
100 110 120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 3.3 V, VI = 12 V. See Thermal Consideration section.
Current Limit Characteristics, VO = 1.0 V
Current Limit Characteristics, VO = 3.3 V
[V]
[V]
1,2
4,0
1,0
3,0
4.5 V
0,6
5.0 V
DI
0,8
VI = 5.0, 12, 14 V
0,4
VI = 4.5 V
25
27
29
31
14 V
33
35 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V.
Note: Output enters hiccup mode at current limit.
4.5 V
5.0 V
2,0
12 V
0,2
0,0
80
Output Current Derating, VO = 3.3 V
30
0
70
IN
0
25
UE
D
Output Current Derating, VO = 0.6 V
12 V
VI = 12, 14 V
VI = 4.5, 5.0 V
14 V
1,0
0,0
25
27
29
31
33
35 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V.
Note: Output enters hiccup mode at current limit.
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 19 of 32
TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)
Output Ripple vs. Input Voltage
Output Ripple vs. Frequency
[mVpk-pk]
50
100
40
80
0.6 V
30
60
1.0 V
1.8 V
20
40
3.3 V
10
0
20
5
7
9
11
0
[V]
13
UE
D
[mVpk-pk]
200
300
400
500
600
0.6 V
1.0 V
1.8 V
3.3 V
[kHz]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 µF/10 mΩ,
IO = 25 A. Default configuration except changed frequency.
Output Ripple vs. External Capacitance
Load regulation, VO = 1.0 V
IN
Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 µF/10 mΩ, IO = 25 A.
[V]
[mV]
50
SC
ON
T
1,010
40
0.6V
30
1.0 V
1.8 V
20
3.3 V
10
0
0
1
2
3
4
5 [mF]
4.5 V
5.0 V
1,000
12 V
14 V
0,995
0,990
0
5
10
15
20
25 [A]
Load regulation at Vo=1.0 V, TP1 = +25 °C, CO = 470 µF/10 mΩ
DI
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V. IO = 25 A.
Parallel coupling of capacitors with 470 µF/10 mΩ
1,005
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 20 of 32
TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
Top trace: output voltage (0.5 V/div.).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (20 ms/div.).
Shut-down enabled by disconnecting VI Top trace: output voltage (0.5 V/div).
at:
Bottom trace: CTRL signal (2 V/div.).
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
Time scale: (2 ms/div.).
CO = 470 µF/10 mΩ, IO = 25 A
DI
Start-up by enabling CTRL signal at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
Top trace: output voltage (0.5 V/div).
Bottom trace: input voltage (5 V/div.).
Time scale: (2 ms/div.).
Shut-down by CTRL signal
SC
ON
T
Start-up by CTRL signal
Top trace: output voltage (0.5 V/div.).
Bottom trace: input voltage (5 V/div.).
Time scale: (20 ms/div.).
IN
Start-up enabled by connecting VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 µF/10 mΩ, IO = 25 A
Shut-down by input source
UE
D
Start-up by input source
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 21 of 32
TYPICAL CHARACTERISTICS
Efficiency vs. Output Current and Switching frequency
Load transient vs. Switching frequency
[%]
[mV]
400
90
85
320
kHz
80
480
kHz
75
640
kHz
70
5
10
15
20
DLC,
Default NLR
Universal PID,
Opt. NLR
100
25 [A]
DLC,
Opt. NLR
200
400
500
600 [kHz]
Load transient peak voltage deviation vs. frequency.
Step-change (6.25-18.75-6.25 A).
TP1 = +25 °C, VI = 12 V, VO =1.0 V, CO = 470 µF/10 mΩ
Power Dissipation vs. Output Current and Switching frequency
[W]
Load Transient vs. Decoupling Capacitance, VO = 1.0 V
[mV]
400
6
200
kHz
4
320
kHz
3
2
480
kHz
1
640
kHz
0
5
10
15
20
Universal PID,
No NLR
DLC,
NLR
300
SC
ON
T
5
0
300
IN
Efficiency vs. load current and switching frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ
Default configuration except changed frequency
No
Universal PID,
Default NLR
200
0
0
DLC,
NLR
300
200
kHz
Universal PID,
No NLR
UE
D
95
Universal PID,
Default NLR
200
DLC,
Default NLR
Universal PID,
Opt. NLR
100
0
25 [A]
0
No
DLC,
NLR
1
2
3
4
Opt.
5 [mF]
Dissipated power vs. load current and switching frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ
Default configuration except changed frequency
Load transient peak voltage deviation vs. decoupling capacitance.
Step (6.25-18.75-6.25 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/µs
Output Ripple vs. Switching frequency
Load Transient vs. Decoupling Capacitance, VO = 3.3 V
[mVpk-pk]
[mV]
400
150
DI
120
0.6 V
90
1.0 V
1.8 V
60
3.3 V
Universal PID,
No NLR
DLC,
NLR
300
Universal PID,
Default NLR
200
DLC,
Default NLR
Universal PID,
Opt. NLR
100
30
0
0
200
300
400
500
600
[kHz]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 µF/10 mΩ,
IO = 25 A resistive load. Default configuration except changed frequency.
No
DLC,
NLR
0
1
2
3
4
Opt.
5 [mF]
Load transient peak voltage deviation vs. decoupling capacitance.
Step (6.25-18.75-6.25 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/µs
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 22 of 32
MECHANICAL DRAWING (HORIZONTAL, SURFACE MOUNT)
PIN
NAME
1A
VIN
2A
GND
3A
VOUT
4A
VTRK/PG
4B
PREF
5A
+S
5B
-S
6A
SA0
6B
DDC
7A
SCL
7B
SDA
VSET
SYNC
9A
SALRT
9B
CTRL
PLATING
Copper Alloy
Min
0.1 Njm Au
over
1~3 Njm Ni
Brass
Min
0.1 Njm Au
over
2 Njm Ni
DI
SC
ON
T
8A
8B
MATERIAL
IN
PIN
NUMBER
UE
D
units: mm [inches]
tolerance unless specied:
X.X ±0.50 [0.02]
X.XX ±0.25 [0.01]
(not applied on footprint or typical values)
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date 12/21/2015 Ϳ page 23 of 32
MECHANICAL DRAWING (HORIZONTAL, THROUGH HOLE MOUNT)
PIN
NAME
1A
VIN
2A
GND
3A
VOUT
4A
VTRK/PG
4B
PREF
5A
+S
5B
-S
6A
SA0
6B
DDC
7A
SCL
7B
SDA
VSET
SYNC
9A
SALRT
9B
CTRL
PLATING
Copper Alloy
Min
8~13 Njm
matte tin
over
2.5~5 Njm
Ni
Brass
Min
0.2 Njm Au
over
1.27 Njm Ni
DI
SC
ON
T
8A
8B
MATERIAL
IN
PIN
NUMBER
UE
D
units: mm [inches]
tolerance unless specied:
X.X ±0.50 [0.02]
X.XX ±0.25 [0.01]
(not applied on footprint or typical values)
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 24 of 32
MECHANICAL DRAWING (VERTICAL, THROUGH HOLE MOUNT)
PIN
NAME
1A
VIN
2A
GND
3A
VOUT
4A
+S
4B
-S
5A
VSET
5B
VTRK
6A
SALRT
6B
SDA
7A
SCL
7B
SA1
8A
SA0
8B
SYNC
PG
CTRL
10A
DDC
10B
PREF
PLATING
Min
0.1 Njm Au
over
1~3 Njm Ni
Copper Alloy
Min
0.1 Njm Au
over
1 Njm Ni
DI
SC
ON
T
9A
9B
MATERIAL
IN
PIN
NUMBER
UE
D
units: mm [inches]
tolerance unless specied:
X.X ±0.50 [0.02]
X.XX ±0.25 [0.01]
(not applied on footprint or typical values)
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
OPERATING INFORMATION
date 12/21/2015 Ϳ page 25 of 32
POWER CONVERSION AND MANAGEMENT
REQUIRED CONFIGURATIONS
Power Management Overview
The NDM2Z-25 module incorporates a wide range of power
management features. All power management functions
can be configured via the SMBus interface. The NDM2Z-25
can monitor and report many characteristics of the module
including input voltage, output voltage, output current and
internal temperature. Additionally, the NDM2Z-25 includes
circuit protection features that protect the module and load
from damage due to system faults. Monitoring parameters
can also be configured to provide alerts for specific
conditions. The ability of CUI modules to digitally control,
configure and monitor OS features provides significant
benefits over traditional analog POL products.
IN
NDM2Z-25 Module Pins
Each NDM2Z-25 module should have a resistor placed
between VSET and PREF to set the output voltage of the
module. The maximum output voltage which can be
congured by PMBus commands can never exceed 110% of
the voltage set by the VSET pin. The SMBus address of each
module is set by either pin-strap conguration or resistor
value associated with the SA0 and SA1 pins. More information regarding setting the SMBus address for a module can
be found in the section titled “SMBus”.
Power Conversion Overview
The NDM2Z-25 module has several features to enable high
power conversion efficiency. Non-linear loop response (NLR)
improves the response time and reduces the output
deviation as a result of load transients. The incorporation
of DFM enhances the performance of CUI modules over that
available from conventional analog POL offerings.
UE
D
The NDM2Z-25 modules are available in different
congurations; not all pins and functions are supported by
each conguration. This document describes all pins and
functions.
The Novum Z Products PMBus Commands application note
denes the available PMBus™ commands.
SC
ON
T
PCB Layout
Good performance of any point of load voltage regulator
module can only be achieved with careful PCB layout
considerations. Ground planes or very wide traces should
be used for power and ground routing. Input capacitors
should be placed close to the input voltage pins of the
module and output capacitors should be placed close to the
load. The module should also be placed as close as possible
to the load.
INPUT AND OUTPUT CAPACITORS
Input Capacitors
Input capacitors are recommended to be used with the
NDM2Z-25 module in order to minimize input voltage ripple.
A 330 NjF POSCAP or electrolytic and 3x 22 NjF ceramic
capacitors should be placed as close as possible to the input
pins of the module. Additional input capacitors may be
used if less input voltage ripple is desired.
DI
Output Capacitors
Output capacitors are recommended to be used with the
NDM2Z-25 module in order to improve transient response
and minimize output voltage ripple. A 330 NjF POSCAP or
electrolytic and 3x 22 NjF ceramic capacitors should be
placed as close as possible to the load. Additional output
capacitors may be used to further improve the output
voltage characteristics.
CONFIGURING THE MODULE
Pin Settings
Pins SA0 and SA1 are used to set the SMBus address of the
NDM2Z-25 module. Details of this feature are discussed in
the section titled “SMBus”. Pin SYNC is used to synchronize the switching clock of the module to an external clock
source. More information regarding synchronization can be
found in the section titled “SWITCHING FREQUENCY AND
SYNCHRONIZATION”.
Pin VSET is used to configure the output voltage of the
module. The voltage established by the VSET pin limits the
maximum output voltage that can be configured by SMBus
commands.
The SA0, SA1, SYNC and VSET pin configurations are read
by the module when power is applied or whenever a SMBus
RESTORE command is issued.
The CTRL pin is active high and can be used to enable the
module. Internal connections on the module will drive the
CTRL pin high if it is left floating.
Pins +S and -S are used for remote voltage sensing of the
output voltage.
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
date 12/21/2015 Ϳ page 26 of 32
Unused Pins
Table 1 describes the required or allowed connections for unused pins on the NDM2Z-25 module.
Table 1: Unused Pins
VSET
Tie to PREF with 133 kƻ resistor, see VOUT_COMMAND PMBus command
Float
DDC, SCL, SDA, SALRT
Pulled high with resistor, see "RECOMMENDED OPERATIN CONDITIONS"
UE
D
VTRK, SA0, SA1, SYNC, CTRL, +S, -S
Conguration of Parameters Using the SMBus
The NDM2Z-25 module is supplied with default settings. All module settings (except for module SMBus address,
congured by pins SA0 and SA1) can be re-congured via the SMBus interface. The output voltage can not be set to
greater than 110% of the voltage set by the VSET pin.
START-UP PROCEDURE
Table 2: NDM2Z-25 Start-up sequence
IN
Start-up Sequence
The NDM2Z-25 module follows an internal start-up procedure after power is applied to pin VIN. Table 2 describes the
start-up sequence. If the module is to be synchronized to an external clock source, the clock frequency must be stable
prior to asserting CTRL (or applying input voltage to the module if CTRL is not used). Once this process is completed, the
module is ready to accept assertion of CTRL and commands via the SMBus interface.
STEP NAME
DESCRIPTION
1
Power applied or
RESTORE_FACTORY
Input voltage is applied to NDM2Z-25 module pin VIN or RESTORE_FACTORY
PMBus command issued
Factory conguration
settings
Module loads factory conguration settings. This step is also performed after
using PMBus commands to restore the factory conguration le.
SA0, SA1, SYNC and
VSET pin settings
Module loads values congured by the SA0, SA1, SYNC and VSET pins.
Default conguration
settings
Module loads default conguration settings. This data over-rides pin setting
data, except for maximum limit for VOUT_COMMAND. This step also performed
after using PMBus commands to restore the default conguration le.
User conguration
settings
Module loads user conguration settings. This data over-rides pin setting and
default conguration data, except for maximum limit for VOUT_COMMAND. This
step also performed after using PMBus commands to restore the user
conguration le.
Module ready
The module is ready to accept a CTRL signal.
---
Pre-ramp delay
The module requires approximately 5 ms following a CTRL signal and prior to
ramping its output. Additional pre-ramp delay may be congured using PMBus
commands.
Approximately
5 ms
2
3
4
5
6
7
SC
ON
T
STEP
DI
Soft-start Delay Ramp Times
Once CTRL is asserted the NDM2Z-25 module requires a
pre-ramp delay time before the output voltage may be
allowed to start the ramp-up process. After the delay period
has expired, the output will begin to ramp towards the
target voltage according to the pre-congured soft-start
ramp time that has been set. It is recommended to set the
soft-start ramp time to a value greater than 500 Njs in order
to prevent fault conditions due to excessive inrush current.
Soft start delay and ramp times may be set using PMBus
commands.
Output Pre-Bias
An output pre-bias condition exists when a non-zero
TIME DURATION
Depends on input
supply ramp time
Approximately 10
ms (module will
ignore a CTRL
signal and PMBus
commands during
this period)
voltage is present on the NDM2Z-25 module output before
the module output voltage is enabled. If a pre-bias voltage
exists, the output voltage of the module is set to match the
existing pre-bias voltage. The output voltage is then ramped
to the final regulation value in the specified ramp time.
The pre-bias voltage can be higher or lower than the final
output voltage. Higher pre-bias output voltages will cause
energy to be pumped into the input voltage rail powering
the module. This condition could cause the module to report
an error condition if the input voltage exceeds the input
over voltage lock out threshold. The module will report an
error condition if the pre-bias output voltage exceeds the
output over voltage protection threshold.
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
RESISTOR (k)
VOUT (V)
RESISTOR (k)
VOUT (V)
10.0
0.60
38.3
1.30
11.0
0.65
42.2
1.40
12.1
0.70
46.4
1.50
13.3
0.75
51.1
1.60
14.7
0.80
56.2
1.70
16.2
0.85
61.9
1.80
17.8
0.90
68.1
1.90
19.6
0.95
75.0
2.00
21.5
1.00
82.5
2.10
23.7
1.05
90.9
2.20
26.1
1.10
100.0
2.30
28.7
1.15
110.0
2.50
31.6
1.20
121.0
3.00
34.8
1.25
133.0
3.30
SMBus Setting Method
The voltage present at the VOUT pin of the NDM2Z-25
module can be reconfigured using PMBus commands. A
voltage level reconfigured by a PMBus command overrides the voltage set by the VSET pin, but cannot be set to
greater than 110% of the voltage set by the VSET pin.
SC
ON
T
IN
Soft-stop Delay and Ramp Times
After CTRL is de-asserted the NDM2Z-25 module utilizes
a pre-ramp delay time before the output starts the rampdown process. After the delay period has expired, the
output will begin to ramp towards ground according to the
pre-congured soft-stop ramp time that has been set. It is
recommended to set the soft-start ramp down to a value
greater than 500 Njs in order to prevent voltage spikes in
the module input supply rail due the energy stored in the
output capacitors. There will be a delay after the output
voltage has reached ground potential and then the output of
the module will be set to high impedance. Once the output
of the module is high impedance the output voltage may
oat to a non-zero value if another source or leakage path
is connected to the output. The soft-stop delay and ramp
times may be congured via PMBus commands.
PMBus commands can be used to set the output of the
NDM2Z-25 module to high impedance as soon as the output
voltage drops below a selectable threshold.
Table 4: Resistor VOUT voltage settings
UE
D
Power Good
The PG pin on the NDM2Z-25 module will assert if the
output of the module is within tolerance of the target
voltage and no fault conditions exist. A PG delay period
is dened as the time from when all conditions within the
module for asserting PG are met to when PG is actually
asserted. By default, PG delay is set equal to the soft-start
ramp time setting. The tolerance, polarity and delay of PG
may be congured via PMBus commands.
date 12/21/2015 Ϳ page 27 of 32
OUTPUT VOLTAGE SETTING
Pin-Strap and Resistor Setting Methods
Using the pin-strap method, the voltage on the VOUT pin
of the NDM2Z-25 module can be set to one of three default
voltages as shown in Table 3. Table 4 lists the available
output voltage settings with a resistor connected between
VSET and PREF.
Table 3: Pin-strap VOUT voltage settings
VOUT (V)
LOW (< 0.8 V)
0.6
OPEN (N/C)
1.2
HIGH (> 2.0 V)
2.5
DI
VSET
Voltage Tracking
The NDM2Z-25 module includes a feature that allows the
output ramp voltage to track the ramp of a reference
voltage which is applied to the VTRK pin. The voltage ramp
tracking capability can be configured so that member
modules track at either 50% or 100% of the reference
voltage ramp rate. In addition, a member module can be
configured so that the termination voltage either tracks
or ignores perturbations on the reference voltage once it
has stabilized. Tracking at 50% and tracking final voltage
perturbations is intended for DDR memory applications. All
other applications which required voltage tracking should
use 100% tracking and ignore final voltage perturbations.
The reference voltage for tracking must have a target voltage which is equal to or greater than the target voltage of
the member modules. The turn-on delay of the reference
voltage must be at least 10 ms greater than that set for the
member modules. In voltage tracking mode, the turn-off
delay of the member modules establishes the time duration
which the member modules will track the reference voltage
after CTRL is de-asserted. The turn-off delay of the member
modules must be at least 5 ms greater than the sum of the
turn-off delay and fall time of the reference voltage.
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Voltage Margining
The NDM2Z-25 module offers a means to vary the output
voltage higher or lower relative to the nominal voltage
setting. The rate of change of the output voltage during
voltage margining is also configurable. The margin feature
can be reconfigured through PMBus commands.
SWITCHING FREQUENCY AND SYNCHRONIZATION
Non-Linear Response (NLR) Settings
The NDM2Z-25 module incorporates a non-linear response
(NLR) loop that decreases the response time and the output
voltage deviation in the event of a sudden output load
current step. This implementation results in a higher
equivalent loop bandwidth than what would be possible
using a traditional linear loop. PMBus commands can be
used to congure the NLR response of the module.
Adaptive Diode Emulation
Please contact CUI technical support regarding the
implementation of adaptive diode emulation.
Adaptive Frequency Control
The NDM2Z-25 module includes adaptive frequency control
to improve conversion efciency. Adaptive frequency control
is not available for current sharing groups and is not
allowed when the module is placed in auto-detect mode
and a clock source is present on the SYNC pin.
Adaptive frequency control is only available while the
module is operating within adaptive diode emulation mode.
Adaptive frequency control can be enabled and disabled
with PMBus commands.
SC
ON
T
IN
Switching Frequency
The switching frequency of the NDM2Z-25 module can
be recongured by PMBus commands or controlled by an
external clock source connected to the SYNC pin. If the
module is operated at a switching frequency of other than
the factory default setting, the compensation may need to
be adjusted and the ripple, noise, transient response and
efciency may be affected.
loop every time the output voltage ramps to the regulated
level. PMBus commands can be used to congure when the
module re-compensates the loop.
The user also has the option to manually congure the loop
compensation.
UE
D
Current sharing modules which are also configured to track
a voltage must have all of the VTRK pins tied together.
All of the CTRL pins of the member modules must also be
connected together and driven by a common source. The
rise and fall times of the member modules should be set
between 5 ms and 10 ms to ensure current sharing while
ramping. PMBus commands can be used to configure the
voltage tracking features.
date 12/21/2015 Ϳ page 28 of 32
MULTI-MODULE CONFIGURATION
Output Sequencing
Multiple device sequencing of NDM2Z-25 modules may
be achieved by issuing PMBus commands to assign the
preceding device in the sequencing chain as well as the
device that will follow in the sequencing chain. The CTRL
pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of
the group. CTRL must be driven low to initiate a sequenced
turnoff of the group.
DI
SYNC Auto Detect
The NDM2Z-25 module will automatically check for a clock
signal on the SYNC pin after CTRL is asserted (or applying
input voltage to the module if CTRL is not used). If a clock
signal is present, the module will synchronize to the rising
edge of the external clock. The external clock signal must
be stable and conform to the “RECOMMENDED OPERATING
CONDITIONS” parameters when CTRL is asserted (or
applying input voltage to the module if CTRL is not used).
In the event of a loss of the external clock signal, the
output voltage of the module may show transient overshoot
or undershoot and the module will automatically congure
to switch at a frequency close to the previous incoming
frequency. If no incoming clock signal is present when CTRL
is asserted (or applying input voltage to the module if CTRL
is not used), the module will switch at the frequency set by
the conguration le.
CONTROL LOOP
Adaptive Loop Compensation
The NDM2Z-25 module employs automatic adaptive loop
compensation to increase the performance and stability of
the module over a wide range of conditions. The default
setting congures the module to re-compensate the control
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
POWER FAULT MANAGEMENT
Input Under and Over Voltage Lockout
Input under voltage lockout (UVLO) and input over voltage
lockout (OVLO) indicate faults for the NDM2Z-25 module
when the input voltage falls outside of preset thresholds.
The default response due to an input voltage fault is
an immediate shutdown of the module. The module will
continuously check for the presence of the fault condition.
Once the fault condition is no longer present, the module
will be re-enabled. PMBus commands can be used to
congure the thresholds and response of the module to the
fault condition.
SC
ON
T
IN
Active Current Sharing
Paralleling multiple NDM2Z-25 modules can be used to
increase the output current capability of a single power rail.
By connecting the DDC of each module together and
conguring the modules as a current sharing rail, the units
will share the load current.
Upon system start-up, the module with the lowest member
position as selected with the PMBus command is dened as
the reference module; the remaining modules are members.
The reference module broadcasts the current over the DDC.
The output voltages of the member modules are controlled
by the reference current information to balance the current
loading of each module in the system.
A current sharing rail can be part of a system sequencing
group. For fault conguration, the current share rail is
congured in a quasi-redundant mode. In this mode, when
a member module fails the remaining members will
continue to operate and attempt to maintain regulation. If
fault spreading is enabled, the current share rail failure is
broadcast only after the entire current share rail fails.
Members of the current sharing rail can be disabled to
improve system power conversion efciency. If the
reference module fails or is disabled then the remaining
module with the lowest member position will become the
new reference module. A change to the number of members
of a current sharing rail will cause automatic phase
re-distribution of the members of that current sharing rail.
If the members of a current sharing rail are forced to shut
down due to an observed fault, all members of the rail will
attempt to re-start simultaneously after the fault has
cleared. PMBus commands can be used to congure current
sharing.
addresses; phase offset = device address x 45°.
For example:
• A module address of 0x00 or 0x20 would congure 0° of
phase offset
• A module address of 0x01 or 0x21 would congure 45° of
phase offset
• A module address of 0x02 or 0x22 would congure 90° of
phase offset
The phase offset of each module may also be set via the
PMBus.
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Fault Spreading
NDM2Z-25 modules can be configured to broadcast a fault
event over the DDC (Group Communication Bus) to the
other modules in the group. When a nondestructive fault
occurs and the module is configured to shut down on a
fault, the module will shut down and broadcast the fault
event over the DDC. The other modules on the DDC will
shut down together if configured to do so, and will attempt
to re-start in their prescribed order if configured to do so.
PMBus commands can be used to confi gure the
transmission and reception of faults.
date 12/21/2015 Ϳ page 29 of 32
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Output Under and Over Voltage Protection
The NDM2Z-25 module employs an output voltage
protection circuit that can be used to protect load circuitry
from being subjected to voltages outside of prescribed
limits. A hardware comparator is used to compare the
voltage seen at the +S pin to voltage thresholds. If the +S
pin voltage is outside of these thresholds the PG pin will
de-assert and the module will indicate a fault condition.
Phase Spreading
When multiple NDM2Z-25 modules share a common DC
input supply, it may be desirable to adjust the clock phase
offset of each module. In order to enable phase spreading,
all modules must be synchronized to the same switching
clock. For modules driven by a common synchronizing clock
the phase offset of each module is controlled by the module
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CUI Inc Ϳ SERIES: NDM2Z-25 Ϳ DESCRIPTION: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER
Table 5: Pin-strap SMBus Addressing
SA0
ADDRESS
HIGH
0x25
OPEN
0x24
LOW
0x23
Table 6: Single Resistor SMBus Addressing
RSA0 (k)
ADDRESS
IN
Output Over Current Protection
Output over current protection will protect the NDM2Z-25
module and load from damage if an overload condition is
imposed on the output. The module will indicate a fault
condition when the output current limit threshold is
exceeded. The default response from an output current fault
is an immediate shutdown of the module. The module will
continuously check for the presence of the fault condition,
and if the fault condition no longer exists the module will be
re-enabled. PMBus commands can be used to congure the
current limit threshold and the response of the module to
the fault condition.
SMBus interface, each device must have a unique address
so the host can distinguish between the devices. The
NDM2Z-25 module address can be set according to the
pin-strap options listed in Table 5; address values are
right-justied.
If additional module addresses are required, a resistor can
be connected to pin SA0 as shown in Table 6 to provide up
to 25 unique module addresses.
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The default response to an output voltage fault is to
immediately shut down. The module will continuously check
for the presence of the fault condition, when the fault
condition no longer exists the module will be re-enabled.
PMBus commands can be used to set the voltage
thresholds and congure the response of the module to the
fault condition. When operating from an external clock the
only allowed response to an output voltage fault is an
immediate shutdown.
date 12/21/2015 Ϳ page 30 of 32
SMBUS
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SMBus Communications
The NDM2Z-25 module provides a SMBus interface that
enables the user to congure the module operation as well
as monitor input and output parameters. The module can
be used with any standard 2-wire I2C host device, accepts
most standard PMBus commands, is compatible with SMBus
version 2.0 and includes an SALRT line to help mitigate
bandwidth limitations related to continuous fault
monitoring. It is recommended that CTRL be pulled low
while conguring the module with PMBus commands.
Pull-up resistors are required on the SMBus lines as
described in "RECOMMENDED OPERATING CONDITIONS".
SMBus Addresses
When communicating with multiple SMBus devices using the
ADDRESS
10.0
0x4B
34.8
0x58
11.0
0x4C
38.3
0x59
12.1
0x4D
42.2
0x5A
13.3
0x4E
46.4
0x5B
14.7
0x4F
51.1
0x5C
16.2
0x50
56.2
0x5D
17.8
0x51
61.9
0x5E
19.6
0x52
68.1
0x5F
21.5
0x53
75.0
0x60
23.7
0x54
82.5
0x61
26.1
0x55
90.9
0x62
28.7
0x56
100.0
0x63
31.6
0x57
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Thermal Overload Protection
The NDM2Z-25 module includes a thermal sensor that
measures the temperature of the module and indicates a
fault when the temperature exceeds a preset limit. The
default response from a temperature fault is an
immediate shutdown of the module. The module will
continuously check for the fault condition and once the fault
has cleared the module will be re-enabled. PMBus
commands can be used to congure the thermal
protection threshold and the response of the module to the
fault condition. Permanent damage to the module may
result if the thermal limit is set too high.
RSA0 (k)
When using only pin SA0 to set the SMBus address, pin SA1
should be tied to PREF.
If more than 25 unique module addresses are required or if
other SMBus address values are desired, pins SA0 and SA1
can be congured with a resistor to PREF as listed in
Table 7.
Using this method, the user can theoretically congure up
to 625 unique SMBus addresses. However, the SMBus is
inherently limited to 128 modules so attempting to
congure an address higher than 128 (0x80) will cause the
module address to repeat (i.e, attempting to congure a
module address of 129 (0x81) would result in a module
address of 1).
Therefore, the user should use index values 0-4 on pin SA1
and the full range of index values on pin SA0, which will
provide 125 module address combinations.
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Note that the SMBus address 0x4B is reserved for module
test and cannot be used in the system.
SINGLE WIRE COMMUNICATIONS
Digital-DC Bus
The DDC (Digital-DC Communication Bus) is used to
communicate between NDM2Z modules. This dedicated bus
provides the communication channel between modules for
features such as sequencing, fault spreading, and current
sharing. A pull-up resistor is required on the DDC as
dened in “RECOMMENDED OPERATING CONDITIONS”.
Table 7: Dual Resistor SMBus Addressing
12.1
13.3
14.7
10.0
0x00
0x19
0x32
0x4B
0x64
11.0
0x01
0x1A
0x33
0x4C
0x65
12.1
0x02
0x1B
0x34
0x4D
0x66
13.3
0x03
0x1C
0x35
0x4E
0x67
14.7
0x04
0x1D
0x36
0x4F
0x68
16.2
0x05
0x1E
0x37
0x50
0x69
17.8
0x06
0x1F
0x38
0x51
0x6A
19.6
0x07
0x20
0x39
0x52
0x6B
21.5
0x08
0x21
0x3A
0x53
0x6C
23.7
0x09
0x22
0x3B
0x54
0x6D
26.1
0x0A
0x23
0x3C
0x55
0x6E
28.7
0x0B
0x24
0x3D
0x56
0x6F
31.6
0x0C
0x25
0x3E
0x57
0x70
34.8
0x0D
0x26
0x3F
0x58
0x71
38.3
0x0E
0x27
0x40
0x59
0x72
0x0F
0x28
0x41
0x5A
0x73
46.4
0x10
0x29
0x42
0x5B
0x74
51.1
0x11
0x2A
0x43
0x5C
0x75
56.2
0x12
0x2B
0x44
0x5D
0x76
61.9
0x13
0x2C
0x45
0x5E
0x77
68.1
0x14
0x2D
0x46
0x5F
0x78
75.0
0x15
0x2E
0x47
0x60
0x79
82.5
0x16
0x2F
0x48
0x61
0x7A
90.9
0x17
0x30
0x49
0x62
0x7B
100.0
0x18
0x31
0x4A
0x63
0x7C
Snapshot™ Parameter Capture
The NDM2Z-25 module offers features that enable the user
to capture parametric data during normal operation or
following a fault. The Snapshot feature enables the user to
read status and parameter values via a block read transfer
through the SMBus. This can be done during normal
operation, although it should be noted that reading the 22
bytes will occupy the SMBus for up to 1400 Njs.
The SNAPSHOT_CONTROL command enables the user to
store the snapshot parameters to ash memory in
response to a pending fault as well as to read the stored
data from ash memory after a fault has occurred.
Automatic writes to ash memory following a fault are
triggered when any fault threshold level is exceeded,
provided that the specic response to that fault is
to shut down (writing to ash memory is not allowed if the
module is congured to re-try following the specic fault
condition). It should also be noted that the input voltage to
the module must be maintained during the time when the
module is writing the data to ash memory; a process that
requires between 700 Njs to 1400 Njs depending on whether
the data is set up for a block write. Undesirable results may
be observed if the input voltage to the module drops too
low during this process. In the event that the module
experiences a fault and power is lost, the user can extract
the last SNAPSHOT parameters stored during the fault
by using the SMBus to transfer data from ash memory to
RAM and then using the SMBus to read data from RAM.
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42.2
RSA1 (k)
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11.0
IN
10.0
date 12/21/2015 Ϳ page 31 of 32
RSA0 (k)
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Monitoring Via SMBus
A system controller can be used to monitor the NDM2Z-25
module system parameters through the SMBus. Fault
conditions can be detected by monitoring the SALRT pin,
which will be asserted when pre-congured fault conditions
occur. Modules can also be monitored for power conversion
parameters including but not limited to the following:
•
•
•
•
•
•
Input voltage
Output voltage
Output current
Module temperature
Switching frequency
Duty cycle
THERMAL CONSIDERATIONS
Mounting
Heat from the NDM2Z-25 module will be conducted through
the pins to the host board. Provisions must be made for the
host board to accommodate this additional heating.
Airow
Airow past the NDM2Z-25 module will assist in cooling
the module. Factors affecting the efciency of the cooling
include the rate, direction and temperature of the airow.
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date 12/21/2015 Ϳ page 32 of 32
REVISION HISTORY
date
1.0
09/28/2015
1.1
12/14/2015
1.2
12/21/2015
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rev.
DI
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IN
The revision history provided is for informational purposes only and is believed to be accurate.
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20050 SW 112th Ave.
Tualatin, OR 97062
800.275.4899
Fax 503.612.2383
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techsupport@cui.com
Novum and Architects of Modern Power are trademarks of CUI.
PMBus is a trademark of SMIF, Inc.
Auto-Control is a trademark of Powervation Ltd.
All other trademarks are the property of their respective owners.
CUI offers a two (2) year limited warranty. Complete warranty information is listed on our website.
CUI reserves the right to make changes to the product at any time without notice. Information provided by CUI is believed to be accurate and reliable. However, no responsibility is
assumed by CUI for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
CUI products are not authorized or warranted for use as critical components in equipment that requires an extremely high level of reliability. A critical component is any component of a
life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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