Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CYW88335
Single-Chip 5G Wi-Fi IEEE 802.11ac MAC/Baseband/Radio
with Integrated Bluetooth 4.1 for Automotive Applications
The Cypress CYW88335 single-chip device provides the highest level of integration for Automotive In-Vehicle Infotainment connectivity systems with integrated single-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth 4.1. In IEEE 802.11ac mode, the WLAN
operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 433.3 Mbps.
In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers,
and receive low-noise amplifiers. Optional external PAs, LNAs, and antenna diversity are also supported.
The CYW88335 offers an SDIO v3.0 interface for high speed 802.11ac connectivity. The Bluetooth host controller is interfaced over
a 4-wire high speed UART and includes PCM for audio.
The CYW88335 brings the latest mobile connectivity technology to automotive infotainment, telematics and rear seat entertainment.
Offering Automotive Grade 3 (–40°C to +85°C) temperature performance, the CYW88335 is tested to AECQ100 environmental stress
guidelines and manufactured in ISO9001 and TS16949 certified facilities.
The CYW88335 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which
ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external
radios (such as LTE cellular, GPS, and WiMAX) is provided via an external interface. As a result, enhanced overall quality for
simultaneous voice, video, and data transmission is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM88335
CYW88335
BCM88335L2CUBG
CYW88335L2CUBG
Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined on first use.
For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary.
Features
IEEE 802.11x Key Features
■
IEEE 802.11ac compliant.
■
Single-stream spatial multiplexing up to 433.3 Mbps data rate.
■
Supports 20, 40, and 80 MHz channels with optional SGI (256
QAM modulation).
■
Full IEEE 802.11a/b/g/n legacy compatibility with enhanced
performance.
■
TX and RX low-density parity check (LDPC) support for
improved range and power efficiency.
■
Supports RX space-time block coding (STBC)
■
Supports IEEE 802.11ac/n beamforming.
■
On-chip power amplifiers and low-noise amplifiers for both
bands.
■
Support for optional front-end modules (FEM) with external PAs
and LNAs
■
Shared Bluetooth and WLAN receive signal path eliminates the
need for an external power splitter while maintaining excellent
sensitivity for both Bluetooth and WLAN.
Cypress Semiconductor Corporation
Document Number: 002-15057 Rev. *B
•
■
Internal fractional nPLL allows support for a wide range of
reference clock frequencies
■
Supports IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other co-located wireless
technologies such as LTE, GPS, or WiMAX
■
Supports standard SDIO v3.0 (including DDR50 mode at
50 MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit), and
gSPI (48 MHz) host interfaces.
■
Backward compatible with SDIO v2.0 host interfaces.
■
■
198 Champion Court
Integrated ARMCR4™ processor with tightly coupled memory
for complete WLAN subsystem functionality, minimizing the
need to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field upgrade with
future features. On-chip memory includes 768 KB SRAM and
640 KB ROM.
OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as
future devices.
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 8, 2017
CYW88335
Bluetooth Key Features
General Features
■
Complies with Bluetooth Core Specification Version 4.1 for
automotive applications with provisions for supporting future
specifications.
■
Bluetooth Class 1 or Class 2 transmitter operation.
■
Supports extended synchronous connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■
Adaptive frequency hopping (AFH) for reducing radio
frequency interference.
■
Interface support, host controller interface (HCI) using a highspeed UART interface and PCM for audio data.
■
Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■
Automatic frequency detection for standard crystal and TCXO
values.
■
Supports low energy host wake-up for long term system sleep
capability.
■
Supports battery voltage range from 3.0V to 4.8V supplies with
internal switching regulator.
■
Programmable dynamic power management
■
OTP: 502 bytes of user-accessible memory
■
Nine GPIOs
■
Package options:
❐ 145 ball WLBGA (4.87 mm × 5.413 mm, 0.4 mm pitch)
■
Security:
™
™
❐ WPA and WPA2 (Personal) support for powerful encryption and authentication
❐ AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility
®
❐ Reference WLAN subsystem provides Cisco Compatible
Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0)
❐ Reference WLAN subsystem provides Wi-Fi Protected Setup
(WPS)
■
Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. Functional Block Diagram
VIO
WLAN
Host I/F
External
Coexistence I/F
VBAT
5 GHz WLAN TX
WL_REG_ON
5 GHz WLAN RX
SDIO*/SPI
FEM or
T/R
Switch
COEX
2.4 GHz WLAN TX
CLK_REQ
BT_REG_ON
UART
Bluetooth
Host I/F
CYW88335
2.4 GHz WLAN/BT RX
Bluetooth TX
FEM or
T/R
Switch
CBF
I2S
PCM
BT_DEV_WAKE
BT_HOST_WAKE
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://
community.cypress.com/).
Document Number: 002-15057 Rev. *B
Page 2 of 110
CYW88335
Contents
1. Overview ........................................................................ 4
1.1 Overview ............................................................... 4
1.2 Features ................................................................ 6
1.3 Standards Compliance .......................................... 6
1.4 Automotive Usage Model ...................................... 7
2. Power Supplies and Power Management ................... 8
2.1 Power Supply Topology ........................................ 8
2.2 PMU Features ....................................................... 8
2.3 WLAN Power Management ................................. 10
2.4 PMU Sequencing ................................................ 10
2.5 Power-Off Shutdown ........................................... 11
2.6 Power-Up/Power-Down/Reset Circuits ............... 11
3. Frequency References ............................................... 12
3.1 Crystal Interface and Clock Generation .............. 12
3.2 External Frequency Reference ............................ 12
3.3 Frequency Selection ............................................ 14
3.4 External 32.768 kHz Low-Power Oscillator ......... 14
4. Bluetooth Subsystem Overview ................................ 15
4.1 Features .............................................................. 15
4.2 Bluetooth Radio ................................................... 16
5. Bluetooth Baseband Core ......................................... 17
5.1 Bluetooth 4.1 Features ........................................ 17
5.2 Bluetooth Low Energy ......................................... 17
5.3 Link Control Layer ............................................... 17
5.4 Test Mode Support .............................................. 18
5.5 Bluetooth Power Management Unit ..................... 18
5.6 Adaptive Frequency Hopping .............................. 22
5.7 Advanced Bluetooth/WLAN Coexistence ............ 22
5.8 Fast Connection (Interlaced Page and
Inquiry Scans) ................................................... 22
6. Microprocessor and Memory Unit for Bluetooth ..... 23
6.1 Overview ............................................................. 23
6.2 RAM, ROM, and Patch Memory .......................... 23
6.3 Reset ................................................................... 23
7. Bluetooth Peripheral Transport Unit ........................ 24
7.1 PCM Interface ..................................................... 24
7.2 UART Interface .................................................... 30
7.3 I2S Interface ........................................................ 31
8. WLAN Global Functions ............................................ 34
8.1 WLAN CPU and Memory Subsystem .................. 34
8.2 One-Time Programmable Memory ...................... 34
8.3 GPIO Interface .................................................... 34
8.4 External Coexistence Interface ........................... 35
8.5 UART Interface .................................................... 35
8.6 JTAG Interface .................................................... 35
9. WLAN Host Interfaces ................................................ 36
9.1 SDIO v3.0 ............................................................ 36
9.2 Generic SPI Mode ............................................... 37
10. Wireless LAN MAC and PHY ................................... 45
10.1 IEEE 802.11ac MAC ......................................... 45
10.2 IEEE 802.11ac PHY .......................................... 48
11. WLAN Radio Subsystem ......................................... 50
11.1 Receiver Path .................................................... 50
Document Number: 002-15057 Rev. *B
11.2 Transmit Path .................................................... 50
11.3 Calibration ......................................................... 50
12. Pinout and Signal Descriptions .............................. 52
12.1 Ball Maps ........................................................... 52
12.2 Signal Descriptions ............................................ 53
12.3 WLAN GPIO Signals and Strapping Options .... 58
12.4 GPIO/SDIO Alternative Signal Functions .......... 61
12.5 I/O States .......................................................... 62
13. DC Characteristics ................................................... 65
13.1 Absolute Maximum Ratings ............................... 65
13.2 Environmental Ratings ...................................... 65
13.3 Electrostatic Discharge Specifications .............. 65
13.4 Recommended Operating Conditions and
DC Characteristics ............................................ 66
14. Bluetooth RF Specifications .................................... 68
15. WLAN RF Specifications .......................................... 74
15.1 Introduction ........................................................ 74
15.2 2.4 GHz Band General RF Specifications ........ 74
15.3 WLAN 2.4 GHz Receiver Performance
Specifications ................................................... 75
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications ................................................... 79
15.5 WLAN 5 GHz Receiver Performance
Specifications ................................................... 80
15.6 WLAN 5 GHz Transmitter Performance
Specifications ................................................... 83
15.7 General Spurious Emissions Specifications ...... 84
16. Internal Regulator Electrical Specifications .......... 85
16.1 Core Buck Switching Regulator ......................... 85
16.2 3.3V LDO (LDO3P3) ......................................... 86
16.3 2.5V LDO (BTLDO2P5) ..................................... 87
16.4 CLDO ................................................................ 88
16.5 LNLDO .............................................................. 89
17. System Power Consumption ................................... 90
17.1 WLAN Current Consumption ............................. 90
17.2 Bluetooth Current Consumption ........................ 91
18. Interface Timing and AC Characteristics ............... 92
18.1 SDIO/gSPI Timing ............................................. 92
18.2 JTAG Timing .................................................. 101
19. Power-Up Sequence and Timing ........................... 102
19.1 Sequencing of Reset and
Regulator Control Signals ............................... 102
20. Package Information .............................................. 105
20.1 Package Thermal Characteristics ................... 105
20.2 Junction Temperature Estimation and
PSIJT Versus THETAJC .................................. 105
20.3 Environmental Characteristics ......................... 105
21. Mechanical Information ......................................... 106
22. Ordering Information .............................................. 108
23. References .............................................................. 108
Document History ........................................................ 109
Sales, Solutions, and Legal Information ................... 110
Page 3 of 110
CYW88335
1. Overview
1.1 Overview
The Cypress CYW88335 single-chip device provides the highest level of integration for Automotive In-Vehicle Infotainment wireless
connectivity systems, with integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio, and Bluetooth 4.1 + enhanced data rate (EDR).
It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for platform
flexibility in size, form, and function.
The following figure shows the interconnect of all the major physical blocks in the CYW88335 and their associated external interfaces,
which are described in greater detail in the following sections.
Document Number: 002-15057 Rev. *B
Page 4 of 110
CYW88335
Figure 2. CYW88335 Block Diagram
SECI UART
and GCI-GPIOs
UART
PMU
WLAN RAM
Sharing
WL_HOST_WAKE
WL_DEV_WAKE
JTAG
Other GPIOs
TCM
RAM768KB
ROM640KB
SDIOD
PCM
ARMCM3
Registers
WLAN
Master
Slave
JTAG
Master
ARMCR4
WLAN ÅÆ BT Access
AXI2AHB
AHB2AXI
Chip
Common
OTP
RX/TX
BLE
AHB2APB
AXI2APB
DOT11MAC (D11)
GCI Coex I/F
GPIO
Timers
WD
Pause
SDIO 3.0
NIC-301 AXI Backplane
I2S
DMA
WL_REG_ON
BT_REG_ON
VBAT
RAM
ROM
AHB Bus Matrix
BT_HOST_WAKE
BT_DEV_WAKE
UART
PCM
I2S
Other GPIOs
Port Control
GCI
LCU
APU
BlueRF
Shared LNA Control
and Other Coex I/Fs
RF Switch Controls
1 x 1 802.11ac PHY
2.4 GHz/5 GHz 802.11ac
Dual-Band Radio
Modem
XTAL
Bluetooth RF
32 kHz External LPO
BT
PA
WLAN
Bluetooth
CLB
FEM or
SP3T
2.4 GHz
FEM or
SPDT
5 GHz
Diplexer
Document Number: 002-15057 Rev. *B
Page 5 of 110
CYW88335
1.2 Features
The CYW88335 supports the following features:
■
IEEE 802.11a/b/g/n/ac dual-band radio with virtual-simultaneous dual-band operation
■
Bluetooth v4.1 + EDR with integrated Class 1 PA
■
Concurrent Bluetooth and WLAN operation
■
On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■
WLAN host interface options:
❐ SDIO v3.0 (1-bit/4-bit)—up to 208 MHz clock rate in SDR104 mode
❐ gSPI—up to 48 MHz clock rate
■
BT host digital interface (which can be used concurrently with the above interfaces):
❐ UART (up to 4 Mbps)
■
ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receptions
■
I2S/PCM for BT audio
■
HCI high-speed UART (H4, H4+, H5) transport support
■
Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S
and PCM interface)
■
Bluetooth SmartAudio® technology improves voice and music quality for automotive applications
■
Bluetooth low-power inquiry and page scan
■
Bluetooth Low Energy (BLE) support
■
Bluetooth Packet Loss Concealment (PLC)
■
Bluetooth Wide Band Speech (WBS)
■
Audio rate-matching algorithms
1.3 Standards Compliance
The CYW88335 supports the following standards:
■
Bluetooth 2.1 + EDR
■
Bluetooth 3.0
■
Bluetooth 4.1 (Bluetooth Low Energy)
■
IEEE802.11ac single-stream mandatory and optional requirements for 20 MHz, 40 MHz, and 80 MHz channels
■
IEEE 802.11n—Handheld Device Class (Section 11)
■
IEEE 802.11a
■
IEEE 802.11b
■
IEEE 802.11g
■
IEEE 802.11d
■
IEEE 802.11h
■
IEEE 802.11i
Document Number: 002-15057 Rev. *B
Page 6 of 110
CYW88335
■
Security:
❐ WEP
™
❐ WPA Personal
™
❐ WPA2 Personal
❐ WMM
❐ WMM-PS (U-APSD)
❐ WMM-SA
❐ AES (Hardware Accelerator)
❐ TKIP (HW Accelerator)
❐ CKIP (SW Support)
■
Proprietary Protocols:
❐ CCXv2
❐ CCXv3
❐ CCXv4
❐ CCXv5
■
IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements
The CYW88335 will support the following future drafts/standards:
■
IEEE 802.11r—Fast Roaming (between APs)
■
IEEE 802.11w—Secure Management Frames
■
IEEE 802.11 Extensions:
®
❐ IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported)
❐ IEEE 802.11h 5 GHz Extensions
❐ IEEE 802.11i MAC Enhancements
❐ IEEE 802.11k Radio Resource Measurement
1.4 Automotive Usage Model
The CYW88335 incorporates a number of unique features to simplify integration into automotive platforms. Its flexible PCM and UART
interfaces enable it to transparently connect with existing platform circuits. In addition, the TCXO and LPO inputs allow the use of
existing automotive features to further minimize the size, power, and cost of the complete system.
■
The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or
multiple external codec devices.
■
The UART interface supports hardware flow control with tight integration to power-control sideband signaling to support the lowest
power operation.
■
The crystal oscillator interface accommodates any of the typical reference frequencies used by mobile platform architectures.
■
The highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions output regardless of the
state of operation. It has been fully characterized in the global cellular bands.
■
The transceiver design has excellent blocking and intermodulation performance in the presence of a cellular transmission (LTE,
GSM®, GPRS, CDMA, WCDMA, or iDEN).
The CYW88335 is designed to directly interface with new and existing automotive platform designs.
Document Number: 002-15057 Rev. *B
Page 7 of 110
CYW88335
2. Power Supplies and Power Management
2.1 Power Supply Topology
One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW88335. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW88335.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off and on based on the dynamic
demands of the digital baseband.
The CYW88335 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO
supply) provide the CYW88335 with all the voltages it requires, further reducing leakage currents.
2.2 PMU Features
■
VBAT to 1.35V (275 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator
■
VBAT to 3.3V (200 mA nominal, 450 mA maximum) LDO3P3
■
VBAT to 2.5V (15 mA nominal, 70 mA maximum) BTLDO2P5
■
1.35V to 1.2V (100 mA nominal, 150 mA maximum) LNLDO
■
1.35V to 1.2V (175 mA nominal, 300 mA maximum) CLDO with bypass mode for deep-sleep
■
Additional internal LDOs (not externally accessible)
Document Number: 002-15057 Rev. *B
Page 8 of 110
CYW88335
Figure 3 shows the regulators and a typical power topology.
Figure 3. Typical Power Topology for the CYW88335
Shaded areas are internal to the CYW88335
Internal LNLDO
80 mA
Internal LNLDO
80 mA
Internal VCOLDO
80 mA
Internal LNLDO
80 mA
1.2V
XTAL LDO
30 mA
1.2V
WL RF – AFE
1.2V
WL RF – TX (2.4 GHz, 5 GHz)
1.2V
WL RF – LOGEN (2.4 GHz, 5 GHz)
1.2V
WL RF – RX/LNA (2.4 GHz, 5 GHz)
WL RF – XTAL
WL RF – RFPLL PFD/MMD
LNLDO
100 mA
1.2V
BT RF
DFE/DFLL
WL_REG_ON
BT_REG_ON
VBAT
PLL/RXTX
Core Buck
Regulator
CBUCK
Peak 600 mA
Average 275 mA
WLAN BBPLL/DFLL
1.35V
WLAN/BT/CLB/Top, always on
WL OTP
VDDIO
LPLDO1
3 mA
1.1V
CLDO
Peak 300 mA
Average 175 mA
(Bypass in deep
sleep)
WL PHY
1.2V– 1.1V
WL DIGITAL
BT DIGITAL
WL/BT SRAMs
VDDIO
BTLDO2P5
Peak 70 mA
Average 15 mA
2.5V
MEMLPLDO
3 mA
0.9V
BT CLASS 1 PA
WL PA/PAD (2.4 GHz, 5 GHz)
VDDIO_RF
Internal LNLDO
25 mA
Internal LNLDO
8 mA
Document Number: 002-15057 Rev. *B
2.5V
3.3V
2.5V
LDO3P3
Peak 800–450 mA
Average 200 mA
WL OTP 3.3V
WL RF – VCO
WL RF – CP
Page 9 of 110
CYW88335
2.3 WLAN Power Management
All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce
leakage current and supply voltages. Additionally, the CYW88335 integrated RAM is a high Vt memory with dynamic clock control.
The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW88335 includes an advanced WLAN
power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW88335 into
various power management states appropriate to the current environment and activities that are being performed. The power
management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up
sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock frequency) in the PMU
sequencer are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated
altogether) for the current mode. Slower clock speeds are used wherever possible.
The CYW88335 WLAN power states are described as follows:
■
Active mode— All WLAN blocks in the CYW88335 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■
Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW88335 remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power consumption
to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU
sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■
Deep-sleep mode—Most of the chip, including both analog and digital domains, and most of the regulators are powered off. Logic
states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered
off. Upon a wake-up event triggered by the PMU timers, an external interrupt, or a host resume through the SDIO bus, logic states
in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.
■
Power-down mode—The CYW88335 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic reenabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources
based on a computation of the required resources and a table that describes the relationship between resources and the time needed
to enable and disable them.
Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of four states (enabled, disabled, transition_on, and transition_off) and has a timer that contains 0 when the
resource is enabled or disabled and a nonzero value in the transition states. The timer is loaded with the time_on or time_off value of
the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz
PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is
0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go
immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or
the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■
Computes the required resource set based on requests and the resource dependency table.
■
Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■
Compares the request with the current resource status and determines which resources must be enabled or disabled.
■
Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.
■
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
Document Number: 002-15057 Rev. *B
Page 10 of 110
CYW88335
2.5 Power-Off Shutdown
The CYW88335 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW88335 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW88335 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shut-down state, the provided VDDIO remains applied to the CYW88335, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW88335 to be fully integrated in an embedded device and
take full advantage of the lowest power-savings modes.
When the CYW88335 is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW88335 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks,
allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see
Power-Up Sequence and Timing on page 102.
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal
Description
WL_REG_ON
This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the
BT_REG_ON input to control the internal CYW88335 regulators. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that
is enabled by default. It can be disabled through programming.
BT_REG_ON
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal
CYW88335 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has
an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming.
Document Number: 002-15057 Rev. *B
Page 11 of 110
CYW88335
3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW88335 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator,
including all external components, is shown in Figure 4. Consult the reference schematics for the latest configuration and recommended components.
Figure 4. Recommended Oscillator Configuration
C *
WRF_XTAL_IN
37.4 MHz
C *
X ohms *
WRF_XTAL_OUT
* Values determined by crystal drive
level. See reference schematics for details.
A fractional-N synthesizer in the CYW88335 generates the radio frequencies, clocks, and data/packet timing, enabling the CYW88335
to operate using a wide selection of frequency references.
For SDIO applications, the recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal
interface are listed in Table 3 on page 13.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for details.
3.2 External Frequency Reference
As an alternative to a crystal, an external precision frequency reference can be used. The recommended default frequency is 37.4
MHz. This must meet the phase noise requirements listed in Table 3.
If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling capacitor, as shown
in Figure 5. The internal clock buffer connected to this pin will be turned off when the CYW88335 goes into sleep mode. When the
clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_BUCK_VDD1P5
pin.
Figure 5. Recommended Circuit to Use with an External Reference Clock
1000 pF
Reference
Clock
WRF_XTAL_IN
NC
Document Number: 002-15057 Rev. *B
WRF_XTAL_OUT
Page 12 of 110
CYW88335
Table 3. Crystal Oscillator and External Clock—Requirements and Performance
Parameter
External Frequency
Referenceb c
Crystala
Conditions/Notes
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Frequency
2.4 GHz and 5 GHz bands,
IEEE 802.11ac operation
35
37.4
38.4
–
37.4
–
MHz
Frequency
5 GHz band, IEEE 802.11n operation
only
19
37.4
38.4
35
37.4
38.4
MHz
Frequency
2.4 GHz band IEEE 802.11n
operation, and both bands legacy
802.11a/b/g operation only
Frequency tolerance over
the lifetime of the
Without trimming
equipment, including
e
temperature
Ranges between 19 MHz and 38.4 MHzd
–20
–
20
–20
–
20
ppm
Crystal load capacitance
–
–
12
–
–
–
–
pF
ESR
–
–
–
60
–
–
–
Ω
200
–
–
–
–
–
µW
Resistive
–
–
–
30k
100k
–
Ω
Capacitive
–
–
7.5
–
–
7.5
pF
WRF_XTAL_IN
input low level
DC-coupled digital signal
–
–
–
0
–
0.2
V
WRF_XTAL_IN
input high level
DC-coupled digital signal
–
–
–
1.0
–
1.26
V
WRF_XTAL_IN
input voltage
(see Figure 5)
AC-coupled analog signal
–
–
–
1000
–
1200
mVp-p
Duty cycle
37.4 MHz clock
–
–
–
40
50
60
%
Phase
(IEEE 802.11b/g)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–129
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–136
dBc/Hz
Phase noisef
(IEEE 802.11a)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–137
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–144
dBc/Hz
37.4 MHz clock at 10 kHz offset
Phase
(IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–134
dBc/Hz
–
–
–
–
–
–141
dBc/Hz
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–142
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–149
dBc/Hz
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–148
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–155
dBc/Hz
Drive level
Input impedance
(WRF_XTAL_IN)
noisef
External crystal must be able to
tolerate this drive level.
noisef
Phase noisef
(IEEE 802.11n, 5 GHz)
noisef
Phase
(IEEE 802.11ac, 5 GHz)
a.
b.
c.
d.
e.
f.
(Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.
See “External Frequency Reference” on page 12 for alternative connection methods.
For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.
The frequency step size is approximately 80 Hz.
It is the responsibility of the equipment designer to select oscillator components that comply with these specifications.
Assumes that external clock has a flat phase-noise response above 100 kHz.
Document Number: 002-15057 Rev. *B
Page 13 of 110
CYW88335
3.3 Frequency Selection
Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard
mobile platform reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, and 38.4 MHz, but also other frequencies in this range with
an approximate resolution of 80 Hz. The CYW88335 must have the reference frequency set correctly in order for any of the UART or
PCM interfaces to function correctly, since all bit timing is derived from the reference frequency.
Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require
support to be added in the driver plus additional, extensive system testing. Contact Cypress for details.
The reference frequency for the CYW88335 may be set in the following ways:
■
Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency.
■
Autodetect any of the standard handset reference frequencies using an external LPO clock.
For applications where the reference frequency is one of the standard frequencies commonly used, the CYW88335 automatically
detects the reference frequency and programs itself to the correct reference frequency. In order for automatic frequency detection to
work correctly, the CYW88335 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed in Table 4 on
page 14 and is present during power-on reset.
3.4 External 32.768 kHz Low-Power Oscillator
The CYW88335 uses a secondary low-frequency clock for low-power-mode timing. An external 32.768 kHz precision oscillator is
required.
Use a precision external 32.768 kHz clock that meets the requirements listed in Table 4.
Table 4. External 32.768 kHz Sleep Clock Specifications
Parameter
Nominal input frequency
Frequency accuracy
Duty cycle
Input signal amplitude
Signal type
Input impedancea
Clock jitter (during initial start-up)
a.
LPO Clock
Units
32.768
kHz
±200
ppm
30–70
%
200–1800
mV, p-p
Square-wave or sine-wave
–
>100k
0.35T
VH = 2.0V
SCK
VL = 0.8V
thtr > 0
totr < 0.8T
SD and WS
T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr
* tRC is only relevant for transmitters in slave mode.
Figure 16. I2S Receiver Timing
T
tLC > 0.35T
tHC > 0.35
VH = 2.0V
SCK
VL = 0.8V
tsr > 0.2T
thr > 0
SD and WS
T = Clock period
Tr = Minimum allowed clock period for transmitter
T > Tr
Document Number: 002-15057 Rev. *B
Page 33 of 110
CYW88335
8. WLAN Global Functions
8.1 WLAN CPU and Memory Subsystem
The CYW88335 WLAN section includes an integrated ARM Cortex-R4™ 32-bit processor with internal RAM and ROM. The ARM
Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug capabilities. It is intended
for deeply embedded applications that require fast interrupt response features. Delivering more than 30% performance gain over
ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb®-2 instruction set.
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It supports integrated sleep modes.
Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin overhead, and
reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode and System buses), and extensive
debug features including real time trace of program execution.
On-chip memory for the CPU includes 768 KB SRAM and 640 KB ROM.
8.2 One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal One-Time Programmable (OTP) memory, which is read by
the system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC
address can be stored, depending on the specific board design. Customer accessible OTP memory is 502 bytes.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test
tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state
can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with
the reference board design package.
OTP programming is intended to be performed when the WLAN/BT hardware modules are manufactured. It should not be
programmed in the field or by the automobile manufacturer. Additionally, OTP programming should be done in an environment where
the room temperature is between 20°C and 30°C.
8.3 GPIO Interface
The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the CYW88335 that can be used to
connect to various external devices:
■
WLBGA package – 9 GPIOs
Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via
the GPIO control register. In addition, the GPIO pins can be assigned to various other functions (see Table 22 on page 61).
Document Number: 002-15057 Rev. *B
Page 34 of 110
CYW88335
8.4 External Coexistence Interface
An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such
as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance.
Figure 17 shows the LTE coexistence interface. See Table 22 on page 61 for details on multiplexed signals such as the GPIO pins.
See Table 10 on page 30 for UART baud rates.
Figure 17. Cypress GCI or BT-SIG Mode LTE Coexistence Interface for the CYW88335
CYW88335
WLAN
GCI
SECI_OUT/BT_TXD
SECI_IN/BT_TXD
LTE\IC
UART_IN
UART_OUT
BT
NOTES:
SECI_OUT/BT_TXD and SECI_IN/BT_RXD are multiplexed on the GPIOs.
The 2-wire LTE coexistence interface is intended for future compatibility with the BT
SIG
2-wire interface that is being standardized for Core 4.1.
ORing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is
achieved by setting the GPIO mask registers appropriately.
8.5 UART Interface
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins (see Table 22 on page 61). Provided
primarily for debugging during development, this UART enables the CYW88335 to operate as RS-232 data termination equipment
(DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and
provides a FIFO size of 64 × 8 in each direction.
8.6 JTAG Interface
The CYW88335 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
See Table 22 on page 61 for JTAG pin assignments.
Document Number: 002-15057 Rev. *B
Page 35 of 110
CYW88335
9. WLAN Host Interfaces
9.1 SDIO v3.0
The CYW88335 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
■
DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■
HS: High speed up to 50 MHz (3.3V signaling).
■
SDR12: SDR up to 25 MHz (1.8V signaling).
■
SDR25: SDR up to 50 MHz (1.8V signaling).
■
SDR50: SDR up to 100 MHz (1.8V signaling).
■
SDR104: SDR up to 208 MHz (1.8V signaling).
DDR50: DDR up to 50 MHz (1.8V signaling).
Note: The CYW88335 is backward compatible with SDIO v2.0 host interfaces.
■
The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different
from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided.
SDIO mode is enabled by strapping options. Refer to Table 17 WLAN GPIO Functions and Strapping Options.
The following three functions are supported:
■
Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B)
■
Function 1 Backplane Function to access the internal system-on-chip (SoC) address space
(Max. BlockSize/ByteCount = 64B)
■
Function 2 WLAN Function for efficient WLAN packet transfer through DMA
(Max. BlockSize/ByteCount = 512B)
9.1.1 SDIO Pins
Table 13. SDIO Pin Description
SD 4-Bit Mode
DATA0
SD 1-Bit Mode
Data line 0
gSPI Mode
DATA
Data line
DO
Data output
DATA1
Data line 1 or Interrupt
IRQ
Interrupt
IRQ
Interrupt
DATA2
Data line 2 or Read Wait
RW
Read Wait
NC
Not used
DATA3
Data line 3
N/C
Not used
CS
Card select
CLK
Clock
CLK
Clock
SCLK
Clock
CMD
Command line
CMD
Command line
DI
Data input
Figure 18. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
SD Host
CMD
CYW88335
DAT[3:0]
Document Number: 002-15057 Rev. *B
Page 36 of 110
CYW88335
Figure 19. Signal Connections to SDIO Host (SD 1-Bit Mode)
CLK
CMD
SD Host
DATA
CYW88335
IRQ
RW
Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD
line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper
programming of the SDIO host’s internal pull-ups.
9.2 Generic SPI Mode
In addition to the full SDIO mode, the CYW88335 includes the option of using the simplified generic SPI (gSPI) interface/protocol.
Characteristics of the gSPI mode include:
■
Supports up to 48 MHz operation
■
Supports fixed delays for responses and data from device
■
Supports alignment to host gSPI frames (16 or 32 bits)
■
Supports up to 2 KB frame size per transfer
■
Supports little endian (default) and big endian configurations
■
Supports configurable active edge for shifting
■
Supports packet transfer through DMA for WLAN
gSPI mode is enabled using the strapping option pins strap_host_ifc_[3:1].
Figure 20. Signal Connections to SDIO Host (gSPI Mode)
SCLK
DI
SD Host
DO
CYW88335
IRQ
CS
Document Number: 002-15057 Rev. *B
Page 37 of 110
CYW88335
9.2.1 SPI Protocol
The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianness is supported in both modes. Figure 21 and
Figure 22 show the basic write and write/read commands.
Figure 21. gSPI Write Protocol
Figure 22. gSPI Read Protocol
Document Number: 002-15057 Rev. *B
Page 38 of 110
CYW88335
Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 23.
Figure 23. gSPI Command Structure
CYW
BCM_SPID
Command Structure
31
30 29
28
C
A
F0
F1
27
11 10
Ad dres s – 17 bits
0
P acket length - 11b its *
* 11’ h0 = 204 8 by tes
F unction N o: 00
01
10
11
–
–
–
–
F unc
F unc
F unc
F unc
0
Ϭ͗ůů^W/ƐƉĞĐŝĮĐƌĞŐŝƐƚĞƌƐ
1
1: Registers and meories belonging to other blocks in the chip (64 bytes max)
2
2: DMA channel 1. WLAN packets up to 2048 bytes.
3
ϯ͗DĐŚĂŶŶĞůϮ;ŽƉƟŽŶĂůͿ͘WĂĐŬĞƚƐƵƉƚŽϮϬϰϴďLJƚĞƐ͘
A cce ss : 0 – F ixed add ress
1 – Incremental add res s
C ommand : 0 – R ead
1 – W rite
Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following
bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.
Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge
of the clock burst for the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data
word. This allows data to be ready for the first clock edge without relying on asynchronous delays.
Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read
command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval
between the command/address is not fixed.
Document Number: 002-15057 Rev. *B
Page 39 of 110
CYW88335
Status
The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information
about any packet errors, protocol errors, information about available packet in the RX queue, etc. The status information helps in
reducing the number of interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing
overhead. The gSPI bus timing for read/write transactions with and without status notification are as shown in Figure 24 and Figure
25 on page 41. See Table 14 on page 41 for information on status field details.
Figure 24. gSPI Signal Timing Without Status (32-bit Big Endian)
Write
cs
sclk
mosi
C31
C31 C30
C30
C1
C1
C0
C0
D31
D31 D30
D30
Command 32 bits
Write‐Read
D1
D1
D0
D0
Write Data 16*n bits
cs
sclk
mosi
C31
C31 C30
C30
C0
C0
miso
D31
D31 D30
D30
Response
Delay
Command
32 bits
Read
D1
D1
D0
D0
Read Data 16*n bits
cs
sclk
mosi
C31
C31 C30
C30
C0
C0
miso
D31
D31 D30
D30
Command
32 bits
Document Number: 002-15057 Rev. *B
Response
Delay
D0
D0
Read Data
16*n bits
Page 40 of 110
CYW88335
Figure 25. gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian)
cs
Write
sclk
mosi
C31
C31
C1
C1
C0
C0
D31
D31
D1
D1
D0
D0
S31
S31
miso
Command 32 bits
Write‐Read
Write Data 16*n bits
S1
S1
S0
S0
Status 32 bits
cs
sclk
mosi
C31
C31
C0
C0
miso
D31
D31
Command 32 bits
Read
D1
D1
D0
D0
Read Data 16*n bits
S31
S31
S0
S0
Status 32 bits
cs
sclk
mosi
C31
C31
C0
C0
miso
D31
D31
Command 32 bits
D1
D1
D0
D0
Read Data 16*n bits
S31
S31
S0
S0
Status 32 bits
Table 14. gSPI Status Field Details
Bit
Name
Description
0
Data not available
1
Underflow
FIFO underflow occurred due to current (F2, F3) read command
2
Overflow
FIFO overflow occurred due to current (F1, F2, F3) write command
3
F2 interrupt
F2 channel interrupt
4
F3 interrupt
F3 channel interrupt
5
F2 RX Ready
F2 FIFO is ready to receive data (FIFO empty)
6
F3 RX Ready
F3 FIFO is ready to receive data (FIFO empty)
7
Reserved
8
F2 Packet Available
Packet is available/ready in F2 TX FIFO
F2 Packet Length
Length of packet available in F2 FIFO
F3 Packet Available
Packet is available/ready in F3 TX FIFO
F3 Packet Length
Length of packet available in F3 FIFO
9:19
20
21:31
Document Number: 002-15057 Rev. *B
The requested read data is not available
–
Page 41 of 110
CYW88335
9.2.2 gSPI Host-Device Handshake
To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up WLAN
register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW88335 is ready for data transfer. The
device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for
waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to
pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt
and then take necessary actions.
9.2.3 Boot-Up Sequence
After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to poll with a read
command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct
register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wakeup-WLAN bit
(F0 reg 0x00 bit 7). The wakeup-WLAN issues a clock request to the PMU.
For the first time after power-up, the host must wait for the availability of low power clock inside the device. Once that is available, the
host must write to a PMU register to set the crystal frequency, which turns on the PLL. After the PLL is locked, the chipActive interrupt
is issued to the host. This interrupt indicates the device awake/ready status. See Table 15 for information on gSPI registers.
In Table 15, the following notation is used for register access:
■
R: Readable from host and CPU
■
W: Writable from host
■
U: Writable from CPU
Table 15. gSPI Registers
Address
x0000
Register
Bit
Access
Default
Word length
0
R/W/U
0
0: 16 bit word length
1: 32 bit word length
Endianness
1
R/W/U
0
0: Little Endian
1: Big Endian
High-speed mode
4
R/W/U
1
0: Normal mode. RX and TX at different edges.
1: High speed mode. RX and TX on same edge (default).
Interrupt polarity
5
R/W/U
1
0: Interrupt active polarity is low
1: Interrupt active polarity is high (default)
A write of 1 will denote a wake-up command from the host
to the device. This will be followed by an F2 Interrupt from
the gSPI device to the host, indicating device awake
status.
Wake-up
x0001
x0002
x0003
x0004
Description
7
R/W
0
7:0
R/W/U
8‘h04
Status enable
0
R/W
1
0: no status sent to host after read/write
1: status sent to host after read/write
Interrupt with status
1
R/W
0
0: do not interrupt if status is sent
1: interrupt host even if status is sent
Response delay for all
2
R/W
0
0: response delay applicable to F1 read only
1: response delay applicable to all function read
Reserved
–
–
–
–
0
R/W
0
Requested data not available; Cleared by writing a 1 to
this location
1
R
0
F2/F3 FIFO underflow due to last read
2
R
0
F2/F3 FIFO overflow due to last write
5
R
0
F2 packet available
6
R
0
F3 packet available
7
R
0
F1 overflow due to last write
Response delay
Interrupt register
Document Number: 002-15057 Rev. *B
Configurable read response delay in multiples of 8 bits
Page 42 of 110
CYW88335
Table 15. gSPI Registers (Cont.)
Address
x0005
Register
Interrupt register
Bit
Access
Default
5
R
0
F1 Interrupt
Description
6
R
0
F2 Interrupt
7
R
0
F3 Interrupt
x0006–
x0007
Interrupt enable
register
15:0
R/W/U
x0008–
x000B
Status register
31:0
R
32'h0000
0
R
1
F1 enabled
1
R
0
F1 ready for data transfer
13:2
R/U
12'h40
0
R/U
1
F2 enabled
1
R
0
F2 ready for data transfer
15:2
R/U
14'h800
0
R/U
1
F3 enabled
1
R
0
F3 ready for data transfer
15:2
R/U
14'h800
x000C–
x000D
F1 info register
16'hE0E7 Particular Interrupt is enabled if a corresponding bit is set
Same as status bit definitions
F1 max packet size
x000E–
x000F
F2 info register
x0010–
x0011
F3 info register
x0014–
x0017
Test–Read only
register
31:0
R
This register contains a predefined pattern, which the host
32'hFEED
can read and determine if the gSPI interface is working
BEAD
properly.
x0018–
x001B
Test–R/W register
31:0
R/W/U
This is a dummy register where the host can write some
32'h00000
pattern and read it back to determine if the gSPI interface
000
is working properly.
Document Number: 002-15057 Rev. *B
F2 max packet size
F3 max packet size
Page 43 of 110
CYW88335
Figure 26 shows the WLAN boot-up sequence from power-up to firmware download.
Figure 26. WLAN Boot-Up Sequence
VBAT*
VDDIO
WL_REG_ON
1.9 μF, ESL 1.35V, Co= 2.2 µF, Vo = 1.2V
20
–
–
dB
LDO turn-on time
LDO turn-on time when rest of chip is up
–
140
180
µs
External output capacitor, Co
Total ESR (trace/capacitor):
5 mΩ–240 mΩ
0.5a
2.2
4.7
µF
External input capacitor
Only use an external input capacitor at the
VDD_LDO pin if it is not supplied from CBUCK
output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ
–
1
2.2
µF
a.
Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-15057 Rev. *B
Page 89 of 110
CYW88335
17. System Power Consumption
Note: Unless otherwise stated, these values apply for the conditions specified in Table 27 on page 66.
17.1 WLAN Current Consumption
Table 43 shows the typical, total current consumed by the CYW88335. To calculate total-solution current consumption for designs
using external PAs, LNAs, and/or FEMs, add the current consumption of the external devices to the numbers in Table 43.
All values in Table 43 are with the Bluetooth core in reset (that is, with Bluetooth off).
Table 43. Typical WLAN Current Consumption (CYW88335 Current Only)
Mode
Bandwidth (MHz)
Band
(GHz)
VBAT = 3.6V, VDDIO = 1.8V, TA 25°C
Vbat, mA
Vioa, µA
Sleep Modes
–
–
0.005
SLEEPc
–
–
0.005
d
IEEE Power Save, DTIM 1
–
2.4
0.850
IEEE Power Save, DTIM 3d
–
2.4
0.350
IEEE Power Save, DTIM 1d
–
5
0.550
IEEE Power Save, DTIM 3d
–
5
0.300
Active Modes
Receivee,f MCS8 (SGI)
20
2.4
50
g
CRS
20
2.4
46
Receivee,f MCS7 (SGI)
20
5
66
g
CRS
20
5
56
Receivee,f MCS7 (SGI)
40
5
79.5
CRSg
40
5
67
e,f
Receive MCS9 (SGI)
80
5
110
CRSg
80
5
103
Active Modes with External PAs (TX Output Power is –5 dBm at the Chip Port)
Transmit, CCK
20
2.4
88
Transmit, MCS8, HT20, SGIe, h
20
2.4
76
e,
h
Transmit, MCS7, SGI
20
5
111
Transmit, MCS7e, h
40
5
125
Transmit, MCS9, SGIe, h
40
5
125
e,
h
Transmit, MCS9, SGI
80
5
147
Active Modes with Internal PAs (TX Output Power Measured at the Chip Port)
TX CCK 11 Mbps at 21.7 dBm
20
2.4
325
TX OFDM MCS8 (SGI) at 17.2 dBm
20
2.4
240
TX OFDM MCS7 (SGI) at 18.5 dBm
20
5
280
TX OFDM MCS7 at 18.7 dBm
40
5
340
TX OFDM MCS9 (SGI) at 16.2 dBm
40
5
270
TX OFDM MCS9 (SGI) at 15.7 dBm
80
5
270
OFFb
a.
b.
c.
d.
e.
f.
g.
h.
5
150
150
150
150
150
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
VIO is specified with all pins idle (not switching) and not driving any loads.
WL_REG_ON, BT_REG_ON low.
Idle, not associated, or inter-beacon.
Beacon Interval = 102.4 ms. Beacon duration = 1 ms @1 Mbps. Average current over the specified DTIM intervals.
Measured using packet engine test mode.
Duty cycle is 100%. Carrier sense (CS) detect/packet receive.
Carrier sense (CCA) when no carrier present.
Duty cycle is 100%. Excludes external PA contribution.
Document Number: 002-15057 Rev. *B
Page 90 of 110
CYW88335
17.2 Bluetooth Current Consumption
The Bluetooth BLE current consumption measurements are shown in Table 44.
Note:
■
The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 44.
■
The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.
Table 44. Bluetooth BLE Current Consumption
Operating Mode
VBAT (VBAT = 3.6V) Typical
VDDIO (VDDIO = 1.8V) Typical
Units
10
225
µA
180
235
µA
320
235
µA
500 ms Sniff Master
170
250
µA
500 ms Sniff Slave
120
250
µA
DM1/DH1 Master
22.81
0.034
mA
DM3/DH3 Master
28.06
0.044
mA
DM5/DH5 Master
29.01
0.047
mA
3DH5 Master
27.09
0.100
mA
7.9
0.123
mA
11.38
0.180
mA
Sleep
Standard 1.28s Inquiry Scan
P and I
Scanb
SCO HV3 Master
HV3 + Sniff +
Scana
Scanb
175
235
µA
BLE Scan 10 ms
14.09
0.022
mA
BLE Adv—Unconnectable 1.00 sec
69
245
µA
BLE Adv—Unconnectable 1.28 sec
67
235
µA
BLE
BLE Adv—Unconnectable 2.00 sec
42
240
µA
4.30
0.020
mA
BLE Connected 1 sec
53
240
µA
BLE Connected 1.28 sec
48
240
µA
BLE Connected 7.5 ms
a.
b.
At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s.
No devices present. A 1.28 second interval with a scan window of 11.25 ms.
Document Number: 002-15057 Rev. *B
Page 91 of 110
CYW88335
18. Interface Timing and AC Characteristics
18.1 SDIO/gSPI Timing
18.1.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 33 and Table 45.
Figure 33. SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tISU
tIH
Input
Output
tODLY
tODLY
(max)
(min)
Table 45. SDIO Bus Timinga Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
b)
SDIO CLK (All values are referred to minimum VIH and maximum VIL
Frequency – Data Transfer mode
fPP
0
–
25
MHz
Frequency – Identification mode
fOD
0
–
400
kHz
Clock low time
tWL
10
–
–
ns
Clock high time
tWH
10
–
–
ns
Clock rise time
tTLH
–
–
10
ns
Clock fall time
tTHL
–
–
10
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
5
–
–
ns
tIH
5
–
–
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
tODLY
0
–
14
ns
Output delay time – Identification mode
tODLY
0
–
50
ns
a.
b.
Timing is based on CL 40pF load on CMD and Data.
Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Document Number: 002-15057 Rev. *B
Page 92 of 110
CYW88335
18.1.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 34 and Table 46 on page 93.
Figure 34. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tISU
tTLH
tIH
Input
Output
tODLY
tOH
Table 46. SDIO Bus Timinga Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
b)
SDIO CLK (all values are referred to minimum VIH and maximum VIL
Frequency – Data Transfer Mode
fPP
0
–
50
MHz
Frequency – Identification Mode
fOD
0
–
400
kHz
Clock low time
tWL
7
–
–
ns
Clock high time
tWH
7
–
–
ns
Clock rise time
tTLH
–
–
3
ns
tTHL
–
–
3
ns
Clock fall time
Inputs: CMD, DAT (referenced to CLK)
Input setup time
tISU
6
–
–
ns
Input hold time
tIH
2
–
–
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
tODLY
–
–
14
ns
Output hold time
tOH
2.5
–
–
ns
Total system capacitance (each line)
CL
–
–
40
pF
a.
b.
Timing is based on CL 40pF load on CMD and Data.
Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Document Number: 002-15057 Rev. *B
Page 93 of 110
CYW88335
18.1.3 SDIO Bus Timing Specifications in SDR Modes
Clock Timing
Figure 35. SDIO Clock Timing (SDR Modes)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 47. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter
–
Symbol
Minimum
Maximum
Unit
40
–
ns
SDR12 mode
20
–
ns
SDR25 mode
tCLK
Comments
10
–
ns
SDR50 mode
4.8
–
ns
SDR104 mode
–
tCR, tCF
–
0.2 × tCLK
ns
tCR, tCF < 2.00 ns (max.) @100 MHz, CCARD = 10 pF
tCR, tCF < 0.96 ns (max.) @208 MHz, CCARD = 10 pF
Clock duty cycle
–
30
70
%
–
Document Number: 002-15057 Rev. *B
Page 94 of 110
CYW88335
Device Input Timing
Figure 36. SDIO Bus Input Timing (SDR Modes)
SDIO_CLK
tIS
tIH
CMD input
DAT[3:0] input
Table 48. SDIO Bus Input Timing Parameters (SDR Modes)
Symbol
Minimum
Maximum
Unit
Comments
SDR104 Mode
tIS
1.4
–
ns
CCARD = 10 pF, VCT = 0.975V
tIH
0.8
–
ns
CCARD = 5 pF, VCT = 0.975V
SDR50 Mode
tIS
3.0
–
tIH
0.8
–
ns
CCARD = 10 pF, VCT = 0.975V
ns
CCARD = 5 pF, VCT = 0.975V
SDR25 Mode
tIS
3.0
–
ns
CCARD = 10 pF, VCT = 0.975V
tIH
0.8
–
ns
CCARD = 5 pF, VCT = 0.975V
tIS
3.0
–
ns
CCARD = 10 pF, VCT = 0.975V
tIH
0.8
–
ns
CCARD = 5 pF, VCT = 0.975V
SDR12 Mode
Document Number: 002-15057 Rev. *B
Page 95 of 110
CYW88335
Device Output Timing
Figure 37. SDIO Bus Output Timing (SDR Modes up to 100 MHz)
tCLK
SDIO_CLK
tODLY
tOH
CMD output
DAT[3:0] output
Table 49. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)
Symbol
Minimum
Maximum
Unit
Comments
tODLY
–
7.5
ns
tCLK ≥ 10 ns CL= 30 pF using driver type B for SDR50
tODLY
–
14.0
ns
tCLK ≥ 20 ns CL= 40 pF using for SDR12, SDR25
tOH
1.5
–
ns
Hold time at the tODLY (min) CL= 15 pF
Figure 38. SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)
tCLK
SDIO_CLK
tOP
tODW
CMD output
DAT[3:0] output
Document Number: 002-15057 Rev. *B
Page 96 of 110
CYW88335
Table 50. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz)
Symbol
Minimum
Maximum
Unit
Comments
tOP
0
2
UI
∆tOP
–350
+1550
ps
Delay variation due to temp change after tuning
tODW
0.60
–
UI
tODW=2.88 ns @208 MHz
Card output phase
■
∆tOP = +1550 ps for junction temperature of ∆tOP = 90 degrees during operation
■
∆tOP = –350 ps for junction temperature of ∆tOP = –20 degrees during operation
■
∆tOP = +2600 ps for junction temperature of ∆tOP = –20 to +125 degrees during operation
Figure 39. ∆tOP Consideration for Variable Data Window (SDR 104 Mode)
Data valid window
Sampling point after tuning
ȴtOP =
1550 ps
ȴtOP =
–350 ps
Data valid window
Sampling point after card junction heating
by +90°C from tuning temperature
Data valid window
Sampling point after card junction cooling
by –20°C from tuning temperature
Document Number: 002-15057 Rev. *B
Page 97 of 110
CYW88335
18.1.4 SDIO Bus Timing Specifications in DDR50 Mode
Figure 40. SDIO Clock Timing (DDR50 Mode)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 51. SDIO Bus Clock Timing Parameters (DDR50 Mode)
Parameter
Symbol
Minimum
Maximum
Unit
Comments
–
tCLK
20
–
ns
DDR50 mode
–
tCR,tCF
–
0.2 × tCLK
ns
tCR, tCF < 4.00 ns (max) @50 MHz, CCARD = 10 pF
Clock duty cycle
–
45
55
%
–
Document Number: 002-15057 Rev. *B
Page 98 of 110
CYW88335
Data Timing, DDR50 Mode
Figure 41. SDIO Data Timing (DDR50 Mode)
FPP
SDIO_CLK
tISU2x
DAT[3:0]
input
Invalid
tIH2x
Data
tISU2x
Invalid
tIH2x
Data
Invalid
tODLY2x (max)
DAT[3:0]
output
Data
Invalid
tODLY2x (max)
tODLY2x
tODLY2x
(min)
(min)
Data
Available timing
window for card
output transition
Data
In DDR50 mode, DAT[3:0] lines are sampled on both edges of
the clock (not applicable for CMD line)
Data
Available timing
window for host to
sample data from card
Table 52. SDIO Bus Timing Parameters (DDR50 Mode)
Parameter
Symbol
Minimum
Maximum
Unit
Comments
Input CMD
Input setup time
tISU
6
Input hold time
tIH
0.8
–
ns
CCARD < 10pF (1 Card)
–
ns
CCARD < 10pF (1 Card)
Output CMD
Output delay time
tODLY
–
13.7
ns
CCARD < 30pF (1 Card)
Output hold time
tOH
1.5
–
ns
CCARD < 15pF (1 Card)
Input setup time
tISU2x
3
–
ns
CCARD < 10pF (1 Card)
Input hold time
tIH2x
0.8
–
ns
CCARD < 10pF (1 Card)
Input DAT
Output DAT
Output delay time
tODLY2x
–
7.0
ns
CCARD < 25pF (1 Card)
Output hold time
tODLY2x
1.5
–
ns
CCARD < 15pF (1 Card)
Document Number: 002-15057 Rev. *B
Page 99 of 110
CYW88335
18.1.5 gSPI Signal Timing
The gSPI host and device always use the rising edge of clock to sample data.
Figure 42. gSPI Timing
Table 53. gSPI Timing Parameters
Parameter
Clock period
Symbol
Minimum
Maximum
Units
Note
T1
20.8
–
ns
Clock high/low
T2/T3
(0.45 × T1) – T4
(0.55 × T1) – T4
ns
Clock rise/fall timea
T4/T5
–
2.5
ns
Measured from 10% to 90% of
VDDIO
Input setup time
T6
5.0
–
ns
Setup time, SIMO valid to SPI_CLK
active edge
Input hold time
T7
5.0
–
ns
Hold time, SPI_CLK active edge to
SIMO invalid
Output setup time
T8
5.0
–
ns
Setup time, SOMI valid before
SPI_CLK rising
Output hold time
T9
5.0
–
ns
Hold time, SPI_CLK active edge to
SOMI invalid
CSX to clockb
–
7.86
–
ns
CSX fall to 1st rising edge
CSXa
–
–
–
ns
Last falling edge to CSX high
Clock to
a.
b.
Fmax = 48 MHz
–
Limit applies when SPI_CLK = Fmax. For slower clock speeds, longer rise/fall times are acceptable provided that the transitions are monotonic and the setup and
hold time limits are complied with.
SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-word transaction).
Document Number: 002-15057 Rev. *B
Page 100 of 110
CYW88335
18.2 JTAG Timing
Table 54. JTAG Timing Characteristics
Period
Output
Maximum
Output
Minimum
TCK
125 ns
–
–
–
–
TDI
–
–
–
20 ns
0 ns
TMS
–
–
–
20 ns
0 ns
TDO
–
100 ns
0 ns
–
–
250 ns
–
–
–
–
Signal Name
JTAG_TRST
Document Number: 002-15057 Rev. *B
Setup
Hold
Page 101 of 110
CYW88335
19. Power-Up Sequence and Timing
19.1 Sequencing of Reset and Regulator Control Signals
The CYW88335 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and
internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the
signals for various operational states (see Figure 43, Figure 44 on page 103, and Figure 45 and Figure 46 on page 104). The timing
values indicated are minimum required values; longer delays are also acceptable.
19.1.1 Description of Control Signals
■
WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the
internal CYW88335 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW88335 regulators. If both the
BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT
section is in reset.
Note:
■
■ For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where
both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then
there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.
■
The CYW88335 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC
and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO
accesses.
■
Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high. BT_REG_ON can be driven
low 100 ms after WL_REG_ON goes high.
■
VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO
should NOT be present first or be held high before VBAT is high.
Document Number: 002-15057 Rev. *B
Page 102 of 110
CYW88335
19.1.2 Control Signal Timing Diagrams
Figure 43. WLAN = ON, Bluetooth = ON
32.678 kHz
Sleep Clock
90% of VH
VBAT*
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high
before VBAT is high.
Figure 44. WLAN = OFF, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT*
VDDIO
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Document Number: 002-15057 Rev. *B
Page 103 of 110
CYW88335
Figure 45. WLAN = ON, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT*
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
100 ms
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
3. Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high. BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high.
Figure 46. WLAN = OFF, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT*
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .
Document Number: 002-15057 Rev. *B
Page 104 of 110
CYW88335
20. Package Information
20.1 Package Thermal Characteristics
Table 55. Package Thermal Characteristicsa
Characteristic
WLBGA
JA (°C/W) (value in still air)
JB (°C/W)
JC (°C/W)
0.98
JT (°C/W)
3.30
32.9
2.56
JB (°C/W)
9.85
Maximum Junction Temperature Tj (°C)
125
Maximum Power Dissipation (W)
1.119
a.
No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and P = specified power
maximum continuous power dissipation.
20.2 Junction Temperature Estimation and PSIJT Versus THETAJC
Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using
the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is
dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom
and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation
for calculating the device junction temperature is:
TJ = TT + P x JT
Where:
■
TJ = Junction temperature at steady-state condition (°C)
■
TT = Package case top center temperature at steady-state condition (°C)
■
P = Device power dissipation (Watts)
■
JT = Package thermal characteristics; no airflow (°C/W)
20.3 Environmental Characteristics
For environmental characteristics data, see Table 25 on page 65.
Document Number: 002-15057 Rev. *B
Page 105 of 110
CYW88335
21. Mechanical Information
Figure 47. 145-Ball WLBGA Package Mechanical Information
Document Number: 002-15057 Rev. *B
Page 106 of 110
CYW88335
Figure 48. WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up
Note: No top-layer metal is allowed in keep-out areas.
Document Number: 002-15057 Rev. *B
Page 107 of 110
CYW88335
22. Ordering Information
Part Number
Package
CYW88335L2CUBGa
145 ball WLBGA (4.87 mm × 5.413
mm, 0.4 mm pitch)
a.
Operating Ambient Temperature
Description
Dual-band 2.4 GHz and 5 GHz WLAN
–40°C to +85°C
+ BT 4.1 for Automotive Applications
CYW88335L2CUBG offers an updated solder ball composition to improve thermal cycling performance. Assembly processes are not affected. Form, fit, and
function are unchanged.
23. References
The references in this section may be used in conjunction with this document.
Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal (CSP) and
Downloads & Support site (see IoT Resources).
For Cypress documents, replace the “xx” in the document number with the largest number available in the repository to
ensure that you have the most current version of the document.
Document (or Item) Name
[1]
Bluetooth MWS Coexistence 2-wire Transport Interface Specification
Document Number: 002-15057 Rev. *B
Number
Source
–
www.bluetooth.com
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CYW88335
Document History
Document Title: CYW88335 Single-Chip 5G Wi-Fi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 for
Automotive Applications
Document Number: 002-15057
Revision
ECN
Orig. of
Change
Submission
Date
**
–
–
09/23/2015
*A
5461640
UTSV
10/20/2016
*B
5730057
AESATMP7 05/08/2017
Document Number: 002-15057 Rev. *B
Description of Change
88335-DS100-R:
Initial release
Updated to Cypress template
Updated Cypress Logo and Copyright.
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CYW88335
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110
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 002-15057 Rev. *B
Revised May 8, 2017
Page 110 of 110
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