CY14B101LA-SP25XI

CY14B101LA CY14B101NA 1-Mbit (128 K × 8/64 K × 16) nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 20 ns, 25 ns, and 45 ns access times Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16 (CY14B101NA) Hands off automatic STORE on power-down with only a small capacitor STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or AutoStore on power-down RECALL to SRAM initiated by software or power-up Infinite read, write, and RECALL cycles 1 million STORE cycles to QuantumTrap 20 year data retention Single 3 V +20% to –10% operation Industrial temperature ■ Packages ❐ 32-pin small-outline integrated circuit (SOIC) ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-pin shrink small-outline package (SSOP) ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS) compliant Functional Description The Cypress CY14B101LA/CY14B101NA is a fast static RAM (SRAM), with a nonvolatile element in each memory cell. The memory is organized as 128 K bytes of 8 bits each or 64 K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. Logic Block Diagram [1, 2, 3] A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 R O W D E C O D E R Quatrum Trap 1024 X 1024 STORE RECALL STATIC RAM ARRAY 1024 X 1024 STORE/RECALL CONTROL HSB VCC VCAP POWER CONTROL SOFTWARE DETECT A14 - A2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 A1 A2 A3 A4 A10 A11 CE BLE I N P U T B U F F E R S COLUMN I/O COLUMN DEC OE WE BHE Notes 1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. Cypress Semiconductor Corporation Document #: 001-42879 Rev. *L • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 14, 2011 [+] Feedback CY14B101LA CY14B101NA Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 5 Device Operation .............................................................. 6 SRAM Read ....................................................................... 6 SRAM Write ....................................................................... 6 AutoStore Operation ........................................................ 6 Hardware STORE Operation ............................................ 6 Hardware RECALL (Power-up) ........................................ 7 Software STORE ............................................................... 7 Software RECALL ............................................................. 7 Preventing AutoStore ....................................................... 8 Data Protection ................................................................. 8 Noise Considerations ....................................................... 8 Best Practices ................................................................... 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 DC Electrical Characteristics ........................................ 10 Data Retention and Endurance ..................................... 11 Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 AC Test Loads ................................................................ 11 AC Test Conditions ........................................................ 11 AC Switching Characteristics ....................................... 12 SRAM Read Cycle .................................................... 12 SRAM Write Cycle ..................................................... 12 Switching Waveforms .................................................... 12 AutoStore/Power-Up RECALL ....................................... 15 Switching Waveforms .................................................... 15 Software Controlled STORE/RECALL Cycle ................ 16 Switching Waveforms .................................................... 16 Hardware STORE Cycle ................................................. 17 Switching Waveforms .................................................... 17 Truth Table For SRAM Operations ................................ 18 Ordering Information ...................................................... 19 Ordering Code Definitions ......................................... 20 Package Diagrams .......................................................... 21 Acronyms ........................................................................ 25 Document Conventions ............................................. 25 Units of Measure ....................................................... 25 Document History Page ................................................. 26 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC Solutions ......................................................... 28 Document #: 001-42879 Rev. *L Page 2 of 28 [+] Feedback CY14B101LA CY14B101NA Pinouts Figure 1. Pin Diagram – 44-pin TSOP II NC [7] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC [6] NC [5] NC [4] NC A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC [5] [4] NC A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 44-pin TSOP II (× 8) 44-pin TSOP II (× 16) [8] Top View (not to scale) Top View (not to scale) Figure 2. Pin Diagram – 48-pin SSOP and 32-pin SOIC VCAP A16 A14 A12 A7 A6 A5 NC A4 NC NC NC VSS NC NC DQ0 A3 A2 A1 A0 DQ1 DQ2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15 HSB WE A13 A8 A9 NC A11 NC NC NC VSS NC NC DQ6 OE A10 CE DQ7 DQ5 DQ4 DQ3 VCC 48-pin SSOP (×8) 32-pin SOIC Top View (not to scale) (×8) (x8) Top View (not to scale) Notes 4. Address expansion for 2-Mbit. NC pin not connected to die. 5. Address expansion for 4-Mbit. NC pin not connected to die. 6. Address expansion for 8-Mbit. NC pin not connected to die. 7. Address expansion for 16-Mbit. NC pin not connected to die. 8. HSB pin is not available in 44-pin TSOP II (× 16) package. Document #: 001-42879 Rev. *L Page 3 of 28 [+] Feedback CY14B101LA CY14B101NA Pinouts (continued) Figure 3. 48-ball FBGA and 54-pin TSOP II 48-FBGA (x8) Top View (not to scale) 1 NC NC DQ0 VSS VCC DQ3 NC 2 OE NC NC DQ1 DQ2 NC HSB 3 A0 A3 A5 [9] NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC DQ5 DQ6 NC WE A11 6 NC NC DQ4 VCC VSS DQ7 NC NC [11] A B C D E F G H NC [12] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC VCAP A14 A 12 A9 [10] A8 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 54 - TSOP II (x16) Top View (not to scale) HSB NC [11] [10] NC [9] NC A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC Notes 9. Address expansion for 2-Mbit. NC pin not connected to die. 10. Address expansion for 4-Mbit. NC pin not connected to die. 11. Address expansion for 8-Mbit. NC pin not connected to die. 12. Address expansion for 16-Mbit. NC pin not connected to die. Document #: 001-42879 Rev. *L Page 4 of 28 [+] Feedback CY14B101LA CY14B101NA Pin Definitions Pin Name A0–A16 A0–A15 DQ0–DQ7 DQ0–DQ15 WE CE OE BHE BLE VSS VCC HSB[13] I/O Type Input Input/Output Input Input Input Input Input Ground Description Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration. Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration. Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation. Bidirectional Data I/O Lines for × 16 configuration. Used as input or output lines depending on operation. Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. Byte High Enable, Active LOW. Controls DQ15–DQ8. Byte Low Enable, Active LOW. Controls DQ7–DQ0. Ground for the device. Must be connected to the ground of the system. Power supply Power supply inputs to the device. 3.0 V +20%, –10% Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress. When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. No connect No connect. This pin is not connected to the die. VCAP NC Note 13. HSB pin is not available in 44-pin TSOP II (× 16) package. Document #: 001-42879 Rev. *L Page 5 of 28 [+] Feedback CY14B101LA CY14B101NA Device Operation The CY14B101LA/CY14B101NA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B101LA/CY14B101NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. Refer to the Truth Table For SRAM Operations on page 18 for a complete description of read and write modes. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 8. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the store. This corrupts the data stored in nvSRAM. Figure 4 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 10 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 4. AutoStore Mode VCC SRAM Read The CY14B101LA/CY14B101NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0–16 or A0–15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. 0.1 uF 10 kOhm VCC SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–15 are written into the memory if the data is valid tSD before the end of a WE-controlled write or before the end of a CE-controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. WE VCAP VCAP VSS AutoStore Operation The CY14B101LA/CY14B101NA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by HSB; Software STORE activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101LA/CY14B101NA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note 14. HSB pin is not available in 44-pin TSOP II (× 16) package. Hardware STORE Operation The CY14B101LA/CY14B101NA provides the HSB[14] pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101LA/CY14B101NA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. Document #: 001-42879 Rev. *L Page 6 of 28 [+] Feedback CY14B101LA CY14B101NA SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B101LA/CY14B101NA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B101LA/CY14B101NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Hardware RECALL (Power-up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on power up, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B101LA/CY14B101NA Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. Table 1. Mode Selection CE H L L L WE X H L H OE X L X L BHE, BLE[15] X L L X A15–A0[16] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Mode Not selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable I/O Output high Z Output data Input data Output data Output data Output data Output data Output data Output data Power Standby Active Active Active[17] Notes 15. BHE and BLE are applicable for x16 configuration only. 16. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are do not care. 17. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document #: 001-42879 Rev. *L Page 7 of 28 [+] Feedback CY14B101LA CY14B101NA Table 1. Mode Selection (continued) CE L WE H OE L BHE, BLE[15] X A15–A0[16] 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output high Z Output data Output data Output data Output data Output data Output high Z Power Active[18] L H L X Active ICC2[18] L H L X Active[18] Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or reenabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled. Data Protection The CY14B101LA/CY14B101NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B101LA/CY14B101NA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Noise Considerations Refer to CY application note AN1064. Note 18. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document #: 001-42879 Rev. *L Page 8 of 28 [+] Feedback CY14B101LA CY14B101NA Best Practices nvSRAM products have been used effectively for over 27 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ ■ The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. ■ Document #: 001-42879 Rev. *L Page 9 of 28 [+] Feedback CY14B101LA CY14B101NA Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time: At 150 C ambient temperature ...................... 1000 h At 85 C ambient temperature .................... 20 Years Ambient temperature with power applied .................................. –55 C to + 150 C Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V Voltage applied to outputs in High Z state .................................... –0.5 V to VCC + 0.5 V Input voltage ....................................... –0.5 V to VCC + 0.5 V Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 Seconds) ......................................... +260 C DC output current (1 output at a time, 1s duration) .... 15 mA Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Latch up current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40 C to +85 C VCC 2.7 V to 3.6 V DC Electrical Characteristics Over the Operating Range (VCC = 2.7 V to 3.6 V) Parameter VCC ICC1 Description Power supply voltage Average VCC current tRC = 20 ns tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) Test Conditions Min 2.7 – Typ [19] 3.0 – Max 3.6 70 70 52 Unit V mA mA mA ICC2 ICC3 ICC4 ISB Average VCC current during STORE All inputs don’t care, VCC = Max Average current for duration tSTORE Average VCC current at tRC = 200 ns, VCC(Typ), 25 °C Average VCAP current during AutoStore cycle VCC standby current All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA) All inputs don’t care. Average current for duration tSTORE CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL – – – 35 10 – mA mA – – – – 5 5 mA mA IIX[20] IOZ VIH VIL VOH VOL VCAP[21] Input leakage current (except HSB) VCC = Max, VSS < VIN < VCC Input leakage current (for HSB) Off-state output leakage current Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Storage capacitor IOUT = –2 mA IOUT = 4 mA Between VCAP pin and VSS, 5 V rated –1 –100 –1 2.0 VSS – 0.5 2.4 – 61 – – – – – – – 68 +1 +1 +1 VCC + 0.5 0.8 – 0.4 180 µA µA µA V V V V µF Notes 19. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested. 20. The HSB pin has IOUT = -2 µA for VOH of 2.4 V when both active high and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. 21. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. Document #: 001-42879 Rev. *L Page 10 of 28 [+] Feedback CY14B101LA CY14B101NA Data Retention and Endurance Over the Operating Range Parameter DATAR NVC Data retention Nonvolatile STORE operations Description Min 20 1,000 Unit Years K Capacitance Parameter[22] CIN COUT Description Input capacitance (except BHE, BLE and HSB) Input capacitance (for BHE, BLE and HSB) Output capacitance (except HSB) Output capacitance (for HSB) Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(Typ) Max 7 8 7 8 Unit pF pF pF pF Thermal Resistance Parameter[22] Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 54-pin TSOP II 36.4 10.13 48-pin SSOP 37.47 24.71 48-ball FBGA 48.19 6.5 44-pin TSOP II 41.74 11.90 32-pin SOIC 41.55 24.43 Unit C/W C/W JA JC AC Test Loads Figure 5. AC Test Loads 3.0 V OUTPUT 30 pF 577  R1 R2 789  3.0 V OUTPUT 5 pF 577  R1 for tristate specs R2 789  AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.5 V Note 22. These parameters are guaranteed by design and are not tested. Document #: 001-42879 Rev. *L Page 11 of 28 [+] Feedback CY14B101LA CY14B101NA AC Switching Characteristics Over the Operating Range Parameters [23] Description Cypress Alt Parameter Parameter SRAM Read Cycle tACE tACS Chip enable access time tRC Read cycle time tRC[24] tAA[25] tDOE tOHA[25] tLZCE[26, 27] tHZCE[26, 27] tLZOE[26, 27] tHZOE[26, 27] tPU[26] tPD[26] tDBE[[26] tLZBE[26] tHZBE[26] tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Byte enable to data valid Byte enable to output active Byte disable to output inactive Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write Byte enable to end of write 20 ns Min – 20 – – 3 3 – 0 – 0 – – 0 – 20 15 15 8 0 15 0 0 – 3 15 Max 20 – 20 10 – – 8 – 8 – 20 10 – 8 – – – – – – – – 8 – – 25 ns Min – 25 – – 3 3 – 0 – 0 – – 0 – 25 20 20 10 0 20 0 0 – 3 20 Max 25 – 25 12 – – 10 – 10 – 25 12 – 10 – – – – – – – – 10 – – 45 ns Min – 45 – – 3 3 – 0 – 0 – – 0 – 45 30 30 15 0 30 0 0 – 3 30 Max 45 45 20 – – 15 – 15 – 45 20 15 – – – – – – – – 15 – – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SRAM Write Cycle tWC tWC tPWE tWP tSCE tCW tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR tHZWE[26, 27, 28] tWZ tLZWE[26, 27] tBW tOW - Switching Waveforms Figure 6. SRAM Read Cycle #1 (Address Controlled) [24, 25, 29] tRC Address Address Valid tAA Data Output Previous Data Valid tOHA Notes 23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 5 on page 11. 24. WE must be HIGH during SRAM read cycles. 25. Device is continuously selected with CE, OE, and BHE/BLE LOW. 26. These parameters are guaranteed by design and are not tested. 27. Measured ±200 mV from steady state output voltage. 28. If WE is low when CE goes low, the outputs remain in the high impedance state. 29. HSB must remain HIGH during Read and Write cycles. Output Data Valid Document #: 001-42879 Rev. *L Page 12 of 28 [+] Feedback CY14B101LA CY14B101NA Switching Waveforms (continued) Figure 7. SRAM Read Cycle #2 (CE and OE Controlled) [30, 31, 32] Address Address Valid tRC tACE CE tAA tLZCE OE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance tPU ICC Standby Active Output Data Valid tPD tDOE tHZBE tHZOE tHZCE Figure 8. SRAM Write Cycle #1 (WE Controlled) [30, 32, 33, 34] tWC Address Address Valid tSCE CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input tHZWE Data Output Previous Data tHD Input Data Valid tLZWE High Impedance tHA Notes 30. BHE and BLE are applicable for × 16 configuration only. 31. WE must be HIGH during SRAM read cycles. 32. HSB must remain HIGH during Read and Write cycles. 33. CE or WE must be > VIH during address transitions. 34. If WE is low when CE goes low, the outputs remain in the high impedance state. Document #: 001-42879 Rev. *L Page 13 of 28 [+] Feedback CY14B101LA CY14B101NA Switching Waveforms (continued) Figure 9. SRAM Write Cycle #2 (CE Controlled) [35, 36, 37, 38] tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA Figure 10. SRAM Write Cycle #3 (BHE and BLE Controlled) [35, 36, 37, 38] tWC Address tSCE CE tSA BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output tBW tHA Address Valid Notes 35. BHE and BLE are applicable for × 16 configuration only. 36. If WE is low when CE goes low, the outputs remain in the high impedance state. 37. HSB must remain HIGH during Read and Write cycles. 38. CE or WE must be > VIH during address transitions. Document #: 001-42879 Rev. *L Page 14 of 28 [+] Feedback CY14B101LA CY14B101NA AutoStore/Power-Up RECALL Over the Operating Range Parameter tHRECALL[39] tSTORE tDELAY [40] [41] Description Power-Up RECALL duration STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level VCC rise time HSB output disable voltage HSB to output active time HSB High active time 20 ns Min – – – – 150 – – – Max 20 8 20 2.65 – 1.9 5 500 Min – – – – 150 – – – 25 ns Max 20 8 25 2.65 – 1.9 5 500 Min – – – – 150 – – – 45 ns Max 20 8 25 2.65 – 1.9 5 500 Unit ms ms ns V µs V µs ns VSWITCH tVCCRISE [42] VHDIS[42] tLZHSB[42] tHHHD[42] Switching Waveforms Figure 11. AutoStore or Power-Up RECALL [43] VCC VSWITCH VHDIS t VCCRISE 44 tHHHD Note 40 tSTORE tHHHD Note 40 tSTORE 44 Note HSB OUT Note tDELAY AutoStore tLZHSB tDELAY tLZHSB POWERUP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL tHRECALL tHRECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 39. tHRECALL starts from the time VCC rises higher than VSWITCH. 40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 41. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 42. These parameters are guaranteed by design and are not tested. 43. Read and Write cycles are ignored during STORE, RECALL, and while VCC is lower than VSWITCH. 44. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document #: 001-42879 Rev. *L Page 15 of 28 [+] Feedback CY14B101LA CY14B101NA Software Controlled STORE/RECALL Cycle Over the Operating Range Parameter[45, 46] tRC tSA tCW tHA tRECALL Description STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration Min 20 0 15 0 – 20 ns Max – – – – 200 Min 25 0 20 0 – 25 ns Max – – – – 200 Min 45 0 30 0 – 45 ns Max – – – – 200 Unit ns ns ns ns µs Switching Waveforms Figure 12. CE and OE Controlled Software STORE/RECALL Cycle [46] tRC Address tSA CE tSA OE tHHHD HSB (STORE only) DQ (DATA) tLZCE tHZCE t DELAY Note 47 tRC Address #6 tCW Address #1 tCW tHA tHA tHA tHA tLZHSB High Impedance tSTORE/tRECALL RWI Figure 13. AutoStore Enable/Disable Cycle tRC Address tSA CE tSA Address #1 tCW tRC Address #6 tCW tHA tHA tHA tHA OE tHZCE tSS Note 47 tLZCE DQ (DATA) t DELAY Notes 45. The software sequence is clocked with CE controlled or OE controlled reads. 46. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles. 47 DQ d h ih d bi lid b h i di bl d i Document #: 001-42879 Rev. *L Page 16 of 28 [+] Feedback CY14B101LA CY14B101NA Hardware STORE Cycle Over the Operating Range Parameter tDHSB tPHSB tSS [48, 49] Description HSB to output active time when write latch not set Hardware STORE pulse width Soft sequence processing time 20 ns Min – 15 – Max 20 – 100 Min – 15 – 25 ns Max 25 – 100 Min – 15 – 45 ns Max 25 – 100 Unit ns ns s Switching Waveforms Figure 14. Hardware STORE Cycle [50] Write latch set tPHSB HSB (IN) tSTORE tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI tHHHD Write latch not set tPHSB HSB (IN) HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. tDELAY tDHSB tDHSB HSB (OUT) RWI Figure 15. Soft Sequence Processing [48, 49] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 Address #6 tCW tSS CE VCC Notes 48. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 49. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 50. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. Document #: 001-42879 Rev. *L Page 17 of 28 [+] Feedback CY14B101LA CY14B101NA Truth Table For SRAM Operations HSB must remain HIGH for SRAM operations Table 2. Truth Table for × 8 Configuration CE H L L L WE X H H L OE X L H X High Z Data Out (DQ0–DQ7); High Z Data in (DQ0–DQ7); Inputs/Outputs[51] Read Output disabled Write Mode Deselect/Power-down Standby Active Active Active Power Table 3. Truth Table for × 16 Configuration CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE[52] X H L H L L H L L H L BLE[52] X H L L H L L H L L H Inputs/Outputs[51] High Z High Z Data Out (DQ0–DQ15) Data Out (DQ0–DQ7); DQ8–DQ15 in High Z Data Out (DQ8–DQ15); DQ0–DQ7 in High Z High Z High Z High Z Data In (DQ0–DQ15) Data In (DQ0–DQ7); DQ8–DQ15 in High Z Data In (DQ8–DQ15); DQ0–DQ7 in High Z Mode Deselect/Power-down Output disabled Read Read Read Output disabled Output disabled Output disabled Write Write Write Standby Active Active Active Active Active Active Active Active Active Active Power Notes 51. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 52. BHE and BLE are applicable for × 16 configuration only. Document #: 001-42879 Rev. *L Page 18 of 28 [+] Feedback CY14B101LA CY14B101NA Ordering Information Speed (ns) 20 25 Ordering Code CY14B101LA-ZS20XIT CY14B101LA-ZS20XI CY14B101LA-SZ25XIT CY14B101LA-SZ25XI CY14B101LA-ZS25XIT CY14B101LA-ZS25XI CY14B101LA-SP25XIT CY14B101LA-SP25XI CY14B101NA-ZS25XIT CY14B101NA-ZS25XI 45 CY14B101LA-SZ45XIT CY14B101LA-SZ45XI CY14B101LA-ZS45XIT CY14B101LA-ZS45XI CY14B101LA-SP45XIT CY14B101LA-SP45XI CY14B101LA-BA45XIT CY14B101LA-BA45XI CY14B101NA-ZS45XIT CY14B101NA-ZS45XI All the above parts are Pb-free. Package Diagram 51-85087 51-85087 51-85127 51-85127 51-85087 51-85087 51-85061 51-85061 51-85087 51-85087 51-85127 51-85127 51-85087 51-85087 51-85061 51-85061 51-85128 51-85128 51-85087 51-85087 Package Type 44-pin TSOP II 44-pin TSOP II 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 44-pin TSOP II 44-pin TSOP II 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 48-ball FBGA 48-ball FBGA 44-pin TSOP II 44-pin TSOP II Operating Range Industrial Document #: 001-42879 Rev. *L Page 19 of 28 [+] Feedback CY14B101LA CY14B101NA Ordering Code Definitions CY 14 B 101 L A - ZS 20 X I T Option: T - Tape and Reel Blank - Std. Pb-free Package: SZP - 32 SOIC ZSP - 44 TSOP II SPP - 48 SSOP BAP - 48 FBGA ZSP - 54 TSOP II Temperature: I - Industrial (-40 to 85 C) Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns Data Bus: L-×8 N - × 16 Die revision: Blank - No Rev A - First Rev Voltage: B - 3.0 V Density: 101 - 1 Mb 14 - nvSRAM Cypress Document #: 001-42879 Rev. *L Page 20 of 28 [+] Feedback CY14B101LA CY14B101NA Package Diagrams Figure 16. 32-pin SOIC (300 Mil), 51-85127 51-85127 *B Figure 17. 44-pin TSOP II, 51-85087 51-85087 *C Document #: 001-42879 Rev. *L Page 21 of 28 [+] Feedback CY14B101LA CY14B101NA Package Diagrams (continued) Figure 18. 48-pin SSOP (300 Mils), 51-85061 51-85061 *D Document #: 001-42879 Rev. *L Page 22 of 28 [+] Feedback CY14B101LA CY14B101NA Package Diagrams (continued) Figure 19. 48-ball FBGA (6 × 10 × 1.2 mm), 51-85128 51-85128 *F Document #: 001-42879 Rev. *L Page 23 of 28 [+] Feedback CY14B101LA CY14B101NA Package Diagrams (continued) Figure 20. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm), 51-85160 51-85160 *A Document #: 001-42879 Rev. *L Page 24 of 28 [+] Feedback CY14B101LA CY14B101NA Acronyms Acronym BHE BLE CE CMOS EIA FBGA HSB I/O nvSRAM OE RoHS RWI SOIC SRAM SSOP TSOP WE byte high enable byte low enable chip enable complementary metal oxide semiconductor electronic industries alliance fine-pitch ball grid array hardware store busy input/output non-volatile static random access memory output enable restriction of hazardous substances read and write inhibited small outline integrated circuit static random access memory shrink small outline package thin small outline package write enable Description Document Conventions Units of Measure Symbol °C Hz kHz k MHz A F s mA ms ns  % pF V W degree Celsius Hertz kilo Hertz kilo ohms Mega Hertz micro Amperes micro Farads micro seconds milli Amperes milli seconds nano seconds ohms percent pico Farads Volts Watts Unit of Measure Document #: 001-42879 Rev. *L Page 25 of 28 [+] Feedback CY14B101LA CY14B101NA Document History Page Document Title: CY14B101LA/CY14B101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM Document Number: 001-42879 Orig. of SubmisRev. ECN No. Description of Change Change sion Date ** 2050747 UNC / 01/31/08 New Datasheet PYRS *A 2607447 GVCH / 11/14/08 Removed 15 ns access speed AESA Updated “Features” Updated Logic block diagram Added footnote 1 2, 3 and 7 Pin definition: Updated WE, HSB and NC pin description Page 4: Updated SRAM READ, SRAM WRITE, AutoStore operation description Updated Figure 4 Page 4: Updated Hardware store operation and Hardware RECALL (Powerup)description Page 4: Updated Software store and software recall description Footnote 1 and 11 referenced for Mode selection Table Added footnote 11 Updated footnote 9 and 10 Page 6: updated Data protection description Maximum Ratings:Added Max. Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed ICC2 from 6 mA to 10 mA Changed ICC3 from 15 mA to 35 mA Changed ICC4 from 6 mA to 5 mA Changed ISB from 3 mA to 5 mA Added IIX for HSB Updated ICC1, ICC3, ISB and IOZ Test conditions Changed VCAP voltage min value from 68 µF to 61 µF Added VCAP voltage max value to 180 µF Updated footnote 12 and 13 Added footnote 14 Added Data retention and Endurance Table Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages Updated Input Rise and Fall time in AC test Conditions Referenced footnote 17 to tOHA parameter Updated All switching waveforms Updated footnote 17 Added footnote 20 Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled) Changed tSTORE max value from 12.5 ms to 8 ms Updated tDELAY value Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 24 Added footnote 26 and 27 Software controlled STORE/RECALL Table: Changed tAS to tSA Changed tGHAX to tHA Changed tHA value from 1 ns to 0 ns Added Figure 13 Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70 µs to 100 µs Added truth table for SRAM operations Updated ordering information and part numbering nomenclature *B 2654484 GVCH / 02/05/09 Changed the datasheet from Advance information to Preliminary PYRS Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZWE and tHZWE Updated Figure 12 Document #: 001-42879 Rev. *L Page 26 of 28 [+] Feedback CY14B101LA CY14B101NA Document History Page (continued) Document Title: CY14B101LA/CY14B101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM Document Number: 001-42879 Orig. of SubmisRev. ECN No. Description of Change Change sion Date *C 2733909 GVCH / 07/09/09 Removed 48-ball FBGA package and added 54-pin TSOP II Package AESA Corrected typo error in pin diagram of 48-pin SSOP Page 4; Added note to AutoStore Operation description Page 4; Updated Hardware STORE (HSB) Operation description Page 5; Updated Software STORE Operation description Added best practices Updated VHDIS parameter description Updated tDELAY parameter description Updated footnote 24 and added footnote 29 *D 2757348 GVCH 08/28/09 Moved datasheet status from Preliminary to Final Removed commercial temperature related specs Updated thermal resistance values for all the packages *E 2793420 GVCH 10/27/09 Updated 48-pin SSOP package diagram *F 2839453 GVCH / 01/06/10 Changed STORE cycles to QuantumTrap from 200 K to 1 Million PYRS Added Contents *G 2894534 GVCH 03/17/10 Removed inactive parts from Ordering Information table. Updated links in Sales, Solutions, and Legal Information. Updated Package Diagrams. *H 2922854 GVCH 04/26/10 Pin Definitions: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Table 1: Added more clarity on BHE/BLE pin operation Updated HSB pin operation in Figure 11 Updated footnote 44 Updated package diagram 51-85087 *I 2958648 GVCH 06/22/10 Added 48-Ball FBGA package related information Updated package diagram 51-85128 Updated template and added Acronym table *J 3074645 GVCH 10/29/10 48 FBGA package: 16 Mb address expansion is not supported Removed inactive parts from Ordering Information table. CY14B101NA-ZS20XIT, CY14B101NA-ZS20XI Added Document Conventions table *K 3134300 GVCH 01/11/2011 Updated style format Updated input capacitance for BHE and BLE pin Updated input and output capacitance for HSB pin Fixed typo in Figure 11 *L 3313245 GVCH 07/14/2011 Updated DC Electrical Characteristics (Added Note 21 and referred the same note in VCAP parameter). Updated Thermal Resistance (JA and JC values for 48-ball FBGA package). Updated AC Switching Characteristics (Added Note 23 and referred the same note in Parameters). Updated Package Diagrams. Document #: 001-42879 Rev. *L Page 27 of 28 [+] Feedback CY14B101LA CY14B101NA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-42879 Rev. *L Revised July 14, 2011 Page 28 of 28 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback