CY14E256Q

CY14C256Q CY14B256Q CY14E256Q 256-Kbit (32 K × 8) SPI nvSRAM 256-Kbit (32 K × 8) SPI nvSRAM Features ■ ■ 256-Kbit nonvolatile static random access memory (nvSRAM) internally organized as 32 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL) ❐ Support automatic STORE on power-down with a small capacitor (except for CY14X256Q1A) Industry standard configurations ❐ Operating voltages: • CY14C256Q: VCC = 2.4 V to 2.6 V • CY14B256Q: VCC = 2.7 V to 3.6 V • CY14E256Q: VCC = 4.5 V to 5.5 V ❐ Industrial temperature ❐ 8- and 16-pin small outline integrated circuit (SOIC) package ❐ Restriction of hazardous substances (RoHS) compliant Functional Overview The Cypress CY14X256Q combines a 256-Kbit nvSRAM[1] with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X256Q1A). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction. ■ High reliability ❐ Infinite read, write, and RECALL cycles ❐ 1million STORE cycles to QuantumTrap ❐ Data retention: 20 years at 85 C ■ 40 MHz, and 104 MHz High speed serial peripheral interface (SPI) ❐ 40 MHz clock rate SPI write and read with zero cycle delay ❐ 104 MHz clock rate SPI write and SPI read (with special fast read instructions) ❐ Supports SPI mode 0 (0,0) and mode 3 (1,1) ■ SPI access to special functions ❐ Nonvolatile STORE/RECALL ❐ 8-byte serial number ❐ Manufacturer ID and Product ID ❐ Sleep mode Write protection ❐ Hardware protection using Write Protect (WP) pin ❐ Software protection using Write Disable instruction ❐ Software block protection for 1/4, 1/2, or entire array Low power consumption ❐ Average active current of 3 mA at 40 MHz operation ❐ Average standby mode current of 150 A ❐ Sleep mode current of 8 A VCC VCAP Configuration Feature AutoStore Software STORE Hardware STORE CY14X256Q1A CY14X256Q2A CY14X256Q3A No Yes No Yes Yes No Yes Yes Yes ■ ■ Logic Block Diagram Serial Number 8x8 Manufacture ID/ Product ID Power Control Block SLEEP SI CS SCK WP SO SPI Control Logic Write Protection Instruction decoder QuantrumTrap 32 K x 8 SRAM 32 K x 8 STORE RECALL RDSN/WRSN/RDID READ/WRITE STORE/RECALL/ASENB/ASDISB Memory Data & Address Control WRSR/RDSR/WREN Status Register Note 1. This device will be referred to as nvSRAM throughout the document. Cypress Semiconductor Corporation Document #: 001-65282 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 3, 2011 CY14C256Q CY14B256Q CY14E256Q Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 SRAM Write ................................................................. 4 SRAM Read ................................................................ 4 STORE Operation ....................................................... 4 AutoStore Operation .................................................... 5 Software STORE Operation ........................................ 5 Hardware STORE and HSB pin Operation ................. 5 RECALL Operation ...................................................... 5 Hardware RECALL (Power-Up) .................................. 5 Software RECALL ....................................................... 5 Disabling and Enabling AutoStore ............................... 6 Serial Peripheral Interface ............................................... 6 SPI Overview ............................................................... 6 SPI Modes ................................................................... 7 SPI Operating Features .................................................... 8 Power-Up .................................................................... 8 Power On Reset .......................................................... 8 Power-Down ................................................................ 8 Active Power and Standby Power Modes ................... 8 SPI Functional Description .............................................. 9 Status Register ............................................................... 10 Read Status Register (RDSR) Instruction ................. 10 Fast Read Status Register (FAST_RDSR) Instruction ......................................................................... 10 Write Status Register (WRSR) Instruction ................ 10 Write Protection and Block Protection ......................... 12 Write Enable (WREN) Instruction .............................. 12 Write Disable (WRDI) Instruction .............................. 12 Block Protection ........................................................ 12 Hardware Write Protection (WP) ............................... 12 Memory Access .............................................................. 13 Read Sequence (READ) Instruction .......................... 13 Fast Read Sequence (FAST_READ) Instruction ...... 13 Write Sequence (WRITE) Instruction ........................ 13 nvSRAM Special Instructions ........................................ 15 Software STORE (STORE) Instruction ..................... 15 Software RECALL (RECALL) Instruction .................. 15 AutoStore Enable (ASENB) Instruction ..................... 15 AutoStore Disable (ASDISB) Instruction ................... 15 Special Instructions ....................................................... 16 SLEEP Instruction ..................................................... 16 Serial Number ................................................................. 16 WRSN (Serial Number Write) Instruction .................. 16 RDSN (Serial Number Read) Instruction ................... 17 FAST_RDSN (Fast Serial Number Read) Instruction ......................................................................... 17 Device ID ......................................................................... 18 RDID (Device ID Read) Instruction ........................... 18 FAST_RDID (Fast Device ID Read) Instruction ........ 19 HOLD Pin Operation ................................................. 19 Best Practices ................................................................. 20 Maximum Ratings ........................................................... 21 DC Electrical Characteristics ........................................ 21 Data Retention and Endurance ..................................... 22 Capacitance .................................................................... 22 Thermal Resistance ........................................................ 22 AC Test Conditions ........................................................ 23 AC Switching Characteristics ....................................... 24 AutoStore or Power-Up RECALL .................................. 25 Software Controlled STORE and RECALL Cycles ...... 26 Hardware STORE Cycle ................................................. 27 Ordering Information ...................................................... 28 Ordering Code Definitions ......................................... 28 Package Diagrams .......................................................... 29 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Document History Page ................................................. 32 Sales, Solutions, and Legal Information ...................... 33 Worldwide Sales and Design Support ....................... 33 Products .................................................................... 33 PSoC Solutions ......................................................... 33 Document #: 001-65282 Rev. *B Page 2 of 33 CY14C256Q CY14B256Q CY14E256Q Pinouts Figure 1. Pin Diagram - 8-pin SOIC[2, 3, 4] CS 1 2 3 4 8 CY14X256Q1A 7 Top View 6 not to scale 5 VCC HOLD SCK SI CS 1 2 3 4 8 CY14X256Q2A 7 Top View 6 not to scale 5 VCC HOLD SCK SI SO WP VSS SO VCAP VSS Figure 2. Pin Diagram - 16-pin SOIC NC 1 2 3 4 5 6 7 8 16 15 CY14X256Q3A 14 Top View 13 not to scale 12 11 10 9 VCC NC VCAP SO SI SCK CS HSB NC NC NC WP HOLD NC VSS Pin Definitions Pin Name [2, 3, 4] CS SCK SI SO WP HOLD HSB I/O Type Input Input Input Output Input Input Description Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low power standby mode. Serial Clock. Runs at speeds up to a maximum of fSCK. Serial input is latched at the rising edge of this clock. Serial output is driven at the falling edge of the clock. Serial Input. Pin for input of all SPI instructions and data. Serial Output. Pin for output of data through SPI. Write Protect. Implements hardware write protection in SPI. HOLD Pin. Suspends serial operation. Input/Output Hardware STORE Busy: Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional). Input: Hardware STORE implemented by pulling this pin LOW externally. Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It must never be connected to ground. No connect No Connect: This pin is not connected to the die. Power supply Ground Power supply Power supply VCAP NC VSS VCC Notes 2. HSB pin is not available in 8-pin SOIC packages (CY14X256Q1A/CY14X256Q2A). 3. CY14X256Q1A part does not have VCAP pin and does not support AutoStore. 4. CY14X256Q2A part does not have WP pin. Document #: 001-65282 Rev. *B Page 3 of 33 CY14C256Q CY14B256Q CY14E256Q Device Operation CY14X256Q is a 256-Kbit serial (SPI) nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to the SRAM, which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence which transfers the data in parallel to the nonvolatile QuantumTrap cells. A small capacitor (VCAP) is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power-down data security. The QuantumTrap nonvolatile elements built in the reliable SONOS technology make nvSRAM the ideal choice for secure data storage. The 256-Kbit memory array is organized as 32 K words × 8 bits. The memory can be accessed through a standard SPI interface that enables very high clock speeds up to 40 MHz with zero cycle delay read and write cycles. This nvSRAM chip also supports 104 MHz SPI access speed with a special instruction for read operation. This device supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave. The device is enabled using the Chip Select (CS) pin and accessed through Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. This device provides the feature for hardware and software write protection through the WP pin and WRDI instruction respectively along with mechanisms for block write protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the Status Register. Further, the HOLD pin is used to suspend any serial communication without resetting the serial sequence. CY14X256Q uses the standard SPI opcodes for memory access. In addition to the general SPI instructions for read and write, it provides four special instructions that allow access to four nvSRAM specific functions: STORE, RECALL, AutoStore Disable (ASDISB), and AutoStore Enable (ASENB). The major benefit of nvSRAM over serial EEPROMs is that all reads and writes to nvSRAM are performed at the speed of SPI bus with zero cycle delay. Therefore, no wait time is required after any of the memory accesses. The STORE and RECALL operations need finite time to complete and all memory accesses are inhibited during this time. While a STORE or RECALL operation is in progress, the busy status of the device is indicated by the Hardware STORE Busy (HSB) pin and also reflected on the RDY bit of the Status Register. The device is available in three different pin configurations that enable you to choose a part which fits in best in their application. The feature summary is given in Table 1. Table 1. Feature Summary Feature WP VCAP HSB AutoStore Power-Up RECALL Hardware STORE Software STORE SRAM Write All writes to nvSRAM are carried out on the SRAM and do not use up any endurance cycles of the nonvolatile memory. This allows you to perform infinite write operations. A write cycle is performed through the WRITE instruction. The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode, two bytes of address, and one byte of data. Write to nvSRAM is done at SPI bus speed with zero cycle delay. The device allows burst mode writes to be performed through SPI. This enables write operations on consecutive addresses without issuing a new WRITE instruction. When the last address in memory is reached in burst mode, the address rolls over to 0x0000 and the device continues to write. The SPI write cycle sequence is defined explicitly in the Memory Access section of SPI Protocol Description. SRAM Read A read cycle is performed at the SPI bus speed. The data is read out with zero cycle delay after the READ instruction is executed. READ instruction can be used upto 40 MHz clock speed. The READ instruction is issued through the SI pin of the nvSRAM and consists of the READ opcode and two bytes of address. The data is read out on the SO pin. A speed higher than 40 MHz (up to 104 MHz) requires FAST_READ instruction. The FAST_READ instruction is issued through the SI pin of the nvSRAM and consists of the FAST_READ opcode, two bytes of address, and one dummy byte. The data is read out on the SO pin. This device allows burst mode reads to be performed through SPI. This enables reads on consecutive addresses without issuing a new READ instruction. When the last address in memory is reached in burst mode read, the address rolls over to 0x0000 and the device continues to read. The SPI read cycle sequence is defined explicitly in the Memory Access section of SPI Protocol Description. STORE Operation STORE operation transfers the data from the SRAM to the nonvolatile QuantumTrap cells. The device STOREs data to the nonvolatile cells using one of the three STORE operations: AutoStore, activated on device power-down; Software STORE, activated by a STORE instruction; and Hardware STORE, activated by the HSB. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, read/write to CY14X256Q is inhibited until the cycle is completed. The HSB signal or the RDY bit in the Status Register can be monitored by the system to detect if a STORE or Software RECALL cycle is in progress. The busy status of nvSRAM is indicated by HSB being pulled LOW or RDY bit being set to ‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. However, software initiated STORE cycles are performed regardless of whether a write operation has taken place. CY14X256Q1A CY14X256Q2A CY14X256Q3A Yes No No No Yes No Yes No Yes No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Document #: 001-65282 Rev. *B Page 4 of 33 CY14C256Q CY14B256Q CY14E256Q AutoStore Operation The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap cells during power-down. This STORE makes use of an external capacitor (VCAP) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from VCC to charge the capacitor connected to the VCAP pin. When the voltage on the VCC pin drops below VSWITCH during power-down, the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the VCAP capacitor. The AutoStore operation is not initiated if no write cycle has been performed since last RECALL. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled by issuing the AutoStore Disable instruction (AutoStore Disable (ASDISB) Instruction on page 15). If AutoStore is enabled without a capacitor on the VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the STORE. This will corrupt the data stored in nvSRAM, Status Register as well as the serial number and it will unlock the SNL bit. To resume normal functionality, the WRSR instruction must be issued to update the nonvolatile bits BP0, BP1, and WPEN in the Status Register. Figure 3 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 21 for the size of the VCAP. Note CY14X256Q1A does not support AutoStore operation. You must perform Software STORE operation by using the SPI STORE instruction to secure the data. Figure 3. AutoStore Mode VCC is completed, the SRAM is activated again for read and write operations. Hardware STORE and HSB pin Operation The HSB pin in CY14X256Q3A is used to control and acknowledge STORE operations. If no STORE or RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB pin is driven LOW, nvSRAM conditionally initiates a STORE operation after tDELAY duration. A STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for tSTORE duration or as long as HSB pin is LOW. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by an internal 100 k pull-up resistor. Note For successful last data byte STORE, a hardware STORE should be initiated at least one clock cycle after the last data bit D0 is received. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. The HSB pin must be left unconnected if not used. Note CY14X256Q1A/CY14X256Q2A do not have HSB pin. RDY bit of the SPI Status Register may be probed to determine the Ready or Busy status of nvSRAM. RECALL Operation A RECALL operation transfers the data stored in the nonvolatile QuantumTrap elements to the SRAM. A RECALL may be initiated in two ways: Hardware RECALL, initiated on power-up and Software RECALL, initiated by a SPI RECALL instruction. Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. All memory accesses are inhibited while a RECALL cycle is in progress. The RECALL operation does not alter the data in the nonvolatile elements. 0.1 uF 10 kOhm VCC CS VCAP VCAP VSS Hardware RECALL (Power-Up) During power-up, when VCC crosses VSWITCH, an automatic RECALL sequence is initiated, which transfers the content of nonvolatile memory on to the SRAM. The data would previously have been stored on the nonvolatile memory through a STORE sequence. A Power-Up RECALL cycle takes tFA time to complete and the memory access is disabled during this time. HSB pin is used to detect the ready status of the device. Software STORE Operation Software STORE enables the user to trigger a STORE operation through a special SPI instruction. STORE operation is initiated by executing STORE instruction irrespective of whether a write has been performed since the last NV operation. A STORE cycle takes tSTORE time to complete, during which all the memory accesses to nvSRAM are inhibited. The RDY bit of the Status Register or the HSB pin may be polled to find the Ready or Busy status of the nvSRAM. After the tSTORE cycle time Document #: 001-65282 Rev. *B Software RECALL Software RECALL allows you to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM. A Software RECALL is issued by using the SPI instruction for RECALL. A Software RECALL takes tRECALL time to complete during which all memory accesses to nvSRAM are inhibited. The Page 5 of 33 CY14C256Q CY14B256Q CY14E256Q controller must provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions. Disabling and Enabling AutoStore If the application does not require the AutoStore feature, it can be disabled by using the ASDISB instruction. If this is done, the nvSRAM does not perform a STORE operation at power-down. AutoStore can be re enabled by using the ASENB instruction. However, these operations are not nonvolatile and if you need this setting to survive the power cycle, a STORE operation must be performed following AutoStore Disable or Enable operation. Note CY14X256Q2A/CY14X256Q3A has AutoStore enabled from the factory. In CY14X256Q1A, VCAP pin is not present and AutoStore option is not available. The AutoStore Enable and Disable instructions to CY14X256Q1A are ignored. Note If AutoStore is disabled and VCAP is not required, then the VCAP pin must be left open. The VCAP pin must never be connected to ground. The Power-Up RECALL operation cannot be disabled in any case. master and all the communication is synchronized with this clock. SPI slave never initiates a communication on the SPI bus and acts on the instruction from the master. CY14X256Q operates as a SPI slave and may share the SPI bus with other SPI slave devices. Chip Select (CS) For selecting any slave device, the master needs to pull-down the corresponding CS pin. Any instruction can be issued to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high impedance state. Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each active Chip Select cycle. Serial Clock (SCK) Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. CY14X256Q enables SPI modes 0 and 3 for data communication. In both these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. Data Transmission - SI/SO SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as Master Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier. CY14X256Q has two separate pins for SI and SO, which can be connected with the master as shown in Figure 4 on page 7. Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission. The 256-Kbit serial nvSRAM requires a 2-byte address for any read or write operation. However, because the address is only 15-bits, it implies that the first MSB which is fed in is ignored by the device. Although this bit is ‘don’t care’, Cypress recommends that this bit is treated as 0 to enable seamless transition to higher memory densities. Serial Opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. CY14X256Q uses the standard opcodes for memory accesses. In addition to the memory accesses, it provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to Table 2 on page 9 for details. Serial Peripheral Interface SPI Overview The SPI is a four- pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. CY14X256Q provides serial access to nvSRAM through SPI interface. The SPI bus on CY14X256Q can run at speeds up to 104 MHz except READ instruction. The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on SPI bus is activated using the CS pin. The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both these modes, data is clocked into the nvSRAM on the rising edge of SCK starting from the first rising edge after CS goes active. The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS is activated the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are given below: SPI Master The SPI master device controls the operations on a SPI bus. A SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices using the CS pin. All the operations must be initiated by the master activating a slave device by pulling the CS pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. SPI Slave The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an input from the SPI Document #: 001-65282 Rev. *B Page 6 of 33 CY14C256Q CY14B256Q CY14E256Q Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin till the next falling edge of CS and the SO pin remains tri-stated. Status Register CY14X256Q has an 8-bit Status Register. The bits in the Status Register are used to configure the SPI bus. These bits are described in the Table 4 on page 10. Figure 4. System Configuration Using SPI nvSRAM SCK M OSI M IS O SCK SI SO SCK SI SO u C o n tro lle r CY14X256Q CY14X256Q CS HO LD CS HO LD CS1 HO LD 1 CS2 HO LD 2 SPI Modes CY14X256Q may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ■ ■ Figure 5. SPI Mode 0 SPI Mode 0 (CPOL=0, CPHA=0) SPI Mode 3 (CPOL=1, CPHA=1) CS 0 SCK 1 2 3 4 5 6 7 For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles, is considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 5 and Figure 6. The status of clock when the bus master is in standby mode and not transferring data is: ■ ■ SI 7 MSB 6 5 4 3 2 1 0 LSB Figure 6. SPI Mode 3 SCK remains at 0 for Mode 0 SCK remains at 1 for Mode 3 CS CPOL and CPHA bits must be set in the SPI controller for either Mode 0 or Mode 3. The device detects the SPI mode from the status of SCK pin when the device is selected by bringing the CS pin LOW. If SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3. 0 SCK 1 2 3 4 5 6 7 SI 7 MSB 6 5 4 3 2 1 0 LSB Document #: 001-65282 Rev. *B Page 7 of 33 CY14C256Q CY14B256Q CY14E256Q SPI Operating Features Power-Up Power-up is defined as the condition when the power supply is turned on and VCC crosses Vswitch voltage. During this time, the CS must be allowed to follow the VCC voltage. Therefore, CS must be connected to VCC through a suitable pull-up resistor. As a built in safety feature, CS is both edge sensitive and level sensitive. After power-up, the device is not selected until a falling edge is detected on CS. This ensures that CS must have been HIGH, before going Low to start the first operation. As described earlier, nvSRAM performs a Power-Up RECALL operation after power-up and therefore, all memory accesses are disabled for tFA duration after power-up. The HSB pin can be probed to check the Ready/Busy status of nvSRAM after powerup. The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous STORE operation. Before selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain valid until the end of the instruction transmission. Power-Down At power-down (continuous decay of VCC), when VCC drops from the normal operating voltage and below the VSWITCH threshold voltage, the device stops responding to any instruction sent to it. If a write cycle is in progress and the last data bit D0 has been received when the power goes down, it is allowed tDELAY time to complete the write. After this, all memory accesses are inhibited and a conditional AutoStore operation is performed (AutoStore is not performed if no writes have happened since the last RECALL cycle). This feature prevents inadvertent writes to nvSRAM from happening during power-down. However, to completely avoid the possibility of inadvertent writes during power-down, ensure that the device is deselected and is in standby power mode, and the CS follows the voltage applied on VCC. Power On Reset A Power On Reset (POR) circuit is included to prevent inadvertent writes. At power-up, the device does not respond to any instruction until the VCC reaches the POR threshold voltage (VSWITCH). After VCC transitions the POR threshold, the device is internally reset and performs an power-Up RECALL operation. During power-Up RECALL all device accesses are inhibited. The device is in the following state after POR: ■ ■ ■ ■ Active Power and Standby Power Modes When CS is LOW, the device is selected and is in the active power mode. The device consumes ICC current, as specified in DC Electrical Characteristics on page 21. When CS is HIGH, the device is deselected and the device goes into the standby power mode after tSB time if a STORE or RECALL cycle is not in progress. If a STORE/RECALL cycle is in progress, the device goes into the standby power mode after the STORE or RECALL cycle is completed. In the standby power mode, the current drawn by the device drops to ISB. Deselected (after power-up, a falling edge is required on CS before any instructions are started). Standby power mode Not in the HOLD condition Status Register state: ❐ Write Enable (WEN) bit is reset to ‘0’. ❐ WPEN, BP1, BP0 unchanged from previous STORE operation. Document #: 001-65282 Rev. *B Page 8 of 33 CY14C256Q CY14B256Q CY14E256Q SPI Functional Description The CY14X256Q uses an 8-bit instruction register. Instructions and their opcodes are listed in Table 2. All instructions, addresses, and data are transferred with the MSB first and start with a HIGH to LOW CS transition. There are, in all, 18 SPI Table 2. Instruction Set Instruction Category Status Register Control Instructions RDSR Status Register access FAST_RDSR WRSR Write protection and block protection SRAM Read/Write Instructions READ Memory access Special NV Instructions STORE nvSRAM special functions RECALL ASENB ASDISB Special Instructions Sleep Serial number SLEEP WRSN RDSN FAST_RDSN RDID Device ID read Reserved FAST_RDID - Reserved 1011 1001 1100 0010 1100 0011 1100 1001 1001 1111 1001 1001 0001 1110 0011 1100 0110 0000 0101 1001 0001 1001 FAST_READ WRITE 0000 0011 0000 1011 0000 0010 WREN WRDI 0000 0101 0000 1001 0000 0001 0000 0110 0000 0100 Instruction Name instructions which provide access to most of the functions in nvSRAM. Further, the WP, HOLD and HSB pins provide additional functionality driven through hardware. Opcode Operation Read Status Register Fast Status Register read - SPI clock > 40 MHz Write Status Register Set write enable latch Reset write enable latch Read data from memory array Fast read - SPI clock > 40 MHz Write data to memory array Software STORE Software RECALL AutoStore Enable AutoStore Disable Sleep mode enable Write serial number Read serial number Fast serial number read - SPI clock > 40 MHz Read manufacturer JEDEC ID and product ID Fast manufacturer JEDEC ID and product ID Read - SPI clock > 40 MHz The SPI instructions are divided based on their functionality in the following types: ❐ Status Register control instructions: • Status Register access: RDSR, FAST_RDSR and WRSR instructions • Write protection and block protection: WREN and WRDI instructions along with WP pin and WEN, BP0, and BP1 bits ❐ SRAM read/write instructions • Memory access: READ, FAST_READ and WRITE instructions ❐ Special NV instructions • nvSRAM special instructions: STORE, RECALL, ASENB, and ASDISB ❐ Special instructions • SLEEP, WRSN, RDSN, FAST_RDSN, RDID, FAST_RDID Document #: 001-65282 Rev. *B Page 9 of 33 CY14C256Q CY14B256Q CY14E256Q Status Register The Status Register bits are listed in Table 3. The Status Register consists of a Ready bit (RDY) and data protection bits BP1, BP0, WEN, and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE or Software RECALL cycle is in progress. The Status Register can be modified by WRSR instruction and read by RDSR or FAST_RDSR instruction. However, only the WPEN, BP1, and BP0 bits of the Status Register can be modified by using the WRSR instruction. The WRSR instruction has no effect on WEN and RDY bits. The Table 3. Status Register Format Bit 7 WPEN (0) Bit 6 SNL (0) Bit 5 X (0) Bit 4 X (0) default value shipped from the factory for WEN, BP0, BP1, bits 4 -5, SNL and WPEN is ‘0’. SNL (bit 6) of the Status Register is used to lock the serial number written using the WRSN instruction. The serial number can be written using the WRSN instruction multiple times while this bit is still '0'. When set to '1', this bit prevents any modification to the serial number. This bit is factory programmed to '0' and can only be written to once. After this bit is set to '1', it can never be cleared to '0'. Bit 3 BP1 (0) Bit 2 BP0 (0) Bit 1 WEN (0) Bit 0 RDY Table 4. Status Register Bit Definition Bit Bit 0 (RDY) Bit 1 (WEN) Definition Ready Write Enable Description Read only bit indicates the ready status of device to perform a memory access. This bit is set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress. WEN indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. WEN = '1' --> Write enabled WEN = '0' --> Write disabled Used for block protection. For details see Table 5 on page 12. Used for block protection. For details see Table 5 on page 12. These bits are non-writable and always return ‘0’ upon read. Set to '1' for locking serial number Bit 2 (BP0) Bit 3 (BP1) Bit 4-5 Bit 6 (SNL) Bit 7 (WPEN) Block Protect bit ‘0’ Block Protect bit ‘1’ Don’t care Serial Number Lock Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 12. Read Status Register (RDSR) Instruction The Read Status Register instruction provides access to the Status Register at SPI frequency up to 40 MHz. This instruction is used to probe the Write Enable status of the device or the Ready status of the device. RDY bit is set by the device to 1 whenever a STORE or Software RECALL cycle is in progress. The block protection and WPEN bits indicate the extent of protection employed. This instruction is issued after the falling edge of CS using the opcode for RDSR. Write Status Register (WRSR) Instruction The WRSR instruction enables the user to write to the Status Register. However, this instruction cannot be used to modify bit 0 (RDY), bit 1 (WEN) and bits 4-5. The BP0 and BP1 bits can be used to select one of four levels of block protection. Further, WPEN bit must be set to ‘1’ to enable the use of Write Protect (WP) pin. WRSR instruction is a write instruction and needs writes to be enabled (WEN bit set to ‘1’) using the WREN instruction before it is issued. The instruction is issued after the falling edge of CS using the opcode for WRSR followed by eight bits of data to be stored in the Status Register. WRSR instruction can be used to modify only bits 2, 3, 6 and 7 of the Status Register. Note In CY14X256Q, the values written to Status Register are saved to nonvolatile memory only after a STORE operation. If AutoStore is disabled (or while using CY14X256Q1A), any modifications to the Status Register must be secured by performing a Software STORE operation. Note CY14X256Q2A does not have WP pin. Any modification to bit 7 of the Status Register has no effect on the functionality of CY14X256Q2A. Fast Read Status Register (FAST_RDSR) Instruction The FAST_RDSR instruction allows you to read the Status Register at a SPI frequency above 40 MHz and up to 104 MHz (max).This instruction is used to probe the Write Enable status of the device or the Ready status of the device. RDY bit is set by the device to 1 whenever a STORE or Software RECALL cycle is in progress. The block protection and WPEN bits indicate the extent of protection employed. This instruction is issued after the falling edge of CS using the opcode for RDSR followed by a dummy byte. Document #: 001-65282 Rev. *B Page 10 of 33 CY14C256Q CY14B256Q CY14E256Q Figure 7. Read Status Register (RDSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Op-Code SI 0 0 0 0 HI-Z 0 1 0 1 0 SO D7 D6 D5 D4 D3 D2 D1 D0 MSB Data LSB Figure 8. Fast Read Status Register (FAST_RDSR) Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SCK Op-Code Dummy Byte SI 0 0 0 0 1 0 0 1 X X X X X X X X 0 SO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB Data LSB Figure 9. Write Status Register (WRSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode Data in SI 0 0 0 0 HI-Z 0 0 0 1 D7 X MSB X X D3 D2 X X LSB SO Document #: 001-65282 Rev. *B Page 11 of 33 CY14C256Q CY14B256Q CY14E256Q Write Protection and Block Protection CY14X256Q provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block protection mechanism through BP0 and BP1 pins of the Status Register. The write enable and disable status of the device is indicated by WEN bit of the Status Register. The write instructions (WRSR WRITE and WRSN) and nvSRAM special instruction (STORE, RECALL, ASENB and ASDISB) need the write to be enabled (WEN bit = ‘1’) before they can be issued. Block Protection Block protection is provided using the BP0 and BP1 pins of the Status Register. These bits can be set using WRSR instruction and probed using the RDSR instruction. The nvSRAM is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any data within the protected segment is read only. Table 5 shows the function of Block Protect bits. Table 5. Block Write Protect Bits Level 0 1 (1/4) 2 (1/2) 3 (All) Status Register Bits BP1 0 0 1 1 BP0 0 1 0 1 None 0x6000-0x7FFF 0x4000-0x7FFF 0x0000-0x7FFF Array Addresses Protected Write Enable (WREN) Instruction On power-up, the device is always in the write disable state. The following WRITE, WRSR, WRSN, or nvSRAM special instruction must therefore be preceded by a Write Enable instruction. If the device is not write enabled (WEN = ‘0’), it ignores the write instructions and returns to the standby state when CS is brought HIGH. A new CS falling edge is required to re-initiate serial communication. The instruction is issued following the falling edge of CS. When this instruction is used, the WEN bit of Status Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up. Note After completion of a write instruction (WRSR, WRITE and WRSN) or nvSRAM special instruction (STORE, RECALL, ASENB, and ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to provide protection from any inadvertent writes. Therefore, WREN instruction needs to be used before a new write instruction is issued. Figure 10. WREN Instruction CS 0 SCK SI SO 0 0 0 0 0 1 1 0 1 2 3 4 5 6 7 Hardware Write Protection (WP) The write protect pin (WP) is used to provide hardware write protection. WP pin enables all normal read and write operations when held HIGH. When the WP pin is brought LOW and WPEN bit is ‘1’, all write operations to the Status Register are inhibited. The hardware write protection function is blocked when the WPEN bit is ‘0’. This allows you to install the device in a system with the WP pin tied to ground, and still write to the Status Register. WP pin can be used along with WPEN and Block Protect bits (BP1 and BP0) of the Status Register to inhibit writes to memory. When WP pin is LOW and WPEN is set to ‘1’, any modifications to the Status Register are disabled. Therefore, the memory is protected by setting the BP0 and BP1 bits and the WP pin inhibits any modification of the Status Register bits, providing hardware write protection. Note WP going LOW when CS is still LOW has no effect on any of the ongoing write operations to the Status Register. Note CY14X256Q2A does not have WP pin and therefore does not provide hardware write protection. Table 6 summarizes all the protection features of this device Table 6. Write Protection Operation WPEN X 0 1 1 WP X X LOW HIGH WEN Protected Unprotected Blocks Blocks 0 1 1 1 Protected Protected Protected Protected Protected Writable Writable Writable Status Register Protected Writable Protected Writable HI-Z Write Disable (WRDI) Instruction Write Disable instruction disables the write by clearing the WEN bit to ‘0’ in order to protect the device against inadvertent writes. This instruction is issued following the falling edge of CS followed by opcode for WRDI instruction. The WEN bit is cleared on the rising edge of CS following a WRDI instruction. Figure 11. WRDI Instruction CS 0 SCK SI SO 0 0 0 0 0 1 0 0 1 2 3 4 5 6 7 HI-Z Document #: 001-65282 Rev. *B Page 12 of 33 CY14C256Q CY14B256Q CY14E256Q Memory Access All memory accesses are done using the READ and WRITE instructions. These instructions cannot be used while a STORE or RECALL cycle is in progress. A STORE cycle in progress is indicated by the RDY bit of the Status Register and the HSB pin. Read Sequence (READ) Instruction The read operations on this device are performed by giving the instruction on the SI pin and reading the output on SO pin. The following sequence needs to be followed for a read operation: After the CS line is pulled LOW to select a device, the read opcode is transmitted through the SI line followed by two bytes of address. The MSB bit (A15) of the address is a “don’t care”. After the last address bit is transmitted on the SI pin, the data (D7-D0) at the specific address is shifted out on the SO line on the falling edge of SCK starting with D7. Any other data on SI line after the last address bit is ignored. CY14X256Q allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction. If only one byte is to be read, the CS line must be driven HIGH after one byte of data comes out. However, the read sequence may be continued by holding the CS line LOW and the address is automatically incremented and data continues to shift out on SO pin. When the last data memory address (0x7FFF) is reached, the address rolls over to 0x0000 and the device continues to read. Note The READ instruction operates up to a maximum of 40 MHz SPI frequency. MSB. The first byte specified can be at any location. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single FAST_READ instruction. When the highest address in the memory array is reached, address counter rolls over to start address 0x0000 and thus allowing the read sequence to continue indefinitely. The FAST_READ instruction is terminated by driving CS High at any time during data output. Note FAST_READ instruction operates up to maximum of 104 MHz SPI frequency. Write Sequence (WRITE) Instruction The write operations on this device are performed through the SI pin. To perform a write operation, if the device is write disabled, then the device must first be write enabled through the WREN instruction. When the writes are enabled (WEN = ‘1’), WRITE instruction is issued after the falling edge of CS. A WRITE instruction constitutes transmitting the WRITE opcode on SI line followed by two bytes of address and the data (D7-D0) which is to be written. The MSB bit (A15) of the address is a “don’t care”. CY14X256Q enables writes to be performed in bursts through SPI which can be used to write consecutive addresses without issuing a new WRITE instruction. If only one byte is to be written, the CS line must be driven HIGH after the D0 (LSB of data) is transmitted. However, if more bytes are to be written, CS line must be held LOW and address is incremented automatically. The following bytes on the SI line are treated as data bytes and written in the successive addresses. When the last data memory address (0x7FFF) is reached, the address rolls over to 0x0000 and the device continues to write. The WEN bit is reset to ‘0’ on completion of a WRITE sequence. Note When a burst write reaches a protected block address, it continues the address increment into the protected space but does not write any data to the protected memory. If the address roll over takes the burst write to unprotected space, it resumes writes. The same operation is true if a burst write is initiated within a write protected block. Fast Read Sequence (FAST_READ) Instruction The FAST_READ instruction allows you to read memory at SPI frequency above 40 MHz and up to 104 MHz (Max). The host system must first select the device by driving CS low, the FAST_READ instruction is then written to SI, followed by 2 address byte and then a dummy byte. The MSB bit (A15) of the address is a “don’t care”. From the subsequent falling edge of the SCK, the data of the specific address is shifted out serially on the SO line starting with Figure 12. Read Instruction Timing CS SCK Op-Code 15-bit Address 1 1 X A14 A13 A12 A11 A10 A9 A8 SI ~~ ~~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 0 0 0 0 0 0 A3 A2 A1 A0 MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 SO HI-Z MSB Data LSB Document #: 001-65282 Rev. *B Page 13 of 33 CY14C256Q CY14B256Q CY14E256Q Figure 13. Burst Mode Read Instruction Timing CS SCK Op-Code SI 0 0 0 0 0 0 1 1 X A14 A13 A12 A11 A10 A9 A8 ~ ~ 15-bit Address A3 A2 A1 A0 MSB ~ ~ LSB Data Byte 1 Data Byte N SO HI-Z MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 ~ ~ ~ ~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7 MSB LSB Figure 14. Fast Read Instruction Timing CS SCK Op-Code SI 0 0 0 0 1 0 1 1 ~~ ~~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 15-bit Address X A14 A13 A12 A11 A10 A9 A8 Dummy Byte X X X X X X X A3 A2 A1 A0 X MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 SO HI-Z MSB Data LSB Figure 15. Write Instruction Timing CS SCK Op-Code 15-bit Address 1 0 X A14 A13 A12 A11 A10 A9 A8 SI 0 0 0 0 0 0 MSB ~~ ~~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB Data LSB SO HI-Z Figure 16. Burst Mode Write Instruction Timing CS SCK ~ ~ ~ ~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7 Data Byte 1 Data Byte N SI 0 0 0 0 0 0 1 0 X A14 A13 A12 A11 A10 A9 A8 MSB HI-Z ~ ~ A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB LSB SO Document #: 001-65282 Rev. *B ~ ~ Op-Code 15-bit Address Page 14 of 33 CY14C256Q CY14B256Q CY14E256Q nvSRAM Special Instructions CY14X256Q provides four special instructions which enables access to the nvSRAM specific functions: STORE, RECALL, ASDISB, and ASENB. Table 7 lists these instructions. Table 7. nvSRAM Special Instructions Function Name STORE RECALL ASENB ASDISB Opcode 0011 1100 0110 0000 0101 1001 0001 1001 Operation Software STORE Software RECALL AutoStore Enable AutoStore Disable AutoStore Enable (ASENB) Instruction The AutoStore Enable instruction enables the AutoStore on CY14X256Q2A/CY14X256Q3A. This setting is not nonvolatile and needs to be followed by a STORE sequence to survive the power cycle. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the ASENB opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the ASENB instruction. Note If ASDISB and ASENB instructions are executed in CY14X256Q2A/CY14X256Q3A, the device is busy for the duration of software sequence processing time (tSS). However, ASDISB and ASENB instructions have no effect on CY14X256Q1A as AutoStore is internally disabled. Figure 19. AutoStore Enable Operation Software STORE (STORE) Instruction When a STORE instruction is executed, nvSRAM performs a Software STORE operation. The STORE operation is performed irrespective of whether a write has taken place since the last STORE or RECALL operation. To issue this instruction, the device must be write enabled (WEN bit = ‘1’). The instruction is performed by transmitting the STORE opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the STORE instruction. Figure 17. Software STORE Operation CS 0 SCK SI SO 0 0 1 1 1 1 0 0 1 2 3 4 5 6 7 CS 0 SCK SI SO 0 1 0 1 1 0 0 1 1 2 3 4 5 6 7 HI-Z AutoStore Disable (ASDISB) Instruction AutoStore is enabled by default in CY14X256Q2A/CY14X256Q3A. The ASDISB instruction disables the AutoStore. This setting is not nonvolatile and needs to be followed by a STORE sequence to survive the power cycle. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the ASDISB opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the ASDISB instruction. Figure 20. AutoStore Disable Operation HI-Z Software RECALL (RECALL) Instruction When a RECALL instruction is executed, nvSRAM performs a Software RECALL operation. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the RECALL opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the RECALL instruction. Figure 18. Software RECALL Operation CS 0 SCK SI SO 0 1 1 0 0 HI-Z CS 1 2 3 4 5 6 7 0 SCK 1 2 3 4 5 6 7 0 0 0 SI SO 0 0 0 1 1 0 0 1 HI-Z Document #: 001-65282 Rev. *B Page 15 of 33 CY14C256Q CY14B256Q CY14E256Q Special Instructions SLEEP Instruction SLEEP instruction puts the nvSRAM in a sleep mode. When the SLEEP instruction is issued and CS is brought HIGH, the nvSRAM performs a STORE operation to secure the data to nonvolatile memory and then enters into sleep mode. The device starts consuming IZZ current after tSLEEP time from the instance when SLEEP instruction is registered. The device is not accessible for normal operations after SLEEP instruction is issued. Once in sleep mode, the SCK and SI pins are ignored and SO is Hi-Z but device continues to monitor the CS pin. To wake the nvSRAM from the sleep mode, the device must be selected by toggling the CS pin from HIGH to LOW. The device wakes up and is accessible for normal operations after tWAKE duration after a falling edge of CS pin is detected. Note Whenever nvSRAM enters into sleep mode, it initiates nonvolatile STORE cycle which results in an endurance cycle per sleep command execution. A STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Figure 21. Sleep Mode Entry t SLEEP Serial Number The serial number is an 8 byte programmable memory space provided to you uniquely identify this device. It typically consists of a two byte Customer ID, followed by five bytes of unique serial number and one byte of CRC check. However, nvSRAM does not calculate the CRC and it is up to the system designer to utilize the eight byte memory space in whatever manner desired. The default value for eight byte locations are set to ‘0x00’. WRSN (Serial Number Write) Instruction The serial number can be written using the WRSN instruction. To write serial number the write must be enabled using the WREN instruction. The WRSN instruction can be used in burst mode to write all the 8 bytes of serial number. The serial number is locked using the SNL bit of the Status Register. Once this bit is set to '1', no modification to the serial number is possible. After the SNL bit is set to '1', using the WRSN instruction has no effect on the serial number. A STORE operation (AutoStore or Software STORE) is required to store the serial number in nonvolatile memory. If AutoStore is disabled, you must perform a Software STORE operation to secure and lock the serial Number. If SNL bit is set to ‘1’ and is not stored (AutoStore disabled), the SNL bit and serial number defaults to ‘0’ at the next power cycle. If SNL bit is set to ‘1’ and is stored, the SNL bit can never be cleared to ‘0’. This instruction requires the WEN bit to be set before it can be executed. The WEN bit is reset to '0' after completion of this instruction. CS 0 SCK SI SO 1 0 1 1 1 0 0 1 1 2 3 4 5 6 7 Hi-Z Figure 22. WRSN Instruction CS SCK Op-Code Byte - 8 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ~ ~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 56 57 58 59 60 61 62 63 Byte - 1 ~ ~ SI 1 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 MSB 8-Byte Serial Number HI-Z LSB SO Document #: 001-65282 Rev. *B Page 16 of 33 CY14C256Q CY14B256Q CY14E256Q RDSN (Serial Number Read) Instruction The serial number is read using RDSN instruction at SPI frequency upto 40 MHz. A serial number read may be performed in burst mode to read all the eight bytes at once. After the last byte of serial number is read, the device does not loop back. RDSN instruction can be issued by shifting the op-code for RDSN in through the SI pin of nvSRAM after CS goes LOW. This is followed by nvSRAM shifting out the eight bytes of serial number through the SO pin. Figure 23. RDSN Instruction CS SCK Op-Code SI 1 1 0 0 0 0 1 1 ~ ~ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 56 57 58 59 60 61 62 63 Byte - 8 Byte - 1 SO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 ~ ~ D7 D6 D5 D4 D3 D2 D1 D0 MSB 8-Byte Serial Number LSB FAST_RDSN (Fast Serial Number Read) Instruction The FAST_RDSN instruction is used to read serial number at SPI frequency above 40 MHz and up to 104 MHz (max). A serial number read may be performed in burst mode to read all the eight bytes at once. After the last byte of serial number is read, the device does not loop back. FAST_RDSN instruction can be issued by shifting the op-code for FAST_RDSN in through the SI pin of nvSRAM followed by dummy byte after CS goes LOW. This is followed by nvSRAM shifting out the eight bytes of serial number through the SO pin. Figure 24. FAST_RDSN Instruction CS SCK Op-Code Dummy Byte 0 1 SI 1 1 0 0 1 0 X X X X X XX X ~ ~ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 56 57 58 59 60 61 62 63 Byte - 8 Byte - 1 SO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 ~ ~ D7 D6 D5 D4 D3 D2 D1 D0 MSB 8-Byte Serial Number LSB Document #: 001-65282 Rev. *B Page 17 of 33 CY14C256Q CY14B256Q CY14E256Q Device ID Device ID is 4-byte read only code identifying a type of product uniquely. This includes the product family code, configuration and density of the product. Table 8. Device ID Bits #of Bits Device CY14C256Q1A CY14C256Q2A CY14C256Q3A CY14B256Q1A CY14B256Q2A CY14B256Q3A CY14E256Q1A CY14E256Q2A CY14E256Q3A 31 - 21 (11 bits) Manufacture ID 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 20 - 7 (14 bits) Product ID 00001000000001 00001100000000 00001100000001 00001000010001 00001100010000 00001100010001 00001000100001 00001100100000 00001100100001 4. Die Rev (3 bits) This is used to represent any major change in the design of the product. The initial setting of this is always 0x0. 6- 3 (4 bits) Density ID 0010 0010 0010 0010 0010 0010 0010 0010 0010 2-0 (3 bits) Die Rev 000 000 000 000 000 000 000 000 000 The device ID is divided into four parts as shown in Table 8: 1. Manufacturer ID (11 bits) This is the JEDEC assigned manufacturer ID for Cypress. JEDEC assigns the manufacturer ID in different banks. The first three bits of the manufacturer ID represent the bank in which ID is assigned. The next eight bits represent the manufacturer ID. Cypress’s manufacturer ID is 0x34 in bank 0. Therefore the manufacturer ID for all Cypress nvSRAM products is: Cypress ID - 000_0011_0100 2. Product ID (14 bits) The product ID is defined as shown in the Table 8 3. Density ID (4 bits) The 4 bit density ID is used as shown in Table 8 for indicating the 256 Kb density of the product. RDID (Device ID Read) Instruction This instruction is used to read the JEDEC assigned manufacturer ID and product ID of the device at SPI frequency upto 40 MHz. This instruction can be used to identify a device on the bus. RDID instruction can be issued by shifting the op-code for RDID in through the SI pin of nvSRAM after CS goes LOW. This is followed by nvSRAM shifting out the four bytes of device ID through the SO pin. Figure 25. RDID instruction CS 01 SCK Op-Code 2 34 5 6 701 2 34 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI 1001111 1 Byte - 4 Byte - 3 Byte - 2 Byte - 1 SO HI-Z MSB D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 LSB 4-Byte Device ID Document #: 001-65282 Rev. *B Page 18 of 33 CY14C256Q CY14B256Q CY14E256Q FAST_RDID (Fast Device ID Read) Instruction The FAST_RDID instruction allows the user you to read the JEDEC assigned manufacturer ID and product ID at SPI frequency above 40 MHz and up to 104 MHz (max). FAST_RDID instruction can be issued by shifting the op-code for FAST_RDID in through the SI pin of nvSRAM followed by dummy byte after CS goes LOW. This is followed by nvSRAM shifting out the four bytes of device ID through the SO pin. Figure 26. FAST_RDID instruction CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 SCK 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Op-Code SI 10011 00 Dummy Byte 1XXXXXXXX Byte - 4 Byte - 3 Byte - 2 Byte - 1 SO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB 4-Byte Device ID LSB HOLD Pin Operation The HOLD pin is used to pause the serial communication. When the device is selected and a serial sequence is underway, HOLD is used to pause the serial communication with the master device without resetting the ongoing serial sequence. To pause, the HOLD pin must be brought LOW when the SCK pin is LOW. To resume serial communication, the HOLD pin must be brought HIGH when the SCK pin is LOW (SCK may toggle during HOLD). While the device serial communication is paused, inputs to the SI pin are ignored and the SO pin is in the high impedance state. This pin can be used by the master with the CS pin to pause the serial communication by bringing the pin HOLD LOW and deselecting an SPI slave to establish communication with another slave device, without the serial communication being reset. The communication may be resumed at a later point by selecting the device and setting the HOLD pin HIGH. Figure 27. HOLD Operation CS SCK HOLD SO ~~ ~~ Document #: 001-65282 Rev. *B Page 19 of 33 CY14C256Q CY14B256Q CY14E256Q Best Practices nvSRAM products have been used effectively for over 26 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ ■ The nonvolatile cells in this nvSRAM product are delivered by Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection. ■ Document #: 001-65282 Rev. *B Page 20 of 33 CY14C256Q CY14B256Q CY14E256Q Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time At 150 C ambient temperature ....................... 1000 h At 85 C ambient temperature ..................... 20 Years Ambient temperature with power applied ........................................... –55 C to +150 C Supply voltage on VCC relative to VSS CY14C256Q: VCC = 2.4 V to 2.6 V ....–0.5 V to +3.1 V CY14B256Q: VCC = 2.7 V to 3.6 V ....–0.5 V to +4.1 V CY14E256Q: VCC = 4.5 V to 5.5 V ....–0.5 V to +7.0 V DC voltage applied to outputs in High Z state ..................................... –0.5 V to VCC + 0.5 V Input voltage ........................................ –0.5 V to VCC + 0.5 V Transient voltage (< 20 ns) on any pin to ground potential .................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) .................................................. 1.0 W Surface mount lead soldering temperature (3 seconds) .......................................... +260 C DC output current (1 output at a time, 1s duration)..... 15 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current .................................................... > 140 mA Table 9. Operating Range Device CY14C256Q CY14B256Q CY14E256Q Range Ambient Temperature VCC 2.7 V to 3.6 V 4.5 V to 5.5 V Industrial –40 C to +85 C 2.4 V to 2.6 V DC Electrical Characteristics Parameter VCC Description Power supply Test Conditions CY14C256Q CY14B256Q CY14E256Q ICC1 Average VCC current fSCK = 40 MHz; Values obtained without output loads (IOUT = 0 mA) CY14C256Q CY14B256Q CY14E256Q fSCK = 104 MHz; Values obtained without output loads (IOUT = 0 mA) ICC2 ICC3 Average VCC current during STORE All inputs don’t care, VCC = Max Average current for duration tSTORE – – – – – – – – 4 10 2 1 mA mA mA mA Min 2.4 2.7 4.5 – Typ[5] 2.5 3.0 5.0 – Max 2.6 3.6 5.5 3 Unit V V V mA Average VCC current All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA) fSCK = 1 MHz; VCC = VCC (Typ), 25 °C Average VCAP current All inputs don't care. Average current for duration tSTORE during AutoStore cycle VCC standby current CS > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. fSCK = 0 MHz. tSLEEP time after SLEEP Instruction is registered. All inputs are static and configured at CMOS logic level. ICC4 ISB – – – – 3 150 mA A IZZ IIX[6] Sleep mode current Input leakage current (except HSB) Input leakage current (for HSB) – –1 –100 –1 – – – – 8 +1 +1 +1 A A A A IOZ Off-state output leakage current Notes 5. Typical values are at 25 °C, VCC = VCC (Typ). Not 100% tested. 6. The HSB pin has IOUT = -2 µA for VOH of 2.4 V when both active high and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document #: 001-65282 Rev. *B Page 21 of 33 CY14C256Q CY14B256Q CY14E256Q DC Electrical Characteristics (continued) Parameter VIH Description Input HIGH voltage Test Conditions CY14C256Q CY14B256Q CY14E256Q VIL Input LOW voltage CY14C256Q Vss – 0.5 CY14B256Q Vss – 0.5 CY14E256Q VOH Output HIGH voltage IOUT = –1 mA IOUT = –2 mA VOL Output LOW voltage IOUT = 2 mA IOUT = 4 mA VCAP Storage capacitor Between VCAP pin and VSS CY14C256Q CY14B256Q CY14E256Q CY14C256Q CY14B256Q CY14E256Q CY14C256Q CY14B256Q CY14E256Q 170 42 220 47 270 180 F F – – – – 0.4 0.4 V V 2.0 2.4 – – – – V V – – 0.7 0.8 V V Min 1.7 2.0 – Typ[5] Max VCC + 0.5 VCC + 0.5 Unit V V Data Retention and Endurance Parameter DATAR NVC Data retention Nonvolatile STORE operations Description Min 20 1,000 Unit Years K Capacitance Parameter[7] CIN COUT Description Input capacitance Output pin capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC (Typ) Max 7 7 Unit pF pF Thermal Resistance Parameter [7] Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 8-pin SOIC 101.08 37.86 16-pin SOIC 56.68 32.11 Unit C/W C/W JA JC Note 7. These parameters are guaranteed by design and are not tested. Document #: 001-65282 Rev. *B Page 22 of 33 CY14C256Q CY14B256Q CY14E256Q Figure 28. AC Test Loads and Waveforms For 2.5 V (CY14C256Q): 909  2.5 V OUTPUT 30 pF R2 1290  R1 909  2.5 V OUTPUT 5 pF R1 For Tri-state specs R2 1290  For 3 V (CY14B256Q): 577  3.0 V OUTPUT 30 pF R2 789  R1 577  3.0 V OUTPUT 5 pF R1 For Tri-state specs R2 789  For 5 V (CY14E256Q): 963  5.0 V OUTPUT 30 pF R2 512  R1 963  5.0 V OUTPUT 5 pF R1 For Tri-state specs R2 512  AC Test Conditions CY14C256Q Input pulse levels Input rise and fall times (10% - 90%) Input and output timing reference levels 0 V to 2.5 V < 3 ns 1.25 V CY14B256Q 0 V to 3 V < 3 ns 1.5 V CY14E256Q 0 V to 3 V < 3 ns 1.5 V Document #: 001-65282 Rev. *B Page 23 of 33 CY14C256Q CY14B256Q CY14E256Q AC Switching Characteristics Cypress Parameter fSCK tCL[8] tCH[8] tCS tCSS tCSH tSD tHD tHH tSH tCO tHHZ[8] tHLZ[8] tOH tHZCS[8] Alt. Parameter fSCK tWL tWH tCE tCES tCEH tSU tH tHD tCD tV tHZ tLZ tHO tDIS Description Clock frequency, SCK Clock pulse width LOW Clock pulse width HIGH CS HIGH time CS setup time CS hold time Data in setup time Data in hold time HOLD hold time HOLD setup time Output Valid HOLD to output HIGH Z HOLD to output LOW Z Output hold time Output disable time 40 MHz Min – 11 11 20 10 10 5 5 5 5 – – – 0 – Max 40 – – – – – – – – – 9 15 15 – 20 104 MHz Min Max – 104 4.5 – 4.5 – 20 – 5 – 5 – 4 – 3 – 3 – 3 – – 8 – 8 – 8 0 – – 8 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 29. Synchronous Data Timing (Mode 0) tCS CS tCSS tCH tCL tCSH SCK tSD tHD SI VALID IN tCO tOH tHZCS SO HI-Z ~ ~ HI-Z Figure 30. HOLD Timing CS SCK tHH tSH HOLD tHHZ SO Note 8. These parameters are guaranteed by design and are not tested. ~~ ~~ tHH tSH tHLZ Document #: 001-65282 Rev. *B Page 24 of 33 CY14C256Q CY14B256Q CY14E256Q AutoStore or Power-Up RECALL Parameter tFA [9] tSTORE [10] tDELAY [11] VSWITCH Power-Up RECALL duration Description CY14C256Q CY14B256Q CY14E256Q CY14X256Q Min Max – 40 – 20 – 20 8 – 25 – – 2.35 – 2.65 – 4.40 150 – 1.9 – 5 – 500 – – 40 – 20 – 20 – 8 – 100 Unit ms ms ms ms ns V V V s V s ns ms ms ms ms µs STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level CY14C256Q CY14B256Q CY14E256Q tVCCRISE[12] VHDIS[12] tLZHSB[12] tHHHD[12] tWAKE VCC rise time HSB output disable voltage HSB high to nvSRAM active time HSB high active time Time for nvSRAM to wake up from SLEEP mode tSLEEP tSB CY14C256Q CY14B256Q CY14E256Q Time to enter SLEEP mode after issuing SLEEP instruction Time to enter into standby mode after CS going HIGH Switching Waveforms Figure 31. AutoStore or Power-Up RECALL[13] VCC VSWITCH VHDIS t VCCRISE 14 tHHHD Note 10 tSTORE tHHHD Note 10 tSTORE 14 Note HSB OUT Note tDELAY AutoStore tLZHSB tDELAY tLZHSB POWERUP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL tFA tFA Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 9. tFA starts from the time VCC rises above VSWITCH. 10. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated. 11. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY. 12. These parameters are guaranteed by design and are not tested. 13. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 14. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document #: 001-65282 Rev. *B Page 25 of 33 CY14C256Q CY14B256Q CY14E256Q Software Controlled STORE and RECALL Cycles CY14X256Q Parameter tRECALL tSS [15, 16] Description Min RECALL duration Soft sequence processing time – – Max 600 500 Unit s s Switching Waveforms Figure 32. Software STORE Cycle[16] Figure 33. Software RECALL Cycle[16] CS 0 SCK SI 0 0 1 1 1 1 0 0 tSTORE CS 1 2 3 4 5 6 7 SCK SI 0 1 1 0 0 0 0 0 tRECALL 0 1 2 3 4 5 6 7 RWI RDY HI-Z RWI RDY HI-Z Figure 34. AutoStore Enable Cycle Figure 35. AutoStore Disable Cycle CS 0 SCK SI 0 1 0 1 1 0 0 1 tSS 1 2 3 4 5 6 7 CS 0 SCK SI 0 0 0 1 1 0 0 1 tSS 1 2 3 4 5 6 7 RWI RDY HI-Z RWI RDY HI-Z Notes 15. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 16. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. Document #: 001-65282 Rev. *B Page 26 of 33 CY14C256Q CY14B256Q CY14E256Q Hardware STORE Cycle Parameter tPHSB Description Hardware STORE pulse width CY14C256Q3A/CY14B256Q3A/ CY14E256Q3A Min 15 Max – ns Unit Switching Waveforms Figure 36. Hardware STORE Cycle[17] Write Latch set HSB (IN) tDELAY HSB (OUT) tSTORE ~ ~ tPHSB tHHHD ~ ~ tLZHSB RWI Write Latch not set HSB (IN) ~ ~ tPHSB HSB pin is driven HIGH to VCC only by Internal 100 K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. HSB (OUT) tDELAY RWI Note 17. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated. Document #: 001-65282 Rev. *B ~ ~ Page 27 of 33 CY14C256Q CY14B256Q CY14E256Q Ordering Information Ordering Code CY14B256Q1A-SXIT CY14B256Q1A-SXI CY14B256Q2A-SXIT CY14B256Q2A-SXI All these parts are Pb-free. This table contains final information. Contact your local Cypress sales representative for availability of these parts. Package Diagram 51-85066 Package Type 8-pin SOIC (with WP), 40 MHz 8-pin SOIC (with VCAP), 40 MHz Operating Range Industrial Ordering Code Definitions CY 14 B 256 Q 2 A - S 104 X I T Option: T - Tape & Reel Blank - Std. Pb-free Frequency: Blank - 40 MHz 104 - 104 MHz Die revision: Blank - No Rev A - 1st Rev Package: SXP - 8 SOIC SFP - 16 SOIC 1 - With WP 2 - With VCAP 3 - With WP, VCAP and HSB Q - Serial (SPI) nvSRAM Density: 256 - 256 Kb Voltage: C - 2.5 V B - 3.0 V E - 5.0 V Temperature: I - Industrial (-40 to 85 °C) 14 - nvSRAM Cypress Document #: 001-65282 Rev. *B Page 28 of 33 CY14C256Q CY14B256Q CY14E256Q Package Diagrams Figure 37. 8-pin (150 mil) SOIC, 51-85066 51-85066 *D Document #: 001-65282 Rev. *B Page 29 of 33 CY14C256Q CY14B256Q CY14E256Q Package Diagrams (continued) Figure 38. 16-pin (300 mil) SOIC, 51-85022 51-85022 *C Document #: 001-65282 Rev. *B Page 30 of 33 CY14C256Q CY14B256Q CY14E256Q Acronyms Acronym nvSRAM SPI RoHS I/O CMOS SOIC SONOS CPHA CPOL EEPROM JEDEC CRC EIA RWI Description Nonvolatile static random access memory Serial peripheral interface Restriction of hazardous substances Input/output Complementary metal oxide semiconductor Small outline integrated circuit Silicon-oxide-nitride-oxide-silicon Clock phase Clock polarity Electrically erasable programmable read-only memory Joint Electron Devices Engineering Council Cyclic redundancy check Electronic Industries Alliance Read and write inhibited Document Conventions Units of Measure Symbol °C Hz kbit kHz K A mA F MHz s ms ns pF V  W Hertz 1024 bits kilo Hertz kilo ohms micro Amperes milli Amperes micro Farad mega Hertz micro seconds milli seconds nano seconds pico Farad Volts ohms Watts Unit of Measure degree Celsius Document #: 001-65282 Rev. *B Page 31 of 33 CY14C256Q CY14B256Q CY14E256Q Document History Page Document Title: CY14C256Q, CY14B256Q, CY14E256Q 256-Kbit (32 K × 8) SPI nvSRAM Document Number: 001-65282 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 3096371 GVCH 12/08/2010 New datasheet *A 3217968 GVCH 04/06/2011 Updated AutoStore Operation (description). Updated Hardware STORE and HSB pin Operation (Added more clarity on HSB pin operation). Updated Table 4 (description of Bit 4-5). Updated DC Electrical Characteristics (Added ICC1 parameter for 104 MHz frequency). Updated AutoStore or Power-Up RECALL (tLZHSB parameter description). *B 3247264 GVCH 05/03/2011 Datasheet status changed from “Preliminary” to “Final” Updated Ordering Information Document #: 001-65282 Rev. *B Page 32 of 33 CY14C256Q CY14B256Q CY14E256Q Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-65282 Rev. *B Revised May 3, 2011 Page 33 of 33 All products and company names mentioned in this document may be the trademarks of their respective holders.