CY22150

CY22150 One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator Features • • • • • • • • Integrated phase-locked loop (PLL) Commercial and industrial operation Flash-programmable Field-programmable 2-wire serial programming interface Low-skew, low-jitter, high-accuracy outputs 3.3V operation with 2.5V output option 16-lead TSSOP • times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. The CY22150 can be programmed at the package level. In-house programming of samples and prototype quantities is available using the CY3672 FTG Development Kit. Production quantities are available through Cypress’s value-added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. The CY22150 provides an industry-standard interface for volatile, system-level customization of unique frequencies and options. Serial programming and reprogramming allows quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. High performance suited for commercial, industrial, networking, telecomm and other general-purpose applications. Application compatibility in standard and low-power systems. Industry-standard packaging saves on board space. • Benefits • Internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external crystal or a driven source. • Performance guaranteed for applications that require an extended temperature range. • Nonvolatile reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. Parts can be reprogrammed up to 100 • • • Logic Block Diagram Divider Bank 1 XIN XOUT P LCLK1 LCLK2 Crosspoint Switch Matrix LCLK3 LCKL4 OSC. Q Φ VCO PLL Divider Bank 2 CLK5 CLK6 Serial SDAT Programming SCLK Interface SPI Control VDD VSS AVDD AVSS VDDL VSSL Pin Configuration XIN VDD AVDD SDAT AVSS VSSL LCLK1 LCLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK6 CLK5 VSS LCLK4 VDDL SCLK LCLK3 Cypress Semiconductor Corporation Document #: 38-07104 Rev. *F • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 11, 2004 CY22150 Part Number CY22150FC Outputs 6 Input Frequency Range 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) Output Frequency Range 80 kHz–200 MHz (3.3V) 80 KHz–166.6 MHz (2.5V) 80 kHz – 166.6 MHz (3.3V) 80 KHz – 150 MHz (2.5V) Specifications Field programmable Serially programmable Commercial temperature Field programmable Serially programmable Industrial temperature CY22150FI 6 Pin Definitions Pin Name XIN Pin Number 1 Pin Description Reference Input. Driven by a crystal (8 MHz – 30 MHz) or external clock (1 MHz – 133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting a crystal, regardless of manufacturer, process, performance, or quality. 3.3V voltage supply 3.3V analog voltage supply Serial data input Analog ground LCLK ground Configurable clock output 1 at VDDL level (3.3V or 2.5V) Configurable clock output 2 at VDDL level (3.3V or 2.5V) Configurable clock output 3 at VDDL level (3.3V or 2.5V) Serial clock input LCLK voltage supply (2.5V or 3.3V) Configurable clock output 4 at VDDL level (3.3V or 2.5V) Ground Configurable clock output 5 (3.3V) Configurable clock output 6 (3.3V) Reference output VDD AVDD SDAT AVSS VSSL LCLK1 LCLK2 LCLK3 SCLK VDDL LCLK4 VSS CLK5 CLK6 XOUT[1] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Frequency Calculation and Register Definitions The CY22150 is an extremely flexible clock generator with four basic variables that can be used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, and the post divider, which can be a fixed or calculated value. There are three basic formulas for determining the final output frequency of a CY22150-based design: • CLK = ((REF * P)/Q)/Post Divider • CLK = REF/Post Divider • CLK = REF. Note: 1. Float XOUT if XIN is driven by an external clock source. The basic PLL block diagram is shown in Figure 1. Each of the six clock outputs on the CY22150 has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups. The post divider options can be applied to the calculated VCO frequency ((REF*P)/Q) or to the REF directly. In addition to the six post divider output options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. Document #: 38-07104 Rev. *F Page 2 of 13 CY22150 DIV1N [OCH] DIV1SRC [OCH] 1 Qtotal DIV1CLK REF (Q+2) [42H] Ptotal (2(PB+4)+PO) [40H], [41H], [42H] 1 DIV2CLK PFD VCO 0 /DIV1N /2 /3 Divider Bank 1 Divider Bank 2 /4 /2 /DIV2N CLKSRC Crosspoint Switch Matrix [44H] [44H] [44H,45H] [45H] LCLK1 LCLK2 LCLK3 LCLK4 0 [45H] [45H,46H] CLK5 CLK6 DIV2SRC [47H] DIV2N [47H] CLKOE [09H] Figure 1. Basic Block Diagram of CY22150 PLL Default Start-up Condition for the CY22150 The default (programmed) condition of the device is generally set by the distributor who programs the device using a customer-specific JEDEC file produced by CyClocksRT. Parts shipped from the factory are blank and unprogrammed. In this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. While you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use CyClocksRT to produce the required register setting file. The serial interface address of the CY22150 is 69H. Should there be a conflict with any other devices in your system, this can also be changed using CyClocksRT. powered back up again, the SPI registers will need to be reconfigured again. All programmable registers in the CY22150 are addressed with eight bits and contain eight bits of data. The CY22150 is a slave device with an address of 1101001 (69H). Table 1 lists the SPI registers and their definitions. Specific register definitions and their allowable values are listed below. Reference Frequency The REF can be a crystal or a driven frequency. For crystals, the frequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between 1 MHz and 133 MHz. Using a Crystal as the Reference Input The input crystal oscillator of the CY22150 is an important feature because of the flexibility it allows the user in selecting a crystal as a REF source. The input oscillator has programmable gain, allowing for maximum compatibility with a reference crystal, regardless of manufacturer, process, performance and quality. Programmable Crystal Input Oscillator Gain Settings The Input crystal oscillator gain (XDRV) is controlled by two bits in register 12H, and are set according to Table 2. The parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (ESR, available from the Frequency Calculations and Register Definitions Using the Serial Programming Interface The CY22150 provides an industry standard serial interface for volatile, in-system programming of unique frequencies and options. Serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. The Serial Programming Interface (SPI) provides volatile programming, i.e., when the target system is powered down, the CY22150 reverts to its pre-SPI state, as defined above (programmed or unprogrammed). When the system is Document #: 38-07104 Rev. *F Page 3 of 13 CY22150 manufacturer), and the CapLoad setting during crystal start-up. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 2. All other bits in the register are reserved and should be programmed as shown in Table 3. Using an External Clock as the Reference Input The CY22150 can also accept an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table 4. Table 1. Summary Table – CY22150 Programmable Registers Register 09H OCH 12H 13H 40H 41H 42H 44H 45H 46H 47H DIV2SRC mux and DIV2N divider Description CLKOE control DIV1SRC mux and DIV1N divider Input crystal oscillator drive control Input load capacitor control Charge Pump and PB counter PO counter, Q counter Crosspoint switch matrix control D7 0 D6 0 D5 CLK6 D4 CLK5 D3 LCLK4 D2 LCLK3 D1 LCLK2 D0 LCLK1 DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 0 CapLoad (7) 1 PB(7) PO 0 CapLoad (6) 1 PB(6) Q(6) 1 CapLoad (5) 0 PB(5) Q(5) XDRV(1) CapLoad (4) Pump(2) PB(4) Q(4) XDRV(0) CapLoad (3) Pump(1) PB(3) Q(3) 0 CapLoad (2) Pump(0) PB(2) Q(2) 0 CapLoad (1) PB(9) PB(1) Q(1) 0 CapLoad (0) PB(8) PB(0) Q(0) CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 for LCLK1 for LCLK1 for LCLK1 for LCLK2 for LCLK2 for LCLK2 for LCLK3 for LCLK3 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 for LCLK3 for LCLK4 for LCLK4 for LCLK4 for CLK5 for CLK5 for CLK5 for CLK6 CLKSRC1 CLKSRC0 for CLK6 for CLK6 1 1 1 1 1 1 DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) Table 2. Programmable Crystal Input Oscillator Gain Settings Cap Register Settings Effective Load Capacitance (CapLoad) Crystal ESR Crystal Input Frequency 8 – 15 MHz 15 – 20 MHz 20 – 25 MHz 25 – 30 MHz Table 3. Bit Locations and Values Address 12H D7 0 D6 0 D5 1 D4 XDRV(1) D3 XDRV(0) D2 0 D1 0 D0 0 00H – 80H 6 pF to 12 pF 30Ω 00 01 01 10 60Ω 01 10 10 10 80H – C0H 12pF to 18pF 30Ω 01 01 10 10 60Ω 10 10 10 11 C0H – FFH 18pF to 30pF 30Ω 01 10 10 11 60Ω 10 10 11 N/A Table 4. Programmable External Reference Input Oscillator Drive Settings Reference Frequency Drive Setting 1 – 25 MHz 00 25 – 50 MHz 01 50 – 90 MHz 10 90 – 133 MHz 11 Document #: 38-07104 Rev. *F Page 4 of 13 CY22150 Input Load Capacitors Input load capacitors allow the user to set the load capacitance of the CY22150 to match the input load capacitance from a crystal. The value of the input load capacitors is determined by 8 bits in a programmable register [13H]. Total load capacitance is determined by the formula: CapLoad = (CL– CBRD – CCHIP)/0.09375 pF where: • CL = specified load capacitance of your crystal. • CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyClocksRT, this value defaults to 2 pF. • CCHIP = 6 pF. • 0.09375 pF = the step resolution available due to the 8-bit register. In CyclocksRT, only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF, and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula above can be used to calculate a new CapLoad value and programmed into register 13H. In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad will be determined automatically and programmed into the CY22150. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 0. See Table 5 for CapLoad bit locations and values. The input load capacitors are placed on the CY22150 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes. made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO). PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings (see Section 5). The 3 MSBs of register 40H are preset and reserved and cannot be changed. PO is a single bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining seven bits of 42H are used to define the Q counter, as shown in Table 6. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Stable operation of the CY22150 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. Registers 40H, 41H and 42H are defined in Table 7. PLL Post Divider Options [OCH(7..0)], [47H(7..0)] The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. The divider banks have 4 unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the two divider banks. The minimum value of DIVxN is 4. The maximum value of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. DIV1SRC is a single bit variable, controlled by register OCH. The remaining seven bits of register OCH determine the value of post divider DIV1N. DIV2SRC is a single bit variable, controlled by register 47H. The remaining seven bits of register 47H determine the value of post divider DIV2N. Register OCH and 47H are defined in Table 8. PLL Frequency, Q Counter [42H(6..0)] The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7 bit divider with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: Qtotal = Q + 2 The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in the table. Stable operation of the CY22150 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 6. Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see “PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 9 summarizes the proper charge pump settings, based on Ptotal. See Table 10 for register 40H bit locations and values. PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is Table 5. Input Load Capacitor Register Bit Settings Address 13H D7 D6 D5 D4 D3 D2 D1 D0 CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0) Document #: 38-07104 Rev. *F Page 5 of 13 CY22150 Table 6. P Counter Register Definition Address 40H 41H 42H D7 1 PB(7) PO D6 1 PB(6) Q(6) D5 0 PB(5) Q(5) D4 Pump(2) PB(4) Q(4) D3 Pump(1) PB(3) Q(3) D2 Pump(0) PB(2) Q(2) D1 PB(9) PB(1) Q(1) D0 PB(8) PB(0) Q(0) Table 7. P Counter Register Definition Address 40H 41H 42H D7 1 PB(7) PO D6 1 PB(6) Q(6) D5 0 PB(5) Q(5) D4 Pump(2) PB(4) Q(4) D3 Pump(1) PB(3) Q(3) D2 Pump(0) PB(2) Q(2) D1 PB(9) PB(1) Q(1) D0 PB(8) PB(0) Q(0) Table 8. PLL Post Divider Options Address OCH 47H D7 DIV1SRC DIV2SRC D6 DIV1N(6) DIV2N(6) D5 DIV1N(5) DIV2N(5) D4 DIV1N(4) DIV2N(4) D3 DIV1N(3) DIV2N(3) D2 DIV1N(2) DIV2N(2) D1 DIV1N(1) DIV2N(1) D0 DIV1N(0) DIV2N(0) Table 9. Charge Pump Settings Charge Pump Setting – Pump(2..0) 000 001 010 011 100 101, 110, 111 Table 10. Register 40H Change Pump Bit Settings Address 40H D7 1 D6 1 D5 0 D4 Pump(2) D3 Pump(1) be D2 Pump(0) rising D1 PB(9) edge D0 PB(8) with Calculated Ptotal 16 – 44 45 – 479 480 – 639 640 – 799 800 – 1023 Do not use – device will be unstable Although using the above table will guarantee stability, it is recommended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to determine the best charge pump setting. Clock Output Settings: CLKSRC – Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] CLKOE – Clock Output Enable Control [09H(5..0)] Every clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H. The remainder of register 46H(5:0) must be written with the values stated in the register table when writing register values 46H(7:6). In addition, each clock output has individual CLKOE control, set by register 09H(5..0). When DIV1N is divisible by four, then CLKSRC(0,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is guaranteed to CLKSRC(0,0,1). phase-aligned When DIV2N is divisible by four, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by eight, then CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). Each clock output has its own output enable, controlled by register 09H(5..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 13. The output swing of LCLK1 through LCLK4 is set by VDDL. The output swing of CLK5 and CLK6 is set by VDD. Test, Reserved, and Blank Registers Writing to any of the following registers will cause the part to exhibit abnormal behavior, as follows. [00H to 08H] [0AH to 0BH] [0DH to 11H] [14H to 3FH] [43H] [48H to FFH] – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved. Document #: 38-07104 Rev. *F Page 6 of 13 CY22150 Table 11. CLKSRC2 0 0 0 0 1 1 1 1 Table 12. Address 44H 45H 46H D7 CLKSRC2 for LCLK1 CLKSRC0 for LCLK3 CLKSRC1 for CLK6 D6 CLKSRC1 for LCLK1 CLKSRC2 for LCLK4 CLKSRC0 for CLK6 D5 CLKSRC0 for LCLK1 CLKSRC1 for LCLK4 1 D4 CLKSRC2 for LCLK2 CLKSRC0 for LCLK4 1 D3 CLKSRC1 for LCLK2 CLKSRC2 for CLK5 1 D2 CLKSRC0 for LCLK2 CLKSRC1 for CLK5 1 D1 CLKSRC2 for LCLK3 CLKSRC0 for CLK5 1 D0 CLKSRC1 for LCLK3 CLKSRC2 for CLK6 1 CLKSRC1 0 0 1 1 0 0 1 1 CLKSRC0 0 1 0 1 0 1 0 1 Reference input. DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. Reserved – do not use. Definition and Notes Table 13. CLKOE Bit Setting Address 09H D7 0 D6 0 D5 CLK6 D4 CLK5 D3 LCLK4 D2 LCLK3 D1 LCLK2 D0 LCLK1 Programmable Interface Timing The CY22150 utilizes a 2-wire serial-interface SDAT and SCLK that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is as follows. Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); eight-bit Memory Address (MA); ACK; eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK; eight-bit data in MA+2; ACK; etc. until STOP bit.The basic serial format is illustrated in Figure 3. Data Valid Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 2. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 4. Data valid SDAT Start Sequence – Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next eight-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). Stop Sequence – Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY22150 will respond with an ACK pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 5. (N = the number of eight-bit segments transmitted.) During Read mode, the ACK pulse after the data packet is sent is generated by the master. Transition to next bit CLKHIGH VIH SCLK VIL tDH tSU CLKLOW Figure 2. Data Valid and Data Transition Periods Document #: 38-07104 Rev. *F Page 7 of 13 CY22150 SDAT Write Multiple Contiguous Registers Start Signal 1-bit 1-bit 1-bit 1-bit 1-bit Slave Slave Slave Slave ACK ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit 8-bit Device Register Register Register Register Data Address Address Data Data (XXH) (XXH) (XXH+1) (XXH+2) 1-bit Slave ACK 1-bit Slave ACK 1-bit Slave ACK 1-bit Slave ACK 8-bit Register Data (FFH) 8-bit Register Data (00H) Stop Signal SDAT Read Multiple Contiguous Registers Start Signal 1-bit 1-bit 1-bit 1-bit Slave Slave 1-bit Master R/W = 1 ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit Device Register 7-Bit Register Register Address Address Device Data Data (XXH) Address (XXH) (XXH+1) 1-bit Master ACK 1-bit Master ACK 1-bit Master ACK 1-bit Master ACK 8-bit Register Data (FFH) 8-bit Register Data (00H) Stop Signal Figure 3. Data Frame Architecture SDAT SCLK STOP START Transition to next bit Figure 4. Start and Stop Frame SDAT + START DA6 SCLK DA5DA0 + R/W ACK RA7 + RA6RA1 + RA0 ACK D7 D6 + + D1 D0 ACK STOP Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data Parameter fSCLK CLKLOW CLKHIGH tSU tDH Description Frequency of SCLK Start mode time from SDA LOW to SCL LOW SCLK LOW period SCLK HIGH period Data transition to SCLK HIGH Data hold (SCLK LOW to data transition) Rise time of SCLK and SDAT Fall time of SCLK and SDAT Stop mode time from SCLK HIGH to SDAT HIGH Stop mode to Start mode 0.6 1.3 0.6 1.3 0.6 100 0 300 300 Min. Max. 400 Unit kHz µs µs µs ns ns ns ns µs µs Document #: 38-07104 Rev. *F Page 8 of 13 CY22150 Applications Controlling Jitter Jitter is defined in many ways including: phase noise, long-term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deterministic. These jitter terms are usually given in terms of rms, peak to peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Power Supply Noise and clock output loading are two major system sources of clock jitter. Power Supply noise can be mitigated by proper power supply decoupling (0.1 µF ceramic cap 0.25”) of the clock and ensuring a low impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs will also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. The rate and magnitude that the PLL corrects the VCO frequency is directly related to jitter performance. If the rate is too slow, then long term jitter and phase noise will be poor. Therefore, to improve long-term jitter and phase noise, reducing Q to a minimum is advisable. This technique will increase the speed of the Phase Frequency Detector which in turn drive the input voltage of the VCO. In a similar manner increasing P till the VCO is near its maximum rated speed will also decrease long term jitter and phase noise. For example: Input Reference of 12 MHz; desired output frequency of 33.3 MHz. One might arrive at the following solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter results will be Q = 2, P = 50, Post Div = 9. For more information, refer to the application note “Jitter in PLL-Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your local Cypress field applications engineer. Test Circuit VDD 0.1 mF OUTPUTS CLK out C LOAD AVDD 0.1 mF GND VDDL 0.1 µ F t1 t3 80% t4 t2 CLK 50% 50% CLK 20% Figure 6. Duty Cycle Definition; DC = t2/t1 Figure 7. Rise and Fall Time Definitions t6 Figure 8. Peak-to-Peak Jitter Document #: 38-07104 Rev. *F Page 9 of 13 CY22150 Table 14. Absolute Maximum Conditions Parameter VDD VDDL TS TJ Supply Voltage I/O Supply Voltage Storage Temperature[2] Junction Temperature Package Power Dissipation – Commercial Temp Package Power Dissipation – Industrial Temp Digital Inputs Digital Outputs referred to VDD Digital Outputs referred to VDDL ESD Static Discharge Voltage per MIL-STD-833, Method 3015 Table 15. Recommended Operating Conditions Parameter VDD VDDLHI TAC TAI CLOAD CLOAD fREFD fREFC tPU [3] Description Min. –0.5 –0.5 –65 Max. 7.0 7.0 125 125 450 380 Unit V V °C °C mW mW V V V V AVSS – 0.3 VSS – 0.3 VSS – 0.3 AVDD + 0.3 VDD + 0.3 VDDL +0.3 2000 Description Operating Voltage Operating Voltage Operating Voltage Ambient Commercial Temp Ambient Industrial Temp Max. Load Capacitance, VDD/VDDL = 3.3V Max. Load Capacitance, VDDL = 2.5V Driven REF Crystal REF Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. 3.135 3.135 2.375 0 –40 Typ. 3.3 3.3 2.5 Max. 3.465 3.465 2.625 70 85 15 15 Unit V V V °C °C pF pF MHz MHz ms VDDLLO[3] 1 8 0.05 133 30 500 Table 16. DC Electrical Characteristics Parameter[4] IOH3.3 IOL3.3 IOH2.5 IOL2.5 VIH VIL CIN IIZ VHYS IVDD[5,6] IVDDL3.3[5,6] IVDDL2.5[5,6] Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current Hysteresis of Schmitt triggered inputs Supply Current Supply Current Description VOH = VDD – 0.5, VDD/VDDL = 3.3V (sink) VOL = 0.5, VDD/VDDL = 3.3V (source) VOH = VDDL – 0.5, VDDL = 2.5V (source) VOL = 0.5, VDDL = 2.5V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD SCLK and SDAT Pins SCLK and SDAT Pins SCLK and SDAT Pins AVDD/VDD Current VDDL Current (VDDL = 3.465V) 0.05 45 25 5 Min. 12 12 8 8 0.7 0.3 7 Typ. 24 24 16 16 Max. Unit mA mA mA mA VDD VDD pF µA VDD mA mA mA Supply Current VDDL Current (VDDL = 2.625V) 17 Notes: 2. Rated for 10 years. 3. VDDLis only specified and characterized at 3.3V ± 5% and 2.5V ± 5%. VDDLmay be powered at any value between 3.465V and 2.375V. 4. Not 100% tested. 5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. 6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations. Document #: 38-07104 Rev. *F Page 10 of 13 CY22150 Table 17. AC Electrical Characteristics Parameter[7] t1 Name Output Frequency, Commercial Temp Output Frequency, Industrial Temp t2LO t2HI t3LO t4LO t3HI t4HI t5[8] t6[9] t10 Output Duty Cycle Output Duty Cycle Rising Edge Slew Rate (VDDL = 2.5V) Falling Edge Slew Rate (VDDL = 2.5V) Rising Edge Slew Rate (VDDL = 3.3V) Falling Edge Slew Rate (VDDL = 3.3V) Skew Clock Jitter PLL Lock Time Description Clock output limit, 3.3V Clock output limit, 2.5V Clock output limit, 3.3V Clock output limit, 2.5V Duty cycle is defined in Figure 6; t1/t2 fOUT < 166 MHz, 50% of VDD Duty cycle is defined in Figure 6; t1/t2 fOUT > 166 MHz, 50% of VDD Output clock rise time, 20% – 80% of VDDL. Defined in Figure 7. Output dlock fall time, 80% – 20% of VDDL. Defined in Figure 7. Output dlock rise time, 20% – 80% of VDD/VDDL. Defined in Figure 7. Output dlock fall time, 80% – 20% of VDD/VDDL. Defined in Figure 7. Output-output skew between related outputs. Peak-to-peak period jitter 250 0.30 3 Min. 0.08 (80 kHz) 0.08 (80 kHz) 0.08 (80 kHz) 0.08 (80 kHz) 45 40 0.6 0.6 0.8 0.8 50 50 1.2 1.2 1.4 1.4 250 Typ. Max. 200 166.6 166.6 150 55 60 Unit MHz MHz MHz MHz % % V/ns V/ns V/ns V/ns ps ps ms Device Characteristics Parameter Name theta JA Transistor Count Value 115 74,600 Unit °C/W transistors θJA Complexity Ordering Information Ordering Code CY22150FC CY22150FI CY22150ZC-xxx CY3672 CY3672ADP000 [10] Package Name Z16 Z16 Z16 Z16 FTG Development System CY22150F Socket Package Type 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP N/A Operating Range Commercial (0 to 70°C) Industrial (–40 to 85°C) Commercial (0 to 70°C) Industrial (–40 to 85°C) Operating Voltage 3.3V 3.3V 3.3V 3.3V CY22150ZI-xxx[10] Notes: 7. Not 100% tested, guaranteed by design. 8. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Diagram for more information. 9. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL, (2.5V or 3.3V jitter in “PLL-Based Systems: Causes, Effects, and Solutions,” available at http://wwww.cypress.com/clock/appnotes.html, or contact your local Cypress field applications engineer). 10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of 100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document #: 38-07104 Rev. *F Page 11 of 13 CY22150 Package Diagram 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] 51-85091-*A BP Microsystems is a trademark of BP Microsystems. HiLo Systems is a trademark of Hi-Lo Systems, Inc. CyClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07104 Rev. *F Page 12 of 13 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY22150 Document History Page Document Title: CY22150 One-PLL General-Purpose Flash-Programmable and 2-Wire Serially-Programmable Clock Generator Document Number: 38-07104 REV. ** *A *B ECN NO. 107498 110043 113514 Issue Date 08/08/01 02/06/02 05/01/02 Orig. of Change CKN CKN CKN Description of Change New Data Sheet Preliminary to Final Removed overline on Figure 5 Register Address Register Data Changed CLKHIGH unit from ns to µs in parameter description table Added (sink) to rows 1 and 4 and added (source) to rows 2 and 3 in the DC Electrical Characteristics table (Figure 16) Power-up requirements added to Operating Conditions Information Changed 0 to 1 under 12H/D5 of Table 1 and Table 3. Reworded and reformatted Programmable Crystal Input Oscillator Gain Settings text. Minor Change: Fixed the broken line in the block diagram Corrected Table 2 specs. *C *D 121868 125453 12/14/02 05/19/03 RBI CKN *E *F 242808 252352 See ECN See ECN RGL RGL Document #: 38-07104 Rev. *F Page 13 of 13