CY22393 Automotive
Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Features
■
Three integrated phase-locked loops (PLLs)
■
Ultra-wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
■
Improved linear crystal load capacitors
■
Flash programmability with external programmer
■
Field-programmable
■
Low-jitter, high-accuracy outputs
■
Power management options (Shutdown, OE, Suspend)
■
Configurable crystal drive strength
■
Frequency select through three external LVTTL inputs
■
3.3 V operation
■
16-pin TSSOP package
■
CyClocksRT™ software support
■
AEC-Q100 Qualified
■
Available in Automotive-A and Automotive-E grade
Advanced Features
■
Two-wire serial interface for in-system configurability
■
Configurable output buffer
■
Digital VCXO
Functional Description
The CY22393 has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
For a complete list of related resources, click here.
Logic Block Diagram – CY22393
XTALIN
XTALOUT
XBUF
OSC.
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
SHUTDOWN/OE
PLL2
SCLK
11-Bit P
8-Bit Q
SDAT
S2/SUSPEND
4x4
Crosspoint
Switch
PLL3
11-Bit P
8-Bit Q
Cypress Semiconductor Corporation
Document Number: 001-73555 Rev. *E
•
198 Champion Court
•
Divider
/2, /3, or /4
CLKE
Divider
7-Bit
CLKD
Divider
7-Bit
CLKC
Divider
7-Bit
CLKB
Divider
7-Bit
CLKA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2018
CY22393 Automotive
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Configurable PLLs ....................................................... 4
General-Purpose Inputs .............................................. 4
Crystal Input ................................................................ 4
Crystal Drive Level and Power .................................... 4
Digital VCXO ............................................................... 4
Output Configuration ................................................... 5
Power-Saving Features ............................................... 5
Improving Jitter ............................................................ 5
Power Supply Sequencing .......................................... 5
CyClocksRT Software ...................................................... 5
Device Programming ........................................................ 6
Junction Temperature Limitations .................................. 6
Dynamic Updates ............................................................. 6
Memory Bitmap Definitions ............................................. 6
Clk{A–D}_Div[6:0] ........................................................ 6
ClkE_Div[1:0] ............................................................... 6
Clk*_FS[2:0] ................................................................ 6
Xbuf_OE ...................................................................... 6
PdnEn .......................................................................... 6
Clk*_ACAdj[1:0] ........................................................... 6
Clk*_DCAdj[1:0] .......................................................... 7
PLL*_Q[7:0] ................................................................. 7
PLL*_P[9:0] ................................................................. 7
PLL*_P0 ...................................................................... 7
PLL*_LF[2:0] ............................................................... 7
PLL*_En ...................................................................... 7
DivSel .......................................................................... 7
OscCap[5:0] ................................................................ 7
OscDrv[1:0] ................................................................. 7
Reserved ..................................................................... 7
Serial Programming Bitmaps
– Summary Table 1 ........................................................... 8
Serial Programming Bitmaps
– Summary Table 2 ........................................................... 9
Document Number: 001-73555 Rev. *E
Serial Bus Programming Protocol and Timing ............ 10
Default Startup Condition for the CY22393 ............... 11
Device Address ......................................................... 11
Data Valid .................................................................. 11
Data Frame ............................................................... 11
Acknowledge Pulse ................................................... 12
Write Operations ............................................................. 12
Writing Individual Bytes ............................................. 12
Writing Multiple Bytes ................................................ 12
Read Operations ............................................................. 12
Current Address Read ............................................... 12
Random Read ........................................................... 12
Sequential Read ........................................................ 12
Serial Programming Interface
Timing Specifications .................................................... 13
Electrical Specifications ................................................ 14
Absolute Maximum Conditions .................................. 14
Operating Conditions ................................................. 14
Recommended Crystal Specifications ....................... 14
Electrical Characteristics ........................................... 15
Test Circuit ...................................................................... 15
Switching Characteristics .............................................. 16
Switching Waveforms .................................................... 17
Ordering Information ...................................................... 18
Possible Configurations ............................................. 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 2 of 22
CY22393 Automotive
Pin Configuration
Figure 1. 16-pin TSSOP pinout
Pin Definitions
Name
Pin Number
Description
CLKC
1
Configurable clock output C
VDD
2
Power supply
AGND
3
Analog ground
XTALIN
4
Reference crystal input or external reference clock input
XTALOUT
5
Reference crystal feedback
XBUF
6
Buffered reference clock output
CLKD
7
Configurable clock output D
CLKE
8
Configurable clock output E
CLKB
9
Configurable clock output B
CLKA
10
Configurable clock output A
GND
11
Ground
SDAT (S0)
12
Serial port data. S0 value latched during start-up
SCLK (S1)
13
Serial port clock. S1 value latched during start-up
AVDD
14
Analog power supply
S2/
SUSPEND
15
General-purpose input for frequency control; bit 2. Optionally, Suspend mode control input
SHUTDOWN/
OE
16
Places outputs in tristate condition and shuts down chip when LOW. Optionally, only places outputs
in tristate condition and does not shut down chip when LOW
Document Number: 001-73555 Rev. *E
Page 3 of 22
CY22393 Automotive
Functional Overview
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to the
cross point switch. The output of PLL1 is also sent to a /2, /3, or
/4 synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming or
by external CMOS inputs, S0, S1, and S2. See General-Purpose
Inputs on page 4 for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
cross point switch. The frequency of PLL2 is changed using
serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross point switch. The frequency of PLL3 is changed using
serial programming.
The oscillator inverter has programmable drive strength. This
enables maximum compatibility with crystals from various
manufacturers. Parallel resonant, fundamental mode crystals
should be used.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when nonlinear load
capacitance interacts with load, bias, supply, and temperature
changes. Nonlinear (FET gate) crystal load capacitors must not
be used for MPEG, communications, or other applications that
are sensitive to absolute frequency requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375 pF for a total crystal load range of 6 pF to
30 pF. Typical crystals have a CL specification in the range of
12 pF to 18 pF.
For driven clock inputs, the input load capacitors can be
bypassed. This allows the clock chip to accept driven frequency
inputs up to 166 MHz. If the application requires a driven input,
leave XTALOUT floating.
General-Purpose Inputs
Crystal Drive Level and Power
S2 is a general-purpose input that is programmed to enable two
frequency settings. The options that switch with this
general-purpose input are as follows: the frequency of PLL1, the
output divider of CLKB, and the output divider of CLKA.
Crystals are specified to accept a maximum drive level.
Generally, larger crystals can accept more power. For a specific
voltage swing, power dissipation in the crystal is proportional to
ESR and proportional to the square of the crystal frequency.
(Note that the actual ESR is sometimes much less than the value
specified by the crystal manufacturer.) Power is also almost
proportional to the square of CL.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start-up and used as the other two indices into
this array.
CLKA and CLKB have seven-bit dividers that point to one of the
two programmable settings (register 0 or register 1). Both clocks
share a single register control and both must be set to register 0,
or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0, 0, 0 to 1, 1, 1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be
glitch-free.
Crystal Input
The input crystal oscillator is an important feature of CY24293
because of its flexibility and performance features.
Document Number: 001-73555 Rev. *E
Power can be reduced to less than the DL specified in
Recommended Crystal Specifications on page 14 by selecting a
reduced frequency crystal with low CL and low R1 (ESR).
Digital VCXO
The serial programming interface is used to dynamically change
the capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency.
For special pullable crystals specified by Cypress, the
capacitance pull range is +150 ppm to –150 ppm from midrange.
Be aware that adjusting the frequency of the reference affects all
frequencies on all PLLs in a similar manner because all
frequencies are derived from the single reference.
Page 4 of 22
CY22393 Automotive
Output Configuration
Under normal operation there are four internal frequency
sources that are routed through a programmable cross point
switch to any of the four programmable 7-bit output dividers. The
four sources are: reference, PLL1, PLL2, and PLL3. The
following is a description of each output.
■
CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section General-Purpose Inputs on page 4
for more information.
■
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section General-Purpose Inputs on page 4
for more information.
■
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
■
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
■
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
■
XBUF is the buffered reference.
The clock outputs are designed to drive a single-point load with
a total lumped load capacitance of 15 pF. While driving multiple
loads is possible with the proper termination, it is generally not
recommended.
Power-Saving Features
The SHUTDOWN/OE input tristates the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, reference oscillator, and all other
active components. The resulting current on the VDD pins is less
than 5 mA (typical). Relock the PLLs after leaving the shutdown
mode.
Document Number: 001-73555 Rev. *E
The S2/SUSPEND input is configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs are shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
associated logic, while suspending an output simply forces a
tristate condition.
With the serial interface, each PLL and/or output is individually
disabled. This provides total control over the power savings.
Improving Jitter
Jitter Optimization Control is useful for mitigating problems
related to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs
(CLKA–CLKD). This prevents the output edges from aligning and
allows superior jitter performance.
Power Supply Sequencing
There are no power supply sequencing requirements. The part
is not fully operational until all VDD pins are brought up to the
voltages specified in the Operating Conditions on page 14.
All grounds must be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second-generation software application that
allows users to configure this device. The easy-to-use interface
offers complete control of the many features of this device
including, but not limited to, input frequency, PLL and output
frequencies, and different functional options. It checks the data
sheet frequency range limitations and automatically applies
performance tuning. CyClocksRT also has a power estimation
feature that allows you to see the power consumption of a
specific configuration. You can download a free copy of
CyberClocks that includes CyClocksRT on Cypress’s web site,
www.cypress.com.
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency rules
that are not documented in this datasheet, but are required for
proper operation of the device. Check these rules by using the
latest version of CyClocksRT.
Page 5 of 22
CY22393 Automotive
Device Programming
Part numbers starting with CY22392F are ‘field programmable’
devices. Field programmable devices are shipped
unprogrammed and must be programmed prior to installation on
a PCB. After a programming file (.jed) is created using the
CyberClocks software, devices can be programmed in small
quantities using the CY3672 programmer and CY3698[1]
adapter. Programming of the clock device should be done at
temperatures < 75 C. Volume programming is available through
Cypress Semiconductor’s value-added distribution partners or
by using third-party programmers from BP Microsystems, HiLo
Systems, and others. For sufficiently large volumes, Cypress can
supply pre-programmed devices with a part number extension
that is configuration-specific.
Junction Temperature Limitations
It is possible to program this family such that the maximum
junction temperature rating is exceeded. The package JA is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the junction
temperature and package power dissipation maximum ratings.
Dynamic Updates
The output divider registers are not synchronized with the output
clocks. Changing the divider value of an active output is likely
cause a glitch on that output.
CLKA and CLKB have two divider registers, selected by the
DivSel bit (which, in turn, is selected by S2, S1, and S0). This
allows the output divider value to change dynamically.
ClkE_Div[1:0]
CLKE has a simpler divider (see Table 1).
Table 1. ClkE Divider
ClkE_Div[1:0]
Clk{A–D}_Div[6:0]
Each of the four main output clocks (CLKA–CLKD) features a
7-bit linear output divider. Any divider setting between 1 and 127
may be used by programming the value of the desired divider
into this register. Odd divide values are automatically duty-cycle
corrected. Setting a divide value of zero powers down the divider
and forces the output to a tristate condition.
Off
01
PLL1 0 Phase/4
10
PLL1 0 Phase/2
11
PLL1 0 Phase/3
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1, PLL2,
and PLL3. Each PLL provides both positive and negative phased
outputs, for a total of seven clock sources (see Table 2). Note
that the phase is a relative measure of the PLL output phases.
No absolute phase relation exists at the outputs.
Table 2. Clock Source
Clk*_FS[2:0]
PLL1, CLKA, and CLKB each have multiple registers supplying
data. To program these resources safely, always program an
inactive register, and then transition to that register. This allows
these resources to stay active during programming.
Memory Bitmap Definitions
00
Clk*_FS[2:0]
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL can cause the PLL to try to lock
an out-of-bounds condition. Therefore, you must turn off the PLL
being programmed during the update. Do this by setting the
PLL*_En bit LOW.
The serial interface is active even with the SHUTDOWN/OE pin
LOW as the serial interface logic uses static components and is
completely self-timed. The part does not meet the IDDS current
limit with transitioning inputs.
ClkE Output
Clock Source
000
Reference Clock
001
Reserved
010
PLL1 0 Phase
011
PLL1 180 Phase
100
PLL2 0 Phase
101
PLL2 180 Phase
110
PLL3 0 Phase
111
PLL3 180 Phase
Xbuf_OE
This bit enables the XBUF output when HIGH.
PdnEn
This bit selects the function of the SHUTDOWN/OE pin. When
this bit is HIGH, the pin is an active LOW shutdown control. When
this bit is LOW, this pin is an active HIGH output enable control.
Clk*_ACAdj[1:0]
These bits modify the output predrivers, changing the duty cycle
through the pads. These are nominally set to 01, with a higher
value shifting the duty cycle higher. The performance of the
nominal setting is guaranteed.
Note
1. CY3698 only supports programming of only the 16-pin TSSOP package.
Document Number: 001-73555 Rev. *E
Page 6 of 22
CY22393 Automotive
Clk*_DCAdj[1:0]
These bits modify the DC drive of the outputs. The performance
of the nominal setting is guaranteed.
DivSel
Table 3. Output Drive Strength
Clk*_DCAdj[1:0]
a divider setting of zero (off). Because the PLL1_En bit is
dynamic, internal logic automatically turns off dependent outputs
when PLL1_En goes LOW.
Output Drive Strength
00
–30% of nominal
01
Nominal
10
+15% of nominal
11
+50% of nominal
This bit controls which register is used for the CLKA and CLKB
dividers.
OscCap[5:0]
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
C LOAD = 6pF + OscCap 0.375pF
PLL*_Q[7:0]
Equation 2
Set to zero for external reference clock.
PLL*_P[9:0]
OscDrv[1:0]
PLL*_P0
These are the 8-bit Q value and 11-bit P values that determine
the PLL frequency. The formula is:
PT
F PLL = F REF -------
QT
Equation 1
P T = 2 P + 3 + PO
QT = Q + 2
These bits control the crystal oscillator gain setting. These must
always be set according to Table 5. The parameters are the
Crystal Frequency, Internal Crystal Parasitic Resistance
(equivalent series resistance), and the OscCap setting during
crystal start-up, which occurs when power is applied, or after
shutdown is released. If in doubt, use the next higher setting.
Table 5. Crystal Oscillator Gain Settings
OscCap
00H–20H
Crystal Freq\ R 30
PLL*_LF[2:0]
These bits adjust the loop filter to optimize the stability of the PLL.
Table 4 can be used to guarantee stability. However,
CyClocksRT uses a more complicated algorithm to set the loop
filter for enhanced jitter performance. Use the Print Preview
function in CyClocksRT to determine the charge pump settings
for optimal jitter performance.
20H–30H
30H–40H
60
30
60
30
60
8–15 MHz
00
01
01
10
01
10
15–20 MHz
01
10
01
10
10
10
20–25 MHz
01
10
10
10
10
11
25–30 MHz
10
10
10
11
11
NA
For external reference, the use Table 6.
Table 4. Loop Filter Settings
Table 6. Osc Drv for External Reference
PLL*_LF[2:0]
PT Min
PT Max
000
16
231
External Freq (MHz)
1–25
25–50
50–90
90–166
OscDrv[1:0]
00
01
10
11
001
232
626
010
627
834
011
835
1043
100
1044
1600
Reserved
These bits must be programmed LOW for proper operation of the
device.
PLL*_En
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must have
Document Number: 001-73555 Rev. *E
Page 7 of 22
CY22393 Automotive
Serial Programming Bitmaps – Summary Table 1
Addr
DivSel
b7
08H
0
ClkA_FS[0]
b6
b5
b4
b3
09H
1
ClkA_FS[0]
ClkA_Div[6:0]
0AH
0
ClkB_FS[0]
ClkB_Div[6:0]
0BH
1
ClkB_FS[0]
ClkB_Div[6:0]
0CH
–
ClkC_FS[0]
ClkC_Div[6:0]
0DH
–
ClkD_FS[0]
0EH
–
ClkD_FS[2:1]
ClkC_FS[2:1]
0FH
–
Clk{C,X}_ACAdj[1:0]
Clk{A,B,D,E}_ACAdj[1:0]
10H
–
ClkX_DCAdj[1]
Clk{D,E}_DCAdj[1]
b1
b0
ClkD_Div[6:0]
ClkB_FS[2:1]
PdnEn
11H
–
PLL2_Q[7:0]
–
PLL2_P[7:0]
13H
–
14H
–
15H
–
16H
–
17H
–
PLL2_En
Xbuf_OE
ClkC_DCAdj[1]
12H
Reserved
b2
ClkA_Div[6:0]
PLL2_LF[2:0]
ClkA_FS[2:1]
ClkE_Div[1:0]
Clk{A,B}_DCAdj[1]
PLL2_PO
PLL2_P[9:8]
PLL3_PO
PLL3_P[9:8]
PLL3_Q[7:0]
PLL3_P[7:0]
Reserved
PLL3_En
Document Number: 001-73555 Rev. *E
PLL3_LF[2:0]
Osc_Cap[5:0]
Osc_Drv[1:0]
Page 8 of 22
CY22393 Automotive
Serial Programming Bitmaps – Summary Table 2
Addr
S2 (1, 0)
40H
000
b7
b6
DivSel
PLL1_En
001
DivSel
PLL1_En
010
DivSel
PLL1_En
011
PLL1_P[9:8]
PLL1_LF[2:0]
PLL1_PO
PLL1_P[9:8]
PLL1_LF[2:0]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_P[7:0]
4BH
DivSel
PLL1_En
100
PLL1_LF[2:0]
PLL1_Q[7:0]
4DH
PLL1_P[7:0]
4EH
DivSel
PLL1_En
101
PLL1_LF[2:0]
PLL1_Q[7:0]
50H
PLL1_P[7:0]
51H
DivSel
PLL1_En
110
PLL1_LF[2:0]
PLL1_Q[7:0]
53H
PLL1_P[7:0]
54H
DivSel
PLL1_En
111
PLL1_LF[2:0]
PLL1_Q[7:0]
56H
57H
PLL1_PO
PLL1_Q[7:0]
4AH
55H
PLL1_LF[2:0]
PLL1_P[7:0]
48H
52H
b0
PLL1_Q[7:0]
47H
4FH
b1
PLL1_P[7:0]
45H
4CH
b2
PLL1_Q[7:0]
44H
49H
b3
PLL1_P[7:0]
42H
46H
b4
PLL1_Q[7:0]
41H
43H
b5
PLL1_P[7:0]
DivSel
PLL1_En
Document Number: 001-73555 Rev. *E
PLL1_LF[2:0]
Page 9 of 22
CY22393 Automotive
Serial Bus Programming Protocol and Timing
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit.
The CY22393 has a 2-wire serial interface for in-system
programming. They use the SDAT and SCLK pins, and operate
up to 400 kbit/s in Read or Write mode. Except for the data hold
time, it is compliant with the I2C bus standard. The basic Write
serial format is as follows:
The basic serial format is illustrated in Figure 2.
Figure 2. Data Frame Architecture
SDAT Write
Multiple
Contiguous
Registers
1 Bit
1 Bit Slave
ACK
R/W = 0
7-bit
Device
Address
1 Bit
Slave
ACK
8-bit
Register
Address
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+1)
8-bit
Register
Data
(XXH+2)
1 Bit
Slave
ACK
1 Bit
Slave
ACK
8-bit
Register
Data
(FFH)
1 Bit
Slave
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
SDAT Read
Current
Address
Read Start Signal
SDAT Read
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 1 ACK
7-bit
Device
Address
1 Bit
Slave
ACK
1 Bit
Master
NACK
8-bit
Register
Data
Stop Signal
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
1 Bit
Slave
ACK
8-bit
Register
Address
(XXH)
1 Bit
Master
ACK
7-bit
Device
Address
+R/W=1
8-bit
Register
Data
(XXH)
1 Bit
Master
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Master
ACK
8-bit
Register
Data
(FFH)
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
NACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Document Number: 001-73555 Rev. *E
Page 10 of 22
CY22393 Automotive
Default Startup Condition for the CY22393
Device Address
The default (programmed) condition of CY24293 is set by the
distributor, who programs the device using a customer-specified
JEDEC file produced by CyClocksRT, Cypress’s proprietary
development software. Parts shipped by the factory are blank
and unprogrammed. In this condition, all bits are set to 0, all
outputs are tristated, and the crystal oscillator circuit is active.
The device address is a 7-bit value that is configured during Field
Programming. By programming different device addresses, two
or more parts are connected to the serial interface and can be
independently controlled. The device address is combined with
a read/write bit as the LSB and is sent after each start bit.
While users can develop their own subroutine to program any or
all of the individual registers as described in the following pages,
it may be easier to simply use CyClocksRT to produce the
required register setting file.
The default serial interface address is 69H, but there must not
be a conflict with any other devices in your system. This can also
be changed using CyClocksRT.
Data Valid
Data is valid when the clock is HIGH, and can only be
transitioned when the clock is LOW as illustrated in Figure 3.
Figure 3. Data Valid and Data Transition Periods
Data Valid
Transition
to next Bit
SDAT
tSU:DAT
tHD:DAT
tHIGH
VIH
SCLK
tLOW
VIL
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 4.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by the register address (eight bits) and register data
(eight bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Figure 4. Start and Stop Frame
SDAT
START
Document Number: 001-73555 Rev. *E
Transition
to next Bit
SCLK
STOP
Page 11 of 22
CY22393 Automotive
Acknowledge Pulse
During Write Mode, the CY22393 responds with an
Acknowledge pulse after every eight bits. To do this, it pulls the
SDAT line LOW during the N*9th clock cycle, as illustrated in
Figure 5. (N = the number of bytes transmitted). During Read
Mode, the master generates the acknowledge pulse after the
data packet is read.
Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data)
SDAT
+
START
DA6
DA5 DA0
SCLK
+
R/W
+
ACK
RA7
RA6 RA1
RA0
ACK
D7
+
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition. Instead, the master
sends multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, the same as
after the first byte, and accepts data until the STOP condition
responds to the acknowledge bit. When receiving multiple bytes,
the CY22393 internally increment the register address.
Read Operations
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Current Address Read
The CY22393 have an onboard address counter that retains “1”
more than the address of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation returns the value stored in location ‘n+1’. When the
CY22393 receives the slave address with the R/W bit set to a ‘1’,
Document Number: 001-73555 Rev. *E
+
D6
D1
D0
ACK
STOP
+
it issues an acknowledge and transmit the 8-bit word. The master
device does not acknowledge the transfer, but generates a
STOP condition, which causes the CY22393 to stop
transmission.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. Do this by sending the address to the
CY22393 as part of a write operation. After the word address is
sent, the master generates a START condition following the
acknowledge. This terminates the write operation before any
data is stored in the address, but not before setting the internal
address pointer. Next, the master reissues the control byte with
the R/W byte set to ‘1’. The CY22393, then, issues an
acknowledge and transmits the 8-bit word. The master device
does not acknowledge the transfer, but generates a STOP
condition which causes CY22393 to stop transmission.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmitting the first 8-bit data word. This
action increments the internal address pointer, and subsequently
outputs the next 8-bit data word. By continuing to issue
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. Note that
register addresses outside of 08H to 1BH and 40H to 57H can
be read from but are not real registers and do not contain
configuration information. When the internal address pointer
points to the FFH register, after the next increment, the pointer
points to the 00H register.
Page 12 of 22
CY22393 Automotive
Serial Programming Interface Timing Specifications
Parameter
Description
Min
Max
Unit
–
400
kHz
Hold time START condition
0.6
–
s
tLOW
Low period of the SCLK clock
1.3
–
s
tHIGH
High period of the SCLK clock
0.6
–
s
tSU:STA
Setup time for a repeated START condition
0.6
–
s
tHD:DAT
Data hold time
100
–
ns
tSU:DAT
Data setup time
100
–
ns
tR
Rise time
–
300
ns
tF
Fall time
–
300
ns
tSU:STO
Setup time for STOP condition
0.6
–
s
tBUF
Bus-free time between STOP and START conditions
1.3
–
s
fSCLK
Frequency of SCLK
tHD:STA
Figure 6. Definition for Timing on the Serial BUS
SDAT
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tr
tBUF
SCLK
S
tHD;STA
tHD;DAT
Document Number: 001-73555 Rev. *E
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Page 13 of 22
CY22393 Automotive
Electrical Specifications
Maximum programming cycles ........................................100
Absolute Maximum Conditions
Package power dissipation (Automotive-A Grade) .. 350 mW
Supply voltage .............................................–0.5 V to +7.0 V
DC input voltage ......................... –0.5 V to + (AVDD + 0.5 V)
Storage temperature ................................ –65 °C to +125 °C
Junction temperature
Automotive-A Grade ................................................. 125 C
Automotive-A E Grade ............................................... 150 C
Data retention at TJ = 125 C ...............................> 10 years
Data retention at TJ = 150 C .................................> 2 years
Package power dissipation (Automotive-E Grade) .. 217 mW
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2000 V
Latch-up (per JEDEC 17) ................................... > ±200 mA
Stresses exceeding absolute maximum conditions may cause
permanent damage to the device. These conditions are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in the operation
sections of this datasheet is not implied. Extended exposure to
absolute maximum conditions may affect reliability.
Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
3.135
3.3
3.465
V
–
85
C
–
125
C
VDD/AVDD
Supply voltage
TA
Automotive-A Grade operating temperature, Ambient
–40
TA
Automotive-E Grade operating temperature, Ambient
-40
CLOAD_OUT
Maximum load capacitance
–
–
15
pF
fREF
External reference crystal
8
–
30
MHz
External reference clock[2], Automotive
1
–
150
MHz
Min
Typ
Max
Unit
Recommended Crystal Specifications
Parameter
Description
FNOM
Nominal crystal frequency
CLNOM
Nominal load capacitance
R1
Equivalent series resistance
(ESR)
DL
Crystal drive level
Description
Parallel resonance, fundamental mode
8
–
30
MHz
8
–
20
pF
Fundamental mode
–
–
50
No external series resistor assumed
–
0.5
2
mW
Notes
2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
Document Number: 001-73555 Rev. *E
Page 14 of 22
CY22393 Automotive
Electrical Characteristics
3.3 V
Parameter
IOH
Conditions [3]
Description
Output high current
[4, 5]
[4, 5]
IOL
Output low current
CXTAL_MIN
Crystal load capacitance [4]
CXTAL_MAX
Crystal load capacitance
CIN
Input pin capacitance
[3]
[4]
Min
Typ
Max
Unit
VOH = VDD – 0.5 V, VDD = 3.3 V
12
24
–
mA
VOL = 0.5 V, VDD = 3.3 V
12
24
–
mA
Capload at minimum setting
–
6
–
pF
Capload at maximum setting
–
30
–
pF
Except crystal pins
–
7
–
pF
–
VIH
High-level input voltage
CMOS levels,% of AVDD
70%
VIL
Low-level input voltage
CMOS levels,% of AVDD
–
IIH
Input high current
VIN = AVDD – 0.3 V
–
IIL
Input low current
VIN = +0.3 V
–
IOZ
Output leakage current
Three-state outputs (OE = Low)
–
10
A
IDD
Total power supply current
3.3-V power supply; 2 outputs at 20 MHz;
4 outputs at 40 MHz [6, 7]
–
50
–
mA
3.3-V power supply; 2 outputs at 166 MHz;
4 outputs at 83 MHz [6, 7]
–
100
–
mA
Shutdown active
–
5
20
A
IDDS
Total power supply current in
shutdown mode
–
AVDD
30%
AVDD
100 MHz or divider = 1, measured at
VDD/2
40%
50%
60%
Output clock rise time, 20% to 80% of VDD
0.75
1.4
–
V/ns
Output clock fall time, 20% to 80% of VDD
0.75
1.4
–
V/ns
Time for output to enter or leave three-state
mode after SHUTDOWN/OE switches
–
150
300
ns
Output frequency
[8, 9]
Clock output limit, CMOS, Automotive
Output duty cycle
[8, 10]
t3
Rising edge slew rate [8]
t4
[8]
Falling edge slew rate
[8]
t5
Output three-state timing
t6
Clock jitter [8, 9]
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–
400
–
ps
t7
Lock time [8]
PLL lock time from power-up
–
1.0
3
ms
Notes
8. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
9. Reference output duty cycle depends on XTALIN duty cycle.
10. Jitter varies significantly with configuration. Reference output jitter depends on XTALIN jitter and edge rate.
Document Number: 001-73555 Rev. *E
Page 16 of 22
CY22393 Automotive
Switching Waveforms
Figure 8. All Outputs, Duty Cycle and Rise and Fall Time
t1
t2
OUTPUT
t3
t4
Figure 9. Output Tristate Timing
OE
t5
t5
ALL
TRISTATE
OUTPUTS
Figure 10. CLK Output Jitter
t6
CLK
OUTPUT
Figure 11. CPU Frequency Change
SELECT
OLD SELECT
Fold
NEW SELECT STABLE
t7
Fnew
CPU
Document Number: 001-73555 Rev. *E
Page 17 of 22
CY22393 Automotive
Ordering Information
Ordering Code
Package Type
Product Flow
Pb-free
CY22393FXA
16-pin TSSOP
Automotive-A Grade, –40 °C to 85 °C
CY22393FXAT
16-pin TSSOP - Tape and Reel
Automotive-A Grade, –40 °C to 85 °C
CY22393FXE
16-pin TSSOP
Automotive-E Grade, –40 °C to 125 °C
CY22393FXET
16-pin TSSOP - Tape and Reel
Automotive-E Grade, –40 °C to 125 °C
Programmer
CY3675-CLKMAKER1
Programmer
Possible Configurations
Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information
Ordering Code
Package Type
Product Flow
Pb-Free
CY22393ZXA-xxx
16-pin TSSOP
Automotive-A Grade, –40 °C to 85 °C
CY22393ZXA-xxxT
16-pin TSSOP - Tape and Reel
Automotive-A Grade, –40 °C to 85 °C
CY22393ZXE-xxx
16-pin TSSOP
Automotive-E Grade, –40 °C to 125 °C
CY22393ZXE-xxxT
16-pin TSSOP - Tape and Reel
Automotive-E Grade, –40 °C to 125 °C
Ordering Code Definitions
CY 22393
F
X
X
X -xxx T
T = tape and reel, blank = tube
Configuration specific identifier (factory programmed)
Temperature Range: X = A or E
A = Automotive-A Grade = –40 C to 85 C,
E = Automotive-E Grade = –40 C to 125 C
Pb-free
Package: X = blank or Z
blank = 16-pin TSSOP (field programmable)
Z = 16-pin TSSOP (factory programmed)
X = F or blank
F = field programmable; blank = factory programmed
Part Identifier:
22393: 3.3 V CMOS clock generator
Company ID: CY = Cypress
Document Number: 001-73555 Rev. *E
Page 18 of 22
CY22393 Automotive
Package Diagram
Figure 12. 16-pin TSSOP 4.40 mm Body Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 001-73555 Rev. *E
Page 19 of 22
CY22393 Automotive
Acronyms
Document Conventions
Table 7. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 8. Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
ESR
Equivalent Series Resistance
°C
FAE
Field Application Engineer
kHz
kilohertz
FET
Field Effect Transistor
MHz
megahertz
JEDEC
Joint Electron Devices Engineering Council
A
microampere
LSB
Least Significant Bit
F
microfarad
LVTTL
Low Voltage Transistor-Transistor Logic
MPEG
Motion Picture Experts Group
OE
Output Enable
PLL
Phase-Locked Loop
TSSOP
Thin Shrink Small Outline Package
VCXO
Voltage-Controlled Crystal Oscillator
Document Number: 001-73555 Rev. *E
Symbol
Unit of Measure
degree Celsius
s
microsecond
mA
milliampere
mm
millimeter
ms
millisecond
mW
milliwatt
ns
nanosecond
ohm
%
percent
pF
picofarad
ppm
parts per million
ps
picosecond
V
volt
Page 20 of 22
CY22393 Automotive
Document History Page
Document Title: CY22393 Automotive, Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Document Number: 001-73555
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
3416122
PURU
11/14/2011
New data sheet.
*A
3693908
PURU
07/26/2012
Updated Ordering Information:
Updated part numbers (Added CY22393 Automotive-E Grade Devices).
*B
4337034
CINM
04/23/2014
Changed status from Preliminary to Final.
Updated Features:
Added “AEC-Q100 Qualified”.
Added “Available in Automotive-A and Automotive-E grade”.
Added Device Programming.
Updated Electrical Specifications:
Updated Absolute Maximum Conditions:
Added junction temperature for Automotive-A and Automotive-E grade.
Added data retention at TJ = 150 C.
Added package power dissipation for Automotive-A and Automotive-E grade.
Updated Electrical Characteristics:
Added Note 5 and referred the same note in Description of IOH and IOL
parameters.
Added Notes 6, 7 and referred the same notes in Condition of IDD parameter.
Updated to new template.
*C
4580394
TAVA
12/10/2014
Updated Serial Bus Programming Protocol and Timing:
Updated Figure 2.
Updated Package Diagram:
spec 51-85091 – Changed revision from *D to *E.
Completing Sunset Review.
*D
4724475
PSR
04/15/2015
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Serial Bus Programming Protocol and Timing:
Removed figure “Data Transfer Sequence on the Serial Bus”.
Updated Data Valid:
Updated Figure 3.
Updated Serial Programming Interface Timing Specifications:
Updated entire table.
Added Figure 6.
Updated to new template.
*E
6054859
PAWK
02/01/2018
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Document Number: 001-73555 Rev. *E
Page 21 of 22
CY22393 Automotive
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-73555 Rev. *E
CyClocksRT is a trademark of Cypress Semiconductor Corporation.
Revised February 1, 2018
Page 22 of 22
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