CY2308SI-2T

CY2308 3.3V Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see “Available CY2308 Configurations” on page 3 Multiple low skew outputs Two banks of four outputs, three-stateable by two select inputs 10 MHz to 133 MHz operating range 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz) Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP 3.3V operation Industrial Temperature available The CY2308 has two banks of four outputs each that is controlled by the Select inputs as shown in the table “Select Input Decoding” on page 2”. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. The CY2308 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off resulting in less than 50 μA of current draw. The PLL shuts down in two additional cases as shown in the table “Select Input Decoding” on page 2. Multiple CY2308 devices accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is less than 700 ps. The CY2308 is available in five different configurations as shown in the table “Available CY2308 Configurations” on page 3. The CY2308–1 is the base part where the output frequencies equal the reference if there is no counter in the feedback path. The CY2308–1H is the high drive version of the –1 and rise and fall times on this device are much faster. The CY2308–2 enables the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depend on the output that drives the feedback pin. The CY2308–3 enables the user to obtain 4X and 2X frequencies on the outputs. The CY2308–4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile and is used in a variety of applications. The CY2308–5H is a high drive version with REF/2 on both banks. Functional Description The CY2308 is a 3.3V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven into the FBK pin and obtained from one of the outputs. The input-to-output skew is less than 350 ps and output-to-output skew is less than 200 ps. Logic Block Diagram /2 REF PLL MUX FBK CLKA1 CLKA2 CLKA3 CLKA4 /2 Extra Divider (–3, –4) Extra Divider (–5H) S2 S1 Select Input Decoding /2 CLKB1 CLKB2 CLKB3 Extra Divider (–2, –3) CLKB4 Cypress Semiconductor Corporation Document Number: 38-07146 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 19, 2008 [+] Feedback CY2308 Pinouts Figure 1. Pin Diagram - 16 Pin SOIC (Top view) REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Table 1. Pin Definitions - 16 Pin SOIC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF [1] [2] [2] Signal CLKA1 CLKA2 VDD GND CLKB1[2] CLKB2[2] S2[3] S1[3] CLKB3[2] CLKB4 GND VDD CLKA3[2] CLKA4[2] FBK [2] Description Input reference frequency, 5V tolerant input Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input Select Input Decoding S2 0 0 1 1 S1 0 1 0 1 CLOCK A1–A4 Tri-State Driven Driven[4] Driven CLOCK B1–B4 Tri-State Tri-State Driven [4] Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N Driven Notes 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs. 4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0. Document Number: 38-07146 Rev. *F Page 2 of 14 [+] Feedback CY2308 Available CY2308 Configurations Device CY2308–1 CY2308–1H CY2308–2 CY2308–2 CY2308–3 CY2308–3 CY2308–4 CY2308–5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference/2 Reference Reference or Reference[5] 2 X Reference 2 X Reference Reference /2 Zero Delay and Skew Control Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK pin and CLKA/CLKB Pins To close the feedback loop of the CY2308, the FBK pin is driven from any of the eight available output pins. The output driving the FBK pin drives a total load of 7 pF plus any additional load that it drives. The relative loading of this output to the remaining outputs adjusts the input-output delay. This is shown in the Figure 2. For applications requiring zero input-output delay, all outputs including the one providing feedback is equally loaded. If input-output delay adjustments are required, use the Zero Delay and Skew Control graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, outputs are loaded equally. For further information on using CY2308, refer to the application note “CY2308: Zero Delay Buffer.” Note 5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2. Document Number: 38-07146 Rev. *F Page 3 of 14 [+] Feedback CY2308 Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V DC Input Voltage REF ........................................... –0.5 to 7V Storage Temperature .................................. –65°C to +150°C Junction Temperature .................................................. 150°C Static Discharge Voltage (MIL-STD-883, Method 3015).................................... >2000V Operating Conditions for Commercial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance[6] Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.0 0 – – – 0.05 Max 3.6 70 30 15 7 50 Unit V °C pF pF pF ms Electrical Characteristics for Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[7] VIN = 0V VIN = VDD IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (–1H, –5H) IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –5H) Unloaded outputs, 100 MHz REF, Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (–1, –2, –3, –4) Unloaded outputs, 33 MHz REF (–1, –2, –3, –4) Test Conditions Min – 2.0 – – – 2.4 – – – – – Max 0.8 – 50.0 100.0 0.4 – 25.0 45.0 70.0 (–1H,–5H) 32.0 18.0 Unit V V μA μA V V μA mA mA mA mA Output HIGH Voltage[7] Power Down Supply Current REF = 0 MHz Supply Current Switching Characteristics for Commercial Temperature Devices Parameter[8] t1 t1 t1 tPD t3 Name Output Frequency Output Frequency Output Frequency Duty = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Cycle[7, 8] Rise Time[7, 8] (–1, –2, –3, –4) Test Conditions 30-pF load, All devices 20-pF load, –1H, –5H devices[9] 15-pF load, –1, –2, –3, –4 devices Measured at 1.4V, FOUT = 66.66 MHz 30-pF load Measured between 0.8V and 2.0V, 30-pF load Min 10 10 10 40.0 – Typ. – – – 50.0 – Max 100 133.3 133.3 60.0 2.20 Unit MHz MHz MHz % ns Note 6. Applies to both Ref Clock and FBK. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters are specified with loaded outputs. 9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz. Document Number: 38-07146 Rev. *F Page 4 of 14 [+] Feedback CY2308 Switching Characteristics for Commercial Temperature Devices (continued) Parameter[8] t3 t3 t4 t4 t4 t5 Name Rise Time (–1, –2, –3, –4) Rise Time[7, 8] (–1H, –5H) Fall Time[7, 8] (–1, –2, –3, –4) Fall Time[7, 8] (–1, –2, –3, –4) Fall Time[7, 8] (–1H, –5H) Output to Output Skew on same Bank (–1, –2, –3, –4)[7, 8] [7, 8] Test Conditions Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load All outputs equally loaded Min – – – – – – Typ. – – – – – – Max 1.50 1.50 2.20 1.50 1.25 200 Unit ns ns ns ns ns ps Output to Output Skew (–1H, All outputs equally loaded –5H) Output Bank A to Output Bank B Skew (–1, –4, –5H) Output Bank A to Output Bank B Skew (–2, –3) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge[7, 8] Device to Device Skew[7, 8] Output Slew Rate[7, 8] Cycle to Cycle Jitter[7, 8] (–1, –1H, –4, –5H) All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on –1H, –5H device using Test Circuit 2 Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 133.3 MHz, loaded outputs, 15-pF load tJ Cycle to Cycle Jitter[7, 8] (–2, –3) Measured at 66.67 MHz, loaded outputs 30-pF load Measured at 66.67 MHz, loaded outputs 15-pF load tLOCK PLL Lock Time[7, 8] Stable power supply, valid clocks presented on REF and FBK pins – – – – – 1 – – – – 0 0 – 75 200 200 400 ±250 700 ps ps ps ps ps V/ns 200 ps – – 200 ps – – 100 ps – – 400 ps – – 400 ps – – 1.0 ms Document Number: 38-07146 Rev. *F Page 5 of 14 [+] Feedback CY2308 Operating Conditions for Industrial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance[6] Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.0 –40 – – – 0.05 Max 3.6 85 30 15 7 50 Unit V °C pF pF pF ms Electrical Characteristics for Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[7, 8] VIN = 0V VIN = VDD IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (–1H, –5H) IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –5H) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (–1, –2, –3, –4) Unloaded outputs, 66 MHz REF (–1, –2, –3, –4) Test Conditions Min – 2.0 – – – 2.4 – – – – – Max 0.8 – 50.0 100.0 0.4 – 25.0 45.0 70(–1H,–5H) 35.0 20.0 Unit V V μA μA V V μA mA mA mA mA Output HIGH Voltage[7, 8] Power Down Supply Current Supply Current Switching Characteristics for Industrial Temperature Devices Parameter[8] t1 t1 t1 tPD t3 t3 t3 t4 t4 t4 Name Output Frequency Output Frequency Output Frequency Duty Cycle = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) [7, 8] Test Conditions 30 pF load, All devices 20 pF load, –1H, –5H devices [9] Min 10 10 10 40.0 – – – – – – Typ – – – 50.0 – – – – – – Max 100 133.3 133.3 60.0 2.50 1.50 1.50 2.50 1.50 1.25 Unit MHz MHz MHz % ns ns ns ns ns ns 15 pF load, –1, –2, –3, –4 devices Measured at 1.4V, FOUT = 66.66 MHz 30 pF load Measured between 0.8V and 2.0V, 30 pF load Measured between 0.8V and 2.0V, 15 pF load Measured between 0.8V and 2.0V, 30 pF load Measured between 0.8V and 2.0V, 30 pF load Measured between 0.8V and 2.0V, 15 pF load Measured between 0.8V and 2.0V, 30 pF load Rise Time[7, 8] (–1, –2, –3, –4) Rise Time[7, 8] (–1, –2, –3, –4) Rise Time[7, 8] (–1H, –5H) Fall Time[7, 8] (–1, –2, –3, –4) Fall Time[7, 8] (–1, –2, –3, –4) Fall Time[7, 8] (–1H, –5H) Document Number: 38-07146 Rev. *F Page 6 of 14 [+] Feedback CY2308 Switching Characteristics for Industrial Temperature Devices (continued) Parameter[8] t5 Name Test Conditions Min – – – – – – 1 – – – – Typ – – – – 0 0 – 75 – – – Max 200 200 200 400 ±250 700 – 200 200 100 400 Unit ps ps ps ps ps ps V/ns ps ps ps ps All outputs equally loaded Output to Output Skew on same Bank (–1, –2, –3, –4)[7, 8] Output to Output Skew (–1H, –5H) All outputs equally loaded Output Bank A to Output Bank All outputs equally loaded B Skew (–1, –4, –5H) Output Bank A to Output Bank All outputs equally loaded B Skew (–2, –3) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge[78] Device to Device Skew[7, 8] Output Slew Rate[7, 8] Cycle to Cycle Jitter[7, 8] (–1, –1H, –4, –5H) Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on –1H, –5H device using Test Circuit 2 Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load tJ Cycle to Cycle Jitter[7, 8] (–2, –3) Measured at 66.67 MHz, loaded outputs 30 pF load Measured at 66.67 MHz, loaded outputs 15 pF load tLOCK PLL Lock Time[7, 8] Stable power supply, valid clocks presented on REF and FBK pins – – 400 ps – – 1.0 ms Switching Waveforms Figure 3. Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V Figure 4. All Outputs Rise/Fall Time 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V OUTPUT Document Number: 38-07146 Rev. *F Page 7 of 14 [+] Feedback CY2308 Switching Waveforms (continued) Figure 5. Output-Output Skew OUTPUT 1.4V OUTPUT t5 1.4V Figure 6. Input-Output Propagation Delay INPUT VDD/2 FBK t6 VDD/2 Figure 7. Device-Device Skew FBK, Device 1 VDD/2 FBK, Device 2 t7 VDD/2 Document Number: 38-07146 Rev. *F Page 8 of 14 [+] Feedback CY2308 Typical Duty Cycle[10] and IDD Trends[11] for CY2308–1,2,3,4 Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C) 60 58 56 Duty Cycle (% ) Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) 60 58 56 Duty Cycle (% ) 54 52 50 48 46 44 42 33 M Hz 66 M Hz 100 MH z 133 MH z 33 MHz 66 MHz 100 MHz 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V) 60 58 56 Duty Cycle (%) Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V) 60 58 56 Duty Cycle (%) -40C 0C 25C 70C 85C 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 -40C 0C 25C 70C 85C IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) 140 120 100 80 60 40 20 0 0 2 4 6 8 N umb er o f Lo ad ed Out p ut s 33 M Hz 66 M Hz 100 M Hz IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 140 120 100 80 60 40 20 0 0 2 4 6 8 33 M Hz 66 M Hz 100 M Hz N umb er o f Lo ad ed Out p ut s Notes 10. Duty Cycle is taken from typical chip measured at 1.4V. 11. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = number of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz). Document Number: 38-07146 Rev. *F Page 9 of 14 [+] Feedback CY2308 Typical Duty Cycle[10] and IDD Trends[11] for CY2308–1H, 5H Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C) 60 58 56 Duty Cycle (% ) Duty Cycle (% ) 60 58 56 54 52 50 48 46 44 42 40 33 M Hz 66 M Hz 100 MH z 133 MH z Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V) 60 58 56 Duty Cycle (%) 60 60 58 58 56 56 Duty Cycle Vs Frequency Duty Cycle Vs VDD (for 15 pF Loads over Temperature - 25C) (for 15 pF Loads over Frequency - 3.3V,3.3V) Duty Cycle (% ) Duty Cycle (%) 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 -40C 0C 25C 70C 85C 54 54 52 52 50 50 48 48 46 46 44 44 42 42 40 40 20 3 40 3.1 60 3.2 80 3.3 Frequency (MHz) VDD (V) 100 3.4 120 3.5 140 3.6 -40C 33 M Hz 0C 66 M Hz 25C 100 MH z 70C 133 MH z 85C IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) 140 120 100 80 60 40 20 0 0 2 4 6 8 20 0 0 N u m b e r o f L o a d e d Ou t p u t s 33 MHz 66 MHz 100 MHz 140 120 100 IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 33 MHz 80 60 40 66 MHz 100 MHz 2 4 6 8 N u m b e r o f L o a d e d Ou t p u t s Document Number: 38-07146 Rev. *F Page 10 of 14 [+] Feedback CY2308 Test Circuits Test Circuit 1 VDD 0.1 μ F Outputs V DD 0.1 μ F GND GND 0.1 μ F CLK OUT C LOAD Test Circuit 2 V DD 0.1 μF Outputs 1 KΩ V DD GND GND 1 KΩ CLK out 10 pF Test Circuit for all parameters except t8 Test Circuit for t8, Output slew rate on –1H, –5 device Ordering Information Ordering Code CY2308SC–1[12] CY2308SC–1T[12] CY2308SI–1[12] CY2308SI–1T[12] CY2308SC–1H[12] CY2308SC–1HT[12] CY2308SI–1H[12] CY2308SI–1HT[12] CY2308ZC–1H[12] CY2308ZC–1HT[12] CY2308ZI–1H[12] CY2308ZI–1HT[12] CY2308SC–2[12] CY2308SC–2T[12] CY2308SI–2[12] CY2308SI–2T[12] CY2308SC–3[12] CY2308SC–3T[12] CY2308SC–4[12] CY2308SC–4T[12] Package Type 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil TSSOP 16-pin 150 mil TSSOP - Tape and Reel 16-pin 150 mil TSSOP 16-pin 150 mil TSSOP - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Note 12. Not recommended for new designs. Document Number: 38-07146 Rev. *F Page 11 of 14 [+] Feedback CY2308 Ordering Information (continued) Ordering Code Pb-Free CY2308SXC–1 CY2308SXC–1T CY2308SXI–1 CY2308SXI–1T CY2308SXC–1H CY2308SXC–1HT CY2308SXI–1H CY2308SXI–1HT CY2308ZXC–1H CY2308ZXC–1HT CY2308ZXI–1H CY2308ZXI–1HT CY2308SXC–2 CY2308SXC–2T CY2308SXI–2 CY2308SXI–2T CY2308SXC–3 CY2308SXC–3T CY2308SXI–3 CY2308SXI–3T CY2308SXC–4 CY2308SXC–4T CY2308SXI–4 CY2308SXI–4T CY2308SXC–5H] CY2308SXC–5HT CY2308SXI–5H CY2308SXI–5HT 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil TSSOP 16-pin 150 mil TSSOP - Tape and Reel 16-pin 150 mil TSSOP 16-pin 150 mil TSSOP - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC -Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel 16-pin 150 mil SOIC 16-pin 150 mil SOIC - Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package Type Operating Range Document Number: 38-07146 Rev. *F Page 12 of 14 [+] Feedback CY2308 Package Drawings and Dimensions 16 Lead (150 Mil) SOIC 8 Figure 7. 16-Pin (150 Mil) SOIC S16.15 PIN 1 ID 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B Figure 8. 16-Pin TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] 51-85091-*A Document Number: 38-07146 Rev. *F Page 13 of 14 [+] Feedback CY2308 Document History Page Document Title: CY2308 3.3V Zero Delay Buffer Document Number: 38-07146 REV. ** *A *B *C *D *E ECN 110255 118722 121832 235854 310594 1344343 Orig. of Change SZV RGL RBI RGL RGL KVM/VED Submission Date 12/17/01 10/31/02 12/14/02 06/24/04 02/09/05 08/20/07 Added Note 1 in page 2. Power up requirements added to Operating Conditions Information Added Pb-Free Devices Removed obsolete parts in the ordering information table Specified typical value for cycle-to-cycle jitter Brought the Ordering Information Table up to date: removed three obsolete parts and added two parts Changed titles to tables that are specific to commercial and industrial temperature ranges Updated template. Added Note “Not recommended for new designs.” Changed IDD (PD mode) from 12.0 to 25.0 μA for Commercial and Industrial Temperature Devices Deleted Duty Cycle parameters for Fout < 50 MHz Removed CY2308SI-4, CY2308SI-4T and CY2308SC-5HT. Description of Change Changed from Specification number: 38-00528 to 38-07146 *F 2568575 AESA 09/19/08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07146 Rev. *F Revised September 19, 2008 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback