CY24115SXC-2

CY24115 MediaClock™ Mini Disc Clock Generator Features • • • • Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs 3.3V operation 8-pin SOIC package Benefits • High-performance PLL tailored for mini disc applications • Meets critical timing requirements in complex system designs • Enables application compatibility • Industry standard package saves on board space Part Number CY24115-1 CY24115-2 Outputs 1 1 Input Frequency Range 1 MHz–30 MHz 1 MHz–30 MHz Output Frequencies 45.1584 MHz/90.3168 MHz (selectable) 90.3168 MHz/180.6336 MHz (selectable) Logic Block Diagram XIN XOUT OSC Q Φ VCO P OUTPUT DIVIDERS CLKA PLL FS0 FS1 CLKSEL VSS FREQUENCY TABLE VDD Table 1. CLKSEL Function CY24115-1 CLKSEL CLKA 45.1584 Unit MHz PPM Error 0 0 Pin Configurations CY24115 8-pin SOIC XIN VDD CLKSEL VSS 1 2 3 4 8 7 6 5 XOUT FS1 FS0 CLKA 0 1 90.3168 MHz Table 2. CLKSEL Function, CY24115-2 CLKSEL 0 CLKA 90.3168 Unit MHz PPM Error 0 1 180.6336 MHz 0 Table 3. Input Frequency Function, CY24115-1 and CY24115-2 FS1 0 0 1 1 FS0 0 1 0 1 Xtal Input 2.8224 5.6448 11.2896 22.5792 Unit MHz MHz MHz MHz Cypress Semiconductor Corporation Document #: 38-07275 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 10, 2004 CY24115 Pin Summary Pin Name XIN VDD CLKSEL Pin Number 1 2 3 Pin Description Reference input (crystal or external input) 3.3V voltage supply CLKA Select Line For 24115-1, see Table 1 for output values For 24115-2, see Table 2 for output values Ground 24115-1: 45.1584 MHz/90.3168 MHz (frequency selectable). See Table 1. 24115-2: 90.3168 MHz/180.6336 MHz (frequency selectable). See Table 2. Input Frequency FS0. See Table 3. Input Frequency FS1. See Table 3. Reference Output VSS CLKA FS0 FS1 XOUT[1] Parameter VDD TS TJ 4 5 6 7 8 Absolute Maximum Conditions Description Supply Voltage Storage Temperature[2] Junction Temperature Digital Inputs Digital Outputs Referred to VDD Electrostatic Discharge VSS – 0.3 VSS – 0.3 2 Min. –0.5 –65 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 Unit V °C °C V V kV Recommended Operating Conditions Parameter VDD TA CLOAD fREF t1 DCIN CIN tPU Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Driven Reference Edge Rate Driven Reference Duty Cycle XIN, XOUT capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 2.8224 0.8 40 12 500 60 Min. 3.14 0 Typ. 3.3 Max. 3.47 70 15 22.5792 Unit V °C pF MHz V/ns % pF ms DC Electrical Characteristics Parameter IOH IOL CIN VIL VIH IIZ IDD Notes: Name Output High Current Output Low Current Input Capacitance Input Low Voltage Input High Voltage Input Leakage Current Supply Current Description VOH = VDD – 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) CLKSEL, FS0, FS1, excludes XIN, XOUT Min. 12 12 Typ. 24 24 Max. Unit mA mA 7 30 70 5 pF % of VDD % of VDD µA Sum of Core and Output Current 35 mA 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07275 Rev. *C Page 2 of 5 CY24115 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] DC t3 t4 t9 t10 Name Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20%–80% of VDD Output Clock Fall Time, 80%–20% of VDD Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 350 3 Max. 55 Unit % V/ns V/ns ps ms Notes: 3. Not 100% tested. Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD GND t1 t2 CLK 50% 50% CLK t3 80 20 t4 Figure 1. Duty Cycle Definition; DC = t2/t1 Figure 2. Rise and Fall Time Definitions Ordering Information Ordering Code CY24115SC-1 CY24115SC-1T CY24115SC-2 CY24115SC-2T Lead Free CY24115SXC-1 CY24115SXC-1T CY24115SXC-2 CY24115SXC-2T 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel Commercial Commercial Commercial Commercial 3.3V 3.3V 3.3V 3.3V Package Type 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel Operating Range Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V Document #: 38-07275 Rev. *C Page 3 of 5 CY24115 Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07275 Rev. *C Page 4 of 5 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24115 Document Title: CY24115 MediaClock™ Mini Disc Clock Generator Document Number: 38-07275 REV. ** *A ECN NO. 110767 113515 Issue Date 02/06/02 04/30/02 Orig. of Change CKN CKN Description of Change New Data Sheet Changed from Preliminary to Final P. 2 in Electrical Characteristics table added (source) to row 1 and (sink) to row 2 Power up requirements added to Operating Conditions Information Added Lead Devices *B *C 121884 252154 12/14/02 See ECN RBI RGL Document #: 38-07275 Rev. *C Page 5 of 5