CY24292
Four Outputs PCI-Express Clock Generator
Four Outputs PCI-Express Clock Generator
Features
Functional Description
■
25 MHz Crystal or Clock Input
CY24292 is a clock generator device intended for PCI-Express
applications. The device includes: four 100 MHz differential
clocks with HCSL Compatible outputs for PCI-Express, and one
single-ended 25 MHz output.
■
Four Differential 100 MHz PCI-Express Clocks
■
Supports HCSL Compatible Output Levels
■
One Single-ended 25 MHz Output
■
Spread Spectrum Capability on all 100 MHz PCI-Express Clock
Outputs
■
SMBus Interface with Read Back Capability
Using a serially programmable SMBus interface, the CY24292
incorporates spread spectrum modulation on all four 100 MHz
outputs. The device incorporates a Lexmark Spread Spectrum
profile for maximum electromagnetic interference (EMI)
reduction. The spread feature or individual outputs can also be
disabled using the SMBus interface.
■
32-pin QFN Package
For a complete list of related documentation, click here.
■
Operating Voltage 3.3 V
■
Commercial and Industrial Operating Temperature Range
Logic Block Diagram
VDD
PCIE0P
XIN/EXCLKIN
(25 MHz)
XOUT
PCIE0N
Clock Buffer/
Crystal
Oscillator
PCIE1P
PCIE1N
PLL Clock
(100 MHz)
(100 MHz)
Synthesizer,
PCIE2P
Dividers, Buffers
PCIE2N
(100 MHz)
and
SCLK
Configuration
SDATA
PCIE3P
PCIE3N
Logic
(100 MHz)
PD_RESET#
25M
(25 MHz)
I REF
R
GND
Cypress Semiconductor Corporation
Document Number: 001-46142 Rev. *G
•
198 Champion Court
REF
•
= 475 Ohms 1%
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2017
CY24292
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
SMBus Serial Data Interface ....................................... 4
Data Protocol ............................................................... 4
Control Registers ......................................................... 6
Application Information ................................................... 8
Crystal Recommendations .......................................... 8
Crystal Loading ........................................................... 8
Calculating Load Capacitors ....................................... 8
Current Source (Iref) Reference Resistor .................... 8
Output Termination ...................................................... 8
PCB Layout Recommendations .................................. 9
Decoupling Capacitors ................................................ 9
PCI-Express Layout Guidelines ...................................... 9
HCSL Compatible Layout Guidelines .......................... 9
Absolute Maximum Ratings .......................................... 10
Recommended Operation Conditions .......................... 10
DC Electrical Characteristics ........................................ 11
Document Number: 001-46142 Rev. *G
Thermal Resistance ........................................................ 11
AC Electrical Characteristics ........................................ 12
Test and Measurement Setup ........................................ 14
Single-ended Signals ................................................ 14
Differential Signals .................................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagram ............................................................ 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
CY24292
Pin Configuration
VDD
GND
VDD
GND
VDD
GND
25M
NC
Figure 1. 32-pin QFN Pinout CY24292
32
31
30
29
28
27
26
25
GND
3
22
XIN/EXCLKIN
IREF
4
CY24292
21
VDD
PCIE2N
5
32 Pin QFN
20
PD_RESET#
PCIE2P
6
19
GND
GND
7
18
VDD
VDD
8
17
GND
9
10
11
12
13
14
15
16
VDD
XOUT
SDATA
23
SCLK
2
PCIE0N
PCIE1N
PCIE0P
VDD
VDD
24
PCIE3P
1
PCIE3N
PCIE1P
Pin Definitions
Pin Number
1
Pin Name
PCIE1P
Pin Type
Description
Output
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
Output
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
2
PCIE1N
3
GND
Power
Ground
4
IREF
Output
Current set for all differential clock drivers. Connect 475 resistor to ground.
5
PCIE2N
Output
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
6
PCIE2P
Output
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
7
GND
Power
Ground
8
VDD
Power
3.3 V Power supply
9
PCIE3N
Output
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
10
PCIE3P
Output
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
11
VDD
Power
3.3 V Power supply
12
PCIE0P
Output
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
13
PCIE0N
Output
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
14
SCLK
Input
SMBus clock input
15
SDATA
Input
SMBus data input
16
VDD
Power
3.3 V Power supply
17
GND
Power
Ground
Document Number: 001-46142 Rev. *G
Page 3 of 20
CY24292
Pin Definitions (continued)
Pin Number
Pin Name
Pin Type
Description
18
VDD
Power
3.3 V Power supply
19
GND
Power
Ground
20
PD_RESET#
Input
Global reset pin. Powers down PLLs, disables outputs and sets the SMBus tables to their
default state when pulled low. Has internal weak pull up.
21
VDD
Power
3.3 V Power supply
22
XIN/EXCLKIN Input
Crystal or clock input. Connect to 25 MHz fundamental mode crystal or clock.
23
XOUT
Output
Crystal output. Connect to 25 MHz fundamental mode crystal. Float for clock input.
24
VDD
Power
3.3 V Power supply
25
NC
–
No connect. Pin has no internal connection.
26
25M
Output
25 MHz Single-ended LVCMOS output. Pull-down when disabled by PD_RESET#. Driven low when individually disabled (via SMBus byte 0, bit 0).
27
GND
Power
Ground
28
VDD
Power
3.3 V Power supply
29
GND
Power
Ground
30
VDD
Power
3.3 V Power supply
31
GND
Power
Ground
32
VDD
Power
3.3 V Power supply
Functional Overview
SMBus Serial Data Interface
A two-signal serial interface is provided to enhance the flexibility
and function of the clock synthesizer. Through the serial data
interface, various device functions such as clock output buffers
can be individually enabled or disabled. The registers associated
with the serial data interface initialize to their default setting upon
power up, and therefore this interface is optional. Clock device
register changes are normally made upon system initialization, if
required. This is a RAM-based technology which does not keep
its value when power is off or during a power transition.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write and read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte is transferred.
For byte write and byte read operations, the system controller
can access individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in Table 1.
The block write and block read protocol is outlined in Table 2 on
page 5, while Table 3 on page 5 outlines the corresponding byte
write and byte read protocol. The slave receiver address is
11010010 (D2h) for write and 11010011 (D3h) for read.
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = block read or block write operation, 1 = byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be '0000000'
Document Number: 001-46142 Rev. *G
Page 4 of 20
CY24292
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Description
Start
Block Read Protocol
Bit
1
Slave address – 7 bits
2:8
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
28
29:36
37
38:45
46
Command code – 8-bit ‘00000000’ stands for block
operation
Acknowledge from slave
Byte count – 8 bits
11:18
19
20
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
21:27
Data byte N/Slave acknowledge
Data byte N – 8 bits
Acknowledge from slave
Stop
Acknowledge from slave
Repeat start
Slave address – 7 bits
28
Read
29
Acknowledge from slave
30:37
Acknowledge from slave
Command code – 8-bit ‘00000000’ stands for block
operation
38
39:46
47
48:55
56
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/acknowledge
Data byte N from slave – 8 bits
Not acknowledge
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command code – 8 bits ‘1xxxxxxx’ stands for byte
operation, bits[6:0] of bits[6:0] the command code
represents the offset of the byte to be accessed
Byte Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
Command code – 8 bits ‘1xxxxxxx’ stands for byte
operation, of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
19
Acknowledge from slave
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
29
Stop
21:27
28
Read = 1
29
Acknowledge from slave
30:37
Document Number: 001-46142 Rev. *G
Slave address – 7 bits
Data byte from slave – 8 bits
38
Not acknowledge
39
Stop
Page 5 of 20
CY24292
Control Registers
Table 4. Byte 0: Spread Spectrum Control Register
Bit
Type
At Power up
7
R/W
1
6
R
Undefined
5
R/W
1
4
R
3
2
1
0
Outputs Affected
Description
All 100 MHz PCI-Express outputs Spread select for 100 MHz PCI-Express clocks
Not applicable
Not used
All outputs
Global OE bit. Enables or disables all outputs.
Undefined
Not applicable
Not used
R
Undefined
Not applicable
Not used
R
Undefined
Not applicable
Not used
R
Undefined
R/W
1
Not applicable
Not used
Single-ended 25 MHz output,
25M
OE for single-ended 25 MHz output, 25M.
Output driven low when disabled.
Notes
0 = spread off
1 = –0.5% down
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Table 5. Byte 1: Control Register
Bit
Type
At Power up
0 to 7
R
Undefined
Outputs Affected
Not applicable
Description
Notes
Description
Notes
Description
Notes
Not used
Table 6. Byte 2: Control Register
Bit
Type
At Power up
0 to 7
R
Undefined
Outputs Affected
Not applicable
Not used
Table 7. Byte 3: Control Register
Bit
Type
At Power up
Outputs Affected
6,7
R
0
Not applicable
Not used
OE for 100 MHz PCI-Express output PCIE3
0 = disabled
1 = enabled
0 = disabled
1 = enabled
5
R/W
1
100 MHz PCI-Express output
PCIE3
4
R/W
1
100 MHz PCI-Express output
PCIE2
OE for 100 MHz PCI-Express output PCIE2
3
R
0
Not applicable
Not used
2
R/W
1
100 MHz PCI-Express output
PCIE1
OE for 100 MHz PCI-Express output PCIE1
0 = disabled
1 = enabled
1
R/W
1
100 MHz PCI-Express output
PCIE0
OE for 100 MHz PCI-Express output PCIE0
0 = disabled
1 = enabled
0
R
Undefined
Not applicable
Not used
Table 8. Byte 4: Control Register
Bit
Type
At Power up
0 to 7
R
Undefined
Outputs Affected
Not applicable
Document Number: 001-46142 Rev. *G
Description
Notes
Not used
Page 6 of 20
CY24292
Table 9. Byte 5: Control Register
Bit
Type
At Power up
Outputs Affected
7
R
0
Not applicable
Revision ID bit 3
6
R
0
Not applicable
Revision ID bit 2
5
R
0
Not applicable
Revision ID bit 1
4
R
1
Not applicable
Revision ID bit 0
3
R
1
Not applicable
Vendor ID bit 3
2
R
0
Not applicable
Vendor ID bit 2
1
R
0
Not applicable
Vendor ID bit 1
0
R
0
Not applicable
Vendor ID bit 0
Description
Notes
Description
Notes
Table 10. Byte 6: Control Register
Bit
Type
At Power up
0 to 7
R
Undefined
Outputs Affected
Not applicable
Not used
The state of the clock outputs upon assertion of the PD_RESET# signal from input pin or Global OE control bit from byte 0, bit 5 of
the SMBus is shown in the following table.
Table 11. Power Down Reset Table
H/W PD_RESET# (pin 24)
S/W PD_RESET# (Byte 0 bit 5)
All Clock Outputs
0
0
Disabled, Hi-Z. 25M has weak pull-down.
0
1
Disabled, Hi-Z. 25M has weak pull-down.
1
0
Disabled, Hi-Z. 25M has weak pull-down.
1
1
Enabled
Document Number: 001-46142 Rev. *G
Page 7 of 20
CY24292
Application Information
Crystal Recommendations
The CY24292 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24292 to operate at the
wrong frequency and violate the ppm specification. For most applications there is a 300 ppm frequency shift between the series and
parallel crystals due to incorrect loading.
Table 12. Crystal Recommendations
Frequency
Cut
Load Cap (max) Eff Series Rest (max)
25.00 MHz Parallel
30
16 pF
Crystal Loading
Crystal loading plays a critical role in achieving low ppm
performance. To realize low ppm performance, consider the total
capacitance the crystal sees to calculate the appropriate
capacitive loading (CL).
Figure 2 shows a typical crystal configuration using two trim
capacitors. It is important to note that the trim capacitors in series
with the crystal are not parallel. It is a common misconception
that load capacitors are in parallel with the crystal and are
approximately equal to the load capacitance of the crystal. This
is not true.
Drive (max) Tolerance (max) Stability (max) Aging (max)
1.0 mW
30 ppm
10 ppm
5 ppm/yr
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2.
Load capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
Calculating Load Capacitors
CL .................................................. Crystal load capacitance
In addition to the standard external trim capacitors, the trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading.
CLe ........................................ Actual loading seen by crystal
using standard value trim capacitors
As mentioned in the previous section, the capacitance on each
side of the crystal is in series with the crystal. This means the
total capacitance on each side of the crystal must be twice the
specified crystal load capacitance (CL). While the capacitance
on each side of the crystal is in series with the crystal, the trim
capacitors (Ce1, Ce2) must be calculated to provide equal
capacitive loading on both sides.
Figure 2. Crystal Loading Example
Ci2
Pin
3 to 6 pF
X2
X1
Cs1
Current Source (Iref) Reference Resistor
If the board target trace impedance (Z) is 50 , then for
RREF = 475 (1%) provides IREF of 2.32 mA. The output
current (IOH) is equal to 6 × IREF.
The PCI-Express differential clock outputs of CY24292 are open
source drivers and require an external series resistor and a
resistor to ground. These resistor values and their allowable
locations are explained in detail in the section PCI-Express
Layout Guidelines on page 9.
Cs2
Trace
2.8 pF
XTAL
Ce1
Cs .............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
Output Termination
Clock
Chip
Ci
1
Ce .................................................... External trim capacitors
Ce2
Document Number: 001-46142 Rev. *G
Trim
26 pF
Page 8 of 20
CY24292
4. An optimum layout is one with all components on the same
side of the board, minimizing vias through other signal layers
(any ferrite beads and bulk decoupling capacitors can be
mounted on the back). Other signal traces must be routed
away from the CY24292. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
PCB Layout Recommendations
For optimum device performance and lowest phase noise, the
following guidelines must be observed.
1. Each 0.01 µF decoupling capacitor must be mounted on the
component side of the board as close to the VDD pin as
possible.
2. No vias must be used between the decoupling capacitor and
the VDD pin.
3. The PCB trace to the VDD pin and the ground via must be
kept as short as possible. The distance of the ferrite bead and
bulk decoupling from the device is less critical.
Decoupling Capacitors
Decoupling capacitors of 0.01 µF must be connected between
VDD and GND as close to the device as possible. Do not share
ground vias between components. Route power from power
source through the capacitor pad, and then into the CY24292
pin.
PCI-Express Layout Guidelines
HCSL Compatible Layout Guidelines
Table 13. Common Recommendations for Differential Routing
Differential Routing[1]
Dimension or Value
Unit
L1 length, route as non-coupled 50 trace
0.5 max
inch
L2 length, route as non-coupled 50 trace
0.2 max
inch
L3 length, route as non-coupled 50 trace
0.2 max
inch
RS
33
RT
49.9
Differential Routing [1]
Dimension or Value
Unit
L4 length, route as coupled microstrip 100 differential trace
2 to 32
inch
1.8 to 30
inch
Table 14. Differential Routing for PCI-Express Load or Connector
L4 length, route as coupled stripline 100 differential trace
Figure 3. PCI-Express Device Routing
Rs
L1
L2
L4
L2
L4
RS
L1
RT
Output Buffer
L3
RT
L3
PCI Express Load or
Connector
Note
1. Refer to Figure 3.
Document Number: 001-46142 Rev. *G
Page 9 of 20
CY24292
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage
–0.5
4.6
V
VIN
Input voltage
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, Storage
Non Operating
–65
150
°C
TJ
Temperature, Junction
–
125
°C
ESDHBM
ESD Protection (Human Body
Model)
2000
–
V
UL-94
Flammability rating
MSL
Moisture sensitivity level
JEDEC EIA/JESD22-A114-E
V-0 at 1/8 in.
3
Recommended Operation Conditions
Parameter
Description
Min
Typ
Max
Unit
3.0
–
3.6
V
0
–
70
°C
VDD
Supply voltage
TAC
Commercial ambient temperature
TAI
Industrial ambient temperature
–40
–
85
°C
tPU
Power up time for all VDD to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
tPD
Minimum pulse width of PD_RESET# input
100
–
–
ns
VSMB
SMBus Voltage
3.0
–
3.6
V
RREFTOL
Tolerance on the 475RREF resistor that sets output currents on
100MHz ports
–
–
1
%
Document Number: 001-46142 Rev. *G
Page 10 of 20
CY24292
DC Electrical Characteristics
Unless otherwise stated, VDD = 3.3 V ± 0.3 V, ambient temperature = –40 °C to 85 °C Industrial, 0 °C to 70 °C Commercial, RREF = 475
Parameter[2]
Description
Condition
Min
Typ
Max
Unit
–
–
0.4
V
VDD – 0.4
–
–
V
VOL1
Low level output voltage of 25M
IOL = 8 mA
clock
VOH1
High level output voltage of 25M
IOH = –8 mA
clock
VOL2
Low level output voltage of 100M HCSL termination
clocks
(RS = 33 , RT = 49.9 )
–0.2
0
0.05
V
VOH2
High level output voltage of 100M HCSL termination
clocks
(RS = 33 RT49.9
0.65
0.71
0.95
V
VOL3
Low level output voltage SDATA IOL = 4 mA
–
–
0.4
V
IOH
Output high current for differential
IOH = 6 × IREF
clocks
–13
–15.2
–17
mA
VIL1
Low level input voltage of SCLK,
SDATA
–0.3
–
0.8
V
VIH1
High level input voltage of SCLK,
SDATA
2.1
–
VDD + 0.3
V
VIL2
Low level input voltage of
XIN/EXCLKIN, PD_RESET# pins
–0.3
–
0.8
V
VIH2
High level input voltage of
XIN/EXCLKIN, PD_RESET# pins
2.0
–
VDD + 0.3
V
IDD
Operating supply current
IDDPD
No load, PD_RESET# pin = 1
–
50
70
mA
Full load, PD_RESET# pin = 1
–
135
170
mA
Power down current
PD_RESET# pin = 0
–
250
350
A
CIN
Input capacitance
All input pins
–
5
–
pF
RPU
Pull up resistor, PD_RESET#
–
90
–
k
RPD
Pull down resistor, 25M output
PD_RESET# = 0
50
–
150
k
Thermal Resistance
Parameter[3]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
32-pin QFN
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
22
°C/W
19.5
°C/W
Notes
2. Parameters are guaranteed by design and characterization. Not 100% tested in production.
3. These parameters are guaranteed by design and are not tested.
Document Number: 001-46142 Rev. *G
Page 11 of 20
CY24292
AC Electrical Characteristics
Unless otherwise stated, VDD = 3.3 V ± 0.3 V, ambient temperature = –40 °C to 85 °C Industrial, 0°C to 70°C Commercial, RREF = 475
Table 15. Single-Ended 25 MHz Output
Parameter[4]
Description
Condition
Min
Typ
Max
Unit
FIN
Input clock frequency (crystal or
external clock)
–
–
25
–
MHz
TINDC
Input clock duty cycle
–
40
–
60
%
FOUT
Output clock frequency, 25M
–
–
25
–
MHz
20% to 80% of VDD
–
0.5
1
ns
80% to 20% of VDD
–
0.5
1
ns
Measured at VDD/2
45
50
55
%
–
–
200
ps
TR
TF
TDC
[5]
Output rise time
Output fall time
[5]
Output clock duty
cycle[5]
TCCJ
Cycle-to-cycle
TOEPD
Output enable from power down
reset
PD_RESET# going high to 99% of final
frequency
–
–
2
ms
TLOCK
Clock stabilization from power up
Measured from 90% of the applied power
supply level
–
1
2
ms
jitter[5]
–
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production.
5. Measured with Cload = 15 pF lumped load.
Document Number: 001-46142 Rev. *G
Page 12 of 20
CY24292
Table 16. Differential 100 MHz, HCSL Terminated Outputs
Parameter [6]
Description
Test Condition
FOUT
Output frequency
SPPROFILE
Spread modulation profile
SPMOD
Spread modulation frequency
TCCJ
TPHJ
TDC
ERR
Cycle-to-cycle jitter
[7]
Peak-to-peak phase jitter
[7, 8]
[7]
Output clock duty cycle
Rising edge rate
Min
Typ
Max
Unit
–
–
100
MHz
–
–
Lexmark
type
30
32
33
kHz
–
–
90
ps
–
–
86
ps
45
50
55
%
[7, 9]
See notes 7 and 9
0.6
–
4.0
V/ns
[7, 9]
See notes 7 and 9
0.6
–
4.0
V/ns
See notes 10, 11, and 12
0.25
0.35
0.55
V
–
–
140
mV
ERF
Falling edge rate
VCROSS
Absolute crossing point
voltage [10, 11, 12]
VXdelta
Variation of VCROSS over all rising
See notes 10, 11, and 13
clock edges[10, 11, 13]
TPERIOD AVG
Average clock period
accuracy[7, 14]
See notes 7 and 14
–300
–
2800
ppm
TPERIOD ABS
Absolute clock period[7, 15]
See notes 7 and 15
pairs[16]
9.847
–
10.203
ns
Measured at VCROSS point
See note 16
–
–
100
ps
Measured at VCROSS point
See note 16
–
–
50
ps
TOSKEW ALL
Output skew, all
TOSKEW P-P
PCIE0P/N to PCIE3P/N skew
and PCIE1P/N to PCIE2P/N
skew[16]
TOEPD
Output enable from power down PD_RESET# going high to 99% of
reset
final frequency
–
–
2
ms
TLOCK
Clock stabilization from power up
Measured from 90% of the applied
power supply level
–
1
2
ms
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production.
7. Measurement taken from differential waveform (PCIEP minus PCIEN). Either single ended probes with math or a differential probe can be used.
8. Phase jitter is determined using data captured on an oscilloscope at a sample rate of 20 GS/sec, for a minimum 100,000 continuous clock periods. This data is then
processed using the ClockJitter 1.3.0 software from PCISIG, using the PCI_E_1_1 template.
9. Measured from -150 mV to +150 mV on the differential waveform (derived from PCIEP minus PCIEN). The signal must be monotonic through the measurement region
for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
10. Measurement taken from a single-ended waveform.
11. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN.
12. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
13. Defined as the total variation of all crossing voltages of Rising PCIEP and Falling PCIEN. This is the maximum allowed variance in VCROSS for any particular system.
14. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly, or 100 Hz. For 300 PPM then
we have an error budget of 30 kHz. The period is to be measured with a frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies
to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum, there is an additional 2500 PPM nominal
shift in maximum period resulting from the 0.5% down spread, resulting in a maximum average period specification of +2800 PPM.
15. Defined as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation.
16. Measured at the rising 0 V point of the differential signal. Skew is the time difference of the rising 0 V point between any two differential signal pairs. The measurement
is taken over 1000 samples, and the average value is used.
Document Number: 001-46142 Rev. *G
Page 13 of 20
CY24292
Test and Measurement Setup
Single-ended Signals
Figure 4. Test Load Configuration for Single-ended Output Signal
453 Ohm
50 Ohm
CLoad
Differential Signals
Figure 5. Test Load Configuration for Differential Output Signal
33 Ohm
PCIEP
CLoad
50 Ohm
CLoad
50 Ohm
33 Ohm
PCIEN
475
Ohm
Document Number: 001-46142 Rev. *G
Page 14 of 20
CY24292
Ordering Information
Ordering Code
Package Type
Production Flow
Pb-free
CY24292LFXC
32-pin QFN
Commercial, 0 °C to 70 °C
CY24292LFXCT
32-pin QFN – Tape and Reel
Commercial, 0 °C to 70 °C
CY24292LFXI
32-pin QFN
Industrial, –40 °C to 85 °C
CY24292LFXIT
32-pin QFN – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 24292
L
X
X
X -xxx T
T = Tape and Reel, blank = tube
Configuration specific identifier (Factory Programmed)
Temperature Range: X = C or I
C = Commercial = 0 °C to 70 °C; I = Industrial = –40 °C to 85 °C
Pb-free
X = F or blank
F = Field Programmable; blank = Factory Programmed
Package:
L = 32-pin QFN
Part Identifier
Company ID: CY = Cypress
Document Number: 001-46142 Rev. *G
Page 15 of 20
CY24292
Package Diagram
Figure 6. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
DIMENSIONS
NOTES:
1.
SYMBOL
HATCH AREA IS SOLDERABLE EXPOSED PAD
MIN.
NOM.
MAX.
2. BASED ON REF JEDEC # MO-248
A
0.50
0.55
0.60
3. PACKAGE WEIGHT: 0.0388g
A1
-
0.020
0.045
4. DIMENSIONS ARE IN MILLIMETERS
A2
0.15 BSC
001-42168 *F
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
L
0.30
0.40
0.50
b
0.18
0.25
0.30
e
Document Number: 001-46142 Rev. *G
0.50 TYP
Page 16 of 20
CY24292
Acronyms
Document Conventions
Table 17. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 18. Units of Measure
EIA
electronic industries alliance
EMI
electromagnetic interference
°C
degree Celsius
ESD
electrostatic discharge
kHz
kilohertz
HCSL
host clock signal level
k
kilohm
JEDEC
joint electron devices engineering council
MHz
megahertz
F
microfarad
Symbol
Unit of Measure
LVCMOS
low voltage complementary metal oxide
semiconductor
mA
milliampere
OE
output enable
ms
millisecond
PCI
peripheral component interconnect
mV
millivolt
PLL
phase-locked loop
ns
nanosecond
QFN
quad-flat no-leads
ohm
RAM
random access memory
%
percent
pF
picofarad
ppm
parts per million
ps
picosecond
V
volt
Document Number: 001-46142 Rev. *G
Page 17 of 20
CY24292
Document History Page
Document Title: CY24292, Four Outputs PCI-Express Clock Generator
Document Number: 001-46142
Rev.
ECN
Orig. of
Change
Submission
Date
**
2490167
PYG / DPF
/ AESA
See ECN
*A
2507681
DPF /
AESA
New data sheet.
05/23/2008
Updated Pin Configuration (Changed pinout based on PCIE_Bonding_Rev G).
Updated DC Electrical Characteristics (Added Note 2 and referred the same
note in parameter column, added HCSL termination in Condition column for
VOL2, VOH2).
Updated AC Electrical Characteristics (updated Note 5, added Note 11 and
referred the same note in TDC parameter in Table 16, changed Cload from 2
pF to 4 pF in a Note below, added maximum value of VXdelta (140 mV) in the
Table 16).
Updated to new template.
Changed status from Preliminary to Final.
Updated Pin Definitions (Added explanation of 25M output disable feature).
Updated Control Registers (Changed default setting (At Power up column) for
bit 7 in Table 4 to ‘1’, changed description of bit 5 in Table 4 to ‘Global OE bit’,
added explanation of 25M output disable feature in Table 4, changed unused
bits (Type Column) from R/W to R in Table 7, changed default setting (At Power
up column) for bit 4 in Table 9 to ‘1’, added explanation of 25M output disable
feature in Table 11).
Updated the sub-section Crystal Recommendations under the main section
Application Information (Added “max” to Load Cap and Eff Series Rest columns
in Table 12).
Updated sub-section “LVDS Compatible Layout Guidelines” under the main
section PCI-Express Layout Guidelines (changed “LVDS Down Device” to
“LVDS Device” in all instances).
Updated Absolute Maximum Ratings (Changed maximum value of TJ
parameter to 125 °C).
Updated Recommended Operation Conditions (Added VSMB and RREFTOL
parameters and its details).
Updated DC Electrical Characteristics (added RREF value to conditions at top,
removed VOHSD and VOLSD parameters and their details, changed maximum
value of VOH2 parameter from 0.85 V to 0.95 V, added VOL3 parameter and its
details, changed typical value of IOH parameter from –14.2 mA to –15.2 mA,
added minimum value of VIL1 parameter, changed maximum value of VIL1
parameter from 1 V to 0.8 V, changed minimum value of VIH1 parameter from
2.2 V to 2.1 V, added typical and maximum values for IDD no load and full load
parameters, changed typical value of IDDPD parameter from TBD to 250 µA,
changed maximum value of IDDPD parameter from TBD to 350 µA, added RPU
parameter and its details, changed RPD parameter to apply to 25M output only).
Updated AC Electrical Characteristics (added RREF value to conditions at top,
removed FERR parameter and its details in Table 15, added SPPROFILE
parameter and its details in Table 16, added minimum and maximum values for
SPMOD parameter, changed maximum value of TCCJ parameter from 100 ps to
90 ps in Table 16, added TPHJ parameter and its details in Table 16, changed
TR and TF parameters and its details into ERR and ERF parameters in Table 16,
removed TRFMATCH parameter and its details in Table 16, splitted TOSKEW
parameter into two parameters namely TOSKEW ALL and TOSKEW P-P parameter
and also changed their details in Table 16, added minimum value of VCROSS
parameter and also changed the description of the same parameter in Table 16,
changed description of VXdelta parameter in Table 16).
Updated Package Diagram (to spec 001-42168 Rev *C).
Fixed various typos.
*B
2811340
CXQ
12/03/2009
*C
2901711
KVM
05/14/10
Document Number: 001-46142 Rev. *G
Description of Change
Updated Package Diagram.
Page 18 of 20
CY24292
Document History Page (continued)
Document Title: CY24292, Four Outputs PCI-Express Clock Generator
Document Number: 001-46142
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
*D
3448896
PURU
11/28/2011
Updated Features (Removed LVDS related information).
Updated Functional Description (Removed LVDS related information).
Updated Output Termination under Application Information (Removed LVDS
related information).
Removed the sub-section “LVDS Compatible Layout Guidelines” under the
main section PCI-Express Layout Guidelines.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
*E
4580588
TAVA
12/05/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram.
*F
5281281
PSR
04/26/2017
Added Thermal Resistance.
Updated to new template.
*G
5784045
PSR
06/27/2017
Updated AC Electrical Characteristics: Added FIN and TINDC parameters.
Updated Figure 6 in Package Diagram (spec 001-42168 *E to *F).
Document Number: 001-46142 Rev. *G
Page 19 of 20
CY24292
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-46142 Rev. *G
Revised June 27, 2017
Page 20 of 20