CY25404ZXI-XXX

CY25404 Quad PLL Programmable Clock Generator with Spread Spectrum Features ■ ■ Four fully integrated phase-locked loops (PLLs) Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock Wide operating output frequency range ❐ 3 to 166 MHz Programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles Selectable VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V Selectable output clock voltages, independent of VDD supply: ❐ 2.5 V, 3.0 V, and 3.3 V Frequency select feature with option to select eight different frequencies over nine clock outputs Output enable, and SS ON/OFF controls Low jitter, high accuracy outputs Ability to synthesize nonstandard frequencies with Fractional-N capability Up to nine clock outputs with programmable drive strength Glitch-free outputs while frequency switching 20-pin TSSOP package ■ Commercial and Industrial temperature ranges Benefits ■ ■ ■ Multiple high performance PLLs allow synthesis of unrelated frequencies Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies Application specific programmable electromagnetic interference (EMI) reduction using spread spectrum for clocks Programmable PLLs for system frequency margin tests Meets critical timing requirements in complex system designs Suitability for PC, consumer, portable, and networking applications Capable of zero parts per million (PPM) frequency synthesis error Uninterrupted system operation during clock frequency switch Application compatibility in standard and low power systems ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Block Diagram XIN/ EXCLKIN XOUT OSC PLL1 Crossbar Switch Output Dividers and Bank 2 Bank 1 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 Control Bank 3 FS 0 FS 1 FS 2 MUX and Control Logic PLL2 Drive Strength CLK8 CLK9 PLL3 (SS) PLL4 (SS) SSON OE Cypress Semiconductor Corporation Document #: 001-43258 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 11, 2011 CY25404 Contents General Description ......................................................... 4 Four Configurable PLLs .............................................. 4 Input Reference Clocks ............................................... 4 VDD Power Supply Options ......................................... 4 Output Bank Settings .................................................. 4 Output Source Selection ............................................. 4 Spread Spectrum Control ............................................ 4 Frequency Select ........................................................ 4 Glitch-Free Frequency Switch ..................................... 4 Output Enable Mode ................................................... 4 Output Drive Strength .................................................. 4 Generic Configuration and Custom Frequency ........... 4 Absolute Maximum Conditions....................................... 5 Recommended Operating Conditions ............................ 5 DC Electrical Specifications ............................................ 6 Recommended Crystal Specification for SMD Package .............................................................. 7 Recommended Crystal Specification for Thru-Hole Package ..................................................... 7 AC Electrical Specifications ............................................ 7 Test and Measurement Setup .......................................... 8 Voltage and Timing Definitions ....................................... 8 Ordering Information ........................................................ 9 Possible Configurations ............................................... 9 Ordering Code Definitions ........................................... 9 Package Drawing and Dimensions ............................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document #: 001-43258 Rev. *C Page 2 of 13 CY25404 Figure 1. Pin Diagram - CY25404 20 LD TSSOP VDD XOUT XIN/EXCLKIN VSS 1 2 3 4 CY25404 20 CLK9 19 VSS 18 CLK8 17 VDD_CLK_B3 16 CLK7/SSON 15 VDD_CLK_B2 14 CLK6 13 VSS 12 CLK5 11 CLK4/FS2 CLK1 5 VDD_CLK_B1 6 CLK2 VSS CLK3/FS0 7 8 9 OE/FS1 10 Table 1. Pin Definition - CY25404 (VDD = 2.5 V, 3.0 V or 3.3 V Supply) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD XOUT XIN/EXCLKIN VSS CLK1 VDD_CLK_B1 CLK2 VSS CLK3/FS0 OE/FS1 CLK4/FS2 CLK5 VSS CLK6 VDD_CLK_B2 CLK7/SSON Name Power Output Input Power Output Power Output Power Output/Input Input Output/Input Output Power Output Power Output/Input IO Power supply: 2.5 V/3.0 V/3.3 V Crystal output Crystal Input or 1.8 V external clock input Power supply ground Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage Power supply for Bank1, (CLK1, CLK2, CLK3) outputs: 2.5 V/3.0 V/3.3 V Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage Power supply ground Multifunction programmable pin: Programmable clock output or frequency select input pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage Multifunction programmable pin: High-true output enable or frequency select pin Multifunction programmable pin: Programmable clock output or frequency select input pin. Output voltage of CLK4 depends on VDD_CLK_B2 Voltage Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage Power supply ground Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage Power supply for Bank2, (CLK4, CLK5, CLK6) outputs: 2.5 V/3.0 V/3.3 V Multifunction programmable pin. Programmable clock output or spread spectrum On/OFF control input pin. Output voltage of CLK7 depends on VDD_CLK_B3 voltage Power supply for Bank3, (CLK7, CLK8, CLK9) outputs: 2.5 V/3.0 V/3.3 V Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage Power supply ground Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage Description 17 18 19 20 VDD_CLK_B3 CLK8 VSS CLK9 Power Output Power Output Document #: 001-43258 Rev. *C Page 3 of 13 CY25404 General Description Four Configurable PLLs The CY25404 has four programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having four PLLs is that a single device generates up to four independent frequencies from a single crystal. Frequency Select There are three multifunction frequency select pins (FS0, FS1 and FS2) that provide an option to select eight different sets of frequencies among each of the four PLLs. Each output has programmable output divider options. Input Reference Clocks The input to the CY25404 can be either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz, while that for clock signals is 8 MHz to 166 MHz. The required voltage level for the input reference clock (EXCLKIN) is shown in the DC and AC Electrical Specification tables. Glitch-Free Frequency Switch When the frequency select pin (FS) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. Output Enable Mode There is a multifunction programmable pin 10, OE/FS1 that can be programmed to operate as output enable (OE) mode. OE is a high-true input and individual clock outputs can be programmed to be sensitive to this OE pin. If activated it shuts off the output drivers, resulting in minimum power consumption for the device. VDD Power Supply Options This device has programmable power supply option and it can be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V. Output Bank Settings There are nine clock outputs grouped in three output driver banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9) respectively. Separate power supplies are used for each of these banks and they can be any of 2.5 V, 3.0 V, or 3.3 V. These voltages are independent of VDD power supply used, giving user multiple choice of output clock voltage levels. Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Table 2 shows the typical rise and fall times for different drive strength settings. Table 2. Output Drive Strength Output Drive Strength Low Mid Low Mid High High Rise/Fall Time (ns) (Typical Value) 6.8 3.4 2.0 1.0 Output Source Selection These devices have programmable input sources for each of its nine clock outputs (CLK1–9). There are five available clock sources for these outputs. These clock sources are: XIN/EXCLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source selection is done using four out of five crossbar switch. Thus, any one of these five available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to four independent clock outputs. Spread Spectrum Control Two of the four PLLs (PLL3 and PLL4) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK7/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. Generic Configuration and Custom Frequency There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The device, CY25404 can be custom programmed to any desired frequencies and listed features. For customer specific programming, please contact local cypress field application engineer (FAE) or sales representative. Document #: 001-43258 Rev. *C Page 4 of 13 CY25404 Absolute Maximum Conditions Parameter VDD VDD_CLK_BX VIN TS ESDHBM UL-94 MSL Supply voltage Output bank supply voltage Input voltage Temperature, storage ESD protection (human body model) Flammability rating Moisture sensitivity level Relative to VSS Non functional JEDEC EIA/JESD22-A114-E V-0 at 1/8 in. – Description Condition – – Min –0.5 –0.5 –0.5 –65 2000 – 3 10 Max 4.5 4.5 VDD+0.5 +150 Unit V V V °C volts ppm Recommended Operating Conditions Parameter VDD VDD_CLK_BX TAC TAI CLOAD tPU VDD operating voltage Output driver voltage for Bank 1, 2 and 3 Commercial ambient temperature Industrial ambient temperature Maximum load capacitance Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Description Min 2.25 2.25 0 –40 – 0.05 Typ – – – -– – Max 3.60 3.60 +70 +85 15 500 Unit V V °C °C pF ms Notes 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. Document #: 001-43258 Rev. *C Page 5 of 13 CY25404 DC Electrical Specifications Parameter VOL Description Output low voltage Conditions IOL = 2 mA, drive strength = [00] IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output high voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VIL1 VIL2 VIH1 VIH2 IIL1 IIH1 IIL2 IIH2 RDN IDD[1,2] CIN [1] Min – Typ – Max 0.4 Unit V VDD_CLK_BX – 0.4 – – V Input low voltage of FS0, OE/FS1, FS2, and SSON Input low voltage of EXCLKIN Input high voltage of FS0, OE/FS1, FS2, and SSON Input high voltage of EXCLKIN Input low current of OE/FS1 pin Input high current of OE/FS1 pin Input low current of SSON, FS0 and FS2 pins VIL = 0V VIH = VDD – – – – – – 0.8*VDD 1.62 – – – 14 100 – – – – – – – – – – 160 22 0.2*VDD 0.18 – 2.2 10 10 10 36 250 – 7 V V V V µA µA µA µA k mA pF VIL = 0V (Internal pull dn = 160k typ) Input high current of SSON, FS0, and VIH = VDD (Internal pull dn = 160k typ) FS2 pins Pull down resistor of SSON, FS0, and Clock outputs in off-state by setting OE FS2 and off state (CLK1-CLK9) pins = Low Supply current for CY25404 Input capacitance OE = High, No load SSON, CLKIN, FS0, OE/FS1, and FS2 pins Document #: 001-43258 Rev. *C Page 6 of 13 CY25404 AC Electrical Specifications Parameter FIN (crystal) FIN (clock) FCLK DC1 DC2 TRF1 [1] Description Crystal frequency, XIN Input clock frequency, EXCLKIN Output clock frequency Output duty cycle, All clocks except Ref Out Ref out duty cycle Output rise/fall time Conditions – – Min 8 8 3 45 40 – Typ – – – 50 – 6.8 Max 48 166 166 55 60 – Unit MHz MHz MHz % % ns – Duty cycle is defined in Figure 3 on page 8; t1/t2, measured at 50% of VDD_CLK_BX Ref In Min 45%, Max 55% Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 4 on page 8, CLOAD = 15 pF, Drive strength [00] Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 4 on page 8, CLOAD = 15 pF, Drive strength [01] Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 4 on page 8, CLOAD = 15 pF, Drive strength [10] Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 4 on page 8, CLOAD = 15 pF, Drive strength [11] Configuration dependent. See Table 3 Measured from 90% of the applied power supply level TRF2[1] TRF3[1] TRF4[1] TCCJ[1,2] TLOCK[1] Output rise/fall time – 3.4 – ns Output rise/fall time – 2.0 – ns Output rise/fall time – 1.0 – ns Cycle-to-cycle jitter (peak) PLL lock time – – 100 1 – 3 ps ms Table 3. Configuration Example for C-C Jitter Ref. Freq. (MHz) 14.3181 19.2 27 48 CLK1 Output Freq. (MHz) 8.0 74.25 48 48 C-C Jitter Typ (ps) 134 99 67 93 CLK2 Output Freq. (MHz) 166 166 27 27 C-C Jitter Typ (ps) 103 94 109 123 CLK3 Output Freq. (MHz) 48 8 166 166 C-C Jitter Typ (ps) 92 91 103 137 CLK4 Output Freq. (MHz) 74.25 27 74.25 166 C-C Jitter Typ (ps) 81 110 97 138 8 48 CLK5 Output Freq. (MHz) C-C Jitter Typ (ps) 75 103 Not Used Not Used Recommended Crystal Specification for SMD Package Parameter FIN R1 CL DL(max) Crystal frequency Maximum motional resistance (ESR) Parallel load capacitance (device has internal load capacitance adjustment feature) Maximum crystal drive level Description Range 1 8 – 14 135 8 – 18 300 Range 2 Range 3 14 – 28 50 8 – 14 300 28 – 48 30 8 – 12 300 Unit MHz  pF µW Recommended Crystal Specification for Thru-Hole Package Parameter FIN R1 CL DL(max) Crystal frequency Maximum motional resistance (ESR) Parallel load capacitance (device has internal load capacitance adjustment feature) Maximum crystal drive level Description Range 1 8 – 14 90 8 – 18 1000 Range 2 Range 3 14 – 24 50 8 – 12 1000 24 – 32 30 8 – 12 1000 Unit MHz  pF µW Page 7 of 13 Document #: 001-43258 Rev. *C CY25404 Test and Measurement Setup Figure 2. Test and Measurement Setup V DD 0.1  F DUT Outputs C LOAD GND Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 VDD_CLK_BX 50% of V Clock Output 0V DD_CLK_BX Figure 4. Rise Time = TRF, Fall Time = TRF TRF TRF V DD_CLK_BX 80% of V 20% of V 0V D D_CLK_BX Clock Output D D_CLK_BX Document #: 001-43258 Rev. *C Page 8 of 13 CY25404 Ordering Information Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales representative for more information. Possible Configurations Part Number[3] Pb-free CY25404ZXC-xxx CY25404ZXC-xxxT CY25404ZXI-xxx CY25404ZXI-xxxT 20-pin TSSOP 20-pin TSSOP -Tape and Reel 20-pin TSSOP 20-pin TSSOP -Tape and Reel Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to +85 °C Industrial, –40 °C to +85 °C Type Production Flow Ordering Code Definitions CY25404 ZX C/I - xxx T Package Type: (T = Tape and Reel) Customer specific identification code Temperature code (C= Commercial or I= Industrial) 20-Pin TSSOP package Marketing Code: CY25404 = Device Number Note 3. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document #: 001-43258 Rev. *C Page 9 of 13 CY25404 Package Drawing and Dimensions Figure 5. 20-LD TSSOP, Thin Shrunk Small Outline Package (4.40 mm Body) ZZ2 51-85118 *C Document #: 001-43258 Rev. *C Page 10 of 13 CY25404 Acronyms Acronym DL EMI ESD FAE FS JEDEC EIA Description drive level electromagnetic interference electrostatic discharge field application engineer frequency select joint electron devices engineering council electronic industries alliance output enable oscillator power-down phase-locked loop parts per million spread spectrum spread spectrum clock spread spectrum on thin shrunk small outline package OE OSC PD PLL PPM SS SSC SSON TSSOP Document Conventions Units of Measure Symbol °C fF mA MHz s ms W ns pF ppm ps V  W Unit of Measure degrees Celsius femtofarads milliampere megahertz microseconds millisecond microwatts nanoseconds picofarads parts per million picoseconds volts ohms watts Document #: 001-43258 Rev. *C Page 11 of 13 CY25404 Document History Page Document Title: CY25404 Quad PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-43258 REV. ** *A *B ECN NO. 1793805 2748211 2899300 Issue Date See ECN 08/10/09 03/26/2010 Orig. of Change DPF/AESA New data sheet TSAI CXQ Posting to external web. Description of Change Updated Ordering Information. Added note regarding Possible Configurations in Ordering Information section. Added Possible Configurations table for “xxx’ parts. Updated Package Drawing and Dimensions Added Ordering Code Definitions Updated Package Drawing and Dimensions Added Acronyms Added Units of Measure Added Contents *C 3308261 07/11/2011 BASH Document #: 001-43258 Rev. *C Page 12 of 13 CY25404 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-43258 Rev. *C Revised July 11, 2011 Page 13 of 13