CY2DL818ZI

CY2DL818 1:8 Clock Fanout Buffer Features • • • • • • • • • • • • • Low voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVDS Outputs Drives either a 50-ohm or 100-ohm load (selectable) Low input capacitance Low output skew Low propagation delay Typical (tpd < 4 ns) Packages available include: TSSOP Does not exceed Bellcore 802.3 standards Operation at => 350 MHz – 700 Mbps Description This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DL818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVDS output pairs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. The Cypress CY2DL818 is ideal for both level translations from single-ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL818 has configurable input and output functions. The input can be selectable for LVCMOS/LVTTL, LVPECL, or LVDS signals, while the output drivers support standard and high-drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device. Block Diagram 37 36 Pin Configuration Q1A Q1B 35 34 Q2A Q2B (LVPECL / LVDS / LVTTL) 10 11 28 27 31 30 Q4A Q4B Q5A Q5B Q6A Q6B INPUT A INPUT B InConfig 6 26 25 24 23 VDD GND INPUT A INPUT B GND VDD VDD VDD VDD VDD GND GND CY2DL 818 INPUT 33 32 Q3A Q3B GND VDD VDD VDD VDD InConfig CNTRL Q7A Q7B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND 38 pin TSSOP 22 21 Q8A Q8B CNTRL 7 OUTPUT (LVDS) Cypress Semiconductor Corporation Document #: 38-07058 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 15, 2002 CY2DL818 Pin Description Pin Number 1, 9,12, 18,19,20,38 2,3,4,5,8, 13 14,15,16,17,29 10,11 Pin Name GND VDD Input A, Input B(#) Pin Standard Interface POWER Ground POWER Power Supply Pin Description 37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 6 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, Q6A, Q6B, Q7A, Q7B, Q8A, Q8B InConfig Default: LVPECL / LDVS Differential input pair or single line. Optional: LVTTL/LVCMOS LVPECL/LVDS default. See InConfig below. single pin. LDVS Differential Outputs LVTTL / LVCMOS 7 CNTRL LVTTL / LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) To LVTTL/LVCMOS (logic = 1) “default pull-up” See Figure 5 and Figure 6 for additional information Converts into a high-speed driver. Logic = 0 = 100 ohm Logic = 1 = 50-ohm “default pull-up” See Figure 7 for additional Information Output Drive Control for Standard and Bus/B/Hi-Drive CNTRL Pin 7 Binary Value 0 1 Drive STD Standard Hi-drive/Bus/B Impedance 100 Ohms 50 Ohms 100 Ohms 50 Ohms Output Voltage Value VO = Voutput V = 1/2 * VO V = 2 * VO V = VO Input Receiver Configuration for Differential or LVTTL/LVCMOS InCONFIG Pin 6 Binary Value 1 0 Input Receiver Family LVTTL in LVCMOS LVDS LVPECL Input Receiver Type Single-ended non-inverting, inverting, void of bias resistors. Low-voltage differential signaling Low-voltage pseudo (positive) emitter coupled logic Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal Input Condition Input B (–) Pin 11 Input A (+) Pin 10 Input B (–) Pin 11 Input A (+) Pin 10 Input A (+) Pin 10 Input B (–) Pin 11 Input A (+) Pin 10 Input B (–) Pin 11 LVTTL/LVCMOS INPUT LOGIC Input Logic Input Input – Bar Input Input – Bar Input Input – Bar Input Input – Bar Output Logic Q Pins, Q1A or Q1 Input Input – Bar Input – Bar Input Input Input – Bar Input – Bar Input Min. Typ. Max. 0.40 40 0.5 80 Unit mA/MHz mA Ground VCC Ground VCC Power Supply Characteristics Parameter ICCD IC Description Test Conditions Dynamic Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open Total Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open fL = 100 MHz Document #: 38-07058 Rev. *B Page 2 of 8 CY2DL818 Maximum Ratings[1][2] Storage Temperature: ................................ –65°C to + 150°C Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential (Inputs and VCC only)....................................... –0.3V to 4.6V Supply Voltage to Ground Potential (Outputs only) ........................................ –0.3V to VDD + 0.3V DC Input Voltage ................................... –0.3V to VDD + 0.3V DC Output Voltage................................. –0.3V to VDD + 0.9V Power Dissipation........................................................ 0.75W DC Electrical Characteristics: 3.3V–LVDS Input Parameter VID VIC VIH VIL IIH IIL II Description Magnitude of Differential Input Voltage Common-mode of Differential Input VoltageIVIDI (min. and max.) Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max VDD = Max VDD = Max, VIN = VDD(max.) InConfig/Cntrl Pins VIN = VDD VIN = VSS Conditions Min. 100 2 0.8 ±10 ±10 ±20 ±20 ±20 Typ. Max. Unit 600 mV V V V µA µA µA IVIDI/2 2.4 – (IVIDI/2) DC Electrical Characteristics: 3.3V–LVPECL Input Parameter I VID I Description Differential input voltage p-p Common-Mode Voltage Input High Current Input Low Current VDD = Max VDD = Max Conditions Guaranteed Logic High Level VIN = VDD VIN = VSS Min. 400 1.65 Typ. Max. 2400 2.25 Unit mV V µA µA VCM IIH IIL ±10 ±10 ±20 ±20 DC Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input Parameter Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis Conditions Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max VDD = Max VDD = Max., VIN = VDD(Max) VDD = Min., IIN = -18mA –0.7 80 VIN = 2.7V VIN = 0.5V Min. 2 0.8 1 –1 20 –1.2 Typ. Max. Unit V V µA µA µA V mV VIH VIL IIH IIL II VIK VH DC Electrical Characteristics: 3.3V–LVDS OUTPUT Parameter I VOD I Risetime Falltime Risetime Falltime IOS VOH VOL Description Differential Output Voltage p-p Pin Control (pin 7) logic is “FALSE” defaulting to 100-ohm output DIfferential 20% to 80% Pin Control (pin 7) logic is “TRUE” setting 50-ohm output drivers differential 20% to 80% Output Short Circuit Output Voltage high Output Voltage low Conditions VDD = 3.3V, VIN = VIH or VIL CL – 10 pF RL and CL to GND CL = Cintrinsic and Cexternal See Figure 3 CL – 10 pF RL and CL to GND CL = Cintrinsic and Cexternal See Figure 3 DOUT = 0V or DOUT- = 0V RL = 100 ohm 925 RL = 100 ohm Min. 0.25 800 800 RL = 50 ohm 350 350 Typ. Max. 0.55 1500 1500 600 600 –10 1550 Unit V ps ps ps ps mA mV mV Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07058 Rev. *B Page 3 of 8 CY2DL818 AC Switching Characteristics @ 3.3 V VDD = 3.3V ±5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tSK(0) tSK(p) tSK(t) Description Propagation Delay – Low to High Propagation Delay – High to Low Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. 200 1.6 Conditions Min. Typ 4.5 4.5 200 Max Unit ns ns ps ps ns High Frequency Parametrics Parameter Fmax Description Maximum frequency VDD = 3.3V Deterministic Jitter Conditions 50% duty cycle tW(50-50) Standard Load Circuit. LVDS VID = 100 mV 50% duty cycle tW(50-50) Standard Load Circuit. LVDS VID = 100 mV 50 Min. Typ Max 400 Unit MHz Dj ps Idd @ 25° C Idd (mA) vs. Input Freq. (MHz) 200 180 160 140 High or B Drive Curves 120 100 80 60 Standard Drive Curves 40 20 0 40 140 240 340 440 540 Idd (mA) Input Freq. (MHz) LD 3.135 LD 3.3 LD 3.465 HD 3.135 HD 3.3 HD 3.465 Figure 1. IDD Current vs. Frequency in Low Drive and High Drive Full Load Document #: 38-07058 Rev. *B Page 4 of 8 CY2DL818 A Pulse Generator TPA 10pF B 50 TPC 50 TPB Standard Termination V1A V1B V0Y V0Z T PLH TPHL 80% 0V Differential V0Y - V0Z 20% 1.4 V 0V Differential 1.0 V 1.4 V 0V Differential 1.0 V tR tF Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6] A P u ls e G e n e r a to r TPA 50 TP C B 50 TP B VOC VOD S t a n d a r d T e r m in a t io n V I( A ) V I( B ) V o c (p p ) 1 .4 0 V 1 .0 V N e x t D e v ic e VDD V o c (s s ) Figure 3. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[3,4,5,6,7] Notes: 3. All input pulses are supplied by a frequency generator with the following characteristics: TR and tF ≤ 1 ns; pulse rate = 50 Mpps; pulse width = 10 ± 0.2 ns. 4. RL = 50 ohm/100 ohm ± 1%. 5. CL includes instrumentation and fixture capacitance within 6 mm of the DUT. 6. TPA and B are used for prop delay and Rise/Fall Measurements. TPC is used for VOC measurements only. 7. All outputs should be loaded, used or not, in order to minimize noise and currents. Document #: 38-07058 Rev. *B Page 5 of 8 CY2DL818 A Pulse Generator TPA 10pF B 50 TPC 50 TPB Standard Termination VI(A) VI(B) 1.4V 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 4. Test Circuit and Voltage Definitions for the Differential Output Signal [3,4,5,6] INPUT A LVCMOS / LVTTL INPUT B GND InConfig 1 LVTTL/LVCMOS Figure 5. InConfig Control for LVCMOS Input[8] LVPECL & LVDS In C o n fig 0 L V D S /L V P E C L Figure 6. InConfig Control for Differential Input[9] 0 S ta n d a rd CNTRL 1 100 50 100 H i D r iv e B 50 O hm s Ohm s O hm s Ohm s ’V o = V o ’V o = 1 /2 V o ’V o = 2 V o ’V o = V o Figure 7. CNTRL Control for Standard or High-drive Drivers[10] Notes: 8. See Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal on page 2. 9. LVPECL or LVDS differential input value. 10. Standard 100-ohm output impedance: high-drive 50-ohm output impedance. Document #: 38-07058 Rev. *B Page 6 of 8 CY2DL818 Ordering Information Part Number CY2DL818ZI CY2DL818ZIT CY2DL818ZC CY2DL818ZCT Package Type 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-pin TSSOP 38-pin TSSOP–Tape and Reel Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0° to 70°C Commercial, 0° to 70°C Package Drawing and Dimensions 38-pin TSSOP (4.40 mm body) Z38 51-85151-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07058 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2DL818 Document Title: CY2DL818 1:8 Clock Fanout Buffer Document Number: 38-07058 Rev. ** *A *B ECN No. 115151 117611 122745 Issue Date 05/30/02 09/16/02 12/15/02 Orig. of Change EHX RGL RBI New Data Sheet Changed the figure cross reference in page 2 and added a note 6 in page 5 Added power-up requirements to maximum ratings information. Description of Change Document #: 38-07058 Rev. *B Page 8 of 8