CY2DP3120AIT

FastEdge™ Series CY2DP3120 1:20 Differential Clock/Data Fanout Buffer Features • Twenty ECL/PECL differential outputs • One ECL/PECL compatible differential or single-ended clock inputs • One HSTL compatible differential or single-ended clock inputs • Hot-swappable/-insertable • 50 ps output-to-output skew • 150 ps device-to-device skew • 500 ps propagation delay (typical) • 1.4 ps RMS period jitter (max.) • 1.5 GHz Operation (2.7 GHz max. toggle frequency) • PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V • Industrial temperature range: –40°C to 85°C • 52-pin 1.4-mm TQFP package • Temperature compensation like 100K ECL • Pin compatible with MC100ES6221 Functional Description The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3120 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ECL/PECL signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point. Since the CY2DP3120 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3120 delivers consistent performance over various platforms. Block Diagram Pin Configuration VCC CLKA CLKA# VCC VCC CLK_SEL 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 38 2 37 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 VCC Q0# Q1# Q2# Q3# Q4# Q5# Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q6# Q7 Q7# Q8 Q8# Q9 Q9# Q10 Q10# Q11 Q11# VCC Q0 Q 0# VEE CLKA CLKA# VBB CLKB CLKB# VEE Q19# Q19 Q18# Q18 VCC CLKB CLKB# Q 19 Q 19# VBB VEE CLK_SEL CY2DP3120 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC Q17 Q16 Q15 Q14 Q13 Q17# Q16# Q15# Q14# Q13# Q12# Q12 VEE Cypress Semiconductor Corporation Document #: 38-07514 Rev.*C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 28, 2004 FastEdge™ Series CY2DP3120 Pin Definitions[1, 2, 3] Pin 3 4 6 5 7 8 9 1,2,14,27,40 Name CLKA, VBB[3] CLKA# CLKB, CLKB# VEE[2] VCC I/O I,PD O I,PD -PWR +PWR O Type ECL/PECL/HSTL Input clock select ECL/PECL Bias HSTL Power Power ECL/PECL Differential input clocks Reference voltage output Differential input clocks Alternate differential input clocks Alternate differential input clocks Negative supply Positive Supply True output Description CLK_SEL I,PD I,PD/PU ECL/PECL I,PD/PU HSTL 52,50,48,46,44,42,39,37, Q(0:19) 35,33,31,29,26,24,22,20, 18,16,13,11 51,49,47,45,43,41,38,36, Q#(0:19) O 34,32,30,28,25,23,21,19, 17,15,12,10 Table 1. Control CLK_SEL 0 1 ECL/PECL Complement output Operation CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations CLKB, CLKB# input pair is active. CLKB can be driven with HSTL-compatible signals with respective power configurations Governing Agencies The following agencies provide specifications that apply to the CY2DP3120. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name JEDEC Specification JESD 020B (MSL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) 883E Method 1012.1 (Thermal Theta JC) Mil-Spec Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|). Document #: 38-07514 Rev.*C Page 2 of 9 FastEdge™ Series CY2DP3120 Absolute Maximum Ratings Parameter VCC VEE TS TJ ESDh MSL Description Positive Supply Voltage Negative Supply Voltage Temperature, Storage Temperature, Junction ESD Protection Moisture Sensitivity Level Assembled Die Condition Non-Functional Non-Functional Non-Functional Non-Functional Human Body Model 2000 3 50 Min. –0.3 -4.6 –65 Max. 4.6 0.3 +150 150 Unit V V °C °C V N.A. gates Gate Count Total Number of Used Gates Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter IBB LUI TA ØJc ØJa IEE CIN LIN VIN VTT VOUT IIN Description Output Reference Current Latch Up Immunity Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient Maximum Quiescent Supply Current Input pin capacitance Pin Inductance Input Voltage Output Termination Voltage Output Voltage Input Current (ECL,PECL and HSTL)[7] Relative to VCC[6] Relative to VCC[6] Relative to VCC[6] VIN = VIL, or VIN = VIH –0.3 –0.3 VCC – 2 VCC + 0.3 l150l Condition Relative to VBB Functional, typical Functional Functional Functional VEE pin –40 22[4] 60[4] 250[5] 3 1 VCC + 0.3 100 +85 Min. Max. |200| Unit uA mA °C °C/W °C/W mA pF nH V V V uA PECL/HSTL DC Electrical Specifications Parameter VCC VCMR VX VOH VOL VIH VIL VBB[3] Description Operating Voltage PECL Input Differential Crosspoint Voltage[8] Condition 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V Differential operation Min. 2.375 3.135 1.2 0.68 VCC – 1.25 VCC – 1.995 VCC –1.995 VCC – 1.165 VCC – 1.945 [11] Max. 2.625 3.465 VCC 0.9 VCC – 0.7 VCC – 1.5 VCC – 1.3 VCC – 0.880 [11] VCC – 1.625 Unit V V V V V V V V V HSTL Input Differential Crosspoint Volt- Standard Load Differential age[9] Operation Output High Voltage Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% Input Voltage, High Input Voltage, Low Output Reference Voltage IOH = –30 mA[10] IOL = –5 mA[10] Single-ended operation Single-ended operation Relative to VCC[6] VCC – 1.620 VCC – 1.220 V Notes: 4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 6. where VCC is 3.3V±5% or 2.5V±5% 7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. Refer to Figure 1 9. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig. 2. 10. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 11. VIL will operate down to VEE; VIH will operate up to VCC Page 3 of 9 Document #: 38-07514 Rev.*C FastEdge™ Series CY2DP3120 ECL DC Electrical Specifications Parameter VEE VCMR VOH VOL VIH VIL VBB[3] Description Negative Power Supply ECL Input Differential cross point voltage[8] Output High Voltage Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% Input Voltage, High Input Voltage, Low Output Reference Voltage Condition –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V Differential operation IOH = –30 mA[10] IOL = –5 mA[10] Single-ended operation Single-ended operation Min. –2.625 –3.465 VEE + 1.2 –1.25 –1.995 –1.995 –1.165 –1.945 [11] – 1.620 Max. –2.375 –3.135 0V –0.7 –1.5 –1.3 –0.880 [11] –1.625 – 1.220 Unit V V V V V V V AC Electrical Specifications Parameter VPP FCLK TPD VDIF Vo VCMRO tsk(0) tsk(PP) TPER tsk(P) TR,TF Description Input Frequency Propagation Delay CLKA or CLKB to Output pair HSTL Differential Input Voltage[12] Output Voltage (peak-to-peak; see Figure 3) Output Common Voltage Range (typical) Output-to-output Skew Part-to-Part Output Skew Output Period Jitter (rms)[14] Output Pulse Skew[] 660 MHz [13], See Figure 3 660 MHz 660 MHz [13] Condition 50% duty cycle Standard load 660 MHz [13] Duty Cycle Standard Load Differential Operation < 1 GHz Min. 0.1 400 0.4 0.375 Max. 1.3 1.5 750 1.9 – Unit V GHz ps V V V ECL/PECL Differential Input Voltage[8] Differential operation VCC – 1.425 – – – See Figure 3 – 0.08 50 150 1.4 50 0.3 ps ps ps ps ns 660 MHz [13] [13], Output Rise/Fall Time (see Figure 3) 660 MHz 50% duty cycle Differential 20% to 80% Notes: 12. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew 13. 50% duty cycle; standard load; differential operation 14. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07514 Rev.*C Page 4 of 9 FastEdge™ Series CY2DP3120 Timing Definitions VCC VCM R M ax = VCC V IH VPP V P P ra n g e 0 .1 V - 1 .3 V VCM R V IL V C M R M in = V E E + 1 . 2 VEE Figure 1. PECL/ECL Input Waveform Definitions VCC V C C = 3 .3 V V IH V X m a x = 0 .9 V V D IF V IL V D IF = > = 0 .4 V m in VX VEE V E E = 0 .0 V V X M in = 0 .6 8 Figure 2. HSTL Differential Input Waveform Definitions tr, tf, 2 0 -8 0 % VO Figure 3. ECL/LVPECL Output In p u t C lo c k VPP TPLH, TPD O u tp u t C lo c k TPHL VO tS K (O ) A n o th e r O u tp u t C lo c k Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Document #: 38-07514 Rev.*C Page 5 of 9 FastEdge™ Series CY2DP3120 Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT RT = 50 ohm P u ls e G e n e ra to r Z = 50 ohm 5" VTT RT = 50 ohm Zo = 50 ohm RT = 50 ohm VTT DUT C Y2D P3120 Zo = 50 ohm 5" RT = 50 ohm VTT Figure 5. CY2DP3120 AC Test Reference Applications Information Termination Examples CY2DP3120 VCC 5" VTT RT = 50 ohm Zo = 50 ohm 5" RT = 50 ohm VTT VEE Figure 6. Standard LVPECL – PECL Output Termination CY2DP3120 VCC 5" VTT RT = 50 ohm Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 7. Driving a PECL/ECL Single-ended Input Document #: 38-07514 Rev.*C Page 6 of 9 FastEdge™ Series CY2DP3120 CY2DP3120 V C C = 3 .3 V 5" 3 .3 V 120 ohm LVDS Zo = 50 ohm 5" 33 ohm ( 2 p la c e s ) 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) VEE = 0V L V P E C L to LVDS Figure 8. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface VDD-2 X VCC Y Z One output is shown for clarity Figure 9. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and supplies. Ordering Information Part Number CY2DP3120AI CY2DP3120AIT CY2DP3120AXI CY2DP3120AXIT 52-pin TQFP 52-pin TQFP – Tape and Reel 52-pin TQFP - Lead Free 52-pin TQFP – Tape and Reel - Lead Free Package Type Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Document #: 38-07514 Rev.*C Page 7 of 9 FastEdge™ Series CY2DP3120 Package Diagram 52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52 51-85131-** FastEdge is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07514 Rev.*C Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. FastEdge™ Series CY2DP3120 Document History Page Document Title: CY2DP3120 FastEdge™ Series 1:20 Differential Clock/Data Fanout Buffer Document Number: 38-07514 REV. ** *A ECN NO. 122438 125457 Issue Date 12/05/02 04/17/03 Orig. of Change RGL RGL New data sheet Corrected typo Q14 to Q4 in pin 44 in the pin configuration diagram Changed pin #s 1,14,27 and 40 from VCC to VCCO Changed title to FastEdge™ Series 1:20 Differential Clock/Data Fanout Buffer Supplied data to all TBD’s to match the device Description of Change *B *C 229391 247606 See ECN See ECN RGL RGL/GGK Changed VOH and VOL to match the Char Data Document #: 38-07514 Rev.*C Page 9 of 9