CY2SSTV855_06

CY2SSTV855 Differential Clock Buffer/Driver Features • Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for electromagnetic interference (EMI) reduction • 28-pin TSSOP package • Conforms to JEDEC DDR specifications Functional Description The CY2SSTV855 is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs. In support of low power requirements, when power-down is HIGH, the outputs switch in phase and frequency with the input clock. When power-down is LOW, all outputs are disabled to a high-impedance state and the PLL is shut down. The device supports a low-frequency power-down mode. When the input is < 20 MHz, the PLL is disabled and the outputs are put in the Hi-Z state. When the input frequency is > 20 MHz, the PLL and outputs are enabled. When AVDD is tied to ground, the PLL is turned off and bypassed with the input reference clock gated to the outputs. The Cypress CY2SSTV855 is Spread Aware and supports tracking of Spread Spectrum clock inputs to reduce EMI Block Diagram Pin Configuration YT0 YC0 PWRDWN AVDD Powerdown and test logic YT1 YC1 GND YC0 YT0 VDDQ GND CLKINT CLKINC VDDQ AVDD AGND VDDQ YT1 YC1 GND YT2 YC2 CLKINT CLKINC FBINT FBINC PLL YT3 YC3 FBOUTT FBOUTC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND YC3 YT3 VDDQ PWRDWN FBINT FBINC VDDQ FBOUTC FBOUTT VDDQ YT2 YC2 GND 28-pin TSSOP Cypress Semiconductor Corporation Document #: 38-07459 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 2, 2006 CY2SSTV855 CY2SSTV855 Pin Definition[1, 2] Pin 6 7 22 23 3,12,17,26 2,13,16,27 19 Name CLKINT CLKINC FBINC FBINT YT(0:3) YC(0:3) FBOUTT I/O I I I I O O O Description True Clock Input. Low Voltage Differential True Clock Input. Complementary Clock Input. Low Voltage Differential Complementary Clock Input. Feedback Complementary Clock Input. Differential Input Connect to FBOUTC for accessing the PLL. Feedback True Clock Input. Differential Input Connect to FBOUTT for accessing the PLL. True Clock Outputs. Differential Outputs. Complementary Clock Outputs. Differential Outputs. Feedback True Clock Output. Differential Outputs. Connect to FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Complementary Clock Output. Differential Outputs. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Control input to turn device in the power-down mode. 2.5V Power Supply for Output Clock Buffers.2.5V Nominal. 2.5V Power Supply for PLL. 2.5V Nominal. Ground Analog Ground. 2.5V Analog Ground. connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When AVDD is strapped LOW, the PLL is turned off and bypassed for test purposes. 20 FBOUTC O 24 4,8,11,18,21,25 9 1,5,14,15,28 10 PWRDWN VDDQ AVDD GND AGND I Zero-delay Buffer When used as a zero-delay buffer the CY2SSTV855 will likely be in a nested clock tree application. For these applications the CY2SSTV855 offers a differential clock input pair as a PLL reference. The CY2SSTV855 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback differential input, FBINT/C, is connected to the feedback output, FBOUTT/C. By Function Table Inputs AVDD GND GND 2.5V 2.5V 2.5V PWRDWN H H H H X CLKINT L H L H < 20 MHz CLKINC H Outputs YT(0:3) L H L H Hi-Z YC(0:3) H L H L Hi-Z FBOUTT L H L H Hi-Z FBOUTC H L H L Hi-Z PLL BYPASSED/OFF BYPASSED/OFF On On Off L H L < 20 MHz Notes: 1. PU = internal pull-up. 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07459 Rev. *F Page 2 of 7 CY2SSTV855 Differential Parameter Measurement Information CLKINT CLKINC FBINT FBINC t(∅)n t(∅)n = t(∅) n+1 Σ 1=N n N t(∅)n N (is large number of samples) Figure 1. Static Phase Offset CLKINT CLKINC FBINT FBINC td(∅) t(∅) td(∅) td(∅) t( ∅ ) td(∅) Figure 2. Dynamic Phase Offset Y[0:3], FBOUTT YC[0:3], FBOUTC Y[0:3], FBOUTT YC[0:3], FBOUTC tsk(o) Figure 3. Output Skew Document #: 38-07459 Rev. *F Page 3 of 7 CY2SSTV855 Differential Parameter Measurement Information (continued) YT[0:3], FBOUTT YC[0:3], FBOUTC t(hper_n) 1 f(o) t(hper_N+1) tjit(hper) = thper(n) - 1 2x fo Figure 4. Half-period Jitter YT[0:3], FBOUTT YC[0:3], FBOUTC t c(n) tjit(cc) = tc(n)-tc(n+1) Figure 5. Cycle-to-cycle Jitter t c(n) VDD VDD V D D /2 16pF C LKT 60 O hm VTR R T = 120 O hm C LKC 60 O hm 16pF V D D /2 VCP R e c e iv e r Figure 6. Differential Signal Using Direct Termination Resistor Document #: 38-07459 Rev. *F Page 4 of 7 CY2SSTV855 Absolute Maximum Conditions[3] Input Voltage Relative to VSS:...............................VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum Power Supply: ................................................3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Electrical Specifications (AVDD = VDDQ = 2.5V ± 5%, TA = –40°C to +85°C)[4] Parameter VID VIX IIN IOL IOH VOL VOH VOUT VOC IOZ IDDQ IDD Cin Description Differential Input Voltage [5] [6] Conditions CLKINT, FBINT CLKTIN, FBINT VIN = 0V or VIN = VDDQ, CLKINT, FBINT VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT = 1V VDDQ = 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = –12 mA Min. 0.36 (VDDQ/2) – 0.2 –10 26 –18 1.7 1.1 (VDDQ/2) – 0.2 Typ. VDDQ/2 – 35 –32 – – – VDDQ/2 Max. VDDQ + 0.6 (VDDQ/2) + 0.2 10 – – 0.6 – VDDQ – 0.4 (VDDQ/2) + 0.2 10 300 12 – Unit V V µA mA mA V V V V µA mA mA pF Differential Input Crossing Voltage Input Current Output Low Current Output High Current Output Low Voltage Output High Voltage Output Voltage Swing[7] Output Crossing Voltage[8] High-Impedance Output Current Dynamic Supply Current[9] PLL Supply Current Input Pin Capacitance VO = GND or VO = VDDQ VDDQ = 170 MHz AVDD only –10 – – – 235 9 4 AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = –40°C to +85°C)[10, 11] Parameter fCLK tDC tLOCK tSL(O) tPZL, tPZH tPLZ, tPHZ tCCJ tJITT(H-PER) Description Operating Clock Frequency Input Clock Duty Cycle[12] Maximum PLL lock Time Output Clocks Slew Rate Output Enable Time (all Cycle to Cycle Jitter Half-period jitter outputs)[13] Output Disable Time (all outputs)[13] Conditions AVDD = 2.5V ± 0.2V Min. 60 40 Typ. Max. 170 60 100 2 Unit MHz % µs V/ns ns ns 20% to 80% of VOD 1 30 10 f > 66 MHz f > 66 MHz –100 –100 100 100 ps ps Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Unused inputs must be held HIGH or LOW to prevent them from floating. 5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 6. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing. 7. For load conditions see Figure 6. 8. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6. 9. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 6. 10. Parameters are guaranteed by design and characterization. Not 100% tested in production. 11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a downspread of –0.5% 12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC, where the cycle time (tC) decreases as the frequency goes up. 13. Refers to transition of non-inverting output. 14. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 6. Document #: 38-07459 Rev. *F Page 5 of 7 CY2SSTV855 AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = –40°C to +85°C)[10, 11] (continued) Parameter tPLH tPHL tSK(0) t(Ø) tD(Ø) Description Low-to-High Propagation Delay, CLKINT to YT[0:3] High-to-Low Propagation Delay, CLKINT to YT[0:3] Any Output to Any Output Skew[14] Static Phase Offset[14] Dynamic Phase Offset Conditions Min. 1.5 1.5 – –450 Typ. 3.5 3.5 – – – Max. 6 6 100 450 350 Unit ns ns ps ps ps f > 66 MHz –350 Ordering Information Part Number CY2SSTV855ZC CY2SSTV855ZCT CY2SSTV855ZI CY2SSTV855ZIT Package Type 28-pin TSSOP 28-pin TSSOP – Tape and Reel 28-pin TSSOP 28-pin TSSOP – Tape and Reel 28-pin TSSOP 28-pin TSSOP – Tape and Reel 28-pin TSSOP 28-pin TSSOP – Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Industrial, –40° to 85°C Industrial,–40° to 85°C Commercial, 0° to 70°C Commercial, 0° to 70°C Industrial, –40° to 85°C Industrial,–40° to 85°C Lead Free CY2SSTV855ZXC CY2SSTV855ZXCT CY2SSTV855ZXI CY2SSTV855ZXIT Package Drawing and Dimensions 28-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z28.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.16 gms 4.30[0.169] 4.50[0.177] 6.25[0.246] 6.50[0.256] PART # Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG. 28 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 9.60[0.378] 9.80[0.386] 51-85120-*A Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07459 Rev. *F Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2SSTV855 Document History Page Document Title: CY2SSTV855 Differential Clock Buffer/Driver Document #: 38-07459 REV. ** *A *B ECN NO. 117544 122934 124087 Issue Date 09/09/02 12/18/02 04/23/03 Orig. of Change HWT RBI RGL New data sheet Description of Change Add power up requirements to maximum ratings information Changed the package drawing and dimension from Z28 to Z29 Corrected the block diagram Changed the Output Enable/Disable time from 3/3 to 30/10 ns Eliminated Dynamic Phase Offset spec. Changed the Phase Error Jitter spec. from ±50 to ±150 ps Added an Industrial Grade Devices (temp from –40°C to 85). Removed “PRELIMINARY” Added Lead Free Devices Changed the static and dynamic offset numbers *C *D *E *F 215389 224444 401500 436956 See ECN See ECN See ECN See ECN RGL RGL RGL RGL Document #: 38-07459 Rev. *F Page 7 of 7