CY3125R62

5 CY3125 Warp® CPLD Development Tool for UNIX • VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following features: — Designs are portable across multiple devices and/or EDA environments — Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design — Support for functions and libraries facilitating modular design methodology • IEEE Standard 1076 and 1164 VHDL synthesis supports: — Enumerated types — Operator overloading — For... Generate statements — Integers • IEEE Standard 1364 Verilog synthesis supports: — Reduction and conditional operators — Blocking and non-blocking procedural assignments — While loops — Industry-standard PLDs (16V8, 20V8, 22V10) • VHDL and Verilog timing model output for use with third-party simulators • Static Timing Report: — Provides timing information for any path broken down by the different steps of the path • Architecture Explorer and Dynamic Timing Analysis for PSI, Delta39K and Quantum38K devices: — Graphical representation of exactly how your design will be implemented on your specific target device — Zoom from the device level down to the macrocell level — Determine the timing for any path and view that path on a graphical representation of the chip • Workstation support for Sun Solaris™ • On-line documentation and help Functional Description DESIGN ENTRY Features Verilog VHDL State Machine — Structural Verilog and VHDL — Designs can include multiple entry methods (but only one HDL language) in a single design. • UltraGen™ Synthesis and Fitting Technology: — Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device. — User-selectable speed and/or area optimization on a block-by-block basis — Perfect communication between synthesis and fitting — Automatic selection of optimal flip-flop type (D type/T type) — Automatic pin assignment • Supports for the following Cypress Programmable Logic Devices: — PSI™ (Programmable Serial Interface™) — Delta39K™ CPLDs — Quantum38K™ CPLDs — Ultra37000™ CPLDs — FLASH370i™ CPLDs — MAX340™ CPLDs Cypress Semiconductor Corporation Document #: 38-03046 Rev. *A • UltraGenTM Synthesis and Fitting VERFICA TION — Boolean COMPILATION — Integers • Several design entry methods support high-level and low-level design descriptions: — Behavioral VHDL and Verilog (IF...THEN...ELSE; CASE...) Programming File Timing Simulator VHDL, Verilog &Third-Party Simulation Models Figure 1. Warp® VHDL Design Flow Warp® is a state-of-the-art HDL compiler for designing with Cypress’s Complex Programmable Logic Devices (CPLDs). Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 Verilog as its Hardware Description Languages (HDL) for design entry. Then, it synthesizes and optimizes the entered design, and outputs a JEDEC or Intel hex file for the desired PLD or CPLD (see Figure 1). Furthermore, Warp accepts VHDL or Verilog produced by the Active-HDL FSM graphical Finite State Machine editor. For simulation, Warp provides a timing simulator, as well as VHDL and Verilog timing models for use with third party simulators. 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 9, 2002 CY3125 VHDL and Verilog Compilers VHDL and Verilog are powerful, industry standard languages for behavioral design entry and simulation, and are supported by all major vendors of EDA tools. They allow designers to learn a single language that is useful for all facets of the design process. VHDL and Verilog offer designers the ability to describe designs at many different levels. At the highest level, designs can be entered as a description of their behavior. This behavioral description is not tied to any specific target device. As a result, simulation can be done very early in the design to verify correct functionality, which significantly speeds the design process. The Warp syntax for VHDL and Verilog includes support for intermediate level entry modes such as state tables and Boolean entry. At the lowest level, designs can be described using gate-level descriptions. Warp gives the designer the flexibility to intermix all of these entry modes. In addition, Verilog and VHDL allow you to design hierarchically, building up entities in terms of other entities. This allows you to work either “top-down” (designing the highest levels of the system and its interfaces first, then progressing to greater and greater detail) or “bottom-up” (designing elementary building blocks of the system, then combining these to build larger and larger parts) with equal ease. Because these languages are IEEE standards, multiple vendors offer tools for design entry and simulation at both high and low levels and synthesis of designs to different silicon targets. The use of device-independent behavioral design entry gives users the freedom to easily migrate to high-volume technologies. The wide availability of VHDL and Verilog tools provides complete vendor independence as well. Designers can begin their project using Warp for Cypress CPLDs and convert to high volume ASICs using the same VHDL or Verilog behavioral description with industry-standard synthesis tools. The VHDL and Verilog languages also allow users to define their own functions. User-defined functions allow users to extend the capabilities of the language and build reusable files of tested routines. VHDL and Verilog provide control over the timing of events or processes. They have constructs that identify processes as either sequential, concurrent, or a combination of both. This is essential when describing the interaction of complex state machines. VHDL and Verilog are rich programming languages. Their flexibility reflects the nature of modern digital systems and allows designers to create accurate models of digital designs. Because they are not verbose languages they are easy to learn and compile. In addition, models created in VHDL and Verilog can readily be transported to other EDA Environments. Warp supports IEEE 1076/1164 VHDL including loops, for/generate statements, full hierarchical designs with packages, enumerated types, and integers as well as IEEE 1364 Verilog including loops, reduction and conditional operators. A VHDL Design Example Design Entry Warp descriptions specify: • The behavior or structure of a design, and • The mapping of signals in a design to the pins of a PLD/CPLD (optional) Document #: 38-03046 Rev. *A The part of a Warp description that specifies the behavior or structure of the design is called an entity/architecture pair. Entity/architecture pairs, as their name implies, are divided into two parts: an entity declaration, which declares the design’s interface signals (i.e., defines what external signals the design has, and what their directions and types are), and a design architecture, which describes the design’s behavior or structure. The entity portion of a design file is a declaration of what a design presents to the outside world (the interface). For each external signal, the entity declaration specifies a signal name, a direction and a data type. In addition, the entity declaration specifies a name by which the entity can be referenced in a design architecture. This section shows code segments from five sample design files. The top portion of each example features the entity declaration. Behavioral Description The architecture portion of a design file specifies the function of the design. As shown in Figure 1, multiple design-entry methods are supported in Warp. A behavioral description in VHDL often includes well known constructs such as If...Then...Else, and Case statements. Here is a code segment from a simple state machine design (soda vending machine) that uses behavioral VHDL to implement the design: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY drink IS PORT (nickel,dime,quarter,clock:#in std_logic; returnDime,returnNickel,giveDrink:out std_logic); END drink; ARCHITECTURE fsm OF drink IS TYPE drinkState IS (zero,five,ten,fifteen, twenty,twentyfive,owedime); SIGNAL drinkstatus:drinkState; BEGIN PROCESS BEGIN WAIT UNTIL clock = ’1’; giveDrink