CY62158H MoBL®
8-Mbit (1M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
8-Mbit (1M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
Functional Description
Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 16 A
CY62158H is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC.
Device is accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
■
High speed: 45 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction[1, 2]
■
Operating voltage range: 4.5 V to 5.5 V
■
1.0-V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Available in Pb-free 44-pin TSOP II package
Write to the device is performed by taking Chip Enable 1 (CE1)
LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE)
input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0 through
A19).
Read from the device is performed by taking Chip Enable 1 (CE1)
and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62158H on page 11 for a
complete description of read and write modes.
Logic Block Diagram – CY62158H
SENSE
AMPLIFIERS
1M x 8
RAM ARRAY
I/O0‐I/O7
COLUMN
DECODER
WE
OE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ECC DECODER
DATAIN
DRIVERS
ECC ENCODER
CE2
CE1
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate 2001 V
Storage temperature ............................... –65 °C to + 150 °C
Latch-up current ..................................................... >140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage to ground potential ..... –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z state[5] .................................. –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC[6]
Industrial
–40 C to +85 C
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to 85 C
Parameter
Description
45 ns
Test Conditions
Typ[7]
Max
2.4
–
–
–
–
–
–
0.4
V
Output HIGH
voltage
4.5 V to 5.5 V
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VOL
Output LOW
voltage
4.5 V to 5.5 V
VCC = Min, IOL = 2.1 mA
VIH[5]
Input HIGH
voltage
4.5 V to 5.5 V
–
2.2
–
VCC + 0.5
V
VIL[5]
Input LOW
voltage
4.5 V to 5.5 V
–
–0.5
–
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–1.0
–
+1.0
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
A
ICC
VCC operating supply current
VCC = Max, IOUT = 0 mA, f = 22.22 MHz
CMOS levels
(45 ns)
–
29.0
36.0
mA
f = 1 MHz
–
7.0
9.0
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V,
CMOS inputs;
VIN > VCC – 0.2 V, VIN < 0.2 V,
VCC = 4.5 to 5.5 V
f = fmax (address and data only),
–
5.5
16.0
A
25 °C[10]
–
5.5
6.5
A
[10]
40 °C
–
6.3
8.0
70 °C[10]
–
8.4
12.0
85 °C
–
12.0[10]
16.0
VOH
ISB1
[9]
ISB2
[9]
VCC = Min, IOH = –1.0 mA
Unit
Min
VCC –
0.4[8]
V
f = 0 (OE, and WE), VCC = VCC(max)
Automatic power down current – CE1 > VCC – 0.2 V or
CMOS inputs;
CE2 < 0.2 V, or
VCC = 4.5 to 5.5 V
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
8. This parameter is guaranteed by design and not tested.
9. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
10. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-96968 Rev. *E
Page 4 of 16
CY62158H MoBL®
Capacitance
Parameter[11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter[11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
66.93
°C/W
13.09
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
VCC
OUTPUT
R1
VHIGH
GND
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
5.0 V
Unit
R1
1800
R2
990
RTH
639
VTH
1.77
V
VHIGH
5.0
V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-96968 Rev. *E
Page 5 of 16
CY62158H MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Min
Typ[12]
Max
Unit
1.0
–
–
V
–
7.0
26.0
A
–
5.5
16.0
A
Chip deselect to data retention
time
0
–
–
–
Operation recovery time
45
–
–
ns
Description
VDR
VCC for data retention
ICCDR[13, 14]
Data retention current
Conditions
1.2 V < VCC < 2.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
2.2 V < VCC < 3.6 V or
4.5 V < VCC < 5.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR
[15]
tR[15, 16]
Data Retention Waveform
Figure 3. Data Retention Waveform
V CC
V C C (m in )
D A T A R E T E N T I O N M O D E
V D R = 1 . 0 V
tCDR
V C C (m in )
tR
CE1
(o r)
CE2
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
13. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
14. ICCDR is guaranteed only after device is first powered up to VCC(min) and brought down to VDR.
15. These parameters are guaranteed by design.
16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-96968 Rev. *E
Page 6 of 16
CY62158H MoBL®
Switching Characteristics
Parameter [17]
Description
45 ns
Unit
Min
Max
45.0
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
tOHA
Data hold from address change
tACE
–
45.0
ns
10.0
–
ns
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid
–
45.0
ns
tDOE
OE LOW to data valid / OE LOW to ERR valid
–
22.0
ns
tLZOE
[18, 19, 20]
OE LOW to Low Z
5.0
–
ns
tHZOE
OE HIGH to High Z[18, 19, 20, 21]
–
18.0
ns
10.0
–
ns
–
18.0
ns
0
–
ns
–
45.0
ns
tLZCE
tHZCE
CE1 LOW and CE2 HIGH to Low
Z[18, 19, 20]
CE1 HIGH and CE2 LOW to High
Z[18, 19, 20, 21]
power-up[20]
tPU
CE1 LOW and CE2 HIGH to
tPD
CE1 HIGH and CE2 LOW to power-down[20]
Write
Cycle[22, 23]
tWC
Write cycle time
45.0
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35.0
–
ns
tAW
Address setup to write end
35.0
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35.0
–
ns
tSD
Data setup to write end
25.0
–
ns
tHD
Data hold from write end
0
–
ns
–
18.0
ns
10.0
–
ns
tHZWE
tLZWE
WE LOW to High
Z[18, 19, 20, 21]
[18, 19, 20]
WE HIGH to Low Z
Notes
17. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified
otherwise.
18. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
19. Tested initially and after any design or process changes that may affect these parameters.
20. These parameters are guaranteed by design and are not tested.
21. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
23. The minimum write cycle pulse width for Write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of tHZWE and tSD.
Document Number: 001-96968 Rev. *E
Page 7 of 16
CY62158H MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[24, 25]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[25, 26, 27]
ADDRESS
tRC
CE
tPD
t HZCE
tACE
OE
t HZOE
t DOE
t LZOE
DATA I /O
HIGH IMPEDANCE
DATAOUT VALID
HIGH
IMPEDANCE
t LZCE
VCC
SUPPLY
CURRENT
tPU
ISB
Notes
24. The device is continuously selected. OE = VIL, CE = VIL.
25. WE is HIGH for read cycle.
26. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
27. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-96968 Rev. *E
Page 8 of 16
CY62158H MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled)[28, 29, 30]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
OE
tH Z O E
D A T A I/O
Note 31
tH D
tS D
D A T A I N V A L I D
Notes
28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
29. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
30. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH.
31. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-96968 Rev. *E
Page 9 of 16
CY62158H MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE Low)[32, 33, 34, 35]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
t PWE
WE
tSD
t HZWE
DATA I/O
Note 36
t LZWE
tHD
DATAIN VALID
Figure 8. Write Cycle No. 3 (CE Controlled)[32, 33, 34]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
t PWE
WE
OE
t HZOE
DATA I/O
Note 36
tHD
tSD
DATAIN VALID
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
34. Data I/O is in high impedance state if CE = VIH, or OE = VIH.
35. The minimum write cycle pulse width should be equal to the sum of the tHZWE and tSD.
36. During this period I/O are in the output state. Do not apply input signals.
Document Number: 001-96968 Rev. *E
Page 10 of 16
CY62158H MoBL®
Truth Table – CY62158H
CE1
CE2
WE
[37]
[37]
X[37]
OE
I/Os
Mode
Power
X
[37]
X
High Z
Deselect /
Power down
Standby (ISB2)
L
X[37]
X[37]
High Z
Deselect /
Power down
Standby (ISB2)
L
H
H
L
Data Out
(I/O0–I/O7)
Read
Active (ICC)
L
H
H
H
High Z
Output disabled Active (ICC)
L
H
L
X
Data In
(I/O0–I/O7)
Write
H
X
Active (ICC)
Note
37. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-96968 Rev. *E
Page 11 of 16
CY62158H MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62158H-45ZSXI
51-85087
Package Type (all Pb-free)
44-pin TSOP II (Pb-free)
Operating
Range
Industrial
CY62158H-45ZSXIT
Ordering Code Definitions
CY 621
5
8
H
XX - 45
ZS
X
I
T
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: I = Industrial
Pb-free
Package Type:
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: XX = No character or 18 or 30
No character = 5 V typ; 30 = 3 V typ; 18 = 1.8 V typ
Process Technology: H = 65 nm
Bus width: 8 = × 8
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-96968 Rev. *E
Page 12 of 16
CY62158H MoBL®
Package Diagram
Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-96968 Rev. *E
Page 13 of 16
CY62158H MoBL®
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
A
microampere
SRAM
Static Random Access Memory
s
microsecond
VFBGA
Very Fine-Pitch Ball Grid Array
mA
milliampere
WE
Write Enable
mm
millimeter
ECC
Error Correcting Code
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
Document Number: 001-96968 Rev. *E
Symbol
Unit of Measure
Page 14 of 16
CY62158H MoBL®
Document History Page
Document Title: CY62158H MoBL®, 8-Mbit (1M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-96968
Rev.
ECN No.
Orig. of
Change
Submission
Date
*B
5258628
NILE
05/06/2016
Changed status from Preliminary to Final.
*C
5430402
VINI
09/13/2016
Updated DC Electrical Characteristics:
Updated Note 5 (Replaced 2 ns with 20 ns).
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*D
5980470
AESATMP8
11/30/2017
Updated logo and Copyright.
*E
6122301
NILE
04/04/2018
Updated Features:
Referred Note 1 in “Embedded error-correcting code (ECC) for single-bit
error correction”.
Added Note 2 and referred the same note in “Embedded error-correcting
code (ECC) for single-bit error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-96968 Rev. *E
Description of Change
Page 15 of 16
CY62158H MoBL®
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-96968 Rev. *E
Revised April 4, 2018
Page 16 of 16