CY7B9930V-5AI

RoboClockII™ Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation Matched pair output skew < 200 ps Zero input-to-output delay 10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines Commercial temperature range with eight outputs at 200 MHz Industrial temperature range with eight outputs at 200 MHz 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs Multiply ratios of (1–6, 8, 10, 12) Operation up to 12x input frequency Individual output bank disable for aggressive power management and EMI reduction Output high impedance option for testing purposes Fully integrated PLL with lock indicator Low cycle-to-cycle jitter (2000V MIL-STD-883, Method 3015) Latch up current......................................................... >±200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ±10% 3.3V ±10% Electrical Characteristics Over the Operating Range Parameter VOH VOL IOZ VIH VIL II IlH IlL Description LVTTL HIGH voltage QFA[0:1], [1:2]Q[A:B][0:1] LOCK LVTTL LOW voltage QFA[0:1], [1:2]Q[A:B][0:1] LOCK High impedance state leakage current LVTTL Input HIGH LVTTL Input LOW LVTTL VIN >VCC LVTTL Input HIGH Current LVTTL Input LOW Current FBKA+, REF[A:B]± REFSEL, DIS[1:2] FBKA+, REF[A:B]± REFSEL, DIS[1:2] FBKA+, REF[A:B]± FBKA+, REF[A:B]± REFSEL, DIS[1:2] FBKA+, REF[A:B]± REFSEL, DIS[1:2] Min. < VCC < Max. Min. < VCC < Max. Min. < VCC < Max. VIN = VCC VIN = VCC/2 VIN = GND – –50 –200 VCC = GND, VIN = 3.63V VCC = Max., VIN = VCC VIN = VCC VCC = Max., VIN = GND Min. < VCC < Max. Min. < VCC < Max. Test Conditions VCC = Min., IOH = –30 mA IOH = –2 mA, VCC = Min. VCC = Min., IOL= 30 mA IOL= 2 mA, VCC = Min. Min. 2.4 2.4 – – –100 2.0 2.0 –0.3 –0.3 – – – –500 –500 0.87*VCC 0.47*VCC Max. – – 0.5 0.5 100 VCC+0.3 VCC+0.3 0.8 0.8 100 500 500 – – – 0.53*VCC 0.13*VCC 200 50 – Unit V V V V μA V V V V μA μA μA μA μA V V V μA μA μA LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK) LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2]) 3-Level Input Pins (FBDS[0:1], FS, Output_Mode) VIHH VIMM VILL IIHH IIMM IILL Three level input HIGH[4] Three level input Three level input HIGH current MID[4] Three level input pins Three level input LOW[4] Three level input MID Three level input pins current Three level input LOW current Three level input pins LVDIFF Input Pins (REF[A:B]±) VDIFF VIHHP VILLP VCOM Input differential voltage Highest input HIGH voltage Lowest input LOW voltage Common mode range (crossing voltage) 400 1.0 GND 0.8 VCC VCC VCC – 0.4 VCC mV V V V Note 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. Document Number: 38-07271 Rev. *C Page 5 of 11 [+] Feedback RoboClockII™ Junior, CY7B9930V, CY7B9940V Electrical Characteristics Over the Operating Range Parameter ICCI ICCN Description Internal operating current Output current dissipation/pair[6] CY7B9930V CY7B9940V CY7B9930V CY7B9940V VCC = Max., CLOAD = 25 pF, RLOAD = 50Ω at VCC/2, fMAX Operating Current VCC = Max., fMAX[5] – – – – 200 200 40 50 mA mA mA mA (continued) Test Conditions Min. Max. Unit Capacitance Parameter CIN Description Input capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Min. – Max. 5 Unit pF Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11] Parameter fin fout tSKEWPR tSKEWBNK tSKEW0 tSKEW1 tCCJ1-3 tCCJ4-12 tPD tPDDELTA tREFpwh tREFpwl Clock input frequency Clock input frequency Matched pair skew[12, 13] Description CY7B9930V CY7B9940V CY7B9930V CY7B9940V Intrabank skew[12, 13] Output-Output skew (same frequency and phase, rise to rise, fall to fall)[12, 13] Output-Output skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[12, 13] Cycle-to-cycle jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) Cycle-to-cycle jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) Propagation delay, REF to FB Rise Propagation delay difference between two devices[14] REF input (pulse width HIGH)[15] REF input (pulse width LOW)[15] time[16] CY7B9930/40V-2 CY7B9930/40V-5 Min. 12 24 12 24 – – – – – – –250 – 2.0 2.0 Max. 100 200 100 200 185 200 250 250 150 100 250 200 – – 2.0 2.0 Min. 12 24 12 24 – – – – – – –500 Max. 100 200 100 200 185 250 550 650 150 100 500 200 – – Unit MHz MHz MHz MHz ps ps ps ps ps PeakPeak ps PeakPeak ps ps ns ns tr/tf Output rise/fall 0.15 2.0 0.15 2.0 ns Notes 5. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B9930V, fNOM = 200 MHz for CY7B9940V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50Ω at VCC/2. 7. This is for non-three level inputs. 8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF. 9. Both outputs of pair must be terminated, even if only one is being used. 10. Each package must be properly decoupled. 11. AC parameters are measured at 1.5V, unless otherwise indicated. 12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω. 13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 15. Tested initially and after any design or process changes that may affect these parameters. 16. Rise and fall times are measured between 2.0V and 0.8V. Document Number: 38-07271 Rev. *C Page 6 of 11 [+] Feedback RoboClockII™ Junior, CY7B9930V, CY7B9940V Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11] (continued) Parameter tLOCK tRELOCK1 tRELOCK2 tODCV tPWH tPWL tPDEV tOAZ tOZA Description PLL lock time from power up PLL relock time (from same frequency, different phase) with stable power supply PLL Relock Time (from different frequency, different phase) with Stable Power Supply[17] Output duty cycle deviation from 50%[11] Output HIGH time deviation from 50%[18] Output LOW time deviation from 50%[18] ACTIVE[12, 20] Period deviation when changing from reference to reference[19] DIS[1:2] HIGH to output high impedance from DIS[1:2] LOW to output ACTIVE from output is high impedance[20, 21] CY7B9930/40V-2 CY7B9930/40V-5 Min. – – – –1.0 – – – 1.0 0.5 Max. 10 500 1000 1.0 1.5 2.0 0.025 10 14 Min. – – – –1.0 – – – 1.0 0.5 Max. 10 500 1000 1.0 1.5 2.0 0.025 10 14 Unit ms μs μs ns ns ns UI ns ns AC Test Loads and Waveform See note. [22] 3.3V R1 For LOCK output only R1 = 910 Ω R2 = 910 Ω CL < 30 pF OUTPUT For all other outputs R1 = 100 Ω CL R2 = 100 Ω CL < 25 pF up to 185 MHz 10 pF from 185 to 200 MHz (Includes fixture and probe capacitance) R2 (a) LVTTL AC Test Load 3.3V 2.0V GND < 1 ns 0.8V 2.0V 0.8V < 1 ns (b) TTL Input Test Waveform Notes 17. fNOM must be within the frequency range defined by the same FS state. 18. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 19. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period. 20. Measured at 0.5V deviation from starting voltage. 21. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 18 MHz, 10 pF from 185 to 200 MHz. 22. These figures are for illustration only. The actual ATE loads may vary. Document Number: 38-07271 Rev. *C Page 7 of 11 [+] Feedback RoboClockII™ Junior, CY7B9930V, CY7B9940V AC Timing Diagrams See note. [11] tREFpwl tREFpwh REF t SKEWPR tPD t PWH 2.0V FB 0.8V tCCJ1-3,4-12 Q [1:4]QA[0:1] t SKEWBNK [1:4]QB[0:1] REF TO DEVICE 1 and 2 tODCV tPD FB DEVICE1 tPDELTA Q t SKEW0,1 Other Q FB DEVICE2 t SKEW0,1 tODCV t SKEWBNK t PWL QFA1 or [1:4]Q[A:B]1 t SKEWPR QFA0 or [1:4]Q[A:B]0 tPDELTA Document Number: 38-07271 Rev. *C Page 8 of 11 [+] Feedback RoboClockII™ Junior, CY7B9930V, CY7B9940V Ordering Information Propagation Delay (ps) 500 500 500 500 250 250 250 250 Pb-free 500 500 500 500 500 500 250 250 250 250 100 100 200 200 200 200 200 200 200 200 CY7B9930V-5AXC CY7B9930V-5AXCT CY7B9940V-5AXC CY7B9940V-5AXCT CY7B9940V-5AXI CY7B9940V-5AXIT CY7B9940V-2AXC CY7B9940V-2AXCT CY7B9940V-2AXI CY7B9940V-2AXIT 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack–Tape and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack–Tape and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack–Tape and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack–Tape and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack–Tape and Reel Industrial Commercial Industrial Commercial Commercial Commercial Max. Speed (MHz) 100 100 200 200 100 200 100 200 Ordering Code CY7B9930V-5AC CY7B9930V-5AI CY7B9940V-5AI CY7B9940V-5AC [23] [23] [23] Package Type 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial CY7B9930V-2AC [23] CY7B9940V-2AC CY7B9930V-2AI [23] CY7B9940V-2AI [23] Note 23. It is a obsolete device. Document Number: 38-07271 Rev. *C Page 9 of 11 [+] Feedback RoboClockII™ Junior, CY7B9930V, CY7B9940V Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 RoboClockII is a trademark of Cypress Semiconductor. Document Number: 38-07271 Rev. *C Page 10 of 11 [+] Feedback RoboClockII™ Junior, CY7B9930V, CY7B9940V Document History Page Document Title: RoboClockII™ Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer Document Number: 38-07271 REV. ** *A *B ECN NO. 110536 115109 128463 Issue Date 12/02/01 7/03/02 7/29/03 Orig. of Change SZV HWT RGL Description of Change Change from Spec number: 38-01141 Add 44TQFP package for both CY7B9930/40V – Industrial Operating Range Added clock input frequency (fin) specifications in the switching characteristics table. Added Min. values for the clock output frequency (fout) in the switching characteristics table. *C 1346903 8/8/07 WWZ/VED/ Update the ordering info to reflect the current status and Pb-free part numbers. ARI Implemented new template. Updated the package diagram. © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. 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Document Number: 38-07271 Rev. *C Revised August 8, 2007 Page 11 of 11 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback