CY7C09199V-7AXC

CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features ■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.) True Dual-Ported memory cells which enable simultaneous access of the same memory location ■ 3.3V low operating power ■ Active= 115 mA (typical) ■ 6 Flow-Through and Pipelined devices ■ Standby= 10 μA (typical) ■ 32K x 8/9 organizations (CY7C09079V/179V) ■ Fully synchronous interface for easier operation ■ 64K x 8/9 organizations (CY7C09089V/189V) ■ Burst counters increment addresses internally ■ 128K x 8/9 organizations (CY7C09099V/199V) ■ Shorten cycle times ■ 3 Modes ■ Minimize bus noise ■ Flow-Through ■ Supported in Flow-Through and Pipelined modes ■ Pipelined ■ Burst Pipelined output mode on both ports enables fast 100 MHz operation 0.35-micron CMOS for optimum speed and power ■ Dual Chip Enables for easy depth expansion Automatic power down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pb-free packages available ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram R/WL R/WR OEL OER CE0L CE1L 1 0 0 0/1 1 0/1 FT/PipeL [3] A0–A14/15/16L CLKL ADSL CNTENL CNTRSTL 0/1 0 0 1 0/1 8/9 [2] I/O0L–I/O7/8L CE0R CE1R 1 FT/PipeR 8/9 I/O Control [2] I/O0R–I/O7/8R I/O Control 15/16/17 15/16/17 Counter/ Address Register Decode Counter/ Address Register Decode True Dual-Ported RAM Array [3] A0–A14/15/16R CLKR ADSR CNTENR CNTRSTR Notes 1. See page 6 for Load Conditions. 2. I/O0–I/O7 for x8 devices, I/O0–I/O8 for x9 devices. 3. A0–A14 for 32K, A0–A15 for 64K, and A0–A16 for 128K devices. Cypress Semiconductor Corporation Document #: 38-06043 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 10, 2008 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Functional Description A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW-to-HIGH transition of that port’s clock signal. This reads/writes one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and loops back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines enable minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode, data is available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to enable the shortest possible cycle times. Pin Configurations NC NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC Figure 1. 100-Pin TQFP (Top View) - CY7C09099V (128K x 8), CY7C09089V (64K x 8),CY7C09079V (32K x 8) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 [7] NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R [5] A15L 11 65 A15R [5] [6] A16L 12 64 A16R [6] VCC 13 63 GND NC 14 62 NC NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER [7] NC 24 52 GND NC 25 51 NC NC NC NC I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. This pin is NC for CY7C09079V. 6. This pin is NC for CY7C09079V and CY7C09089V. 7. For CY7C09079V and CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an IDT 5V x16 flow-through device. Document #: 38-06043 Rev. *C Page 2 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Pin Configurations (continued NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14R A14L 10 66 A15L 11 65 A15R [8] A16L 12 64 A16R [9] VCC 13 63 GND NC 14 62 NC NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR [8] [9] OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER NC 24 52 GND NC 25 51 NC NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND Document #: 38-06043 Rev. *C I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Selection Guide CY7C09079V/89V/99V CY7C09179V/89V/99V-6[1] CY7C09079V/89V/99V CY7C09179V/89V/99V-7[1] CY7C09079V/89V/99V CY7C09179V/89V/99V -9 CY7C09079V/89V/99V CY7C09179V/89V/99V -12 fMAX2 (MHz) (Pipelined) 100 83 67 50 Max. Access Time (ns) (Clock to Data, Pipelined) 6.5 7.5 9 12 Typical Operating Current ICC (mA) 175 155 135 115 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 25 25 20 20 Typical Standby Current for ISB3 (μA) (Both Ports CMOS Level) 10 μA 10 μA 10 μA 10 μA Description Pin Definitions Left Port Right Port Description A0L–A16L A0R–A16R Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices). ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Notes 8. This pin is NC for CY7C09179V. 9. This pin is NC for CY7C09179V and CY7C09189V Document #: 38-06043 Rev. *C Page 4 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Maximum Ratings Static Discharge Voltage............................................ >2001V Latch-Up Current ..................................................... >200 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[10] Operating Range Storage Temperature ................................. –65°C to +150°C Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 300 mV Industrial[11] –40°C to +85°C 3.3V ± 300 mV Ambient Temperature with Power Applied.. –55°C to +125°C Range Supply Voltage to Ground Potential................–0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ........................... –0.5V to VCC+0.5V DC Input Voltage ..................................... –0.5V to VCC+0.5V Output Current into Outputs (LOW) ............................. 20 mA Electrical Characteristics Over the Operating Range VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Output HIGH Voltage (VCC = Min. IOH = 2.4 –4.0 mA) Output LOW Voltage (VCC = Min. IOH = +4.0 mA) Input HIGH Voltage 2.0 Input LOW Voltage Output Leakage Current –10 Operating Current Commercial. 175 (VCC = Max. IOUT = 0 mA) Industrial[11] Outputs Disabled Standby Current (Both Commercial. 25 Ports TTL Level)[12] CEL Industrial[11] & CER ≥ VIH, f = fMAX Standby Current (One Commercial. 115 Port TTL Level)[12] CEL | Industrial[11] CER ≥ VIH, f = fMAX Commercial. 10 Standby Current (Both Ports CMOS Level)[12] Industrial[11] CEL & CER ≥ VCC – 0.2V, f=0 Standby Current (One Commercial 105 [11] Port CMOS Level)[12] Industrial CEL | CER ≥ VIH, f = fMAX 2.4 Unit Max Typ 2.4 0.4 2.0 Min Typ Max -12 2.4 0.4 0.8 10 320 Min Max Typ Min Max Typ -6[1] Description Min Parameter CY7C09079V/89V/99V CY7C09179V/89V/99V -7[1] -9 V 0.4 0.4 V 2.0 0.8 –10 10 –10 135 225 115 185 295 0.8 10 205 V V μA mA mA 2.0 155 275 0.8 10 275 390 95 25 85 85 120 20 35 65 75 20 50 mA mA 175 105 165 165 210 95 150 105 160 85 140 mA mA 250 10 10 250 250 10 10 250 250 10 250 μA μA 135 95 125 125 170 85 95 115 125 75 100 mA mA –10 Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max Unit 10 pF 10 pF Notes 10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 11. Industrial parts are available in CY7C09099V and CY7C09199V only. 12. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). Document #: 38-06043 Rev. *C Page 5 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Figure 3. AC Test Loads 3.3V 3.3V R1 = 590Ω OUTPUT C = 30 pF OUTPUT R2 = 435Ω RTH = 250Ω R1 = 590Ω OUTPUT C = 30 pF C = 5 pF R2 = 435Ω VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) Figure 4. AC Test Loads (Applicable to -6 and -7 only)[13] Z0 = 50Ω OUTPUT ALL INPUT PULSES R = 50Ω 3.0V C 10% GND 90% 10% 90% ≤ 3 ns ≤ 3 ns VTH = 1.4V (a) Load 1 (-6 and -7 only) Figure 5. Load Derating Curve 0. 60 Δ (ns) for all -7 access times 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) Note 13. Test Conditions: C = 10 pF. Document #: 38-06043 Rev. *C Page 6 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09179V/89V/99V Parameter Description -6[1] Min -7[1] Max Max Min -12 Max Unit fMAX1 fMax Flow-Through 53 45 40 33 MHz fMAX2 fMax Pipelined 100 83 67 50 MHz tCYC1 Clock Cycle Time - Flow-Through tCYC2 Clock Cycle Time - Pipelined tCH1 Clock HIGH Time - Flow-Through tCL1 Clock LOW Time - Flow-Through tCH2 Max Min 22 25 30 ns 10 12 15 20 ns 6.5 7.5 12 12 ns 6.5 7.5 12 12 ns Clock HIGH Time - Pipelined 4 5 6 8 ns tCL2 Clock LOW Time - Pipelined 4 tR Clock Rise Time 3 3 3 3 ns tF Clock Fall Time 3 3 3 3 ns tSA Address Set-Up Time tHA Address Hold Time tSC Chip Enable Set-Up Time tHC Chip Enable Hold Time tSW R/W Set-Up Time tHW R/W Hold Time tSD Input Data Set-Up Time tHD Input Data Hold Time tSAD ADS Set-Up Time tHAD ADS Hold Time tSCN CNTEN Set-Up Time tHCN CNTEN Hold Time tSRST CNTRST Set-Up Time tHRST CNTRST Hold Time tOE Output Enable to Data Valid tOLZ 19 Min -9 6 8 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4.5 5 5 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 8 [14, 15] OE to Low Z 2 [14, 15] OE to High Z 1 tOHZ 5 1 9 2 7 1 1 10 2 7 1 ns 12 2 7 1 ns ns 7 ns tCD1 Clock to Data Valid - Flow-Through 15 18 20 25 ns tCD2 Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns tDC Data Output Hold After Clock HIGH 2 [14, 15] Clock HIGH to Output High Z 2 tCKLZ[14, 15] Clock HIGH to Output Low Z 2 tCKHZ 2 9 2 2 9 2 2 2 9 2 2 ns 9 2 ns ns Port to Port Delays tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns tCCS Clock to Clock Set-Up Time 9 10 15 15 ns Notes 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06043 Rev. *C Page 7 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS An An+1 tCD1 DATAOUT An+2 tCKHZ tDC Qn tCKLZ An+3 Qn+1 Qn+2 tDC tOHZ tOLZ OE tOE Notes 16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 17. ADS = VIL, CNTEN and CNTRST = VIH. 18. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 19. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document #: 38-06043 Rev. *C Page 8 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS An An+1 1 Latency DATAOUT An+2 An+3 tDC tCD2 Qn Qn+1 Qn+2 tOHZ tCKLZ tOLZ OE tOE Figure 8. Bank Select Pipelined Read[20, 21] - tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tDC tSC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC CE0(B2) tSC tHC tCD2 DATAOUT(B2) tCD2 D4 D2 tCKLZ Document #: 38-06043 Rev. *C tCKHZ tCKLZ Page 9 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 9. Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR tCD1 tSW tSA ADDRESSR tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 21. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 22. The same waveforms apply for a right port write to flow-through left port read. 23. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 24. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 25. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document #: 38-06043 Rev. *C Page 10 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 tHA DATAIN tCD2 An+3 An+4 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Document #: 38-06043 Rev. *C An+2 tSD tHD Qn+3 NO OPERATION WRITE READ Page 11 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W ADDRESS tSW tHW tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 27. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 28. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *C Page 12 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 12. Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 27, 28] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 20, 26, 27, 28] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS tSA DATAIN An+1 tSD tHA An+3 An+4 An+5 tHD Dn+2 tDC tCD1 DATAOUT An+2 Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ Document #: 38-06043 Rev. *C WRITE READ Page 13 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 14. Pipelined Read with Address Counter Advance[29] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn tDC Qn+1 READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Figure 15. Flow-Through Read with Address Counter Advance[29] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn+3 Qn+2 COUNTER HOLD READ WITH COUNTER Note 29. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document #: 38-06043 Rev. *C Page 14 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[30, 31] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Notes 30. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 31. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document #: 38-06043 Rev. *C Page 15 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 17. Counter Reset (Pipelined Outputs)[19, 26, 32, 33] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 32. CE0 = VIL; CE1 = VIH. 33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06043 Rev. *C Page 16 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Table 1. Read/Write and Enable Operation[34, 35, 36] Inputs OE CLK CE0 Outputs CE1 R/W I/O0–I/O9 Operation [37] X H X X High-Z Deselected X X L X High-Z Deselected[37] X L H L DIN Write L L H H DOUT Read[37] L H X High-Z Outputs Disabled H X Table 2. Address Counter Control Operation[34, 38, 39, 40] Address Previous Address X CLK ADS CNTEN X X X An X L X An X An CNTRST I/O Mode Operation L Dout(0) Reset Counter Reset to Address 0 X H Dout(n) Load Address Load into Counter H H H Dout(n) Hold External Address Blocked—Counter Disabled H L H Dout(n+1) Increment Counter Enabled—Internal Address Generation Notes 34. “X” = “Don’t Care”, “H” = VIH, “L” = VIL. 35. ADS, CNTEN, CNTRST = “Don’t Care.” 36. OE is an asynchronous input signal. 37. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 38. CE0 and OE = VIL; CE1 and R/W = VIH. 39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 40. Counter operation is independent of CE0 and CE1. Document #: 38-06043 Rev. *C Page 17 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5[1] CY7C09079V-6AC 7.5[1] CY7C09079V-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09079V-7AI A100 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09079V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09079V-12AC A100 100-Pin Thin Quad Flat Pack Commercial A100 100-Pin Thin Quad Flat Pack Commercial 64K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1] Ordering Code Package Name Package Type Operating Range CY7C09089V-6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09089V-6AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 7.5[1] CY7C09089V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09089V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09089V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09089V-12AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C09089V-12AXI A100 100-Pin Pb-Free Thin Quad Flat Pack Industrial 128K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1] 7.5[1] 9 12 Ordering Code Package Name Package Type Operating Range CY7C09099V-6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099V-6AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C09099V-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099V-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09099V-7AXI A100 100-Pin Pb-Free Thin Quad Flat Pack Industrial CY7C09099V-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099V-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09099V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099V-12AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 32K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) [1] 6.5 7.5[1] Ordering Code Package Name Package Type Operating Range CY7C09179V-6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09179V-6AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C09179V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09179V-9C A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09179V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09179V-12AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial Document #: 38-06043 Rev. *C Page 18 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V 64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1] 7.5[1] Ordering Code Package Name CY7C09189V-6AC A100 CY7C09189V-6AXC CY7C09189V-7AC Package Type Operating Range 100-Pin Thin Quad Flat Pack Commercial A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09189V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09189V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189V-12AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 128K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1] Ordering Code Package Name Package Type Operating Range CY7C09199V-6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199V-6AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 7.5[1] CY7C09199V-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199V-7AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 9 CY7C09199V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09199V-9AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C09199V-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09199V-9AXI A100 100-Pin Pb-Free Thin Quad Flat Pack Industrial CY7C09199V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199V-12AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial Document #: 38-06043 Rev. *C Page 19 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048) 51-85048-*B Document #: 38-06043 Rev. *C Page 20 of 21 [+] Feedback CY7C09079V/89V/99V CY7C09179V/89V/99V Document History Page Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static RAM Document Number: 38-06043 Orig. of Change Description of Change SZV 09/29/01 Change from Spec number: 38-00667 to 38-06043 RBI 12/27/02 Power up requirements added to Operating Conditions Information 365034 PCN See ECN Added Pb-Free Logo Added Pb-Free Part Ordering Information: CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC, CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC, CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC, CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC, CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC 2623658 VKN/PYRS 12/17/08 Added CY7C09089V-12AXI part in the Ordering information table Rev. ECN No. ** 110191 *A 122293 *B *C Orig. of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06043 Rev. *C Revised December 10, 2008 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21 [+] Feedback