CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
■
Functional Description
Temperature ranges
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
■
Pin and function compatible with CY7C1021BV33
■
High speed
❐ tAA = 8 ns (Commercial)
❐ tAA = 10 ns (Industrial and Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■
CMOS for optimum speed and power
■
Low active power: 325 mW (max)
■
Automatic power down when deselected
■
Independent control of upper and lower bits
■
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II, and 48-Ball FBGA packages
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O1 through I/O8), is written into
the location specified on the address pins (A0 through A15). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9
through I/O16) is written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O9 to I/O16. For more information, see the
“Truth Table” on page 10 for a complete description of Read and
Write modes.
The input and output pins (I/O1 through I/O16) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
64K x 16
RAM Array
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 23, 2010
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CY7C1021CV33
Contents
Features ............................................................................
Functional Description.....................................................
Logic Block Diagram........................................................
Contents ............................................................................
Selection Guide ................................................................
Pin Configuration .............................................................
Pin Definitions ..................................................................
Maximum Ratings.............................................................
Operating Range...............................................................
Electrical Characteristics.................................................
Capacitance ......................................................................
Thermal Resistance..........................................................
Document Number: 38-05132 Rev. *K
1
1
1
2
3
3
4
5
5
5
6
6
Switching Characteristics ............................................... 7
Switching Waveforms ...................................................... 8
Truth Table...................................................................... 10
Ordering Information ..................................................... 11
Package Diagrams ......................................................... 12
Document History Page................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY7C1021CV33
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Commercial
-8
-10
-12
-15
Unit
8
10
12
15
ns
80
90
85
Industrial
95
90
85
Automotive-A
90
Automotive-E
Maximum CMOS Standby Current
80
mA
5
mA
90
Commercial
5
5
5
Industrial
5
5
5
Automotive-A
mA
mA
mA
mA
5
5
Automotive-E
mA
10
mA
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II [1]
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
Figure 2. 48-Ball FBGA Pinout [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O2
I/O1
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12
NC
NC
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Note
1. NC pins are not connected on the die.
Document Number: 38-05132 Rev. *K
Page 3 of 16
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CY7C1021CV33
Pin Definitions
Pin Name
A0–A15
I/O1–I/O16 [2]
SOJ, TSOP
Pin Number
BGA Pin
Number
I/O Type
Input
1–5, 18–21, A3, A4, A5, B3,
24–27, 42–44 B4, C3, C4,
D4, H2, H3,
H4, H5, G3,
G4, F3, F4
Description
Address Inputs. Used to select one of the address locations.
7–10, 13–16,
B6, C6, C5, Input or Output Bidirectional Data I/O lines. Used as input or output lines
depending on operation.
29–32, 35–38 D5, E5, F5, F6,
G6, B1, C1,
C2, D2, E2,
F2, F1, G1
NC
22, 23, 28
A6, D3, E3,
E4, G2, H1, H6
No Connect
No Connects. Not connected to the die.
WE
17
G5
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE
6
B5
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
40, 39
B2, A1
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls I/O16 – I/O9,
BLE controls I/O8 – I/O1.
OE
41
A2
Input or
Control
Output Enable, Active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, the I/O pins are tristated and act as input data
pins.
VSS
12, 34
D1, E6
Ground
Ground for the Device. Connected to ground of the system.
VCC
11, 33
D6, E1
Power Supply Power Supply Inputs to the Device.
Note
2. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages.
Document Number: 38-05132 Rev. *K
Page 4 of 16
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CY7C1021CV33
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch Up Current ..................................................... >200 mA
Storage Temperature ................................. –65C to +150C
Operating Range
Ambient Temperature with
Power Applied ............................................ –55C to +125C
Range
Supply Voltage on VCC Relative to GND[3] .....–0.5V to +4.6V
Commercial
DC Voltage Applied to Outputs
in High Z State[3] ...................................... –0.5V to VCC+0.5V
Industrial
DC Input Voltage[3] .................................. –0.5V to VCC+0.5V
Ambient
Temperature (TA)
VCC
0C to +70C
3.3V 10%
–40C to +85C
Automotive-A
–40C to +85C
Automotive -E
–40C to +125C
Current into Outputs (LOW)......................................... 20 mA
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
-8
Min
-10
Max
Min
-12
Max
Min
-15
Max
VOH
Output HIGH Voltage VCC = Min,
I/OH = –4.0 mA
VOL
Output LOW Voltage VCC = Min,
I/OL = 8.0 mA
VIH
Input HIGH
Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
VIL
Input LOW Voltage[3]
–0.3
0.8
–0.3
0.8
–0.3
IIX
Input Leakage
Current
–1
+1
GND < VI < VCC
2.4
2.4
0.4
Commercial
2.4
0.4
Output Leakage
Current
GND < VI < VCC,
Output disabled
VCC Operating
Supply Current
VCC = Max,
I/OUT = 0 mA,
f = fMAX = 1/tRC
Automatic CE Power Max VCC,
Down Current —TTL CE > VIH
Inputs
VIN > VIH or
VIN < VIL, f = fMAX
V
0.8
–0.3
0.8
V
–1
+1
A
–1
+1
–1
+1
–1
+1
–1
+1
–1
+1
Automotive-A
–1
+1
+1
+12
–1
+1
–1
+1
Industrial
–1
+1
–1
+1
Automotive-A
–1
+1
–12
+12
Commercial
95
90
85
Industrial
90
85
Automotive-A
90
Commercial
mA
80
15
15
Industrial
15
15
Automotive-A
15
Automatic CE Power Max VCC,
Commercial
Down Current —
CE > VCC – 0.3V, Industrial
CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0 Automotive-A
Automotive-E
80
A
90
15
Automotive-E
ISB2
VCC
+ 0.3
+1
Automotive-E
ISB1
2.0
+1
–1
V
V
–1
Commercial
Unit
0.4
–1
Automotive-E
ICC
0.4
–12
Max
2.4
Industrial
Automotive-E
I/OZ
Min
15
mA
15
20
5
5
5
5
5
5
5
mA
5
10
Note
3. VIL (min) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
Document Number: 38-05132 Rev. *K
Page 5 of 16
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CY7C1021CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25C, f = 1 MHz, VCC = 3.3V
Max
Unit
8
pF
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
SOJ
TSOP II
FBGA
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
65.06
76.92
95.32
C/W
34.21
15.86
10.68
C/W
Figure 3. AC Test Loads and Waveforms [4]
8-ns devices:
10-, 12-, 15-ns devices:
Z = 50
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317
3.3V
OUTPUT
30 pF*
OUTPUT
R2
351
30 pF*
1.5V
(b)
(a)
High-Z characteristics:
3.0V
GND
90%
90%
10%
10%
Rise Time: 1 V/ns
(c)
R 317
3.3V
ALL INPUT PULSES
Fall Time: 1 V/ns
OUTPUT
R2
351
5 pF
(d)
Note
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown
in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document Number: 38-05132 Rev. *K
Page 6 of 16
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CY7C1021CV33
Switching Characteristics
Over the Operating Range [5]
Parameter
Description
-8
Min
-10
Max
Min
-12
Max
Min
-15
Max
Min
Max
Unit
Read Cycle
tpower[6]
VCC(Typical) to the First Access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
8
10
tDOE
OE LOW to Data Valid
5
5
[7]
OE LOW to Low Z
tLZOE
100
100
100
100
s
8
10
12
15
ns
8
3
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low Z[7]
3
0
Z[7, 8]
10
4
Z[7, 8]
ns
12
15
ns
6
7
ns
3
0
5
3
4
15
3
0
3
12
0
6
3
ns
7
ns
3
CE HIGH to High
tPU[9]
tPD[9]
CE LOW to Power Up
CE HIGH to Power Down
8
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
5
6
7
ns
tLZBE
Byte Enable to Low Z
0
Byte Disable to High Z
tHZBE
0
0
0
4
6
ns
tHZCE
0
5
ns
ns
0
0
5
7
ns
0
6
ns
7
ns
[10]
Write Cycle
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
8
9
10
ns
tAW
Address Setup to Write End
7
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Setup to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
ns
tSD
Data Setup to Write End
5
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
3
ns
Z[7, 8]
tHZWE
WE LOW to High
tBW
Byte Enable to End of Write
4
6
5
7
6
8
7
9
ns
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms [4]” on page 6. Transition is measured
500 mV from steady state voltage.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE is LOW to initiate a write. The
transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
Document Number: 38-05132 Rev. *K
Page 7 of 16
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CY7C1021CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[11, 12]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVI/OUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05132 Rev. *K
Page 8 of 16
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CY7C1021CV33
Switching Waveforms
(continued)
Figure 6. Write Cycle No. 1 (CE Controlled)[14, 15]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
14. Data I/O is high impedance if OE, BHE, and/or BLE= VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05132 Rev. *K
Page 9 of 16
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CY7C1021CV33
Switching Waveforms
(continued)
Figure 8. Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
H
L
L
BLE
BHE
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
H
L
L
Data Out
Data Out
Read – All Bits
Active (ICC)
L
H
Data Out
High Z
Read – Lower Bits Only
Active (ICC)
H
L
High Z
Data Out
Read – Upper Bits Only
Active (ICC)
L
L
Data In
Data In
Write – All Bits
Active (ICC)
L
H
Data In
High Z
Write – Lower Bits Only
Active (ICC)
H
L
High Z
Data In
Write – Upper Bits Only
Active (ICC)
X
L
I/O1 – I/O8
I/O9 –
I/O16
WE
Mode
Power
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 38-05132 Rev. *K
Page 10 of 16
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CY7C1021CV33
Ordering Information
Speed
(ns)
10
12
15
Package Type
Operating
Range
CY7C1021CV33-10VXC
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
Commercial
CY7C1021CV33-10ZXC
51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021CV33-10BAXI
51-85096 48-ball FBGA (Pb-free)
Ordering Code
Package
Diagram
CY7C1021CV33-10ZXI
51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021CV33-10ZSXA
51-85087 44-pin TSOP Type II (Pb-free)
Industrial
CY7C1021CV33-12ZXC
51-85087 44-pin TSOP Type II (Pb-free)
Automotive-A
Commercial
CY7C1021CV33-12VXE
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
Automotive-E
CY7C1021CV33-12ZSXE
51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021CV33-12BAE
51-85096 48-ball FBGA
CY7C1021CV33-15ZSXA
51-85087 44-pin TSOP Type II (Pb-free)
Automotive-A
The 44 pin TSOP II package containing the Automotive grade device is designated as “ZS”, while the same package containing the Commercial/Industrial grade device
is “Z”.
Document Number: 38-05132 Rev. *K
Page 11 of 16
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CY7C1021CV33
Package Diagrams
Figure 9. 44-Pin (400 Mil) Molded SOJ
44
23
DIMENSIONS IN INCHES MIN.
0.395
0.405
0.435
0.445
22
1
SEATING PLANE
1.120
1.130
0.095
0.115
0.045
MAX.
MAX.
0.128
0.148
0.013
0.023
0.023
0.033
0.050
TYP.
0.082
MIN.
0.004
0.025
MIN.
0°-10°
0.007
0.013
0.365
0.375
51-85082 *C
Document Number: 38-05132 Rev. *K
Page 12 of 16
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CY7C1021CV33
Package Diagrams
(continued)
Figure 10. 44-Pin Thin Small Outline Package Type II
51-85087 *C
Document Number: 38-05132 Rev. *K
Page 13 of 16
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CY7C1021CV33
Package Diagrams
(continued)
Figure 11. 48-Ball FBGA (7 x 7 x 1.2 mm)
TOP VIEW
PIN 1 CORNER
(LASER MARK)
1 2
3
4
5
6
BOTTOM VIEW
A
PIN 1 CORNER
B
Ø0.05 M C
7.00±0.10
C
Ø0.25 M C A B
D
Ø0.30±0.05(48X)
E
6
5
4
3
F
1
A
G
B
7.00±0.10
0.75
C
D
E
2.625
A
5.25
7.00±0.10
H
B
2
F
G
A
1.875
0.75
0.10 C
0.21±0.05
SIDE VIEW
0.56±0.05
0.25 C
H
3.75
B
0.34
SEATING PLANE
C
Document Number: 38-05132 Rev. *K
7.00±0.10
0.15(4X)
1.20 MAX.
51-85096 *H
Page 14 of 16
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CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05132
REV.
ECN NO. Submission
Date
Orig. of
Change
Description of Change
**
109472
12/06/01
HGK
New data sheet
*A
115044
05/08/02
HGK
Ram7 version C4K x 16 Async
Removed “Preliminary”
*B
115808
06/25/02
HGK
ISB1 and ICC values changed
*C
120413
10/31/02
DFP
Updated BGA pin E4 to NC
*D
238454
See ECN
RKF
1) Added Automotive Specifications to datasheet
2) Added Pb-free devices in the Ordering Information
*E
334398
See ECN
SYT
Added Pb-free on page 9 and 10
*F
493565
See ECN
NXR
Added Automotive-A operating range
Corrected typo in the Pin Definition table
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed I/OS parameter from DC Electrical Characteristics table
Updated the ordering information table
*G
563963
See ECN
VKN
Added tPOWER specification in the AC Switching Characteristics table
Added footnote 8
*H
1390863
See ECN
VKN/AESA Corrected TSOP II package outline
*I
1891366
See ECN
VKN/AESA Added -10ZSXA part in the Ordering Information table
Updated Ordering Information Table
*J
2880096
02/17/2010
*K
2897691
03/23/2010
VKN/AESA Added “CY7C1021CV33-10ZXI” part in the Ordering Information table
Updated package diagrams.
Document Number: 38-05132 Rev. *K
RAME
Updated Ordering Information
Updated Package Diagrams
Page 15 of 16
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CY7C1021CV33
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© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05132 Rev. *K
Revised March 23, 2010
Page 16 of 16
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