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CY7C1021CV33 Automotive
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Automotive-A: –40 °C to 85 °C
❐ Automotive-E: –40 °C to 125 °C
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
■
Pin and function compatible with CY7C1021CV33
■
High speed
❐ tAA = 10 ns (Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■
CMOS for optimum speed and power
■
Low active power: 325 mW (max)
■
Automatic power down when deselected
■
Independent control of upper and lower bits
■
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II, and 48-ball FBGA packages
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O1 through I/O8) [1], is written into
the location specified on the address pins (A0 through A15). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9
through I/O16) [1] is written into the location specified on the
address pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O1 to I/O8 [1]. If Byte High Enable (BHE) is LOW, then data
from memory appears on I/O9 to I/O16 [1]. For more information,
see the Truth Table on page 11 for a complete description of
Read and Write modes.
The input and output pins (I/O1 through I/O16) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For a complete list of related documentation, click here.
Logic Block Diagram
64K x 16
RAM Array
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7[1]
I/O8–I/O15[1]
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Note
1. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages.
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 2, 2014
CY7C1021CV33 Automotive
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 38-05132 Rev. *Q
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Page 2 of 19
CY7C1021CV33 Automotive
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
-12
Unit
10
12
ns
90
–
mA
Automotive-E
–
90
mA
Automotive-A
5
–
mA
Automotive-E
–
10
mA
Automotive-A
Maximum CMOS Standby Current
-10
Pin Configuration
Figure 1. 44-pin SOJ/TSOP II pinout [2]
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
Figure 2. 48-ball FBGA pinout [2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O2
I/O1
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
NC
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Note
2. NC pins are not connected on the die.
Document Number: 38-05132 Rev. *Q
Page 3 of 19
CY7C1021CV33 Automotive
Pin Definitions
Pin Name
SOJ, TSOP
Pin Number
BGA Pin
Number
I/O Type
A0–A15
1–5, 18–21,
24–27, 42–44
A3, A4, A5,
B3, B4, C3,
C4, D4, H2,
H3, H4, H5,
G3, G4, F3,
F4
Input
I/O1–I/O16 [3] 7–10, 13–16,
29–32, 35–38
B6, C6, C5,
D5, E5, F5,
F6, G6, B1,
C1, C2, D2,
E2, F2, F1,
G1
Input or
Output
Description
Address Inputs. Used to select one of the address locations.
Bidirectional Data I/O lines. Used as input or output lines depending
on operation.
NC
22, 23, 28
A6, D3, E3,
E4, G2, H1,
H6
No Connect No Connects. Not connected to the die.
WE
17
G5
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE
6
B5
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip. When
HIGH, deselects the chip.
BHE, BLE
40, 39
B2, A1
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls I/O16–I/O9 [3],
BLE controls I/O8–I/O1 [3].
OE
41
A2
Input or
Control
Output Enable, Active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, the I/O pins are tristated and act as input data pins.
VSS
12, 34
D1, E6
Ground
Ground for the Device. Connected to ground of the system.
VCC
11, 33
D6, E1
Power Supply Power Supply Inputs to the Device.
Note
3. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages.
Document Number: 38-05132 Rev. *Q
Page 4 of 19
CY7C1021CV33 Automotive
DC Input Voltage [4] ............................ –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC Relative to GND [4] ...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [4] ................................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Ambient Temperature (TA)
VCC
Automotive-A
–40 C to +85 C
3.3 V 10%
Automotive-E
–40 C to +125 C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
-10
Min
-12
Max
Unit
Max
Min
2.4
–
2.4
–
V
–
0.4
–
0.4
V
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[4]
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current
Automotive-A
–1
+1
–
–
A
Automotive-E
–
–
–12
+12
Output Leakage Current GND < VI < VCC,
Output disabled
Automotive-A
–1
+1
–
–
Automotive-E
–
–
–12
+12
VCC Operating Supply
Current
VCC = Max,
IOUT = 0 mA,
f = fMAX = 1/tRC
Automotive-A
–
90
–
–
Automotive-E
–
–
–
90
Automatic CE Power
Down Current —TTL
Inputs
Max VCC,
Automotive-A
CE > VIH
Automotive-E
VIN > VIH or
VIN < VIL, f = fMAX
–
15
–
–
–
–
–
20
Automatic CE Power
Max VCC,
Automotive-A
Down Current — CMOS CE > VCC – 0.3 V, Automotive-E
VIN > VCC – 0.3 V,
Inputs
or VIN < 0.3 V, f = 0
–
5
–
–
–
–
–
10
I/OZ
ICC
ISB1
ISB2
GND < VI < VCC
A
mA
mA
mA
Note
4. VIL (min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns.
Document Number: 38-05132 Rev. *Q
Page 5 of 19
CY7C1021CV33 Automotive
Capacitance
Parameter [5]
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
CIN
Input capacitance
COUT
Output capacitance
Max
Unit
8
pF
8
pF
Thermal Resistance
Parameter [5]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin SOJ
44-pin TSOP II 48-ball FBGA
Unit
Test conditions follow standard test
methods and procedures for
measuring thermal impedance,
per EIA/JESD51
65.06
76.92
95.32
C/W
34.21
15.86
10.68
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [6]
8-ns devices:
10-, 12-, 15-ns devices:
Z = 50
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317
3.3 V
OUTPUT
30 pF*
OUTPUT
R2
351
30 pF*
1.5 V
(b)
(a)
High Z characteristics:
3.0 V
GND
90%
90%
10%
10%
Rise Time: 1 V/ns
(c)
R 317
3.3 V
ALL INPUT PULSES
Fall Time: 1 V/ns
OUTPUT
R2
351
5 pF
(d)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High Z) for all 8-ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load
shown in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d).
Document Number: 38-05132 Rev. *Q
Page 6 of 19
CY7C1021CV33 Automotive
Switching Characteristics
Over the Operating Range
Parameter [7]
Description
-10
-12
Unit
Min
Max
Min
Max
–
100
–
s
Read Cycle
tpower[8]
VCC(Typical) to the First Access
100
tRC
Read Cycle Time
10
–
12
–
ns
tAA
Address to Data Valid
–
10
–
12
ns
tOHA
Data Hold from Address Change
3
–
3
–
ns
tACE
CE LOW to Data Valid
–
10
–
12
ns
tDOE
OE LOW to Data Valid
–
5
–
6
ns
tLZOE
OE LOW to Low Z [9]
0
–
0
–
ns
–
5
–
6
ns
3
–
3
–
ns
[9, 10]
tHZOE
OE HIGH to High Z
tLZCE
CE LOW to Low Z [9]
[9, 10]
tHZCE
CE HIGH to High Z
tPU[11]
CE LOW to Power Up
tPD[11]
tDBE
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Write Cycle
–
5
–
6
ns
0
–
0
–
ns
CE HIGH to Power Down
–
10
–
12
ns
Byte Enable to Data Valid
–
5
–
6
ns
0
–
0
–
ns
–
5
–
6
ns
[12, 13]
tWC
Write Cycle Time
10
–
12
–
ns
tSCE
CE LOW to Write End
8
–
9
–
ns
tAW
Address Setup to Write End
8
–
9
–
ns
tHA
Address Hold from Write End
0
–
0
–
ns
tSA
Address Setup to Write Start
0
–
0
–
ns
tPWE
WE Pulse Width
7
–
8
–
ns
tSD
Data Setup to Write End
5
–
6
–
ns
tHD
Data Hold from Write End
0
–
0
–
ns
tLZWE
WE HIGH to Low Z [9]
3
–
3
–
ns
–
5
–
6
ns
7
–
8
–
ns
[9, 10]
tHZWE
WE LOW to High Z
tBW
Byte Enable to End of Write
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
8. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 6. Transition is measured 500 mV from steady state
voltage.
11. This parameter is guaranteed by design and is not tested.
12. The internal write time of the memory is defined by the overlap of WE, CE, and BHE/BLE LOW. All Signals must be ACTIVE to initiate a write and any of these signals
can terminate a write by going INACTIVE.The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
13. The minimum write cycle pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05132 Rev. *Q
Page 7 of 19
CY7C1021CV33 Automotive
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVI/OUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
14. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05132 Rev. *Q
Page 8 of 19
CY7C1021CV33 Automotive
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [17, 18]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
t BW
BHE, BLE
tSD
tHD
VALID DATA
DATA I/O
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
DATA I/O
tHD
VALID DATA
Notes
17. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05132 Rev. *Q
Page 9 of 19
CY7C1021CV33 Automotive
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
VALID DATA
DATA I/O
tLZWE
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [19]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
NOTE 19
tHZWE
tHD
DATAIN VALID
tLZWE
Notes
19. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 38-05132 Rev. *Q
Page 10 of 19
CY7C1021CV33 Automotive
Truth Table
CE
OE
H
L
L
I/O1–I/O8 [20]
I/O9–I/O16 [20]
WE
BLE
BHE
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
H
L
L
Data Out
Data Out
Read – All Bits
Active (ICC)
L
H
Data Out
High Z
Read – Lower Bits Only
Active (ICC)
H
L
High Z
Data Out
Read – Upper Bits Only
Active (ICC)
L
L
Data In
Data In
Write – All Bits
Active (ICC)
L
H
Data In
High Z
Write – Lower Bits Only
Active (ICC)
Active (ICC)
X
L
Mode
Power
H
L
High Z
Data In
Write – Upper Bits Only
L
H
H
X
X
High Z
High Z
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled Active (ICC)
Selected, Outputs Disabled Active (ICC)
Note
20. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages.
Document Number: 38-05132 Rev. *Q
Page 11 of 19
CY7C1021CV33 Automotive
Ordering Information
Speed
(ns)
10
12
Ordering Code
Package
Diagram
Package Type
CY7C1021CV33-10ZSXA
51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021CV33-12VXE
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1021CV33-12ZSXE
51-85087 44-pin TSOP Type II (Pb-free)
Operating
Range
Automotive-A
Automotive-E
Ordering Code Definitions
CY 7 C 1 02 1
C V33 - XX XX
X X
Temperature Range: X = A or E
A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = ZS or V or BA
ZS = 44-pin TSOP Type II
V = 44-pin Molded SOJ
BA = 48-ball FBGA
Speed: XX = 10 ns or 12 ns
Voltage range: V33 = 3 V to 3.6 V
Process Technology: C = 0.16 µm
Data width: 1 = × 16-bits
Density: 02 = 1-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05132 Rev. *Q
Page 12 of 19
CY7C1021CV33 Automotive
Package Diagrams
Figure 10. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082
51-85082 *E
Document Number: 38-05132 Rev. *Q
Page 13 of 19
CY7C1021CV33 Automotive
Package Diagrams (continued)
Figure 11. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05132 Rev. *Q
Page 14 of 19
CY7C1021CV33 Automotive
Package Diagrams (continued)
Figure 12. 48-ball FBGA (7 × 7 × 1.2 mm) BA48 Package Outline, 51-85096
51-85096 *J
Document Number: 38-05132 Rev. *Q
Page 15 of 19
CY7C1021CV33 Automotive
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
ball grid array
CE
chip enable
°C
degree Celsius
CMOS
complementary metal oxide semiconductor
µA
microampere
FBGA
fine-pitch ball grid array
µs
microsecond
I/O
input/output
mA
milliampere
OE
output enable
mm
millimeter
SOJ
small outline J-lead
mW
milliwatt
SRAM
static random access memory
MHz
megahertz
TQFP
thin quad flat pack
ns
nanosecond
TSOP
thin small-outline package
%
percent
TTL
transistor-transistor logic
pF
picofarad
WE
write enable
V
volt
W
watt
Document Number: 38-05132 Rev. *Q
Symbol
Unit of Measure
Page 16 of 19
CY7C1021CV33 Automotive
Document History Page
Document Title: CY7C1021CV33 Automotive, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05132
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
109472
12/06/01
HGK
New data sheet
*A
115044
05/08/02
HGK
Ram7 version C4K x 16 Async
Removed “Preliminary”
Description of Change
*B
115808
06/25/02
HGK
ISB1 and ICC values changed
*C
120413
10/31/02
DFP
Updated BGA pin E4 to NC
*D
238454
See ECN
RKF
Added Automotive Specifications to datasheet
Added Pb-free devices in the Ordering Information
*E
334398
See ECN
SYT
Added Pb-free on page 9 and 10
*F
493565
See ECN
NXR
Added Automotive-A operating range
Corrected typo in the Pin Definition table
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the ordering information table
*G
563963
See ECN
VKN
Added tPOWER specification in the AC Switching Characteristics table
Added footnote 8
*H
1390863
See ECN
VKN /
AESA
Corrected TSOP II package outline
*I
1891366
See ECN
VKN /
AESA
Added -10ZSXA part in the Ordering Information table
Updated Ordering Information Table
*J
2880096
02/17/2010
VKN /
AESA
Added “CY7C1021CV33-10ZXI” part in the Ordering Information table
Updated package diagrams.
*K
2897691
03/23/2010
RAME
Updated Ordering Information
Updated Package Diagrams
*L
3089939
11/18/2010
PRAS
Removed inactive parts from Ordering Information.
*M
3127893
01/04/2011
HMLA
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
*N
3272897
06/07/2011
HMLA
Updated Features (Removed the information associated with speed bins -8
and also the information associated with Commercial and Industrial parts.)
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Selection Guide (Removed the information associated with
Commercial and Industrial parts.)
Updated Operating Range (Removed the information associated with
Commercial and Industrial parts.)
Updated Electrical Characteristics (Removed the information associated with
Commercial and Industrial parts.)
Updated Package Diagrams.
*O
3400821
10/10/2011
HMLA
Updated Operating Range (Straddled both rows under VCC column so that the
same condition is applicable for both Automotive-A and Automotive-E ranges).
Updated Ordering Information (Removed the Note “The 44-pin TSOP II
package containing the Automotive grade device is designated as “ZS”, while
the same package containing the Commercial/Industrial grade device is “Z”.”
below the Ordering Information table since Commercial/Industrial grade
devices are not offered in this data sheet).
Updated Package Diagrams.
Document Number: 38-05132 Rev. *Q
Page 17 of 19
CY7C1021CV33 Automotive
Document History Page (continued)
Document Title: CY7C1021CV33 Automotive, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05132
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*P
3897056
02/13/2013
MEMJ
Updated Document Title to read as “CY7C1021CV33 Automotive, 1-Mbit (64
K × 16) Static RAM”.
Updated Functional Description:
Added Note 1 and referred the same note in I/O0–I/O7 and I/O8–I/O15.
Updated Logic Block Diagram:
Added Note 1 and referred the same note in I/O0–I/O7 and I/O8–I/O15.
Updated Pin Definitions:
Referred Note 3 in description of BHE, BLE pin.
Updated Switching Characteristics:
Updated Note 12 only.
Updated Switching Waveforms:
Updated Figure 6, Figure 7, Figure 8.
Updated Truth Table:
Added Note 20 and referred the same note in I/O1–I/O8 and I/O9–I/O16
columns.
Updated Package Diagrams:
spec 51-85082 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *D to *E.
*Q
4585000
11/24/2014
MEMJ
Added related documentation hyperlink in page 1.
Updated Figure 12 in Package Diagrams (spec 51-85096 *I to *J).
Added Note 13 in Switching Characteristics.
Added note reference 13 in the Switching Characteristics table.
Added Note 19 in Switching Waveforms.
Added note reference 19 in Figure 9.
Document Number: 38-05132 Rev. *Q
Page 18 of 19
CY7C1021CV33 Automotive
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05132 Rev. *Q
Revised December 2, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 19 of 19
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