CY7C1022

022CY7C10 PRELIMINARY CY7C1022 32K x 16 Static RAM Features • 5.0V operation (± 10%) • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected • Independent Control of Upper and Lower bytes • Available in 400-mil SOJ enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable (CE) HIGH and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE HIGH, and WE LOW). The CY7C1022 is available in standard 400-mil-wide SOJ packages. Functional Description The CY7C1022 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking chip enable (CE) input HIGH and write enable (WE) input LOW. If byte low Logic Block Diagram DATA IN DRIVERS Pin Configuration SOJ Top View NC A 14 A 13 A 12 A11 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A6 A5 A4 A3 A2 A1 A0 32K x 16 RAM Array I/O1 – I/O8 I/O9 – I/O16 COLUMN DECODER BHE WE CE OE BLE A0 A1 A2 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A3 A4 A5 A6 NC ROW DECODER A7 A8 A9 A10 A11 A12 A13 A14 SENSE AMPS 1022-2 2CY7C1022 Selection Guide 7C1022-12 Maximum Access Time (ns) Maximum Operating Current (mA) L Maximum CMOS Standby Current (mA) L Shaded areas contain advance information. 7C1022-15 15 160 130 3 0.1 12 170 140 3 0.1 Cypress Semiconductor Corporation Document #: 38-05090 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 18, 2001 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65×C to +150×C Ambient Temperature with Power Applied............................................ –55×C to +125×C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V CY7C1022 DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 4.5V–5.5V Electrical Characteristics Over the Operating Range 7C1022-12 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs [1] 7C1022-15 Min. 2.4 Max. 0.4 2.2 –0.5 –1 –2 6.0 0.8 +1 +2 160 130 20 10 3 0.1 mA mA mA Unit V V V V µA µA mA Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 Max. 0.4 2.2 –0.5 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 L –1 –2 6.0 0.8 +1 +2 170 140 20 ISB1 L 10 3 ISB2 L 0.1 Shaded area contains advance information. Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THÉVENIN EQUIVALENT R2 255Ω R 481 Ω R 481 Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 167Ω 30 pF R2 255Ω GND