CY7C1049CV33-15ZSXE

CY7C1049CV33 4 Mbit (512K x 8) Static RAM Features ■ Functional Description The CY7C1049CV33 is a high performance CMOS Static RAM organized as 524,288 words by eight bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049CV33 is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Temperature ranges ❐ Commercial: 0°C to 70°C ❐ Industrial/Automotive -A: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C High Speed ❐ tAA = 10 ns Low Active Power ❐ 324 mW (max) 2.0V Data Retention Automatic Power Down when Deselected TTL-compatible Inputs and Outputs Easy Memory Expansion with CE and OE features ■ ■ ■ ■ ■ ■ Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE INPUT BUFFER ROW DECODER IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6 512K x 8 ARRAY COLUMN DECODER POWER DOWN IO7 A13 A14 A15 A16 A17 A18 Cypress Semiconductor Corporation Document #: 38-05006 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600 Revised January 07, 2010 [+] Feedback CY7C1049CV33 Contents Features ............................................................................ Functional Description..................................................... Logic Block Diagram........................................................ Contents ............................................................................ Pin Configuration ............................................................. Selection Guide ................................................................ Pin Definitions .................................................................. Maximum Ratings............................................................. Operating Range............................................................... Electrical Characteristics................................................. Capacitance ...................................................................... Thermal Resistance.......................................................... 1 1 1 2 3 3 4 5 5 5 5 5 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table........................................................................ 9 Ordering Information ....................................................... 9 Package Diagrams ......................................................... 10 Document History Page................................................. 11 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 Document #: 38-05006 Rev. *G Page 2 of 12 [+] Feedback CY7C1049CV33 Pin Configuration Figure 1. 36-Pin SOJ (Top View) Figure 2. 44-Pin TSOP II (Top View) A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC Selection Guide Description Maximum Access Time Maximum Operating Current Commercial Industrial/Automotive-A Automotive-E Maximum CMOS Standby Current Commercial/Industrial/ Automotive-A Automotive-E -10 10 90 100 10 -12 12 85 95 10 -15 15 95 15 Unit ns mA mA mA mA mA Document #: 38-05006 Rev. *G Page 3 of 12 [+] Feedback CY7C1049CV33 Pin Definitions Pin Name A0–A18 I/O0–I/O7 NC[1] WE CE OE 36-SOJ Pin Number 44 TSOP-II Pin Number I/O Type Input Description Address inputs used to select one of the address locations. 1–5,14–18, 3–7,16–20, 20–24,32–35 26–30,38–41 7,8,11,12,25, 26,29,30 19,36 13 6 31 9,10,13,14, 31,32,35,36 1,2,21,22,23,2 4,25,42,43, 44 15 8 37 Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation No Connect No connects. This pin is not connected to the die Input/Control Write Enable input, active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Input/Control Chip Enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power supply inputs to the device. VSS, GND VCC 10,28 9,27 12,34 11,33 Note 1. NC pins are not connected on the die. Document #: 38-05006 Rev. *G Page 4 of 12 [+] Feedback CY7C1049CV33 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC to Relative GND[2] –0.5V to +4.6VDC Voltage Applied to Outputs in High-Z State[2].................................... –0.5V to VCC + 0.5V Input Voltage[2] ...................................... –0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Operating Range Range Commercial Industrial/ Automotive-A Automotive-E Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C VCC 3.3V ± 0.3V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current GND < VI < VCC Com’l/Ind’l/ Auto-A Auto-E ICC VCC Operating Supply Current Automatic CE Power Down Current —TTL Inputs Automatic CE Power Down Current —CMOS Inputs VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l Ind’l/Auto-A Auto-E ISB1 Com’l/Ind’l/ Auto-A Auto-E Com’l/Ind’l/ Auto-A Auto-E 10 10 15 40 40 45 90 100 85 95 95 mA mA mA mA Test Conditions VCC = Min.; IOH = –4.0 mA VCC = Min.,; IOL = 8.0 mA 2.0 –0.3 –1 -10 Min 2.4 0.4 VCC + 0.3 0.8 +1 2.0 –0.3 –1 Max Min 2.4 0.4 VCC + 0.3 0.8 +1 –20 +20 mA 2.0 –0.3 -12 Max Min 2.4 0.4 VCC + 0.3 0.8 -15 Max Unit V V V V μA ISB2 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max 8 8 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions 36-Pin SOJ 46.51 18.8 44-TSOP-II 41.66 10.56 Unit °C/W °C/W ΘJA ΘJC Thermal Resistance (Junction Test conditions follow standard to Ambient) test methods and procedures for measuring thermal impedance, Thermal Resistance per EIA / JESD51. (Junction to Case) Notes 2. VIL (min) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05006 Rev. *G Page 5 of 12 [+] Feedback CY7C1049CV33 Figure 3. AC Test Loads and Waveforms [3] 10-ns devices: OUTPUT 50Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 12-, 15-ns devices: 3.3V OUTPUT 30 pF R2 351Ω R 317 Ω Z = 50Ω 30 pF* (a) High-Z characteristics: 3.3V 90% 10% OUTPUT 5 pF (b) R 317 Ω 3.0V GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 10% R2 351Ω (c) Fall Time: 1 V/ns (d) Note 4. AC characteristics (except High-Z) for 10 ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document #: 38-05006 Rev. *G Page 6 of 12 [+] Feedback CY7C1049CV33 AC Switching Characteristics Over the Operating Range [5] -10 Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[7, 8] CE LOW to CE HIGH to Low-Z[8] High-Z[7, 8] 0 10 10 7 7 0 0 7 5 0 3 5 12 8 8 0 0 8 6 0 3 6 3 5 0 12 15 10 10 0 0 10 7 0 3 7 0 5 3 6 0 15 3 10 5 0 6 3 7 100 10 10 3 12 6 0 7 100 12 12 100 15 15 3 15 7 μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min Max Min -12 Max Min -15 Max Unit CE LOW to Power Up CE HIGH to Power Down [9, 10] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z[7, 8] Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05006 Rev. *G Page 7 of 12 [+] Feedback CY7C1049CV33 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [14, 15] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 16 tHZOE Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycles. 13. Address valid before or similar to CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 16. During this period, the I/Os are in output state. Do not apply input signals. tHD DATA VALID Document #: 38-05006 Rev. *G Page 8 of 12 [+] Feedback CY7C1049CV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [15] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L OE X L X H WE X H L H High-Z Data Out Data In High-Z I/O0–I/O7 Power Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1049CV33-10VXC CY7C1049CV33-10ZXI CY7C1049CV33-10VXA 12 15 CY7C1049CV33-12VXC CY7C1049CV33-12ZSXA CY7C1049CV33-15VXE CY7C1049CV33-15ZSXE Package Diagram 51-85090 51-85087 51-85090 51-85090 51-85087 51-85090 51-85087 Package Type 36-Pin (400-Mil) Molded SOJ (Pb-Free) 44-Pin TSOP II (Pb-Free) 36-Pin (400-Mil) Molded SOJ (Pb-Free) 36-Pin (400-Mil) Molded SOJ (Pb-Free) 44-Pin TSOP II (Pb-Free) 36-Pin (400-Mil) Molded SOJ (Pb-Free) 44-Pin TSOP II (Pb-Free) Operating Range Commercial Industrial Automotive-A Commercial Automotive-A Automotive-E Document #: 38-05006 Rev. *G Page 9 of 12 [+] Feedback CY7C1049CV33 Package Diagrams Figure 8. 36-Pin (400-Mil) Molded SOJ V36, 51-85090 PIN 1 I.D .435 .445 .395 .405 .007 .013 .360 .380 .920 .930 DIMENSIONS IN INCHES MIN. MAX. .128 .148 .050 TYP. .026 .032 .015 .020 .025 MIN. SEATING PLANE 51-85090 *D Figure 9. 44-Pin TSOP II, 51-85087 22 1 PIN 1 I.D. 11.938 (0.470) 11.735 (0.462) 10.262 (0.404) 10.058 (0.396) OR E KXA SG EJECTOR PIN 23 44 TOP VIEW BOTTOM VIEW 0.800 BSC (0.0315) 0.400(0.016) 0.300 (0.012) BASE PLANE 10.262 (0.404) 10.058 (0.396) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.729) 18.313 (0.721) 0.10 (.004) SEATING PLANE 0°-5° 0.210 (0.0083) 0.120 (0.0047) 0.597 (0.0235) 0.406 (0.0160) DIMENSION IN MM (INCH) MAX MIN. 51-85087 *B Document #: 38-05006 Rev. *G Page 10 of 12 [+] Feedback CY7C1049CV33 Document History Page Document Title: CY7C1049CV33, 4 Mbit (512K x 8) Static RAM Document Number: 38-05006 Rev. ** *A *B *C *D *E ECN 112569 114091 116479 262949 300091 344595 Orig. of Change HGK DFP CEA RKF RKF SYT Submission Date 03/06/02 04/25/02 09/16/02 See ECN See ECN See ECN New data sheet Changed Tpower unit from ns to μs Add applications foot note to data sheet, page 1. Added Automotive-E Specs Added ΘJA and ΘJC values on Page #3. Added -20-ns Speed bin Added Pb-Free package on page #8 Removed shading for CY7C1049CV33-15ZSXE in the ordering Information on page 9 Added Automotive-A information Removed 8 ns and 20 ns speed bins, Changed tPOWER spec from 1 μs to 100 μs, Updated Ordering Information table. Description of Change *F 2615344 VKN/PYRS 12/03/08 *G 2841563 NXR/ 01/07/2010 Added CY7C1049CV33-10VXA to Ordering Info table. Document #: 38-05006 Rev. *G Page 11 of 12 [+] Feedback CY7C1049CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05006 Rev. *G Revised January 07, 2010 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback