CY7C1248KV18

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Configurations With Read Cycle Latency of 2.0 Cycles: CY7C1246KV18 – 4 M × 8 CY7C1257KV18 – 4 M × 9 CY7C1248KV18 – 2 M × 18 CY7C1250KV18 – 1 M × 36 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36) 450 MHz clock for high bandwidth 2-word burst for reducing address bus frequency Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz Available in 2.0 clock cycle latency Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high speed systems Data valid pin (QVLD) to indicate valid data on the output Synchronous internally self-timed writes DDR II+ operates with 2.0 cycle read latency when DOFF is asserted HIGH Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1] ❐ Supports both 1.5 V and 1.8 V I/O supply HSTL inputs and variable drive HSTL output buffers Available in 165-ball FBGA package (13 × 15 × 1.4 mm) Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Description Functional Description The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1246KV18), 9-bit words (CY7C1257KV18), 18-bit words (CY7C1248KV18), or 36-bit words (CY7C1250KV18) that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Selection Guide 450 MHz 450 ×8 ×9 × 18 × 36 590 590 600 760 400 MHz 400 540 540 550 690 375 MHz 375 520 520 530 660 333 MHz 333 480 480 490 600 Unit MHz mA Maximum operating frequency Maximum operating current Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD. Cypress Semiconductor Corporation Document Number: 001-57834 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 24, 2011 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Logic Block Diagram (CY7C1246KV18) A(20:0) LD K K DOFF 21 Write Add. Decode Read Add. Decode Address Register Write Reg 2M x 8 Array Write Reg 8 2M x 8 Array CLK Gen. Output Logic Control R/W Read Data Reg. 16 Control Logic CQ CQ 8 8 DQ[7:0] QVLD VREF R/W NWS[1:0] 8 8 Reg. Reg. Reg. 8 Logic Block Diagram (CY7C1257KV18) A(20:0) LD K K DOFF 21 Write Add. Decode Read Add. Decode Address Register Write Reg 2M x 9 Array Write Reg 9 2M x 9 Array CLK Gen. Output Logic Control R/W Read Data Reg. 18 Control Logic CQ CQ 9 9 DQ[8:0] QVLD VREF R/W BWS[0] 9 9 Reg. Reg. Reg. 9 Document Number: 001-57834 Rev. *B Page 2 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Logic Block Diagram (CY7C1248KV18) A(19:0) LD K K DOFF 20 Write Add. Decode Read Add. Decode Address Register Write Reg 1M x 18 Array Write Reg 18 1M x 18 Array CLK Gen. Output Logic Control R/W Read Data Reg. 36 Control Logic CQ CQ 18 VREF R/W BWS[1:0] 18 18 Reg. Reg. Reg. 18 18 DQ[17:0] QVLD Logic Block Diagram (CY7C1250KV18) A(18:0) LD K K DOFF 19 Write Add. Decode Read Add. Decode Address Register Write Reg 512K x 36 Array Write Reg 36 512K x 36 Array CLK Gen. Output Logic Control R/W Read Data Reg. 72 Control Logic CQ CQ 36 VREF R/W BWS[3:0] 36 36 Reg. Reg. Reg. 36 36 DQ[35:0] QVLD Document Number: 001-57834 Rev. *B Page 3 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Contents Pin Configuration ............................................................. 5 165-ball FBGA (13 × 15 × 1.4 mm) pinout .................. 5 Functional Overview ........................................................ 9 Read Operations ......................................................... 9 Write Operations ......................................................... 9 Byte Write Operations ................................................. 9 DDR Operation ............................................................ 9 Depth Expansion ......................................................... 9 Programmable Impedance .......................................... 9 Echo Clocks ................................................................ 9 Valid Data Indicator (QVLD) ...................................... 10 PLL ............................................................................ 10 Application Example ...................................................... 10 Truth Table ...................................................................... 11 Write Cycle Descriptions ............................................... 11 Write Cycle Descriptions ............................................... 12 Write Cycle Descriptions ............................................... 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port—Test Clock ................................... 13 Test Mode Select (TMS) ........................................... 13 Test Data-In (TDI) ..................................................... 13 Test Data-Out (TDO) ................................................. 13 Performing a TAP Reset ........................................... 13 TAP Registers ........................................................... 13 TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 TAP Electrical Characteristics ...................................... 16 TAP AC Switching Characteristics ............................... 17 TAP Timing and Test Conditions .................................. 17 Identification Register Definitions ................................ 18 Scan Register Sizes ....................................................... 18 Instruction Codes ........................................................... 18 Boundary Scan Order .................................................... 19 Power Up Sequence in DDR II+ SRAM ......................... 20 Power Up Sequence ................................................. 20 PLL Constraints ......................................................... 20 Maximum Ratings ........................................................... 21 Operating Range ............................................................. 21 Neutron Soft Error Immunity ......................................... 21 Electrical Characteristics ............................................... 21 DC Electrical Characteristics ..................................... 21 AC Electrical Characteristics ..................................... 23 Capacitance .................................................................... 23 Thermal Resistance ........................................................ 23 Switching Characteristics .............................................. 24 Switching Waveforms .................................................... 25 Read/Write/Deselect Sequence ................................ 25 Ordering Information ...................................................... 26 Ordering Code Definitions ......................................... 26 Package Diagram ............................................................ 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC Solutions ......................................................... 28 Document Number: 001-57834 Rev. *B Page 4 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Pin Configuration The pin configuration for CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follows.[2] 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1246KV18 (4 M × 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI CY7C1257KV18 (4 M × 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC DQ8 TDI Note 2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-57834 Rev. *B Page 5 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Pin Configuration (continued) The pin configuration for CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follows.[2] 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1248KV18 (2 M × 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI CY7C1250KV18 (1 M × 36) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 A DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI Document Number: 001-57834 Rev. *B Page 6 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Table 2. Pin Definitions Pin Name DQ[x:0] I/O Pin Description Input output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of both the K and K clocks during read operations. When read access is deselected, Q[x:0] are automatically tristated. CY7C1246KV18  DQ[7:0] CY7C1257KV18  DQ[8:0] CY7C1248KV18  DQ[17:0] CY7C1250KV18  DQ[35:0] InputSynchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K. InputNibble write select 0, 1  active LOW (CY7C1246KV18 only). Sampled on the rising edge of the K and synchronous K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. InputByte write select 0, 1, 2, and 3  active LOW. Sampled on the rising edge of the K and K clocks during synchronous write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1257KV18  BWS0 controls D[8:0] CY7C1248KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1250KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. InputAddress inputs. Sampled on the rising edge of the K clock during active read and write operations. These synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4 M × 8 (2 arrays each of 2 M × 8) for CY7C1246KV18 and 4 M × 9 (2 arrays each of 2 M × 9) for CY7C1257KV18, 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1248KV18, and 1 M × 36 (2 arrays each of 512 K × 36) for CY7C1250KV18. InputSynchronous read or write input. When LD is LOW, this input designates the access type (read when synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times around edge of K. Valid output indicator Input clock Input clock Echo clock Echo clock Input Valid output indicator. The Q valid indicates valid output data. QVLD is edge aligned with CQ and CQ. Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K. Negative input clock input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0]. Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24. Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24. Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. LD NWS0, NWS1 BWS0, BWS1, BWS2, BWS3 A R/W QVLD K K CQ CQ ZQ Document Number: 001-57834 Rev. *B Page 7 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Table 2. Pin Definitions (continued) Pin Name DOFF I/O Input Pin Description PLL turn off  active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 K or less pull-up resistor. The device behaves in DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR I timing. TDO for JTAG TCK pin for JTAG TDI pin for JTAG TMS pin for JTAG Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Ground for the device TDO TCK TDI TMS NC NC/144M NC/288M VREF VDD VSS VDDQ Output Input Input Input N/A Input Input Inputreference Ground Power supply Power supply inputs to the core of the device Power supply Power supply inputs for the outputs of the device Document Number: 001-57834 Rev. *B Page 8 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Functional Overview The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 are synchronous pipelined burst SRAMs equipped with a DDR interface, which operates with a read latency of two cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input and output timing is referenced from the rising edge of the input clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the input clocks (K and K). All synchronous control (R/W, LD, NWS[X:0], BWS[X:0]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C1248KV18 is described in the following sections. The same basic descriptions apply to CY7C1246KV18, CY7C1257KV18, and CY7C1250KV18. When the write access is deselected, the device ignores all inputs after the pending write operations have been completed. Byte Write Operations Byte write operations are supported by the CY7C1248KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. DDR Operation The CY7C1248KV18 enables high performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C1248KV18 requires two No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Read Operations The CY7C1248KV18 is organized internally as two arrays of 1 M × 18. Accesses are completed in a burst of 2 sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K and K). To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). When read access is deselected, the CY7C1248KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output following the next rising edge of the positive input clock (K). This enables for a transition between devices without the insertion of wait states in a depth expanded memory. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5 × the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175  and 350 , with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). Echo Clocks Echo clocks are provided on the DDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR II+. The timing for the echo clocks is shown in the “Switching Characteristics” on page 24. Document Number: 001-57834 Rev. *B Page 9 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Valid Data Indicator (QVLD) QVLD is provided on the DDR II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. power-up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+. PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During Application Example Figure 1 shows two DDR II+ used in an application. Figure 1. Application Example ZQ CQ/CQ KK R = 250ohms DQ A R = 250ohms DQ A SRAM#1 LD R/W BWS SRAM#2 LD R/W BWS ZQ CQ/CQ KK DQ Addresses BUS LD MASTER R/W (CPU or ASIC) BWS Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Document Number: 001-57834 Rev. *B Page 10 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Truth Table The truth table for the CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follow.[3, 4, 5, 6, 7, 8] Operation Write cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read cycle: (2.0 cycle latency) Load address; wait two cycles; read data on consecutive K and K rising edges. NOP: No operation Standby: Clock stopped K L–H LD L R/W L DQ D(A) at K(t + 1)  DQ D(A+1) at K(t + 1)  L–H L H Q(A) at K(t + 2) Q(A+1) at K(t + 2)  L–H Stopped H X X X High Z Previous state High Z Previous state Write Cycle Descriptions The write cycle description table for CY7C1246KV18 and CY7C1248KV18 follows.[3, 9] BWS0/ BWS1/ NWS0 L NWS1 L K L–H K – Comments During the data portion of a write sequence CY7C1246KV18 both nibbles (D[7:0]) are written into the device. CY7C1248KV18 both bytes (D[17:0]) are written into the device. L L – L–H During the data portion of a write sequence CY7C1246KV18 both nibbles (D[7:0]) are written into the device. CY7C1248KV18 both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence CY7C1246KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1248KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L H L–H L H – L–H During the data portion of a write sequence CY7C1246KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1248KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence CY7C1246KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1248KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. H L L–H H L – L–H During the data portion of a write sequence CY7C1246KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1248KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. H H H H L–H – Notes 3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 4. Device powers up deselected with the outputs in a tristate condition. 5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst. 6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-57834 Rev. *B Page 11 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Write Cycle Descriptions The write cycle description table for CY7C1257KV18 follows.[10, 11] BWS0 L L H H K L–H – L–H – K – L–H – L–H Comments During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1250KV18 follows.[10, 11] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L–H – L–H – L–H – L–H – L–H – L–H – K – Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Notes 10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 11. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-57834 Rev. *B Page 12 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8 V I/O logic levels. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 16. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 19 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 18. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull-up resistor. TDO must be left unconnected. Upon power-up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 18). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-57834 Rev. *B Page 13 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a high Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-57834 Rev. *B Page 14 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 TAP Controller State Diagram The state diagram for the TAP controller follows.[12] 1 TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 1 Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-57834 Rev. *B Page 15 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 TAP Controller Block Diagram 0 Bypass Register 2 TDI Selection Circuitry 31 Instruction Register 30 29 . . 2 1 0 1 0 Selection Circuitry TDO Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range [13, 14, 15] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH voltage Output HIGH voltage Output LOW voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input and output load current GND  VI  VDD Test Conditions IOH =2.0 mA IOH =100 A IOL = 2.0 mA IOL = 100 A Min 1.4 1.6 – – Max – – 0.4 0.2 Unit V V V V V V A 0.65 VDD VDD + 0.3 –0.3 –5 0.35 VDD 5 Notes 13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 14. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 15. All voltage referenced to ground. Document Number: 001-57834 Rev. *B Page 16 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 TAP AC Switching Characteristics Over the Operating Range [16, 17] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK clock LOW to TDO valid TCK clock LOW to TDO invalid – 0 10 – ns ns TMS hold after TCK clock rise TDI hold after clock rise Capture hold after clock rise 5 5 5 – – – ns ns ns TMS set-up to TCK clock rise TDI set-up to TCK clock rise Capture set-up to TCK rise 5 5 5 – – – ns ns ns TCK clock cycle time TCK clock frequency TCK clock HIGH TCK clock LOW Description Min 50 – 20 20 Max – 20 – – Unit ns MHz ns ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions. [17] Figure 2. TAP Timing and Test Conditions 0.9V 50 TDO Z0 = 50 CL = 20 pF ALL INPUT PULSES 1.8V 0.9V 0V (a) GND tTH tTL Test Clock TCK tTMSS tTMSH tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Notes 16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-57834 Rev. *B Page 17 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Identification Register Definitions Instruction Field Revision number (31:29) Cypress device ID (28:12) Cypress JEDEC ID (11:1) ID register presence (0) Value CY7C1246KV18 000 11010111100000111 00000110100 CY7C1257KV18 000 11010111100001111 00000110100 CY7C1248KV18 000 11010111100010111 00000110100 CY7C1250KV18 000 Description Version number. 11010111100100111 Defines the type of SRAM. 00000110100 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. 1 1 1 1 Scan Register Sizes Register Name Instruction Bypass ID Boundary scan Bit Size 3 1 32 109 Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-57834 Rev. *B Page 18 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal Document Number: 001-57834 Rev. *B Page 19 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Power Up Sequence in DDR II+ SRAM DDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. PLL Constraints ■ ■ ■ PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. The PLL functions at frequencies down to 120 MHz. If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 20 s of stable clock to relock to the desired clock frequency. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL. ■ Figure 3. Power Up Waveforms ~ ~ K K ~ ~ Unstable Clock > 20 s Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to VDDQ) Document Number: 001-57834 Rev. *B Page 20 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied . –55 °C to +125 °C Supply voltage on VDD relative to GND ........–0.5 V to +2.9 V Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD DC applied to outputs in high Z .........–0.5 V to VDDQ + 0.3 V DC input voltage [18] ............................ –0.5 V to VDD + 0.3 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage (MIL-STD-883, M 3015).. > 2,001 V Latch-up current .................................................... > 200 mA SEL LMBU Neutron Soft Error Immunity Parameter LSBU Description Logical single-bit upsets Logical multi-bit upsets Single event latch-up Test Conditions 25 °C 25 °C 85 °C Typ 197 0 0 Max* 216 0.01 0.1 Unit FIT/ Mb FIT/ Mb FIT/ Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Operating Range Range Commercial Industrial Ambient Temperature (TA) 0 °C to +70 °C –40 °C to +85 °C VDD [19] 1.8 ± 0.1 V VDDQ [19] 1.4 V to VDD Electrical Characteristics DC Electrical Characteristics Over the Operating Range [20] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF Description Power supply voltage I/O supply voltage Output HIGH voltage Output LOW voltage Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current Input reference voltage [23] Test Conditions Min 1.7 1.4 Typ 1.8 1.5 – – – – – – – – 0.75 Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.15 VREF – 0.1 2 2 0.95 Unit V V V V V V V V A A V Note 21 Note 22 IOH 0.1 mA, nominal impedance IOL = 0.1 mA, nominal impedance VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.15 GND  VI  VDDQ GND  VI  VDDQ, output disabled Typical value = 0.75 V 2 2 0.68 Notes 18. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 19. Power-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 20. All voltage referenced to ground. 21. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 . 22. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175  < RQ < 350 . 23. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller. Document Number: 001-57834 Rev. *B Page 21 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Electrical Characteristics DC Electrical Characteristics Over the Operating Range [20] Parameter IDD [24] (continued) Description VDD operating supply Test Conditions VDD = Max, IOUT = 0 mA, 450 MHz (× 8) f = fMAX = 1/tCYC (× 9) (× 18) (× 36) 400 MHz (× 8) (× 9) (× 18) (× 36) 375 MHz (× 8) (× 9) (× 18) (× 36) 333 MHz (× 8) (× 9) (× 18) (× 36) Min – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Typ – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Max 590 590 600 760 540 540 550 690 520 520 530 660 480 480 490 600 330 330 330 330 310 310 310 310 300 300 300 300 280 280 280 280 Unit mA mA mA mA ISB1 Automatic power-down current Max VDD, both ports deselected, VIN  VIH or VIN  VIL f = fMAX = 1/tCYC, inputs static 450 MHz (× 8) (× 9) (× 18) (× 36) 400 MHz (× 8) (× 9) (× 18) (× 36) 375 MHz (× 8) (× 9) (× 18) (× 36) 333 MHz (× 8) (× 9) (× 18) (× 36) mA mA mA mA Note 24. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-57834 Rev. *B Page 22 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 AC Electrical Characteristics Over the Operating Range [25] Parameter VIH VIL Description Input HIGH voltage Input LOW voltage Test Conditions Min VREF + 0.2 –0.24 Typ – – Max VDDQ + 0.24 VREF – 0.2 Unit V V Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter CIN CO Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V Max 4 4 Unit pF pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 4. AC Test Loads and Waveforms VREF = 0.75 V VREF OUTPUT Device Under Test Z0 = 50  RL = 50  0.75 V VREF OUTPUT 5 pF 0.25 V Slew Rate = 2 V/ns 0.75 V R = 50  ALL INPUT PULSES 1.25 V 0.75 V [26] Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165 FBGA Package 13.7 3.73 Unit °C/W °C/W ZQ (a) Device Under VREF = 0.75 V Test ZQ RQ = 250  INCLUDING JIG AND SCOPE RQ = 250  (b) Notes 25. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 26. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms. Document Number: 001-57834 Rev. *B Page 23 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Switching Characteristics Over the Operating Range [27, 28] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHKH tKHKL tKLKH tKHKH Description VDD(typical) to the first access [29] K clock cycle time Input clock (K/K) HIGH Input clock (K/K) LOW K clock rise to K clock rise (rising edge to rising edge) Address set-up to K clock rise Control set-up to K clock rise (LD, R/W) 450 MHz 400 MHz 375 MHz 333 MHz Min Max Min Max Min Max Min Max 1 2.20 0.4 0.4 0.94 – 8.4 – – – 1 2.50 0.4 0.4 1.06 – 8.4 – – – 1 2.66 0.4 0.4 1.13 – 8.4 – – – 1 3.0 0.4 0.4 1.28 – 8.4 – – – Unit ms ns ns ns ns Setup Times tAVKH tSA tSC tIVKH tSCDDR tIVKH tSD tDVKH Hold Times tHA tKHAX tHC tKHIX tHCDDR tKHIX tHD tKHDX Output Times tCO tCHQV tDOH tCHQX tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH 0.275 0.275 – – – – – – – – 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – – – – – – – – 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – – – – – – – – 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – – – – – – – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns Double data rate control set-up to clock (K/K) rise 0.22 (BWS0, BWS1, BWS2, BWS3) D[X:0] set-up to clock (K/K) rise 0.22 Address hold after K clock rise Control hold after K clock rise (LD, R/W) Double data rate control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) D[X:0] hold after clock (K/K) rise 0.275 0.275 0.22 0.22 tCHQZ tCLZ tCHQX1 tQVLD tCQHQVLD PLL Timing tKC Var tKC Var tKC lock tKC lock tKC Reset tKC Reset K/K clock rise to data valid – Data output hold after output K/K clock rise –0.45 (active to active) K/K clock rise to echo clock valid – Echo clock hold after K/K clock rise –0.45 Echo clock high to data valid – Echo clock high to data invalid –0.15 Output clock (CQ/CQ) HIGH [30] 0.85 CQ clock rise to CQ clock rise 0.85 (rising edge to rising edge) [30] Clock (K/K) rise to high Z (active to high Z) [31, 32] – Clock (K/K) rise to low Z [31, 32] –0.45 Echo clock high to QVLD valid [33] –0.15 Clock phase jitter PLL lock time (K) K static to PLL reset [34] – 20 30 0.45 – 0.45 – 0.45 – 0.45 – –0.45 – –0.45 – –0.45 – 0.45 – 0.15 – – – – 0.45 – 0.45 – 0.45 –0.45 – –0.45 – –0.45 – – 0.20 – 0.20 – 0.20 –0.20 – –0.20 – –0.20 – 1.00 – 1.08 – 1.25 – 1.00 – 1.08 – 1.25 – 0.45 – 0.45 – 0.45 – 0.45 – –0.45 – –0.45 – –0.45 – 0.15 –0.20 0.20 –0.20 0.20 –0.20 0.20 0.15 – – – 20 30 0.20 – – – 20 30 0.20 – – – 20 30 0.20 – – Notes 27. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms. 28. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 29. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated. 30. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 31. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage. 32. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 33. tQVLD specification is applicable for both rising and falling edges of QVLD signal. 34. Hold to >VIH or