CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Synchronous
Pipelined SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150
MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect,
depth expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down feature available using ZZ
mode or CE select.
• JTAG boundary scan for B/BG and T/AJ package
version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE3), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE3 Chip Enable input is only available
for the TA(GVTI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package
versions, four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock
(TCK), and Test Data-Out (TDO). The JTAG circuitry is used
to serially shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode
of operation. The TA package version does not offer the JTAG
capability.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
Unit
Maximum Access Time
2.5
3.0
3.5
3.5
ns
Maximum Operating Current
570
510
425
380
mA
Maximum CMOS Standby Current
10
10
10
10
mA
Cypress Semiconductor Corporation
Document #: 38-05264 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 17, 2003
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Functional Block Diagram—256K x 36[1, 2]
B Y T E a W R IT E
BW
B
W aa
BWE
BWE
D
Q
CLK
CLK
B Y T E b W R IT E
B
W bb
BW
D
Q
GW
GW
B Y T E c W R IT E
BW
B W cc
D
Q
B Y T E d W R IT E
Q
Q
[2]
P o w er D o w n L o g ic
In p u t
R eg is ter
AADSP
DSP
A
D
16
A
A d d res s
R eg ister
CLR
ADV
ADV
O U TPU T
R E G IS T E R
256K x 9 x 4
SRAM Array
AADSC
D SC
D
Output Buffers
OE
OE
ZZZ Z
E N A B LE
byte a write
D
byte b write
CE
C1
E
CE2
CE
2
CE2
CE
3
Q
byte c write
D
byte d write
B
W dd
BW
Q
B in ary
C o u nter
& L o g ic
A0-A1
A
1-A 0
MODE
M
ODE
DDQa,
Q a,D QDQb,
b
DDQc,
Q c,D QDQd
d
Functional Block Diagram—512K x 18[1]
BYTE b
WRITE
BWb
BWb
BWE
BWE
D
Q
CLK
BYTE a
WRITE
BWa
BWa
D
Q
ZZZZ
byte a write
CE
CE
1
CE
CE2
2
CE
CE2
3
ENABLE
[2]
D
Q
D
byte b write
GW
GW
Q
Power Down Logic
OE
OE
ADSP
ADSP
Input
Register
17
CLR
ADV
ADV
A0-A1
A1-A0
MODE
MODE
Binary
Counter
& Logic
OUTPUT
REGISTER
D
Q
Output Buffers
Address
Register
ADSC
ADSC
512K x 9 x 2
SRAM Array
A A
DQa,D
DQa, DQb,
Qb
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See the Truth Table, pin descriptions, and timing diagrams for detailed information.
2. CE3 is for the TA version only.
Document #: 38-05264 Rev. *A
Page 2 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations
A
A
CE1
CE2
BWd
BWc
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
C E1
C E2
BW d
BW c
BW b
BW a
C E3
VCC
V SS
CL K
GW
BW E
OE
A DSC
A DSP
A DV
A
A
CY7C1366A/GVT71256C36
256Kx 36 100-pin TQFP
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100-pinTQFP
TQFP
100-Pin
TA Package Version
DQb
DQb
DQb
V CCQ
V SS
DQb
DQb
DQb
DQb
V SS
V CCQ
DQb
DQb
V SS
NC
V CC
ZZ
DQa
DQa
V CCQ
V SS
DQa
DQa
DQa
DQa
V SS
V CCQ
DQa
DQa
DQa
NC
A
A
A
A
A
A
A
A
M ODE
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
38
39
40
41
42
43
44
45
46
47
48
49
50
T Package Version
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
100-pin TQFP
DQc
DQc
DQc
VCCQ
V SS
DQc
DQc
DQc
DQc
V SS
VCCQ
DQc
DQc
NC
V CC
NC
V SS
DQd
DQd
VCCQ
V SS
DQd
DQd
DQd
DQd
V SS
VCCQ
DQd
DQd
DQd
NC
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
A
A
A
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
NC
V SS
VC C
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
Top View
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
NC
NC
V CCQ
V SS
NC
DPa
DQa
DQa
V SS
V CCQ
DQa
DQa
V SS
NC
V CC
ZZ
DQa
DQa
V CCQ
V SS
DQa
DQa
NC
NC
V SS
V DDQ
NC
NC
NC
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
TA Package Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A
A
A
A
48
A
49
47
A
A
45
A
46
44
T CK
V CC
43
41
VS S
T DO
40
Document #: 38-05264 Rev. *A
42
39
36
A1
T DI
35
A
38
34
A
37
33
A
A0
32
TMS
31
T Package Version
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
A
81
A DV
82
A DSP
83
A DSC
84
GW
OE
C LK
88
85
V SS
89
B WE
V CC
90
86
A
91
87
B Wa
92
B Wb
NC
93
NC
95
94
CE2
96
C E1
97
A
98
A
99
Top View
100-pin
TQFP
100-pin
TQFP
A
V CCQ
V SS
NC
NC
DQb
DQb
V SS
V CCQ
DQb
DQb
NC
V CC
NC
V SS
DQb
DQb
V CCQ
V SS
DQb
DQb
DQb
NC
V SS
V CCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
M O DE
NC
NC
NC
100
CY7C1367A/GVT71512C18
512K x 18 100- pin TQFP
Page 3 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations (continued)
CY7C1366A/GVT71256C36
256K x 36 119-ball BGA
Top View
256Kx36
1
2
3
4
5
6
7
A
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1367A/GVT71512C18 512Kx18 119-Ball BGA
Top View
A
1
2
3
4
5
6
7
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
CE3
NC
C
NC
A
A
VCC
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQa
NC
E
NC
DQb
VSS
CE1
VSS
NC
DQa
F
VCCQ
NC
VSS
OE
VSS
DQa
VCCQ
G
NC
DQb
BWb
ADV
VSS
NC
DQa
H
DQb
NC
VSS
GW
VSS
DQa
NC
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VCCQ
DQb
VSS
BWE
VSS
NC
VCCQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05264 Rev. *A
Page 4 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K × 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
4P
37
4N
36
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32,
5B, 6B, 2C, 3C, 5C, 100, 99, 82, 81,
6C, 2R, 6R, 3T, 4T, 44, 45, 46, 47, 48,
5T
49, 50
92 (T/AJ Version)
43 (TA/A Version)
Name
Type
Description
A0
A1
A
InputAddresses: These inputs are registered and must meet the set
Synchronous up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
InputByte Write: A byte write is LOW for a WRITE cycle and HIGH for
Synchronous a READ cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
InputWrite Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge
of CLK.
4H
88
GW
InputGlobal Write: This active LOW input allows a full 36-bit Write to
Synchronous occur independent of the BWE and BWn lines and must meet the
set-up and hold times around the rising edge of CLK.
4K
89
CLK
InputClock: This signal registers the addresses, data, chip enables,
Synchronous write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around the
clock’s rising edge.
4E
98
CE1
InputChip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
2B
97
CE2
InputChip Enable: This active HIGH input is used to enable the
Synchronous device.
(not available for
PBGA)
92 (for TA/A
Version only)
CE3
InputChip Enable: This active LOW input is used to enable the device.
Synchronous Not available for B and T package versions.
4F
86
OE
4G
83
ADV
InputAddress Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
InputAddress Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
4B
85
ADSC
InputAddress Status Controller: This active LOW input causes
Synchronous device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
3R
31
MOD
E
7T
64
ZZ
(a) 6P, 7P, 7N, 6N,
6M, 6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E,
2F, 1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L,
2M, 1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
9, 12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
DQa
DQb
DQc
DQd
Document #: 38-05264 Rev. *A
Input
InputStatic
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Mode: This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
InputSleep: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
Page 5 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K × 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins
Name
Type
Description
2U
3U
4U
38
39
43
for BG/B and
T/AJ
version
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for
TA/A package version.
5U
42
for BG/B and
T/AJ
version
TDO
Output Power IEEE 1149.1 Test Output: LVTTL-level output. Not available for
TA/A package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Power Supply Core Power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26,
5F, 3H, 5H, 3K, 5K, 40, 55, 60, 67, 71,
3M, 5M, 3N, 5N, 3P,
76, 90
5P
VSS
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54, VCCQ
7J, 1M, 7M, 1U, 7U
61, 70, 77
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
NC
Ground
I/O Power
Supply
–
38, 39, 42 for
TA/A Version
Ground: GND.
Power supply for the circuitry.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
512K × 18 Pin Descriptions
X18 PBGA Pins
X18 QFP Pins
4P
37
4N
36
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32,
5B, 6B, 2C, 3C, 5C, 100, 99, 82, 81,
6C, 2R, 6R, 2T, 3T, 80, 48, 47, 46, 45,
5T, 6T
44, 49, 50
92 (T/AJ Version)
43 (TA/A Version)
Name
Type
Description
A0
A1
A
InputAddresses: These inputs are registered and must meet the
Synchronous set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
3G
93
94
BWa
BWb
InputByte Write Enables: A byte write enable is LOW for a WRITE
Synchronous cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
InputWrite Enable: This active LOW input gates byte write operaSynchronous tions and must meet the set up and hold times around the rising
edge of CLK.
4H
88
GW
InputGlobal Write: This active LOW input allows a full 18-bit WRITE
Synchronous to occur independent of the BWE and WEn lines and must meet
the set up and hold times around the rising edge of CLK.
4K
89
CLK
InputClock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
4E
98
CE1
InputChip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
2B
97
CE2
InputChip Enable: This active HIGH input is used to enable the
Synchronous device.
(not available for
PBGA)
92 (for TA/A
Version only)
CE3
InputChip Enable: This active LOW input is used to enable the
Synchronous device. Not available for B/BG and T/AJ package versions.
4F
86
OE
Document #: 38-05264 Rev. *A
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Page 6 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
512K × 18 Pin Descriptions (continued)
X18 PBGA Pins
X18 QFP Pins
Name
4G
83
ADV
InputAddress Advance: This active LOW input is used to control
Synchronous the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
Type
4A
84
ADSP
InputAddress Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a Read cycle is initiated using the new address.
4B
85
ADSC
InputAddress Status Controller: This active LOW input causes
Synchronous device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
3R
31
MODE
7T
64
ZZ
(a) 6D, 7E, 6F, 7G,
6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N, 2P
(a) 58, 59, 62, 63,
68, 69, 72, 73, 74
(b) 8, 9, 12, 13,
18, 19, 22, 23, 24
DQa
DQb
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.
Input data must meet set up and hold times around the rising
edge of CLK.
2U
3U
4U
38
39
43
for B/BG and
T/AJ
version
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for
TA/A package version.
5U
42
for B/BG and
T/AJ
version
TDO
Power Output IEEE 1149.1 Test Output: LVTTL-level output. Not available
for TA/A package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Power Supply Core Power Supply: +3.3V –5% and +10%
InputStatic
VSS
Ground
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54,
7J, 1M, 7M, 1U, 7U
61, 70, 77
VCCQ
I/O Power
Supply
NC
-
1-3, 6, 7, 14, 16,
25, 28-30, 51-53,
56, 57, 66, 75, 78,
79, 80, 95, 96
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects Interlinear Burst.
InputSleep: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26,
5F, 5G, 3H, 5H, 3K, 40, 55, 60, 67, 71,
5K, 3L, 3M, 5M, 3N,
76, 90
5N, 3P, 5P
1B, 7B, 1C, 7C, 2D,
4D, 7D, 1E, 6E, 2F,
1G, 6G, 2H, 7H, 3J,
5J, 1K, 6K, 2L, 4L,
7L, 6M, 2N, 7N, 1P,
6P, 1R, 5R, 7R, 1T,
4T, 6U
Description
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
38, 39, 42 for TA
Version
Document #: 38-05264 Rev. *A
Page 7 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 4.5 ns
(150-MHz device).
The CY7C1366A/CY7C1367A supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for 1366B and BWa,b
for 1367B) inputs. A Global Write Enable (GW) overrides all
byte write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 4.5 ns (150-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
The CY7C1366B/CY7C1367B are double-cycle deselect
parts. Once the SRAM is deselected at clock rise by the chip
select and either ADSP or ADSC signals, its output will
three-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
Document #: 38-05264 Rev. *A
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx
signals. The CY7C1366/CY7C1367A provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1366 and BWa,b for
CY7C1367A) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1366/CY7C1367A is a common I/O device,
the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1366/CY7C1367B is a common I/O device,
the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ[x:0] inputs. Doing so will three-state
the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The
CY7C1366/GVT71256C36
provides
a
two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Page 8 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE CE2
CE2 ADSP ADSC ADV WRITE OE
CLK
DQ
Deselected Cycle, Power-down None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
H
X
H
L
X
X
X
L-H
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
Partial Truth Table for READ/WRITE[10]
Function (1366)
GW
BWE
BWa
BWb
BWc
BWd
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQa
1
0
1
1
1
1
Write Byte 0 – DQb
1
0
1
1
0
1
Write Byte 1, 0
1
0
1
1
0
0
Write Byte 2 – DQc
1
0
1
0
1
1
Write Byte 2, 0
1
0
1
0
1
0
Write Byte 2, 1
1
0
1
0
0
1
Write Byte 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
0
0
1
1
1
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
5. All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.
7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
10. For the X18 product, There are only BWa and BWb.
Document #: 38-05264 Rev. *A
Page 9 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Partial Truth Table for READ/WRITE[10] (continued)
GW
BWE
BWa
BWb
BWc
BWd
Write Byte 3, 0
1
0
0
1
1
0
Write Byte 3, 1
1
0
0
1
0
1
Write Byte 3, 1, 0
1
0
0
1
0
0
Write Byte 3, 2
1
0
0
0
1
1
Write Byte 3, 2, 0
1
0
0
0
1
0
Write Byte 3, 2, 1
1
0
0
0
0
1
Write All Byte
1
0
0
0
0
0
Write All Byte
0
X
X
X
X
X
Function (1366)
Function (1367)
Read
Read
GW
BWE
BWb
BWa
1
1
X
x
1
0
1
1
Write Byte 0 – DQ [7:0] and DP0
1
0
1
0
Write Byte 0 – DQ [15:8] and DP1
1
0
0
1
Write All Byte
1
0
0
0
Write All Byte
0
X
X
X
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
Clock cycles are required to enter into or exit from this “sleep”
mode.
While in this mode, data integrity is guarantee. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep”
mode.CEs,ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ inputs returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode stand-by current
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/ LVCMOS logic level signaling.
Document #: 38-05264 Rev. *A
Min.
ZZ > VDD – 0.2V
2 tcyc
Max
Unit
10
mA
2 tcyc
ns
ns
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP)
TCK – Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Page 10 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
TMS – Test Mode Select (INPUT)
Bypass Register
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
TDI – Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register see Figure 1. It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up
internally, resulting in a logic HIGH level. TDI is connected to
the Most Significant Bit (MSB) of any register (see Figure 2).
TDO – Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the Least Significant Bit (LSB) of any register (see Figure 2).
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
Document #: 38-05264 Rev. *A
Boundary Scan Register
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name, the third column is the
TQFP pin number, and the fourth column is the BGA bump
number.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows IEEE 1149.1
conventions, it is not IEEE 1149.1-compliant because some of
the mandatory instructions are not fully implemented. The TAP
on this device may be used to monitor all input and I/O pads,
but can not be used to load address, data, or control signals
into the device or to preload the I/O buffers. In other words, the
device will not perform IEEE 1149.1 EXTEST, INTEST, or the
preload portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
Page 11 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1-mandatory
instruction. The PRELOAD portion of the command is not
implemented in this device, so the device TAP controller is not
fully IEEE 1149.1-compliant.
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
Document #: 38-05264 Rev. *A
Page 12 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
1
TEST-LOGIC
RESET
0
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05264 Rev. *A
Page 13 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register[12]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Test Conditions
Input High (Logic 1) Voltage[13, 14]
Voltage[13, 14]
Min.
Max.
Unit
2.0
VCC + 0.3
V
–0.3
0.8
V
–5.0
5.0
µA
VIl
Input Low (Logic 0)
ILI
Input Leakage Current
0V < VIN < VCC
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[13, 15]
IOLC = 100 µA
0.2
V
VOHC
LVCMOS Output High
Voltage[13, 15]
IOHC = 100 µA
VOLT
LVTTL Output Low Voltage[13]
VOHT
Voltage[13]
IOLT = 8.0 mA
VCC – 0.2
V
0.4
V
LVTTL Output High
IOHT = 8.0 mA
2.4
V
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All voltage referenced to VSS (GND).
14. Overshoot: VIH(AC) < VCC+1.5V for t2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature ..................................................+150°
Power Dissipation .........................................................1.0W
Range
Ambient
Temperature[18]
0°C to +70°C
Com’l
Ind’I
–40°C to +85°C
VCC
VCCQ
3.3V
–5%/+10%
2.5V-5%/3.3V
+10%
Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Input High (Logic 1) Voltage
Test Conditions
[13, 19]
VIHD
VIl
Input Low (Logic 0) Voltage[13, 19]
ILI
Input Leakage Current
MODE and ZZ Input Leakage
ILO
Output Leakage Current
VOH
VOL
Output High
Output Low Voltage[13]
VCC
Supply Voltage[13]
VCCQ
I/O Supply Voltage [13]
Max.
Unit
All Other Inputs
2.0
5+0.5
V
3.3V I/O
2.0
V
2.5V I/O
1.7
3.3V I/O
–0.3
0.8
V
2.5V
–0.3
0.7
5
µA
30
µA
5
µA
0V < VIN < VCC
IL
Voltage[13]
Min.
Current[20]
0V < VIN < VCC
–
Output(s) disabled, 0V < VOUT < VCC
IOH = –5.0 mA for 3.3V I/O
2.4
IOH = –1.0 mA for 2.5V I/O
2.0
V
IOL = 8.0 mA for 3.3V I/O
0.4
IOL = 1.0 mA for 2.5V I/O
0.4
V
3.135
3.465
V
3.3V I/O
3.135
3.465
V
2.5V I/O
2.375
2.9
V
Typ.
–4.4
225
MHz
ICC
Power Supply Current:
Operating[21, 22, 23]
Device selected; all inputs < VIL
or> VIH; cycle time > tKC min.;
VCC = Max.; outputs open
150
570
510
425
380
mA
ISB1
Automatic CE
Power-down Current—TTL
Inputs[22,23]
Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
CLK cycle time > tKC Min.
80
295
265
200
160
mA
ISB2
CMOS Standby[22, 23]
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
all inputs static; CLK frequency = 0
5
10
10
10
10
mA
ISB3
TTL Standby[22, 23]
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = MAX; CLK frequency = 0
15
30
30
30
30
mA
ISB4
Clock Running[22, 23]
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
CLK cycle time > tKC Min.
40
125
110
90
80
mA
Parameter
Description
Conditions
–5
200
MHz
–6
166
MHz
–6.7
150
MHz
Unit
Notes:
18. TA is the case temperature.
19. Overshoot: VIH < +6.0V for t < tKC /2.
Undershoot:VIL < –2.0V for t < tKC /2.
20. Output loading is specified with CL=5 pF as in AC Test Loads.
21. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
22. “Device Deselected” means the device is in power-down mode as defined in the truth table. “Device Selected” means the device is active.
23. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
Document #: 38-05264 Rev. *A
Page 19 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Capacitance[15]
Parameter
Description
CI
Test Conditions
Typ.
Max.
Unit
5
7
pF
7
8
pF
Input Capacitance
TA = 25°C, f = 1 MHz,
Input/Output Capacitance (DQ) VCC = 3.3V
CI/O
Thermal Resistance
Parameter
ΘJA
ΘJC
Description
Test Conditions
TQFP Typ.
Unit
25
°C/W
9
°C/W
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
4-layer PCB
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
317Ω
VCCQ
DQ
Z0 =50Ω
351Ω
0V
≤ 1.0 ns
≤ 1.0 ns
Vt = 1.5V
(a)
(c)
(b)
Switching Characteristics Over the Operating
90%
10%
90%
10%
50Ω
5 pF
Range[24]
-4.4
225 MHz
Parameter
ALL INPUT PULSES
VCCQ
DQ
Description
Min.
Max.
-5
200 MHz
Min.
Max.
-6
166 MHz
Min.
Max.
-6.7
150 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
4.4
5.0
6.0
6.7
ns
tKH
Clock HIGH Time
1.7
2.0
2.4
2.6
ns
tKL
Clock LOW Time
1.7
2.0
2.4
2.6
ns
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
2.8
3.0
3.5
3.5
ns
VCCQ = 2.5V
2.8
3.5
4.0
4.5
ns
tKQX
Clock to Output Invalid
tKQLZ
Clock to Output in Low-Z[15, 25, 26]
tKQHZ
Clock to Output in High-Z
[15, 25, 26]
tOEQ
OE to Output Valid[27]
tOELZ
OE to Output in Low-Z[15, 25, 26]
tOEHZ
High-Z[15, 25, 26]
1.25
1.25
1.25
1.25
ns
0
0
0
0
ns
1.25
VCCQ = 3.3V
1.25
2.8
VCCQ = 2.5V
OE to Output in
3.0
1.25
3.0
2.8
0
3.0
2.5
1.25
3.5
3.5
0
4.0
4.0
0
3.0
4.0
ns
3.5
ns
4.5
ns
ns
0
3.5
3.5
ns
Set-up Times
tS
Address, Controls, and Data In[28]
1.5
1.5
1.5
2.0
ns
Address, Controls, and Data In[28]
0.5
0.5
0.5
0.5
ns
Hold Times
tH
Notes:
24. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
25. Output loading is specified with CL = 5 pF as in (a) of AC Test Loads.
26. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
27. OE is a “Don’t Care” when a byte write enable is sampled LOW.
28. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “Don’t Care” as defined in the truth table.
Document #: 38-05264 Rev. *A
Page 20 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Typical Output Buffer Characteristics
Output High Voltage
Pull-up Current
Output Low Voltage
Pull-down Current
VOH(V)
IOH(mA) Min.
IOH(mA) Max.
VOL(V)
IOL(mA) Min.
IOL(mA) Max.
–0.5
–38
–105
–0.5
0
0
0
–38
–105
0
0
0
0.8
–38
–105
0.4
10
20
1.25
–26
–83
0.8
20
40
1.5
–20
–70
1.25
31
63
2.3
0
–30
1.6
40
80
2.7
0
–10
2.8
40
80
2.9
0
0
3.2
40
80
3.4
0
0
3.4
40
80
Switching Waveforms
Read Timing[29, 30]
tKC
tKL
CLK
CLK
tKH
tS
ADSP#
ADSP
tH
ADSC#
ADSC
tS
A
ADDRESS
BWa#,BW
BWb#,
x
BWc#,BWE
BWd#
BWE#, GW#
A1
A2
tH
tS
GW
CECE#
tS
ADV
ADV#
tH
OE#
OE
tKQ
DQx
DQ
tKQLZ
tOELZ
Q(A1)
SINGLE READ
tOEQ
tKQ
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
BURST READ
Notes:
29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
30. For the X18 product, there are only BWa and BWb for byte write control.
Document #: 38-05264 Rev. *A
Page 21 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Write Timing[29, 30]
CLK
CLK
tS
ADSP#
ADSP
tH
ADSC#
ADSC
tS
A1
ADDRESS
A
A2
A3
tH
BWa#, BWb#,
x
BWc#, BW
BWd#,
BWE#
BWE
GW#
GW
CE#
CE
tS
ADV#
ADV
tH
OE#
OE
tKQX
DQ
DQx
Q
tOEHZ
D(A1)
SINGLE WRITE
Document #: 38-05264 Rev. *A
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
BURST WRITE
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
BURST WRITE
Page 22 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Read/Write Timing[29, 30]
CLK
CLK
tS
ADSP
ADSP#
tH
ADSC
ADSC#
tS
A
ADDRESS
A1
x
BWa#, BW
BWb#,
BWc#, BWE
BWd#,
BWE#,
GW#
GW
A2
A3
A4
A5
tH
CE#
CE
ADV
ADV#
OE
OE#
DQx
DQ
Q(A1)
Single Reads
Document #: 38-05264 Rev. *A
Q(A2)
D(A3)
Single Write
Q(A4)
Q(A4+1)
Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Page 23 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
ZZ Mode Timing [31, 32]
CLK
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
31. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
32. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05264 Rev. *A
Page 24 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Ordering Information
Speed
(MHz)
225
200
166
150
225
200
166
150
Package
Name
Package Type
CY7C1366A-225AJC/
GVT71256C36T-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-225AC/
GVT71256C36TA-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-225BGC/
GVT71256C36B-4.4
BG119
CY7C1366A-200AJC/
GVT71256C36T-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-200AC/
GVT71256C36TA-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Ordering Code
Commercial
Commercial
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-200BGC/
GVT71256C36B-5
BG119
CY7C1366A-166AJC/
GVT71256C36T-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-166AC/
GVT71256C36TA-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-166BGC/
GVT71256C36B-6
BG119
CY7C1366A-150AJC/
GVT71256C36T-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-150AC/
GVT71256C36TA-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-150BGC/
GVT71256C36B-6.7
BG119
CY7C1367A-225AJC/
GVT71512C18T-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-225AC/
GVT71512C18TA-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-225BGC/
GVT71512C18B-4.4
BG119
CY7C1367A-200AJC/
GVT71512C18T-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-200AC/
GVT71512C18TA-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
119-Lead BGA (14 x 22 x 2.4 mm)
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-200BGC/
GVT715152C18B-5
BG119
CY7C1367A-166AJC/
GVT715152C18T-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-166AC/
GVT71512C18TA-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-166BGC/
GVT71512C18B-6
BG119
CY7C1367A-150AJC/
GVT71512C18T-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-150AC/
GVT71512C18TA-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-150BGC/
GVT71512C18B-6.7
BG119
Document #: 38-05264 Rev. *A
Operating
Range
119-Lead BGA (14 x 22 x 2.4 mm)
119-Lead BGA (14 x 22 x 2.4 mm)
Page 25 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Ordering Information (continued)
Speed
(MHz)
200
166
150
200
166
150
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C1366A-200AJCI/
GVT71256C36T-5I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial temp
CY7C1366A-200ACI/
GVT71256C36TA-5I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-200BGCI/
GVT71256C36B-5I
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-166AJCI/
GVT71256C36T-6I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-166ACI/
GVT71256C36TA-6I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-166BGCI/
GVT71256C36B-6I
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-150AJCI/
GVT71256C36T-6.7I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-150ACI/
GVT71256C36TA-6.7I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-150BGCI/
GVT71256C36B-6.7I
BG119
CY7C1367A-200AJCI/
GVT71512C18T-5I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-200ACI/
GVT71512C18TA-5I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-200BGCI/
GVT715152C18B-5I
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-166AJCI/
GVT715152C18T-6I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-166ACI/
GVT71512C18TA-6I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-166BGCI/
GVT71512C18B-6I
BG119
CY7C1367A-150AJC/
GVT71512C18T-6.7I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-150ACI/
GVT71512C18TA-6.7I
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-150BGCI/
GVT71512C18B-6.7I
BG119
Document #: 38-05264 Rev. *A
119-Lead BGA (14 x 22 x 2.4 mm)
119-Lead BGA (14 x 22 x 2.4 mm)
Page 26 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05264 Rev. *A
Page 27 of 29
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Pentium is a registered trademark, and i486 is a trademark, of Intel Corporation. All product and company names mentioned in
this document are the trademarks of their respective holders.
Document #: 38-05264 Rev. *A
Page 28 of 29
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Document History Page
Document Title: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined
SRAM
Document Number: 38-05264
REV.
ECN No.
Issue Date
Orig. of
Change
**
114117
04/26/02
KKV
New Data Sheet
**
125245
03/19/03
IXR
Changed tKQ, tKQX, tKQLZ, tKHZ, tOEQ, tOELZ, tOEHZ.
Document #: 38-05264 Rev. *A
Description of Change
Page 29 of 29
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