CY7C1370SV25
CY7C1372SV25
18-Mbit (512K × 36/1M × 18)
Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 200 MHz bus operations with zero wait states
❐ Available speed grades are 200, and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte Write capability
■
Single 2.5 V core power supply (VDD)
■
2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 3.0 ns (for 200 MHz device)
■
Clock Enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
CY7C1370SV25 available in JEDEC-standard Pb-free 100-pin
TQFP and non-Pb-free 165-ball FBGA packages and
CY7C1372SV25 available in JEDEC-standard Pb-free 100-pin
TQFP
The CY7C1370SV25 and CY7C1372SV25 are 2.5 V, 512K × 36
and 1M × 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations with
no wait states. The CY7C1370SV25 and CY7C1372SV25 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent Write/Read
transitions. The CY7C1370SV25 and CY7C1372SV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
Burst capability – linear or interleaved burst order
■
“ZZ” Sleep Mode option and Stop Clock option
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370SV25 and BWa–BWb for
CY7C1372SV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. To avoid bus contention,
the output drivers are synchronously three-stated during the data
portion of a write sequence.
Logic Block Diagram – CY7C1370SV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
MEMORY
ARRAY
WRITE
DRIVERS
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document Number: 001-43827 Rev. *G
O
U
T
P
U
T
D
A
T
A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 18, 2016
CY7C1370SV25
CY7C1372SV25
Logic Block Diagram – CY7C1372SV25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
BURST A0'
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document Number: 001-43827 Rev. *G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Page 2 of 29
CY7C1370SV25
CY7C1372SV25
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 7
Single Write Accesses ................................................. 7
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Write Cycle Description ..................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Document Number: 001-43827 Rev. *G
Scan Register Sizes ....................................................... 17
Identification Register Definitions ................................ 17
Identification Codes ....................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Page 3 of 29
CY7C1370SV25
CY7C1372SV25
Selection Guide
Description
200 MHz
167 MHz
Unit
3.0
300
70
3.4
275
70
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1372SV25
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC(36)
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC(72)
A
A
A
A
A
A
A
NC(36)
NC(72)
VSS
VDD
NC(288)
NC(144)
MODE
A
A
A
A
A1
A0
Document Number: 001-43827 Rev. *G
NC
NC
NC
VSS
VDD
(512K × 36)
DQPb
DQb
DQb
VDDQ
VSS
NC(288)
NC(144)
CY7C1370SV25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 29
CY7C1370SV25
CY7C1372SV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1370SV25 (512K × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWc
BWb
CE3
ADV/LD
A
A
NC
BWa
VSS
CLK
CEN
WE
OE
A
A
NC
VSS
VSS
VSS
VDD
VDDQ
DQPb
DQb
R
MODE
NC/1G
A
CE2
DQPc
DQc
NC
DQc
VDDQ
VDDQ
BWd
VSS
VDD
VSS
VSS
VSS
VDDQ
NC
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
NC
DQd
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
DQb
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
DQc
NC
DQd
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
NC/36M
Document Number: 001-43827 Rev. *G
Page 5 of 29
CY7C1370SV25
CY7C1372SV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK.
BWa, BWb,
BWc, BWd
InputByte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
Synchronous on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls
DQc and DQPc, BWd controls DQd and DQPd.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be driven
LOW to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
OE
InputOutput Enable, Active LOW. Combined with the synchronous logic block inside the device to control
Asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data
portion of a write sequence, during the first clock when emerging from a deselected state and when
the device has been deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
DQS
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE defaults to HIGH, to an interleaved burst order.
TDO
JTAG serial Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
output
Synchronous
TDI
JTAG serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
input
Synchronous
TMS
Test Mode
This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Select
Synchronous
Document Number: 001-43827 Rev. *G
Page 6 of 29
CY7C1370SV25
CY7C1372SV25
Pin Definitions (continued)
Pin Name
TCK
VDD
VDDQ
I/O Type
JTAG-Clock
Pin Description
Clock Input to the JTAG Circuitry.
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for the I/O Circuitry.
VSS
Ground
NC
–
No Connects. This pin is not connected to the die.
NC/(36M,
72M,
144M,
288M,
576M, 1G)
–
These Pins are Not Connected. They are used for expansion to the 36M, 72M, 144M, 288M, 576M,
and 1G densities.
ZZ
Ground for the Device. Should be connected to ground of the system.
InputZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
Asynchronous data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull down.
Functional Overview
The
CY7C1370SV25
and
CY7C1372SV25
are
synchronous-pipelined Burst NoBL SRAMs designed
specifically to eliminate wait states during Write/Read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 3.0 ns (200-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the Write Enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core and
control logic. The control logic determines that a read access is
in progress and allows the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
Document Number: 001-43827 Rev. *G
register and onto the data bus within 3.0 ns (200-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (Read/Write/Deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output tri-states following the next clock rise.
Burst Read Accesses
The CY7C1370SV25 and CY7C1372SV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (Read or Write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the Control
Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370SV25 and DQa,b/DQPa,b for
CY7C1372SV25). In addition, the address for the subsequent
Page 7 of 29
CY7C1370SV25
CY7C1372SV25
CY7C1370SV25 and BWa,b for CY7C1372SV25) inputs must be
driven in each cycle of the burst write to write the correct bytes
of data.
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370SV25 & DQa,b/DQPa,b for
CY7C1372SV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the write is complete.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370SV25 and BWa,b for CY7C1372SV25)
signals. The CY7C1370SV25/CY7C1372SV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input selectively writes to only the desired
bytes. Bytes not selected during a byte write operation remains
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte write capability
has been included to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write
operations.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Because the CY7C1370SV25 and CY7C1372SV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370SV25 and DQa,b/DQPa,b for
CY7C1372SV25) inputs. Doing so three-states the output
drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370SV25 and DQa,b/DQPa,b for
CY7C1372SV25) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
Burst Write Accesses
The CY7C1370SV25/CY7C1372SV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in the Single Write Access section. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BW (BWa,b,c,d for
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Min
Max
Unit
IDDZZ
Parameter
Sleep mode standby current
Description
ZZ VDD 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ VDD 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-43827 Rev. *G
Test Conditions
Page 8 of 29
CY7C1370SV25
CY7C1372SV25
Truth Table
The Truth Table for CY7C1370SV25 and CY7C1372SV25 are as follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L–H
Tri-state
Continue Deselect Cycle
None
X
L
H
X
X
X
L
L–H
Tri-state
Read Cycle (Begin Burst)
External
L
L
L
H
X
L
L
L–H Data Out (Q)
Read Cycle (Continue Burst)
Next
X
L
H
X
X
L
L
L–H Data Out (Q)
NOP/Dummy Read (Begin Burst)
External
L
L
L
H
X
H
L
L–H
Tri-state
Dummy Read (Continue Burst)
Next
X
L
H
X
X
H
L
L–H
Tri-state
Write Cycle (Begin Burst)
External
L
L
L
L
L
X
L
L–H
Data In (D)
Write Cycle (Continue Burst)
Next
X
L
H
X
L
X
L
L–H
Data In (D)
NOP/Write Abort (Begin Burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
Write Abort (Continue Burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
Ignore Clock Edge (Stall)
Current
X
L
X
X
X
X
H
L–H
–
Sleep Mode
None
X
H
X
X
X
X
X
X
Tri-state
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Truth Table for details.
2. Write is defined by WE and BWX. See Truth Table for details.
3. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when OE
is inactive or when the device is deselected, and DQs = data when OE is active.
Document Number: 001-43827 Rev. *G
Page 9 of 29
CY7C1370SV25
CY7C1372SV25
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1370SV25 and CY7C1372SV25 are as follows. [8, 9, 10, 11]
Function (CY7C1370SV25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1372SV25)
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Truth Table on page 9 for details.
9. Write is defined by WE and BWX. See Truth Table on page 9 for details.
10. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-43827 Rev. *G
Page 10 of 29
CY7C1370SV25
CY7C1372SV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370SV25 incorporates a serial boundary scan test
access port (TAP).This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
The CY7C1370SV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power up, the device is up in
a reset state which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Document Number: 001-43827 Rev. *G
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Identification Codes on page 17. Three of these instructions are
listed as RESERVED and should not be used. The other five
instructions are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
Page 11 of 29
CY7C1370SV25
CY7C1372SV25
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
Document Number: 001-43827 Rev. *G
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 29
CY7C1370SV25
CY7C1372SV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-43827 Rev. *G
Page 13 of 29
CY7C1370SV25
CY7C1372SV25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
. 2 1 0
Selection
Circuitry
TDO
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 001-43827 Rev. *G
UNDEFINED
Page 14 of 29
CY7C1370SV25
CY7C1372SV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 001-43827 Rev. *G
Page 15 of 29
CY7C1370SV25
CY7C1372SV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
50Ω
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
TDO
Test load termination supply voltage .......................... 1.25 V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [14]
Min
Max
Unit
VOH1
Output HIGH Voltage
Description
IOH = –1.0 mA, VDDQ = 2.5 V
Test Conditions
2.0
–
V
VOH2
Output HIGH Voltage
IOH = –100 µA, VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW Voltage
IOL = 8.0 mA, VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 2.5 V
–
0.2
V
VIH
Input HIGH Voltage
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 2.5 V
–0.3
0.7
V
IX
Input Load Current
–5
5
µA
GND < VIN < VDDQ
Note
14. All voltages referenced to VSS (GND)
Document Number: 001-43827 Rev. *G
Page 16 of 29
CY7C1370SV25
CY7C1372SV25
Scan Register Sizes
Register Name
Bit Size (× 18)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
Identification Register Definitions
Instruction Field
CY7C1370SV25
Revision Number (31:29)
000
Cypress Device ID (28:12)
01011001000100101
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Description
Reserved for version number.
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-43827 Rev. *G
Page 17 of 29
CY7C1370SV25
CY7C1372SV25
Boundary Scan Order
165-ball FBGA [15, 16]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Notes
15. Balls which are NC (No Connect) are pre-set LOW.
16. Bit# 89 is pre-set HIGH.
Document Number: 001-43827 Rev. *G
Page 18 of 29
CY7C1370SV25
CY7C1372SV25
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Current into Outputs (LOW) ........................................ 20 mA
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD relative to GND .......–0.5 V to +3.6 V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up Current ................................................... > 200 mA
Operating Range
Supply Voltage on VDDQ relative to GND ..... –0.5 V to +VDD
DC to Outputs in Tri-State .................–0.5 V to VDDQ + 0.5 V
Range
Commercial
Ambient
Temperature
VDD/VDDQ
0 °C to +70 °C
2.5 V ± 5%
Electrical Characteristics
Over the Operating Range
Parameter [17, 18]
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
for 2.5 V I/O
VOH
Output HIGH Voltage
for 2.5 V I/O, IOH = 1.0 mA
VOL
Output LOW Voltage
for 2.5 V I/O, IOL= 1.0 mA
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
2.0
–
V
–
0.4
V
VIH
Input HIGH Voltage
[19]
for 2.5 V I/O
1.7
VDD + 0.3
V
VIL
Input LOW Voltage [19]
for 2.5 V I/O
–0.3
0.7
V
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input Current of ZZ
IOZ
IDD
[20]
ISB1
Input = VSS
Input = VDD
–
30
A
Output Leakage Current
GND VI VDD, Output Disabled
–5
5
A
VDD Operating Supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle,
200 MHz
–
300
mA
6.0-ns cycle,
167 MHz
–
275
mA
5.0-ns cycle,
200 MHz
–
150
mA
6.0-ns cycle,
167 MHz
–
140
mA
Automatic CE Power down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
ISB2
Automatic CE Power down
Current – CMOS Inputs
Max. VDD, Device Deselected, All speed
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f=0
–
70
mA
ISB3
Automatic CE Power down
Current – CMOS Inputs
Max. VDD, Device Deselected, 5.0-ns cycle,
VIN 0.3 V or VIN > VDDQ 0.3 V, 200 MHz
f = fMAX = 1/tCYC
6.0-ns cycle,
167 MHz
–
130
mA
–
125
mA
–
80
mA
ISB4
Automatic CE Power down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL, f = 0
All speed
grades
Notes
17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
18. TPower up: Assumes a linear ramp from 0 V to VDD (min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
19. Tested initially and after any design or process change that may affect these parameters.
20. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-43827 Rev. *G
Page 19 of 29
CY7C1370SV25
CY7C1372SV25
Capacitance
Parameter [21]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
5
9
pF
5
9
pF
5
9
pF
Thermal Resistance
Parameter [21]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
28.66
20.7
C/W
4.08
4.0
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
21. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-43827 Rev. *G
Page 20 of 29
CY7C1370SV25
CY7C1372SV25
Switching Characteristics
Over the Operating Range
Parameter [22, 23]
Description
-200
-167
Unit
Min
Max
Min
Max
VCC(typical) to the first access read or write
1
–
1
–
ms
tCYC
Clock Cycle Time
5
–
6
–
ns
FMAX
Maximum Operating Frequency
–
200
–
167
MHz
tCH
Clock HIGH
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.2
–
ns
–
3.0
–
3.4
ns
tPower[24]
Clock
Output Times
tCO
Data Output Valid After CLK Rise
tEOV
OE LOW to Output Valid
tDOH
Data Output Hold After CLK Rise
tCHZ
tCLZ
Clock to High Z
[25, 26, 27]
Clock to Low Z
[25, 26, 27]
[25, 26, 27]
tEOHZ
OE HIGH to Output High Z
tEOLZ
OE LOW to Output Low Z [25, 26, 27]
–
3.0
–
3.4
ns
1.3
–
1.3
–
ns
–
3.0
–
3.4
ns
1.3
–
1.3
–
ns
–
3.0
–
3.4
ns
0
–
0
–
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.4
–
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.4
–
1.5
–
ns
tCENS
CEN Setup Before CLK Rise
1.4
–
1.5
–
ns
tWES
WE, BWx Setup Before CLK Rise
1.4
–
1.5
–
ns
tALS
ADV/LD Setup Before CLK Rise
1.4
–
1.5
–
ns
tCES
Chip Select Setup
1.4
–
1.5
–
ns
tAH
Address Hold After CLK Rise
0.4
–
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.4
–
0.5
–
ns
tCENH
CEN Hold After CLK Rise
0.4
–
0.5
–
ns
tWEH
WE, BWx Hold After CLK Rise
0.4
–
0.5
–
ns
tALH
ADV/LD Hold after CLK Rise
0.4
–
0.5
–
ns
tCEH
Chip Select Hold After CLK Rise
0.4
–
0.5
–
ns
Hold Times
Notes
22. Timing reference 1.25 V when VDDQ = 2.5 V.
23. Test conditions shown in (a) of Figure 4 on page 20 unless otherwise noted.
24. This part has a voltage regulator internally; tPower is the time power is supplied above VDD(minimum) initially, before a Read or Write operation can be initiated.
25. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 4 on page 20. Transition is measured ±200 mV from steady-state voltage.
26. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
27. This parameter is sampled and not 100% tested.
Document Number: 001-43827 Rev. *G
Page 21 of 29
CY7C1370SV25
CY7C1372SV25
Switching Waveforms
Figure 5. Read/Write/Timing [28, 29, 30]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
28. For this waveform ZZ is tied LOW.
29. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
30. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-43827 Rev. *G
Page 22 of 29
CY7C1370SV25
CY7C1372SV25
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles [31, 32, 33]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 7. ZZ Mode Timing [34, 35]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
31. For this waveform ZZ is tied LOW.
32. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
33. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
34. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
35. IOs are in High Z when exiting ZZ sleep mode.
Document Number: 001-43827 Rev. *G
Page 23 of 29
CY7C1370SV25
CY7C1372SV25
Ordering Information
The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales
representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products.
Speed(
MHz)
167
Ordering Code
CY7C1370SV25-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
CY7C1372SV25-167AXC
200
CY7C1370SV25-167BZC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
CY7C1370SV25-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7
C 137X S V25 - XXX XX X
C
Temperature Range:
C = Commercial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Frequency Range: XXX = 167 MHz or 200 MHz
V25 = 2.5 V
Die Revision
Part Identifier: 137X = 1370 or 1372
1370 = PL, 512Kb × 36 (18 Mb)
1372 = PL, 1Mb × 18 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-43827 Rev. *G
Page 24 of 29
CY7C1370SV25
CY7C1372SV25
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-43827 Rev. *G
Page 25 of 29
CY7C1370SV25
CY7C1372SV25
Package Diagrams (continued)
Figure 9. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-43827 Rev. *G
Page 26 of 29
CY7C1370SV25
CY7C1372SV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
JTAG
Joint Test Action Group
mA
milliampere
LSB
Least Significant Bit
mm
millimeter
MSB
Most Significant Bit
ms
millisecond
OE
Output Enable
mV
millivolt
SRAM
Static Random Access Memory
ns
nanosecond
TAP
Test Access Port
TCK
Test Clock
TMS
Test Mode Select
TDI
Test Data-In
TDO
Test Data-Out
TQFP
Thin Quad Flat Pack
WE
Write Enable
Document Number: 001-43827 Rev. *G
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 27 of 29
CY7C1370SV25
CY7C1372SV25
Document History Page
Document Title: CY7C1370SV25/CY7C1372SV25, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-43827
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1898286
See ECN
VKN /
AESA
New data sheet.
*A
2082246
See ECN
JASM
Changed status from Preliminary to Final.
Description of Change
*B
2946521
06/07/2010
FSU
Updated Ordering Information (Removed unavailable parts).
*C
3052712
10/11/2010
NJY
Updated Ordering Information (Removed obsolete parts).
*D
3218966
04/07/2011
NJY
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*E
3569737
04/02/2012
PRIT
Updated Features (Removed 250 MHz frequency related information, removed
119-ball BGA package related information).
Updated Selection Guide (Removed 250 MHz frequency related information).
Updated Pin Configurations (Removed 119-ball BGA package related
information, removed CY7C1372SV25 related information in Figure 2).
Updated Functional Overview (Removed 250 MHz frequency related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1372SV25 related information).
Updated Scan Register Sizes (Removed 119-ball BGA package related
information and also removed Bit Size (× 36) column).
Updated Identification Register Definitions (Removed CY7C1372SV25 related
information).
Updated Boundary Scan Order (Removed 119-ball BGA package related
information).
Updated Operating Range (Removed Industrial temperature range related
information).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Switching Characteristics (Removed 250 MHz frequency related
information).
Updated Package Diagrams (Removed 119-ball BGA package related
information).
*F
3957732
04/08/2013
PRIT
Updated Package Diagrams:
spec 51-85180 – Changed revision from *E to *F.
Completing Sunset Review.
*G
5181234
03/18/2016
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 001-43827 Rev. *G
Page 28 of 29
CY7C1370SV25
CY7C1372SV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43827 Rev. *G
Revised March 18, 2016
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
Page 29 of 29
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