CY7C1370KV25
CY7C1372KV25
18-Mbit (512K × 36/1M × 18)
Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Features
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 200-MHz bus operations with zero wait states
❐ Available speed grades are 200 and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte write capability
■
Single 2.5 V core power supply (VDD)
■
2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 3.2 ns (for 200-MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
Available in JEDEC-standard Pb-free 100-pin TQFP, and non
Pb-free 165-ball FBGA packages
■
IEEE 1149.1 JTAG-compatible boundary scan
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option and stop clock option
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370KV25 and CY7C1372KV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1370KV25 and CY7C1372KV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370KV25 and BWa–BWb for
CY7C1372KV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Functional Description
The CY7C1370KV25 and CY7C1372KV25 are 2.5 V, 512K × 36
and 1M × 18 synchronous pipelined burst SRAMs with No Bus
Selection Guide
Description
Maximum access time
× 18
× 36
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-97851 Rev. *G
•
198 Champion Court
•
200 MHz
167 MHz
Unit
3.0
158
178
3.4
143
163
ns
San Jose, CA 95134-1709
mA
•
408-943-2600
Revised March 3, 2017
CY7C1370KV25
CY7C1372KV25
Logic Block Diagram – CY7C1370KV25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
WRITE
DRIVERS
MEMORY
ARRAY
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
A
M
P
S
WE
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
E
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1372KV25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Document Number: 001-97851 Rev. *G
Page 2 of 30
CY7C1370KV25
CY7C1372KV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ........................................................................ 9
Partial Truth Table for Read/Write ................................ 10
Partial Truth Table for Read/Write ................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
Document Number: 001-97851 Rev. *G
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Scan Register Sizes ....................................................... 17
Identification Register Definitions ................................ 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC® Solutions ...................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Page 3 of 30
CY7C1370KV25
CY7C1372KV25
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1372KV25
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC(36)
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC(72)
NC
NC
NC
VSS
VDD
A
A
A
A
A
A
A
NC(36)
NC(72)
VSS
VDD
NC(288)
NC(144)
MODE
A
A
A
A
A1
A0
Document Number: 001-97851 Rev. *G
DQPb
DQb
DQb
VDDQ
VSS
NC(288)
NC(144)
CY7C1370KV25
(512K × 36)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) Pinout
Page 4 of 30
CY7C1370KV25
CY7C1372KV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) Pinout, CY7C1370KV25 (512K x 36)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWc
BWb
CE3
NC/1G
A
CE2
DQPc
DQc
NC
DQc
BWa
VSS
VDDQ
BWd
VSS
VDD
R
MODE
VDDQ
7
8
9
10
11
A
A
NC
CLK
CEN
WE
ADV/LD
OE
A
A
NC
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
NC/36M
Document Number: 001-97851 Rev. *G
Page 5 of 30
CY7C1370KV25
CY7C1372KV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Inputsynchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the
CLK.
BWa, BWb,
BWc, BWd
Inputsynchronous
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls
DQc and DQPc, BWd controls DQd and DQPd.
WE
Inputsynchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Inputsynchronous
Advance/load input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1
Inputsynchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
Inputsynchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
Inputsynchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
Inputasynchronous
Output enable, active LOW. Combined with the synchronous logic block inside the device to control
the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the
data portion of a write sequence, during the first clock when emerging from a deselected state and
when the device has been deselected.
CEN
Inputsynchronous
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
DQS
I/Osynchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
DQPX
I/Osynchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input strap pin
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation. When
left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial output
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
synchronous
Document Number: 001-97851 Rev. *G
Page 6 of 30
CY7C1370KV25
CY7C1372KV25
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TDI
JTAG serial input
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
synchronous
TMS
Test mode select
This pin controls the Test access port state machine. Sampled on the rising edge of TCK.
synchronous
TCK
VDD
VDDQ
JTAG-clock
Power supply
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
I/O power supply Power supply for the I/O circuitry.
VSS
Ground
NC
–
No connects. This pin is not connected to the die.
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M, and 1G densities.
Inputasynchronous
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
ZZ
Ground for the device. Should be connected to ground of the system.
Functional Overview
The
CY7C1370KV25
and
CY7C1372KV25
are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.2 ns
(200-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.2 ns (200-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will three-state following the next clock rise.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Document Number: 001-97851 Rev. *G
Page 7 of 30
CY7C1370KV25
CY7C1372KV25
Burst Read Accesses
The CY7C1370KV25 and CY7C1372KV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load a
new address into the SRAM, as described in Single Read
Accesses. The sequence of the burst counter is determined by
the MODE input signal. A LOW input on MODE selects a linear
burst mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (read
or write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV25 and DQa,b/DQPa,b for
CY7C1372KV25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV25 & DQa,b/DQPa,b for
CY7C1372KV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370KV25 and BWa,b for CY7C1372KV25)
signals. The CY7C1370KV25/CY7C1372KV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
Document Number: 001-97851 Rev. *G
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1370KV25 and CY7C1372KV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV25 and DQa,b/DQPa,b for
CY7C1372KV25) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV25 and DQa,b/DQPa,b for
CY7C1372KV25) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1370KV25/CY7C1372KV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in Single Write Accesses on page 8.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1370KV25 and BWa,b for CY7C1372KV25) inputs must
be driven in each cycle of the burst write in order to write the
correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Page 8 of 30
CY7C1370KV25
CY7C1372KV25
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
01
00
Fourth
Address
A1:A0
10
11
00
01
10
11
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ VDD 0.2 V
–
65
mA
tZZS
Device operation to ZZ
ZZ VDD 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Truth Table
The truth table for CY7C1370KV25/CY7C1372KV25 follows.[1, 2, 3, 4, 5, 6, 7, 8]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
H
L
L
X
X
X
L
L–H
Tri-state
Continue deselect cycle
None
X
L
H
X
X
X
L
L–H
Tri-state
Read cycle (begin burst)
External
L
L
L
H
X
L
L
L–H
Data out (Q)
Next
X
L
H
X
X
L
L
L–H
Data out (Q)
External
L
L
L
H
X
H
L
L–H
Tri-state
Next
X
L
H
X
X
H
L
L–H
Tri-state
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/write abort (begin burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
Write abort (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tri-state
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Ignore clock edge (stall)
Sleep mode
Document Number: 001-97851 Rev. *G
Page 9 of 30
CY7C1370KV25
CY7C1372KV25
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1370KV25 follows.[9, 10, 11, 12]
Function (CY7C1370KV25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write byte a – (DQa and DQPa)
L
H
H
H
L
Write byte b – (DQb and DQPb)
L
H
H
L
H
Write bytes b, a
L
H
H
L
L
Write byte c – (DQc and DQPc)
L
H
L
H
H
Write bytes c, a
L
H
L
H
L
Write bytes c, b
L
H
L
L
H
Write bytes c, b, a
L
H
L
L
L
Write byte d – (DQd and DQPd)
L
L
H
H
H
Write bytes d, a
L
L
H
H
L
Write bytes d, b
L
L
H
L
H
Write bytes d, b, a
L
L
H
L
L
Write bytes d, c
L
L
L
H
H
Write bytes d, c, a
L
L
L
H
L
Write bytes d, c, b
L
L
L
L
H
Write all bytes
L
L
L
L
L
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1372KV25 follows.[9, 10, 11, 12]
Function (CY7C1372KV25)
WE
BWb
BWa
Read
H
x
x
Write – no bytes written
L
H
H
Write byte a – (DQa and DQPa)
L
H
L
Write byte b – (DQb and DQPb)
L
L
H
Write both bytes
L
L
L
Notes
9. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
10. Write is defined by WE and BWX. See Truth Table on page 9 for details.
11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
12. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 001-97851 Rev. *G
Page 10 of 30
CY7C1370KV25
CY7C1372KV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Registers
The CY7C1370KV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Disabling the JTAG Feature
Instruction Register
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The CY7C1370KV25 incorporates a serial boundary scan test
access port (TAP).This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 2.5 V I/O logic levels.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Document Number: 001-97851 Rev. *G
Page 11 of 30
CY7C1370KV25
CY7C1372KV25
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Document Number: 001-97851 Rev. *G
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 30
CY7C1370KV25
CY7C1372KV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-97851 Rev. *G
Page 13 of 30
CY7C1370KV25
CY7C1372KV25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
. 2 1 0
Selection
Circuitry
TDO
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 001-97851 Rev. *G
UNDEFINED
Page 14 of 30
CY7C1370KV25
CY7C1372KV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter[13, 14]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Set-up Times
Hold Times
Notes
13. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 001-97851 Rev. *G
Page 15 of 30
CY7C1370KV25
CY7C1372KV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time (Slew Rate).............................. 2 V/ns
50Ω
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
TDO
Test load termination supply voltage .......................... 1.25 V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter[15]
Min
Max
Unit
VOH1
Output HIGH voltage
Description
IOH = –1.0 mA, VDDQ = 2.5 V
Test Conditions
2.0
–
V
VOH2
Output HIGH voltage
IOH = –100 µA, VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW voltage
IOL = 8.0 mA, VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW voltage
VIH
Input HIGH voltage
VIL
Input LOW voltage
IX
Input load current
IOL = 100 µA
GND < VIN < VDDQ
VDDQ = 2.5 V
–
0.2
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
15. All voltages referenced to VSS (GND).
Document Number: 001-97851 Rev. *G
Page 16 of 30
CY7C1370KV25
CY7C1372KV25
Scan Register Sizes
Register Name
Bit Size (× 18)
Instruction
3
Bypass
1
ID
32
Boundary scan order (165-ball FBGA package)
89
Identification Register Definitions
Instruction Field
CY7C1370KV25
Revision number (31:29)
000
Cypress device ID (28:12)
01011001000010101
Cypress JEDEC ID (11:1)
00000110100
ID register presence (0)
1
Description
Reserved for version number.
Reserved for future use.
Allows unique identification of SRAM
vendor.
Indicate the presence of an ID register.
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
Document Number: 001-97851 Rev. *G
Page 17 of 30
CY7C1370KV25
CY7C1372KV25
Boundary Scan Order
165-ball FBGA[16, 17]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
29
F10
59
E1
89
Internal
30
E10
60
F1
Notes
16. Balls which are NC (No Connect) are pre-set LOW.
17. Bit# 89 is pre-set HIGH.
Document Number: 001-97851 Rev. *G
Page 18 of 30
CY7C1370KV25
CY7C1372KV25
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Commercial
Storage temperature ................................ –65 °C to +150 °C
Industrial
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Range
Ambient Temperature
VDD/VDDQ
0 °C to +70 °C
2.5 V ± 5%
–40 °C to +85 °C
Neutron Soft Error Immunity
Parameter
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
Description
Test
Conditions Typ Max*
Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
2001 V
LMBU
Logical
Multi-Bit Upsets
25 °C
0
0.01 FIT/ Mb
Latch-up current .................................................... > 200 mA
SEL
Single
Event
Latch up
85 °C
0
0.1 FIT/ Dev
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
5
FIT/ Mb
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Document Number: 001-97851 Rev. *G
Page 19 of 30
CY7C1370KV25
CY7C1372KV25
Electrical Characteristics
Over the Operating Range
Parameter[18, 19]
Description
Test Conditions
Min
Max
Unit
–
2.375
2.625
V
2.375
VDD
V
2.0
–
V
–
0.4
V
VDD
Power supply voltage
VDDQ
I/O supply voltage
for 2.5 V I/O
VOH
Output HIGH voltage
for 2.5 V I/O, IOH = 1.0 mA
VOL
Output LOW voltage
for 2.5 V I/O, IOL= 1.0 mA
[18]
for 2.5 V I/O
1.7
VDD + 0.3 V
V
[18]
for 2.5 V I/O
–0.3
0.7
V
–5
5
Input = VSS
–30
–
Input = VDD
–
5
Input = VSS
–5
–
Input = VDD
–
30
GND VI VDD, output disabled
–5
5
5-ns cycle, × 18
200 MHz
× 36
–
158
–
178
6-ns cycle, × 18
167 MHz
× 36
–
143
–
163
× 18
–
75
× 36
–
80
× 18
–
75
× 36
–
80
× 18
Automatic
CE Max. VDD, Device Deselected,
All
speed
Power-down Current – VIN 0.3 V or VIN > VDDQ 0.3 grades
× 36
V, f = 0
CMOS Inputs
–
65
ISB2
–
70
× 18
–
75
ISB3
5-ns cycle,
Automatic
CE Max. VDD, Device Deselected, 200 MHz
Power-down Current – VIN 0.3 V or VIN > VDDQ 0.3 V,
6-ns cycle,
f = fMAX = 1/tCYC
CMOS Inputs
167 MHz
× 36
–
80
× 18
–
75
× 36
–
80
× 18
Automatic
CE
Max. VDD, Device Deselected, All
speed
Power-down Current –
grades
VIN VIH or VIN VIL, f = 0
× 36
TTL Inputs
–
65
–
70
VIH
VIL
Input HIGH voltage
Input LOW voltage
Input leakage current exGND VI VDDQ
cept ZZ and MODE
IX
Input current of MODE
Input current of ZZ
IOZ
IDD
ISB1
ISB4
Output leakage current
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5-ns cycle,
Automatic
CE Max. VDD, Device Deselected, 200 MHz
Power-down Current – VIN VIH or VIN VIL,
6-ns cycle,
f = fMAX = 1/tCYC
TTL Inputs
167 MHz
A
A
mA
mA
mA
mA
mA
Notes
18. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
19. TPower-up: Assumes a linear ramp from 0 V to VDD(min) of at least 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-97851 Rev. *G
Page 20 of 30
CY7C1370KV25
CY7C1372KV25
Capacitance
Parameter
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
5
TA = 25 C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
5
pF
5
5
pF
5
5
pF
Thermal Resistance
Parameter
Description
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
With Still Air (0 m/s)
37.95
17.34
C/W
With Air Flow (1 m/s)
Test conditions follow standard test
methods and procedures for With Air Flow (3 m/s)
Thermal resistance measuring thermal impedance,
per EIA/JESD51.
(junction to board)
-Thermal resistance
(junction to case)
33.19
14.33
C/W
30.44
12.63
C/W
24.07
8.95
C/W
8.36
3.50
C/W
Thermal resistance
(junction to ambient)
JA
JB
JC
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
Z0 = 50
10%
R = 1538
VT = 1.25 V
Document Number: 001-97851 Rev. *G
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
(b)
1 ns
1 ns
(c)
Page 21 of 30
CY7C1370KV25
CY7C1372KV25
Switching Characteristics
Over the Operating Range
Parameter[20, 21]
Description
-200
-167
Unit
Min
Max
Min
Max
VCC(typical) to the first access read or write
1
–
1
–
tCYC
Clock cycle time
5
–
6
–
ns
FMAX
Maximum operating frequency
–
200
–
167
MHz
tCH
Clock HIGH
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.2
–
ns
tPower[22]
ms
Clock
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.4
ns
tEOV
OE LOW to output valid
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.5
–
1.5
–
ns
Z[23, 24, 25]
tCHZ
Clock to high
tCLZ
Clock to low Z[23, 24, 25]
tEOHZ
tEOLZ
OE HIGH to output high
OE LOW to output low
Z[23, 24, 25]
Z[23, 24, 25]
–
3.0
–
3.4
ns
1.3
–
1.5
–
ns
–
3.0
–
3.4
ns
0
–
0
–
ns
Set-up Times
tAS
Address set-up before CLK rise
1.4
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.4
–
1.5
–
ns
tCENS
CEN set-up before CLK rise
1.4
–
1.5
–
ns
tWES
WE, BWx set-up before CLK rise
1.4
–
1.5
–
ns
tALS
ADV/LD set-up before CLK rise
1.4
–
1.5
–
ns
tCES
Chip select set-up
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.4
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.4
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.4
–
0.5
–
ns
tCEH
Chip select hold after CLK rise
0.4
–
0.5
–
ns
Hold Times
Notes
20. Timing reference 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.
22. This part has a voltage regulator internally; tPower is the time power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated.
23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 4 on page 21. Transition is measured ± 200 mV from steady-state voltage.
24. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 001-97851 Rev. *G
Page 22 of 30
CY7C1370KV25
CY7C1372KV25
Switching Waveforms
Figure 5. Read/Write Cycle Timing[26, 27, 28]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCL
tCH
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-97851 Rev. *G
Page 23 of 30
CY7C1370KV25
CY7C1372KV25
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles[29, 30, 31]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 7. ZZ Mode Timing[32, 33]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
33. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 001-97851 Rev. *G
Page 24 of 30
CY7C1370KV25
CY7C1372KV25
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list
of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at www.cypress.com/about-us/sales-offices.
Speed
(MHz)
Ordering Code
CY7C1370KV25-167AXC
CY7C1372KV25-167AXC
167
CY7C1370KV25-167BZC
CY7C1370KV25-167BZI
200
Package
Diagram
Operating
Range
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
CY7C1370KV25-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1370KV25-200BZC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
Industrial
Commercial
Ordering Code Definitions
CY
7
C 13XX K V25 - XXX XX X
X
Temperature Range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz
V25 = 2.5 V VDD
Process Technology: K = 65nm
Part Identifier: 13XX = 1370 or 1372
1370 = PL, 512Kb × 36 (18Mb)
1372 = PL, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-97851 Rev. *G
Page 25 of 30
CY7C1370KV25
CY7C1372KV25
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
Document Number: 001-97851 Rev. *G
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
51-85050 *G
0.65 TYP
Page 26 of 30
CY7C1370KV25
CY7C1372KV25
Package Diagrams (continued)
Figure 9. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-97851 Rev. *G
Page 27 of 30
CY7C1370KV25
CY7C1372KV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CEN
Clock Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
MHz
megahertz
EIA
Electronic Industries Alliance
µA
microampere
FBGA
Fine-Pitch Ball Grid Array
mA
milliampere
I/O
Input/Output
mm
millimeter
ms
millisecond
mV
millivolt
ns
nanosecond
JEDEC
Joint Electron Devices Engineering Council
JTAG
Joint Test Action Group
LSB
Least Significant Bit
MSB
Most Significant Bit
NoBL
No Bus Latency
OE
Output Enable
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-97851 Rev. *G
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 28 of 30
CY7C1370KV25
CY7C1372KV25
Document History Page
Document Title: CY7C1370KV25/CY7C1372KV25, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-97851
Rev.
ECN No.
Orig. of
Change
Submission
Date
*E
5084264
DEVM
01/14/2016
Description of Change
Changed status from Preliminary to Final.
*F
5285670
PRIT
05/26/2016
Updated Operating Range:
Included Industrial Temperature Range related information.
Updated Neutron Soft Error Immunity:
Changed typical value of LSBU parameter from “197 FIT/Mb” to “
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