CY7C335-66HC

1CY 7C33 5 fax id: 6018 CY7C335 Universal Synchronous EPLD Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock select multiplexer — Feed back multiplexer • • • • • • • • • • — Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden User configurable I/O macrocells to implement JK or RS flip-flops and T or D registers Input multiplexer per pair of I/O macrocells allows I/O pin associated with a hidden macrocell state register to be saved for use as an input Four dedicated hidden registers Twelve dedicated registered inputs with individually programmable bypass option Three separate clocks—two input clocks, two output clocks Common (pin 14-controlled) or product term-controlled output enable for each I/O pin 256 product terms—32 per pair of macrocells, variable distribution Global, synchronous, product term-controlled, state register set and reset—inputs to product term are clocked by input clock — 2-ns input set-up and 9-ns output register clock to output — 10-ns input register clock to state register clock • 28-pin, 300-mil DIP, LCC, PLCC • Erasable and reprogrammable • Programmable security bit Functional Description The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very high performance state machines. The architecture of the CY7C335, consisting of the user-configurable output macrocell, bidirectional I/O capability, input registers, and three separate clocks, enables the user to design high-performance state machines that can communicate either with each other or with microprocessors over bidirectional parallel buses of user-definable widths. The four clocks permit independent, synchronous state machines to be synchronized to each other. The user-configurable macrocells enable the designer to designate JK-, RS-, T-, or D-type devices so that the number of product terms required to implement the logic is minimized. The CY7C335 is available in a wide variety of packages including 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and LCCs. Logic Block Diagram OE/I11 14 I10 13 I9 12 I8 11 I7 10 I6 9 VSS 8 I5 7 I4 6 I3 5 I2 4 I1 /CLK3 3 I0 /CLK2 2 CLK1 1 PROGRAMMABLE AND ARRAY (258x68) 9 19 11 17 13 15 13 17 11 19 15 13 17 11 19 9 15 I/O11 16 I/O10 17 I/O9 18 I/O8 19 I/O7 20 I/O6 21 VSS 22 VCC 23 I/O5 24 I/O4 25 I/O3 26 I/O2 27 I/O1 28 I/O0 C335–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 1991 – Revised March 26, 1997 CY7C335 Pin Configurations LCC Top View PLCC Top View 4 3 2 1 282726 I3 I4 I5 VSS I6 I7 I8 5 6 7 8 9 10 11 12131415161718 C335–2 25 24 23 22 21 20 19 I/O3 I/O4 I/O5 VCC VSS I/O6 I/O7 I3 I4 I5 VSS I6 I7 I8 5 6 7 8 9 10 11 4 3 2 1 2827 26 25 24 23 22 21 20 19 I/O3 I/O4 I/O5 VCC VSS I/O6 I/O7 121314 1516 1718 C335–3 Selection Guide CY7C335–100 Maximum Operating Frequency (MHz) ICC1 (mA) Commercial Military Commercial Military 140 100 CY7C335–83 83.3 83.3 140 160 CY7C335–66 66.6 66.6 140 160 CY7C335–50 50 50 140 160 Architecture Configuration Bits The architecture configuration bits are used to program the multiplexers. The function of the architecture bits is outlined in Table 1. Table 1. Architecture Configuration Bits Architecture Configuration Bit C0 C1 Output Enable Select MUX State Register Feed Back MUX I/O Macrocell Input Register Clock Select MUX Input Register Bypass MUX— I/O Macrocell Output Register Bypass MUX State Clock MUX Number of Bits 12 Bits, 1 Per I/O Macrocell 12 Bits, 1 Per I/O Macrocell 12 Bits, 1 Per I/O Macrocell Value 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 12 Bits, 1 Per I/O Macrocell 12 Bits, 1 Per I/O Macrocell 16 Bits, 1 Per I/O Macrocell and 1 Per Hidden Macrocell 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed Function Output Enable Controlled by Product Term Output Enable Controlled by Pin 14 State Register Output is Fed Back to Input Array I/O Macrocell is Configured as an Input and Output of Input Path is Fed to Array ICLK1 Controls the Input Register I/O Macrocell Input Register Clock Input ICLK2 Controls the Input Register I/O Macrocell Input Register Clock Input Selects Input to Feedback MUX from Input Register Selects Input to Feedback MUX from I/O pin Selects Output from the State Register Selects Output from the Array, Bypassing the State Register State Clock 1 Controls the State Register State Clock 2 Controls the State Register C2 C3 C4 C5 2 CY7C335 Table 1. Architecture Configuration Bits (continued) Architecture Configuration Bit C6 Dedicated Input Register Clock Select MUX Input Register Bypass MUX— Input Cell ICLK2 Select MUX ICLK1 Select MUX SCLK2 Select MUX I/O Macrocell Pair Input Select MUX Number of Bits 12 Bits, 1 Per Dedicated Input Cell 12 Bits, 1 Per Dedicated Input Cell 1 Bit 1 Bit 1 Bit 6 Bits, 1 Per I/O Macrocell Pair Value 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed 0—Virgin State 1—Programmed Function ICLK1 Controls the Input Register I/O Macrocell Dedicated Input Register Clock Input ICLK2 Controls the Input Register I/O Macrocell Dedicated Input Register Clock Input Selects Input to Array from Input Register Selects Input to Array from Input Pin Input Clock 2 Controlled by Pin 2 Input Clock 2 Controlled by Pin 3 Input Clock 1 Controlled by Pin 2 Input Clock 1 Controlled by Pin 1 State Clock 2 Grounded State Clock 2 Controlled by Pin 3 Selects Data from I/O Macrocell Input Path of Macrocell A of Macrocell Pair Selects Data from I/O Macrocell Input Path of Macrocell B of Macrocell Pair C7 C8 C9 C10 CX (11–16) 1 INPUTREGISTER INPUT PIN 0 D Q INPUT REG BYPASS MUX TO ARRAY ICLK1 ICLK2 0 INPUT CLOCK 1 MUX C7 C6 C335–4 Figure 1. CY7C335 Input Macrocell 3 CY7C335 C0 PIN 14: OE OUTPUT ENABLE PRODUCT TERM 1 OUTPUT ENABLE 0 MUX OUTPUT REG BYPASS MUX SET PRODUCT TERM 1 EX OR PRODUCT TERM D S Q C4 I/O PIN 0 SCLK1 SCLK2 RESET PRODUCT TERM TO ARRAY STATE CLK 1 MUX C5 0 0 R Q FEED BACK MUX 1 C2 0 INPUT CLOCK 1 MUX INPUT REG BYPASS MUX C3 1 INPUT REGISTER 0 Q D C1 ICLK1 ICLK2 0 TO ARRAY SHARED INPUT MUX C335–5 1 FROM ADJACENT MACROCELL CX (11 – 16) Figure 2. CY7C335 Input/Output Macrocell 4 CY7C335 SET PRODUCT TERM S D Q SCLK1 SCLK2 0 1 STATE CLK MUX C5 R Q TO ARRAY RESET PRODUCT TERM C335–6 Figure 3. CY7C335 Hidden Macrocell SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS PIN 1 1 0 MUX ICLK1 ICLK2 SCLK1 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS 1 0 1 0 0 1 MUX MUX MUX TO ARRAY PIN 2 C9 C8 1 0 1 0 MUX MUX TO ARRAY PIN 3 1 0 MUX C10 C335–7 Figure 4. CY7C335 Input Clocking Scheme 5 CY7C335 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................–65°C to +150°C Ambient Temperature with Power Applied...............................................–55°C to +125°C Supply Voltage to Ground Potential (Pin 22 to Pins 8 and 21) ............................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –3.0V to +7.0V Output Current into Outputs (Low)............................... 12 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA DC Programming Voltage............................................. 13.0V Operating Range Range Commercial Industrial Military[1] Ambient Temperature 0°C to +75°C –40°C to +85°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[2] Parameter VOH VOL VIH VIL IIX IOZ ISC ICC1 ICC2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Output Short Circuit Current Standby Power Supply Current Power Supply Current at Frequency[5] VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL Test Conditions IOH = –3.2 mA IOL = 12 mA Com’l Mil/Ind Com’l Mil/Ind 2.2 0.8 –10 –40 –30 Com’l Mil/Ind Com’l Mil/Ind 10 40 –90 140 160 180 200 V V µA µA mA mA mA mA mA Inputs[3] 0.5 V Min. 2.4 Max. Unit V Guaranteed Input Logical HIGH Voltage for All Inputs[3] Guaranteed Input Logical LOW Voltage for All VSS ≤ VIN ≤ VCC, VCC = Max. VCC = Max., VSS ≤ VOUT ≤ VCC VCC = Max., VOUT = 0.5V[4, 5] VCC = Max., VIN = GND Outputs Open VCC = Max., Outputs Disabled (in High Z State), Device Operating at fMAX External (fMAX5) Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz Min. Max. 10 10 Unit pF pF Notes: 1. tA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V OUT = 0.5V has been chosen to avoid test problems caused by ground degradation. 5. Tested initially and after any design or process changes that may affect these parameters. 6 CY7C335 AC Test Loads and Waveforms (Commercial) R1 313 Ω (470Ω MIL/IND) 5V OUTPUT 50pF INCLUDING JIG AND SCOPE 3.0V R2 208 Ω (319Ω Mil/Ind) 90% GND ≤ 3 ns 10% 90% 10% ≤ 3 ns ALL INPUT PULSES (a) C335–8 (b) C335–11 R=125 Ω (190Ω MIL) OUTPUT C = 50 pF VTH =2.00V (2.02VMIL) 0V 0V C335–9 R=125 Ω (190Ω MIL) OUTPUT C = 5 pF VX 0V 0V C335–10 (c) Thévenin Equivalent (Load 1) (d) Three-state Delay Load (Load2) Parameter t PXZ (–) t PXZ (+) t PZX (+) t PZX (–) t CER (–) t CER (+) t CEA (+) t CEA (–) VX 1.5V 2.6V V th V th 1.5V 2.6V V th V th V OH V OL VX VX V OH V OL VX VX Output Waveform Measurement Level 0.5V 0.5V 0.5V VX VX C335–13 C335–12 V OH C335–14 0.5V 0.5V 0.5V 0.5V V OL VX VX C335–15 C335–16 C335–17 V OH C335–18 0.5V V OL C335–19 Figure 5. Test Waveforms 7 CY7C335 Commercial AC Characteristics 7C335–100 Parameter tPD tEA tER tWH tWL tIS tIH tICO tIOH tIOH – tIH 33x tPZX tPXZ fMAX1 Description Input to Output Propagation Delay Input to Output Enable Input to Output Disable Input and Output Clock Width HIGH[5] Input and Output Clock Width LOW[5] Input or Feedback Set-Up Time to Input Clock Input Register Hold Time from Input Clock Input Register Clock to Output Delay Output Data Stable Time from Input Clock Output Data Stable from Input Clock Minus Input Register Hold Time for 7C335[6] Pin 14 Enable to Output Enabled Pin 14 Disable to Output Disabled Maximum Frequency of (2) CY7C335s in Input Registered Mode (Lowest of 1/(t ICO +tIS) & 1/(tWL +tWH))[5] Maximum Frequency Data Path in Input Registered Mode (Lowest of (1/(tICO), 1/(tWH +tWL), 1/(tIS +tIH))[5] Input Clock to Output Enabled Input Clock to Output Disabled Output Clock to Output Enabled[5] Output Clock to Output Disabled[5] 8 0 9 17 2 3 0 100 58.8 2 3 0 83.3 50 Output Register Input Set-Up Time from Output Clock Output Register Input Hold Time from Output Clock Output Register Clock to Output Delay Input Output Register Clock or Latch Enable to Combinatorial Output Delay (Through Logic Array)[5] Output Data Stable Time from Output Clock Output Data Stable Time From Output Clock (Through Memory Array)[5] Output Data Clock Stable Time From Output Clock Minus Input Register Hold Time[5] Maximum Frequency with Internal Feedback in Output Registered Mode[5] Maximum Frequency of (2) CY7C335s in Output Registered Mode (Lowest of 1/(tCO + tS) & 1/(tWL + tWH))[5] Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/(tCO), 1/(tWL + tWH), 1/(tS + tH))[5] Output Data Stable from Output Clock Minus Input Register Hold Time for 7C335[6] 50 3 0 12 12 50 4 4 2 2 18 3 0 12 12 45.4 Combinatorial Mode Parameters 15 15 15 5 5 2 2 18 3 0 15 15 35.7 15 15 15 6 6 2 2 20 3 0 20 20 20 20 20 8 8 3 3 25 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns MHz 7C335–83 7C335–66 7C335–50 Unit Min. Max. Min. Max. Min. Max. Min. Max. Input Registered Mode Parameters fMAX2 55.5 55.5 50 40 MHz tICEA tICER tCEA tCER tS tH tCO tCO2 tOH tOH2 tOH2–tIH fMAX3 fMAX4 17 15 17 15 9 0 17 15 17 15 12 0 10 18 2 3 0 66.6 41.6 20 20 20 20 15 0 12 23 2 3 0 50 33.3 25 25 25 25 ns ns ns ns ns ns Output Registered Mode Parameters 15 30 ns ns ns ns ns MHz MHz fMAX5 111 100 83.3 62.5 MHz tOH – tIH 33x 0 0 0 0 ns 8 CY7C335 Commercial AC Characteristics (continued) 7C335–100 Parameter Pipelined Mode Parameters tCOS fMAX6 fMAX7 Input Clock to Output Clock Maximum Frequency Pipelined Mode (Lowest of 1/(tCOS), 1/(tCO), 1/(tWL + tWH)), 1/(tIS + tIH)[5] Maximum Frequency of (2) CY7C335s in Pipelined Mode (Lowest of 1/(tCO + tIS) or 1/tCOS) Power-Up Reset Time[5, 7] 10 100 90.9 12 83.3 83.3 15 66.6 66.6 20 50 50 ns MHz MHz Description 7C335–83 7C335–66 7C335–50 Min. Max. Min. Max. Min. Max. Min. Max. Unit Power-Up Reset Parameters tPOR 1 1 1 1 µs Military/Industrial AC Characteristics 7C335–83 Parameter Combinatorial Mode Parameters tPD tEA tER tWH tWL tIS tIH tICO tIOH tIOH – tIH 33x tPZX tPXZ fMAX1 fMAX2 tICEA tICER tCEA tCER tS tH tCO tCO2 Input to Output Propagation Delay Input to Output Enable Input to Output Disable Input and Output Clock Width HIGH[5] Input and Output Clock Width LOW[5] Input or Feedback Set-Up Time to Input Clock Input Register Hold Time from Input Clock Input Register Clock to Output Delay Output Data Stable Time from Input Clock Output Data Stable from Input Clock Minus Input Register Hold Time for 7C335[6] Pin 14 Enable to Output Enabled Pin 14 Disable to Output Disabled Maximum Frequency of (2) CY7C335s in Input Registered Mode (Lowest of 1/(tICO +tIS) & 1/(tWL +tWH))[5] Maximum Frequency Data Path in Input Registered Mode (Lowest of (1/(tICO), 1/(tWH +tWL), 1/(tIS +tIH))[5] Input Clock to Output Enabled Input Clock to Output Disabled Output Clock to Output Enabled [5] Output Clock to Output Disabled [5] 7C335–66 Min. Max. 20 20 20 6 6 3 3 Unit ns ns ns ns ns ns ns 23 3 0 ns ns ns 15 15 38.4 43.4 ns ns MHz MHz 20 20 20 20 12 0 ns ns ns ns ns ns 12 23 ns ns Description Min. Max. 20 20 20 Input Registered Mode Parameters 5 5 3 3 23 3 0 15 15 38.4 43.4 20 20 20 20 10 0 11 22 Output Registered Mode Parameters Output Register Input Set-Up Time to Output Clock Output Register Input Hold Time from Output Clock Output Register Clock to Output Delay Output Register Clock or Latch Enable to Combinatorial Output Delay (Through Logic Array)[5] Notes: 6. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C335. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. 7. This part has been designed with the capability to reset during system power-up. Following power-up, the input and output registers will be reset to a logic LOW state. The output state will depend on how the array is programmed. 9 CY7C335 Military/Industrial AC Characteristics (continued) 7C335–83 Parameter tOH tOH2 tOH2–tIH fMAX3 fMAX4 fMAX5 tOH – tIH 33x tCOS fMAX6 fMAX7 Description Output Data Stable Time from Output Clock Output Data Stable Time From Output Clock Memory Array)[5] (Through Min. 2 3 0 83.3 47.6 90.9 0 Max. 7C335–66 Min. 2 3 0 66.6 41.6 83.3 0 Max. Unit ns ns ns MHz MHz MHz ns Output Data Clock Stable Time From Output Clock Minus Input Register Hold Time[5] Maximum Frequency with Internal Feedback in Output Registered Mode[5] Maximum Frequency of (2) CY7C335s in Output Registered Mode (Lower of 1/(tCO + tS) & 1/(tWL + tWH))[5] Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/(tCO), 1/(tWL + tWH), 1/(tS + tH))[5] Output Data Stable from Output Clock Minus Input Register Hold Time for 7C335[6] Input Clock to Output Clock Maximum Frequency Pipelined Mode (Lowest of 1/(tCOS), 1/(tIS), or 1/(tCO)), 1/(tIS + tIH)[5] Maximum Frequency of (2) CY7C335s in Pipelined Mode (Lowest of 1/(tCO + tIS) or 1/tCOS) Power-Up Reset Time[5, 7] Pipelined Mode Parameters 12 83.3 71.4 15 66.6 66.6 ns MHz MHz Power-Up Reset Parameters tPOR 1 1 µs 10 CY7C335 Switching Waveform INPUTOR I/O PIN tIS INPUT REG. CLOCK tWH tCOS OUTPUT REG. CLOCK tIOH OUTPUT tPD tICER tER tPXZ PIN 14 AS OE C335–20 tIH tS tH tWL tWH tWL tICO tCO tOH tEA tICEA tPZX Power-Up Reset Waveform[7] 90% VCC tPOR OUTPUT tCOS CLOCK tWL C335–21 11 CY7C335 Block Diagram (Page 1 of 2) 1 (C9) 2 (C6,7) 9 SCLK1 SCLK2 0 8 16 24 32 40 48 56 64 RESET node=29 (C8) 3 (C6,7) (C10) 28 node=40 19 27 11 4 (C6,7) 17 26 node=39 25 13 24 node=38 5 (C6,7) 15 23 19 node=34 6 (C6,7) 11 node=33 7 (C6,7) TO LOWER SECTION 12 CY7C335 Block Diagram (Page 2 of 2) TO UPPER SECTION 15 20 9 (C4,5) 13 node=37 19 17 node=32 10 (C4,5) 13 node=31 11 (C4,5) 17 18 12 (C4,5) 11 13 (C4,5) 19 node=36 17 16 14 (C4,5) 9 node=35 15 OE 0 8 16 24 32 40 48 56 64 SET node=30 OE C335–23 13 CY7C335 Ordering Information fMAX (MHz) 100 83.3 ICC1 (mA) 140 160 Ordering Code CY7C335–100WC CY7C335–83LMB CY7C335–83QMB CY7C335–83WMB 140 CY7C335–83HC CY7C335–83JC CY7C335–83WC 66.6 160 140 CY7C335–66QMB CY7C335–66HC CY7C335–66JC CY7C335–66PC CY7C335–66WC 50 140 CY7C335–50JC CY7C335–50PC Package Name W22 L64 Q64 W22 H64 J64 W22 Q64 H64 J64 P21 W22 J64 P21 Package Type 28-Lead (300-Mil) Windowed CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP 28-Pin Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Windowed CerDIP 28-Pin Windowed Leadless Chip Carrier 28-Pin Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP Military Commercial Commercial Operating Range Commercial Military MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tPD tICO tIS tCO tS tH tCOS Switching Characteristics Parameter Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38–00186–D 14 CY7C335 Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D–15 Config.A 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C–4 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C–4 15 CY7C335 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier H64 16 CY7C335 Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D– 15Config.A © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.