CY7C601XX_11

CY7C601xx, CY7C602xx enCoRe™ II Low-Voltage Microcontroller 1. Features enCoRe II low-voltage (enCoRe II LV) – enhanced component reduction ❐ Internal crystalless oscillator with support for optional external clock or external crystal or resonator ❐ Configurable I/O for real world interface without external components ■ Enhanced 8-bit microcontroller ❐ Harvard architecture ❐ M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal ■ Internal memory ❐ 256 bytes of random access memory (RAM) ❐ 8 KB of flash including electrically erasable read only memory (EEROM) emulation ■ Low power consumption ❐ Typically 2.25 mA at 3 MHz ❐ 5 A sleep ■ In-system reprogrammability ❐ Enables easy firmware update ■ General-purpose I/O (GPIO) ports ❐ Up to 36 GPIO pins ❐ 2-mA source current on all GPIO pins ❐ Configurable 8 or 50 mA per pin current sink on designated pins ❐ Each GPIO port supports high-impedance inputs, configurable pull-up, open drain output, complementary metal oxide semiconductor (CMOS), and transistor-transistor logic (TTL) inputs, and CMOS output ❐ Maskable interrupts on all I/O pins ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SPI serial communication ❐ Master or slave operation ❐ Configurable up to 2 Mbit per second transfers ❐ Supports half-duplex single-data line mode for optical sensors 2-channel 8-bit or 1-channel 16-bit capture timer registers, which store both rising and falling edge times ❐ Two registers each for two input pins ❐ Separate registers for rising and falling edge capture ❐ Simplifies interface to radio frequency (RF) inputs for wireless applications Internal low-power wakeup timer during suspend mode ❐ Periodic wakeup with no external components Programmable interval timer interrupts Reduced RF emissions at 27 MHz and 96 MHz Watchdog timer (WDT) Low-voltage detection (LVD) with user-selectable threshold voltages Improved output drivers to reduce electromagnetic interference (EMI) Operating voltage from 2.7 V to 3.6 V DC Operating temperature from 0 °C to 70 °C Available in 40-pin plastic dual inline package (PDIP), 24-pin small outline integrated circuit (SOIC), 24-pin quad small outline package (QSOP) and shrink small outline package (SSOP), 48-pin SSOP Advanced development tools based on Cypress PSoC® tools Industry-standard programmer support 2. Logic Block Diagram Interrupt Control 4 SPI/GPIO Pins 16 Extended I/O Pins 16 GPIO Pins Wakeup Timer Internal 12 MHz Oscillator Clock Control Crystal Oscillator CY7C601xx only M8C CPU RAM 256 Byte Flash 8 KB 12-bit Timer Capture Timers POR / Low-Voltage Detect VDD Watchdog Timer Cypress Semiconductor Corporation Document 38-16016 Rev. *J •198 Champion Court •San Jose, CA 95134-1709 •408-943-2600 Revised June 6, 2011 CY7C601xx, CY7C602xx 3. Contents Applications ...................................................................... 3 Introduction ....................................................................... 3 Conventions ...................................................................... 3 Pinouts .............................................................................. 4 Pin Assignments .......................................................... 5 Register Summary ............................................................ 7 CPU Architecture .............................................................. 9 CPU Registers ................................................................... 9 Flags Register ............................................................. 9 Addressing Modes ..................................................... 11 Instruction Set Summary ............................................... 13 Memory Organization ..................................................... 15 Flash Program Memory Organization ....................... 15 Data Memory Organization ....................................... 16 Flash .......................................................................... 16 SROM ........................................................................ 16 SROM Function Descriptions .................................... 17 SROM Table Read Description ................................. 20 Clocking .......................................................................... 22 Trim Values for the IOSCTR Register ....................... 22 Clock Architecture Description .................................. 23 CPU Clock During Sleep Mode ................................. 30 Reset ................................................................................ 31 Power On Reset ........................................................ 32 Watchdog Timer Reset .............................................. 32 Sleep Mode ...................................................................... 32 Sleep Sequence ........................................................ 33 Wakeup Sequence .................................................... 34 Low-Voltage Detect Control ......................................... 35 POR Compare State ................................................. 36 ECO Trim Register .................................................... 36 General-Purpose I/O Ports ............................................. 37 Port Data Registers ................................................... 37 GPIO Port Configuration ........................................... 38 Serial Peripheral Interface (SPI) .................................... 45 SPI Data Register ...................................................... 46 SPI Configure Register ............................................. 46 SPI Interface Pins ...................................................... 48 Timer Registers .............................................................. 48 Registers ................................................................... 48 Interrupt Controller ......................................................... 55 Architectural Description ........................................... 56 Interrupt Processing .................................................. 56 Interrupt Latency ....................................................... 56 Interrupt Registers ..................................................... 57 Absolute Maximum Ratings .......................................... 60 DC Characteristics .................................................... 60 AC Characteristics .................................................... 61 Ordering Information ...................................................... 64 Package Handling ........................................................... 64 Package Diagrams .......................................................... 65 Document History Page ................................................. 67 Sales, Solutions, and Legal Information ...................... 68 Document 38-16016 Rev. *J Page 2 of 68 CY7C601xx, CY7C602xx 4. Applications The CY7C601xx and CY7C602xx are targeted for the following applications: ■ PC wireless human interface devices (HID) ❐ Mice (optomechanical, optical, trackball) ❐ Keyboards ❐ Presenter tools Gaming ❐ Joysticks ❐ Gamepad General-purpose wireless applications ❐ Remote controls ❐ Barcode scanners ❐ POS terminal ❐ Consumer electronics ❐ Toys ■ In addition, enCoRe II LV includes a WDT, a vectored interrupt controller, a 16-bit free-running timer with capture registers, and a 12-bit programmable interval timer. The power on reset (POR) circuit detects when power is applied to the device, resets the logic to a known state, and executes instructions at flash address 0x0000. When power falls below a programmable trip voltage, it generates a reset or is configured to generate an interrupt. There is a LVD circuit that detects when VCC drops below a programmable trip voltage. This is configurable to generate a LVD interrupt to inform the processor about the low-voltage event. POR and LVD share the same interrupt; there is no separate interrupt for each. The WDT ensures the firmware never gets stalled in an infinite loop. The microcontroller supports 17 maskable interrupts in the vectored interrupt controller. All interrupts can be masked. Interrupt sources include LVR or POR, a programmable interval timer, a nominal 1.024 ms programmable output from the free-running timer, two capture timers, five GPIO ports, three GPIO pins, two SPI, a 16-bit free-running timer wrap, and an internal wakeup timer interrupt. The wakeup timer causes periodic interrupts when enabled. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge-sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. The free-running timer generates an interrupt at 1024-s rate. It also generates an interrupt when the free-running counter overflow occurs – every 16.384 ms. The duration of an event under firmware control is measured by reading the timer at the start and end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.5 and P0.6). The two 8-bit capture registers are ganged into a single 16-bit capture register. The enCoRe II LV supports in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface. ■ 5. Introduction The enCoRe II LV family brings the features and benefits of the enCoRe II to non-USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wakeup circuitry, are also integrated into this chip. The enCoRe II LV is a low-voltage, low-cost 8-bit flash-programmable microcontroller. The enCoRe II LV features up to 36 GPIO pins. The I/O pins are grouped into five ports (Port 0 to 4). The pins on ports 0 and 1 are configured individually, when the pins on ports 2, 3, and 4 are only configured as a group. Each GPIO port supports high-impedance inputs, configurable pull-up, open-drain output, CMOS, and TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50-mA sink current. Additionally, each I/O pin is used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO port 0. GPIO port 0 has, in addition to the port interrupt vector, three dedicated pins that have independent interrupt vectors (P0.2–P0.4). The enCoRe II LV features an internal oscillator. Optionally, an external 1-MHz to 24-MHz crystal is used to provide a higher precision reference. The enCoRe II LV also supports external clock. The enCoRe II LV has 8 KB of flash for user code and 256 bytes of RAM for stack space and user variables. 6. Conventions In this document, bit positions in the registers are shaded to indicate which members of the enCoRe II LV family implement the bits. Available in all enCoRe II LV family members CY7C601xx only Document 38-16016 Rev. *J Page 3 of 68 CY7C601xx, CY7C602xx 7. Pinouts Figure 7-1. Package Configurations Top View CY7C60223 24-Pin SOIC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60223 24-Pin QSOP NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.0 NC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2 VDD P1.1 P1.0 VSS CY7C60123 40-Pin PDIP VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 T1O1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60123 48-Pin SSOP NC NC NC NC VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 TIO1/P0.6 TIO0/PO.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 Document 38-16016 Rev. *J Page 4 of 68 CY7C601xx, CY7C602xx 7.1 Pin Assignments Table 7-1. Pin Assignments 48 40 24 24 SSOP PDIP QSOP SOIC 7 6 42 43 34 35 36 37 38 39 40 41 15 14 13 12 11 10 9 8 25 3 2 38 39 30 31 32 33 34 35 36 37 11 10 9 8 7 6 5 4 21 – – – – 19 20 – – – – – – 11 10 – – – – – – 14 – – – – 18 19 – – – – – – 11 10 – – – – – – 13 Name P4.0 P4.1 P4.2 P4.3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 GPIO port 1 bit 0/ISSP-SCLK If this pin is used as a general-purpose output it draws current. It is, therefore, configured as an input to reduce current draw. GPIO port 1 bit 1/ISSP-SDATA If this pin is used as a general-purpose output it draws current. It is, therefore, configured as an input to reduce current draw. GPIO port 1 bit 2 GPIO port 1 bit 3—Configured individually Alternate function is SSEL signal of the SPI bus. GPIO port 1 bit 4—Configured individually Alternate function is SCLK signal of the SPI bus. GPIO port 1 bit 5—Configured individually Alternate function is SMOSI signal of the SPI bus. GPIO port 1 bit 6—Configured individually Alternate function is SMISO signal of the SPI bus. GPIO port 1 bit 7—Configured individually TTL voltage threshold. GPIO port 0 bit 0—Configured individually On CY7C601xx, optional Clock In when external oscillator is disabled or external oscillator input when external oscillator is enabled. On CY7C602xx, oscillator input when configured as Clock In. GPIO port 2—configured as a group (byte) GPIO port 3—configured as a group (byte) Description GPIO port 4—configured as a group (nibble) 26 22 15 14 P1.1 28 29 30 31 32 33 23 24 25 26 27 28 29 19 17 18 21 22 23 24 9 16 17 20 21 22 23 9 P1.2 P1.3/SSEL P1.4/SCLK P1.5/SMOSI P1.6/SMISO P1.7 P0.0/CLKIN Document 38-16016 Rev. *J Page 5 of 68 CY7C601xx, CY7C602xx Table 7-1. Pin Assignments (continued) 48 40 24 24 SSOP PDIP QSOP SOIC 22 18 8 8 Name Description P0.1/CLKOUT GPIO port 0 bit 1—Configured individually On CY7C601xx, optional Clock Out when external oscillator is disabled or external oscillator output drive when external oscillator is enabled. On CY7C602xx, oscillator output when configured as Clock Out. P0.2/INT0 P0.3/INT1 P0.4/INT2 P0.5/TIO0 P0.6/TIO1 P0.7 NC NC VDD GPIO port 0 bit 2—Configured individually Optional rising edge interrupt INT0. GPIO port 0 bit 3—Configured individually Optional rising edge interrupt INT1. GPIO port 0 bit 4—Configured individually Optional rising edge interrupt INT2. GPIO port 0 bit 5—Configured individually Alternate function timer capture inputs or timer output TIO0. GPIO port 0 bit 6—Configured individually Alternate function timer capture inputs or timer output TIO1. GPIO port 0 bit 7—Configured individually No connect No connect Power Ground 21 20 19 18 17 16 1,2,3, 4 45,46, 47,48 5 27 44 24 17 16 15 14 13 12 – – 1 23 40 20 7 6 5 4 3 2 1 12 7 6 5 4 3 2 1 24 16 – 13 15 – 12 VSS Document 38-16016 Rev. *J Page 6 of 68 CY7C601xx, CY7C602xx 8. Register Summary Table 8-1. enCoRe II LV Register Summary The XIO bit in the CPU flags register must be set to access the extended register space for all registers above 0xFF. Addr 00 01 02 03 04 05 06 07–09 0A–0B 0C 0D 0E 0F 10 11–13 14 15 16 17 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 30 31 32 Name P0DATA P1DATA P2DATA P3DATA P4DATA P00CR P01CR P02CR– P04CR P05CR– P06CR P07CR P10CR P11CR P12CR P13CR P14CR– P16CR P17CR P2CR P3CR P4CR FRTMRL FRTMRH TCAP0R TCAP1R TCAP0F TCAP1F PITMRL PITMRH PIRL PIRH TMRCR TCAPINTE TCAPINTS CPUCLKCR TMRCLKCR CLKIOCR 7 P0.7 P1.7 6 P0.6/TIO1 5 P0.5/TIO0 4 P0.4/INT2 P1.4/SCLK 3 P0.3/INT1 P1.3/SSEL 2 P0.2/INT0 P1.2 1 P0.1/ CLKOUT P1.1 0 P0.0/CLKIN P1.0 R/W bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ----bbbb -bbbbbbb bbbbbbbb --bb-bbb bbbb-bbb -bbb-bbb -bb----b -bb--b-b bbbb-bbb -bb-bbbb bbb-bbbb -bb-bbbb -bbbbbbb -bbbbbbb -bbb-bbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10001111 00000000 P1.6/SMISO P1.5/SMOSI P2.7–P2.2 P3.7–P3.2 Reserved Reserved CLK output Int enable Int enable Int act low Int act low Int act low Int act low Int act low Int act low Int act low Reserved Reserved High sink High sink High sink High sink High sink Reserved TTL thresh TTL thresh TTL thresh TTL thresh TTL thresh High sink High sink Reserved Reserved Reserved P4.3–P4.0 Open drain Open drain Open drain Open drain Open drain P2.1–P2.0 P3.1–P3.0 Pull-up enable Pull-up enable Pull-up enable Pull-up enable Pull-up enable Output enable Output enable Output enable Output enable Output enable Output enable Reserved Pull-up enable Pull-up enable Pull-up enable Pull-up enable Pull-up enable Pull-up enable Pull-up enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Reserved TIO output Reserved Reserved Reserved CLK output Reserved SPI use Reserved Reserved Reserved Reserved Int enable Int enable Int enable Int enable Int enable Int enable Int enable Int enable Int enable Int enable Int enable Reserved Open drain Open drain Open drain Open drain Open drain Open drain Open drain Open drain Int act low TTL threshold Int act low Int act low Int act low Int act low Int act low Int act low Reserved Reserved Reserved TTL thresh TTL thresh TTL thresh Free-running timer [7:0] Free-running timer [15:8] Capture 0 rising [7:0] Capture 1 rising [7:0] Capture 0 falling [7:0] Capture 1 falling [7:0] Prog interval timer [7:0] Reserved Prog interval [7:0] Reserved First edge hold 8-bit capture prescale Reserved Reserved Reserved TCAPCLK divider Reserved TCAPCLK select XOSC Select ITMRCLK divider XOSC Enable EFTB Disabled Cap0 16-bit enable Cap1 fall active Cap1 fall active Cap1 rise active Cap1 rise active Prog interval [11:8] Reserved Cap0 fall active Cap0 fall active Cap0 rise active Cap0 rise active CPU CLK select ITMRCLK select CLKOUT select Prog interval timer [11:8] ----rrrr bbbbbbbb ----bbbb bbbbb------bbbb ----bbbb -------b bbbbbbbb ---bbbbb Document 38-16016 Rev. *J Page 7 of 68 CY7C601xx, CY7C602xx Table 8-1. enCoRe II LV Register Summary (continued) The XIO bit in the CPU flags register must be set to access the extended register space for all registers above 0xFF. Addr 34 35 36 3C 3D DA DB DC Name IOSCTR XOSCTR LPOSCTR SPIDATA SPICR INT_CLR0 INT_CLR1 INT_CLR2 7 6 foffset[2:0] Reserved 5 4 3 XOSC XGM [2:0] 2 Gain[4:0] 1 Reserved 0 Mode R/W bbbbbbbb ---bbb-b b-bbbbbb bbbbbbbb Default 000ddddd 000ddddd d-dddddd 00000000 00000000 00000000 00000000 00000000 32 kHz low power Swap TCAP0 Reserved Reserved 32 kHz bias trim [1:0] SPIData[7:0] 32 kHz freq trim [3:0] LSB first Prog interval timer Comm mode INT1 1 ms timer GPIO Port 0 CPOL SPI Receive CPHA SPI transmit Reserved SCLK select INT0 POR/LVD bbbbbbbb bbbbbbbb bbb----- GPIO port 1 Sleep timer GPIO port 4 GPIO port 3 GPIO port 2 Reserved INT2 16-bit counter wrap 16-bit counter wrap int enable TCAP1 -bbb-bbb DE DF INT_MSK3 INT_MSK2 ENSWINT Reserved GPIO port 4 GPIO port 3 GPIO port 2 int enable int enable int enable Reserved Reserved INT2 Int enable TCAP1 Int enable r-------bbb-bbb 00000000 00000000 E1 INT_MSK1 TCAP0 int enable Prog interval timer int enable 1 ms timer int enable INT1 int enable GPIO port 0 int enable SPI receive int enable Reserved bbb----- 00000000 E0 E2 E3 -----F7 FF 1E0 1E3 1EB 1E4 INT_MSK0 INT_VC RESWDT CPU_A CPU_X CPU_PCL CPU_PCH CPU_SP CPU_F CPU_SCR OSC_CR0 LVDCR ECO_TR VLTCMP GPIO Port 1 Sleep timer int enable int enable SPI transmit int enable INT0 int enable POR/LVD int enable bbbbbbbb bbbbbbbb wwwwwww w ------------------------------------ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010 00010100 00001000 00000000 00000000 00000000 Pending interrupt [7:0] Reset watchdog timer [7:0] Temporary register T1 [7:0] X[7:0] Program counter [7:0] Program counter [15:8] Stack pointer [7:0] Reserved GIES Reserved WDRS No buzz Reserved Reserved Sleep duty cycle [1:0] Reserved XIO PORS Super Sleep Reserved Reserved LVD PPOR Carry Reserved Zero Reserved CPU speed [2:0] VM[2:0] Global IE Stop ---brbbb r-ccb--b --bbbbbb --bb-bbb bb-----------rr Sleep timer [1:0] PORLEV[1:0] Note In the R/W column: b = Both read and write r = Read only w = Write only c = Read or clear d = Calibration value. Must not change during normal use Document 38-16016 Rev. *J Page 8 of 68 CY7C601xx, CY7C602xx 9. CPU Architecture This family of microcontrollers is based on a high-performance, 8-bit, Harvard-architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 9-1. CPU Registers and Register Name Register Flags Program counter Accumulator Stack pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X The accumulator register (CPU_A) is the general-purpose register that holds results of instructions that specify any of the source addressing modes. The index register (CPU_X) holds an offset value used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The stack pointer register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It is also affected by the SWAP and ADD instructions. The flag register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The global interrupt enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the supervisory state status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (AND, OR, XOR). See Table 11-1 on page 13. The 16-bit program counter register (CPU_PC) directly addresses the full 8 KB of program memory space. 10. CPU Registers 10.1 Flags Register The flags register is only set or reset with logical instruction. Table 10-1. CPU Flags Register (CPU_F) [R/W] Bit # Field Read/Write Default – 0 7 6 Reserved – 0 – 0 5 4 XIO R/W 0 3 Super R 0 2 Carry R/W 0 1 Zero R/W 1 0 Global IE R/W 0 Bit [7:5]: Reserved Bit 4: XIO Set by the user to select between the register banks. 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or supervisor code. (This code cannot be accessed directly by the user.) 0 = User code 1 = Supervisor code Bit 2: Carry Set by CPU to indicate whether there is a carry in the previous logical or arithmetic operation. 0 = No carry 1 = Carry Bit 1: Zero Set by CPU to indicate whether there is a zero result in the previous logical or arithmetic operation. 0 = Not equal to zero 1 = Equal to zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled. 0 = Disabled 1 = Enabled Note This register is readable with explicit address 0xF7. The OR F, expr and AND F, expr are used to set and clear the CPU_F bits. Document 38-16016 Rev. *J Page 9 of 68 CY7C601xx, CY7C602xx 10.1.1 Accumulator Register Table 10-2. CPU Accumulator Register (CPU_A) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 CPU accumulator [7:0] Bit [7:0]: CPU accumulator [7:0] 8-bit data value holds the result of any logical or arithmetic instruction that uses a source addressing mode. 10.1.2 Index Register Table 10-3. CPU X Register (CPU_X) Bit # Field Read/Write Default – 0 – 0 – 0 – 0 7 6 5 4 X [7:0] – 0 – 0 – 0 – 0 3 2 1 0 Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. 10.1.3 Stack Pointer Register Table 10-4. CPU Stack Pointer Register (CPU_SP) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 Stack pointer [7:0] Bit [7:0]: Stack pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack. 10.1.4 CPU Program Counter High Register Table 10-5. CPU Program Counter High Register (CPU_PCH) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 Program counter [15:8] Bit [7:0]: Program counter [15:8] 8-bit data value holds the higher byte of the program counter. 10.1.5 CPU Program Counter Low Register Table 10-6. CPU Program Counter Low Register (CPU_PCL) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 Program counter [7:0] Bit [7:0]: Program counter [7:0] 8-bit data value holds the lower byte of the program counter. Document 38-16016 Rev. *J Page 10 of 68 CY7C601xx, CY7C602xx 10.2 Addressing Modes 10.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources; the second source is the A, X, SP, or F register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 10-7. Source Immediate Opcode Instruction Examples ADD A, 7 ;In this case, the immediate value of 7 is added with the accumulator and the result is placed in the accumulator. ;In this case, the immediate value of 8 is moved to the X register. ;In this case, the immediate value of 9 is logically ANDed with the F register and the result is placed in the F register. 10.2.3 Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 10-9. Source Indexed Opcode Instruction Examples ADD A, [X+7] ;In this case, the value in the memory location at address X + 7 is added with the accumulator, and the result is placed in the accumulator. ;In this case, the value in the register space at address X + 8 is moved to the X register. Operand 1 Immediate value Operand 1 Source index MOV AND X, F, 8 9 MOV X, REG[X+8] 10.2.2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 10-8. Source Direct Opcode Instruction Examples ADD A, [7] ;In this case, the value in the RAM memory location at address 7 is added with the accumulator, and the result is placed in the accumulator. ;In this case, the value in the register space at address 8 is moved to the X register. 10.2.4 Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 10-10. Destination Direct Opcode Instruction Examples ADD [7], A ;In this case, the value in the memory location at address 7 is added with the accumulator, and the result is placed in the memory location at address 7. The accumulator is unchanged. ;In this case, the accumulator is moved to the register space location at address 8. The accumulator is unchanged. Operand 1 Source address Operand 1 Destination address MOV X, REG[8] MOV REG[8], A Document 38-16016 Rev. *J Page 11 of 68 CY7C601xx, CY7C602xx 10.2.5 Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 10-11. Destination Indexed Opcode Instruction Example ADD [X+7], A ;In this case, the value in the memory location at address X+7 is added with the accumulator and the result is placed in the memory location at address X+7. The accumulator is unchanged. 10.2.7 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 10-13. Destination Indexed Source Immediate Operand 1 Opcode Instruction Examples ADD [X+7], 5 ;In this case, the value in the memory location at address X+7 is added with the immediate value of 5, and the result is placed in the memory location at address X+7. ;In this case, the immediate value of 6 is moved into the location in the register space at address X+8. Destination index Operand 1 Destination index Operand 2 Immediate value MOV REG[X+8], 6 10.2.6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 10-12. Destination Direct Source Immediate Opcode Instruction Examples ADD [7], 5 ;In this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. ;In this case, the immediate value of 6 is moved into the register space location at address 8. 10.2.8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 10-14. Destination Direct Source Direct Opcode Instruction Example MOV [7], [8] ;In this case, the value in the memory location at address 8 is moved to the memory location at address 7. Operand 1 Destination address Operand 2 Immediate value Operand 1 Destination address Operand 2 Source address MOV REG[8], 6 Document 38-16016 Rev. *J Page 12 of 68 CY7C601xx, CY7C602xx 10.2.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 10-15. Source Indirect Post Increment Opcode Instruction Example MVI A, [8] ;In this case, the value in the memory location at address 8 is an indirect address. The memory location pointed to by the Indirect address is moved into the accumulator. The indirect address is then incremented. 10.2.10 Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 10-16. Destination Indirect Post Increment Opcode Instruction Example MVI [8], A ;In this case, the value in the memory location at address 8 is an indirect address. The accumulator is moved into the memory location pointed to by the indirect address. The indirect address is then incremented. Operand 1 Source address Operand 1 Destination address 11. Instruction Set Summary The instruction set is summarized in Table 11-1 numerically and serves as a quick reference. The instruction set summary tables are described in detail in the PSoC Designer: Assembly Language User Guide. Table 11-1. Instruction Set Summary Sorted Numerically by Opcode Order Opcode Hex Opcode Hex Opcode Hex Cycles Cycles Cycles Bytes Bytes Instruction Format[1, 2] Flags Instruction Format Flags Bytes Instruction Format Flags 00 15 1 01 4 02 6 03 7 04 7 05 8 06 9 08 2 2 2 2 2 3 SSC ADD A, expr ADD A, [expr] ADD A, [X+expr] ADD [expr], A ADD [X+expr], A ADD [expr], expr ADD [X+expr], expr PUSH A ADC A, expr ADC A, [expr] ADC A, [X+expr] ADC [expr], A ADC [X+expr], A ADC [expr], expr ADC [X+expr], expr PUSH X SUB A, expr C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z 2D 8 2E 9 30 2 3 OR [X+expr], A OR [expr], expr OR [X+expr], expr HALT XOR A, expr XOR A, [expr] XOR A, [X+expr] XOR [expr], A XOR [X+expr], A XOR [expr], expr XOR [X+expr], expr ADD SP, expr CMP A, expr CMP A, [expr] CMP A, [X+expr] CMP [expr], expr CMP [X+expr], expr MVI A, [ [expr]++ ] Z Z Z Z Z Z Z Z Z Z if (A=B) Z=1 if (A