CY8CPLC20

CY8CPLC20 Powerline Communication Solution Features Powerline Communication Solution ❐ Integrated Powerline Modem PHY ❐ Frequency Shift Keying Modulation ❐ Configurable baud rates up to 2400 bps ❐ Powerline Optimized Network Protocol ❐ Integrates Data Link, Transport, and Network Layers ❐ Supports Bidirectional Half Duplex Communication ❐ 8-bit CRC Error Detection to Minimize Data Loss 2 ❐ I C enabled Powerline Application Layer 2 ❐ Supports I C Frequencies of 50, 100, and 400 kHz ❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC Powerlines ❐ Reference Designs comply with CENELEC EN 50065-1:2001 and FCC Part 15 ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ Two 8x8 Multiply, 32-Bit Accumulate ® ■ Programmable System Resources (PSoC Blocks) ❐ 12 Rail-to-Rail Analog PSoC Blocks provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ 16 Digital PSoC Blocks provide: • 8 to 32-Bit Timers, Counters, and PWMs • CRC and PRS Modules • Up to Four Full Duplex UARTs • Multiple SPITM Masters or Slaves • Connectable to all GPIO Pins ❐ Complex Peripherals by Combining Blocks ■ Flexible On-Chip Memory ❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles ❐ 2 KB SRAM Data Storage ❐ EEPROM Emulation in Flash ■ Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 12 Analog Inputs on GPIO ❐ Configurable Interrupt on all GPIO ■ ■ Additional System Resources 2 ❐ I C Slave, Master, and Multi-Master to 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full Featured In-Circuit Emulator (ICE) and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128 KB Trace Memory ❐ Complex Events ❐ C Compilers, Assembler, and Linker ■ Logic Block Diagram Powerline Communication Solution Embedded Application Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. PLC Core Powerline Transceiver Packet PSoC Core AC/DC Powerline Coupling Circuit (110V/240V AC, 12V/24V AC/DC etc.) Powerline Cypress Semiconductor Corporation Document Number: 001-48325 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 05, 2009 [+] [+] Feedback CY8CPLC20 Powerline Network Protocol Programmable System Resources CY8CPLC20 1. PLC Functional Overview The CY8CPLC20 is an integrated Powerline Communication (PLC) chip with the Powerline Modem PHY and Network Protocol Stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress's revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip. The physical layer of the Cypress PLC solution is implemented using an FSK modem that enables half duplex communication on any high voltage and low voltage powerline. This modem supports raw data rates up to 2400 bps. A block diagram is shown in Figure 1-2. Figure 1-2. Physical Layer FSK Modem Block Diagram Network Protocol 1.1 Robust Communication using Cypress’s PLC Solution Powerlines are available everywhere in the world and are a widely available communication medium for PLC technology. The pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of powerlines around the world, implementing robust communication has been an engineering challenge for years. The Cypress PLC solution enables secure and reliable communications. Cypress PLC features that enable robust communication over powerlines include: ■ Digital Receiver Digital Transmitter Logic ‘1’ or Logic ‘0’ Modulator Square Wave at FSK Frequencies Hysteresis Comparator Low Pass Filter Powerline Modem PHY Local Oscillator External Low Pass Filter Correlator Transmitter Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low voltage powerlines. Powerline optimized network protocol that supports bidirectional communication with acknowledgement-based signaling. In case of data packet loss due to bursty noise on the powerline, the transmitter has the capability to retransmit data. The Powerline Network Protocol also supports an 8-bit CRC for error detection and data packet retransmission. A Carrier Sense Multiple Access (CSMA) scheme is built into the network protocol that minimizes collisions between packet transmissions on the powerline and supports multiple masters and reliable communication on a bigger network. IF Band Pass Filter Mixer HF Band Pass Filter RX Amplifier Local Oscillator Programmable Gain Amplifier ■ ■ ■ Coupling Circuit 1.2.1 Transmitter Section Digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ‘1’ or low level logic ‘0’. It then generates a square wave at 133.3 kHz (logic ‘0’) or 131.8 kHz (logic ‘1’), which is fed to the Programmable Gain Amplifier to generate FSK modulated signals. This enables tunable amplification of the signal depending on the noise in the channel. The logic ‘1’ frequency can also be configured as 130.4 kHz for wider FSK deviation. 1.2.2 Receiver Section The incoming FSK signal from the powerline is input to a high frequency (HF) band pass filter that filters out-of-band frequency components and outputs a filtered signal within the desired spectrum of 125 kHz to 140 kHz for further demodulation. The mixer block multiplies the filtered FSK signals with a locally generated signal to produce heterodyned frequencies. 1.2 Powerline Modem PHY Figure 1-1. Physical Layer FSK Modem Powerline Communication Solution Embedded Application Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. PLC Core PSoC Core Powerline Transceiver Packet Document Number: 001-48325 Rev. *E CY8CPLC20 Powerline Network Protocol Programmable System Resources Receiver Page 2 of 44 [+] [+] Feedback CY8CPLC20 The intermediate frequency (IF) band pass filters further remove out-of-band noise as required for further demodulation. This signal is fed to the correlator, which produces a DC component (consisting of logic ‘1’ and ‘0’) and a higher frequency component. The output of the correlator is fed to a low pass filter (LPF) that outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. The output of the LPF is digitized by the hysteresis comparator. This eliminates the effects of correlator delay and false logic triggers due to noise. The digital receiver deserializes this data and outputs to the network layer for interpretation. 1.2.3 Coupling Circuit Reference Design The coupling circuit couples low voltage signals from the CY8CPLC20 to the powerline. The topology of this circuit is determined by the voltage on the powerline and design constraints mandated by powerline usage regulations. Cypress provides reference designs for a range of powerline voltages including 110V/240V AC and 12V/24V AC/DC. The CY8CPLC20 is capable of data communication over other AC/DC Powerlines as well with the appropriate external coupling circuit. The 110V AC and 240V AC designs are compliant to the following powerline usage regulations: ■ ■ The network protocol implemented on the CY8CPLC20 supports the following features: ■ ■ ■ ■ ■ ■ ■ ■ ■ Bidirectional half-duplex communication Master-slave or peer-to-peer network topologies Multiple masters on powerline network 8-bit logical addressing supports up to 256 powerline nodes 16-bit extended logical addressing supports up to 65536 powerline nodes 64-bit physical addressing supports up to 264 powerline nodes Individual, broadcast or group mode addressing Carrier Sense Multiple Access (CSMA) Full control over transmission parameters ❐ Acknowledged ❐ Unacknowledged ❐ Repeated Transmit CSMA – The protocol provides the random selection of a period between 85 and 115 ms (out of seven possible values in this range) in which the Band-In-Use (BIU) detector must indicate that the line is not in use, before attempting a transmission. BIU – A Band-In-Use detector, as defined under CENELEC EN 50065-1, is active whenever a signal that exceeds 86 dBmVrms anywhere in the range 131.5 kHz to 133.5 kHz is present for at least 4 ms. This threshold can be configured for different end-system applications not requiring CENELEC compliance.The modem tries to retransmit after every 85 to 115 ms when the band is in use. The transmitter times out after 1.1 seconds to 3 seconds (depending on the noise on the Powerline) and generates an interrupt to indicate that the transmitter was unable to acquire the powerline. 1.3.1 CSMA and Timing Parameters ■ FCC Part 15 for North America EN 50065-1:2001 for Europe ■ 1.3 Network Protocol Cypress’s powerline optimized network protocol performs the functions of the data link and network layers in an ISO/OSI-equivalent model. Figure 1-3. Powerline Network Protocol Powerline Communication Solution Embedded Application 1.3.2 Powerline Transceiver Packet Powerline Network Protocol Programmable System Resources Digital and Analog Peripherals CY8CPLC20 The powerline network protocol defines a Powerline Transceiver (PLT) packet structure, which is used for data transfer between nodes across the powerline. Packet formation and data transmission across the powerline network are implemented internally in CY8CPLC20. A PLT packet is divided into a variable length header (minimum 6 bytes to maximum 20 bytes, depending on address type), a variable length payload (minimum 0 bytes to maximum 31 bytes), and a packet CRC byte. This packet (preceded by a one byte preamble “0xAB”) is then transmitted by the powerline modem PHY and the external coupling circuit across the powerline. The format of the PLT packet is shown in Table 1-1 on page 4. Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. PLC Core PSoC Core Powerline Transceiver Packet Document Number: 001-48325 Rev. *E Page 3 of 44 [+] [+] Feedback CY8CPLC20 Table 1-1. Powerline Transceiver (PLT) Packet Structure Byte Offset 7 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Payload (0 to 31 Bytes) Powerline Transceiver Packet CRC RSVD Seq Num SA Type 6 5 4 Bit Offset 3 2 1 0 1.3.6 Sequence Numbering The sequence number is increased for every new unique packet transmitted. If in acknowledged mode and an acknowledgment is not received for a given packet, that packet is re-transmitted (if TX_Retry > 0) with the same sequence number. If in unacknowledged mode, the packet is transmitted (TX_Retry + 1) times with the same sequence number. If the receiver receives consecutive packets from the same source address with the same sequence number and packet CRC, it does not notify the host of the reception of the duplicate packet. If in acknowledged mode, it still sends an acknowledgment so that the transmitter knows that the packet was received. 1.3.7 Addressing The CY8CPLC20 has three modes of addressing: ■ DA Type Service RSVD RSVD Response RSVD Type Destination Address (8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical) Source Address (8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical) Command Payload Length Powerline Packet Header CRC Logical addressing: Every CY8CPLC20 node can have either a 8-bit logical address or a 16-bit logical address. The logical address of the PLC Node is set by the local application or by a remote node on the Powerline. Physical addressing: Every CY8CPLC20 has a unique 64-bit physical address. Group addressing: This is explained in the next section. 1.3.3 Packet Header The packet header contains the first 6 bytes of the packet when 1-byte logical addressing is used. When 8-byte physical addressing is used, the source and destination addresses each contain 8 bytes. In this case, the header can consist of a maximum of 20 bytes. Unused fields marked RSVD are for future expansion and are transmitted as bit 0. Table 1-2 describes the PLT packet header fields in detail. Table 1-2. Powerline Transceiver (PLT) Packet Header Field Name SA Type DA Type No. of Tag Bits 1 Source Address Type 2 Destination Address Type 1 1 Response Description 0 – Logical Addressing 1 – Physical Addressing 00 – Logical Addressing 01 – Group Addressing 10 – Physical Addressing 11 – Invalid 0 – Unacknowledged Messaging 1 – Acknowledged Messaging 0 - Not an acknowledgement or response packet 1 - Acknowledgement or response packet 4-bit unique identifier for each packet between source and destination. 4-bit CRC value. This enables the receiver to suspend receiving the rest of the packet if its header is corrupted ■ ■ 1.3.8 Group Membership Group membership enables the user to multicast messages to select groups. The CY8CPLC20 supports two types of group addressing: ■ Single Group Membership – The network protocol supports up to 256 different groups on the network in this mode. In this mode, each PLC node can only be part of a single group. For example, multiple PLC nodes can be part of Group 131. Multiple Group Membership – The network protocol supports eight different groups in this mode and each PLC node can be a part of multiple groups. For example, a single PLC node can be a part of Group 3, Group 4, and Group 7 at the same time. ■ Service Type Response Both these membership modes can also be used together for group membership. For example, a single PLC node can be a part of Group 131 and also multiple groups such as Group 3, Group 4, and Group 7. The group membership ID for broadcasting messages to all nodes in the network is 0x00. The service type is always set to Unacknowledgment Mode in Group Addressing Mode. This is to avoid acknowledgment flooding on the powerline during multicast. 1.3.9 Remote Commands In addition to sending normal data over the Powerline, the CY8CPLC10 can also send (and request) control information to (and from) another node on the network. The type of remote command to transmit is set by the TX_CommandID register and when received, is stored in the RX_CommandID register. When a control command (Command ID = 0x01-0x08 and 0x0C-0x0F) is received, the protocol automatically processes the packet (if Lock_Configuration is '0'), responds to the initiator, and notifies the host of the successful transmission and reception. Page 4 of 44 Seq Num Header CRC 4 4 Sequence Number 1.3.4 Payload The packet payload has a length of 0 to 31 bytes. Payload content is user defined and can be read or written through I2C. 1.3.5 Packet CRC The last byte of the packet is an 8-bit CRC value used to check packet data integrity. This CRC calculation includes the header and payload portions of the packet and is in addition to the powerline packet header CRC. Document Number: 001-48325 Rev. *E [+] [+] Feedback CY8CPLC20 When the send data command (ID 0x09) or request for data command (ID 0x0A) is received, the protocol replies with an acknowledgment packet (if TX_Service_Type = '1'), and notify the host of the new received data. If the initiator doesn't receive the acknowledgment packet within 500ms, it notifies the host of the no acknowledgment received condition. When a response command (ID 0x0B) is received by the initiator within 1.5s of sending the request for data command, the protocol notifies the host of the successful transmission and reception. If the response command is not received by the initiator within 1.5s, it notifies the host of the no response received condition. Table 1-3. Remote Commands Cmd ID 0x01 Command Name SetRemote_TXEnable Description The host is notified by updating the appropriate values in the INT_Status register (including Status_Value_Change). The command IDs 0x30-0xff can be used for custom commands that would be processed by the external host (e.g. set an LED color, get a temperature/voltage reading). The available remote commands are described in Table 1-3 with the respective Command IDs. Payload (TX Data) Response (RX Data) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) Sets the TX Enable bit in the 0 - Disable Remote TX PLC Mode Register. Rest of the 1 - Enable Remote TX PLC Mode register is unaffected Set the Addressing to Extended Addressing Mode 0 - Disable Extended Addressing 1 - Enable Extended Addressing If Ext Address = 0, Payload = 8-bit Logical Address If Ext Address = 1, Payload = 16-bit Logical Address 0x03 SetRemote_ExtendedAddr 0x04 SetRemote_LogicalAddr Assigns the specified logical address to the remote PLC node 0x05 GetRemote_LogicalAddr Get the Logical Address of the None remote PLC node If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, {If Ext Address = 0, Response = 8-bit Logical Address If Ext Address = 1, Response = 16-bit Logical Address} If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = 64-bit Physical Address If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Remote PLC Mode register If TX Enable = 0, Response = None If TX Enable = 1, Response = Remote Version register If Local Service Type = 0, Response = None If Local Service Type = 1, Response = Ack 0x06 GetRemote_PhysicalAddr Get the Physical Address of the None remote PLC node 0x07 GetRemote_State Request PLC_Mode Register content from a Remote PLC node None 0x08 GetRemote_Version Get the Version Number of the None Remote Node 0x09 SendRemote_Data Transmit data to a Remote Node. Payload = Local TX Data Document Number: 001-48325 Rev. *E Page 5 of 44 [+] [+] Feedback CY8CPLC20 Table 1-3. Remote Commands (continued) Cmd ID 0x0A Command Name RequestRemote_Data Description Request data from a Remote Node Payload (TX Data) Payload = Local TX Data Response (RX Data) If Local Service Type = 1, Response = Ack Then, the remote node host must send a ResponseRemote_Data command. The response must be completely transmitted within 1.5s of receiving the request. Otherwise, the requesting node will time out. None 0x0B 0x0C ResponseRemote_Data SetRemote_BIU Transmit response data to a Remote Node. Payload = Local TX Data Enables/Disables BIU function- 0 - Enable Remote BIU If Remote Lock Config = 0, ality at the remote node 1 - Disable Remote BIU Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) Sets the Threshold Value at the 3-bit Remote Remote node Threshold Value If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x0D SetRemote_ThresholdValue 0x0E SetRemote_GroupMembership Sets the Group Membership of Byte0 - Remote SIngle the Remote node Group Membership Address Byte1- Remote Multiple Group Membership Address GetRemote_GroupMembership Gets the Group Membership of None the Remote node 0x0F If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Byte0 - Remote SIngle Group Membership Address Byte1- Remote Multiple Group Membership Address 0x10 0x2F 0x30 0xFF Reserved User Defined Command Set Document Number: 001-48325 Rev. *E Page 6 of 44 [+] [+] Feedback CY8CPLC20 2. PSoC Core The CY8CPLC20 is based on the Cypress PSoC® 1 architecture. The PSoC platform consists of many Programmable System-on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/Os are included in a range of convenient pinouts and packages. The PSoC architecture, as shown in Figure 2-1., consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing enables all the device resources to be combined into a complete custom system. The CY8CPLC20 family can have up to five I/O ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O). Figure 2-1. PSoC Core Analog Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Drivers The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a 4 MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 25 vectors, to simplify programming of realtime embedded events. Program execution is timed and protected using the included Sleep and Watchdog timers (WDT). Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using Flash. Program Flash uses four protection levels on blocks of 64 bytes, enabling customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5 percent over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for the digital system use. A low power 32 kHz ILO (internal low speed oscillator) is provided for the sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. When operating the Powerline Transceiver (PLT) user module, the ECO must be selected to ensure accurate protocol timing. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, enabling great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. SYSTEM BUS Global Digital Interconnect SRAM 2K Interrupt Controller 2.1 Programmable System Resources Global Analog Interconnect Flash 32K Figure 2-2. Programmable System Resources SROM PSoC CORE Sleep and Watchdog CPU Core (M8C) Embedded Application Powerline Network Protocol Programmable System Resources Digital and Analog Peripherals Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Analog Block Array PLC Core Analog Input Muxing PSoC Core Powerline Transceiver Packet Digital Clocks Two Multiply Accums. POR and LVD Decimator I 2C System Resets Internal Voltage Ref. SYSTEM RESOURCES Document Number: 001-48325 Rev. *E Page 7 of 44 [+] [+] Feedback CY8CPLC20 2.1.1 The Digital System The digital system contains 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone, or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals called user module references. Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Figure 2-3. Digital System Block Diagram Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 PWMs (8 to 32 bit) PWMs with Dead Band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to four) SPI master and slave (up to four each) I2C slave and multi-master (one available as a System Resource) Cyclical Redundancy Checker and Generator (8 to 32 bit) IrDA (up to four) Pseudo Random Sequence Generators (8 to 32 bit) 8 8 Digital Clocks FromCore To SystemBus ToAnalog System DIGITAL SYSTEM Digital PSoCBlock Array Row Input Configuration Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration 8 8 Row Output Configuration Row Input Configuration Row 1 DBB10 DBB11 DCB12 4 DCB13 4 Row Input Configuration The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and perform logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Row 2 DBB20 DBB21 DCB22 4 DCB23 4 Row Output Configuration Row Input Configuration Row 3 DBB30 DBB31 DCB32 4 DCB33 4 Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Document Number: 001-48325 Rev. *E Page 8 of 44 [+] [+] Feedback CY8CPLC20 2.1.2 The Analog System The analog system contains 12 configurable blocks, each containing an opamp circuit, enabling the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Figure 2-4. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] Analog-to-digital converters (up to four, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band pass, low pass, and notch) Amplifiers (up to four, with selectable gain to 48x) Instrumentation amplifiers (up to two, with selectable gain to 93x) Comparators (up to four, with 16 selectable thresholds) DACs (up to four, with 6- to 9-bit resolution) Multiplying DACs (up to four, with 6- to 9-bit resolution) High current output drivers (4 with 40 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible P2[3] P2[4] P2[2] P2[0] P2[1] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23 Analog blocks are provided in columns of three, which includes one CT (continuous time) and two SC (switched capacitor) blocks, as shown in the Figure 2-4.. Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48325 Rev. *E Page 9 of 44 [+] [+] Feedback CY8CPLC20 2.2 Additional System Resources Figure 2-5. CY8CPLC20: Additional System Resources Powerline Communication Solution Embedded Application Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. PLC Core PSoC Core Powerline Transceiver Packet System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Resources include a multiplier, decimator, low voltage detection, and power on reset. The following statements describe the merits of each system resource. ■ For up to date ordering, packaging, and electrical specification information, see the latest PLC device data sheets on the web at www.cypress.com/go/plc. 3.1 Application Notes Application notes are an excellent introduction to the wide variety of possible PLC designs. They are located here: www.cypress.com/go/plc. Select Application Notes under the Support tab. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are supported. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. ■ ■ 3.2 Development Kits PLC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. ■ 3.3 Training Free PLC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. ■ ■ 3.4 CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. 3. Getting Started The quickest way to understand Cypress’s Powerline Communication offering is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). The latest version of PSoC Designer can be downloaded from www.cypress.com/psocdesigner. PSoC Designer 5.0 SP5 or later provides support for CY8CPLC20 devices. This data sheet is an overview of the CY8CPLC20 integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PLC Technical Reference Manual. 3.5 Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. 3.6 Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Page 10 of 44 Document Number: 001-48325 Rev. *E CY8CPLC20 Powerline Network Protocol Programmable System Resources [+] [+] Feedback CY8CPLC20 4. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built in support for third party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. 4.1.4 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 4.1.5 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 4.1.6 Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. 4.1 PSoC Designer Software Subsystems 4.1.1 System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Programmable System-on-Chip Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. 4.1.2 Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. 4.1.3 Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. 4.2 In-Circuit Emulator (ICE) A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 001-48325 Rev. *E Page 11 of 44 [+] [+] Feedback CY8CPLC20 5. Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select Components 2. Configure Components 3. Organize and Connect 4. Generate, Verify, and Debug 5.3 Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. 5.1 Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. 5.4 Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. 5.2 Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. Document Number: 001-48325 Rev. *E Page 12 of 44 [+] [+] Feedback CY8CPLC20 5.5 PLC User Modules The CY8CPLC20 has the Powerline Transceiver (PLT) User Module in PSoC Designer 5.0 SP5 or later. The PLT User Module (UM) enables data communication over powerlines up to baud rates of 2400 bps. This UM also exposes all the APIs from the network protocol for ease of application development. The UM, when instantiated, provides the user with three implementation modes: ■ ■ FSK Modem + Network Stack – This mode enables the user to use the Cypress network protocol for PLC and build any application with the APIs provided by the network protocol. FSK Modem + Network Stack + I2C – This mode enables the user to interface the CY8CPLC20 with any other microcontroller or PSoC device. Users can also split the application between the PLC device and the external microcontroller. If the external microcontroller is a PSoC device, then the I2C UMs can be used to interface it with the PLC device. ■ FSK Modem Only – This mode enables the user to use the raw FSK modem and build any network protocol or application with the help of the APIs generated by the modem PHY. Figure 5-1. on page 13 shows the starting window for the PLT UM with the three implementation modes from which the user can choose. Figure 5-1. PLT User Module The power consumption estimate of the CY8CPLC20 chip with the PLT User Module loaded along with the other User Modules can be determined using the application note AN55403 titled "Estimating CY8CPLC20/CY8CLED16P01 Power Consumption". 1. Pin Information Document Number: 001-48325 Rev. *E Page 13 of 44 [+] [+] Feedback CY8CPLC20 6. Document Conventions 6.1 Acronyms Used This table lists the acronyms used in this data sheet. Table 6-1. Acronyms Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO ICE IDE I/O ISSP IPOR LSb LVD MSb PC PGA POR PPOR PSoC® PWM ROM SC SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose I/O in-circuit emulator integrated development environment input/output in-system serial programming imprecise power on reset least-significant bit low voltage detect most-significant bit program counter programmable gain amplifier power on reset precision power on reset Programmable System-on-Chip pulse width modulator read only memory switched capacitor static random access memory 6.2 Units of Measure A units of measure table is located in the section Electrical Specifications on page 22. 6.3 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Document Number: 001-48325 Rev. *E Page 14 of 44 [+] [+] Feedback CY8CPLC20 7. Pin Information The CY8CPLC20 PLC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd and XRES are not capable of Digital I/O. 7.1 28-Pin Part Pinout Table 7-1. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 Type Digital Analog I/O I Reserved O I/O I O Pin Name P0[7] RSVD FSK_OUT P0[1] TX_SHUTD OWN Description Analog Column Mux Input Reserved Analog FSK Output Analog Column Mux Input Output to disable PLC transmit circuitry in receive mode Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting Direct switched capacitor block input Direct switched capacitor block input Reserved I2C Serial Clock (SCL) I2C Serial Data (SDA) XTAL_STABILITY. Connect a 0.1 μF capacitor between the pin and Vss. Crystal (XTALin[2]), ISSP-SCLK[1], I2C SCL Ground connection. Crystal (XTALout[2]), ISSP-SDATA[1], I2C SDA Optional External Clock Input (EXTCLK[2]) Active high external reset with internal pull down Analog Output to external Low Pass Filter Circuitry Analog Input from the external Low Pass Filter Circuitry Analog Ground External Voltage Reference (VREF) Reserved Reserved Analog column mux input and column output Analog FSK Input Supply Voltage Figure 7-1. CY8CPLC20 28-Pin PLC Device A , I , P0[7] RSVD FSK_OUT A, I , P0[1] TX_ SHUTDOWN P2[5] A, I , P2[3] A , I,P2[1] RSVD I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I I P2[5] P2[3] P2[1] RSVD P1[7] P1[5] P1[3] P1[1] Reserved I/O I/O I/O I/O Power I/O I/O I/O I/O Input O I Analog Ground I/O Reserved Reserved I/O I/O I Power 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd FSK_IN P0[4] , A , IO RSVD RSVD P2[6] , External VREF AGND RXCOMP _IN RXCOMP OUT _ XRES P1[6] P1[4] , EXTCLK P1[2] P1[0] , XTALout, I2C SDA Vss P1[0] P1[2] P1[4] P1[6] XRES RXCOMP_ OUT RXCOMP_ IN AGND P2[6] RSVD RSVD P0[4] FSK_IN Vdd LEGEND: A = Analog, I = Input, O = Output., RSVD = Reserved (Should be left unconnected) Notes 1. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details. 2. When using the PLT user module, the external crystal is always required for protocol timing. For the FSK modem, either enable the PLL Mode or select the external 24 MHz on P1[4]. Do not use the IMO. Document Number: 001-48325 Rev. *E Page 15 of 44 [+] [+] Feedback CY8CPLC20 7.2 48-Pin Part Pinout Table 7-2. 48-Pin Part Pinout (QFN )[3] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Type Digital Analog I/O I I/O I I/O I/O I/O I/O Reserved I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] RSVD P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] Description Direct switched capacitor block input Direct switched capacitor block input Figure 7-2. CY8CPLC20 48-Pin PLC Device P2[5] TX_SHUTDOWN P0[1], A, I FSK_OUT RSVD P0[7], A, I RSVD P2[6], External VREF 36 35 34 33 32 31 30 29 28 27 26 25 AGND RXCOMP _IN RXCOMP OUT _ P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] Reserved P5[1] I2C SCL, P1[7] I2C SDA, P1[5] Optional External Clock Input (EXTCLK[2]) 27 28 29 30 31 32 33 34 I/O I/O Input I/O I/O I/O I/O O P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] RXCOM P_OUT RXCOM P_IN AGND P2[6] RSVD RSVD P0[4] Active high external reset with internal pull down Analog Output to external Low Pass Filter Circuitry 35 I Analog Input from external Low Pass Filter Circuitry 36 Analog Ground Analog Ground 37 I/O External Voltage Reference (VREF) 38 Reserved Reserved 39 Reserved Reserved 40 I/O I/O Analog column mux input and column output 41 I FSK_IN Analog FSK Input 42 Power Vdd Supply Voltage 43 I/O I P0[7] Analog column mux input 44 Reserved RSVD Reserved 45 O FSK_OU Analog FSK Output T] 46 I/O I P0[1] Analog column mux input 47 O TX_SHU Output to disable transmit circuitry in TDOWN receive mode Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting 48 I/O P2[5] LEGEND: A = Analog, I = Input, O = Output, RSVD = Reserved (should be left unconnected). Note 3. The QFN package has a center pad that must be connected to ground (Vss). Document Number: 001-48325 Rev. *E P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2] I2C Serial Clock (SCL) I2C Serial Data (SDA) XTAL_STABILITY. Connect a 0.1 μF capacitor between the pin and Vss. Crystal (XTALin[2]), I2C Serial Clock (SCL), ISSP-SCLK[1] Ground connection. Crystal (XTALout[2]), I2C Serial Data (SDA), ISSP-SDATA[1] A , I , P2[3] A , I , P2[1] P4[7] P4[5] P4[3] P4[1] RSVD P3[7] P3[5] P3[3] P3[1] P5[3] 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 QFN ( Top View ) Vdd FSK_IN P0[4], A, IO RSVD Page 16 of 44 [+] [+] Feedback CY8CPLC20 7.3 100-Pin Part Pinout (On-Chip Debug) The 100-pin TQFP part is for the CY8CPLC20-OCD On-Chip Debug PLC device. Note that the OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production. Table 7-3. 100-Pin OCD Part Pinout (TQFP) Analog Pin No. 1 2 3 4 Name Description Analog Digital Digital Pin No. 51 52 53 54 Name Description I/O O I/O I/O I/O I/O I/O I/O I/O I NC NC P0[1] TX_SHUT DOWN No Connection No Connection Analog Column Mux Input Output to disable transmit circuitry in receive mode Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting Direct switched capacitor block input Direct switched capacitor block input I/O I/O I/O I/O I/O I/O I/O I/O NC P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] Vss P4[4] P4[6] RXCOM P_OUT RXCOM P_IN AGND NC P2[6] NC RSVD NC NC RSVD NC P0[4] NC No Connection 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO Reserved RSVD Power Vss I/O P3[7] I/O P3[5] I/O P3[3] I I I/O I/O I/O I/O I/O I/O P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] NC NC NC P1[5] P1[3] P1[1]* NC Vdd NC Vss NC P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0]* P1[2] P1[4] P1[6] NC NC NC OCD even data I/O OCD odd data output Reserved Ground Connection 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Input I/O I/O Power I/O I/O O I Ground I/O Reserved OCD high speed clock output OCD CPU clock output Active high pin reset with internal pull down Ground Connection Analog Output to external Low Pass Filter Circuitry Analog Input from external Low Pass Filter Circuitry Analog Ground No Connection External Voltage Reference (VREF) input No Connection Reserved No Connection No Connection Reserved No Connection Analog column mux input and column output, VREF No Connection Analog FSK Input Supply Voltage Supply Voltage Ground Connection Ground Connection I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I2C Serial Clock (SCL) No Connection No Connection No Connection I2C Serial Data (SDA) IFMTEST, XTAL_STABILITY. Connect a 0.1 μF capacitor between the pin and Vss. Crystal (XTALin[2]), I2C Serial Clock (SCL), TC SCLK No Connection Supply Voltage No Connection Ground Connection No Connection Reserved I/O I/O Crystal (XTALout[2]), I2C Serial Data (SDA), TC SDATA VFMTEST Optional External Clock Input (EXTCLK[2]) No Connection No Connection No Connection I Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O FSK_IN Vdd Vdd Vss Vss P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] NC P0[7] NC RSVD NC FSK_OU T NC No Connection Analog Column Mux Input No Connection Reserved No Connection Analog FSK Output No Connection I/O I Reserved O LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test, RSVD = Reserved (should be left unconnected). Document Number: 001-48325 Rev. *E Page 17 of 44 [+] [+] Feedback CY8CPLC20 Figure 7-3. CY8CPLC20-OCD Vdd Vdd FSK_IN NC P0[4], AIO NC RSVD NC 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC RSVD NC P2[6] , External VREF NC AGND RXCOMP _IN RXCOMP OUT _ P4[6] P4[4] Vss P4[2] P4[0] XRES CCLK HCLK P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0] NC NC NC NC FSK_OUT NC RSVD NC P0[7], AI NC P6[7] P6[6] P6[5] P6[4] P6[3] 100 99 98 97 96 95 94 93 92 91 90 89 88 26 27 28 29 30 31 32 33 34 35 NC NC I2C SDA, P1[5] P1[3] XTALin, I2C SCL, P1[1] NC Vdd NC Vss NC Not for Production Document Number: 001-48325 Rev. *E P7[3] P7[2] P7[1] P7[0] XTALout, I2C SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6] NC P7[7] P7[6] P7[5] P7[4] 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 TX_ SHUTDOWN 4 P2[5] 5 AI , P2[3] 6 AI , P2[1] 7 P4[7] 8 P4[5] 9 10 P4[3] P4[1] 11 OCDE 12 OCDO 13 RSVD 14 Vss 15 P3[7] 16 P3[5] 17 P3[3] 18 P3[1] 19 P5[7] 20 P5[5] 21 22 P5[3] P5[1] 23 I2 C SCL, P1[7] 24 NC 25 NC NC AI , P0[1] OCD TQFP 87 86 85 84 83 82 81 80 79 78 P6[2] P6[1] P6[0] Vss Vss Page 18 of 44 [+] [+] Feedback CY8CPLC20 8. Register Reference This section lists the registers of the CY8CPLC20 PLC device. For detailed register information, reference the PLC Technical Reference Manual. 8.1 Register Conventions 8.1.1 Abbreviations Used The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific 8.2 Register Mapping Tables The CY8CPLC20 device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Table 8-1. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW DBB20DR0 PRT0IE 01 RW DBB20DR1 PRT0GS 02 RW DBB20DR2 PRT0DM2 03 RW DBB20CR0 PRT1DR 04 RW DBB21DR0 PRT1IE 05 RW DBB21DR1 PRT1GS 06 RW DBB21DR2 PRT1DM2 07 RW DBB21CR0 PRT2DR 08 RW DCB22DR0 PRT2IE 09 RW DCB22DR1 PRT2GS 0A RW DCB22DR2 PRT2DM2 0B RW DCB22CR0 PRT3DR 0C RW DCB23DR0 PRT3IE 0D RW DCB23DR1 PRT3GS 0E RW DCB23DR2 PRT3DM2 0F RW DCB23CR0 PRT4DR 10 RW DBB30DR0 PRT4IE 11 RW DBB30DR1 PRT4GS 12 RW DBB30DR2 PRT4DM2 13 RW DBB30CR0 PRT5DR 14 RW DBB31DR0 PRT5IE 15 RW DBB31DR1 PRT5GS 16 RW DBB31DR2 PRT5DM2 17 RW DBB31CR0 PRT6DR 18 RW DCB32DR0 PRT6IE 19 RW DCB32DR1 PRT6GS 1A RW DCB32DR2 PRT6DM2 1B RW DCB32CR0 PRT7DR 1C RW DCB33DR0 PRT7IE 1D RW DCB33DR1 PRT7GS 1E RW DCB33DR2 PRT7DM2 1F RW DCB33CR0 DBB00DR0 20 # AMX_IN DBB00DR1 21 W DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # Blank fields are Reserved and should not be accessed. 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW RW # # RW Addr (0,Hex) ASC10CR0 80 ASC10CR1 81 ASC10CR2 82 ASC10CR3 83 ASD11CR0 84 ASD11CR1 85 ASD11CR2 86 ASD11CR3 87 ASC12CR0 88 ASC12CR1 89 ASC12CR2 8A ASC12CR3 8B ASD13CR0 8C ASD13CR1 8D ASD13CR2 8E ASD13CR3 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 ASD22CR0 98 ASD22CR1 99 ASD22CR2 9A ASD22CR3 9B ASC23CR0 9C ASC23CR1 9D ASC23CR2 9E ASC23CR3 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 # Access is bit specific. Name Access Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X W Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W Document Number: 001-48325 Rev. *E Page 19 of 44 [+] [+] Feedback CY8CPLC20 Table 8-1. Register Map Bank 0 Table: User Space (continued) Name Addr (0,Hex) Access Name Addr (0,Hex) Access DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Name Access Name W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F CPU_SCR1 CPU_SCR0 Addr (0,Hex) E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access W R R RW RW RW RW RL # # Table 8-2. Register Map Bank 1 Table: Configuration Space PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU Addr Access Name (1,Hex) 00 RW DBB20FN 01 RW DBB20IN 02 RW DBB20OU 03 RW 04 RW DBB21FN 05 RW DBB21IN 06 RW DBB21OU 07 RW 08 RW DCB22FN 09 RW DCB22IN 0A RW DCB22OU 0B RW 0C RW DCB23FN 0D RW DCB23IN 0E RW DCB23OU 0F RW 10 RW DBB30FN 11 RW DBB30IN 12 RW DBB30OU 13 RW 14 RW DBB31FN 15 RW DBB31IN 16 RW DBB31OU 17 RW 18 RW DCB32FN 19 RW DCB32IN 1A RW DCB32OU 1B RW 1C RW DCB33FN 1D RW DCB33IN 1E RW DCB33OU 1F RW 20 RW CLK_CR0 21 RW CLK_CR1 22 RW ABF_CR0 23 AMD_CR0 Blank fields are Reserved and should not be accessed. Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 # Access is bit specific. Name Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Document Number: 001-48325 Rev. *E Page 20 of 44 [+] Feedback CY8CPLC20 Table 8-2. Register Map Bank 1 Table: Configuration Space (continued) Addr Access Name (1,Hex) DBB01FN 24 RW DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW ALT_CR1 DCB02IN 29 RW CLK_CR2 DCB02OU 2A RW 2B DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 DBB10FN 30 RW ACB00CR3 DBB10IN 31 RW ACB00CR0 DBB10OU 32 RW ACB00CR1 33 ACB00CR2 DBB11FN 34 RW ACB01CR3 DBB11IN 35 RW ACB01CR0 DBB11OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW ACB02CR3 DCB12IN 39 RW ACB02CR0 DCB12OU 3A RW ACB02CR1 3B ACB02CR2 DCB13FN 3C RW ACB03CR3 DCB13IN 3D RW ACB03CR0 DCB13OU 3E RW ACB03CR1 3F ACB03CR2 Blank fields are Reserved and should not be accessed. Name 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Addr (1,Hex) Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Name Access Name VLT_CMP DEC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW FLS_PR1 CPU_SCR1 CPU_SCR0 Addr (1,Hex) E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access R RW W W RW W RL RW # # Document Number: 001-48325 Rev. *E Page 21 of 44 [+] Feedback CY8CPLC20 9. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CPLC20 device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. The following table lists the units of measure that are used in this chapter. Table 9-1. Units of Measure Symbol °C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms Unit of Measure degrees Celsius decibels femtofarads hertz 1024 bytes 1024 bits kilohertz kilohms megahertz megaohms microamperes microfarads microhenrys microseconds microvolts microvolts root-mean-square Symbol μW mA ms mV nA ns nV Ω pA pF pp ppm ps sps σ V Unit of Measure microwatts milliamperes millisecond millivolts nanoamperes nanoseconds nanovolts ohms picoamperes picofarads peak-to-peak parts per million picoseconds samples per second sigma: one standard deviation volts 9.1 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9-2. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrade reliability. TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss 0.5 Vss 0.5 -25 -50 2000 – – – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 – 200 °C V V V mA mA V mA Human Body Model ESD. Document Number: 001-48325 Rev. *E Page 22 of 44 [+] [+] Feedback CY8CPLC20 9.2 Operating Temperature Table 9-3. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 39.The user must limit the power consumption to comply with this requirement. 9.3 DC Electrical Characteristics 9.3.1 DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-4. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 4.75 – Typ – 8 Max 5.25 14 Units V mA Notes Conditions are 5.0V, TA = 25°C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz Trimmed for appropriate Vdd VREF Reference Voltage (Bandgap) 1.28 1.3 1.32 V 9.3.2 DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature range: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-5. DC GPIO Specifications Symbol RPU RPD VOH Description Pull Up Resistor Pull Down Resistor High Output Level Min 4 4 Vdd 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes VOL Low Output Level – – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High Level Source Current Low Level Source Current Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output 10 25 – 2.1 – – – – – – – – 60 1 3.5 3.5 – – 0.8 – – 10 10 mA mA V V mV nA pF pF IOH = 10 mA, (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. VOH = Vdd-1.0V, see the limitations of the total current in the note for VOH VOL = 0.75V, see the limitations of the total current in the note for VOL Gross tested to 1 μA. Package and pin dependent. Temp = 25°C. Package and pin dependent. Temp = 25°C. Document Number: 001-48325 Rev. *E Page 23 of 44 [+] [+] Feedback CY8CPLC20 9.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-6. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (Absolute Value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range. All cases, except highest. Power = High, Opamp Bias = High Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (Internal Signals) Low Output Voltage Swing (Internal Signals) Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio Min – – – – – – 0.0 0.5 60 80 Vdd 0.01 – Typ 1.6 1.3 1.2 7.0 200 4.5 – – – – – – Max 10 8 7.5 35.0 – 9.5 Vdd Vdd 0.5 – – – 0.1 Units Notes TCVOSOA IEBOA CINOA VCMOA mV mV mV μV/°C pA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25°C. V V dB dB V V μA μA μA μA μA μA dB CMRROA GOLOA VOHIGHOA VOLOWOA ISOA PSRROA – – – – – – 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 – Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd. 9.3.4 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-7. DC Low Power Comparator Specifications Symbol Description VREFLPC Low Power Comparator (LPC) Reference Voltage Range ISLPC LPC Supply Current LPC Voltage Offset VOSLPC Min 0.2 – – Typ – 10 2.5 Max Vdd - 1 40 30 Units V μA mV Notes Document Number: 001-48325 Rev. *E Page 24 of 44 [+] [+] Feedback CY8CPLC20 9.3.5 DC Analog Output Buffer Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-8. DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Min Input Offset Voltage (Absolute Value) – Average Input Offset Voltage Drift – Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low – Power = High – High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low 0.5 x Vdd + 1.3 Power = High 0.5 x Vdd + 1.3 Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low – Power = High ISOB PSRROB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio – Typ 3 +6 – – – Max 12 – Vdd - 1.0 1 1 Units mV μV/°C V W W Notes – – – – V V VOLOWOB – – 0.5 x Vdd 1.3 0.5 x Vdd 1.3 2 5 – V V – – 40 1.1 2.6 64 mA mA dB 9.3.6 DC Analog Reference Specifications Table 9-9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 9-9. 5V DC Analog Reference Specifications Symbol VBG5 – – – – – – – – – – Description Bandgap Voltage Reference 5V AGND = Vdd/2[4] AGND = 2 x Bandgap[4] AGND = P2[4] (P2[4] = Vdd/2)[4] AGND = Bandgap[3] AGND = 1.6 x Bandgap[4] AGND Block to Block Variation (AGND = Vdd/2)[4] RefHi = Vdd/2 + Bandgap RefHi = 3 x Bandgap RefHi = 2 x Bandgap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + Bandgap (P2[4] = Vdd/2) Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 Units V V V V V V V V V V V Note 4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V Document Number: 001-48325 Rev. *E Page 25 of 44 [+] [+] Feedback CY8CPLC20 Table 9-9. 5V DC Analog Reference Specifications (continued) Symbol Description – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) – RefHi = 2 x Bandgap – RefHi = 3.2 x Bandgap – RefLo = Bandgap – RefLo = 2 x Bandgap - P2[6] (P2[6] = 1.3V) – – Min Typ Max P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6] + 0.058 0.058 2.50 2.60 2.70 4.02 4.16 4.29 BG - 0.082 BG + 0.023 BG + 0.129 2 x BG - P2[6] 2 x BG - P2[6] + 2 x BG - P2[6] + 0.084 0.025 0.134 RefLo = P2[4] – Bandgap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] P2[4] - P2[6] + P2[4] - P2[6] + 0.057 0.026 0.110 Units V V V V V V V 9.3.7 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-10. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min – – Typ 12.2 80 Max – – Units kΩ fF Notes 9.3.8 POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-11. DC POR and LVD Specifications Symbol VPPOR2R VPPOR2 VPH2 VLVD6 VLVD7 Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 10b Vdd value for LVD Trip VM[2:0] = 110b VM[2:0] = 111b Min – – – 4.63 4.72 Typ 4.55 4.55 0 4.73 4.81 Max – – – 4.82 4.91 Units V V mV V V Notes Document Number: 001-48325 Rev. *E Page 26 of 44 [+] [+] Feedback CY8CPLC20 9.3.9 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-12. DC Programming Specifications Symbol IDDP VILP Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying VILP to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying VIHP to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[5] FlashDR Flash Data Retention Min – – 2.2 – – – Vdd - 1.0 50,000 1,800,000 10 Typ 10 – – – – – – – – – Max 30 0.8 – 0.2 1.5 Vss + 0.75 Vdd – – – Units mA V V mA mA V V – – Years Erase/write cycles per block Erase/write cycles Driving internal pull down resistor Driving internal pull down resistor Notes Note 5. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-48325 Rev. *E Page 27 of 44 [+] [+] Feedback CY8CPLC20 9.4 AC Electrical Characteristics 9.4.1 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Note See the individual user module data sheets for information on maximum frequencies for user modules. Table 9-13. AC Chip-Level Specifications Symbol FIMO24 FIMO6 FCPU1 F48M F32K1 F32K2 F32K_U Description Internal Main Oscillator Frequency for 24 MHz Internal Main Oscillator Frequency for 6 MHz CPU Frequency (5V Nominal) Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator Internal Low Speed Oscillator (ILO) Untrimmed Frequency Min 23.4 5.5 0.93 0 15 – 5 Typ 24 6 24 48 32 32.768 – Max 24.6 6.5[6] 24.6[6] 49.2[6, 7] 64 – – Units MHz MHz MHz MHz kHz kHz kHz Accuracy is capacitor and crystal dependent. 50% duty cycle. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. A multiple (x732) of crystal frequency. Notes Trimmed for 5V operation using factory trim values. SLIMO Mode = 0. Trimmed for 5V operation using factory trim values. SLIMO Mode = 1. Refer to the AC Digital Block Specifications below. FPLL Jitter24M2 TPLLSLEW TPLLSLEWLOW TOS TOSACC PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm – – 0.5 0.5 – – 23.986 – – – 250 300 – 600 10 50 500 600 MHz ps ms ms ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the TOSACC period. Correct operation assumes a properly loaded 1 μW maximum drive level 32.768 kHz crystal. -40°C ≤ TA ≤ 85°C. Jitter32k TXRST DC24M DCILO Step24M Fout48M 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle Internal Low Speed Oscillator Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency – 10 40 20 – 46.8 100 – 50 50 50 48.0 – 60 80 – 49.2 ns μs % % kHz MHz Trimmed. Utilizing factory trim values. Notes 6. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 7. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-48325 Rev. *E Page 28 of 44 [+] [+] Feedback CY8CPLC20 Table 9-13. AC Chip-Level Specifications (continued) Symbol Jitter24M1 FMAX Description 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. SRPOWER_UP Power Supply Slew Rate TPOWERUP Time from end of POR to CPU executing code Min – – – – Typ 600 – – 16 Max 12.3 250 100 Units ps MHz V/ms ms Notes Vdd slew rate during power up. Power up from 0V. See the System Resets section of the PSoC Technical Reference Manual. Figure 9-1. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 9-2. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 9-3. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 9-4. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Document Number: 001-48325 Rev. *E Page 29 of 44 [+] [+] Feedback CY8CPLC20 Figure 9-5. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 9.4.2 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-14. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12.3 18 18 – – Units MHz ns ns ns ns Notes Normal Strong Mode 10% - 90% 10% - 90% 10% - 90% 10% - 90% Figure 9-6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Document Number: 001-48325 Rev. *E Page 30 of 44 [+] [+] Feedback CY8CPLC20 9.4.3 AC Operational Amplifier Specifications Table 9-15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 9-15. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units μs μs μs μs μs μs V/μs V/μs V/μs V/μs V/μs V/μs MHz MHz MHz nV/rt-Hz Notes – – – – – – 3.9 0.72 0.62 TSOA – – – – – – 5.9 0.92 0.72 SRROA 0.15 1.7 6.5 – – – – – – SRFOA 0.01 0.5 4.0 0.75 3.1 5.4 – – – – – – – 100 – – – – – – – BWOA ENOA When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 9-7. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 Document Number: 001-48325 Rev. *E Page 31 of 44 [+] [+] Feedback CY8CPLC20 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 9-8. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 9.4.3 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-16. AC Low Power Comparator Specifications Symbol TRLPC Description LPC Response Time Min – Typ – Max 50 Units μs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC. 9.4.4 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-17. AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) Maximum Input Clock Frequency 20 50 [8] Min Typ Max 49.2 Units MHz ns MHz MHz ns MHz MHz ns ns ns MHz MHz Notes 50[8] – – 50[8] – – – – – – – – – – – – – – 49.2 24.6 – 49.2 24.6 – – – 49.2 49.2 50[8] – – Document Number: 001-48325 Rev. *E Page 32 of 44 [+] [+] Feedback CY8CPLC20 Table 9-17. AC Digital Block Specifications (continued) Function CRCPRS (CRC Mode) SPIM SPIS Description Maximum Input Clock Frequency Min – Typ – Max 24.6 Units MHz Notes Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions – – 50 [8] – – – – – – – 8.2 4.1 – 24.6 49.2 24.6 49.2 MHz MHz ns MHz MHz MHz MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. Transmitter Maximum Input Clock Frequency Vdd ≥ 4.75V, 2 Stop Bits – – – – Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Receiver Maximum Input Clock Frequency Vdd ≥ 4.75V, 2 Stop Bits 9.4.5 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-18. 5V AC Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min – – Typ – – Max 4 4 Units μs μs μs μs V/μs V/μs V/μs V/μs Notes TSOB – – – – 3.4 3.4 SRROB 0.5 0.5 – – – – SRFOB 0.55 0.55 – – – – BWOB 0.8 0.8 – – – – MHz MHz BWOB 300 300 – – – – kHz kHz Note 8. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period) Document Number: 001-48325 Rev. *E Page 33 of 44 [+] [+] Feedback CY8CPLC20 9.4.6 AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-19. 5V AC External Clock Specifications Symbol FOSCEXT – – – Description Frequency High Period Low Period Power Up IMO to Switch Min 0.093 20.6 20.6 150 Typ – – – – Max 24.6 5300 – – Units MHz ns ns µs Notes 9.4.7 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-20. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TERASEALL Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Flash Erase Time (Bulk) Min 1 1 40 40 0 – – – – – – Typ – – – – – 10 40 – 80 – – Max 20 20 – – 8 – – 45 – 100[9] 200[9] Units ns ns ns ns MHz ms ms ns ms ms ms Notes TPROGRAM_HOT Flash Block Erase + Flash Block Write Time TPROGRAM_COLD Flash Block Erase + Flash Block Write Time Erase all Blocks and protection fields at once 0°C