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MB91F527/MB91F528
32-bit Microcontroller
FR Family FR81S
Hardware Manual
Doc. No. 002-05578 Rev. *A
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com
Copyrights
© Cypress Semiconductor Corporation, 2013-2016. This document is the property of Cypress Semiconductor Corporation
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States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as
specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with
Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable
license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code
form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your
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resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents
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2
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Preface
Thank you for your continued use of Cypress semiconductor products.
Read this manual and "MB91520 Series Data Sheet" thoroughly before using products in the MB91520
series.
Purpose of this manual and intended readers
This series is Cypress 32-bit microcontroller designed for automotive and industrial control. It contains the FR81S
CPU that is compatible with the FR family. The FR81S CPU has a high level performance among the FR family by
enhancing instruction pipeline and load store processing, and improving internal bus transfer.
It is best suited for application control for automotive.
This manual explains the function, operation, and the usage for the engineer who develops the product by actually
using this series.
Code : PREF-1v0-91528-3-E
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
3
How to Use This Manual
Finding a function
The following methods can be used to search for the explanation of a desired function in this manual:
Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
Search from the register
The register list for this device has been described. You can look up the name of a desired register on the list to
find the address of its location or the page that explains it.
The address where each register is located is not described in the text. To verify the address of a register, see "A.
I/O Map" of "APPENDIX".
Search from the index
You can look up the keyword such as the name of a peripheral function in the index to find the explanation of
the function.
About the chapters
Basically, this manual explains 1 peripheral function per chapter.
Terminology
This manual uses the following terminology.
Term
4
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
How to Use This Manual
How to Read This Manual
Primary Terms
The following explains the primary terms used in this series
Term
XBS
On-chip bus
Explanation
A 32-bit width, high-speed internal bus.
The bus master is used for access from the CPU (for instruction fetch), the CPU
(for data reading or writing), or the on-chip bus.
The bus slave is used to access to the on-chip bus, RAM (via the XBS built-in wild
register), and flash memory.
The bus has a crossbar switch configuration, and a circuit from each bus master to
each bus slave can operate simultaneously.
A 32-bit width, high-speed internal bus. It has a 2-layer structure for XBS and DMA, and
they can operate simultaneously.
The bus master of the XBS layer is accessed from the XBS.
The bus master of the DMA layer is accessed from the DMA.
The bus slave of both layers has an external bus interface, CAN, 16/32-bit peripheral bus
bridge and others.
The bus slave of only DMA layer has an access to the XBS.
32-bit peripheral
bus
A 32-bit width, low-speed internal bus.
It connects to various types of peripherals.
16-bit peripheral
bus (R-bus)
A 16-bit width, low-speed internal bus.
It connects to various types of peripherals. The 32-bit width access to this bus is
divided into 16 bits × 2.
External bus
(External bus)
8/16-bit width, low-speed external bus. It connects to memory devices, ASIC and
others. This series is the bus master, and a device connected to the external bus is a
bus slave.
Main clock
(MCLK)
This is the reference clock for LSI operation, and it is supplied from the high-speed
system oscillator.
It is connected to the timer for main oscillation stabilization wait, the clock
generator (PLL) and others.
Sub clock
(SBCLK)
This is the reference clock for LSI operation, and it is supplied from the low-speed
system oscillator.
It is connected to the timer for sub oscillation stabilization wait and others.
It can be used by the dual clock products only.
CR oscillation
The clock for watchdog timer 1 (hardware watchdog)
PLL clock
(PLLCLK)
The main clock is multiplied by PLL.
CPU clock
(CCLK)
The clock for peripherals operating under the XBS.
On-chip bus
clock (HCLK)
The clock for peripherals operating under the on-chip bus.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
5
How to Use This Manual
Term
6
Explanation
Peripheral clock
(PCLK)
The clock for peripherals operating under the 32-bit peripheral bus and 16-bit
peripheral bus.
External
bus clock
(TCLK)
The reference clock for an external bus interface connected to the X-bus and for the
external clock output. It is generated from the base clock by the clock generator.
Main clock mode
The operation mode based on the main clock. The main clock mode has the main
RUN, main sleep, main stop, oscillation stabilization wait RUN, oscillation
stabilization wait reset, and program reset state.
Main RUN
The main clock mode is selected, and all circuits are operable.
Oscillation
stabilization
wait time
When the clock is switched from the stop state to the oscillation state, the clock
takes the oscillation stabilization time. During the oscillation stabilization wait
time, the clock is not supplied.
OCD
The on-chip debugger for this series
OCDU
The OCD interface built in this product.
OCD tool
The OCD tool can be connected to the DEBUG I/F pin of this device.
Chip reset
sequence
In the chip reset sequence, the connection of OCD tool is checked. It takes
(1026+3) PCLK cycles.
Power-shutdown
The power supply to the target circuit is stopped, and power consumption is
decreased.
Always power
supply ON block
It is not a target division for the power-shutdown.
PMU
Power
management unit
The power shutdown is controlled. PMU exists in always ON block.
SSCG
SSCG mean "Spread Spectrum Clock Generator".
When the clock in electronic equipment generates a single frequency, the radiation
because of the frequency and the higher harmonics wave grows.
It is a technology to suppress the peak of EMI to low.
SSCG is a technology that suppresses the peak of EMI to low by the clock
frequency change slightly and oscillates it (= frequency modulation). When the
clock in electronic equipment generates a single frequency, the radiation because of
the frequency and the higher harmonics wave grows.
SSCG is a technology that does working that suppresses the peak of EMI to low
especially depending that makes the clock frequency change slightly and oscillates
it (= frequency modulation).
ADC
A/D converter
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
How to Use This Manual
Access Unit and Address Position
Offset
Address
+0
000060H
000064H
SSR0[R/W]
B, H, W
00001000
Register name
Readable/Writable only
Read only
Address offset value/Register
name
Block
+1
+2
+3
SIDR0[R]
B, H, W
SODR0[W]
B, H, W
XXXXXXXX
SCR0[R/W]
B, H, W
00000100
SMR0[R/W]
B, H, W
00000-0-
UART0
DRCL0[W]
B
XXXXXXX
UTIMC0[R/W]
B
0--00001
U-TIMER0
UTIM0[R] H
(UTIMR0[W]H)
00000000 00000000
Byte access, Half-word access, Word access
Write only
Initial Value
Although three types of access (Byte, Half-word, and Word access) are enabled, some registers have access
restrictions. For details, see "APPENDIX", or section "4. Detailed Register Description" of each chapter.
B, H, W
: Byte access, Half-word access, and Word access are enabled.
B
: Byte access (Use the Byte access only.)
H
: Half-word access (Use the Half-word access only.)
W
: Word access (Use the Word access only.)
B, H
: Byte access and Half-word access only (The Word access is not allowed.)
H, W
: Half-word access and Word access only (The Byte access is not allowed.)
(Reference)
The following explains the address position during access.
During Word access, the address is a multiple of 4 (the lowest order 2 bits are forcibly set to "00").
During Half-word access, the address is a multiple of 2 (the lowest order 1 bit is forcibly set to "0").
During Byte access, the address remains unchanged.
Therefore, if the SSR0 register is set to the Half-word access, for example, SSR0 + SIDR0 (SODR0) register at
address 060H is accessed.
(If the address offsets are +1 and +2 (for example, SIDR0+SCR0), the Half-word access is not allowed.)
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How to Use This Manual
Access Unit and Bit Position
Register name
Register abbreviation
Target peripheral function
Address
Access unit
Bit position
4.3 Serial Status Register
The register indicates the UART state.
(Example) SSR0 (UART0) : Address 0060H (Access : Byte, Half-word, Word)
bit
Initial value
Attribute
7
6
5
4
3
2
1
0
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
0
0
0
0
1
0
0
0
R/W
R/WX
R/WX
R/WX
R/WX
R/W
R/W
R/W
If the access unit is changed, the bit position changes.
If the address offset is +0: (Example of SSR0 register)
Access size
Address
Bit position
Word
060H+0H
7
6
5
4
3
2
1
0
Half-word
060H+0H
15
14
13
12
11
10
9
8
Word
060H+0H
31
30
29
28
27
26
25
24
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Bit name
If the address offset is +1: (Example of SIDR0 register)
Access size
Address
Bit position
Word
060H+1H
7
6
5
4
3
2
1
0
Half-word
060H+0H
7
6
5
4
3
2
1
0
Word
060H+0H
23
22
21
20
19
18
17
16
D7
D6
D5
D4
D3
D2
D1
D0
Bit name
If the address offset is +2: (Example of SCR0 register)
Access size
Address
Word
060H+2H
7
6
5
4
3
2
1
0
Half-word
060H+2H
15
14
13
12
11
10
9
8
Word
060H+0H
15
14
13
12
11
10
9
8
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Bit name
8
Bit position
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
How to Use This Manual
If the address offset is +3: (Example of SMR0 register)
Access size
Address
Bit position
Word
060H+3H
7
6
5
4
3
2
1
0
Half-word
060H+2H
7
6
5
4
3
2
1
0
Word
060H+0H
7
6
5
4
3
2
1
0
MD1
MD0
CS2
CS1
CS0
-
SCKE
-
Bit name
Meaning of Bit Attribute Symbols
R
: Read enabled
W
: Write enabled
RM
: Reading operation during read-modify-write(RMW) operation
"/" (slash)
R/W
"," (comma) R, W
: Read and write enabled. (The read value is the written value.)
: The read and written values differ from each other. (The read value is different
from the written value.)
R0
: The read value is "0".
R1
: The read value is "1".
W0
: This bit must always be written to "0".
W1
: This bit must always be written to "1".
(RM0)
: "0" is read by read-modify-write(RMW) operation.
(RM1)
: "1" is read by read-modify-write(RMW) operation.
RX
: The read value is undefined. (A reserved bit or an undefined bit)
WX
: Writing does not affect on the operation. (Undefined bit)
R/W writing examples
R/W
: Read and write enabled (The read value is the written value.)
R,W
: Read and write enabled (The read value is different from the written value.)
R,RM/W
: Read and write enabled (The read value is different from the written value. The written
value is read by read-modify-write (RMW) instruction.) An example is a port data register.
R(RM1),W : Read and write enabled (The read value is different from the written value. For
read-modify-write (RMW) instructions, "1" will be read out.) An example is an interrupt
request flag.
R,WX
: Read only (Read enabled. Writing has no effect on operation.)
R1,W
: Write only (Write enabled. The read value is "1".)
R0,W
: Write only (Write enabled. The read value is "0".)
RX,W
: Write only (Write enabled. The read value is undefined.)
R0,W0
: Reserved bit (The written value is "0". The read value is the written value.)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
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How to Use This Manual
10
R0,W0
: Reserved bit (The written value is "0". The read value is "0".)
R1,W0
: Reserved bit (The written value is "0". The read value is "1".)
RX,W0
: Reserved bit (The written value is "0". The read value is undefined.)
R/W1
: Reserved bit (The written value is "1". The read value is the written value.)
R1,W1
: Reserved bit (The written value is "1". The read value is "1".)
R0,W1
: Reserved bit (The written value is "1". The read value is "0".)
RX,W1
: Reserved bit (The written value is "1". The read value is undefined.)
RX,WX
: Undefined bit (The read value is undefined. Writing has no effect on operation.)
R0,WX
: Undefined bit (The read value is "0". Writing has no effect on operation.)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Table of Contents
Chapter 1: Overview ......................................................................................................................................................... 46
1.
2.
Overview .................................................................................................................................................................. 47
Features .................................................................................................................................................................... 47
2.1. FR81S CPU Core ............................................................................................................................................. 47
2.2. Peripheral Functions ........................................................................................................................................ 48
3. Product Line-up ........................................................................................................................................................ 51
4. Function overview .................................................................................................................................................... 60
5. Block Diagram ......................................................................................................................................................... 66
6. Memory Map ............................................................................................................................................................ 71
7. Pin Assignment ........................................................................................................................................................ 72
8. Device Package ........................................................................................................................................................ 76
9. Explanation of Pin Functions ................................................................................................................................... 84
9.1. Pins of Each Function .................................................................................................................................... 107
9.1.1.
Pins of A/D Converter (ch.0 to ch.63) ................................................................................................... 107
9.1.2.
Pins of CAN (ch.0 to ch.5) .................................................................................................................... 109
9.1.3.
Pins of D/A Converter (ch.0, ch.1) ........................................................................................................ 109
9.1.4.
Pins of External Interrupt Input ............................................................................................................. 110
9.1.5.
Pins of Multi-function Serial Interface (ch.0 to ch.19) .......................................................................... 110
9.1.6.
Pins of PPG (ch.0 to ch.87) ................................................................................................................... 114
9.1.7.
Pin of RTC ............................................................................................................................................. 118
9.1.8.
Pins of Up/down Counter ...................................................................................................................... 118
9.1.9.
Pins of Output Compare (ch.0 to ch.5: 16bit, ch.6 to ch.13: 32bit) ....................................................... 119
9.1.10. Pins of Input Capture (ch.0 to ch.3: 16bit, ch.4 to ch.11: 32bit) ............................................................ 119
9.1.11. Pins of Free-run Timer (ch.0 to ch.2: 16bit, ch.3 to ch.10: 32bit) ......................................................... 120
9.1.12. Pins of Base Timer (ch.0, ch.1) ............................................................................................................. 121
9.1.13. Pins of Reload Timer (ch.0 to ch.7) ....................................................................................................... 121
9.1.14. Pins of External Bus Interface ............................................................................................................... 122
9.1.15. Pins of Waveform Generator (ch.0 to ch.5) ........................................................................................... 123
9.1.16. Pin of Clock Monitor ............................................................................................................................. 124
9.1.17. Pins of FlexRay (1 Unit ch.A, ch.B)...................................................................................................... 124
9.1.18. Pins of JTAG ......................................................................................................................................... 125
9.1.19. Pins of Port Function (General-Purpose I/O) ........................................................................................ 125
9.1.20. Other Pins .............................................................................................................................................. 131
10. I/O Circuit Types .................................................................................................................................................... 133
Chapter 2: Handling The Device .................................................................................................................................... 140
1.
Handling Precautions ............................................................................................................................................. 141
1.1. Precautions for Product Design ...................................................................................................................... 141
1.2. Precautions for Package Mounting ................................................................................................................ 142
1.3. Precautions for Use Environment .................................................................................................................. 143
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
11
Table of Contents
2.
3.
Handling Device ..................................................................................................................................................... 144
Application Notes ................................................................................................................................................... 146
3.1. Function Switching of a Multiplexed Port ..................................................................................................... 147
3.2. Low-power Consumption Mode .................................................................................................................... 147
3.3. Notes When Writing Data in a Register that Includes the Status Flag ........................................................... 147
Chapter 3: CPU ............................................................................................................................................................... 148
1.
2.
3.
Overview ................................................................................................................................................................ 149
Features .................................................................................................................................................................. 149
CPU Operating Description .................................................................................................................................... 150
3.1. CPU Operating Status .................................................................................................................................... 151
3.1.1.
Reset State ............................................................................................................................................. 151
3.1.2.
Normal Run State .................................................................................................................................. 152
3.1.3.
Low-power Consumption State ............................................................................................................. 152
3.1.4.
Debug Run State .................................................................................................................................... 152
4. Pipeline Operation .................................................................................................................................................. 153
5. Floating Point Operation Processing ...................................................................................................................... 153
6. Data Structure ......................................................................................................................................................... 153
7. Addressing .............................................................................................................................................................. 153
8. Programming Model............................................................................................................................................... 154
8.1. General-purpose Registers, Dedicated Registers, and Floating Point Registers ............................................ 155
8.2. System Register ............................................................................................................................................. 156
9. Reset and EIT Processing ....................................................................................................................................... 156
9.1. Reset .............................................................................................................................................................. 157
9.2. EIT Processing ............................................................................................................................................... 157
9.3. Vector Table ................................................................................................................................................... 157
10. Memory Protection Function (MPU) ..................................................................................................................... 159
10.1. Overview........................................................................................................................................................ 160
10.2. List of Registers ............................................................................................................................................. 161
10.3. Description of Registers ................................................................................................................................. 162
10.3.1. MPU Control Register : MPUCR .......................................................................................................... 162
10.3.2. Instruction Access Protection Violation Address Register : IPVAR ...................................................... 165
10.3.3. Instruction Access Protection Violation Status Register : IPVSR ......................................................... 166
10.3.4. Data Access Protection Violation Address Register :DPVAR ............................................................... 167
10.3.5. Data Access Protection Violation Status Register : DPVSR.................................................................. 168
10.3.6. Data Access Error Address Register : DEAR ........................................................................................ 169
10.3.7. Data Access Error Status Register : DESR ............................................................................................ 170
10.3.8. Protection Area Base Address Register 0 to 7 : PABR0 to PABR7 ....................................................... 172
10.3.9. Protection Area Control Register 0 to 7 : PACR0 to PACR7................................................................. 173
10.4. Operations of Memory Protection Function .................................................................................................. 176
10.4.1. Setting Up Memory Protection Areas .................................................................................................... 176
10.4.2. Instruction Access Protection Violation ................................................................................................. 177
10.4.3. Data Access Protection Violation .......................................................................................................... 177
10.4.4. Data Access Errors ................................................................................................................................ 177
10.4.5. Memory Protection Operation by Delay Slot ........................................................................................ 178
10.4.6. DEAR and DESR Update ...................................................................................................................... 178
10.4.7. Notes...................................................................................................................................................... 179
Chapter 4: Operation Mode............................................................................................................................................ 180
1.
2.
12
Overview ................................................................................................................................................................ 181
Features .................................................................................................................................................................. 181
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Table of Contents
3.
4.
Configuration ......................................................................................................................................................... 181
Register .................................................................................................................................................................. 182
4.1. Bus Mode Register : BMODR (Bus MODe Register) ................................................................................... 182
5. Operation ................................................................................................................................................................ 182
5.1. MD0, MD1, P006 Pins Settings ..................................................................................................................... 183
5.2. Fetching the Operation Mode ........................................................................................................................ 183
5.3. Explanation of Each Operation Mode ............................................................................................................ 185
5.3.1.
User Mode ............................................................................................................................................. 185
5.3.2.
Serial Writer Mode ................................................................................................................................ 185
Chapter 5: Clock .............................................................................................................................................................. 189
1.
2.
3.
4.
Overview ................................................................................................................................................................ 190
Features .................................................................................................................................................................. 192
Configuration ......................................................................................................................................................... 193
Registers ................................................................................................................................................................. 199
4.1. Division Configuration Register 0 : DIVR0 (DIVision clock configuration Register 0) ............................... 200
4.2. Division Configuration Register 1 : DIVR1 (DIVision clock configuration Register 1) ............................... 201
4.3. Division Configuration Register 2 : DIVR2 (DIVision clock configuration Register 2) ............................... 202
4.4. Clock Source Selection Register : CSELR (Clock source SELection Register) ............................................ 203
4.5. Clock Source Monitor Register : CMONR (Clock source MONitor Register).............................................. 205
4.6. Main Timer Control Register : MTMCR (Main clock TiMer Control Register) ........................................... 207
4.7. Sub Timer Control Register : STMCR (Sub clock TiMer Control Register) ................................................. 209
4.8. PLL Setting Register : PLLCR (PLL Configuration Register) ...................................................................... 212
4.9. Clock Stabilization Selection Register : CSTBR (Clock STaBilization selection Register) .......................... 215
4.10. PLL Oscillation Timer Control Register : PTMCR (PLL clock osc TiMer Control Register) ....................... 217
4.11. PLL/SSCG Clock Selection Register : CCPSSELR (CCtl Pll/Sscg clock SELection Register) .................... 218
4.12. PLL/SSCG Output Clock Division Setting Register : CCPSDIVR
(CCtl Pll/Sscg clock DIVision Register) ........................................................................................................ 219
4.13. PLL Feedback Division Setting Register : CCPLLFBR (CCtl PLL FB clock division Register) .................. 221
4.14. SSCG Feedback Division Setting Register 0 : CCSSFBR0 (CCtl SScg FB clock division Register 0) ........ 222
4.15. SSCG Feedback Division Setting Register 1 : CCSSFBR1 (CCtl SScg FB clock division Register 1) ........ 223
4.16. SSCG Configuration Setting Register 0 : CCSSCCR0 (CCtl SSCg Config. Register 0) ............................... 224
4.17. SSCG Configuration Setting Register 1 : CCSSCCR1 (CCtl SSCg Config. Register 1) ............................... 226
4.18. Clock Gear Configuration Setting Register 0 : CCCGRCR0 (CCtl Clock GeaR Config. Register 0) ........... 227
4.19. Clock Gear Configuration Setting Register 1 : CCCGRCR1 (CCtl Clock GeaR Config. Register 1) ........... 228
4.20. Clock Gear Configuration Setting Register 2 : CCCGRCR2 (CCtl Clock GeaR Config. Register 2) ........... 229
4.21. RTC/PMU Clock Selection Register : CCRTSELR (CCtl RTc pmu clock SELection Register) ................... 230
4.22. PMU Clock Division Setting Register 0 : CCPMUCR0 (CCtl PMU Clock division Register 0) .................. 231
4.23. PMU Clock Division Setting Register 1 : CCPMUCR1 (CCtl PMU Clock division Register 1) .................. 232
4.24. Sync/Async Control Register : SACR ........................................................................................................... 234
4.25. Peripheral Interface Clock Divider : PICD .................................................................................................... 234
5. Operation ................................................................................................................................................................ 236
5.1. Oscillation Control ......................................................................................................................................... 236
5.1.1.
Main Clock (MCLK) ............................................................................................................................. 236
5.1.2.
Sub Clock (SBCLK) .............................................................................................................................. 237
5.1.3.
PLL/SSCG Clock (PLLSSCLK) ........................................................................................................... 237
5.1.4.
Limitations when PLL/SSCG Clock is used ......................................................................................... 239
5.2. Oscillation Stabilization Wait......................................................................................................................... 241
5.2.1.
Conditions for Generating Stabilization Wait Time ............................................................................... 241
5.2.2.
Selecting Stabilization Wait Time.......................................................................................................... 241
5.2.3.
End of the Stabilization Wait Time ........................................................................................................ 242
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5.3. Selecting the Source Clock (SRCCLK) ......................................................................................................... 242
5.3.1.
Selecting the Source Clock at the Time of Initialization ....................................................................... 242
5.3.2.
Procedure of switching the source clock ............................................................................................... 242
5.4. Timer .............................................................................................................................................................. 248
5.4.1.
Main Clock Oscillation Stabilization Wait Timer (Main Timer) ........................................................... 248
5.4.2.
Sub Clock Oscillation Stabilization Wait Timer (Sub Timer) ................................................................ 248
5.4.3.
PLL/SSCG Clock Oscillation Stabilization Wait timer (PLL Timer) .................................................... 248
5.4.4.
Setting.................................................................................................................................................... 249
5.4.5.
Procedure for Setting the Timer Interrupt .............................................................................................. 249
5.4.6.
Timer Operations ................................................................................................................................... 250
5.4.7.
Watch Mode and Timer Interrupt .......................................................................................................... 250
5.5. Notes when Clocks Conflict .......................................................................................................................... 251
5.6. The Clock Gear Circuit .................................................................................................................................. 251
5.6.1.
Procedure of Gear Up ............................................................................................................................ 251
5.6.2.
Procedure of Gear Down ....................................................................................................................... 252
5.7. Operations during MDI Communications ...................................................................................................... 252
5.8. About PMU clock (PMUCLK) ...................................................................................................................... 252
Chapter 6: FlexRay Dedicated Clock ............................................................................................................................. 255
1.
2.
3.
4.
Overview ................................................................................................................................................................ 256
Features .................................................................................................................................................................. 257
Configuration ......................................................................................................................................................... 257
Registers ................................................................................................................................................................. 258
4.1. FlexRay PLL Division (Divide-by-M) Selection Register: PLL2DIVM ....................................................... 259
4.2. FlexRay PLL Multiplication Rate (Divide-by-N) Selection Register: PLL2DIVN ....................................... 260
4.3. FlexRay PLL Auto Gear Multiplication Rate (Divide-by-G) Selection Register: PLL2DIVG ...................... 261
4.4. FlexRay PLL Divide-by-G Step Multiplication Rate Selection Register: PLL2MULG ................................ 262
4.5. Auto Gear Control Register: PLL2CTRL ...................................................................................................... 263
4.6. FlexRay PLL Multiplication Rate (Divide-by-K) Selection Register: PLL2DIVK ....................................... 264
4.7. FlexRay PLL Clock Output Control Register: CLKR2 ................................................................................. 265
5. Settings ................................................................................................................................................................... 266
6. Clock Auto-Gear Up/Down .................................................................................................................................... 267
7. Operation ................................................................................................................................................................ 269
8. Notes ...................................................................................................................................................................... 270
Chapter 7: Clock Reset State Transitions ...................................................................................................................... 271
1.
2.
Overview ................................................................................................................................................................ 272
Device States and Transitions ................................................................................................................................ 272
2.1. Diagram of State Transitions.......................................................................................................................... 272
2.2. Explanation of Each States ............................................................................................................................ 275
2.3. Priority of State Transition Requests.............................................................................................................. 276
3. Device State and Regulator Mode Corresponding to those States ......................................................................... 277
Chapter 8: Reset .............................................................................................................................................................. 279
1.
2.
3.
4.
14
Overview ................................................................................................................................................................ 280
Features .................................................................................................................................................................. 280
Configuration ......................................................................................................................................................... 281
Registers ................................................................................................................................................................. 285
4.1. Reset Source Register : RSTRR (ReSeT Result Register) ............................................................................. 286
4.2. Reset Control Register : RSTCR (ReSeT Control Register) .......................................................................... 289
4.3. CPU Abnormal Operation Register : CPUAR (CPU Abnormal operation Register) ..................................... 290
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5.
4.4. PMU Status Register : PMUSTR (Power Management Unit STatus Register) ............................................. 292
Operation ................................................................................................................................................................ 293
5.1. Reset Level .................................................................................................................................................... 294
5.1.1.
Initialize Reset (INIT) ........................................................................................................................... 294
5.1.2.
Reset (RST) ........................................................................................................................................... 295
5.2. Reset Factor ................................................................................................................................................... 295
5.2.1.
Power-on Reset ...................................................................................................................................... 295
5.2.2.
RSTX Pin Input ..................................................................................................................................... 295
5.2.3.
Watchdog Reset 0 .................................................................................................................................. 296
5.2.4.
Watchdog Reset 1 .................................................................................................................................. 296
5.2.5.
External Low-Voltage Detection Reset.................................................................................................. 296
5.2.6.
Illegal Standby Mode Transition Detection Reset ................................................................................. 296
5.2.7.
Internal Low-Voltage Detection Reset ................................................................................................... 297
5.2.8.
Flash Security Violation Reset............................................................................................................... 297
5.2.9.
Software Reset (RSTCR:SRST) ............................................................................................................ 297
5.2.10. Recovery from Standby (Power Shutdown) .......................................................................................... 298
5.3. Reset Acceptance ........................................................................................................................................... 298
5.3.1.
Generation of Reset Request ................................................................................................................. 298
5.3.2.
Acceptance of Reset Request ................................................................................................................ 298
5.3.3.
Reset Issue Delay Counter ..................................................................................................................... 299
5.3.4.
Irregular Reset ....................................................................................................................................... 299
5.4. Reset Issue ..................................................................................................................................................... 299
5.4.1.
Super Initialize Reset (SINIT) ............................................................................................................... 300
5.4.2.
Initialize Reset (INIT) ........................................................................................................................... 302
5.4.3.
Reset (RST) ........................................................................................................................................... 303
5.5. Reset Sequence .............................................................................................................................................. 304
5.5.1.
Reset Cycle ............................................................................................................................................ 306
5.5.2.
Reset Release ......................................................................................................................................... 306
5.5.3.
Operating Mode Fix .............................................................................................................................. 306
5.5.4.
Transition of Bus Control ...................................................................................................................... 306
5.5.5.
Reset Vector Fetch ................................................................................................................................ 306
5.5.6.
Reset and Forced Break ......................................................................................................................... 307
5.6. Notes .............................................................................................................................................................. 307
Chapter 9: DMA Controller (DMAC) ............................................................................................................................ 308
1.
2.
3.
4.
Overview ................................................................................................................................................................ 309
Features .................................................................................................................................................................. 309
Configuration ......................................................................................................................................................... 310
Registers ................................................................................................................................................................. 311
4.1. DMA Control Register: DMACR (DMA Control Register) .......................................................................... 314
4.2. DMA Channel Control Register 0 to 15: DCCR0 to 15 (DMA Channel Control Register 0 to 15) .............. 316
4.3. DMA Channel Status Register 0 to 15 : DCSR0 to 15: (DMA Channel Status Register 0 to 15).................. 322
4.4. DMA Transfer Count Register 0 to 15 : DTCR0 to 15: (DMA Transfer Count Register 0 to 15) ................. 324
4.5. DMA Transfer Source Register 0 to 15 : DSAR0 to 15: (DMA Source Address Register 0 to 15) ............... 325
4.6. DMA Transfer Destination Register 0 to 15 : DDAR0 to 15 (DMA Destination Address Register 0 to 15) . 326
4.7. DMA Transfer Suppression NMI Flag Register : DNMIR (DMA-halt by NMI Register) ............................ 327
4.8. DMA Transfer Suppression Level Register : DILVR (DMA-halt by Interrupt Level Register) .................... 328
5. Operation ................................................................................................................................................................ 330
5.1. Configuration ................................................................................................................................................. 330
5.1.1.
Common Items for All Channels ........................................................................................................... 330
5.1.2.
Separate Items for Each Channel ........................................................................................................... 331
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5.1.3.
Operations ............................................................................................................................................. 335
5.2. Table for On-chip Bus IPs and Corresponding DMAC Channels ................................................................. 348
6. DMA Usage Examples ........................................................................................................................................... 349
Chapter 10: Generation And Clearing Of DMA Transfer Requests ........................................................................... 351
1.
2.
Overview ................................................................................................................................................................ 352
Features .................................................................................................................................................................. 352
2.1. Transfer Request Generation Setting ............................................................................................................. 352
2.2. Interrupt Clearing Setting............................................................................................................................... 352
3. Configuration ......................................................................................................................................................... 353
4. Registers ................................................................................................................................................................. 353
4.1. DMA Request Clear Register 0 : ICSEL0 (Interrupt Clear SELect register 0) .............................................. 355
4.2. DMA Request Clear Register 1 : ICSEL1 (Interrupt Clear SELect register 1) .............................................. 356
4.3. DMA Request Clear Register 2 : ICSEL2 (Interrupt Clear SELect register 2) .............................................. 357
4.4. DMA Request Clear Register 3 : ICSEL3 (Interrupt Clear SELect register 3) .............................................. 357
4.5. DMA Request Clear Register 4: ICSEL4 (Interrupt Clear SELect register 4) ............................................... 358
4.6. DMA Request Clear Register 5 : ICSEL5 (Interrupt Clear SELect register 5) .............................................. 359
4.7. DMA Request Clear Register 6 : ICSEL6 (Interrupt Clear SELect register 6) .............................................. 360
4.8. DMA Request Clear Register 7 : ICSEL7 (Interrupt Clear SELect register 7) .............................................. 361
4.9. DMA Request Clear Register 8 : ICSEL8 (Interrupt Clear SELect register 8) .............................................. 362
4.10. DMA Request Clear Register 9 : ICSEL9 (Interrupt Clear SELect register 9) .............................................. 362
4.11. DMA Request Clear Register 10 : ICSEL10 (Interrupt Clear SELect register 10) ........................................ 363
4.12. DMA Request Clear Register 11 : ICSEL11 (Interrupt Clear SELect register 11) ........................................ 364
4.13. DMA Request Clear Register 12: ICSEL12 (Interrupt Clear SELect register 12) ......................................... 365
4.14. DMA Request Clear Register 13 : ICSEL13 (Interrupt Clear SELect register 13) ........................................ 365
4.15. DMA Request Clear Register 14 : ICSEL14 (Interrupt Clear SELect register 14) ........................................ 366
4.16. DMA Request Clear Register 15 : ICSEL15 (Interrupt Clear SELect register 15) ........................................ 367
4.17. DMA Request Clear Register 16 : ICSEL16 (Interrupt Clear SELect register 16) ........................................ 368
4.18. DMA Request Clear Register 17 : ICSEL17 (Interrupt Clear SELect register 17) ........................................ 369
4.19. DMA Request Clear Register 18 : ICSEL18 (Interrupt Clear SELect register 18) ........................................ 369
4.20. DMA Request Clear Register 19 : ICSEL19 (Interrupt Clear SELect register 19) ........................................ 371
4.21. DMA Request Clear Register 20 : ICSEL20 (Interrupt Clear SELect register 20) ........................................ 372
4.22. DMA Request Clear Register 21 : ICSEL21 (Interrupt Clear SELect register 21) ........................................ 373
4.23. DMA Request Clear Register 22 : ICSEL22 (Interrupt Clear SELect register 22) ........................................ 374
4.24. DMA Request Clear Register 23 : ICSEL23 (Interrupt Clear SELect register 23) ........................................ 375
4.25. DMA Request Clear Register 24 : ICSEL24 (Interrupt Clear SELect register 24) ........................................ 375
4.26. DMA Request Clear Register 25 : ICSEL25 (Interrupt Clear SELect register 25) ........................................ 376
4.27. DMA Request Clear Register 26 : ICSEL26 (Interrupt Clear SELect register 26) ........................................ 377
4.28. DMA Request Clear Register 27 : ICSEL27 (Interrupt Clear SELect register 27) ........................................ 378
4.29. DMA Request Clear Register 28: ICSEL28 (Interrupt Clear SELect register 28) ......................................... 378
4.30. DMA Request Clear Register 29: ICSEL29 (Interrupt Clear SELect register 29) ......................................... 379
4.31. DMA Request Clear Register 30: ICSEL30 (Interrupt Clear SELect register 30) ......................................... 379
4.32. DMA Request Clear Register 31: ICSEL31 (Interrupt Clear SELect register 31) ......................................... 380
4.33. DMA Request Clear Register 32: ICSEL32 (Interrupt Clear SELect register 32) ......................................... 380
4.34. DMA Request Clear Register 33: ICSEL33 (Interrupt Clear SELect register 33) ......................................... 381
4.35. IO Transfer Request Setting Register 0 to 15 : IORR0 to 15
(IO triggered DMA Request Register for ch.0 to 15) ..................................................................................... 381
5. Operation ................................................................................................................................................................ 383
5.1. Configuration ................................................................................................................................................. 383
5.2. Notes .............................................................................................................................................................. 383
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Chapter 11: FixedVector Function ................................................................................................................................. 384
1.
2.
3.
4.
5.
Overview ................................................................................................................................................................ 385
Features .................................................................................................................................................................. 385
Configuration ......................................................................................................................................................... 385
Registers ................................................................................................................................................................. 385
Operation ................................................................................................................................................................ 385
5.1. Operation After Reset Released ..................................................................................................................... 386
5.2. Usage ............................................................................................................................................................. 386
6. Notes ...................................................................................................................................................................... 386
Chapter 12: I/O Ports ...................................................................................................................................................... 387
1.
2.
3.
4.
Overview ................................................................................................................................................................ 388
Features .................................................................................................................................................................. 388
Configuration ......................................................................................................................................................... 389
Registers ................................................................................................................................................................. 389
4.1. Port Data Register 00 to 29 : PDR00 to 29 (Port Data Register 00 to 29) ..................................................... 393
4.2. Data Direction Register 00 to 29 : DDR00 to 29 (Data Direction Register 00 to 29) .................................... 394
4.3. Port Function Register 00 to 29 : PFR00 to 29 (Port Function Register 00 to 29) ......................................... 395
4.4. Input Data Direct Register 00 to 29 : PDDR00 to 29 (Port Data Direct Register 00 to 29) ........................... 396
4.5. Port Pull-up/down Enable Register 00 to 29 : PPER00 to 29
(Port Pull-up/down Enable Register 00 to 29) ............................................................................................... 397
4.6. Port Input Level Selection Register 00 to 15: PILR00 to 15 (Port Input Level Register 00 to 15) ................ 398
4.7. Extended Port Function Register 00 to 111 : EPFR00 to 111 (Extended Port Function Register 00 to 111) . 399
4.7.1.
Extended Port Function Register 00, 01, 56 : EPFR00, EPFR01, EPFR56 ........................................... 399
4.7.2.
Extended Port Function Register 02 to 05, 57 to 60 : EPFR02 to 05, 57 to 60 ..................................... 401
4.7.3.
Extended Port Function Register 06 to 09, 33 to 36, 61 to 64, 100 to 107 :
EPFR06 to 09, 33 to 36, 61 to 64, 100 to 107 ....................................................................................... 404
4.7.4.
Extended Port Function Register 10 to 15, 45, 71 to 78, 89 to 98 :
EPFR10 to 15, 45, 71 to 78, 89 to 98 .................................................................................................... 411
4.7.5.
Extended Port Function Register 79, 80, 99 : EPFR79, 80, 99 .............................................................. 418
4.7.6.
Extended Port Function Register 51, 86 : EPFR51, 86.......................................................................... 420
4.7.7.
Extended Port Function Register 26 : EPFR26 ..................................................................................... 421
4.7.8.
Extended Port Function Register 27 : EPFR27 ..................................................................................... 422
4.7.9.
Extended Port Function Register 28 : EPFR28 ..................................................................................... 422
4.7.10. Extended Port Function Register 29, 48, 81, 82 : EPFR29, 48, 81, 82 .................................................. 423
4.7.11. Extended Port Function Register 49, 83 : EPFR49, 83.......................................................................... 425
4.7.12. Extended Port Function Register 42 : EPFR42 ..................................................................................... 426
4.7.13. Extended Port Function Register 43, 44, 50 : EPFR43, 44, 50 .............................................................. 427
4.7.14. Extended Port Function Register 65 to 70, 110 : EPFR65 to 70, 110 .................................................... 428
4.7.15. Extended Port Function Register 84, 85 : EPFR84, 85 ....................................................................... 431
4.7.16. Extended Port Function Register 87 : EPFR87 ..................................................................................... 432
4.7.17. Extended Port Function Register 88 : EPFR88 ..................................................................................... 432
4.7.18. Extended Port Function Register 108, 109 : EPFR108, 109 .................................................................. 433
4.7.19. Extended Port Function Register 111 : EPFR111 .................................................................................. 434
4.8. Port Input Enable Register: PORTEN (PORT ENable register)..................................................................... 435
4.9. KEY CoDe Register : KEYCDR ................................................................................................................... 436
5. Operation ................................................................................................................................................................ 437
5.1. Pin I/O Assignment ........................................................................................................................................ 437
5.1.1.
Peripheral I/O (Bidirectional) Pin Assignment ...................................................................................... 439
5.1.2.
Peripheral Input Assignment ................................................................................................................. 440
5.1.3.
Peripheral Output Assignment ............................................................................................................... 441
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5.1.4.
External Bus Assignment ...................................................................................................................... 442
5.1.5.
Port Function (Input) Assignment ......................................................................................................... 444
5.1.6.
Port Function (Output) Assignment ....................................................................................................... 445
5.1.7.
A/D Converter Input Assignment .......................................................................................................... 446
5.1.8.
D/A converter output assignment .......................................................................................................... 446
5.2. EPFR setting priority ..................................................................................................................................... 446
5.3. Notes on Input I/O Relocation Setting ........................................................................................................... 447
5.4. Noise Filter .................................................................................................................................................... 447
5.5. Input blocked by GPORTEN ......................................................................................................................... 447
5.6. Notes on Pins with the A/D Converter Function ............................................................................................ 448
5.7. Setting when Using the Base Timer TIOA1 Pin ............................................................................................ 448
5.8. Key Code Register Function Settings ............................................................................................................ 448
5.9. Operation at Wake Up from Power Shutdown ............................................................................................... 450
5.10. Notes on switching the I/O port function ....................................................................................................... 450
5.11. Input blocked when specific peripheral functions are used............................................................................ 450
Chapter 13: Interrupt Control (Interrupt Controller) ................................................................................................. 451
1.
2.
3.
4.
Overview ................................................................................................................................................................ 452
Features .................................................................................................................................................................. 452
Configuration ......................................................................................................................................................... 452
Registers ................................................................................................................................................................. 454
4.1. Interrupt Control Registers 00 to 47 : ICR00 to ICR47 (Interrupt Control Register 00 to 47) ...................... 455
5. Operation ................................................................................................................................................................ 456
5.1. Setting ............................................................................................................................................................ 456
5.2. Starting ........................................................................................................................................................... 456
5.3. Determining Priorities .................................................................................................................................... 456
5.4. Recovering From Stop Mode ......................................................................................................................... 457
5.5. Recovering From Standby Mode (Power shutdown) ..................................................................................... 457
Chapter 14: External Interrupt Input ........................................................................................................................... 458
1.
2.
3.
4.
Overview ................................................................................................................................................................ 459
Features .................................................................................................................................................................. 459
Configuration ......................................................................................................................................................... 459
Registers ................................................................................................................................................................. 460
4.1. External Interrupt Factor Register 0/1/2 : EIRR0/EIRR1/EIRR2
(External Interrupt Request Register 0/1/2) ................................................................................................... 462
4.2. External Interrupt Enable Register 0/1/2 : ENIR0/ENIR1/ENIR2
(ENable Interrupt request Register 0/1/2) ...................................................................................................... 463
4.3. External Interrupt Request Level Register 0/1/2 : ELVR0/ELVR1/ELVR2
(External interrupt LeVel Register 0/1/2) ....................................................................................................... 464
5. Operation ................................................................................................................................................................ 465
6. Setting .................................................................................................................................................................... 467
7. Q&A ....................................................................................................................................................................... 468
8. Notes ...................................................................................................................................................................... 469
Chapter 15: NMI Input ................................................................................................................................................... 470
1.
2.
3.
4.
5.
18
Overview ................................................................................................................................................................ 471
Features .................................................................................................................................................................. 471
Configuration ......................................................................................................................................................... 471
Register .................................................................................................................................................................. 471
Operation ................................................................................................................................................................ 472
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6.
Usage Example ....................................................................................................................................................... 473
Chapter 16: Delay Interrupt ........................................................................................................................................... 474
1.
2.
3.
4.
5.
6.
Overview ................................................................................................................................................................ 475
Features .................................................................................................................................................................. 475
Configuration ......................................................................................................................................................... 475
Registers ................................................................................................................................................................. 476
Operation ................................................................................................................................................................ 476
Restrictions ............................................................................................................................................................. 477
Chapter 17: Interrupt Request Batch Read .................................................................................................................. 478
1.
2.
3.
4.
Overview ................................................................................................................................................................ 479
Features .................................................................................................................................................................. 479
Configuration ......................................................................................................................................................... 479
Registers ................................................................................................................................................................. 480
4.1. Interrupt Request Batch Read Register 0 upper-order : IRPR0H
(Interrupt Request Peripheral Read register 0H) ............................................................................................ 481
4.2. Interrupt Request Batch Read Register 0 lower-order : IRPR0L
(Interrupt Request Peripheral Read register 0L) ............................................................................................ 481
4.3. Interrupt Request Batch Read Register 1 upper-order : IRPR1H
(Interrupt Request Peripheral Read register 1H) ............................................................................................ 482
4.4. Interrupt Request Batch Read Register 1 lower-order : IRPR1L
(Interrupt Request Peripheral Read register 1L) ............................................................................................ 482
4.5. Interrupt Request Batch Read Register 3 upper-order : IRPR3H
(Interrupt Request Peripheral Read register 3H) ............................................................................................ 483
4.6. Interrupt Request Batch Read Register 3 lower-order : IRPR3L
(Interrupt Request Peripheral Read register 3L) ............................................................................................ 484
4.7. Interrupt Request Batch Read Register 4 upper-order : IRPR4H
(Interrupt Request Peripheral Read register 4H) ............................................................................................ 484
4.8. Interrupt Request Batch Read Register 4 lower-order : IRPR4L
(Interrupt Request Peripheral Read register 4L) ............................................................................................ 485
4.9. Interrupt Request Batch Read Register 5 upper-order : IRPR5H
(Interrupt Request Peripheral Read register 5H) ............................................................................................ 486
4.10. Interrupt Request Batch Read Register 5 lower-order : IRPR5L
(Interrupt Request Peripheral Read register 5L) ............................................................................................ 486
4.11. Interrupt Request Batch Read Register 6 upper-order : IRPR6H
(Interrupt Request Peripheral Read register 6H) ............................................................................................ 487
4.12. Interrupt Request Batch Read Register 6 lower-order : IRPR6L
(Interrupt Request Peripheral Read register 6L) ............................................................................................ 488
4.13. Interrupt Request Batch Read Register 7 upper-order : IRPR7H
(Interrupt Request Peripheral Read register 7H) ............................................................................................ 488
4.14. Interrupt Request Batch Read Register 7 lower-order : IRPR7L
(Interrupt Request Peripheral Read register 7L) ............................................................................................ 489
4.15. Interrupt Request Batch Read Register 8 upper-order : IRPR8H
(Interrupt Request Peripheral Read register 8H) ............................................................................................ 489
4.16. Interrupt Request Batch Read Register 8 lower-order : IRPR8L
(Interrupt Request Peripheral Read register 8L) ............................................................................................ 490
4.17. Interrupt Request Batch Read Register 9 upper-order : IRPR9H
(Interrupt Request Peripheral Read register 9H) ............................................................................................ 490
4.18. Interrupt Request Batch Read Register 9 lower-order : IRPR9L
(Interrupt Request Peripheral Read register 9L) ............................................................................................ 491
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4.19. Interrupt Request Batch Read Register 10 upper-order : IRPR10H
(Interrupt Request Peripheral Read register 10H) .......................................................................................... 491
4.20. Interrupt Request Batch Read Register 10 lower-order : IRPR10L
(Interrupt Request Peripheral Read register 10L) .......................................................................................... 492
4.21. Interrupt Request Batch Read Register 11 upper-order : IRPR11H
(Interrupt Request Peripheral Read register 11H) .......................................................................................... 493
4.22. Interrupt Request Batch Read Register 11 lower-order : IRPR11L
(Interrupt Request Peripheral Read register 11L) .......................................................................................... 493
4.23. Interrupt Request Batch Read Register 12 upper-order : IRPR12H
(Interrupt Request Peripheral Read register 12H) .......................................................................................... 494
4.24. Interrupt Request Batch Read Register 12 lower-order : IRPR12L
(Interrupt Request Peripheral Read register 12L) .......................................................................................... 494
4.25. Interrupt Request Batch Read Register 13 upper-order : IRPR13H
(Interrupt Request Peripheral Read register 13H) .......................................................................................... 495
4.26. Interrupt Request Batch Read Register 13 lower-order : IRPR13L
(Interrupt Request Peripheral Read register 13L) .......................................................................................... 495
4.27. Interrupt Request Batch Read Register 14 upper-order : IRPR14H
(Interrupt Request Peripheral Read register 14H) .......................................................................................... 496
4.28. Interrupt Request Batch Read Register 14 lower-order : IRPR14L
(Interrupt Request Peripheral Read register 14L) .......................................................................................... 496
4.29. Interrupt Request Batch Read Register 15 upper-order : IRPR15H
(Interrupt Request Peripheral Read register 15H) .......................................................................................... 497
4.30. Interrupt Request Batch Read Register 15 lower-order : IRPR15L
(Interrupt Request Peripheral Read register 15L) .......................................................................................... 498
4.31. Interrupt Request Batch Read Register 16 upper-order : IRPR16H
(Interrupt Request Peripheral Read register 16H) .......................................................................................... 499
4.32. Interrupt Request Batch Read Register 16 lower-order : IRPR16L
(Interrupt Request Peripheral Read register 16L) .......................................................................................... 499
4.33. Interrupt Request Batch Read Register17 upper-order : IRPR17H
(Interrupt Request Peripheral Read register 17H) .......................................................................................... 500
4.34. Interrupt Request Batch Read Register 17 lower-order : IRPR17L
(Interrupt Request Peripheral Read register 17L) .......................................................................................... 501
5. Operation ................................................................................................................................................................ 501
Chapter 18: PPG .............................................................................................................................................................. 502
1.
2.
3.
4.
20
Overview ................................................................................................................................................................ 503
Features .................................................................................................................................................................. 503
Configuration ......................................................................................................................................................... 508
Registers ................................................................................................................................................................. 509
4.1. PPG Control Status Register : PCN0 to PCN 87 ........................................................................................... 525
4.2. PPG Cycle Setting Register : PCSR0 to PCSR87 .......................................................................................... 529
4.3. PPG Duty Setting Register : PDUT0 to PDUT87 .......................................................................................... 530
4.4. PPG Timer Register : PTMR0 to PTMR87.................................................................................................... 531
4.5. PPG Control Status Register2 : PCN200 to PCN287 .................................................................................... 532
4.6. Start Delay Value Setting Register : PSDR0 to PSDR87 ............................................................................... 535
4.7. Timing Point Capture Value Setting Register : PTPC0 to PTPC87 ............................................................... 536
4.8. PPG Communication Mode High Format Cycle Setting Register : PHCSR0 to PHCSR3 ............................ 537
4.9. PPG Communication Mode Low Format Cycle Setting Register : PLCSR0 to PLCSR3 ............................. 538
4.10. PPG Communication Mode High Format Duty Setting Register : PHDUT0 to PHDUT3 ............................ 539
4.11. PPG Communication Mode Low Format Duty Setting Register : PLDUT0 to PLDUT3 ............................. 540
4.12. PPG Communication Mode Data Setting Register : PCMDDT0 to PCMDDT3 ........................................... 541
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4.13. PPG Communication Mode Data Bit Length Setting Register : PCMDWD0 to PCMDWD3 ...................... 542
4.14. GATE Function Control Register : GATEC0, GATEC2, GATEC4 ............................................................... 543
4.15. General-purpose Trigger Selection Register : GTRS0 to GTRS43 ................................................................ 544
4.16. General-purpose Trigger Setting Register : GTREN0 to GTREN5 ............................................................... 548
5. Operation ................................................................................................................................................................ 551
5.1. PWM Operation (Normal Wave Form) .......................................................................................................... 551
5.2. PWM Operation (Center Aligned Wave Form Selected) ............................................................................... 554
5.3. One-shot Operation (Normal Wave Form Selected) ...................................................................................... 556
5.4. One-shot Operation (Center Aligned Wave Form Selected) .......................................................................... 558
5.5. Restart Operation ........................................................................................................................................... 559
5.6. GATE Operation ............................................................................................................................................ 561
5.7. Start Delay Mode Operation (PWM Normal Wave Form Selected) .............................................................. 562
5.8. Timing Point Capture Mode Operation (PWM Normal Wave Form Selected) .............................................. 564
5.9. PPG Communication Mode Operation .......................................................................................................... 567
5.10. PPG Communication Activation .................................................................................................................... 568
5.11. PPG Communication Operation ..................................................................................................................... 569
5.12. PPG Communication Forced Stop and Restart operation .............................................................................. 573
5.13. PPG Output Pulse Polarity Selection ............................................................................................................. 575
5.14. Interrupt ......................................................................................................................................................... 577
6. Notes ...................................................................................................................................................................... 578
Chapter 19: Watchdog Timer ......................................................................................................................................... 583
1.
2.
Overview ................................................................................................................................................................ 584
Features .................................................................................................................................................................. 584
2.1. Watchdog Timer 0 (Software Watchdog) ....................................................................................................... 584
2.2. Watchdog Timer 1 (Hardware Watchdog) ...................................................................................................... 585
3. Configuration ......................................................................................................................................................... 586
4. Registers ................................................................................................................................................................. 587
4.1. Watchdog Timer 0 Control Register : WDTCR0 (WatchDog Timer 0 Configuration Register) .................... 587
4.2. Watchdog Timer 0 Clear Register : WDTCPR0 (WatchDog Timer Clear Pattern Register 0) ...................... 589
4.3. Watchdog Timer 0 Extended Configuration Register : WDTECR0
(Watchdog Timer Extended Configuration Register 0) .................................................................................. 589
4.4. Watchdog Timer 1 Cycle information Register : WDTCR1
(WatchDog Timer Cycle information Register 1) .......................................................................................... 591
4.5. Watchdog Timer 1 Clear Register : WDTCPR1 (WatchDog Timer Clear Pattern Register 1) ...................... 591
5. Operation ................................................................................................................................................................ 592
5.1. Software Watchdog Function ......................................................................................................................... 592
5.1.1.
Settings .................................................................................................................................................. 592
5.1.2.
Activation .............................................................................................................................................. 593
5.1.3.
Operation ............................................................................................................................................... 593
5.2. Hardware Watchdog Function ........................................................................................................................ 594
5.2.1.
Settings .................................................................................................................................................. 594
5.2.2.
Activation .............................................................................................................................................. 594
5.2.3.
Operation ............................................................................................................................................... 595
6. Usage Example ....................................................................................................................................................... 596
Chapter 20: Base Timer .................................................................................................................................................. 597
1.
2.
Overview ................................................................................................................................................................ 598
Features .................................................................................................................................................................. 598
2.1. 16/32-bit Reload Timer .................................................................................................................................. 598
2.2. 16-bit PWM Timer ......................................................................................................................................... 599
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2.3. 16/32-bit PWC Timer ..................................................................................................................................... 600
2.4. 16-bit PPG Timer ........................................................................................................................................... 601
3. Configuration ......................................................................................................................................................... 602
4. Registers ................................................................................................................................................................. 603
4.1. Common Registers ......................................................................................................................................... 605
4.1.1.
Timer Registers 0, 1 : BTxTMR (Base Timer 0/1 TiMer Register) ....................................................... 605
4.1.2.
Timer Control Registers 0, 1 : BTxTMCR (Base Timer 0/1 TiMer Control Register) .......................... 606
4.1.3.
I/O Selection Register : BTSEL01 (Base Timer SELect register ch.0 and ch.1) ................................... 612
4.1.4.
Simultaneous Software Activation Register : BTSSSR
(Base Timer Software Synchronous Start Register) .............................................................................. 613
4.2. Registers for 16/32-bit Reload Timer ............................................................................................................. 614
4.2.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) ........................................... 614
4.2.2.
Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse Counter Start Register) ..................... 615
4.3. Registers for 16-bit PWM Timer ................................................................................................................... 616
4.3.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) ........................................... 616
4.3.2.
Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse Counter Start Register) ..................... 618
4.3.3.
Duty Setting Registers 0, 1 : BTxPDUT (Base Timer 0/1 Pulse DuTy register) ................................... 619
4.4. Registers for 16-bit PPG Timer ...................................................................................................................... 620
4.4.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) ........................................... 620
4.4.2.
L Width Setting Registers 0, 1 : BTxPRLL (Base Timer 0/1 Pulse Length of "L" register) .................. 621
4.4.3.
H Width Setting Registers 0, 1 : BTxPRLH (Base Timer 0/1 Pulse Length of "H" register) ................ 622
4.5. 16/32-bit PWC Timer Register ...................................................................................................................... 623
4.5.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) ........................................... 623
4.5.2.
Data Buffer Registers 0, 1 : BTxDTBF (Base Timer 0/1 DaTa BuFfer register) .................................. 625
5. Operation ................................................................................................................................................................ 626
5.1. Selection of Timer Function ........................................................................................................................... 626
5.2. I/O Allocation ................................................................................................................................................ 626
5.3. 32-bit Mode Operation ................................................................................................................................... 630
5.3.1.
32-bit Mode Function ............................................................................................................................ 630
5.3.2.
32-bit Mode Setting ............................................................................................................................... 630
5.3.3.
32-bit Mode Operation .......................................................................................................................... 630
5.4. 16/32-bit Reload Timer Operation ................................................................................................................. 631
5.4.1.
Overview ............................................................................................................................................... 633
5.4.2.
Operation in Reload Mode .................................................................................................................... 633
5.4.3.
Operation in One-Shot Mode ................................................................................................................ 636
5.4.4.
32-bit Timer Mode Operation ................................................................................................................ 637
5.4.5.
Interrupts ............................................................................................................................................... 640
5.4.6.
Precautions for Using this Device ......................................................................................................... 641
5.5. 16-bit PWM Timer Operation ........................................................................................................................ 642
5.5.1.
Overview ............................................................................................................................................... 643
5.5.2.
Operation in Reload Mode .................................................................................................................... 643
5.5.3.
Operation in One-Shot Mode ................................................................................................................ 648
5.5.4.
Interrupt ................................................................................................................................................. 650
5.5.5.
Precautions for Using this Device ......................................................................................................... 651
5.6. 16-bit PPG Timer Operation .......................................................................................................................... 652
5.6.1.
Overview ............................................................................................................................................... 652
5.6.2.
Pulse Width Calculation Method ........................................................................................................... 653
5.6.3.
Operation in Reload Mode .................................................................................................................... 653
5.6.4.
Operation in One-Shot Mode ................................................................................................................ 658
5.6.5.
Interrupts ............................................................................................................................................... 661
5.6.6.
Application Notes .................................................................................................................................. 662
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5.7. 16/32-bit PWC Timer Operation .................................................................................................................... 663
5.7.1.
Overview ............................................................................................................................................... 665
5.7.2.
Operation during PWC Measurement ................................................................................................... 669
5.7.3.
32-bit Timer Mode Operation ................................................................................................................ 672
5.7.4.
Interrupt ................................................................................................................................................. 675
5.7.5.
Application Notes .................................................................................................................................. 676
Chapter 21: Reload Timer .............................................................................................................................................. 677
1.
2.
3.
4.
Overview ................................................................................................................................................................ 678
Features .................................................................................................................................................................. 679
Configuration ......................................................................................................................................................... 680
Registers ................................................................................................................................................................. 681
4.1. Control Status Register : TMCSR (TiMer Control and Status Register) ....................................................... 683
4.2. 16-bit Timer Register : TMR (16bit TiMer Register) ..................................................................................... 687
4.3. 16-bit Timer Reload Register A, 16-bit Timer Reload Register B : TMRLRA, TMRLRB
(16bit TiMer ReLoad Register A/B) .............................................................................................................. 688
5. Operation ................................................................................................................................................................ 690
5.1. Setting ............................................................................................................................................................ 690
5.1.1.
Count Source ......................................................................................................................................... 691
5.1.2.
Timer Underflow cycle .......................................................................................................................... 691
5.1.3.
Trigger ................................................................................................................................................... 691
5.1.4.
Gate ....................................................................................................................................................... 692
5.1.5.
Counter Operation Selection ................................................................................................................. 692
5.1.6.
TOUT Pin Level Setting ........................................................................................................................ 693
5.2. Operation Procedure ...................................................................................................................................... 695
5.2.1.
Activation .............................................................................................................................................. 695
5.2.2.
Retrigger ................................................................................................................................................ 697
5.2.3.
Underflow/Reload ................................................................................................................................. 699
5.2.4.
Generation of Interrupt Requests ........................................................................................................... 699
5.2.5.
Concurrent Operation of Register Write and Timer Activation ............................................................. 700
5.3. Operations of Each Counter ........................................................................................................................... 701
5.3.1.
Single One-shot Operation .................................................................................................................... 701
5.3.2.
Single Reload Operation........................................................................................................................ 703
5.3.3.
Dual One-shot Operation ....................................................................................................................... 705
5.3.4.
Dual Reload Operation .......................................................................................................................... 707
5.3.5.
Compare One-shot Operation ................................................................................................................ 709
5.3.6.
Compare Reload Operation ................................................................................................................... 712
5.3.7.
Capture Mode ........................................................................................................................................ 715
5.4. Cascade Input ................................................................................................................................................. 718
5.5. Priority of Concurrent Operations .................................................................................................................. 718
6. Application Note .................................................................................................................................................... 719
6.1. Single One-shot Timer ................................................................................................................................... 720
6.2. Reload Timer .................................................................................................................................................. 723
6.3. PPG ................................................................................................................................................................ 726
6.4. PWM .............................................................................................................................................................. 729
6.5. PWC ............................................................................................................................................................... 732
Chapter 22: 32-Bit Free-Run Timer ............................................................................................................................... 734
1.
2.
Overview ................................................................................................................................................................ 735
Features .................................................................................................................................................................. 736
2.1. Functions of the 32-bit Free-run Timer .......................................................................................................... 736
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2.2. Functions of the Free-run Timer Selector ...................................................................................................... 736
Configuration ......................................................................................................................................................... 737
3.1. Configuration Diagram of the 32-bit Free-run Timer .................................................................................... 737
3.2. Configuration Diagram of the Free-run Timer Selector ................................................................................. 738
4. Registers ................................................................................................................................................................. 739
4.1. Registers of the 32-bit Free-run Timer ........................................................................................................... 741
4.1.1.
Timer Control Register (Upper Bit) : TCCSH ....................................................................................... 741
4.1.2.
Timer Control Register (Lower Bit) : TCCSL ....................................................................................... 742
4.1.3.
Compare Clear Register : CPCLR ......................................................................................................... 744
4.1.4.
Timer Data Register : TCDT ................................................................................................................. 745
4.2. Registers of the Free-run Timer Selector ....................................................................................................... 746
4.2.1.
Free-run Timer Selection Register : FRS ............................................................................................... 746
5. Operation ................................................................................................................................................................ 757
5.1. Operation of the 32-bit Free-run Timer .......................................................................................................... 757
5.1.1.
Count Operation .................................................................................................................................... 757
5.1.2.
Counting Up .......................................................................................................................................... 759
5.1.3.
Timer Clear ............................................................................................................................................ 759
5.1.4.
Each Clear Operations of the Free-run Timer ........................................................................................ 760
5.1.5.
Timer Interrupt ...................................................................................................................................... 761
5.2. Operation of the 32-bit Free-run Timer Selector ............................................................................................ 762
6. Setting .................................................................................................................................................................... 763
7. Q&A ....................................................................................................................................................................... 764
7.1. How to Select Internal Clock Dividers .......................................................................................................... 764
7.2. How to Select the External Clock .................................................................................................................. 765
7.3. How to Enable/Disable the Count Operation of the Free-run Timer .............................................................. 765
7.4. How to Clear the Free-run Timer ................................................................................................................... 766
7.5. About Interrupt Related Registers .................................................................................................................. 766
7.6. How to Enable Compare Clear Interrupt ....................................................................................................... 767
7.7. How to Stop the Free-run Timer Operation ................................................................................................... 767
8. Sample Program ..................................................................................................................................................... 768
9. Notes ...................................................................................................................................................................... 769
3.
Chapter 23: 32-Bit Output Compare ............................................................................................................................. 770
1.
2.
3.
4.
Overview ................................................................................................................................................................ 771
Features .................................................................................................................................................................. 771
Configuration Diagram........................................................................................................................................... 774
Registers ................................................................................................................................................................. 775
4.1. Output Control Register (Upper Bit) : OCSH ................................................................................................ 776
4.2. Output Control Register (Lower Bit) : OCSL ................................................................................................ 778
4.3. Compare Register : OCCP ............................................................................................................................. 779
4.4. Output Level Control Register : OCLS .......................................................................................................... 780
5. Operation ................................................................................................................................................................ 781
5.1. Output Compare Output (Independent Invert) CMOD = "0" ......................................................................... 781
5.2. Output Compare Output (Coordinated Invert) CMOD = "1" ......................................................................... 783
5.3. Output Compare Operation Timing ............................................................................................................... 784
5.3.1.
Compare Register Write ........................................................................................................................ 784
5.3.2.
Compare Match, Interrupt ..................................................................................................................... 785
5.3.3.
Pin Output ............................................................................................................................................. 785
6. Setting .................................................................................................................................................................... 786
7. Q&A ....................................................................................................................................................................... 787
7.1. How to Set the Compare Value ...................................................................................................................... 787
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7.2. How to Set the Compare Mode (Example with OCU7) ................................................................................. 787
7.3. How to Enable/Disable the Compare Operation (Example with OCU6, 7) ................................................... 788
7.4. How to Set the Compare Pin Output Initial Level (Example with OCU6, 7) ................................................ 788
7.5. How to Set the Compare Pin OCU6-OCU7 for Output ................................................................................. 789
7.6. How to Clear the Free-run Timer ................................................................................................................... 789
7.7. How to Enable the Compare Operation (Example with OCU6, 7) ................................................................ 789
7.8. Interrupt Related Register .............................................................................................................................. 789
7.9. Interrupt Type ................................................................................................................................................. 790
7.10. How to Enable the Interrupt ........................................................................................................................... 790
7.11. Calculation Method for the Compare Value ................................................................................................... 790
7.11.1. Toggle Output Pulse .............................................................................................................................. 790
7.11.2. PWM Output ......................................................................................................................................... 791
7.12. How to Set the Operation Mode .................................................................................................................... 792
8. Sample Program ..................................................................................................................................................... 792
9. Notes ...................................................................................................................................................................... 795
Chapter 24: 32-Bit Input Capture .................................................................................................................................. 796
1.
2.
3.
4.
Overview ................................................................................................................................................................ 797
Features .................................................................................................................................................................. 797
Configuration ......................................................................................................................................................... 799
Registers ................................................................................................................................................................. 800
4.1. Input Capture Data Register : IPCP ............................................................................................................... 802
4.2. Input Capture Control Register : ICS ............................................................................................................. 802
4.3. LIN SYNCH FIELD Switching Register : LSYNS ....................................................................................... 804
4.4. Cycle Measurement Data Register : MSCY .................................................................................................. 806
4.5. Cycle and Pulse Width Measurement Control Register (Upper bit) : MSCH ................................................ 807
4.6. Cycle and Pulse Width Measurement Control Register (Lower bit) : MSCL ................................................ 809
5. Operation ................................................................................................................................................................ 810
5.1. Capture and Interrupt Timings ....................................................................................................................... 810
5.2. Edge Detection Specifications for Input Capture And Their Operations ....................................................... 812
5.3. Cycle and Pulse Width Measurement Operation ............................................................................................ 813
6. Setting .................................................................................................................................................................... 817
7. Q&A ....................................................................................................................................................................... 818
7.1. Effective Edge Polarity of External Input: Types and How to Select Them .................................................. 818
7.2. How to Enable External Input Pins (ICU4 to ICU11) .................................................................................... 818
7.3. About Interrupt Related Registers .................................................................................................................. 819
7.4. About Interrupt Types .................................................................................................................................... 819
7.5. How to Enable Interrupt ................................................................................................................................. 819
7.6. How to Measure the Pulse Width of the Input Signal .................................................................................... 820
7.7. How to Set the Operation Mode .................................................................................................................... 820
8. Sample Program ..................................................................................................................................................... 821
9. Notes ...................................................................................................................................................................... 822
Chapter 25: 16-Bit Free-Run Timer ............................................................................................................................... 823
1.
2.
3.
4.
Overview ................................................................................................................................................................ 824
Features .................................................................................................................................................................. 824
Configuration ......................................................................................................................................................... 825
Registers ................................................................................................................................................................. 828
4.1. Registers for the Free-run Timer Simultaneous Activation ............................................................................ 829
4.1.1.
Timer Synchronous Activation Register : (TCGS) ................................................................................ 829
4.1.2.
Timer Synchronous Activation Enable Register : TCGSE .................................................................. 831
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4.2. Registers for the 16-bit Free-run Timer ......................................................................................................... 831
4.2.1.
Compare Clear Buffer Register : CPCLRB/ Compare Clear Register : CPCLR ................................... 832
4.2.2.
Timer Data Register : TCDT0 to TCDT2 .............................................................................................. 834
4.2.3.
Timer State Control Register : TCCS0 to TCCS2 ................................................................................. 835
4.3. Register for the Free-run Timer Selector ....................................................................................................... 842
4.3.1.
Free-run Timer Selection Register : FRS ............................................................................................... 842
5. Operation ................................................................................................................................................................ 858
5.1. Interrupt for the 16-bit Free-run Timer .......................................................................................................... 858
5.2. Operation of the 16-bit Free-run Timer .......................................................................................................... 859
5.2.1.
Timer Clear ............................................................................................................................................ 859
5.2.2.
Timer Mode ........................................................................................................................................... 860
5.2.3.
Compare Clear Buffer ........................................................................................................................... 861
5.2.4.
Timer Interrupt ...................................................................................................................................... 862
5.2.5.
Interrupt Mask Function ........................................................................................................................ 863
5.2.6.
Selected External Count Clock .............................................................................................................. 865
5.3. Operation of the Free-run Timer Selector ...................................................................................................... 866
5.4. Notes on Operating Specifications ................................................................................................................. 868
5.4.1.
Notes at Accessing the Buffer Registers ................................................................................................ 868
5.4.2.
Notes on Using the 16-bit Free-run Timer ............................................................................................. 868
5.4.3.
Notes on Using the Free-run Timer Selector ......................................................................................... 869
Chapter 26: 16-Bit Output Compare ............................................................................................................................. 870
1.
2.
3.
4.
Overview ................................................................................................................................................................ 871
Features .................................................................................................................................................................. 871
Configuration Diagram........................................................................................................................................... 872
Registers ................................................................................................................................................................. 873
4.1. 16-bit Output Compare Registers .................................................................................................................. 873
4.1.1.
Output Compare Buffer Registers (OCCPB0 to OCCPB5)/Output Compare Registers
(OCCP0 to OCCP5) .............................................................................................................................. 874
4.1.2.
Compare Control Register (OCS) .......................................................................................................... 878
4.1.3.
Compare Mode Control Register (OCMOD) ........................................................................................ 884
5. Operation ................................................................................................................................................................ 885
5.1. Interrupts for 16-bit Output Compare ............................................................................................................ 885
5.2. Operation of 16-bit Output Compare ............................................................................................................. 886
5.2.1.
Operation of 16-bit Output Compare (Inverted Mode, MOD0= 0 in OCMOD01 Register) ................. 886
5.2.2.
Operation of 16-bit Output Compare (Set/Reset Mode, MOD0 = 1 in OCMOD01 Register) .............. 890
5.2.3.
16-bit Output Compare Timing ............................................................................................................. 892
5.2.4.
Operation of 16-bit Output Compare and Free-run Timer ..................................................................... 893
5.3. Notes on Using 16-bit Output Compare......................................................................................................... 899
Chapter 27: 16-Bit Input Capture .................................................................................................................................. 900
1.
2.
3.
4.
Overview ................................................................................................................................................................ 901
Features .................................................................................................................................................................. 901
Configuration ......................................................................................................................................................... 902
Registers ................................................................................................................................................................. 903
4.1. 16-bit Input Capture Registers ....................................................................................................................... 903
4.1.1.
Input Capture Data Register : IPCP0 to IPCP3 ..................................................................................... 904
4.1.2.
Input Capture State Control Register : ICS ........................................................................................... 905
4.1.3.
LIN SYNCH FIELD Switching Register : LSYNS ............................................................................... 908
5. Operation ................................................................................................................................................................ 909
5.1. Interrupts for 16-bit Input Capture ................................................................................................................. 909
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5.2. Operation of 16-bit Input Capture .................................................................................................................. 909
5.2.1.
Operation of 16-bit Input Capture ......................................................................................................... 910
5.2.2.
16-bit Input Capture Input Timing ......................................................................................................... 911
5.3. Notes on Using the 16-bit Input Capture ....................................................................................................... 911
Chapter 28: Up/Down Counter ...................................................................................................................................... 912
1.
2.
3.
4.
Overview ................................................................................................................................................................ 913
Features .................................................................................................................................................................. 913
Configuration ......................................................................................................................................................... 915
Registers ................................................................................................................................................................. 917
4.1. Reload Compare Register (RCR0, RCR1, RCR2, RCR3) ............................................................................. 919
4.2. Up/Down Count Register (UDCR0, UDCR1, UDCR2, UDCR3) ................................................................. 920
4.3. Counter Control Register (CCR0, CCR1, CCR2, CCR3) .............................................................................. 922
4.4. Counter Status Register (CSR0, CSR1, CSR2, CSR3) .................................................................................. 927
5. Interrupt .................................................................................................................................................................. 930
6. Operation and Setting Procedure Examples ........................................................................................................... 931
6.1. Operation in Timer Mode ............................................................................................................................... 935
6.2. Operation in Up/down Count Mode ............................................................................................................... 936
6.3. Operation in the Phase Difference Count Mode (Multiply-by-Two) ............................................................. 940
6.4. Operation in the Phase Difference Count Mode (Multiply-by-Four) ............................................................. 942
Chapter 29: Real-Time Clock (RTC) ............................................................................................................................. 944
1.
2.
3.
4.
Overview ................................................................................................................................................................ 945
Features .................................................................................................................................................................. 945
Configuration ......................................................................................................................................................... 946
Registers ................................................................................................................................................................. 947
4.1. RTC Control Register : WTCR ...................................................................................................................... 948
4.2. Sub-second Register : WTBR ........................................................................................................................ 952
4.3. Day/Hour/Minute/Second Register : WTDR/ WTHR/ WTMR/ WTSR ...................................................... 953
5. Operation ................................................................................................................................................................ 955
6. Setting .................................................................................................................................................................... 958
7. Q&A ....................................................................................................................................................................... 959
7.1. How to Set the 0.5 Second Count Interval ..................................................................................................... 959
7.2. How to Initialize the Real-time Clock ........................................................................................................... 959
7.3. How to Set/Update Number of Days (Day) and Time (Hour/Minute/Second) .............................................. 960
7.4. How to Start/Stop the Count of the Real-time Clock ..................................................................................... 960
7.5. How to Confirm That the Real-time Clock Is Running ................................................................................. 960
7.6. How to Know the Number of Days and Time ................................................................................................ 960
7.7. How to Stop the Real-time Clock .................................................................................................................. 961
7.8. How to Calibrate the Real-time Clock ........................................................................................................... 961
7.9. Interrupt Related Registers............................................................................................................................. 961
7.10. Interrupt Types and How to Select Them ....................................................................................................... 962
7.11. How to Enable Interrupts ............................................................................................................................... 962
8. Sample Program ..................................................................................................................................................... 963
9. Notes ...................................................................................................................................................................... 964
Chapter 30: RTC/WDT1 Calibration ............................................................................................................................ 966
1.
2.
3.
4.
Overview ................................................................................................................................................................ 967
Features .................................................................................................................................................................. 967
Configuration ......................................................................................................................................................... 968
Registers ................................................................................................................................................................. 969
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4.1. Calibration Unit Control Register 0 : CUCR0 (Calibration Unit Control Register 0) ................................... 969
4.2. Sub Clock Timer Data Register : CUTD0 (Calibration Unit Timer Data register 0) ..................................... 971
4.3. Main Oscillation Timer Result Register 0 : CUTR0 (Calibration Unit Timer Result register 0) ................. 972
4.4. Calibration Unit Control Register 1 : CUCR1 (Calibration Unit Control Register 1) ................................... 973
4.5. CR Clock Timer Data Register : CUTD1 (Calibration Unit Timer Data register 1) ...................................... 974
4.6. Main Oscillation Timer Result Register 1 : CUTR1 (Calibration Unit Timer Result register 1) ................... 975
5. Operation ................................................................................................................................................................ 976
5.1. Real-Time Clock (RTC) Calibration .............................................................................................................. 976
5.2. Measurement of Errors in CR Clock .............................................................................................................. 976
5.3. Note................................................................................................................................................................ 977
Chapter 31: Power Consumption Control ..................................................................................................................... 978
1.
2.
3.
4.
Overview ................................................................................................................................................................ 979
Features .................................................................................................................................................................. 979
Configuration ......................................................................................................................................................... 980
Registers ................................................................................................................................................................. 982
4.1. Standby Control Register: STBCR (STandBy mode Control Register) ......................................................... 982
4.2. PMU Control Register : PMUCTLR (Power Management Unit ConTroL Register) .................................... 984
4.3. Power on Timing Control Register : PWRTMCTL (PoWeR on TiMing ConTroL register) .......................... 985
4.4. PMU Interrupt Flag Register 0 : PMUINTF0 (Power Management Unit INTerrupt Flag0 register) ............. 986
4.5. PMU Interrupt Flag Register 1 : PMUINTF1 (Power Management Unit INTerrupt Flag1 register) ............. 986
4.6. PMU Interrupt Flag Register 2 : PMUINTF2 (Power Management Unit INTerrupt Flag2 register) ............. 987
4.7. PMU Interrupt Flag Register 3 : PMUINTF3 (Power Management Unit INTerrupt Flag3 register) ............. 988
5. Operation ................................................................................................................................................................ 989
5.1. Clock Control ................................................................................................................................................. 990
5.1.1.
Division Setting ..................................................................................................................................... 990
5.1.2.
Stopping of Unused Clocks ................................................................................................................... 990
5.2. List of Clocks Supplied in Low-power Consumption Mode.......................................................................... 991
5.3. Sleep Mode .................................................................................................................................................... 992
5.3.1.
CPU Sleep Mode ................................................................................................................................... 992
5.3.2.
Bus Sleep Mode..................................................................................................................................... 992
5.3.3.
Configuration of Sleep Mode ................................................................................................................ 993
5.3.4.
Activation of Sleep Mode ...................................................................................................................... 993
5.3.5.
Wake Up from the Sleep Mode ............................................................................................................. 994
5.3.6.
Effect of Sleep Mode ............................................................................................................................. 994
5.4. Standby Mode : Watch Mode ......................................................................................................................... 994
5.4.1.
Configuration of Watch Mode ............................................................................................................... 995
5.4.2.
Activation of Watch Mode..................................................................................................................... 995
5.4.3.
Wake Up from the Watch Mode ............................................................................................................ 996
5.4.4.
Effect of Watch Mode ............................................................................................................................ 996
5.5. Standby Mode : Watch Mode with Power-shutdown ..................................................................................... 996
5.5.1.
Configuration of Watch Mode with Power-shutdown ........................................................................... 997
5.5.2.
Activation of Watch Mode with Power-shutdown ................................................................................. 997
5.5.3.
Wake Up from the Watch Mode with Power-shutdown ........................................................................ 999
5.5.4.
Effect of Watch Mode with Power-shutdown ...................................................................................... 1000
5.6. Standby Mode : Stop Mode ......................................................................................................................... 1001
5.6.1.
Configuration of Stop Mode ................................................................................................................ 1001
5.6.2.
Activation of Stop Mode ..................................................................................................................... 1001
5.6.3.
Wake Up from the Stop Mode ............................................................................................................. 1002
5.6.4.
Effect of Stop Mode ............................................................................................................................ 1002
5.7. Standby Mode : Stop Mode with Power-shutdown...................................................................................... 1002
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5.7.1.
Configuration of Stop Mode with Power-shutdown ............................................................................ 1003
5.7.2.
Activation of Stop Mode with Power-shutdown ................................................................................. 1003
5.7.3.
Wake Up from the Stop Mode with Power-shutdown ......................................................................... 1005
5.7.4.
Effect of Stop Mode with Power-shutdown......................................................................................... 1007
5.8. Stop State of Microcontroller ....................................................................................................................... 1007
5.9. Transition to Illegal Standby Mode .............................................................................................................. 1007
5.10. Restrictions on Power-Shutdown and Normal Standby Control .................................................................. 1008
6. Usage Example ..................................................................................................................................................... 1011
Chapter 32: Low-Voltage Detection (Internal Low-Voltage Detection) .................................................................... 1012
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1013
Features ................................................................................................................................................................ 1013
Configuration ....................................................................................................................................................... 1014
Registers ............................................................................................................................................................... 1014
4.1. Internal Low-Voltage Detection Register : LVD (Low-Voltage Detect internal power fall register) ........... 1015
5. Operation .............................................................................................................................................................. 1016
5.1. Internal Low-voltage Detection ................................................................................................................... 1016
6. Notes .................................................................................................................................................................... 1017
Chapter 33: Low-Voltage Detection (External Low-Voltage Detection) ................................................................... 1018
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1019
Features ................................................................................................................................................................ 1019
Configuration ....................................................................................................................................................... 1020
Registers ............................................................................................................................................................... 1020
4.1. External Low-Voltage Detection Rise Detection Register : LVD5R (Low-Voltage Detect external 5v Rise
register) ........................................................................................................................................................ 1021
4.2. External Low-Voltage Detection Fall Detection Register : LVD5F (Low-Voltage Detect external 5v Fall
register) ........................................................................................................................................................ 1022
5. Operation .............................................................................................................................................................. 1024
6. Notes .................................................................................................................................................................... 1024
Chapter 34: Wild Register ............................................................................................................................................ 1026
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1027
Features ................................................................................................................................................................ 1027
Configuration ....................................................................................................................................................... 1027
Registers ............................................................................................................................................................... 1028
4.1. Wild Register Data Enable Register : WREN (Wild Register ENable register) ........................................ 1029
4.2. Wild Register Address Register 00 to 15 : WRAR00 to 15 (Wild Register Address Register 00 to 15) ...... 1030
4.3. Wild Register Data Register 00 to 15 : WRDR00 to 15 (Wild Register Data Register 00 to 15) ................ 1031
5. Operation .............................................................................................................................................................. 1031
6. Usage Example ..................................................................................................................................................... 1032
Chapter 35: Clock Supervisor ...................................................................................................................................... 1033
1.
2.
3.
Overview .............................................................................................................................................................. 1034
Configuration ....................................................................................................................................................... 1034
Register ................................................................................................................................................................ 1035
3.1. Clock Supervisor Control Register : CSVCR (Clock SuperVisor Control Register) ................................... 1036
4. Operation .............................................................................................................................................................. 1038
4.1. Initial State ................................................................................................................................................... 1039
4.2. Stopping CR Oscillator and the Clock Supervisor Function ........................................................................ 1040
4.3. Re-enabling the Clock Supervisor ............................................................................................................... 1040
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4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
Sub Clock Mode .......................................................................................................................................... 1041
Stop Mode .................................................................................................................................................... 1041
Watch Mode ................................................................................................................................................. 1042
Checking the Reset Factor Using the Clock Supervisor .............................................................................. 1043
Return from CR Clock ................................................................................................................................. 1043
Sub Clock Mode Enabled by Setting SCKS Bit .......................................................................................... 1044
Chapter 36: Regulator Control ..................................................................................................................................... 1045
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1046
Features ................................................................................................................................................................ 1046
Configuration ....................................................................................................................................................... 1047
Register ................................................................................................................................................................ 1048
4.1. Regulator Output Voltage Select Register : REGSEL (REGulator output voltage SELect register) ............ 1048
5. Operation .............................................................................................................................................................. 1049
Chapter 37: External Bus Interface ............................................................................................................................. 1050
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1051
Features ................................................................................................................................................................ 1051
Configuration ....................................................................................................................................................... 1052
Registers ............................................................................................................................................................... 1053
4.1. CS Area Setting Registers: ASR0 to ASR3 (Area Setting Register 0-3) ...................................................... 1054
4.2. CS Bus Setting Registers: ACR0 to ACR3 (Area Configuration Register 0-3) ........................................... 1057
4.3. CS Wait Registers : AWR0 to AWR3 (Area Wait Register 0-3)................................................................... 1059
4.4. External DMA Transfer Registers: DMAR0-3 (DMA transfer Register 0-3) .............................................. 1064
5. Operation .............................................................................................................................................................. 1065
5.1. External Pin Table ........................................................................................................................................ 1066
5.2. External Bus Signal Protocol ....................................................................................................................... 1068
5.2.1.
Address/Data Split Bus Read Protocol ................................................................................................ 1068
5.2.2.
Address/Data split bus write protocol.................................................................................................. 1070
5.2.3.
Address/data multiplexed bus read protocol ........................................................................................ 1072
5.2.4.
Address/Data multiplexed bus write protocol ..................................................................................... 1074
5.3. Address Alignment....................................................................................................................................... 1075
5.4. Split Access .................................................................................................................................................. 1076
5.5. Data Alignment ............................................................................................................................................ 1076
5.6. Address Information .................................................................................................................................... 1079
5.6.1.
Address information and output pins ................................................................................................... 1079
5.6.2.
Address type ........................................................................................................................................ 1079
5.7. Idle Cycle Insertion Function ....................................................................................................................... 1080
5.8. External Bus Output Signal Timing Settings ............................................................................................... 1081
5.9. RDY Pin Access Cycle Extension Function................................................................................................. 1086
5.10. CS Setting Flow ........................................................................................................................................... 1087
5.11. Example of Connecting to Asynchronous Memory ..................................................................................... 1093
5.12. Example of Connection to Little Endian Device ......................................................................................... 1095
Chapter 38: Bus Performance Counters ...................................................................................................................... 1096
1.
2.
3.
4.
30
Overview .............................................................................................................................................................. 1097
Features ................................................................................................................................................................ 1097
Configuration ....................................................................................................................................................... 1098
Registers ............................................................................................................................................................... 1099
4.1. BPC-A Control Register : BPCCRA (Bus Performance Counter Control Register A) ................................ 1099
4.2. BPC-B Control Register : BPCCRB (Bus Performance Counter Control Register B) ................................ 1100
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4.3. BPC-C Control Register : BPCCRC (Bus Performance Counter Control Register C) ................................ 1101
4.4. BPC-A Count Register : BPCTRA (Bus Performance CounTer Register A) ............................................... 1101
4.5. BPC-B Count Register : BPCTRB (Bus Performance CounTer Register B) ............................................... 1102
4.6. BPC-C Count Register : BPCTRC (Bus Performance CounTer Register C) ............................................... 1102
5. Operation .............................................................................................................................................................. 1103
5.1. Setting .......................................................................................................................................................... 1103
5.2. Starting and Stopping ................................................................................................................................... 1104
5.3. Operation ..................................................................................................................................................... 1105
5.4. Measurement and Result Processing ............................................................................................................ 1105
Chapter 39: CRC ........................................................................................................................................................... 1107
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1108
Features ................................................................................................................................................................ 1108
Configuration ....................................................................................................................................................... 1108
Registers ............................................................................................................................................................... 1109
4.1. CRC Control Register : CRCCR (CRC Control Register) ....................................................................... 1109
4.2. CRC Initial Value Register : CRCINIT (CRC Initial value register) ............................................................1110
4.3. CRC Input Data Register : CRCIN (CRC INput data register) ..................................................................... 1111
4.4. CRC Register : CRCR (CRC Register) ......................................................................................................... 1111
5. Operation ...............................................................................................................................................................1112
5.1. CRC Definition .............................................................................................................................................1112
5.2. Reset Operation .............................................................................................................................................1112
5.3. Initialization ..................................................................................................................................................1113
5.4. Byte and Bit Orders ......................................................................................................................................1113
5.5. CRC Calculation Sequence ...........................................................................................................................1113
5.6. Examples .......................................................................................................................................................1115
5.6.1.
Example 1 CRC16, Fixed Byte Input ...................................................................................................1115
5.6.2.
Example 2 CRC16, Mixture of Different Input Bit Widths ..................................................................1117
5.6.3.
Example 3 CRC32, Byte Order, Big-endian .........................................................................................1118
5.6.4.
Example 4 CRC32, Byte Order, Little-endian ......................................................................................1119
Chapter 40: RAMECC .................................................................................................................................................. 1120
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1121
Features ................................................................................................................................................................ 1121
Configuration ....................................................................................................................................................... 1121
Registers ............................................................................................................................................................... 1124
4.1. Single-bit ECC Error Address Register XBS RAM : SEEARX .................................................................. 1125
4.2. Double-bit ECC Error Address Register XBS RAM : DEEARX ................................................................ 1126
4.3. ECC Error Control Register XBS RAM : EECSRX .................................................................................... 1127
4.4. ECC False Error Generation Address Register XBS RAM : EFEARX ....................................................... 1128
4.5. ECC False Error Generation Control Register XBS RAM : EFECRX ........................................................ 1129
4.6. Single-bit ECC Error Address Register BACKUP-RAM : SEEARA.......................................................... 1131
4.7. Double-bit ECC Error Address Register BACKUP-RAM : DEEARA ....................................................... 1132
4.8. ECC Error Control Register BACKUP-RAM : EECSRA ........................................................................... 1133
4.9. ECC False Error Generation Address Register BACKUP-RAM : EFEARA .............................................. 1134
4.10. ECC False Error Generation Control Register BACKUP-RAM : EFECRA ............................................... 1135
4.11. Single-bit ECC Error Address Register AHB RAM : SEEARH .................................................................. 1137
4.12. Double-bit ECC Error Address Register AHB RAM : DEEARH ................................................................ 1138
4.13. ECC Error Control Register AHB RAM : EECSRH ................................................................................... 1139
4.14. ECC False Error Generation Address Register AHB RAM : EFEARH....................................................... 1140
4.15. ECC False Error Generation Control Register AHB RAM : EFECRH ....................................................... 1141
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5.
Operation .............................................................................................................................................................. 1143
5.1. RAMECC Function ..................................................................................................................................... 1143
5.2. Interrupt-related Register ............................................................................................................................. 1144
5.3. Test Mode .................................................................................................................................................... 1145
5.4. Note.............................................................................................................................................................. 1146
Chapter 41: Multi-Function Serial Interface .............................................................................................................. 1147
1.
2.
3.
4.
32
Overview .............................................................................................................................................................. 1148
Features ................................................................................................................................................................ 1148
Configuration ....................................................................................................................................................... 1155
Registers ............................................................................................................................................................... 1156
4.1. Common Registers ....................................................................................................................................... 1159
4.1.1.
Serial Mode Register: SMR ................................................................................................................. 1160
4.1.2.
FIFO Control Register 1: FCR1 .......................................................................................................... 1163
4.1.3.
FIFO Control Register 0: FCR0 .......................................................................................................... 1165
4.1.4.
FIFO BYTE Register: FBYTE ............................................................................................................ 1168
4.1.5.
Transmission FIFO Interrupt Control Register: FTICR ...................................................................... 1170
4.2. Registers for UART ..................................................................................................................................... 1171
4.2.1.
Serial Control Register: SCR ............................................................................................................... 1171
4.2.2.
Serial Status Register: SSR ................................................................................................................. 1172
4.2.3.
Extended Serial Control Register: ESCR ............................................................................................ 1175
4.2.4.
Receive Data Register/Transmit Data Register: RDR/TDR ................................................................ 1176
4.2.5.
Serial Aid Control Status Register: SACSR ........................................................................................ 1178
4.2.6.
Serial TiMer Register: STMR.............................................................................................................. 1180
4.2.7.
Serial Timer Comparison Register: STMCR ....................................................................................... 1181
4.2.8.
Baud rate Generator Register: BGR .................................................................................................... 1182
4.3. Registers for CSIO ....................................................................................................................................... 1183
4.3.1.
Serial Control Register: SCR ............................................................................................................... 1183
4.3.2.
Serial Status Register: SSR ................................................................................................................. 1185
4.3.3.
Extended Serial Control Register: ESCR ............................................................................................ 1187
4.3.4.
Receive Data Register/Transmit Data Register: RDR/TDR ................................................................ 1189
4.3.5.
Serial Aid Control Status Register: SACSR ........................................................................................ 1193
4.3.6.
Serial Timer Register: STMR .............................................................................................................. 1197
4.3.7.
Serial Timer Compare Register: STMCR ............................................................................................ 1198
4.3.8.
Serial Chip Select Control Status Register: SCSCR ............................................................................ 1199
4.3.9.
Serial Chip Select Timing Register: SCSTR3-0 .................................................................................. 1202
4.3.10. Serial Chip Select Format Register: SCSFR2-0 .................................................................................. 1206
4.3.11. Transfer BYTE register: TBYTE3-0 ................................................................................................... 1213
4.3.12. Baud rate Generator Register: BGR .................................................................................................... 1215
4.4. Registers for LIN ......................................................................................................................................... 1215
4.4.1.
Serial Control Register: SCR ............................................................................................................... 1216
4.4.2.
Serial Status Register: SSR ................................................................................................................. 1219
4.4.3.
Extended Serial Control Register: ESCR ............................................................................................ 1222
4.4.4.
Receive Data Register/Transmit Data Register: RDR/TDR ................................................................ 1224
4.4.5.
Serial Aid Control Status Register: SACSR ........................................................................................ 1226
4.4.6.
Serial Timer Register: STMR .............................................................................................................. 1229
4.4.7.
Serial Timer Compare Register: STMCR ............................................................................................ 1230
4.4.8.
Sync Field Upper limit Register: SFUR .............................................................................................. 1231
4.4.9.
Sync Field Lower limit Register: SFLR .............................................................................................. 1232
4.4.10. Baud Rate Generator Register: BGR ................................................................................................... 1233
4.4.11. LIN Assist Mode Status Register: LAMSR ......................................................................................... 1234
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4.4.12. LIN Assist Mode Control Register: LAMCR ...................................................................................... 1236
4.4.13. LIN Assist Mode Interrupt Enable Register: LAMIER ....................................................................... 1239
4.4.14. LIN Assist Mode Transmission/Reception ID register: LAMTID / LAMRID .................................... 1240
4.4.15. LIN Assist Mode Error Status Register: LAMESR ............................................................................. 1242
4.4.16. LIN Assist Mode trouble Examination Register: LAMERT ................................................................ 1244
4.5. Registers for I2C ........................................................................................................................................... 1247
4.5.1.
I2C Bus Control Register: IBCR .......................................................................................................... 1247
4.5.2.
Serial Status Register: SSR ................................................................................................................. 1253
4.5.3.
I2C Bus Status Register: IBSR............................................................................................................. 1257
4.5.4.
Receive Data Register/Transmit Data Register: RDR/TDR ................................................................ 1261
4.5.5.
Serial Aid Control Status Register: SACSR ........................................................................................ 1263
4.5.6.
Serial Timer Register: STMR .............................................................................................................. 1265
4.5.7.
Serial Timer Compare Register: STMCR ............................................................................................ 1266
4.5.8.
7-bit Slave Address Mask Register: ISMK .......................................................................................... 1267
4.5.9.
7-bit Slave Address Register: ISBA .................................................................................................... 1269
4.5.10. Baud rate Generator Register: BGR .................................................................................................... 1270
5. Operation of UART .............................................................................................................................................. 1270
5.1. Interrupt of UART........................................................................................................................................ 1271
5.1.1.
List of Interrupt of UART .................................................................................................................... 1271
5.1.2.
Reception Interrupts and Flag Setting Timing ..................................................................................... 1272
5.1.3.
Interrupts when Using Reception FIFO and Flag Setting Timing ....................................................... 1274
5.1.4.
Transmission Interrupts and Flag Setting Timing ................................................................................ 1276
5.1.5.
Interrupts When Using Transmission FIFO and Flag Setting Timing ................................................. 1277
5.1.6.
Timing of Timer Interrupt Generation and Flag Setting ...................................................................... 1278
5.2. Operation of UART ...................................................................................................................................... 1278
5.2.1.
Transmission/Reception Data Format ................................................................................................. 1278
5.2.2.
Transmission Operation ....................................................................................................................... 1280
5.2.3.
Reception Operation ............................................................................................................................ 1280
5.2.4.
Clock Selection.................................................................................................................................... 1281
5.2.5.
Start Bit Detection ............................................................................................................................... 1282
5.2.6.
Stop Bit ................................................................................................................................................ 1282
5.2.7.
Error Detection .................................................................................................................................... 1282
5.2.8.
Parity Bit ............................................................................................................................................. 1283
5.2.9.
Data Signaling Method ........................................................................................................................ 1284
5.2.10. Operation of Serial Timer .................................................................................................................... 1284
5.2.11. Test Mode ............................................................................................................................................ 1286
5.2.12. UART Baud Rate Selection/Setting..................................................................................................... 1287
5.3. Setup Procedure and Program Flow ............................................................................................................. 1291
5.3.1.
Operation Mode 0 (One-to-One Connection) ...................................................................................... 1291
5.3.2.
Operation Mode 1 (One-to-N Connection) .......................................................................................... 1294
6. Operation of CSIO................................................................................................................................................ 1298
6.1. Interrupts of CSIO........................................................................................................................................ 1298
6.1.1.
List of Interrupts of CSIO .................................................................................................................... 1299
6.1.2.
Reception Interrupts and Flag Setting Timing ..................................................................................... 1300
6.1.3.
Interrupts when Using Reception FIFO and Flag Setting Timing ....................................................... 1302
6.1.4.
Transmission Interrupts and Flag Setting Timing ................................................................................ 1304
6.1.5.
Interrupts When Using Transmission FIFO and Flag Setting Timing ................................................. 1305
6.1.6.
Timing of Timer Interrupt and Flag Setting ......................................................................................... 1306
6.1.7.
Timing of Chip Select Error Generation and Flag Setting ................................................................... 1307
6.2. Operation of CSIO ....................................................................................................................................... 1309
6.2.1.
Normal Transfer (I).............................................................................................................................. 1309
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6.2.2.
Normal Transfer (II) ............................................................................................................................ 1318
6.2.3.
SPI Transfer (I) .................................................................................................................................... 1327
6.2.4.
SPI Transfer (II)................................................................................................................................... 1337
6.2.5.
Operation of Serial Timer .................................................................................................................... 1346
6.2.6.
Operation of Serial Chip Select ........................................................................................................... 1349
6.2.7.
Test Mode ............................................................................................................................................ 1358
6.2.8.
Baud Rate Generation.......................................................................................................................... 1359
6.3. Setup Procedure and Program Flow ............................................................................................................. 1361
7. Operation of LIN Interface (v2.1) ........................................................................................................................ 1364
7.1. Interrupt of LIN Interface (v2.1) manual mode ........................................................................................... 1364
7.1.1.
List of Interrupts of LIN Interface (v2.1) (manual mode) ................................................................... 1365
7.1.2.
Reception Interrupts and Flag Setting Timing ..................................................................................... 1366
7.1.3.
Interrupts when Using Reception FIFO and Flag Setting Timing ....................................................... 1367
7.1.4.
Transmission Interrupts and Flag Setting Timing ................................................................................ 1369
7.1.5.
Interrupts When Using Transmission FIFO and Flag Setting Timing ................................................. 1370
7.1.6.
Timer Interrupt and Flag Setting Timing ............................................................................................. 1371
7.1.7.
Sync Field Detection Interrupts and Flag Setting Timing ................................................................... 1371
7.2. Interrupts in LIN Interface (v2.1) Assist Mode ............................................................................................ 1372
7.2.1.
List of Interrupts of LIN Interface (v2.1) (assist mode) ...................................................................... 1373
7.2.2.
Reception Interrupts and Flag Setting Timing in Assist Mode ............................................................ 1375
7.2.3.
Reception Interrupts and Flag Setting Timing when using Reception FIFO ....................................... 1380
7.2.4.
Transmission Interrupts and Flag Setting Timing ................................................................................ 1381
7.2.5.
Interrupts and Flag Setting Timing when using Transmission FIFO ................................................... 1381
7.2.6.
Timer Interrupts and Flag Setting Timing ........................................................................................... 1382
7.2.7.
Status Interrupts and Flag Setting Timing in Assist Mode .................................................................. 1382
7.3. Operation of Serial Timer ............................................................................................................................ 1384
7.4. Test Mode .................................................................................................................................................... 1386
7.4.1.
Manual Mode ...................................................................................................................................... 1386
7.4.2.
Assist Mode ......................................................................................................................................... 1387
7.5. Operation of LIN Interface (v2.1) ................................................................................................................ 1391
7.5.1.
Manual mode ....................................................................................................................................... 1392
7.5.2.
Assist Mode ......................................................................................................................................... 1406
7.5.3.
LIN Baud Rate Selection/Setting ........................................................................................................ 1426
7.6. Setup Procedure and Program Flow ............................................................................................................. 1426
7.6.1.
Manual mode ....................................................................................................................................... 1426
7.6.2.
Assist mode ......................................................................................................................................... 1431
8. Operation of I2C ................................................................................................................................................... 1436
8.1. Interrupts of I2C ........................................................................................................................................... 1436
8.1.1.
List of Interrupts of I2C Interface ........................................................................................................ 1437
8.1.2.
Timing of Timer Interrupt Generation and Flag Setting ...................................................................... 1438
8.2. Operation for I2C Interface Communication ................................................................................................ 1439
8.2.1.
I2C Bus Start Condition ....................................................................................................................... 1439
8.2.2.
I2C Bus Stop Condition ....................................................................................................................... 1440
8.2.3.
I2C Bus Repeated Start Condition ....................................................................................................... 1440
8.2.4.
I2C Bus Error ....................................................................................................................................... 1440
8.2.5.
Serial Timer Operations ....................................................................................................................... 1441
8.2.6.
Baud Rate Generation.......................................................................................................................... 1442
8.3. I2C Master Mode .......................................................................................................................................... 1444
8.3.1.
Start Condition Generation .................................................................................................................. 1444
8.3.2.
Slave Address Output .......................................................................................................................... 1446
8.3.3.
Acknowledge Reception by Transmitting First Byte ........................................................................... 1449
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8.3.4.
Data Transmission by Master .............................................................................................................. 1457
8.3.5.
Data Reception by Master ................................................................................................................... 1475
8.3.6.
Arbitration Lost ................................................................................................................................... 1483
8.3.7.
Wait of the Master Mode ..................................................................................................................... 1483
8.3.8.
Repetition Start Condition Issue when DMA Mode Enabled (SSR:DMA=1) ..................................... 1484
8.4. I2C Slave Mode ............................................................................................................................................ 1484
8.4.1.
Detection of Slave Address Matching ................................................................................................. 1485
8.4.2.
Data Direction Bit ............................................................................................................................... 1486
8.4.3.
Slave Mode Reception ......................................................................................................................... 1487
8.4.4.
Slave Mode Transmission.................................................................................................................... 1494
8.5. Example of I2C Flowchart............................................................................................................................ 1495
Chapter 42: CAN ........................................................................................................................................................... 1502
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1503
Features ................................................................................................................................................................ 1503
Configuration ....................................................................................................................................................... 1504
Registers ............................................................................................................................................................... 1505
4.1. Overview...................................................................................................................................................... 1505
4.1.1.
List of Base-addresses (Base-addr), External Pins and Buffer Size .................................................... 1506
4.1.2.
List of Overall Control Register .......................................................................................................... 1506
4.1.3.
List of Message Interface Register ...................................................................................................... 1508
4.1.4.
List of Message Handler Register ....................................................................................................... 1511
4.2. Overall Control Registers............................................................................................................................. 1513
4.2.1.
CAN Control Register : CTRLR ......................................................................................................... 1514
4.2.2.
CAN Status Register : STATR ............................................................................................................. 1517
4.2.3.
CAN Error Counter : ERRCNT........................................................................................................... 1520
4.2.4.
CAN Bit Timing Register : BTR ......................................................................................................... 1521
4.2.5.
CAN Interrupt Register : INTR ........................................................................................................... 1522
4.2.6.
CAN Test Register : TESTR................................................................................................................ 1523
4.2.7.
CAN Prescaler Extension Register : BRPER ...................................................................................... 1525
4.3. Message Interface Register .......................................................................................................................... 1526
4.3.1.
IFx Command Request Register : IFxCREQ ....................................................................................... 1527
4.3.2.
IFx Command Mask Register (IFxCMSK) ......................................................................................... 1529
4.3.3.
IFx Mask Registers 1, 2 : IFxMSK1, IFxMSK2.................................................................................. 1533
4.3.4.
IFx Arbitration Registers 1, 2 : IFxARB1, IFxARB2 .......................................................................... 1534
4.3.5.
IFx Message Control Register : IFxMCTR ......................................................................................... 1535
4.3.6.
IFx Data Registers A1, A2, B1, B2 : IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2 ............................... 1536
4.4. Message Object ............................................................................................................................................ 1537
4.4.1.
Configuration of Message Object ........................................................................................................ 1537
4.4.2.
Functions of Message Object .............................................................................................................. 1537
4.5. Message Handler Registers .......................................................................................................................... 1543
4.5.1.
CAN Transmission Request Registers : TREQR1 to TREQR4 ........................................................... 1543
4.5.2.
CAN Data Update Registers : NEWDT1 to NEWDT4 ....................................................................... 1546
4.5.3.
CAN Interrupt Pending Registers : INTPND1 to INTPND4............................................................... 1549
4.5.4.
CAN Message Valid Registers : MSGVAL1 to MSGVAL4 ................................................................ 1552
5. Operation .............................................................................................................................................................. 1554
5.1. Message Object ............................................................................................................................................ 1555
5.1.1.
Message Object ................................................................................................................................... 1555
5.1.2.
Data Transmission/Reception with Message RAM ............................................................................. 1555
5.2. Message Transmission Operation ................................................................................................................ 1556
5.2.1.
Message Transmission ......................................................................................................................... 1557
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5.2.2.
Transmission Priority .......................................................................................................................... 1557
5.2.3.
Transmission Message Object Setting ................................................................................................. 1558
5.2.4.
Update of Transmission Message Object ............................................................................................ 1558
5.3. Message Reception Operation ..................................................................................................................... 1559
5.3.1.
Reception Message Acceptance Filter ................................................................................................. 1559
5.3.2.
Reception Priority................................................................................................................................ 1559
5.3.3.
Data Frame Reception ......................................................................................................................... 1560
5.3.4.
Remote Frame ..................................................................................................................................... 1560
5.3.5.
Reception Message Object Setting ...................................................................................................... 1560
5.3.6.
Reception Message Processing ............................................................................................................ 1561
5.4. FIFO Buffer Function .................................................................................................................................. 1562
5.4.1.
Configuration of FIFO Buffer ............................................................................................................. 1562
5.4.2.
Message Reception by FIFO Buffer .................................................................................................... 1562
5.4.3.
Reading from FIFO Buffer .................................................................................................................. 1563
5.5. Interrupt Function ........................................................................................................................................ 1565
5.6. Bit Timing and CAN System Clock (fsys) Generation ................................................................................ 1566
5.7. Test Mode .................................................................................................................................................... 1568
5.7.1.
Test Mode Setting ................................................................................................................................ 1568
5.7.2.
Silent Mode ......................................................................................................................................... 1569
5.7.3.
Loopback Mode ................................................................................................................................... 1569
5.7.4.
Combination of Silent and Loopback Modes ...................................................................................... 1570
5.7.5.
Basic Mode .......................................................................................................................................... 1571
5.7.6.
Software Control of the CAN_TX Pin ................................................................................................ 1572
5.8. Software Initialization .................................................................................................................................. 1573
5.9. CAN Wake Up Function .............................................................................................................................. 1574
6. Restrictions ........................................................................................................................................................... 1575
6.1. INIT bit ........................................................................................................................................................ 1575
6.1.1.
Restrictions .......................................................................................................................................... 1576
6.1.2.
Bypass method .................................................................................................................................... 1577
Chapter 43: CAN Clock Prescaler ............................................................................................................................... 1578
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1579
Features ................................................................................................................................................................ 1579
Configuration ....................................................................................................................................................... 1579
Registers ............................................................................................................................................................... 1580
4.1. CAN Prescaler Register : CANPRE ............................................................................................................ 1580
Chapter 44: FlexRay...................................................................................................................................................... 1582
1.
2.
3.
36
Overview .............................................................................................................................................................. 1583
Features ................................................................................................................................................................ 1583
Configuration ....................................................................................................................................................... 1584
3.1. Functional Description of Each Block ......................................................................................................... 1584
3.1.1. CPU Interface (CIF)................................................................................................................................... 1584
3.1.2. Input Buffer (IBF) ...................................................................................................................................... 1584
3.1.3. Output Buffer (OBF) ................................................................................................................................. 1584
3.1.4. Message Handler (MHD) ........................................................................................................................... 1585
3.1.5. Message RAM (MRAM) ........................................................................................................................... 1585
3.1.6. Transient Buffer RAM (TBF A/B) ............................................................................................................. 1585
3.1.7. FlexRay Channel Protocol Controller (PRT A/B) ...................................................................................... 1585
3.1.8. Global Time Unit (GTU) ........................................................................................................................... 1585
3.1.9. System Universal Control (SUC) ............................................................................................................... 1586
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3.1.10. Frame and Symbol Processing (FSP) ...................................................................................................... 1586
3.1.11. Network Management (NEM) ................................................................................................................. 1586
3.1.12. Interrupt Control (INT) ............................................................................................................................ 1586
3.2. Configuration of FlexRay ............................................................................................................................ 1586
4. Registers ............................................................................................................................................................... 1588
4.1. Customer Registers ...................................................................................................................................... 1592
4.1.1. Version Information Register: CIF0 ........................................................................................................... 1593
4.1.2. Control Register: CIF1............................................................................................................................... 1594
4.2. Special Register ........................................................................................................................................... 1599
4.2.1. Lock Register: LCK ................................................................................................................................... 1599
4.3. Interrupt-related Registers............................................................................................................................ 1601
4.3.1. Error Interrupt Register: EIR ..................................................................................................................... 1601
4.3.2. Status Interrupt Register: SIR .................................................................................................................... 1604
4.3.3. Error Interrupt Pin Selection Register: EILS (Error Interrupt Line Select) ............................................... 1608
4.3.4. Status Interrupt Pin Selection Register: SILS (Status Interrupt Line Select) ............................................. 1610
4.3.5. Error Interrupt Enable Register: EIES, EIER (Error Interrupt Enable Set/Reset)...................................... 1612
4.3.6. Status Interrupt Enable Register: SIES, SIER (Status Interrupt Enable Set/Reset) ................................... 1614
4.3.7. Interrupt Pin Enable Register: ILE (Interrupt Line Enable) ....................................................................... 1616
4.3.8. Timer 0 Configuration: T0C ...................................................................................................................... 1617
4.3.9. Timer 1 Configuration Register: T1C (Timer 1 Configuration) ................................................................. 1618
4.3.10. Stop Watch Register 1: STPW1 ............................................................................................................... 1620
4.3.11. Stop Watch Register 2: STPW2 ............................................................................................................... 1622
4.4. Communication Controller (CC) Control Registers ..................................................................................... 1623
4.4.1. SUC Configuration Register 1: SUCC1..................................................................................................... 1623
4.4.2. SUC Configuration Register 2: SUCC2..................................................................................................... 1629
4.4.3. SUC Configuration Register 3: SUCC3..................................................................................................... 1630
4.4.4. NEM Configuration Register: NEMC ....................................................................................................... 1631
4.4.5. PRT Configuration Register 1: PRTC1 ...................................................................................................... 1632
4.4.6. PRT Configuration Register 2: PRTC2 ...................................................................................................... 1634
4.4.7. MHD Configuration Register: MHDC ...................................................................................................... 1635
4.4.8. GTU Configuration Register 1: GTUC1 .................................................................................................... 1636
4.4.9. GTU Configuration Register 2: GTUC2 .................................................................................................... 1637
4.4.10. GTU Configuration Register 3: GTUC3 .................................................................................................. 1638
4.4.11. GTU Configuration Register 4: GTUC4 .................................................................................................. 1640
4.4.12. GTU Configuration Register 5: GTUC5 .................................................................................................. 1641
4.4.13. GTU Configuration Register 6: GTUC6 .................................................................................................. 1642
4.4.14. GTU Configuration Register 7: GTUC7 .................................................................................................. 1643
4.4.15. GTU Configuration Register 8: GTUC8 .................................................................................................. 1644
4.4.16. GTU Configuration Register 9: GTUC9 .................................................................................................. 1645
4.4.17. GTU Configuration Register 10: GTUC10 .............................................................................................. 1646
4.4.18. GTU Configuration Register 11: GTUC11 .............................................................................................. 1647
4.5. Communication Controller (CC) Status Registers ....................................................................................... 1649
4.5.1. CC Status Vector Register: CCSV (CC Status Vector) .............................................................................. 1649
4.5.2. CC Error Vector Register: CCEV (CC Error Vector) ................................................................................. 1652
4.5.3. Slot Counter Value Register: SCV (Slot Counter Value) ........................................................................... 1654
4.5.4. Macrotick and Cycle Counter Value Register: MTCCV (Macrotick and Cycle Counter Value) ............... 1655
4.5.5. Rate Correction Value Register: RCV (Rate Correction Value) ................................................................. 1656
4.5.6. Offset Correction Value Register: OCV (Offset Correction Value) ........................................................... 1657
4.5.7. Sync Frame Status Register: SFS (Sync Frame Status) ............................................................................. 1658
4.5.8. Symbol Window and NIT Status Register: SWNIT (Symbol Window and NIT Status) ........................... 1660
4.5.9. Aggregated Channel Status Register: ACS (Aggregated Channel Status) ................................................. 1662
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4.5.10. Even Cycle Sync Frame ID Register: ESIDn (Even Sync ID [1...15]) .................................................... 1665
4.5.11. Odd Cycle Sync Frame ID Register: OSIDn (Odd Sync ID [1...15]) ...................................................... 1666
4.5.12. Network Management Register[1...3]: NMVn (Network Management Vector [1...3]) ........................... 1668
4.6. Message Buffer Control Registers ............................................................................................................... 1669
4.6.1. Message RAM Configuration Register: MRC (Message RAM Configuration) ........................................ 1669
4.6.2. FIFO Rejection Filter Register: FRF (FIFO Rejection Filter) ................................................................... 1672
4.6.3. FIFO Rejection Filter Mask Register: FRFM (FIFO Rejection Filter Mask) ............................................ 1674
4.6.4. FIFO Critical Level Register: FCL (FIFO Critical Level) ......................................................................... 1675
4.7. Message Buffer Status Registers .................................................................................................................. 1676
4.7.1. Message Handler Status Register: MHDS (Message Handler Status) ....................................................... 1676
4.7.2. Last Dynamic Transmission Slot Register: LDTS (Last Dynamic Transmit Slot) .................................... 1678
4.7.3. FIFO Status Register: FSR ........................................................................................................................ 1679
4.7.4. Message Handler Constraints Flags: MHDF ............................................................................................. 1681
4.7.5. Transmission Request Register 1/2/3/4: TXRQ1/2/3/4 (Transmission Request 1/2/3/4) ........................... 1683
4.7.6. New Data Register 1/2/3/4: NDAT1/2/3/4 (New Data 1/2/3/4) ................................................................. 1687
4.7.7. Message Buffer Status Changed Register 1/2/3/4: MBSC (Message Buffer Status Changed 1/2/3/4) ...... 1691
4.8. Identification Registers ................................................................................................................................ 1695
4.8.1. Core Release Register: CREL .................................................................................................................... 1695
4.8.2. Endian Register: ENDN ............................................................................................................................. 1696
4.9. Input Buffer .................................................................................................................................................. 1697
4.9.1. Write Data Section Register: WRDSn [1...64] (Write Data Section [1...64]) ............................................ 1697
4.9.2. Write Header Section Register 1: WRHS1 (Write Header Section 1) ....................................................... 1699
4.9.3. Write Header Section Register 2: WRHS2 (Write Header Section 2) ....................................................... 1701
4.9.4. Write Header Section Register 3: WRHS3 (Write Header Section 3) ....................................................... 1702
4.9.5. Input Buffer Command Mask Register: IBCM (Input Buffer Command Mask) ....................................... 1703
4.9.6. Input Buffer Command Request Register: IBCR (Input Buffer Command Request) ................................ 1704
4.10. Output Buffer ............................................................................................................................................... 1706
4.10.1. Read Data Section Register: RDDSn (Read Data Section [to164]) ......................................................... 1706
4.10.2. Read Header Section Register 1: RDHS1 (Read Header Section 1) ........................................................ 1708
4.10.3. Read Header Section Register 2: RDHS2 (Read Header Section 2) ........................................................ 1709
4.10.4. Read Header Section Register 3: RDHS3 (Read Header Section 3) ........................................................ 1711
4.10.5. Message Buffer Status Register: MBS (Message Buffer Status) ............................................................. 1713
4.10.6. Output Buffer Command Mask Register: OBCM (Output Buffer Command Mask) .............................. 1717
4.10.7. Output Buffer Command Request Register: OBCR (Output Buffer Command Request) ....................... 1718
5. Operation .............................................................................................................................................................. 1720
5.1. Communication Cycle ................................................................................................................................. 1720
5.1.1. Static Segment ........................................................................................................................................... 1721
5.1.2. Dynamic Segment ...................................................................................................................................... 1721
5.1.3. Symbol Window ........................................................................................................................................ 1721
5.1.4. Network Idle Time (NIT) ........................................................................................................................... 1722
5.1.5. NIT Start and Offset Correction Start Settings .......................................................................................... 1722
5.2. Communication Modes ................................................................................................................................ 1723
5.2.1. Time-triggered Distributed Mode: TT-D (Time-triggered Distributed) ..................................................... 1723
5.3. Clock Synchronization ................................................................................................................................. 1723
5.3.1. Global Time ............................................................................................................................................... 1723
5.3.2. Local Time ................................................................................................................................................. 1724
5.3.3. Synchronization Process ............................................................................................................................ 1724
5.3.4. External Clock Synchronization ................................................................................................................ 1725
5.4. Error Handling ............................................................................................................................................. 1725
5.4.1. Clock Correction Failure Counter .............................................................................................................. 1726
5.4.2. Counter for Cycle Pair Number Required for State Transition from Passive to Active ............................. 1727
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5.4.3. HALT Command ....................................................................................................................................... 1727
5.4.4. FREEZE Command ................................................................................................................................... 1727
5.5. Communication Controller States ................................................................................................................ 1728
5.5.1. Communication Controller State Diagram ................................................................................................ 1728
5.5.2. DEFAULT_CONFIG State ........................................................................................................................ 1730
5.5.3. CONFIG State ........................................................................................................................................... 1730
5.5.4. MONITOR_MODE ................................................................................................................................... 1731
5.5.5. READY State ............................................................................................................................................. 1731
5.5.6. WAKEUP State .......................................................................................................................................... 1732
5.5.7. STARTUP State ......................................................................................................................................... 1736
5.5.8. NORMAL_ACTIVE State ........................................................................................................................ 1740
5.5.9. NORMAL_PASSIVE State ....................................................................................................................... 1741
5.5.10. HALT State .............................................................................................................................................. 1741
5.6. Network Management .................................................................................................................................. 1742
5.7. Filtering and Masking .................................................................................................................................. 1742
5.7.1. Slot Counter Filtering ................................................................................................................................ 1743
5.7.2. Cycle Counter Filtering ............................................................................................................................. 1743
5.7.3. Channel ID Filtering .................................................................................................................................. 1744
5.7.4. FIFO Filtering ............................................................................................................................................ 1744
5.8. Transmission Procedure ............................................................................................................................... 1745
5.8.1. Static Segment ........................................................................................................................................... 1745
5.8.2. Dynamic Segment ...................................................................................................................................... 1745
5.8.3. Transmission Buffer ................................................................................................................................... 1745
5.8.4. Frame Transmission ................................................................................................................................... 1746
5.8.5. Null Frame Transmission ........................................................................................................................... 1747
5.9. Reception Procedure .................................................................................................................................... 1747
5.9.1. Reception Buffer ........................................................................................................................................ 1747
5.9.2. Frame Reception ........................................................................................................................................ 1747
5.9.3. Null Frame Reception ................................................................................................................................ 1748
5.10. FIFO Function.............................................................................................................................................. 1748
5.10.1. Details ...................................................................................................................................................... 1748
5.10.2. FIFO Settings ........................................................................................................................................... 1749
5.10.3. Access to FIFO ........................................................................................................................................ 1750
5.11. Message Handling ........................................................................................................................................ 1750
5.11.1. Message Buffer Reconfiguration ............................................................................................................. 1750
5.11.2. Host Access to Message RAM ................................................................................................................. 1751
5.11.3. FlexRay Protocol Controller Access to Message RAM ........................................................................... 1757
5.12. Message RAM ............................................................................................................................................. 1758
5.12.1. Header Partition ....................................................................................................................................... 1759
5.12.2. Data Partition ........................................................................................................................................... 1762
5.12.3. Parity Check............................................................................................................................................. 1763
5.12.4. Parity Error Handling............................................................................................................................... 1765
5.13. Interrupts ...................................................................................................................................................... 1766
Chapter 45: D/A Converter ........................................................................................................................................... 1768
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1769
Features ................................................................................................................................................................ 1769
Configuration ....................................................................................................................................................... 1769
Registers ............................................................................................................................................................... 1770
4.1. D/A Control Register : DACR ..................................................................................................................... 1770
4.2. D/A Data Register : DADR .......................................................................................................................... 1771
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5.
6.
Operation .............................................................................................................................................................. 1772
Note ...................................................................................................................................................................... 1772
Chapter 46: 12-Bit A/D Converter ............................................................................................................................... 1773
1.
2.
Overview .............................................................................................................................................................. 1774
Features ................................................................................................................................................................ 1774
2.1. Function of A/D Activation Compare .......................................................................................................... 1774
2.2. Function of A/D Activation Arbitration ....................................................................................................... 1776
2.3. Functions of 12-bit A/D Converter Control ................................................................................................. 1777
3. Configuration ....................................................................................................................................................... 1778
4. Registers ............................................................................................................................................................... 1780
4.1. Register of Analog Input Control ................................................................................................................. 1791
4.1.1.
Analog Input Enable Register : ADER ................................................................................................ 1791
4.2. Register of A/D Activation Compare ........................................................................................................... 1793
4.2.1.
A/D Software Activation Register: ADTSS0, ADTSS1 ...................................................................... 1794
4.2.2.
A/D Software Activation Channel Select Register : ADTSE0, ADTSE1 ............................................ 1794
4.2.3.
Compare Buffer Register / Compare Register : ADCOMPB0 to ADCOMPB63 / ADCOMP0 to
ADCOMP63 ........................................................................................................................................ 1797
4.2.4.
A/D Activation Trigger Control Status Register : ADTCS0 to ADTCS63 .......................................... 1798
4.2.5.
A/D Data Register : ADTCD0 to ADTCD63 ...................................................................................... 1803
4.2.6.
A/D Activation Trigger Extend Control Register : ADTECS0 to ADTECS63 .................................... 1804
4.2.7.
Upper Bound Threshold Setting Register : ADRCUT0 to ADRCUT7................................................ 1807
4.2.8.
Lower Bound Threshold Setting Register : ADRCLT0 to ADRCLT7 ................................................. 1809
4.2.9.
Range Compare Control Status Register: ADRCCS0 to ADRCCS63 ................................................. 1810
4.2.10. Range Compare Threshold Over Flag Register : ADRCOT0, ADRCOT1 .......................................... 1813
4.2.11. Range Compare Flag Register : ADRCIF0, ADRCIF1 ....................................................................... 1815
4.2.12. Scan Conversion Control Status Register : ADSCANS0, ADSCANS1 .............................................. 1817
4.2.13. Activation Channel Conversion Count Setting Register : ADNCS0 to ADNCS31 ............................. 1819
4.2.14. Data Protection Status Flag Register : ADPRTF0, ADPRTF1 ............................................................ 1820
4.2.15. Activation Channel Conversion Completion Flag Register : ADEOCF0, ADEOCF1 ........................ 1822
4.3. Register of 12-BIT A/D Converter Control.................................................................................................. 1824
4.3.1.
A/D Control Status Register: ADCS0, ADCS1 ................................................................................... 1824
4.3.2.
A/D Channel Status Register : ADCH ................................................................................................. 1825
4.3.3.
A/D Mode Setting Register : ADMD .................................................................................................. 1827
4.3.4.
A/D Sampling Time Setting Per Channel Register : ADSTPCS ......................................................... 1829
5. Operation .............................................................................................................................................................. 1831
5.1. Interrupt of A/D activation compare ............................................................................................................ 1831
5.1.1.
A/D conversion completion interrupt .................................................................................................. 1832
5.1.2.
Scan conversion completion interrupt by conversion count specification ........................................... 1832
5.1.3.
Range comparison interrupt................................................................................................................. 1833
5.2. A/D activation compare operation ............................................................................................................... 1834
5.2.1.
A/D activation ..................................................................................................................................... 1834
5.2.2.
A/D activation enable .......................................................................................................................... 1834
5.2.3.
Free-run timer input ............................................................................................................................. 1835
5.2.4.
Analog channel select .......................................................................................................................... 1835
5.2.5.
Software activation .............................................................................................................................. 1835
5.2.6.
External trigger activation ................................................................................................................... 1835
5.2.7.
Reload timer activation........................................................................................................................ 1836
5.2.8.
Compare match activation ................................................................................................................... 1836
5.2.9.
PPG activation ..................................................................................................................................... 1843
5.2.10. Activation request mode ...................................................................................................................... 1843
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5.2.11. A/D conversion data ............................................................................................................................ 1844
5.2.12. Protection function .............................................................................................................................. 1844
5.2.13. Scan conversion mode ......................................................................................................................... 1845
5.2.14. High priority activation request operation of other activation channel during the scan conversion .... 1851
5.2.15. Forced termination of activation request ............................................................................................. 1853
5.2.16. Range comparison function ................................................................................................................. 1853
5.3. A/D Activation Arbitration Operation .......................................................................................................... 1858
5.3.1.
A/D Activation Trigger Arbitration ..................................................................................................... 1858
5.3.2.
Analog Channel Select ........................................................................................................................ 1859
5.3.3.
A/D Conversion Cancel Function........................................................................................................ 1859
5.4. 12-bit A/D Converter Operation .................................................................................................................. 1860
5.4.1.
Operation Timing ................................................................................................................................ 1860
5.4.2.
Activation Factors ............................................................................................................................... 1861
5.4.3.
A/D Conversion ................................................................................................................................... 1861
5.4.4.
Re-activation ....................................................................................................................................... 1861
5.4.5.
A/D Conversion Cancel ....................................................................................................................... 1861
5.4.6.
Analog Channel Select Control ........................................................................................................... 1862
5.4.7.
A/D Conversion Time.......................................................................................................................... 1862
5.4.8.
A/D Conversion Completion and A/D Data Retrieval ......................................................................... 1863
5.4.9.
Power down ......................................................................................................................................... 1863
6. Notes .................................................................................................................................................................... 1864
Chapter 47: Flash Memory ........................................................................................................................................... 1866
1.
2.
3.
Overview .............................................................................................................................................................. 1867
Features ................................................................................................................................................................ 1867
Configuration ....................................................................................................................................................... 1868
3.1. Block Diagram ............................................................................................................................................. 1869
3.2. Sector Configuration Diagram ..................................................................................................................... 1870
3.3. Sector Number and Flash Macro Number Correspondence Chart ............................................................... 1872
4. Registers ............................................................................................................................................................... 1876
4.1. Flash Control Register : FCTLR (Flash ConTroL Register) ........................................................................ 1876
4.2. Flash Status Register : FSTR (Flash STatus Register) ................................................................................. 1879
4.3. Flash Interface Control Register : FLIFCTLR(Flash I/F ConTrol Register) ............................................... 1880
4.4. FLash I/F Feature Extension Register 1: FLIFFER1 ................................................................................... 1881
4.5. FLash I/F Feature Extension Register 2: FLIFFER2 ................................................................................... 1882
5. Operation .............................................................................................................................................................. 1882
5.1. Access Mode Setting.................................................................................................................................... 1883
5.1.1.
Configuring CPU-ROM Mode ............................................................................................................ 1883
5.1.2.
Configuring CPU Programming Mode ................................................................................................ 1883
5.2. Writing to Flash Memory by CPU ............................................................................................................... 1883
5.3. Automatic Algorithm ................................................................................................................................... 1884
5.3.1.
Command Sequence ............................................................................................................................ 1884
5.3.2.
Automatic Algorithm Execution State ................................................................................................. 1887
5.4. Reset Command ........................................................................................................................................... 1891
5.5. Write Command ........................................................................................................................................... 1891
5.6. Chip Erase Command .................................................................................................................................. 1893
5.7. Sector Erase Command ................................................................................................................................ 1894
5.8. Sector Erase Suspend Command ................................................................................................................. 1896
5.9. Security Function ......................................................................................................................................... 1897
5.9.1.
Flash Security On/Off Determination When Reset Released .............................................................. 1897
5.9.2.
Flash Security Setting Method ............................................................................................................ 1897
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5.9.3.
Unlocking Flash Security .................................................................................................................... 1897
5.9.4.
Flash Access Restrictions When Security is ON ................................................................................. 1898
5.10. Notes on Using Flash Memory .................................................................................................................... 1899
Chapter 48: WorkFlash Memory ................................................................................................................................. 1900
1.
2.
3.
Overview .............................................................................................................................................................. 1901
Features ................................................................................................................................................................ 1901
Configuration ....................................................................................................................................................... 1902
3.1. Block Diagram ............................................................................................................................................. 1902
3.2. Sector Configuration Diagram ..................................................................................................................... 1903
4. Registers ............................................................................................................................................................... 1903
4.1. WorkFlash Control Register : DFCTLR (WorkFlash ConTroL Register) .................................................... 1904
4.2. WorkFlash Status Register : DFSTR (WorkFlash STatus Register) ............................................................. 1905
4.3. Flash Interface Control Register : FLIFCTLR (Flash I/F ConTroL Register) ............................................. 1906
5. Operation .............................................................................................................................................................. 1907
5.1. Access Mode Setting.................................................................................................................................... 1908
5.1.1.
Configuring CPU-ROM Mode below ................................................................................................. 1908
5.1.2.
Configuring CPU Programming Mode ................................................................................................ 1908
5.2. Writing Flash Memory by CPU ................................................................................................................... 1908
5.3. Automatic Algorithm ................................................................................................................................... 1909
5.3.1.
Command Sequence ............................................................................................................................ 1909
5.3.2.
Automatic Algorithm Execution State ................................................................................................. 1912
5.4. Reset Command ........................................................................................................................................... 1916
5.5. Write Command ........................................................................................................................................... 1916
5.6. Chip Erase Command .................................................................................................................................. 1918
5.7. Sector Erase Command ................................................................................................................................ 1919
5.8. Sector Erase Suspend Command ................................................................................................................. 1921
5.9. Security Function ......................................................................................................................................... 1922
5.9.1.
Flash Security On/Off Determination When Reset Released .............................................................. 1922
5.9.2.
Flash Security Setting Method ............................................................................................................ 1922
5.9.3.
Unlocking Flash Security .................................................................................................................... 1922
5.9.4.
Flash Access Restrictions When Security is ON ................................................................................. 1923
5.10. Notes on Using Work Flash Memory ........................................................................................................... 1923
Chapter 49: On-Chip Debugger : OCD ....................................................................................................................... 1924
1.
2.
3.
Overview .............................................................................................................................................................. 1925
Features ................................................................................................................................................................ 1925
Configuration ....................................................................................................................................................... 1927
3.1. DEBUG I/F Clock........................................................................................................................................ 1928
3.1.1.
DEBUG I/F Main Clock : M_MCLK .................................................................................................. 1928
3.1.2.
DEBUG I/F PLL Clock : M_PCLK .................................................................................................... 1929
4. Registers ............................................................................................................................................................... 1929
4.1. DBG Register ............................................................................................................................................... 1929
4.1.1.
DSU Control Register : DSUCR ......................................................................................................... 1930
4.2. User IO Register .......................................................................................................................................... 1930
4.2.1.
User Event Register : UER .................................................................................................................. 1931
4.2.2.
High-Speed Communication Frequency Register : HSCFR ................................................................ 1931
4.2.3.
Message BuffeR : MBR ...................................................................................................................... 1932
5. Operation .............................................................................................................................................................. 1933
5.1. OCDU Operating Mode ............................................................................................................................... 1933
5.1.1.
Operating Mode ................................................................................................................................... 1934
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Table of Contents
5.1.2.
Operating Mode Status Transition ....................................................................................................... 1934
5.2. Overview of DEBUG I/F ............................................................................................................................. 1935
5.2.1.
Chip Reset Sequence ........................................................................................................................... 1936
5.2.2.
Security Function ................................................................................................................................ 1938
5.3. Specification Restrictions at Connection to OCD Tool of This Series ......................................................... 1938
5.3.1.
Clock Setting ....................................................................................................................................... 1939
5.3.2.
Standby Mode...................................................................................................................................... 1939
5.3.3.
Clock Reset State Transitions .............................................................................................................. 1939
5.3.4.
Summary of Specification Restrictions ............................................................................................... 1941
5.4. OCD-DSU ID Code and Mount Type Information on This Series .............................................................. 1946
Chapter 50: Tuning RAM ............................................................................................................................................. 1948
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1949
Features ................................................................................................................................................................ 1949
Configuration ....................................................................................................................................................... 1950
Registers ............................................................................................................................................................... 1951
4.1. Tuning RAM Control Register: TRCR ........................................................................................................ 1951
4.2. Tuning RAM Allocation Area Selection Resister: TRAR ............................................................................ 1952
5. Operation .............................................................................................................................................................. 1953
5.1. Access to Tuning RAM ................................................................................................................................ 1954
5.2. Specification Restrictions when Using Tuning RAM .................................................................................. 1955
Chapter 51: Waveform Generator ............................................................................................................................... 1956
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1957
Features ................................................................................................................................................................ 1957
Configuration ....................................................................................................................................................... 1957
Registers ............................................................................................................................................................... 1959
4.1. Registers for the Waveform Generator ......................................................................................................... 1959
4.1.1.
16-bit dead TIMeR Register (TMRR) ................................................................................................. 1960
4.1.2.
16-bit Dead Timer State Control Register (DTSCR) ........................................................................... 1961
4.1.3.
16-bit Dead Timer reload Interrupt Register (DTIR) ........................................................................... 1968
4.1.4.
16-bit Dead Timer Minus Control Register (DTMNS)........................................................................ 1970
4.1.5.
Waveform Control Register 1/2 (SIGCR1, SIGCR2) .......................................................................... 1972
4.1.6.
PPG Output Control Register (PICS) .................................................................................................. 1975
5. Operation .............................................................................................................................................................. 1976
5.1. Interrupts for Waveform Generator .............................................................................................................. 1976
5.2. Operation of the Waveform Generator ......................................................................................................... 1978
6. Notes .................................................................................................................................................................... 1996
Chapter 52: Bus Diagnosis Function ............................................................................................................................ 1998
1.
2.
3.
4.
Overview .............................................................................................................................................................. 1999
Features ................................................................................................................................................................ 1999
Configuration ....................................................................................................................................................... 2000
Registers ............................................................................................................................................................... 2003
4.1. BUS DIaGnosis Status Register : BUSDIGSR ............................................................................................ 2003
4.2. BUS diagnosis TeST Register : BUSTSTR0/1 ............................................................................................ 2005
4.3. BUS diagnosis ADdRess Register : BUSADR ............................................................................................ 2010
5. Operation .............................................................................................................................................................. 2012
5.1. Error Detection ............................................................................................................................................ 2012
5.2. Test Function ................................................................................................................................................ 2014
5.3. Notes ............................................................................................................................................................ 2015
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Table of Contents
5.4.
Example of Operating Bus Diagnosis .......................................................................................................... 2015
Chapter 53: RAM Diagnosis Function ......................................................................................................................... 2022
1.
2.
3.
4.
Overview .............................................................................................................................................................. 2023
Features ................................................................................................................................................................ 2023
Configuration ....................................................................................................................................................... 2024
Registers ............................................................................................................................................................... 2026
4.1. TEST Error Address Register 0 XBS RAM : TEAR0X ............................................................................... 2027
4.2. TEST Error Address Register 1 XBS RAM : TEAR1X ............................................................................... 2028
4.3. TEST Error Address Register 2 XBS RAM : TEAR2X ............................................................................... 2030
4.4. TEST Start Address Register XBS RAM : TASARX .................................................................................. 2031
4.5. TEST End Address Register XBS RAM : TAEARX ................................................................................... 2032
4.6. TEST Diagnosis Function Register XBS RAM : TTCRX ........................................................................... 2033
4.7. TEST Initialization Function Register XBS RAM : TICRX ........................................................................ 2035
4.8. TEST Software Reset Generation Control Register XBS RAM : TSRCRX ................................................ 2037
4.9. TEST Fake Error Generation Control Register XBS RAM : TFECRX ....................................................... 2037
4.10. TEST Key Code Control Register XBS RAM : TKCCRX .......................................................................... 2038
4.11. TEST Error Address Register 0 BACKUP-RAM : TEAR0A ...................................................................... 2039
4.12. TEST Error Address Register 1 BACKUP-RAM : TEAR1A ...................................................................... 2040
4.13. TEST Error Address Register 2 BACKUP-RAM : TEAR2A ...................................................................... 2042
4.14. TEST Start Address Register BACKUP-RAM : TASARA ......................................................................... 2043
4.15. TEST End Address Register BACKUP-RAM : TAEARA .......................................................................... 2044
4.16. TEST Diagnosis Function Register BACKUP-RAM : TTCRA .................................................................. 2045
4.17. TEST Initialization Function Register BACKUP-RAM : TICRA ............................................................... 2047
4.18. TEST Software Reset Generation Control Register BACKUP-RAM : TSRCRA ....................................... 2049
4.19. TEST Fake Error Generation Control Register BACKUP-RAM : TFECRA .............................................. 2049
4.20. TEST Key Code Control Register BACKUP-RAM : TKCCRA ................................................................. 2050
4.21. TEST Error Address Register 0 AHB RAM : TEAR0H .............................................................................. 2051
4.22. TEST Error Address Register 1 AHB RAM : TEAR1H .............................................................................. 2052
4.23. TEST Error Address Register 2 AHB RAM : TEAR2H .............................................................................. 2054
4.24. TEST Start Address Register AHB RAM : TASARH .................................................................................. 2055
4.25. TEST End Address Register AHB RAM : TAEARH................................................................................... 2056
4.26. TEST Diagnosis Function Register AHB RAM : TTCRH .......................................................................... 2057
4.27. TEST Initialization Function Register AHB RAM : TICRH ....................................................................... 2059
4.28. TEST Software Reset Generation Control Register AHB RAM : TSRCRH ............................................... 2061
4.29. TEST Fake Error Generation Control Register AHB RAM : TFECRH ...................................................... 2061
4.30. TEST Key Code Control Register AHB RAM : TKCCRH ......................................................................... 2062
5. Operation .............................................................................................................................................................. 2063
5.1. RAM Diagnosis ........................................................................................................................................... 2063
5.2. RAM Initialization ....................................................................................................................................... 2064
5.3. Interrupt-Related Register ............................................................................................................................ 2065
5.4. RAM Diagnosis Fake Error Generation Procedure ...................................................................................... 2065
5.5. Number of Required Cycles ......................................................................................................................... 2066
5.6. Note.............................................................................................................................................................. 2068
Chapter 54: Timing Protection Unit ............................................................................................................................ 2069
1.
2.
3.
4.
44
Overview .............................................................................................................................................................. 2070
Features ................................................................................................................................................................ 2070
Configuration ....................................................................................................................................................... 2070
Registers ............................................................................................................................................................... 2071
4.1. TPU Unlock Register : TPUUNLOCK ........................................................................................................ 2072
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Table of Contents
4.2. TPU Lock Status Register : TPULST .......................................................................................................... 2072
4.3. TPU Access Violation Status Register : TPUVST ....................................................................................... 2073
4.4. TPU Configuration Register : TPUCFG ...................................................................................................... 2074
4.5. TPU Timer Interrupt Request Register : TPUTIR........................................................................................ 2076
4.6. TPU Timer Status Register : TPUTST ......................................................................................................... 2076
4.7. TPU Timer Interrupt Enable Register : TPUTIE.......................................................................................... 2077
4.8. TPU Module ID Register : TPUTMID ........................................................................................................ 2078
4.9. TPU Timer Control Register 00 to 07 : TPUTCN00 to 07........................................................................... 2078
4.10. TPU Timer Control Register 10 to 17 : TPUTCN10 to 17........................................................................... 2080
4.11. TPU Timer Current Count Register 0 to 7 : TPUTCC0 to 7 ........................................................................ 2081
5. Operation .............................................................................................................................................................. 2082
5.1. TPU Control Register Access Protection ..................................................................................................... 2082
5.2. Global Prescaler ........................................................................................................................................... 2083
5.3. Interrupt Control .......................................................................................................................................... 2083
5.4. Timer Operation ........................................................................................................................................... 2084
5.5. Free-run Function......................................................................................................................................... 2084
5.6. Individual Prescaler Function ...................................................................................................................... 2085
5.7. Debug Support Function .............................................................................................................................. 2085
5.8. Operation Flow ............................................................................................................................................ 2085
Chapter 55: Clock Monitor........................................................................................................................................... 2087
1.
2.
3.
4.
Overview .............................................................................................................................................................. 2088
Features ................................................................................................................................................................ 2088
Configuration ....................................................................................................................................................... 2088
Registers ............................................................................................................................................................... 2089
4.1. Clock Monitor Configuration Registers : CMCFG ...................................................................................... 2089
5. Operation .............................................................................................................................................................. 2091
6. Setting .................................................................................................................................................................. 2092
7. Q&A ..................................................................................................................................................................... 2092
7.1. How to Configure the Output Pin (MONCLK) ........................................................................................... 2092
7.2. How to Select the Output Frequency ........................................................................................................... 2093
7.3. How to Enable or Disable Clock Monitor Output ........................................................................................ 2093
7.4. How to Set the Clock Output Mark Level ................................................................................................... 2093
8. Notes .................................................................................................................................................................... 2094
Appendix ........................................................................................................................................................................ 2095
A. I/O Map ................................................................................................................................................................ 2096
― ..................................................................................................................................................................................... 2107
B.
C.
D.
E.
List of Interrupt Vector ......................................................................................................................................... 2191
Pins Statuses in State of CPU ............................................................................................................................... 2209
JTAG Boundary Scan Test.................................................................................................................................... 2217
Major Changes ..................................................................................................................................................... 2218
Revision History ............................................................................................................................................................. 2386
Document Revision History ........................................................................................................................................ 2386
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45
Chapter 1: Overview
This chapter explains the overview.
1. Overview
2. Features
3. Product Line-up
4. Function overview
5. Block Diagram
6. Memory Map
7. Pin Assignment
8. Device Package
9. Explanation of Pin Functions
10. I/O Circuit Types
Code : OVER-1v0-91528-3-E
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MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
1. Overview
This section explains overview of MB91520 series.
MB91520 series is Cypress 32-bit microcontroller for application control for automotives. The FR81S CPU that is
compatible with the FR family is used.
2. Features
This section explains features of MB91520 series.
2.1. FR81S CPU Core
2.2. Peripheral Functions
2.1.
FR81S CPU Core
FR81S CPU core is shown.
32-bit RISC, load/store architecture, 5-stage pipeline
Maximum operating frequency:
MB91F52xR/MB91F52xU (LQS144/LQN144/LQP176): 80 MHz (Source oscillation = 4.0 MHz and 20
multiplied (PLL clock multiplication system))
MB91F52xR/MB91F52xU (LES144/LEP176): 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied (PLL
clock multiplication system))
MB91F52xM/ MB91F52xY: 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied
(PLL clock multiplication system))
General-purpose register : 32-bit ×16 sets
16-bit fixed length instructions (basic instruction), 1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instruction
Bit processing instruction
Barrel shift instruction etc.
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Decrease overhead during branch process
Register interlock function
Easy assembler writing
Built-in multiplier and instruction level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
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Chapter 1: Overview
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of program and data access.
Instruction compatibility with the FR family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for instructions and the data.
Control access privilege in both privilege mode and user mode.
Built-in FPU (floating point arithmetic)
IEEE754 compliant
Floating-point register 32-bit × 16 sets
2.2.
Peripheral Functions
Peripheral function is shown.
Clock generation (equipped with SSCG function)
Main oscillation (4MHz to 16MHz)
Sub oscillation (32kHz) or no sub oscillation
PLL multiplication rate : 1 to 20 times for MB91F52xR/MB91F52xU (LQS144/LQN144/LQP176)
: 1 to 32 times for MB91F52xR/MB91F52xU (LES144/LEP176)
: 1 to 32 times for MB91F52xM/MB91F52xY
100 kHz CR oscillator mounted
Maximum operating frequency:
Peripheral bus clock: 40MHz
External bus clock: 40MHz
Built-in Program flash capacity
MB91F527 : 1536KB + 64KB
MB91F528 : 2048KB + 64KB
Built-in Data flash (WorkFlash) 64KB
Built-in RAM capacity
Main RAM
MB91F527 : 192KB
MB91F528 : 192KB + 128KB (128KB located in the AHB area, a penalty given at access)
Backup RAM 16KB
General-purpose ports :
MB91F527R/MB91F528R :
115 (none sub oscillation), 113 (with sub oscillation)
MB91F527U/MB91F528U :
147 (none sub oscillation), 145 (with sub oscillation)
MB91F527M/MB91F528M :
177 (none sub oscillation), 175 (with sub oscillation)
MB91F527Y/MB91F528Y
219 (none sub oscillation), 217 (with sub oscillation)
Included I2C pseudo open drain ports : Max. 30
External bus interface
22-bit address, 8/16-bit data
DMA Controller
Up to 16 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and software)
A/D converter (successive approximation type)
12-bit resolution : Max. 64 channels (32 channels +32 channels)
Conversion time : 1.4μs
D/A converter (R-2R type)
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Chapter 1: Overview
8-bit resolution : 2 channels
External interrupt input: Max. 24 channels
Level ("H" / "L"), or edge detection (rising or falling) supported
Multi-function serial communication (built-in transmission/reception FIFO memory) : Max. 20 channels
5V tolerant input 8 channels (ch.6, ch.8, ch.9, ch.11, ch.16 to ch.19) CMOS hysteresis input
< UART (Asynchronous serial interface) >
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
The external clock can be used as the transfer clock
Parity, frame, and overrun error detect functions provided
DMA transfer support
Full-duplex double buffering system, 64-byte transmission FIFO, memory, 64-byte reception FIFO memory
SPI supported; master and slave systems supported; 5-bit to 16-bit, 20-bit, 24-bit, 32-bit data length can be
set.
Built-in dedicated baud rate generator (Master operation)
The external clock can be entered. (Slave operation)
Overrun error detection function is provided
DMA transfer support
Serial chip select SPI function
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory
LIN protocol revision 2.1 supported
Master and slave systems supported
Framing error and overrun error detection
LIN synch break generation and detection; LIN synch delimiter generation
Built-in dedicated baud rate generator
The external clock can be adjusted by the reload counter
DMA transfer support
Hardware assist function
< I2C >
10 channels (ch.3, ch.4, ch.12 to ch.19) Standard mode / Fast mode supported
5 channels (ch.5 to ch.8, ch.11) Standard mode supported
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory
Standard mode (Max. 100kbps) / Fast mode (Max. 400kbps) supported
DMA transfer supported (for transmission only)
CAN : 6 channels
Transfer speed : Up to 1Mbps
128-transmission/reception message buffering : 6 channels
FlexRay controller: 1 unit (ch.A/ch.B)
FlexRay specification version 2.1 supported
Max. 128-message buffer configuration
8KB message RAM
Variable-length message buffer configuration
Each message buffer can be configured as a part of a reception buffer, transmission buffer, or reception FIFO.
Host access to message buffers through input and output buffers
Filtering the slot counter, cycle counter, and channels
Maskable interrupts
PPG : 16-bit × Max. 88 channels
LED drive output 4 channels (ch.11 to ch.14)
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49
Chapter 1: Overview
Reload timer : 16-bit × 8 channels
Free-run timer :
16-bit × 3 channels
32-bit × Max. 8 channels
Input capture :
16-bit × 4 channels (linked to the free-run timer)
32-bit × Max. 8 channels (linked to the free-run timer)
Output compare :
16-bit × 6 channels (linked to the free-run timer)
32-bit × Max. 8 channels (linked to the free-run timer)
Wave generator : 6 channels
U/D counter:
8/16-bit up/down counter × Max. 4 channels
Real-time clock (RTC) (for day, hours, minutes, seconds)
Main oscillation / sub oscillation frequency can be selected for the operation clock.
Calibration: A real-time clock (RTC) of the sub clock drive.
The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler
Clock Supervisor
Monitoring abnormality (damage of crystal etc.) of sub oscillation (32kHz) (dual clock products) and main
oscillation (4 MHz).
When abnormality is detected, it switches to the CR clock.
For some devices, ON/OFF can be selected as the initial value.
Base timer : 2 channels
16-bit timer
The timer mode is selected from PWM/PPG/PWC/reload.
As for the PWC function and the reload timer function, a pair of 16-bit timers can be used as one 32-bit timer
in the cascaded mode.
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog (An effective range of a clear counter can be set.)
NMI
Interrupt controller
Interrupt request batch read
Multiple interrupts from peripherals can be read by a series of registers.
I/O relocation
Peripheral function pins can be reassigned.
Low-power consumption mode
Sleep / Stop / Watch / Sub RUN mode
Stop (power shutdown) / Watch (power shutdown) mode
Power on reset
Low-voltage detection reset (External power supply and Internal power supply are independently observed.)
For some devices, ON/OFF can be selected as the initial value for external power supply.
Tuning RAM
Capacity: 128 KB
Can be used as RAM for data tuning.
JTAG pins (TRST, TCK, TMS, TDI, TDO)
Device Package : 144/176/208/416
CMOS 90nm Technology
Power supplies
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Chapter 1: Overview
5V or 3V Power supply
The internal 1.2V is generated from 5V with the voltage step-down regulator.
Restriction on the power-on sequence (from VCC to VCCE)
Applying a voltage higher than the power supply voltage to an analog signal input is prohibited.
Operation guaranteed voltage range (recommended): 3.0V to 5.5V (within the range guaranteed by AC and DC
spec)
Operation guaranteed voltage range: 2.7V to 5.5V
3. Product Line-up
This section shows product line-up of MB91520 series.
Table 3-1 Product Line-up (144 pin)
MB91F527R
System Clock
Minimum instruction
execution time
FLASH Capacity
(Program)
MB91F528R
On-chip PLL Clock multiple method
12.5ns (80MHz) (LQS144/LQN144), 8.0ns (128MHz) (LES144)
1536KB + 64KB
2048KB + 64KB
FLASH Capacity (Data)
RAM Capacity
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
External Bus I/F
(22 address/16 data/4cs)
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 3 channels
Input capture
16-bit × 4 channels
32-bit × 6 channels
Output Compare
16-bit × 6 channels
32-bit × 6 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 44 channels *
Up/down Counter
2 channels
Clock Supervisor
Yes
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51
Chapter 1: Overview
MB91F527R
External interrupt
A/D
D/A (8-bit)
Multi-Function Serial
CAN
FlexRay
8 channels × 2 units
12-bit × 32 channels (1 unit)
12-bit × 16 channels (1 unit)
2 channels
12 channels*1
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
Low-voltage detection
reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
52
MB91F528R
115 ports (no sub clock) / 113 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection
Unit)
Yes
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Chapter 1: Overview
MB91F527R
MB91F528R
Key Code Register
Yes
Wave Generator
Tuning RAM
6 channels
None
Yes
JTAG
Yes
Operation guaranteed
temperature (Ta)
Power supply
-40°C to +125°C
2.7 V to 5.5 V*2
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: 1-pin to 39-pin and 128-pin to 144-pin power supply)
(External bus I/F: 3.0 V to 3.6 V)
Package
LQS144 / LQN144 / LES144
*: PPG output pins on ch.38 and ch.39 do not exist. See "Pins of PPG (ch.0 to ch.87)".
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V).
This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum
guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage.
Table 3-2 Product Line-up (176 pin)
MB91F527U
System Clock
Minimum instruction
execution time
FLASH Capacity
(Program)
MB91F528U
On-chip PLL Clock multiple method
12.5ns (80MHz) (LQP176), 8.0ns (128MHz) (LEP176)
1536KB + 64KB
2048KB + 64KB
FLASH Capacity (Data)
RAM Capacity
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
External Bus I/F
(22 address/16 data/4cs)
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 3 channels
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53
Chapter 1: Overview
MB91F527U
Input capture
16-bit × 4 channels
32-bit × 6 channels
Output Compare
16-bit × 6 channels
32-bit × 6 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 48 channels
Up/down Counter
2 channels
Clock Supervisor
Yes
External interrupt
8 channels × 2 units
A/D
D/A (8-bit)
Multi-Function Serial
CAN
FlexRay
12-bit × 32 channels (1 unit)
12-bit × 16 channels (1 unit)
2 channels
12 channels*1
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
Low-voltage detection
reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
54
MB91F528U
147 ports (no sub clock) / 145 ports (with sub clock)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
MB91F527U
MB91F528U
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection Unit)
Yes
Key Code Register
Yes
6 channels
Wave Generator
None
Tuning RAM
Yes
Yes
JTAG
Operation guaranteed
temperature (Ta)
Power supply
-40°C to +125°C
2.7 V to 5.5 V*2
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: 1-pin to 49-pin and 156-pin to 176-pin power supply)
(External bus I/F: 3.0 V to 3.6 V)
LQP176 / LEP176
Package
2
*1: Only channel 3 and channel 4 support the I C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V).
This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum
guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage.
Table 3-3 Product Line-up (208 pin)
MB91F527M
System Clock
On-chip PLL Clock multiple method
Minimum instruction
execution time
FLASH Capacity
(Program)
MB91F528M
8.0ns (128MHz)
1536KB + 64KB
FLASH Capacity (Data)
RAM Capacity
2048KB + 64KB
64KB
192KB + 16KB
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
(192KB + 128KB) + 16KB
55
Chapter 1: Overview
MB91F527M
External Bus I/F
(22 address/16 data/4cs)
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 8 channels
Input capture
16-bit × 4 channels
32-bit × 8 channels
Output Compare
16-bit × 6 channels
32-bit × 8 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 64 channels
Up/down Counter
4 channels
Clock Supervisor
Yes
External interrupt
8 channels × 3 units
A/D
D/A (8-bit)
Multi-Function Serial
CAN
FlexRay
56
MB91F528M
12-bit × 32 channels (2 units)
2 channels
20 channels*1
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
Low-voltage detection
reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
MB91F527M
MB91F528M
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
177 ports (no sub clock) / 175 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection Unit)
Yes
Key Code Register
Yes
6 channels
Wave Generator
Tuning RAM
None
Yes
Yes
JTAG
Operation guaranteed
temperature (Ta)
Power supply
Package
-40°C to +125°C
2.7 V to 5.5 V*2
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: 1-pin to 57-pin and 188-pin to 208-pin power supply)
(External bus I/F: 3.0 V to 3.6 V)
LQR208 / LER208
*1: Only channel 3, channel 4 and channel 12 to channel 19 support the I 2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2C (standard mode)
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V).
This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum
guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
57
Chapter 1: Overview
Table 3-4 Product Line-up (416 pin)
MB91F527Y
System Clock
MB91F528Y
On-chip PLL Clock multiple method
Minimum instruction
execution time
FLASH Capacity
(Program)
8.0ns (128MHz)
1536KB + 64KB
FLASH Capacity (Data)
RAM Capacity
External Bus I/F
(22 address/16 data/4cs)
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 8 channels
Input capture
16-bit × 4 channels
32-bit × 8 channels
Output Compare
16-bit × 6 channels
32-bit × 8 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 88 channels
Up/down Counter
4 channels
Clock Supervisor
Yes
External interrupt
8 channels × 3 units
A/D
D/A (8-bit)
Multi-Function Serial
CAN
FlexRay
Hardware watchdog
58
2048KB + 64KB
12-bit × 32 channels (2 units)
2 channels
20 channels*1
128msg × 6 channels
1 channel
Yes
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
MB91F527Y
MB91F528Y
CRC generation
Yes
Low-voltage detection
reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
219 ports (no sub clock) / 217 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection Unit)
Yes
Key Code Register
Yes
6 channels
Wave Generator
Tuning RAM
None
Yes
Yes
JTAG
Operation guaranteed
temperature (Ta)
Power supply
-40°C to +125°C
2.7 V to 5.5 V*2
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: See "Figure 7-4")
(External bus I/F: 3.0 V to 3.6 V)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
59
Chapter 1: Overview
MB91F527Y
MB91F528Y
PAB416
Package
*1: Only channel 3, channel 4 and channel 12 to channel 19 support the I 2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V).
This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum
guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage.
Table 3-5 Correspondence table of ON/OFF for initial values of clock supervisor and external
low-voltage detection reset
Initial value of external
Clock
Initial value of clock supervisor
Function
low-voltage detection reset
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Single
OFF
ON
Dual
OFF
S
U
H
K
W
Y
J
L
MB91F52Xxyz
→Revision: C, D, E
→Function: See Table 3-5
→PKG Type: R 144 pin
U 176 pin
M 208 pin
Y BGA 416 pin
→Memory Size: 7 1.5MB
8 2MB
4. Function overview
This section shows function overview of MB91520 series.
Table 4-1 : Function overview
Function
CPU
60
Features
32-bit RISC microcontroller FR81S CPU core
Built-in memory protection function (MPU) 8 channels
Built-in floating-point operation (FPU)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
Features
Clock
Main oscillation : 4MHz (Up to 16MHz can be input)
Sub oscillation : 32kHz or None
PLL multiplication rate: Up to 32 times of multiplication
Built-in 100kHz CR oscillator
I/O ports
Each bit can be programmed for I/O or peripheral signals
Pull-up can be set.
External bus Interface
22-bit address, 8/16-bit Data output
Internal bus interface
On-chip bus : 32-bit,
MB91F52xR/MB91F52xU (LQS144/LQN144/LQP176): Maximum operating frequency :
80MHz
MB91F52xR/MB91F52xU (LES144/LEP176): Maximum operating frequency : 128MHz
MB91F52xM/MB91F52xY: Maximum operating frequency : 128MHz
Peripheral bus interface
Maximum operating frequency : 40MHz
32-bit peripheral bus, or 16-bit peripheral bus (R-bus)
*: Both of them operate in the same frequency.
Flash interface
Wild register function provided.
For small sector (64KB)
DMA controller
Up to 16 channels can be started simultaneously.
The transfer cause (internal peripheral request or software) is selectable.
Burst or block transfer mode is selectable.
- When two or more interrupts are in one interrupt vector, it can select from which
interrupt to generate the DMA demand.
- When two or more interrupts are in one interrupt vector, the interrupt cleared at the DMA
transfer completion can be selected.
Base timer
16-bit timer
Any of four PWM/PPG/PWC/reload timer functions can be selected and used.
A 32-bit timer can be used in 2 channels of cascade mode for the reload timer/PWC
function.
Free-run timer
16-bit/32-bit up counter
Free-run timer ch.0 to ch.2 : 16-bit
Free-run timer ch.3 to ch.5 : 32-bit
Only for MB91F52xM /MB91F52xY, the following is added:
Free-run timer ch.6 to ch.10: 32-bit
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61
Chapter 1: Overview
Function
Features
16-bit/32-bit capture registers to detect a rising edge, a falling edge, or both
edges.
When an edge of pin input is detected, the counter value of free-run timer is
latched and an interrupt request is generated.
Cooperation with the free-run timer is as follows.
Input capture ch.0 to ch.3 : 16-bit → Free-run timer ch.0 to ch.2
Input capture ch.4 to ch.9 : 32-bit → Free-run timer ch.3 to ch.5
Only for MB91F52xM/MB91F52xY is the following cooperation provided:
Input capture ch.4 to ch.11: 32-bit → Free-run timer ch.3 to ch.10
Input capture
Cooperation with LIN synch break/synch field is as follows.
Input capture ch.0 → Multi-function serial ch.0
Input capture ch.1 → Multi-function serial ch.1
Input capture ch.2 → Multi-function serial ch.2
Input capture ch.3 → Multi-function serial ch.3
Input capture ch.4 → Multi-function serial ch.4
Input capture ch.5 → Multi-function serial ch.5
Input capture ch.6 → Multi-function serial ch.6
Input capture ch.7 → Multi-function serial ch.7
Input capture ch.8 → Multi-function serial ch.8, ch.9
Input capture ch.9 → Multi-function serial ch.10, ch.11
Only for MB91F52xM/MB91F52xY are the following added:
Input capture ch.10 → Multi-function serial ch.12, ch.13, ch.14, ch.15
Input capture ch.11 → Multi-function serial ch.16, ch.17, ch.18, ch.19
Built-in cycle/pulse width measurement function (only 32-bit supported)
An interrupt signal is output during collating with the 16-bit/32-bit free-run timer.
Output compare
Cooperation with the free-run timer is as follows.
Output compare ch.0 to ch.5 : 16-bit → Free-run timer ch.0 to ch.2
Output compare ch.6 to ch.11 : 32-bit → Free-run timer ch.3 to ch.5
Only for MB91F52xM/MB91F52xY is the following cooperation:
Output compare ch.6 to ch.13: 32-bit → Free-run timer ch.3 to ch.10
Built-in compare level control function (only 32-bit supported)
16-bit output compare has no dedicated output pins.
There is only the output through the wave generator.
Reload timer
62
16-bit reload timer operation (The toggle output or one-shot output can be
selected)
Event count function can be selected.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
Features
Real-time clock
Day/hours/minutes/seconds register
Main or sub oscillation frequency can be selected for the operation clock.
Sub clock correction function
- The sub clock cycle error is monitored by the main clock.
- The detected error is reflected on the second counter set value.
An interrupt can be generated in unit of 0.5 second, seconds, minutes, hours, or
day.
Calibration
The real-time clock of the sub clock drive is corrected by comparison with the
main clock.
PPG
The cycle and duty used for the one-shot square wave output and PWM output
can be changed by the software.
Operation clock frequency :
Can be selected from following 4 types : PCLK × 1, 1/22, 1/24, 1/26
StartDelay of each channel can be set.
It is possible to use it as activation trigger of A/D Converter.
The cycle of the High format and the Low format and duty can be set.
Delay interrupt
An interrupt for task switching is generated.
The CPU interrupt request can be generated or canceled by the software.
External interrupt
MB91F52xR/MB91F52xU: 16 channel, independent
MB91F52xM/MB91F52xY: 24 channels, independent
Interrupt factor : rising edge / falling edge / "L" level / "H" level can be selected.
Support of edge input detection when returned to standby state.
A/D Converter
With built-in A/D converter 2 units of resolution in 12-bit
MB91F52xR/MB91F52xU: Able to sample the analog value from 48-channel input port
MB91F52xM/MB91F52xY: Able to sample the analog value from 64-channel input port
Conversion time : 12-bit A/D Converter 1.4μs
External trigger activation
Can be activated by an internal timer (16-bit reload timer/compare match/PPG are
used).
Has the function of selecting the sampling time for each channel.
Built-in range comparator
Has the function of selecting the sampling time for each channel.
D/A Converter
Built-in D/A converter 2 channels of resolution in 8-bit
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63
Chapter 1: Overview
Function
Features
Multi-function serial
Any of UART/CSIO/LIN/I2C-UART functions can be selected and used.
Transmission FIFO memory 16-byte, and reception FIFO memory 16-byte provided
Reception interrupt cause (3 types)
- Reception error detection (parity, overrun, and frame error)
- Detects FIFO’s reception of data up to an amount of its threshold.
- Detects the idling period which is 8 × baud rate clock or more, when amount of the data
received is less than FIFO’s threshold.
Transmission interrupt cause (2 types)
- No transmission operation.
- Empty transmission FIFO memory (including the time of transmission)
SPI (Serial Peripheral Interface) supported
LIN protocol revision 2.1 supported
I2C (ch.3, ch.4, ch.12 to ch.19) 100kbps and 400kbps supported
I2C (ch.5 to ch.8, ch.11) only 100kbps supported
Interrupt controller
Detects an interrupt request.
Sets an interrupt level.
Interrupt request batch read
A generation of multiple interrupts from peripherals can be read by a series of
registers.
CAN interface
CAN Specifications Version 2.0, Part A and Part B satisfied
128 message buffers × 6channels
Support plural messages
Flexible composition of acceptance filter :
Entire bit compare
Entire bit Mask
2 portion bit Mask
Up to 1Mbps supported.
CAN prescaler is mounted for the CAN operation clock
CAN wakeup function
CAN clock source can switch main clock/PLL clock.
FlexRay controller
(1 unit ch.A/ch.B)
Supports FlexRay specification version 2.1.
Up to 128-message buffer configuration
8KB message RAM
Variable-length message buffer configuration
Each message buffer can be configured as a part of a reception buffer, transmission buffer,
or reception FIFO.
Host access to message buffers through input and output buffers
Filtering the slot counter, cycle counter, and channels
Maskable interrupts
U/D counter
MB91F52xU/MB91F52xR: 8/16-bit up/down counter × 2channels
MB91F52xM/MB91F52xY: 8/16-bit up/down counter × 4 channels
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Chapter 1: Overview
Function
Software watchdog
Hardware watchdog
Features
It counts while CPU is working.
Stops counting when the CPU is stopped.
The intervals can be selected from 16 types (PCLK × (29 to 224) cycles).
The lower limit of the term of validity to clear can be set up to 16 ways.
RC-based CPU operation detection counter
Used against program overrun
Period: 218 to 655ms (usually 328ms, depending on the accuracy of the CR oscillation)
Note that as shown above, a period of the CR oscillation clock varies widely due to the
production process.
CRC generation
When data is sequentially written in the input registers, the CRC code is displayed in the
result register.
External low-voltage
detection reset
Reset/interrupt generation at external low-voltage detection
When an external power-supply voltage falls below the detection voltage value,
reset/interrupt is generated.
The detecting voltage (2.8 to 4.3 V) is possible to select 11 types.
Internal low-voltage
detection reset
Reset generation at internal low-voltage detection
Monitors 1.2V power supply and generates the reset.
Low-power consumption
mode
Sleep mode
Stop mode
Watch mode
Stop mode (power shutdown)
Watch mode (power shutdown)
Sub RUN Mode
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65
Chapter 1: Overview
Function
Features
I/O relocation
Relocation target peripheral function and number of branches are shown below.
CAN
(Max. 2 divergences for ch.0, Max. 2 divergences for ch.1, ch.5)
External interrupt
(Max. 2 divergences for ch.1 to ch.4, ch.7, ch.9, ch.13, ch.14,
ch.16, ch.17)
Multi-function serial (Max. 2 divergences for ch.0 and ch.2;
Max. 3 divergences for ch.3 and ch.4;
Note that the I2C cannot be relocated.)
Serial chip select input (Max. 2 divergences for ch.3, ch.4, ch.10)
PPG
(Max. 2 divergences for ch.0 to ch.5, ch.16, ch.17, ch.23 to ch.37,
ch.40, ch.41, ch.43, ch.44, ch.48, ch.49, ch.64 to ch.67, ch.86,
ch.87)
U/D counter
(Max. 3 divergences for ch.0; Max. 2 divergences for ch.1, ch.2)
Output compare
(Max. 2 divergences for ch.6 to ch.11)
Input capture
(Max. 4 divergences for ch.0 to ch.3;
Max. 3 divergences for ch.4;
Max. 2 divergences for ch.5 to ch.9)
Free-run timer
(Max. 2 divergences for ch.1, ch.3, ch.4, ch.5)
Base timer
2 channels × 2 divergences
Reload timer
(Max. 3 divergences for ch.0, ch.1, ch.3;
Max. 2 divergences for ch.2, ch.4, ch.5, ch.6, ch.7)
Wave Generator
(Max. 2 divergences for ch.0 to ch.5;
Max. 3 divergences for DTTI input)
External bus Interface (Max. 2 divergences for RDY input)
NMI request
Non-maskable interrupt signal that is entered from NMIX pin.
Debug interface
Built-in OCD
Boundary scan test
JTAG supported (TRST, RCK, TMS, TDI, TDO)
5. Block Diagram
This section shows block diagram of MB91520 series.
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Chapter 1: Overview
Figure 5-1 MB91F527R, MB91F528R
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 PCLK2)
Flex Ray clock control
I/O port setting
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Operation mode
register
Async Bus Bridge (PCLK1 PCLK2)
CRC
Wave generator (6ch)
I / O Port
DTTI,RTO
16bit Free-run timer (3ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
32bit Free-run timer (3ch)
FRCK
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
12bit AD converter (32ch + 16ch)
32bit Input capture (6ch)
Multi-function serial interface (12ch)
ICU
32bit Output compare (6ch)
OCU
Bus Bridge (32bit 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
Base timer (2ch)
TIOA,TIOB
PPG(44ch)
U/D counter (2ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (16ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Clock supervisor
Watchdog timer (SW and HW)
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
See "9.1 Pins of Each Function" for pins that can used by each function.
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67
Chapter 1: Overview
Figure 5-2 MB91F527U, MB91F528U
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 PCLK2)
Flex Ray clock control
Ｉ/Ｏ port setting
32bit Free-run timer (3ch)
I / O Port
FRCK
32bit Input capture (6ch)
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 PCLK2)
CRC
Wave generator (6ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 16ch)
Multi-function serial interface (12ch)
ICU
32bit Output compare (6ch)
OCU
DTTI,RTO
16bit Free-run timer (3ch)
Bus Bridge (32bit 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
Base timer (2ch)
TIOA,TIOB
PPG (48ch)
U/D counter (2ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (16ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Watchdog timer (SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
See "9.1 Pins of Each Function" for pins that can used by each function.
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Chapter 1: Overview
Figure 5-3 MB91F527M, MB91F528M
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 PCLK2)
Flex Ray clock control
Ｉ/Ｏ port setting
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Operation mode
register
Async Bus Bridge (PCLK1 PCLK2)
CRC
Wave generator (6ch)
I / O Port
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 32ch)
32bit Input capture (8ch)
Multi-function serial interface (20ch)
32bit Output compare (8ch)
TIOA,TIOB
FRCK
16bit Input capture (4ch)
ICU
OCU
DTTI,RTO
16bit Free-run timer (3ch)
32bit Free-run timer (8ch)
FRCK
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Bus Bridge (32bit 16bit)
Base timer (2ch)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
PPG (64ch)
U/D counter (4ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (24ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Clock supervisor
Watchdog timer (SW and HW)
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
See "9.1 Pins of Each Function" for pins that can used by each function.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
69
Chapter 1: Overview
Figure 5-4 MB91F527Y, MB91F528Y
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 PCLK2)
Flex Ray clock control
Ｉ/Ｏ port setting
32bit Free-run timer (8ch)
I / O Port
FRCK
32bit Input capture (8ch)
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 PCLK2)
CRC
Wave generator (6ch)
Base timer (2ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 32ch)
Multi-function serial interface (20ch)
32bit Output compare (8ch)
TIOA,TIOB
FRCK
16bit Input capture (4ch)
ICU
OCU
DTTI,RTO
16bit Free-run timer (3ch)
Bus Bridge (32bit 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
PPG (88ch)
U/D counter (4ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (24ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Watchdog timer (SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
See "9.1 Pins of Each Function" for pins that can used by each function.
70
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
6. Memory Map
This section shows memory map of MB91520 series.
Figure 6-1 Memory Map MB91F527, MB91F528
[ Tuning RAM function not used ]
[ Tuning RAM function used ]
MB91F528
MB91F528
MB91F527
0000 0000
H
I/O
0000 0000
H
I/O
0000 0000
H
I/O
0000 4000
H
BackUp RAM(16KB)
0000 4000
H
BackUp RAM(16KB)
0000 4000
H
BackUp RAM(16KB)
0000 8000
0001 0000
H
I/O
I/O
I/O
H
RAM(192KB)
0000 8000
0001 0000
H
RAM(192KB)
0000 8000
0001 0000
H
H
H
RAM(192KB)
0004 0000
H
Reserved
0004 0000
H
Reserved
0004 0000
H
Reserved
0007 0000
H
Flash Memory
(1536+64)KB
0007 0000
H
Flash Momory
(2048+64)KB
0007 0000
H
0008 0000
H
Flash Momory
(2048+64)KB
Tuning Area
(128KB)
000A 0000
H
000C 0000
H
000F FC00
H
0010 0000
H
0028 0000
H
000F FC00
H
0010 0000
H
0020 0000
H
Interrupt Vector
Reset Vector
Reserved
000F FC00
H
0010 0000
H
0028 0000
H
Interrupt Vector
Reset Vector
Reserved
Tuning Area
(128KB)
Interrupt Vector
Reset Vector
Reserved
Register
switching
0033 0000
H
0034 0000
H
Work Flash
(64KB)
0033 0000
H
0034 0000
H
Reserved
8000 0000
H
H
0033 0000
H
0034 0000
H
Reserved
7FFE 0000
H
8000 0000
H
External Area
FFFF FFFF
Work Flash
(64KB)
RAM
(128KB)
Reserved
7FFE 0000
H
8000 0000
H
FFFF FFFF
H
External Area
FFFF FFFF
H
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Work Flash
(64KB)
Tuning RAM
(128KB)
Mirror region of Tuning Area
External Area
71
Chapter 1: Overview
7. Pin Assignment
This section shows pin assignment of MB91520 series.
VCCE
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P012/D26/TIOB0_0/STOPWT_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P010/D24/RXDB_0
P007/D23/TXDB_0
P006/D22/SCS2_0/ADTG1_1/INT2_1/TXENB_0
P005/D21/SCK2_0/ADTG0_1/INT7_1/RXDA_0
P004/D20/SOT2_0/TXDA_0
P003/D19/SIN2_0/TIOB1_1/INT3_0/TXENA_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
VCCE
P134/RX2(128)_0/SCS1_1/ICU7_0/INT7_0
P133/TX2(128)_0
VSS
VCC
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P130/SCK0_0/TCK
P127/SOT0_0/TDO
P126/SIN0_0/INT6_0/TDI
P125/OCU11_0/TMS
P124/OCU10_0/TRST
DEBUGIF
VCC
Figure 7-1 Pin Assignment MB91F527R, MB91F528R
Power supply Gr.1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Power supply Gr.2
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P017/D31/TRG2_0
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0/RDY_1
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/A16/ICU4_1/TRG4_1
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0/TX5(128)_0
P052/A20/PPG34_0/INT14_0/RX5(128)_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCCE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
●
TOP VIEW
LQS144
LQFP-144
LQN144
TEQFP-144
LES144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
P123/OCU9_0/STOPWT_1
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0/TX4(128)_0
P120/AN30/OCU6_0/PPG22_0/INT9_0/RX4(128)_0
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1(128)_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0/RXDB_1
P113/AN25/PPG17_0/RTO1_0/TXDB_1
P112/AN24/PPG16_0/RTO0_0/TXENB_1
P111/RX1(128)_0/SCS62_0/AN23/INT1_0
P110/TX1(128)_0/SCS63_0/AN22
NMIX
P155/AN21/RXDA_1
P154/AN20/TXDA_1
P107/AN19/PPG15_0/TXENA_1
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0/RX3(128)_0
P101/SOT7_0/SDA7/AN13/PPG9_0/TX3(128)_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)_0/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)_0/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0(128)_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
VSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
P087/DAO0/PPG7_0/INT8_0
P086/DAO1/PPG6_0
P085/PPG5_0
P084/SCS51_0/AN3/PPG4_0
P083/SCS50_0/AN2/PPG3_0
P082/SIN5_0/AN1/PPG2_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P080/SCS52_0/PPG0_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P152/SCS53_0
P077/SCK3_0/SCL3
P076/SOT3_0/SDA3/TX5(128)_1
P075/SIN3_0/INT4_0/RX5(128)_1
P074/SCK4_0/SCL4
P073/SOT4_0/SDA4/AN33/ICU3_2
P072/SIN4_0/AN34/ICU2_2/INT5_0
P071/SCK4_2/AN35/ICU1_2/MONCLK
P070/ICU0_2
P067/AN36/FRCK5_0/AIN0_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
VCC
VSS
AVSS1/AVRL1
AVRH1
P057/RDY_0/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVCC1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
VSS
* In a single clock product, pin 121 and pin 122 are the general-purpose ports.
72
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
VCCE
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P167/PPG35_1
P012/D26/TIOB0_0/STOPWT_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P010/D24/RXDB_0
P166/PPG34_1
P007/D23/TXDB_0
P006/D22/SCS2_0/ADTG1_1/INT2_1/TXENB_0
P165/PPG33_1
P005/D21/SCK2_0/ADTG0_1/INT7_1/RXDA_0
P164/PPG32_1
P004/D20/SOT2_0/TXDA_0
P003/D19/SIN2_0/TIOB1_1/INT3_0/TXENA_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
VCCE
P134/RX2(128)_0/SCS1_1/ICU7_0/INT7_0
P133/TX2(128)_0
VSS
VCC
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P163/TRG6_2
P162/TRG5_2
P130/SCK0_0/TCK
P127/SOT0_0/TDO
P126/SIN0_0/INT6_0/TDI
P125/OCU11_0/TMS
P124/OCU10_0/TRST
P161/PPG31_1
P160/PPG30_1
DEBUGIF
VCC
Figure 7-2 Pin Assignment MB91F527U, MB91F528U
Power supply Gr.1
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
Power supply Gr.2
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P170/PPG36_1
P017/D31/TRG2_0
P171/PPG37_1
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P172/PPG38_1
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P173/PPG39_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0/RDY_1
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P174/TRG8_1
P175/TRG9_1
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/A16/ICU4_1/TRG4_1
P176/TRG10_0
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P177/TRG11_0
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0/TX5(128)_0
P052/A20/PPG34_0/INT14_0/RX5(128)_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCCE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
●
TOP VIEW
LQP176
LQFP-176
LEP176
TEQFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
P123/OCU9_0/STOPWT_1
P197/PPG29_1
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0/TX4(128)_0
P120/AN30/OCU6_0/PPG22_0/INT9_0/RX4(128)_0
P196/FRCK3_1/PPG28_1
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1(128)_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0/RXDB_1
P195/FRCK4_1/PPG27_1
P194/FRCK5_1/PPG26_1
P113/AN25/PPG17_0/RTO1_0/TXDB_1
P112/AN24/PPG16_0/RTO0_0/TXENB_1
P111/RX1(128)_0/SCS62_0/AN23/INT1_0
P110/TX1(128)_0/SCS63_0/AN22
NMIX
P155/AN21/RXDA_1
P154/AN20/TXDA_1
P193/PPG25_1
P107/AN19/PPG15_0/TXENA_1
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0/RX3(128)_0
P101/SOT7_0/SDA7/AN13/PPG9_0/TX3(128)_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)_0/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)_0/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0(128)_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P192/PPG24_1/TOT1_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
P191/TIN1_1
P190/TIN0_1
VSS
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
VCC
P087/DAO0/PPG7_0/INT8_0
P086/DAO1/PPG6_0
P085/PPG5_0
P084/SCS51_0/AN3/PPG4_0
P083/SCS50_0/AN2/PPG3_0
P082/SIN5_0/AN1/PPG2_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P080/SCS52_0/PPG0_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P152/SCS53_0
P077/SCK3_0/SCL3
P076/SOT3_0/SDA3/TX5(128)_1
P075/SIN3_0/INT4_0/RX5(128)_1
P074/SCK4_0/SCL4
P187/PPG47_0
P186/PPG46_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P072/SIN4_0/AN34/ICU2_2/INT5_0
P071/SCK4_2/AN35/ICU1_2/MONCLK
P070/ICU0_2
P067/AN36/FRCK5_0/AIN0_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P185/PPG45_0
P184/PPG44_0
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P183/PPG43_0
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P182/PPG42_0
VCC
VSS
AVSS1/AVRL1
AVRH1
P057/RDY_0/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVCC1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
P181/PPG41_0
P180/PPG40_0
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
VSS
* In a single clock product, pin 149 and pin 150 are the general-purpose ports.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
73
Chapter 1: Overview
VCCE
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P167/PPG35_1
P012/D26/TIOB0_0/STOPWT_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P237/SCS19_0/TRG15_0/ZIN3_0
P236/SIN19_0/TRG14_0/BIN3_0/INT23_0
P235/SOT19_0/SDA19/PPG63_0/AIN3_0
P234/SCK19_0/SCL19/PPG62_0
P010/D24/RXDB_0
P166/PPG34_1
P007/D23/TXDB_0
P006/D22/SCS2_0/ADTG1_1/INT2_1/TXENB_0
P165/PPG33_1
P005/D21/SCK2_0/ADTG0_1/INT7_1/RXDA_0
P164/PPG32_1
P004/D20/SOT2_0/TXDA_0
P003/D19/SIN2_0/TIOB1_1/INT3_0/TXENA_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
VCCE
P134/RX2(128)_0/SCS1_1/ICU7_0/INT7_0
P133/TX2(128)_0
VSS
VCC
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P163/TRG6_2
P162/TRG5_2
P130/SCK0_0/TCK
P127/SOT0_0/TDO
P126/SIN0_0/INT6_0/TDI
P233/SCS18_0/PPG61_0/INT16_1
P232/SIN18_0/PPG60_0/INT22_0
P231/SOT18_0/SDA18/OCU13_0/PPG59_0
P230/SCK18_0/SCL18/OCU12_0/PPG58_0
P125/OCU11_0/TMS
P124/OCU10_0/TRST
P161/PPG31_1
P160/PPG30_1
DEBUGIF
VCC
Figure 7-3 Pin Assignment MB91F527M, MB91F528M
Power supply Gr.1
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
Power supply Gr.2
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P170/PPG36_1
P017/D31/TRG2_0
P171/PPG37_1
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P172/PPG38_1
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P173/PPG39_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P200/SCK12_0/SCL12/AN63/TRG12_0
P201/SOT12_0/SDA12/AN62/TRG13_0
P202/SIN12_0/AN61/INT16_0
P203/SCS12_0/AN60
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0/RDY_1
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P174/TRG8_1
P175/TRG9_1
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P204/SCK13_0/SCL13/AN59/PPG48_0
P205/SOT13_0/SDA13/AN58/PPG49_0/AIN2_0
P206/SIN13_0/AN57/BIN2_0/INT17_0
P207/SCS13_0/AN56/ZIN2_0
P046/A16/ICU4_1/TRG4_1
P176/TRG10_0
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P177/TRG11_0
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0/TX5(128)_0
P052/A20/PPG34_0/INT14_0/RX5(128)_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCCE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
●
TOP VIEW
LQFP-208
LQR208
TEQFP-208
LER208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
P123/OCU9_0/STOPWT_1
P197/PPG29_1
P227/SIN17_0/PPG57_0/INT21_0
P226/SOT17_0/SDA17/PPG56_0
P225/SCK17_0/SCL17/PPG55_0
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0/TX4(128)_0
P120/AN30/OCU6_0/PPG22_0/INT9_0/RX4(128)_0
P196/FRCK3_1/PPG28_1
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1(128)_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0/RXDB_1
P195/FRCK4_1/PPG27_1
P194/FRCK5_1/PPG26_1
P113/AN25/PPG17_0/RTO1_0/TXDB_1
P112/AN24/PPG16_0/RTO0_0/TXENB_1
P111/RX1(128)_0/SCS62_0/AN23/INT1_0
P110/TX1(128)_0/SCS63_0/AN22
NMIX
VSS
VCC
P155/AN21/RXDA_1
P154/AN20/TXDA_1
P193/PPG25_1
P107/AN19/PPG15_0/TXENA_1
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0/RX3(128)_0
P101/SOT7_0/SDA7/AN13/PPG9_0/TX3(128)_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P222/SIN16_0/PPG54_0/INT20_0
P221/SOT16_0/SDA16/ICU11_0/PPG49_1
P220/SCK16_0/SCL16/ICU10_0/PPG48_1
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)_0/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)_0/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0(128)_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P192/PPG24_1/TOT1_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
P191/TIN1_1
P190/TIN0_1
VSS
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VCC
P087/DAO0/PPG7_0/INT8_0
P086/DAO1/PPG6_0
P085/PPG5_0
P084/SCS51_0/AN3/PPG4_0
P083/SCS50_0/AN2/PPG3_0
P082/SIN5_0/AN1/PPG2_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P080/SCS52_0/PPG0_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P152/SCS53_0
P077/SCK3_0/SCL3
P076/SOT3_0/SDA3/TX5(128)_1
P075/SIN3_0/INT4_0/RX5(128)_1
P217/SCS15_0/AN48/FRCK10_0/TRG13_1
P216/SIN15_0/AN49/FRCK9_0/TRG12_1/INT19_0
P215/SOT15_0/SDA15/AN50/FRCK8_0/PPG53_0
P214/SCK15_0/SCL15/AN51/PPG52_0
P074/SCK4_0/SCL4
P187/PPG47_0
P186/PPG46_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P072/SIN4_0/AN34/ICU2_2/INT5_0
P071/SCK4_2/AN35/ICU1_2/MONCLK
P070/ICU0_2
P067/AN36/FRCK5_0/AIN0_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P185/PPG45_0
P184/PPG44_0
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P183/PPG43_0
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P213/SCS14_0/AN52/FRCK7_0/INT17_1
P212/SIN14_0/AN53/FRCK6_0/ZIN2_1/INT18_0
P211/SOT14_0/SDA14/AN54/PPG51_0/BIN2_1
P210/SCK14_0/SCL14/AN55/PPG50_0/AIN2_1
P182/PPG42_0
VCC
VSS
AVSS1/AVRL1
AVRH1
P057/RDY_0/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVCC1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
P181/PPG41_0
P180/PPG40_0
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
VSS
* In a single clock product, pin 177 and pin 178 are the general-purpose ports.
74
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Figure 7-4 Pin Assignment MB91F527Y, MB91F528Y
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
VSS
B1
VSS
B 100
VCCE
B 99
P014
B 98
P012
B 97
P010
B 96
P006
B 95
P004
B 94
P002
B 93
P000
B 92
VCCE
B 91
VSS
B 90
C
B 89
VCC
B 88
VSS
B 87
P136
B 86
P135
B 85
VSS
B 84
X1
B 83
X0
B 82
VSS
B 81
P125
B 80
MD1
B 79
VCC
B 78
VSS
B 77
VSS
B 76
A
B
VSS
B2
VSS
B 101
VCCE
B 192
VSS
B 191
P013
B 190
P011
B 189
P007
B 188
P005
B 187
P003
B 186
P001
B 185
VCCE
B 184
VSS
B 183
VSS
B 182
VCC
B 181
RSTX
B 180
VSS
B 179
VSS
B 178
P291
B 177
VSS
B 176
VSS
B 175
P230
B 174
P286
B 173
MD0
B 172
VCC
B 171
VSS
B 170
VSS
B 75
B
C
P015
B3
VSS
B 102
VSS
B 193
P296
B 276
P295
B 275
P294
B 274
VSS
B 273
VSS
B 272
P234
B 271
P293
B 270
P165
B 269
VSS
B 268
VSS
B 267
VSS
B 266
VSS
B 265
P162
B 264
P127
B 263
P126
B 262
P233
B 261
P231
B 260
P287
B 259
P160
B 258
VSS
B 257
VSS
B 256
P284
B 169
D
P016
B4
P017
B 103
P240
B 194
VSS
B 277
P297
B 352
P167
B 351
P237
B 350
P236
B 349
P235
B 348
P166
B 347
P292
B 346
P164
B 345
VSS
B 344
P134
B 343
P133
B 342
P163
B 341
P130
B 340
P290
B 339
P232
B 338
P124
B 337
P161
B 336
P285
B 335
VSS
B 334
VSS
B 255
P226
B 168
P121
B 73
D
E
P020
B5
P021
B 104
P170
B 195
P241
B 278
Index
P123
B 333
P227
B 254
P122
B 167
P282
B 72
E
F
P022
B6
P023
B 105
VSS
B 196
P171
B 279
P197
B 332
VSS
B 253
P283
B 166
P115
B 71
F
G
P024
B7
P025
B 106
VSS
B 197
P242
B 280
P225
B 331
VSS
B 252
P116
B 165
P280
B 70
G
H
P026
B8
VSS
B 107
VSS
B 198
P243
B 281
P120
B 330
P117
B 251
P281
B 164
P194
B 69
H
J
P027
B9
P030
B 108
P244
B 199
P245
B 282
P196
B 329
VSS
B 250
P195
B 163
P111
B 68
J
K
P031
B 10
P032
B 109
P172
B 200
P173
B 283
VSS
B 353
VSS
B 380
VSS
B 379
VSS
B 378
VSS
B 377
VSS
B 376
VSS
B 375
VSS
B 374
P114
B 328
VSS
B 249
P113
B 162
P112
B 67
K
L
P033
B 11
P034
B 110
P200
B 201
P201
B 284
VSS
B 354
VSS
B 381
VSS
B 400
VSS
B 399
VSS
B 398
VSS
B 397
VSS
B 396
VSS
B 373
P110
B 327
P277
B 248
NMIX
B 161
P155
B 66
L
M
VCCE
B 12
VCCE
B 111
P202
B 202
P203
B 285
VSS
B 355
VSS
B 382
VSS
B 401
VSS
B 412
VSS
B 411
VSS
B 410
VSS
B 395
VSS
B 372
VSS
B 326
VSS
B 247
VSS
B 160
VSS
B 65
M
N
VSS
B 13
VSS
B 112
VSS
B 203
VSS
B 286
VSS
B 356
VSS
B 383
VSS
B 402
VSS
B 413
VSS
B 416
VSS
B 409
VSS
B 394
VSS
B 371
P154
B 325
VSS
B 246
VCC
B 159
VCC
B 64
N
P
VSS
B 14
VSS
B 113
VSS
B 204
VSS
B 287
VSS
B 357
VSS
B 384
VSS
B 403
VSS
B 414
VSS
B 415
VSS
B 408
VSS
B 393
VSS
B 370
P107
B 324
P106
B 245
P105
B 158
P193
B 63
P
R
P035
B 15
P036
B 114
P150
B 205
P151
B 288
VSS
B 358
VSS
B 385
VSS
B 404
VSS
B 405
VSS
B 406
VSS
B 407
VSS
B 392
VSS
B 369
P104
B 323
VSS
B 244
P103
B 157
P102
B 62
R
T
P037
B 16
P040
B 115
VSS
B 206
P174
B 289
VSS
B 359
VSS
B 386
VSS
B 387
VSS
B 388
VSS
B 389
VSS
B 390
VSS
B 391
VSS
B 368
P101
B 322
VSS
B 243
P100
B 156
AVCC0
B 61
T
U
P041
B 17
P042
B 116
VSS
B 207
P175
B 290
VSS
B 360
VSS
B 361
VSS
B 362
VSS
B 363
VSS
B 364
VSS
B 365
VSS
B 366
VSS
B 367
P221
B 321
P275
B 242
P276
B 155
AVRH0
B 60
U
V
P043
B 18
P044
B 117
P204
B 208
P205
B 291
P096
B 320
VSS
B 241
P222
B 154
AVRL0
B 59
V
W
P045
B 19
P046
B 118
VSS
B 209
P206
B 292
P093
B 319
VSS
B 240
P220
B 153
AVSS0
W
B 58
Y
P047
B 20
P050
B 119
VSS
B 210
P207
B 293
P092
B 318
P273
B 239
P095
B 152
P097
B 57
Y
AA
P051
B 21
P052
B 120
P176
B 211
P177
B 294
P270
B 317
VSS
B 238
P272
B 151
P094
B 56
AA
AB
P053
B 22
P054
B 121
P250
B 212
P251
B 295
P267
B 316
P090
B 237
P091
B 150
P192
B 55
AB
AC
P252
B 23
P253
B 122
VSS
B 213
VSS
B 296
P180
B 297
P181
B 298
P182
B 299
P211
B 300
VSS
B 301
P061
B 302
P063
B 303
P065
B 304
P066
B 305
P072
B 306
P263
B 307
P074
B 308
P265
B 309
P080
B 310
P082
B 311
TCK
B 312
P083
B 313
P086
B 314
VSS
B 315
P266
B 236
P191
B 149
P271
B 54
AC
AD
VCCE
B 24
VCCE
B 123
VSS
B 214
VSS
B 215
P255
B 216
P256
B 217
VSS
B 218
P213
B 219
VSS
B 220
VSS
B 221
P062
B 222
VSS
B 223
VSS
B 224
P071
B 225
VSS
B 226
VSS
B 227
P076
B 228
VSS
B 229
VSS
B 230
TDI
B 231
VSS
B 232
VSS
B 233
P085
B 234
VSS
B 235
P087
B 148
P190
B 53
AD
AE
VSS
B 25
VSS
B 124
P056
B 125
P254
B 126
P057
B 127
P210
B 128
P212
B 129
P060
B 130
VSS
B 131
VCC
B 132
VCC
B 133
P064
B 134
P185
B 135
P070
B 136
P262
B 137
P187
B 138
P216
B 139
P075
B 140
P264
B 141
P153
B 142
TDO
B 143
TRST
B 144
TMS
B 145
VCC
B 146
VSS
B 147
VSS
B 52
AE
AF
VSS
B 26
VSS
B 27
P055
B 28
AVCC1
B 29
AVRH1
B 30
AVRL1
B 31
AVSS1
B 32
VSS
B 33
VSS
B 34
VCC
B 35
VCC
B 36
P183
B 37
P184
B 38
P067
B 39
P073
B 40
P186
B 41
P215
B 42
P214
B 43
P217
B 44
P077
B 45
P152
B 46
P081
B 47
P084
B 48
VCC
B 49
VSS
B 50
VSS
B 51
AF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Power supply Gr.2
Power supply Gr.1
DEBUGIF
C
B 74
PAB416
BGA-416
* In a single clock product, pin A16 and pin A17 are the general-purpose ports.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
75
Chapter 1: Overview
8. Device Package
This section explains device package of MB91520 series.
Figure 8-1 LQS144 External Dimensions
76
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Figure 8-2 LQN144 External Dimensions
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
77
Chapter 1: Overview
Figure 8-3 LQP176 External Dimensions
78
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Figure 8-4 LQR208 External Dimensions
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
79
Chapter 1: Overview
Figure 8-5 LES144 External Dimensions
80
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Figure 8-6 LEP176 External Dimensions
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
81
Chapter 1: Overview
Figure 8-7 LER208 External Dimensions
82
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Figure 8-8 PAB416 External Dimensions
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
83
Chapter 1: Overview
9. Explanation of Pin Functions
The pin function list of MB91520 series is shown below.
Table 9-1 List of Pin Functions
144
176
208
PAB
416
Polarity
Pin Number
I/O
circuit
type
-
-
-
D3
P240
-
A
General-purpose I/O port
-
-
-
E4
P241
-
A
General-purpose I/O port
2
2
2
C1
3
3
3
D1
P015
D29
TRG0_0
P016
D30
TRG1_0
-
-
4
4
E3
P170
PPG36_1
-
A
General-purpose I/O port
PPG ch.36 output pin(1)
4
5
5
D2
P017
D31
TRG2_0
-
R
General-purpose I/O port
External Bus data bit31 I/O pin
PPG trigger 2 input pin(0)
-
6
6
F4
P171
PPG37_1
-
A
General-purpose I/O port
PPG ch.37 output pin(1)
-
-
-
G4
P242
TRG16_0
-
A
General-purpose I/O port
PPG trigger 16 input pin(0)
-
-
-
H4
P243
TRG17_0
-
A
General-purpose I/O port
PPG trigger 17 input pin(0)
P020
ASX
SIN3_1
TRG3_0
TIN0_2
RTO5_1
P021
CS0X
SOT3_1
TRG6_1
TRG4_0
P022
CS1X
SCK3_1
TRG7_1
TRG5_0
-
5
7
7
E1
6
8
8
E2
7
9
9
F1
84
Pin Name
R
R
F
A
F
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
External Bus data bit29 I/O pin
PPG trigger 0 input pin(0)
General-purpose I/O port
External Bus data bit30 I/O pin
PPG trigger 1 input pin(0)
General-purpose I/O port
External Bus address strobe output pin
Multi-function serial ch.3 serial data input pin(1)
PPG trigger 3 input pin(0)
Reload timer ch.0 event input pin(2)
Waveform generator ch.5 output pin(1)
General-purpose I/O port
External Bus chip select 0 output pin
Multi-function serial ch.3 serial data output pin(1)
PPG trigger 6 input pin(1)
PPG trigger 4 input pin(0)
General-purpose I/O port
External Bus chip select 1 output pin
Multi-function serial ch.3 clock I/O pin(1)
PPG trigger 7 input pin(1)
PPG trigger 5 input pin(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
8
10
10
F2
-
-
-
J3
-
-
-
J4
9
11
11
G1
10
12
12
G2
-
13
13
K3
11
14
14
H1
12
15
15
J1
-
16
16
K4
13
17
17
J2
14
18
18
K1
Pin Name
P023
RDX
SCS3_1
PPG32_0
TIN0_0
P244
PPG64_0
P245
PPG65_0
P024
WR0X
SIN4_1
PPG24_0
TIN1_0
RTO4_1
INT15_0
P025
WR1X
SOT4_1
PPG25_0
TIN2_0
P172
PPG38_1
P026
A00
SCK4_1
PPG26_0
TIN3_0
P027
A01
SCS40_1
PPG27_0
TOT0_0
RTO3_1
P173
PPG39_1
P030
A02
SCS41_1
PPG28_0
TOT1_0
P031
A03
SCS42_1
PPG29_0
TOT2_0
Polarity
Chapter 1: Overview
-
I/O
circuit
type
A
A
A
F
A
A
F
A
A
A
A
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
External Bus read strobe output pin
Serial chip select 3 I/O pin(1)
PPG ch.32 output pin(0)
Reload timer ch.0 event input pin(0)
General-purpose I/O port
PPG ch.64 output pin(0)
General-purpose I/O port
PPG ch.65 output pin(0)
General-purpose I/O port
External Bus write strobe 0 output pin
Multi-function serial ch.4 serial data input pin(1)
PPG ch.24 output pin(0)
Reload timer ch.1 event input pin(0)
Waveform generator ch.4 output pin(1)
INT15 external interrupt input pin(0)
General-purpose I/O port
External Bus write strobe 1 output pin
Multi-function serial ch.4 serial data output pin(1)
PPG ch.25 output pin(0)
Reload timer ch.2 event input pin(0)
General-purpose I/O port
PPG ch.38 output pin(1)
General-purpose I/O port
External Bus address bit0 output pin
Multi-function serial ch.4 clock I/O pin(1)
PPG ch.26 output pin(0)
Reload timer ch.3 event input pin(0)
General-purpose I/O port
External Bus address bit1 output pin
Serial chip select 40 I/O pin(1)
PPG ch.27 output pin(0)
Reload timer ch.0 output pin(0)
Waveform generator ch.3 output pin(1)
General-purpose I/O port
PPG ch.39 output pin(1)
General-purpose I/O port
External Bus address bit2 output pin
Serial chip select 41 output pin(1)
PPG ch.28 output pin(0)
Reload timer ch.1 output pin(0)
General-purpose I/O port
External Bus address bit3 output pin
Serial chip select 42 output pin(1)
PPG ch.29 output pin(0)
Reload timer ch.2 output pin(0)
85
Pin Number
144
176
208
PAB
416
15
19
19
K2
-
-
20
L3
-
-
21
P032
A04
SCS43_1
PPG30_0
TOT3_0
RTO2_1
P200
SCK12_0/SCL12
-
AN63
TRG12_0
P201
SOT12_0/SDA12
-
AN62
TRG13_0
P202
SIN12_0
AN61
INT16_0
P203
SCS12_0
AN60
P033
A05
PPG31_0
ICU3_3
TIN4_0
RTO1_1
SCK3_2
P034
A06
OCU11_1
ICU2_3
TIN5_0
RTO0_1
SOT3_2
P150
RDY_1
SOT8_0/SDA8
-
-
22
M3
-
-
23
M4
16
20
24
L1
17
21
25
L2
18
22
26
R3
OCU10_1
TRG6_0
ICU1_3
TIN6_0
-
I/O
circuit
type
A
Q
L4
-
86
Pin Name
Polarity
Chapter 1: Overview
Q
G
B
A
A
F
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
External Bus address bit4 output pin
Serial chip select 43 output pin(1)
PPG ch.30 output pin(0)
Reload timer ch.3 output pin(0)
Waveform generator ch.2 output pin(1)
General-purpose I/O port
Multi-function serial ch.12 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 63 input pin
PPG trigger 12 input pin(0)
General-purpose I/O port
Multi-function serial ch.12 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 62 input pin
PPG trigger 13 input pin(0)
General-purpose I/O port
Multi-function serial ch.12 serial data input pin(0)
ADC analog 61 input pin
INT16 external interrupt input pin(0)
General-purpose I/O port
Serial chip select 12 I/O pin(0)
ADC analog 60 input pin
General-purpose I/O port
External Bus address bit5 output pin
PPG ch.31 output pin(0)
Input capture ch.3 input pin(3)
Reload timer ch.4 event input pin(0)
Waveform generator ch.1 output pin(1)
Multi-function serial ch.3 clock I/O pin(2)
General-purpose I/O port
External Bus address bit6 output pin
Output compare ch.11 output pin(1)
Input capture ch.2 input pin(3)
Reload timer ch.5 event input pin(0)
Waveform generator ch.0 output pin(1)
Multi-function serial ch.3 serial data output pin(2)
General-purpose I/O port
External Bus RDY input pin (1)
Multi-function serial ch.8 serial data output
pin(0)/I2C bus serial data I/O pin
Output compare ch.10 output pin(1)
PPG trigger 6 input pin(0)
Input capture ch.1 input pin(3)
Reload timer ch.6 event input pin(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
19
23
27
R4
20
24
28
R1
21
25
29
R2
22
26
30
T1
-
27
31
T4
-
28
32
U4
23
29
33
T2
24
30
34
U1
Pin Name
Polarity
Chapter 1: Overview
P151
SCK8_0/SCL8
-
OCU9_1
TRG7_0
ICU0_3
TIN7_0
ZIN0_2
DTTI_1
P035
A07
SIN8_0
OCU8_1
TOT4_0
AIN0_0
INT11_0
P036
A08
SCS8_0
OCU7_1
TOT5_0
BIN0_0
P037
A09
OCU6_1
TOT6_0
ZIN0_0
P174
TRG8_1
P175
TRG9_1
P040
A10
PPG23_1
TOT7_0
AIN1_0
SIN0_1
P041
A11
SIN9_0
ICU9_1
BIN1_0
INT12_0
-
I/O
circuit
type
F
I
A
A
A
A
A
I
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Multi-function serial ch.8 clock I/O pin(0)/
I2C bus serial clock I/O pin
Output compare ch.9 output pin(1)
PPG trigger 7 input pin(0)
Input capture ch.0 input pin(3)
Reload timer ch.7 event input pin(0)
U/D counter ch.0 ZIN input pin(2)
Waveform generator ch.0-ch.5 input pin(1)
General-purpose I/O port
External Bus address bit7 output pin
Multi-function serial ch.8 serial data input pin(0)
Output compare ch.8 output pin(1)
Reload timer ch.4 output pin(0)
U/D counter ch.0 AIN input pin(0)
INT11 external interrupt input pin(0)
General-purpose I/O port
External Bus address bit8 output pin
Serial chip select 8 I/O pin(0)
Output compare ch.7 output pin(1)
Reload timer ch.5 output pin(0)
U/D counter ch.0 BIN input pin(0)
General-purpose I/O port
External Bus address bit9 output pin
Output compare ch.6 output pin(1)
Reload timer ch.6 output pin(0)
U/D counter ch.0 ZIN input pin(0)
General-purpose I/O port
PPG trigger 8 input pin(1)
General-purpose I/O port
PPG trigger 9 input pin(1)
General-purpose I/O port
External Bus address bit10 output pin
PPG ch.23 output pin(1)
Reload timer ch.7 output pin(0)
U/D counter ch.1 AIN input pin(0)
Multi-function serial ch.0 serial data input pin(1)
General-purpose I/O port
External Bus address bit11 output pin
Multi-function serial ch.9 serial data input pin(0)
Input capture ch.9 input pin(1)
U/D counter ch.1 BIN input pin(0)
INT12 external interrupt input pin(0)
87
Pin Number
144
176
208
PAB
416
25
31
35
U2
26
32
36
V1
27
33
37
V2
28
34
38
W1
-
-
39
V3
-
-
40
V4
-
-
41
W4
-
-
42
Y4
29
35
43
W2
88
Pin Name
Polarity
Chapter 1: Overview
P042
A12
SOT9_0
AN47
ICU8_1
TRG0_1
ZIN1_0
P043
A13
ICU7_1
TRG1_1
P044
A14
SCS9_0
ICU6_1
TRG2_1
P045
A15
SCK9_0
AN46
ICU5_1
TRG3_1
TOT1_2
P204
SCK13_0/SCL13
-
AN59
PPG48_0
P205
SOT13_0/SDA13
-
AN58
PPG49_0
AIN2_0
P206
SIN13_0
AN57
BIN2_0
INT17_0
P207
SCS13_0
AN56
ZIN2_0
P046
A16
ICU4_1
TRG4_1
-
I/O
circuit
type
B
A
A
G
Q
Q
G
B
A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
External Bus address bit12 output pin
Multi-function serial ch.9 serial data output pin(0)
ADC analog 47 input pin
Input capture ch.8 input pin(1)
PPG trigger 0 input pin(1)
U/D counter ch.1 ZIN input pin(0)
General-purpose I/O port
External Bus address bit13 output pin
Input capture ch.7 input pin(1)
PPG trigger 1 input pin(1)
General-purpose I/O port
External Bus address bit14 output pin
Serial chip select 9 I/O pin(0)
Input capture ch.6 input pin(1)
PPG trigger 2 input pin(1)
General-purpose I/O port
External Bus address bit15 output pin
Multi-function serial ch.9 clock I/O pin(0)
ADC analog 46 input pin
Input capture ch.5 input pin(1)
PPG trigger 3 input pin(1)
Reload timer ch.1 output pin(2)
General-purpose I/O port
Multi-function serial ch.13 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 59 input pin
PPG ch.48 output pin(0)
General-purpose I/O port
Multi-function serial ch.13 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 58 input pin
PPG ch.49 output pin(0)
U/D counter ch.2 AIN input pin(0)
General-purpose I/O port
Multi-function serial ch.13 serial data input pin(0)
ADC analog 57 input pin
U/D counter ch.2 BIN input pin(0)
INT17 external interrupt input pin(0)
General-purpose I/O port
Serial chip select 13 I/O pin(0)
ADC analog 56 input pin
U/D counter ch.2 ZIN input pin(0)
General-purpose I/O port
External Bus address bit16 output pin
Input capture ch.4 input pin(1)
PPG trigger 4 input pin(1)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
-
36
44
AA3
30
37
45
Y1
-
38
46
AA4
31
39
47
Y2
32
40
48
AA1
-
-
-
AB3
-
-
-
AB4
33
41
49
AA2
34
42
50
AB1
35
43
51
AB2
-
-
-
-
-
-
Pin Name
Polarity
Chapter 1: Overview
I/O
circuit
type
Function
(Please refer to the chapter of "I/O port" for
the switch.)
P176
TRG10_0
P047
A17
AN45
TRG8_0
TIN3_2
SOT0_1
P177
TRG11_0
P050
A18
TRG5_1
PPG33_0
P051
A19
TRG9_0
TX5(128)_0
P250
PPG66_0
P251
PPG67_0
P052
A20
PPG34_0
INT14_0
RX5(128)_0
P053
A21
AN44
PPG35_0
INT14_1
SCK0_1
P054
SYSCLK
PPG36_0
-
AC1
P252
-
A
General-purpose I/O port
-
AC2
P253
-
A
General-purpose I/O port
-
-
AE4
-
-
AD5
P254
PPG68_0
P255
PPG69_0
-
A
B
A
A
A
A
A
R
B
A
A
A
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
General-purpose I/O port
PPG trigger 10 input pin(0)
General-purpose I/O port
External Bus address bit17 output pin
ADC analog 45 input pin
PPG trigger 8 input pin(0)
Reload timer ch.3 event input pin(2)
Multi-function serial ch.0 serial data output pin(1)
General-purpose I/O port
PPG trigger 11 input pin(0)
General-purpose I/O port
External Bus address bit18 output pin
PPG trigger 5 input pin(1)
PPG ch.33 output pin(0)
General-purpose I/O port
External Bus address bit19 output pin
PPG trigger 9 input pin(0)
CAN transmission data 5 output pin(0)
General-purpose I/O port
PPG ch.66 output pin(0)
General-purpose I/O port
PPG ch.67 output pin(0)
General-purpose I/O port
External Bus address bit20 output pin
PPG ch.34 output pin(0)
INT14 external interrupt input pin(0)
CAN reception data 5 input pin(0)
General-purpose I/O port
External Bus address bit21 output pin
ADC analog 44 input pin
PPG ch.35 output pin(0)
INT14 external interrupt input pin(1)
Multi-function serial ch.0 clock I/O pin(1)
General-purpose I/O port
External Bus system clock output pin
PPG ch.36 output pin(0)
General-purpose I/O port
PPG ch.68 output pin(0)
General-purpose I/O port
PPG ch.69 output pin(0)
89
Pin Number
144
176
208
PAB
416
38
46
54
AF3
-
47
55
AC5
-
48
56
AC6
39
49
57
AE3
-
-
-
AD6
41
51
59
AE5
-
56
64
AC7
-
-
65
AE6
-
-
66
AC8
90
Pin Name
Polarity
Chapter 1: Overview
P055
CS2X
SIN10_0
AN43
PPG37_0
TIN4_1
P180
PPG40_0
P181
PPG41_0
P056
CS3X
ICU9_0
PPG0_1
ICU0_1
TIN5_1
DTTI_2
P256
PPG66_1
P057
RDY_0
SCK10_1
AN42
ICU8_0
TRG0_2
PPG1_1
ICU1_1
TIN6_1
P182
PPG42_0
P210
SCK14_0/SCL14
-
AN55
PPG50_0
AIN2_1
P211
SOT14_0/SDA14
-
AN54
PPG51_0
BIN2_1
-
I/O
circuit
type
G
A
A
A
A
G
A
Q
Q
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
External Bus chip select 2 output pin
Multi-function serial ch.10 serial data input pin(0)
ADC analog 43 input pin
PPG ch.37 output pin(0)
Reload timer ch.4 event input pin(1)
General-purpose I/O port
PPG ch.40 output pin(0)
General-purpose I/O port
PPG ch.41 output pin(0)
General-purpose I/O port
External Bus chip select 3 output pin
Input capture ch.9 input pin(0)
PPG ch.0 output pin(1)
Input capture ch.0 input pin(1)
Reload timer ch.5 event input pin(1)
Waveform generator ch.0 to ch.5 input pin(2)
General-purpose I/O port
PPG ch.66 output pin(1)
General-purpose I/O port
External Bus RDY input pin (0)
Multi-function serial ch.10 clock I/O pin(1)
ADC analog 42 input pin
Input capture ch.8 input pin(0)
PPG trigger 0 input pin(2)
PPG ch.1 output pin(1)
Input capture ch.1 input pin(1)
Reload timer ch.6 event input pin(1)
General-purpose I/O port
PPG ch.42 output pin(0)
General-purpose I/O port
Multi-function serial ch.14 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 55 input pin
PPG ch.50 output pin(0)
U/D counter ch.2 AIN input pin(1)
General-purpose I/O port
Multi-function serial ch.14 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 54 input pin
PPG ch.51 output pin(0)
U/D counter ch.2 BIN input pin(1)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
-
-
67
AE7
-
-
68
AD8
46
57
69
AE8
47
58
70
AC10
48
59
71
AD11
49
60
72
AC11
-
61
73
AF12
Pin Name
Polarity
Chapter 1: Overview
P212
SIN14_0
AN53
FRCK6_0
ZIN2_1
INT18_0
P213
SCS14_0
AN52
FRCK7_0
INT17_1
P060
SCS10_0
PPG2_1
ICU2_1
TOT5_1
INT13_0
P061
SOT10_1
-
AN41
ICU6_0
PPG3_1
ICU3_1
TOT6_1
INT13_1
P062
SCS10_1
SCS40_0
AN40
PPG4_1
FRCK0_0
TOT7_1
ZIN1_1
P063
SCS41_0
AN39
PPG5_1
FRCK1_0
BIN1_1
P183
PPG43_0
-
I/O
circuit
type
G
B
A
B
B
B
A
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Multi-function serial ch.14 serial data input pin(0)
ADC analog 53 input pin
Free-run timer 6 clock input pin(0)
U/D counter ch.2 ZIN input pin(1)
INT18 external interrupt input pin(0)
General-purpose I/O port
Serial chip select 14 I/O pin(0)
ADC analog 52 input pin
Free-run timer 7 clock input pin(0)
INT17 external interrupt input pin(1)
General-purpose I/O port
Serial chip select 10 I/O pin(0)
PPG ch.2 output pin(1)
Input capture ch.2 input pin(1)
Reload timer ch.5 output pin(1)
INT13 external interrupt input pin(0)
General-purpose I/O port
Multi-function serial ch.10 serial data output
pin(1)
ADC analog 41 input pin
Input capture ch.6 input pin(0)
PPG ch.3 output pin(1)
Input capture ch.3 input pin(1)
Reload timer ch.6 output pin(1)
INT13 external interrupt input pin(1)
General-purpose I/O port
Serial chip select 10 I/O pin(1)
Serial chip select 40 I/O pin(0)
ADC analog 40 input pin
PPG ch.4 output pin(1)
Free-run timer 0 clock input pin(0)
Reload timer ch.7 output pin(1)
U/D counter ch.1 ZIN input pin(1)
General-purpose I/O port
Serial chip select 41 output pin(0)
ADC analog 39 input pin
PPG ch.5 output pin(1)
Free-run timer 1 clock input pin(0)
U/D counter ch.1 BIN input pin(1)
General-purpose I/O port
PPG ch.43 output pin(0)
91
Pin Number
144
176
208
PAB
416
50
62
74
AE12
51
63
75
AC12
-
64
76
AF13
-
65
77
AE13
52
66
78
AC13
53
67
79
AF14
54
68
80
AE14
55
69
81
AD14
56
57
70
71
82
83
AC14
P064
SCS42_0
AN38
FRCK2_0
AIN1_1
PPG43_1
P065
SCS43_0
FRCK3_0
ZIN0_1
PPG44_1
P184
PPG44_0
P185
PPG45_0
P066
SOT4_2
SCS3_0
AN37
FRCK4_0
BIN0_1
P067
AN36
FRCK5_0
AIN0_1
P070
ICU0_2
P071
SCK4_2
AN35
ICU1_2
MONCLK
P072
SIN4_0
-
AN34
ICU2_2
INT5_0
P073
SOT4_0/SDA4
-
AN33
ICU3_2
P262
PPG70_0
P263
PPG71_0
-
AF15
-
-
-
AE15
-
-
-
AC15
92
Pin Name
Polarity
Chapter 1: Overview
I/O
circuit
type
B
A
A
A
B
B
A
G
G
D
A
A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Serial chip select 42 output pin(0)
ADC analog 38 input pin
Free-run timer 2 clock input pin(0)
U/D counter ch.1 AIN input pin(1)
PPG ch.43 output pin(1)
General-purpose I/O port
Serial chip select 43 output pin(0)
Free-run timer 3 clock input pin(0)
U/D counter ch.0 ZIN input pin(1)
PPG ch.44 output pin(1)
General-purpose I/O port
PPG ch.44 output pin(0)
General-purpose I/O port
PPG ch.45 output pin(0)
General-purpose I/O port
Multi-function serial ch.4 serial data output pin(2)
Serial chip select 3 I/O pin(0)
ADC analog 37 input pin
Free-run timer 4 clock input pin(0)
U/D counter ch.0 BIN input pin(1)
General-purpose I/O port
ADC analog 36 input pin
Free-run timer 5 clock input pin(0)
U/D counter ch.0 AIN input pin(1)
General-purpose I/O port
Input capture ch.0 input pin(2)
General-purpose I/O port
Multi-function serial ch.4 clock I/O pin(2)
ADC analog 35 input pin
Input capture ch.1 input pin(2)
Clock monitor output pin
General-purpose I/O port
Multi-function serial ch.4 serial data input pin(0)
ADC analog 34 input pin
Input capture ch.2 input pin(2)
INT5 external interrupt input pin(0)
General-purpose I/O port
Multi-function serial ch.4 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 33 input pin
Input capture ch.3 input pin(2)
General-purpose I/O port
PPG ch.70 output pin(0)
General-purpose I/O port
PPG ch.71 output pin(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
-
72
84
AF16
-
73
85
AE16
58
74
86
AC16
-
-
87
Pin Name
Polarity
Chapter 1: Overview
P186
PPG46_0
P187
PPG47_0
P074
SCK4_0/SCL4
-
P214
SCK15_0/SCL15
-
AN51
PPG52_0
P215
SOT15_0/SDA15
-
AN50
FRCK8_0
PPG53_0
P216
SIN15_0
AN49
FRCK9_0
TRG12_1
INT19_0
P217
SCS15_0
AN48
FRCK10_0
TRG13_1
P075
SIN3_0
INT4_0
RX5(128)_1
P076
SOT3_0/SDA3
-
TX5(128)_1
P077
SCK3_0/SCL3
-
P264
PPG72_0
P265
PPG73_0
P152
SCS53_0
-
AF18
-
-
88
AF17
-
-
89
AE17
-
-
90
AF19
59
75
91
AE18
60
76
92
AD17
61
77
93
AF20
-
-
-
AE19
-
-
-
AC17
62
78
94
AF21
I/O
circuit
type
A
A
E
Q
Q
G
B
F
P
E
A
A
A
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
PPG ch.46 output pin(0)
General-purpose I/O port
PPG ch.47 output pin(0)
General-purpose I/O port
Multi-function serial ch.4 clock I/O pin(0) /
I2C bus serial clock I/O pin
General-purpose I/O port
Multi-function serial ch.15 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 51 input pin
PPG ch.52 output pin(0)
General-purpose I/O port
Multi-function serial ch.15 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 50 input pin
Free-run timer 8 clock input pin(0)
PPG ch.53 output pin(0)
General-purpose I/O port
Multi-function serial ch.15 serial data input pin(0)
ADC analog 49 input pin
Free-run timer 9 clock input pin(0)
PPG trigger 12 input pin(1)
INT19 external interrupt input pin(0)
General-purpose I/O port
Serial chip select 15 I/O pin(0)
ADC analog 48 input pin
Free-run timer 10 clock input pin(0)
PPG trigger 13 input pin(1)
General-purpose I/O port
Multi-function serial ch.3 serial data input pin(0)
INT4 external interrupt input pin(0)
CAN reception data 5 input pin(1)
General-purpose I/O port
Multi-function serial ch.3 serial data output
pin(0)/I2C bus serial data I/O pin
CAN transmission data 5 output pin(1)
General-purpose I/O port
Multi-function serial ch.3 clock I/O pin(0)/
I2C bus serial clock I/O pin
General-purpose I/O port
PPG ch.72 output pin(0)
General-purpose I/O port
PPG ch.73 output pin(0)
General-purpose I/O port
Serial chip select 53 output pin(0)
93
Pin Number
144
176
208
Pin Name
PAB
416
63
79
95
AE20
64
80
96
AC18
65
81
97
AF22
Polarity
Chapter 1: Overview
P153
SCK5_0/SCL5
-
AN32
FRCK1_1
INT4_1
P080
SCS52_0
PPG0_0
P081
SOT5_0/SDA5
-
AN0
PPG1_0
-
I/O
circuit
type
G
A
G
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Multi-function serial ch.5 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 32 input pin
Free-run timer 1 clock input pin(1)
INT4 external interrupt input pin(1)
General-purpose I/O port
Serial chip select 52 output pin(0)
PPG ch.0 output pin(0)
General-purpose I/O port
Multi-function serial ch.5 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 0 input pin
PPG ch.1 output pin(0)
-
-
-
AE21
TDO
-
W
JTAG test data output
-
-
-
AD20
TDI
-
V
JTAG test data input
-
G
General-purpose I/O port
Multi-function serial ch.5 serial data input pin(0)
ADC analog 1 input pin
PPG ch.2 output pin(0)
66
82
98
AC19
P082
SIN5_0
AN1
PPG2_0
-
-
-
AE22
TRST
-
V
JTAG test reset input
-
-
-
AC20
TCK
-
V
JTAG test clock input
-
-
-
AE23
TMS
-
V
JTAG test mode state input
P083
SCS50_0
AN2
PPG3_0
P084
SCS51_0
AN3
PPG4_0
P085
PPG5_0
P086
DAO1
PPG6_0
P087
DAO0
PPG7_0
INT8_0
P266
PPG74_0
P267
PPG75_0
-
67
83
99
AC21
68
84
100
AF23
69
85
101
AD23
70
86
102
AC22
71
87
103
AD25
-
-
-
AC24
-
-
-
AB23
94
B
B
A
C
C
A
A
General-purpose I/O port
Serial chip select 50 I/O pin(0)
ADC analog 2 input pin
PPG ch.3 output pin(0)
General-purpose I/O port
Serial chip select 51 output pin(0)
ADC analog 3 input pin
PPG ch.4 output pin(0)
General-purpose I/O port
PPG ch.5 output pin(0)
General-purpose I/O port
DAC analog 1 output pin
PPG ch.6 output pin(0)
General-purpose I/O port
DAC analog 0 output pin
PPG ch.7 output pin(0)
INT8 external interrupt input pin(0)
General-purpose I/O port
PPG ch.74 output pin(0)
General-purpose I/O port
PPG ch.75 output pin(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
-
90
106
AD26
-
91
107
AC25
74
92
108
AB24
-
-
-
AA23
-
-
-
AC26
75
93
109
AB25
76
94
110
Y23
-
95
111
AB26
-
-
-
AA25
-
-
-
Y24
77
96
112
W23
78
97
113
AA26
79
98
114
Y25
Pin Name
P190
TIN0_1
P191
TIN1_1
P090
AN4
ICU0_0
TIN2_1
P270
PPG76_0
P271
PPG77_0
P091
AN5
PPG41_1
ICU1_0
TIN3_1
P092
AN6
PPG40_1
ICU2_0
TOT0_1
P192
PPG24_1
TOT1_1
P272
PPG78_0
P273
PPG79_0
P093
TX0(128)_1
SIN11_0
AN7
ICU4_2
PPG16_1
ICU3_0
TOT2_1
P094
AN8
ICU4_0
TOT3_1
P095
TX0(128)_0
SCS11_0
AN9
Polarity
Chapter 1: Overview
-
I/O
circuit
type
A
A
B
A
A
B
B
A
A
A
J
B
B
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Reload timer ch.0 event input pin(1)
General-purpose I/O port
Reload timer ch.1 event input pin(1)
General-purpose I/O port
ADC analog 4 input pin
Input capture ch.0 input pin(0)
Reload timer ch.2 event input pin(1)
General-purpose I/O port
PPG ch.76 output pin(0)
General-purpose I/O port
PPG ch.77 output pin(0)
General-purpose I/O port
ADC analog 5 input pin
PPG ch.41 output pin(1)
Input capture ch.1 input pin(0)
Reload timer ch.3 event input pin(1)
General-purpose I/O port
ADC analog 6 input pin
PPG ch.40 output pin(1)
Input capture ch.2 input pin(0)
Reload timer ch.0 output pin(1)
General-purpose I/O port
PPG ch.24 output pin(1)
Reload timer ch.1 output pin(1)
General-purpose I/O port
PPG ch.78 output pin(0)
General-purpose I/O port
PPG ch.79 output pin(0)
General-purpose I/O port
CAN transmission data 0 output pin(1)
Multi-function serial ch.11 serial data input pin(0)
ADC analog 7 input pin
Input capture ch.4 input pin(2)
PPG ch.16 output pin(1)
Input capture ch.3 input pin(0)
Reload timer ch.2 output pin(1)
General-purpose I/O port
ADC analog 8 input pin
Input capture ch.4 input pin(0)
Reload timer ch.3 output pin(1)
General-purpose I/O port
CAN transmission data 0 output pin(0)
Serial chip select 11 I/O pin(0)
ADC analog 9 input pin
95
Pin Number
144
80
176
99
208
115
PAB
416
V23
81
100
116
Y26
-
-
117
W25
-
-
118
-
119
V25
-
-
-
U24
-
-
-
U25
85
104
123
T25
96
105
124
P096
RX0(128)_0
SOT11_0/SDA11
-
AN10
INT0_0
P097
SCK11_0/SCL11
-
AN11
ICU5_0
PPG17_1
P220
SCK16_0/SCL16
-
ICU10_0
PPG48_1
P221
SOT16_0/SDA16
-
ICU11_0
PPG49_1
P222
SIN16_0
PPG54_0
INT20_0
P275
PPG67_1
P276
TRG16_1
PPG86_1
P100
SCK7_0/SCL7
-
AN12
PPG8_0
P101
SOT7_0/SDA7
-
T23
AN13
PPG9_0
TX3(128)_0
-
I/O
circuit
type
G
G
P
U23
-
86
Pin Name
Polarity
Chapter 1: Overview
P
I
A
A
G
G
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
CAN reception data 0 input pin(0)
Multi-function serial ch.11 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 10 input pin
INT0 external interrupt input pin(0)
General-purpose I/O port
Multi-function serial ch.11 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 11 input pin
Input capture ch.5 input pin(0)
PPG ch.17 output pin(1)
General-purpose I/O port
Multi-function serial ch.16 clock I/O pin(0)/
I2C bus serial clock I/O pin
Input capture ch.10 input pin(0)
PPG ch.48 output pin(1)
General-purpose I/O port
Multi-function serial ch.16 serial data output
pin(0)/I2C bus serial data I/O pin
Input capture ch.11 input pin(0)
PPG ch.49 output pin(1)
General-purpose I/O port
Multi-function serial ch.16 serial data input pin(0)
PPG ch.54 output pin(0)
INT20 external interrupt input pin(0)
General-purpose I/O port
PPG ch.67 output pin(1)
General-purpose I/O port
PPG trigger 16 input pin(1)
PPG ch.86 output pin(1)
General-purpose I/O port
Multi-function serial ch.7 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 12 input pin
PPG ch.8 output pin(0)
General-purpose I/O port
Multi-function serial ch.7 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 13 input pin
PPG ch.9 output pin(0)
CAN transmission data 3 output pin(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
87
106
125
R26
88
107
126
R25
89
108
127
R23
90
109
128
P25
91
110
129
P24
92
111
130
P23
-
112
131
P26
93
113
132
N23
94
114
133
L26
95
115
136
L25
-
-
-
L24
96
116
137
L23
Pin Name
Polarity
Chapter 1: Overview
P102
SIN7_0
AN14
PPG10_0
INT10_0
RX3(128)_0
P103
SCS73_0
AN15
PPG11_0
P104
SCS72_0
AN16
PPG12_0
P105
SCS71_0
AN17
PPG13_0
P106
SCS70_0
AN18
PPG14_0
P107
AN19
PPG15_0
TXENA_1
P193
PPG25_1
P154
AN20
TXDA_1
P155
AN21
RXDA_1
-
NMIX
N
P277
TRG17_1
PPG87_1
P110
TX1(128)_0
SCS63_0
AN22
-
I/O
circuit
type
G
H
H
H
H
U
A
U
S
M
A
B
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Multi-function serial ch.7 serial data input pin(0)
ADC analog 14 input pin
PPG ch.10 output pin(0)
INT10 external interrupt input pin(0)
CAN reception data 3 input pin(0)
General-purpose I/O port
Serial chip select 73 output pin(0)
ADC analog 15 input pin
PPG ch.11 output pin(0)
General-purpose I/O port
Serial chip select 72 output pin(0)
ADC analog 16 input pin
PPG ch.12 output pin(0)
General-purpose I/O port
Serial chip select 71 output pin(0)
ADC analog 17 input pin
PPG ch.13 output pin(0)
General-purpose I/O port
Serial chip select 70 I/O pin(0)
ADC analog 18 input pin
PPG ch.14 output pin(0)
General-purpose I/O port
ADC analog 19 input pin
PPG ch.15 output pin(0)
FlexRay ch.A operation enable output(1)
General-purpose I/O port
PPG ch.25 output pin(1)
General-purpose I/O port
ADC analog 20 input pin
FlexRay ch.A data output(1)
General-purpose I/O port
ADC analog 21 input pin
FlexRay ch.A data input(1)
Non-maskable interrupt input pin
General-purpose I/O port
PPG trigger 17 input pin(1)
PPG ch.87 output pin(1)
General-purpose I/O port
CAN transmission data 1 output pin(0)
Serial chip select 63 output pin(0)
ADC analog 22 input pin
97
Pin Number
144
176
208
PAB
416
97
117
138
J26
98
118
139
K26
99
119
140
K25
-
120
141
H26
-
121
142
J25
-
-
-
G26
-
-
-
H25
100
122
143
K23
101
123
144
F26
102
124
145
G25
98
Pin Name
Polarity
Chapter 1: Overview
P111
RX1(128)_0
SCS62_0
AN23
INT1_0
P112
AN24
PPG16_0
RTO0_0
TXENB_1
P113
AN25
PPG17_0
RTO1_0
TXDB_1
P194
FRCK5_1
PPG26_1
P195
FRCK4_1
PPG27_1
P280
PPG80_0
P281
PPG81_0
P114
SCS61_0
AN26
PPG18_0
RTO2_0
RXDB_1
P115
RX1(128)_1
SOT6_0/SDA6
-
AN27
PPG19_0
RTO3_0
INT1_1
P116
SCK6_0/SCL6
-
AN28
PPG20_0
RTO4_0
-
I/O
circuit
type
G
U
U
A
A
A
A
S
G
G
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
CAN reception data 1 input pin(0)
Serial chip select 62 output pin(0)
ADC analog 23 input pin
INT1 external interrupt input pin(0)
General-purpose I/O port
ADC analog 24 input pin
PPG ch.16 output pin(0)
Waveform generator ch.0 output pin(0)
FlexRay ch.B operation enable output(1)
General-purpose I/O port
ADC analog 25 input pin
PPG ch.17 output pin(0)
Waveform generator ch.1 output pin(0)
FlexRay ch.B data output(1)
General-purpose I/O port
Free-run timer 5 clock input pin(1)
PPG ch.26 output pin(1)
General-purpose I/O port
Free-run timer 4 clock input pin(1)
PPG ch.27 output pin(1)
General-purpose I/O port
PPG ch.80 output pin(0)
General-purpose I/O port
PPG ch.81 output pin(0)
General-purpose I/O port
Serial chip select 61 output pin(0)
ADC analog 26 input pin
PPG ch.18 output pin(0)
Waveform generator ch.2 output pin(0)
FlexRay ch.B data input(1)
General-purpose I/O port
CAN reception data 1 input pin(1)
Multi-function serial ch.6 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 27 input pin
PPG ch.19 output pin(0)
Waveform generator ch.3 output pin(0)
INT1 external interrupt input pin(1)
General-purpose I/O port
Multi-function serial ch.6 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 28 input pin
PPG ch.20 output pin(0)
Waveform generator ch.4 output pin(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
PAB
416
103
125
146
H24
-
126
147
J23
-
-
-
E26
-
-
-
F25
104
127
148
H23
105
128
149
D26
106
129
150
E25
-
-
151
G23
-
-
152
D25
-
-
153
E24
-
130
154
F23
107
131
155
E23
110
134
158
C26
Pin Name
Polarity
Chapter 1: Overview
P117
SCS60_0
AN29
PPG21_0
RTO5_0
P196
FRCK3_1
PPG28_1
P282
PPG82_0
P283
PPG83_0
P120
AN30
OCU6_0
PPG22_0
INT9_0
RX4(128)_0
P121
OCU7_0
PPG23_0
TX4(128)_0
P122
SIN6_0
AN31
OCU8_0
INT9_1
P225
SCK17_0/SCL17
-
PPG55_0
P226
SOT17_0/SDA17
-
PPG56_0
P227
SIN17_0
PPG57_0
INT21_0
P197
PPG29_1
P123
OCU9_0
STOPWT_1
-
DEBUGIF
-
I/O
circuit
type
B
A
A
A
S
A
J
P
P
I
A
R
L
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Serial chip select 60 I/O pin(0)
ADC analog 29 input pin
PPG ch.21 output pin(0)
Waveform generator ch.5 output pin(0)
General-purpose I/O port
Free-run timer 3 clock input pin(1)
PPG ch.28 output pin(1)
General-purpose I/O port
PPG ch.82 output pin(0)
General-purpose I/O port
PPG ch.83 output pin(0)
General-purpose I/O port
ADC analog 30 input pin
Output compare ch.6 output pin(0)
PPG ch.22 output pin(0)
INT9 external interrupt input pin(0)
CAN reception data 4 input pin(0)
General-purpose I/O port
Output compare ch.7 output pin(0)
PPG ch.23 output pin(0)
CAN transmission data 4 output pin(0)
General-purpose I/O port
Multi-function serial ch.6 serial data input pin(0)
ADC analog 31 input pin
Output compare ch.8 output pin(0)
INT9 external interrupt input pin(1)
General-purpose I/O port
Multi-function serial ch.17 clock I/O pin(0)/
I2C bus serial clock I/O pin
PPG ch.55 output pin(0)
General-purpose I/O port
Multi-function serial ch.17 serial data output
pin(0)/I2C bus serial data I/O pin
PPG ch.56 output pin(0)
General-purpose I/O port
Multi-function serial ch.17 serial data input pin(0)
PPG ch.57 output pin(0)
INT21 external interrupt input pin(0)
General-purpose I/O port
PPG ch.29 output pin(1)
General-purpose I/O port
Output compare ch.9 output pin(0)
FlexRay stopwatch input(1)
DEBUGIF I/O pin for debug (OCD)
99
Pin Number
144
176
208
PAB
416
-
-
-
C25
-
-
-
D22
-
135
159
C22
-
136
160
D21
-
-
-
B22
-
-
-
C21
111
137
161
-
-
-
-
D20
112
138
162
-
-
-
-
A22
-
-
163
B21
-
-
164
P284
PPG84_0
P285
PPG85_0
P160
PPG30_1
P161
PPG31_1
P286
TRG18_0
P287
TRG19_0
P124
OCU10_0
TRST
P124
OCU10_0
P125
OCU11_0
TMS
P125
OCU11_0
P230
SCK18_0/SCL18
-
OCU12_0
PPG58_0
P231
SOT18_0/SDA18
-
OCU13_0
PPG59_0
P232
SIN18_0
PPG60_0
INT22_0
P233
SCS18_0
PPG61_0
INT16_1
P290
TRG20_0
PPG64_1
P291
TRG21_0
PPG65_1
-
-
165
D19
-
-
166
C19
-
-
-
D18
-
-
-
B18
I/O
circuit
type
A
A
A
A
A
A
A
A
A
A
P
C20
-
100
Pin Name
Polarity
Chapter 1: Overview
P
I
A
A
A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
PPG ch.84 output pin(0)
General-purpose I/O port
PPG ch.85 output pin(0)
General-purpose I/O port
PPG ch.30 output pin(1)
General-purpose I/O port
PPG ch.31 output pin(1)
General-purpose I/O port
PPG trigger 18 input pin(0)
General-purpose I/O port
PPG trigger 19 input pin(0)
General-purpose I/O port
Output compare ch.10 output pin(0)
JTAG test reset input
General-purpose I/O port
Output compare ch.10 output pin(0)
General-purpose I/O port
Output compare ch.11 output pin(0)
JTAG test mode state input
General-purpose I/O port
Output compare ch.11 output pin(0)
General-purpose I/O port
Multi-function serial ch.18 clock I/O pin(0)/
I2C bus serial clock I/O pin
Output compare ch.12 output pin(0)
PPG ch.58 output pin(0)
General-purpose I/O port
Multi-function serial ch.18 serial data output
pin(0)/I2C bus serial data I/O pin
Output compare ch.13 output pin(0)
PPG ch.59 output pin(0)
General-purpose I/O port
Multi-function serial ch.18 serial data input pin(0)
PPG ch.60 output pin(0)
INT22 external interrupt input pin(0)
General-purpose I/O port
Serial chip select 18 I/O pin(0)
PPG ch.61 output pin(0)
INT16 external interrupt input pin(1)
General-purpose I/O port
PPG trigger 20 input pin(0)
PPG ch.64 output pin(1)
General-purpose I/O port
PPG trigger 21 input pin(0)
PPG ch.65 output pin(1)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
176
208
Pin Name
PAB
416
Polarity
Chapter 1: Overview
P126
SIN0_0
INT6_0
TDI
P126
SIN0_0
INT6_0
P127
SOT0_0
TDO
P127
SOT0_0
P130
SCK0_0
TCK
P130
SCK0_0
P162
TRG5_2
P163
TRG6_2
-
I/O
circuit
type
General-purpose I/O port
Multi-function serial ch.0 serial data input pin(0)
INT6 external interrupt input pin(0)
JTAG test data input
General-purpose I/O port
Multi-function serial ch.0 serial data input pin(0)
INT6 external interrupt input pin(0)
General-purpose I/O port
Multi-function serial ch.0 serial data output pin(0)
JTAG test data output
General-purpose I/O port
Multi-function serial ch.0 serial data output pin(0)
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin(0)
JTAG test clock input
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin(0)
General-purpose I/O port
PPG trigger 5 input pin(2)
General-purpose I/O port
PPG trigger 6 input pin(2)
113
139
167
-
-
-
-
C18
114
140
168
-
-
-
-
C17
115
141
169
-
-
-
-
D17
-
142
170
C16
-
143
171
D16
116
144
172
B23
MD0
-
K
Mode pin 0
117
145
173
A23
MD1
-
K
Mode pin 1
118
146
174
A20
X0
-
N
Main clock oscillation input pin
119
147
175
A19
X1
-
N
Main clock oscillation output pin
-
A
A17
P135
DTTI_0
General-purpose I/O port
Waveform generator ch.0 to ch.5 input pin(0)
X1A
-
O
Sub clock oscillation output pin
P136
-
A
General-purpose I/O port
X0A
-
O
Sub clock oscillation input pin
RSTX
N
M
External reset input pin
P133
TX2(128)_0
P134
RX2(128)_0
SCS1_1
ICU7_0
INT7_0
P000
D16
SIN1_0
TIOA0_1
INT2_0
-
121
122
149
150
177
178
F
Function
(Please refer to the chapter of "I/O port" for
the switch.)
F
A
A
F
F
A
A
A16
123
151
179
B15
126
154
182
D15
127
155
183
D14
131
159
187
A10
A
F
F
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
General-purpose I/O port
CAN transmission data 2 output pin(0)
General-purpose I/O port
CAN reception data 2 input pin(0)
Serial chip select 1 I/O pin(1)
Input capture ch.7 input pin(0)
INT7 external interrupt input pin(0)
General-purpose I/O port
External Bus data bit16 I/O pin
Multi-function serial ch.1 serial data input pin(0)
Base timer ch.0 TIOA output pin(1)
INT2 external interrupt input pin(0)
101
Pin Number
144
176
208
Pin Name
PAB
416
Polarity
Chapter 1: Overview
P001
D17
SOT1_0
TIOA1_1
P002
D18
SCK1_0
TIOB0_1
P003
D19
SIN2_0
TIOB1_1
INT3_0
TXENA_0
P004
D20
SOT2_0
TXDA_0
P164
PPG32_1
P005
D21
SCK2_0
ADTG0_1
INT7_1
RXDA_0
P165
PPG33_1
P006
D22
SCS2_0
ADTG1_1
INT2_1
TXENB_0
P007
D23
TXDB_0
-
I/O
circuit
type
General-purpose I/O port
External Bus data bit17 I/O pin
Multi-function serial ch.1 serial data output pin(0)
Base timer ch.1 TIOA I/O pin(1)
General-purpose I/O port
External Bus data bit18 I/O pin
Multi-function serial ch.1 clock I/O pin(0)
Base timer ch.0 TIOB input pin(1)
General-purpose I/O port
External Bus data bit19 I/O pin
Multi-function serial ch.2 serial data input pin(0)
Base timer ch.1 TIOB input pin(1)
INT3 external interrupt input pin(0)
FlexRay ch.A operation enable output(0)
General-purpose I/O port
External Bus data bit20 I/O pin
Multi-function serial ch.2 serial data output pin(0)
FlexRay ch.A data output(0)
General-purpose I/O port
PPG ch.32 output pin(1)
General-purpose I/O port
External Bus data bit21 I/O pin
Multi-function serial ch.2 clock I/O pin(0)
A/D converter external trigger input pin 0(1)
INT7 external interrupt input pin(1)
FlexRay ch.A data input(0)
General-purpose I/O port
PPG ch.33 output pin(1)
General-purpose I/O port
External Bus data bit22 I/O pin
Serial chip select 2 I/O pin(0)
A/D converter external trigger input pin 1(1)
INT2 external interrupt input pin(1)
FlexRay ch.B operation enable output(0)
General-purpose I/O port
External Bus data bit23 I/O pin
FlexRay ch.B data output(0)
132
160
188
B10
133
161
189
A9
134
162
190
B9
135
163
191
A8
-
164
192
D12
136
165
193
B8
-
166
194
C11
137
167
195
A7
138
168
196
B7
-
-
-
D11
P292
-
A
General-purpose I/O port
-
-
-
C10
P293
-
A
General-purpose I/O port
-
169
197
D10
139
170
198
A6
P166
PPG34_1
P010
D24
RXDB_0
-
102
R
Function
(Please refer to the chapter of "I/O port" for
the switch.)
F
T
R
A
F
A
R
R
A
R
General-purpose I/O port
PPG ch.34 output pin(1)
General-purpose I/O port
External Bus data bit24 I/O pin
FlexRay ch.B data input(0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
-
-
176
-
-
208
199
200
Pin Name
PAB
416
C9
Polarity
Chapter 1: Overview
P234
SCK19_0/SCL19
-
PPG62_0
P235
SOT19_0/SDA19
-
PPG63_0
AIN3_0
P236
SIN19_0
TRG14_0
BIN3_0
INT23_0
P237
SCS19_0
TRG15_0
ZIN3_0
P011
WOT
D25
SOT2_1
TIOA0_0
INT3_1
P012
D26
TIOB0_0
STOPWT_0
P294
PPG86_0
P295
PPG87_0
P167
PPG35_1
-
D9
I/O
circuit
type
P
P
I
Function
(Please refer to the chapter of "I/O port" for
the switch.)
General-purpose I/O port
Multi-function serial ch.19 clock I/O pin(0)/
I2C bus serial clock I/O pin
PPG ch.62 output pin(0)
General-purpose I/O port
Multi-function serial ch.19 serial data output
pin(0)/I2C bus serial data I/O pin
PPG ch.63 output pin(0)
U/D counter ch.3 AIN input pin(0)
General-purpose I/O port
Multi-function serial ch.19 serial data input pin(0)
PPG trigger 14 input pin(0)
U/D counter ch.3 BIN input pin(0)
INT23 external interrupt input pin(0)
General-purpose I/O port
Serial chip select 19 I/O pin(0)
PPG trigger 15 input pin(0)
U/D counter ch.3 ZIN input pin(0)
General-purpose I/O port
RTC output pin
External Bus data bit25 I/O pin
Multi-function serial ch.2 serial data output pin(1)
Base timer ch.0 TIOA output pin(0)
INT3 external interrupt input pin(1)
General-purpose I/O port
External Bus data bit26 I/O pin
Base timer ch.0 TIOB input pin(0)
FlexRay stopwatch input(0)
General-purpose I/O port
PPG ch.86 output pin(0)
General-purpose I/O port
PPG ch.87 output pin(0)
General-purpose I/O port
PPG ch.35 output pin(1)
-
-
201
D8
-
-
202
D7
140
171
203
B6
141
172
204
A5
-
-
-
C6
-
-
-
C5
-
173
205
D6
-
-
-
C4
P296
-
A
General-purpose I/O port
-
-
-
D5
P297
-
A
General-purpose I/O port
142
174
206
B5
143
175
207
A4
P013
D27
TIOA1_0
P014
D28
TIOB1_0
-
40
50
58
AF4
AVCC1
-
-
84
103
122
T26
AVCC0
-
-
A
R
R
A
A
A
R
R
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
General-purpose I/O port
External Bus data bit27 I/O pin
Base timer ch.1 TIOA I/O pin(0)
General-purpose I/O port
External Bus data bit28 I/O pin
Base timer ch.1 TIOB input pin(0)
A/D, D/A converter unit1 analog power supply
pin
A/D, D/A converter unit0 analog power supply
pin
103
Chapter 1: Overview
144
176
208
PAB
416
Polarity
Pin Number
I/O
circuit
type
42
52
60
AF5
AVRH1
-
-
83
102
121
U26
AVRH0
-
-
43
53
61
-
AVSS1/AVRL1
-
-
-
-
-
AF7
AVSS1
-
-
-
-
-
AF6
AVRL1
-
-
82
101
120
-
AVSS0/AVRL0
-
-
-
-
-
W26
AVSS0
-
-
A/D, D/A converter unit0 GND
-
-
-
V26
AVRL0
-
-
A/D converter unit0 lower limit reference voltage
pin
130
158
186
A13
C
-
-
External capacity connection output pin
VCC
-
-
Power supply (1)
VCCE
-
-
Power supply (2)
45
72
109
124
55
88
133
152
63
104
134
157
180
36
128
144
44
156
176
52
184
208
104
AF10
AF11
AE10
AE11
AE24
AF24
N25
N26
A24
B24
A14
B14
M1
M2
AD2
AD1
A11
B11
B3
A3
Pin Name
Function
(Please refer to the chapter of "I/O port" for
the switch.)
A/D converter unit1 upper limit reference voltage
pin
A/D converter unit0 upper limit reference voltage
pin
A/D, D/A converter unit1 GND/
A/D converter unit1 lower limit reference voltage
pin
A/D, D/A converter unit1 GND
A/D converter unit1 lower limit reference voltage
pin
A/D, D/A converter unit0 GND/
A/D converter unit0 lower limit reference voltage
pin
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Pin Number
144
1
37
44
73
108
120
125
129
176
1
45
54
89
132
148
153
157
208
PAB
416
1
53
62
105
135
156
176
181
185
A1
B2
P1
P2
AF1
AE2
AF8
AF9
AE9
AD10
AF26
AE25
M26
M25
A26
B25
A21
A18
B16
A15
A12
B12
Pin Name
VSS
Polarity
Chapter 1: Overview
I/O
circuit
type
-
-
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Function
(Please refer to the chapter of "I/O port" for
the switch.)
GND
105
Chapter 1: Overview
144
-
-
106
176
-
-
208
PAB
416
Polarity
Pin Number
I/O
circuit
type
-
A2,A25
B1,B4
B13,B17
B19,B20
B26
C2,C3
C7,C8
C12,C13
C14,C15
C23,C24
D4,D13
D23,D24
F3,F24
G3,G24
H2,H3
J24
K10-K17
K24
L10-L17
M10-M17
M23,M24
N1-N4
N10-N17
N24
P3,P4
P10-P17
R10-R17
R24
T3
T10-T17
VSS
-
-
GND
-
U3
U10-U17
V24
W3,W24
Y3
AA24
AC3,AC4
AC9,AC23
AD3,AD4
AD7,AD9
AD12,AD13
AD15,AD16
AD18,AD19
AD21,AD22
AD24
AE1,AE26
AF2,AF25
VSS
-
-
GND
Pin Name
Function
(Please refer to the chapter of "I/O port" for
the switch.)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
9.1.
Pins of Each Function
Pins of each function are shown below.
9.1.1.
Pins of A/D Converter (ch.0 to ch.63)
Function
A/D converter external trigger input pin0(1)
A/D converter external trigger input pin1(1)
ADC analog 0 input pin
ADC analog 1 input pin
ADC analog 2 input pin
ADC analog 3 input pin
ADC analog 4 input pin
ADC analog 5 input pin
ADC analog 6 input pin
ADC analog 7 input pin
ADC analog 8 input pin
ADC analog 9 input pin
ADC analog 10 input pin
ADC analog 11 input pin
ADC analog 12 input pin
ADC analog 13 input pin
ADC analog 14 input pin
ADC analog 15 input pin
ADC analog 16 input pin
ADC analog 17 input pin
ADC analog 18 input pin
ADC analog 19 input pin
ADC analog 20 input pin
ADC analog 21 input pin
ADC analog 22 input pin
ADC analog 23 input pin
ADC analog 24 input pin
ADC analog 25 input pin
ADC analog 26 input pin
ADC analog 27 input pin
ADC analog 28 input pin
ADC analog 29 input pin
ADC analog 30 input pin
ADC analog 31 input pin
ADC analog 32 input pin
ADC analog 33 input pin
ADC analog 34 input pin
ADC analog 35 input pin
Pin Number
Pin
Name
Noise
Filter
144
176
208
ADTG0_1
ADTG1_1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
136
137
65
66
67
68
74
75
76
77
78
79
80
81
85
86
87
88
89
90
91
92
93
94
96
97
98
99
100
101
102
103
104
106
63
57
56
55
165
167
81
82
83
84
92
93
94
96
97
98
99
100
104
105
106
107
108
109
110
111
113
114
116
117
118
119
122
123
124
125
127
129
79
71
70
69
193
195
97
98
99
100
108
109
110
112
113
114
115
116
123
124
125
126
127
128
129
130
132
133
137
138
139
140
143
144
145
146
148
150
95
83
82
81
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
B8
A7
AF22
AC19
AC21
AF23
AB24
AB25
Y23
W23
AA26
Y25
V23
Y26
T25
T23
R26
R25
R23
P25
P24
P23
N23
L26
L23
J26
K26
K25
K23
F26
G25
H24
H23
E25
AE20
AF15
AC14
AD14
107
Chapter 1: Overview
Pin
Name
Function
ADC analog 36 input pin
ADC analog 37 input pin
ADC analog 38 input pin
ADC analog 39 input pin
ADC analog 40 input pin
ADC analog 41 input pin
ADC analog 42 input pin
ADC analog 43 input pin
ADC analog 44 input pin
ADC analog 45 input pin
ADC analog 46 input pin
ADC analog 47 input pin
ADC analog 48 input pin
ADC analog 49 input pin
ADC analog 50 input pin
ADC analog 51 input pin
ADC analog 52 input pin
ADC analog 53 input pin
ADC analog 54 input pin
ADC analog 55 input pin
ADC analog 56 input pin
ADC analog 57 input pin
ADC analog 58 input pin
ADC analog 59 input pin
ADC analog 60 input pin
ADC analog 61 input pin
ADC analog 62 input pin
ADC analog 63 input pin
A/D, D/A converter unit1 analog power supply pin
A/D, D/A converter unit0 analog power supply pin
A/D converter unit1 upper limit reference voltage pin
A/D converter unit0 upper limit reference voltage pin
A/D, D/A converter unit1 GND pin/
A/D converter unit1 lower limit reference voltage pin
A/D, D/A converter unit1 GND pin
A/D converter unit1 lower limit reference voltage pin
A/D, D/A converter unit0 GND pin/
A/D converter unit0 lower limit reference voltage pin
A/D, D/A converter unit0 GND pin
A/D converter unit0 lower limit reference voltage pin
108
AN36
AN37
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AN47
AN48
AN49
AN50
AN51
AN52
AN53
AN54
AN55
AN56
AN57
AN58
AN59
AN60
AN61
AN62
AN63
AVCC1
AVCC0
AVRH1
AVRH0
AVSS1/
AVRL1
AVSS1
AVRL1
AVSS0/
AVRL0
AVSS0
AVRL0
Pin Number
Noise
Filter
144
176
208
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
-
53
52
50
49
48
47
41
38
34
30
28
25
40
84
42
83
67
66
62
60
59
58
51
46
42
37
34
31
50
103
52
102
79
78
74
72
71
70
59
54
50
45
38
35
90
89
88
87
68
67
66
65
42
41
40
39
23
22
21
20
58
122
60
121
-
43
53
61
-
-
-
-
-
AF7
AF6
-
82
101
120
-
-
-
-
-
W26
V26
PAB
416
AF14
AC13
AE12
AC11
AD11
AC10
AE5
AF3
AB1
Y1
W1
U2
AF19
AE17
AF17
AF18
AD8
AE7
AC8
AE6
Y4
W4
V4
V3
M4
M3
L4
L3
AF4
T26
AF5
U26
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
9.1.2.
Pins of CAN (ch.0 to ch.5)
Function
CAN reception data 0 input
pin (0)
CAN transmission data 0
output pin (0)
CAN transmission data 0
output pin (1)
CAN reception data 1 input
pin (0)
CAN reception data 1 input
pin (1)
CAN transmission data 1
output pin (0)
CAN reception data 2 input
pin (0)
CAN transmission data 2
output pin (0)
CAN reception data 3 input
pin (0)
CAN transmission data 3
output pin (0)
CAN reception data 4 input
pin (0)
CAN transmission data 4
output pin (0)
CAN reception data 5 input
pin (0)
CAN reception data 5 input
pin (1)
CAN transmission data 5
output pin (0)
CAN transmission data 5
output pin (1)
9.1.3.
Pin Number
Pin Name
Noise
Filter
144
176
208
PAB
416
RX0(128)_0
No
80
99
115
V23
TX0(128)_0
-
79
98
114
Y25
TX0(128)_1
-
77
96
112
W23
RX1(128)_0
No
97
117
138
J26
RX1(128)_1
No
101
123
144
F26
TX1(128)_0
-
96
116
137
L23
RX2(128)_0
No
127
155
183
D14
TX2(128)_0
-
126
154
182
D15
RX3(128)_0
No
87
106
125
R26
TX3(128)_0
-
86
105
124
T23
RX4(128)_0
No
104
127
148
H23
TX4(128)_0
-
105
128
149
D26
RX5(128)_0
No
33
41
49
AA2
RX5(128)_1
No
59
75
91
AE18
TX5(128)_0
-
32
40
48
AA1
TX5(128)_1
-
60
76
92
AD17
Pins of D/A Converter (ch.0, ch.1)
Function
DAC analog 0 output pin
DAC analog 1 output pin
Pin
Name
DAO0
DAO1
Pin Number
Noise
Filter
144
176
208
-
71
70
87
86
103
102
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
AD25
AC22
109
Chapter 1: Overview
9.1.4.
Pins of External Interrupt Input
Function
INT0 external interrupt input pin(0)
INT1 external interrupt input pin(0)
INT1 external interrupt input pin(1)
INT2 external interrupt input pin(0)
INT2 external interrupt input pin(1)
INT3 external interrupt input pin(0)
INT3 external interrupt input pin(1)
INT4 external interrupt input pin(0)
INT4 external interrupt input pin(1)
INT5 external interrupt input pin(0)
INT6 external interrupt input pin(0)
INT7 external interrupt input pin(0)
INT7 external interrupt input pin(1)
INT8 external interrupt input pin(0)
INT9 external interrupt input pin(0)
INT9 external interrupt input pin(1)
INT10 external interrupt input pin(0)
INT11 external interrupt input pin(0)
INT12 external interrupt input pin(0)
INT13 external interrupt input pin(0)
INT13 external interrupt input pin(1)
INT14 external interrupt input pin(0)
INT14 external interrupt input pin(1)
INT15 external interrupt input pin(0)
INT16 external interrupt input pin(0)
INT16 external interrupt input pin(1)
INT17 external interrupt input pin(0)
INT17 external interrupt input pin(1)
INT18 external interrupt input pin(0)
INT19 external interrupt input pin(0)
INT20 external interrupt input pin(0)
INT21 external interrupt input pin(0)
INT22 external interrupt input pin(0)
INT23 external interrupt input pin(0)
9.1.5.
INT0_0
INT1_0
INT1_1
INT2_0
INT2_1
INT3_0
INT3_1
INT4_0
INT4_1
INT5_0
INT6_0
INT7_0
INT7_1
INT8_0
INT9_0
INT9_1
INT10_0
INT11_0
INT12_0
INT13_0
INT13_1
INT14_0
INT14_1
INT15_0
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT19_0
INT20_0
INT21_0
INT22_0
INT23_0
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
80
97
101
131
137
134
140
59
63
56
113
127
136
71
104
106
87
20
24
46
47
33
34
9
-
99
117
123
159
167
162
171
75
79
70
139
155
165
87
127
129
106
24
30
57
58
41
42
11
-
115
138
144
187
195
190
203
91
95
82
167
183
193
103
148
150
125
28
34
69
70
49
50
11
22
166
41
68
67
89
119
153
165
201
PAB
416
V23
J26
F26
A10
A7
B9
B6
AE18
AE20
AC14
C18
D14
B8
AD25
H23
E25
R26
R1
U1
AE8
AC10
AA2
AB1
G1
M3
C19
W4
AD8
AE7
AE17
V25
E24
D19
D8
Pins of Multi-function Serial Interface (ch.0 to ch.19)
Function
MFS ch.0 clock I/O pin(0)
MFS ch.0 clock I/O pin(1)
110
Pin
Name
Pin
Name
SCK0_0
SCK0_1
Pin Number
Noise
Filter
144
176
208
No
No
115
34
141
42
169
50
PAB
416
D17
AB1
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
MFS ch.0 serial data output pin(0)
MFS ch.0 serial data output pin(1)
MFS ch.0 serial data input pin(0)
MFS ch.0 serial data input pin(1)
MFS ch.1 clock I/O pin(0)
MFS ch.1 serial data output pin(0)
MFS ch.1 serial data input pin(0)
MFS ch.2 clock I/O pin(0)
MFS ch.2serial data output pin(0)
MFS ch.2serial data output pin(1)
MFS ch.2serial data input pin(0)
MFS ch.3 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.3 clock I/O pin(1)
MFS ch.3 clock I/O pin(2)
MFS ch.3 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.3 serial data output pin(1)
MFS ch.3 serial data output pin(2)
MFS ch.3 serial data input pin(0)
MFS ch.3 serial data input pin(1)
MFS ch.4 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.4 clock I/O pin(1)
MFS ch.4 clock I/O pin(2)
MFS ch.4 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.4 serial data output pin(1)
MFS ch.4 serial data output pin(2)
MFS ch.4 serial data input pin(0)
MFS ch.4 serial data input pin(1)
MFS ch.5 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.5 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.5 serial data input pin(0)
MFS ch.6 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.6 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.6 serial data input pin(0)
MFS ch.7 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.7 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.7 serial data input pin(0)
Pin
Name
SOT0_0
SOT0_1
SIN0_0
SIN0_1
SCK1_0
SOT1_0
SIN1_0
SCK2_0
SOT2_0
SOT2_1
SIN2_0
SCK3_0/
SCL3
SCK3_1
SCK3_2
SOT3_0/
SDA3
SOT3_1
SOT3_2
SIN3_0
SIN3_1
SCK4_0/
SCL4
SCK4_1
SCK4_2
SOT4_0/
SDA4
SOT4_1
SOT4_2
SIN4_0
SIN4_1
SCK5_0/
SCL5
SOT5_0/
SDA5
SIN5_0
SCK6_0/
SCL6
SOT6_0/
SDA6
SIN6_0
SCK7_0/
SCL7
SOT7_0/
SDA7
SIN7_0
Pin Number
Noise
Filter
144
176
208
No
No
No
No
No
No
114
30
113
23
133
132
131
136
135
140
134
140
37
139
29
161
160
159
165
163
171
162
168
45
167
33
189
188
187
193
191
203
190
PAB
416
C17
Y1
C18
T2
A9
B10
A10
B8
A8
B6
B9
No
61
77
93
AF20
No
No
7
16
9
20
9
24
F1
L1
No
60
76
92
AD17
No
No
6
17
59
5
8
21
75
7
8
25
91
7
E2
L2
AE18
E1
No
58
74
86
AC16
No
No
11
55
14
69
14
81
H1
AD14
-
57
71
83
AF15
No
No
10
52
56
9
12
66
70
11
12
78
82
11
G2
AC13
AC14
G1
No
63
79
95
AE20
-
65
81
97
AF22
No
66
82
98
AC19
No
102
124
145
G25
-
101
123
144
F26
No
106
129
150
E25
No
85
104
123
T25
-
86
105
124
T23
No
87
106
125
R26
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
111
Chapter 1: Overview
Function
MFS ch.8 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.8 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.8 serial data input pin(0)
MFS ch.9 clock I/O pin(0)
MFS ch.9 serial data output pin(0)
MFS ch.9 serial data input pin(0)
MFS ch.10 clock I/O pin(1)
MFS ch.10 serial data output pin(1)
MFS ch.10 serial data input pin(0)
MFS ch.11 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.11 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.11 serial data input pin(0)
MFS ch.12 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.12 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.12 serial data input pin(0)
MFS ch.13 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.13 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.13 serial data input pin(0)
MFS ch.14 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.14 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.14 serial data input pin(0)
MFS ch.15 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.15 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.15 serial data input pin(0)
MFS ch.16 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.16 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.16 serial data input pin(0)
MFS ch.17 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.17 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.17 serial data input pin(0)
112
Pin
Name
SCK8_0/
SCL8
SOT8_0/
SDA8
SIN8_0
SCK9_0
SOT9_0
SIN9_0
SCK10_1
SOT10_1
SIN10_0
SCK11_0/
SCL11
SOT11_0/
SDA11
SIN11_0
SCK12_0/
SCL12
SOT12_0/
SDA12
SIN12_0
SCK13_0/
SCL13
SOT13_0/
SDA13
SIN13_0
SCK14_0/
SCL14
SOT14_0/
SDA14
SIN14_0
SCK15_0/
SCL15
SOT15_0/
SDA15
SIN15_0
SCK16_0/
SCL16
SOT16_0/
SDA16
SIN16_0
SCK17_0/
SCL17
SOT17_0/
SDA17
SIN17_0
Pin Number
Noise
Filter
144
176
208
PAB
416
No
19
23
27
R4
-
18
22
26
R3
No
No
No
No
No
20
28
25
24
41
47
38
24
34
31
30
51
58
46
28
38
35
34
59
70
54
R1
W1
U2
U1
AE5
AC10
AF3
No
81
100
116
Y26
-
80
99
115
V23
No
77
96
112
W23
No
-
-
20
L3
-
-
-
21
L4
No
-
-
22
M3
No
-
-
39
V3
-
-
-
40
V4
No
-
-
41
W4
No
-
-
65
AE6
-
-
-
66
AC8
No
-
-
67
AE7
No
-
-
87
AF18
-
-
-
88
AF17
No
-
-
89
AE17
No
-
-
117
W25
-
-
-
118
U23
No
-
-
119
V25
No
-
-
151
G23
-
-
-
152
D25
No
-
-
153
E24
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
MFS ch.18 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.18 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.18 serial data input pin(0)
MFS ch.19 clock I/O pin(0)/
I2C bus serial clock I/O pin
MFS ch.19 serial data output pin(0)/
I2C bus serial data I/O pin
MFS ch.19 serial data input pin(0)
Serial chip select 1 I/O pin(1)
Serial chip select 2 I/O pin(0)
Serial chip select 3 I/O pin(0)
Serial chip select 3 I/O pin(1)
Serial chip select 40 I/O pin(0)
Serial chip select 40 I/O pin(1)
Serial chip select 41 output pin(0)
Serial chip select 41 output pin(1)
Serial chip select 42 output pin(0)
Serial chip select 42 output pin(1)
Serial chip select 43 output pin(0)
Serial chip select 43 output pin(1)
Serial chip select 50 I/O pin(0)
Serial chip select 51 output pin(0)
Serial chip select 52 output pin(0)
Serial chip select 53 output pin(0)
Serial chip select 60 I/O pin(0)
Serial chip select 61 output pin(0)
Serial chip select 62 output pin(0)
Serial chip select 63 output pin(0)
Serial chip select 70 I/O pin(0)
Serial chip select 71 output pin(0)
Serial chip select 72 output pin(0)
Serial chip select 73 output pin(0)
Serial chip select 8 I/O pin(0)
Serial chip select 9 I/O pin(0)
Serial chip select 10 I/O pin(0)
Serial chip select 10 I/O pin(1)
Serial chip select 11 I/O pin(0)
Serial chip select 12 I/O pin(0)
Serial chip select 13 I/O pin(0)
Serial chip select 14 I/O pin(0)
Serial chip select 15 I/O pin(0)
Serial chip select 18 I/O pin(0)
Serial chip select 19 I/O pin(0)
Pin
Name
SCK18_0/
SCL18
SOT18_0/
SDA18
SIN18_0
SCK19_0/
SCL19
SOT19_0/
SDA19
SIN19_0
SCS1_1
SCS2_0
SCS3_0
SCS3_1
SCS40_0
SCS40_1
SCS41_0
SCS41_1
SCS42_0
SCS42_1
SCS43_0
SCS43_1
SCS50_0
SCS51_0
SCS52_0
SCS53_0
SCS60_0
SCS61_0
SCS62_0
SCS63_0
SCS70_0
SCS71_0
SCS72_0
SCS73_0
SCS8_0
SCS9_0
SCS10_0
SCS10_1
SCS11_0
SCS12_0
SCS13_0
SCS14_0
SCS15_0
SCS18_0
SCS19_0
Pin Number
Noise
Filter
144
176
208
PAB
416
No
-
-
163
B21
-
-
-
164
C20
No
-
-
165
D19
No
-
-
199
C9
-
-
-
200
D9
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
127
137
52
8
48
12
49
13
50
14
51
15
67
68
64
62
103
100
97
96
91
90
89
88
21
27
46
48
79
-
155
167
66
10
59
15
60
17
62
18
63
19
83
84
80
78
125
122
117
116
110
109
108
107
25
33
57
59
98
-
201
183
195
78
10
71
15
72
17
74
18
75
19
99
100
96
94
146
143
138
137
129
128
127
126
29
37
69
71
114
23
42
68
90
166
202
D8
D14
A7
AC13
F2
AD11
J1
AC11
J2
AE12
K1
AC12
K2
AC21
AF23
AC18
AF21
H24
K23
J26
L23
P24
P25
R23
R25
R2
V2
AE8
AD11
Y25
M4
Y4
AD8
AF19
C19
D7
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
113
Chapter 1: Overview
9.1.6.
Pins of PPG (ch.0 to ch.87)
Function
PPG ch.0 output pin(0)
PPG ch.0 output pin(1)
PPG ch.1 output pin(0)
PPG ch.1 output pin(1)
PPG ch.2 output pin(0)
PPG ch.2 output pin(1)
PPG ch.3 output pin(0)
PPG ch.3 output pin(1)
PPG ch.4 output pin(0)
PPG ch.4 output pin(1)
PPG ch.5 output pin(0)
PPG ch.5 output pin(1)
PPG ch.6 output pin(0)
PPG ch.7 output pin(0)
PPG ch.8 output pin(0)
PPG ch.9 output pin(0)
PPG ch.10 output pin(0)
PPG ch.11 output pin(0)
PPG ch.12 output pin(0)
PPG ch.13 output pin(0)
PPG ch.14 output pin(0)
PPG ch.15 output pin(0)
PPG ch.16 output pin(0)
PPG ch.16 output pin(1)
PPG ch.17 output pin(0)
PPG ch.17 output pin(1)
PPG ch.18 output pin(0)
PPG ch.19 output pin(0)
PPG ch.20 output pin(0)
PPG ch.21 output pin(0)
PPG ch.22 output pin(0)
PPG ch.23 output pin(0)
PPG ch.23 output pin(1)
PPG ch.24 output pin(0)
PPG ch.24 output pin(1)
PPG ch.25 output pin(0)
PPG ch.25 output pin(1)
PPG ch.26 output pin(0)
PPG ch.26 output pin(1)
114
Pin
Name
PPG0_0
PPG0_1
PPG1_0
PPG1_1
PPG2_0
PPG2_1
PPG3_0
PPG3_1
PPG4_0
PPG4_1
PPG5_0
PPG5_1
PPG6_0
PPG7_0
PPG8_0
PPG9_0
PPG10_0
PPG11_0
PPG12_0
PPG13_0
PPG14_0
PPG15_0
PPG16_0
PPG16_1
PPG17_0
PPG17_1
PPG18_0
PPG19_0
PPG20_0
PPG21_0
PPG22_0
PPG23_0
PPG23_1
PPG24_0
PPG24_1
PPG25_0
PPG25_1
PPG26_0
PPG26_1
Pin Number
Noise
Filter
144
176
208
-
64
39
65
41
66
46
67
47
68
48
69
49
70
71
85
86
87
88
89
90
91
92
98
77
99
81
100
101
102
103
104
105
23
9
10
11
-
80
49
81
51
82
57
83
58
84
59
85
60
86
87
104
105
106
107
108
109
110
111
118
96
119
100
122
123
124
125
127
128
29
11
95
12
112
14
120
96
57
97
59
98
69
99
70
100
71
101
72
102
103
123
124
125
126
127
128
129
130
139
112
140
116
143
144
145
146
148
149
33
11
111
12
131
14
141
PAB
416
AC18
AE3
AF22
AE5
AC19
AE8
AC21
AC10
AF23
AD11
AD23
AC11
AC22
AD25
T25
T23
R26
R25
R23
P25
P24
P23
K26
W23
K25
Y26
K23
F26
G25
H24
H23
D26
T2
G1
AB26
G2
P26
H1
H26
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
PPG ch.27 output pin(0)
PPG ch.27 output pin(1)
PPG ch.28 output pin(0)
PPG ch.28 output pin(1)
PPG ch.29 output pin(0)
PPG ch.29 output pin(1)
PPG ch.30 output pin(0)
PPG ch.30 output pin(1)
PPG ch.31 output pin(0)
PPG ch.31 output pin(1)
PPG ch.32 output pin(0)
PPG ch.32 output pin(1)
PPG ch.33 output pin(0)
PPG ch.33 output pin(1)
PPG ch.34 output pin(0)
PPG ch.34 output pin(1)
PPG ch.35 output pin(0)
PPG ch.35 output pin(1)
PPG ch.36 output pin(0)
PPG ch.36 output pin(1)
PPG ch.37 output pin(0)
PPG ch.37 output pin(1)
PPG ch.38 output pin(1)
PPG ch.39 output pin(1)
PPG ch.40 output pin(0)
PPG ch.40 output pin(1)
PPG ch.41 output pin(0)
PPG ch.41 output pin(1)
PPG ch.42 output pin(0)
PPG ch.43 output pin(0)
PPG ch.43 output pin(1)
PPG ch.44 output pin(0)
PPG ch.44 output pin(1)
PPG ch.45 output pin(0)
PPG ch.46 output pin(0)
PPG ch.47 output pin(0)
PPG ch.48 output pin(0)
PPG ch.48 output pin(1)
PPG ch.49 output pin(0)
PPG ch.49 output pin(1)
PPG ch.50 output pin(0)
Pin
Name
PPG27_0
PPG27_1
PPG28_0
PPG28_1
PPG29_0
PPG29_1
PPG30_0
PPG30_1
PPG31_0
PPG31_1
PPG32_0
PPG32_1
PPG33_0
PPG33_1
PPG34_0
PPG34_1
PPG35_0
PPG35_1
PPG36_0
PPG36_1
PPG37_0
PPG37_1
PPG38_1
PPG39_1
PPG40_0
PPG40_1
PPG41_0
PPG41_1
PPG42_0
PPG43_0
PPG43_1
PPG44_0
PPG44_1
PPG45_0
PPG46_0
PPG47_0
PPG48_0
PPG48_1
PPG49_0
PPG49_1
PPG50_0
Pin Number
Noise
Filter
144
176
208
-
12
13
14
15
16
8
31
33
34
35
38
76
75
50
51
-
15
121
17
126
18
130
19
135
20
136
10
164
39
166
41
169
42
173
43
4
46
6
13
16
47
94
48
93
56
61
62
64
63
65
72
73
-
15
142
17
147
18
154
19
159
24
160
10
192
47
194
49
197
50
205
51
4
54
6
13
16
55
110
56
109
64
73
74
76
75
77
84
85
39
117
40
118
65
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
J1
J25
J2
J23
K1
F23
K2
C22
L1
D21
F2
D12
Y2
C11
AA2
D10
AB1
D6
AB2
E3
AF3
F4
K3
K4
AC5
Y23
AC6
AB25
AC7
AF12
AE12
AF13
AC12
AE13
AF16
AE16
V3
W25
V4
U23
AE6
115
Chapter 1: Overview
Function
PPG ch.51 output pin(0)
PPG ch.52 output pin(0)
PPG ch.53 output pin(0)
PPG ch.54 output pin(0)
PPG ch.55 output pin(0)
PPG ch.56 output pin(0)
PPG ch.57 output pin(0)
PPG ch.58 output pin(0)
PPG ch.59 output pin(0)
PPG ch.60 output pin(0)
PPG ch.61 output pin(0)
PPG ch.62 output pin(0)
PPG ch.63 output pin(0)
PPG ch.64 output pin(0)
PPG ch.64 output pin(1)
PPG ch.65 output pin(0)
PPG ch.65 output pin(1)
PPG ch.66 output pin(0)
PPG ch.66 output pin(1)
PPG ch.67 output pin(0)
PPG ch.67 output pin(1)
PPG ch.68 output pin(0)
PPG ch.69 output pin(0)
PPG ch.70 output pin(0)
PPG ch.71 output pin(0)
PPG ch.72 output pin(0)
PPG ch.73 output pin(0)
PPG ch.74 output pin(0)
PPG ch.75 output pin(0)
PPG ch.76 output pin(0)
PPG ch.77 output pin(0)
PPG ch.78 output pin(0)
PPG ch.79 output pin(0)
PPG ch.80 output pin(0)
PPG ch.81 output pin(0)
PPG ch.82 output pin(0)
PPG ch.83 output pin(0)
PPG ch.84 output pin(0)
PPG ch.85 output pin(0)
PPG ch.86 output pin(0)
PPG ch.86 output pin(1)
116
Pin
Name
PPG51_0
PPG52_0
PPG53_0
PPG54_0
PPG55_0
PPG56_0
PPG57_0
PPG58_0
PPG59_0
PPG60_0
PPG61_0
PPG62_0
PPG63_0
PPG64_0
PPG64_1
PPG65_0
PPG65_1
PPG66_0
PPG66_1
PPG67_0
PPG67_1
PPG68_0
PPG69_0
PPG70_0
PPG71_0
PPG72_0
PPG73_0
PPG74_0
PPG75_0
PPG76_0
PPG77_0
PPG78_0
PPG79_0
PPG80_0
PPG81_0
PPG82_0
PPG83_0
PPG84_0
PPG85_0
PPG86_0
PPG86_1
Pin Number
Noise
Filter
144
176
208
-
-
-
66
87
88
119
151
152
153
163
164
165
166
199
200
-
PAB
416
AC8
AF18
AF17
V25
G23
D25
E24
B21
C20
D19
C19
C9
D9
J3
D18
J4
B18
AB3
AD6
AB4
U24
AE4
AD5
AE15
AC15
AE19
AC17
AC24
AB23
AA23
AC26
AA25
Y24
G26
H25
E26
F25
C25
D22
C6
U25
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
PPG ch.87 output pin(0)
PPG ch.87 output pin(1)
PPG trigger 0 input pin(0)
PPG trigger 0 input pin(1)
PPG trigger 0 input pin(2)
PPG trigger 1 input pin(0)
PPG trigger 1 input pin(1)
PPG trigger 2 input pin(0)
PPG trigger 2 input pin(1)
PPG trigger 3 input pin(0)
PPG trigger 3 input pin(1)
PPG trigger 4 input pin(0)
PPG trigger 4 input pin(1)
PPG trigger 5 input pin(0)
PPG trigger 5 input pin(1)
PPG trigger 5 input pin(2)
PPG trigger 6 input pin(0)
PPG trigger 6 input pin(1)
PPG trigger 6 input pin(2)
PPG trigger 7 input pin(0)
PPG trigger 7 input pin(1)
PPG trigger 8 input pin(0)
PPG trigger 8 input pin(1)
PPG trigger 9 input pin(0)
PPG trigger 9 input pin(1)
PPG trigger 10 input pin(0)
PPG trigger 11 input pin(0)
PPG trigger 12 input pin(0)
PPG trigger 12 input pin(1)
PPG trigger 13 input pin(0)
PPG trigger 13 input pin(1)
PPG trigger 14 input pin(0)
PPG trigger 15 input pin(0)
PPG trigger 16 input pin(0)
PPG trigger 16 input pin(1)
PPG trigger 17 input pin(0)
PPG trigger 17 input pin(1)
PPG trigger 18 input pin(0)
PPG trigger 19 input pin(0)
PPG trigger 20 input pin(0)
PPG trigger 21 input pin(0)
Pin Number
Pin
Name
Noise
Filter
144
176
208
PPG87_0
PPG87_1
TRG0_0
TRG0_1
TRG0_2
TRG1_0
TRG1_1
TRG2_0
TRG2_1
TRG3_0
TRG3_1
TRG4_0
TRG4_1
TRG5_0
TRG5_1
TRG5_2
TRG6_0
TRG6_1
TRG6_2
TRG7_0
TRG7_1
TRG8_0
TRG8_1
TRG9_0
TRG9_1
TRG10_0
TRG11_0
TRG12_0
TRG12_1
TRG13_0
TRG13_1
TRG14_0
TRG15_0
TRG16_0
TRG16_1
TRG17_0
TRG17_1
TRG18_0
TRG19_0
TRG20_0
TRG21_0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
25
41
3
26
4
27
5
28
6
29
7
31
18
6
19
7
30
32
-
2
31
51
3
32
5
33
7
34
8
35
9
39
142
22
8
143
23
9
37
27
40
28
36
38
-
2
35
59
3
36
5
37
7
38
8
43
9
47
170
26
8
171
27
9
45
31
48
32
44
46
20
89
21
90
201
202
-
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
C5
L24
C1
U2
AE5
D1
V1
D2
V2
E1
W1
E2
W2
F1
Y2
C16
R3
E2
D16
R4
F1
Y1
T4
AA1
U4
AA3
AA4
L3
AE17
L4
AF19
D8
D7
G4
U25
H4
L24
B22
C21
D18
B18
117
Chapter 1: Overview
9.1.7.
Pin of RTC
Function
RTC output signal pin
9.1.8.
WOT
Pin Number
Noise
Filter
144
176
208
PAB
416
-
140
171
203
B6
Pins of Up/down Counter
Function
U/D counter ch.0 AIN input pin(0)
U/D counter ch.0 AIN input pin(1)
U/D counter ch.0 BIN input pin(0)
U/D counter ch.0 BIN input pin(1)
U/D counter ch.0 ZIN input pin(0)
U/D counter ch.0 ZIN input pin(1)
U/D counter ch.0 ZIN input pin(2)
U/D counter ch.1 AIN input pin(0)
U/D counter ch.1 AIN input pin(1)
U/D counter ch.1 BIN input pin(0)
U/D counter ch.1 BIN input pin(1)
U/D counter ch.1 ZIN input pin(0)
U/D counter ch.1 ZIN input pin(1)
U/D counter ch.2 AIN input pin(0)
U/D counter ch.2 AIN input pin(1)
U/D counter ch.2 BIN input pin(0)
U/D counter ch.2 BIN input pin(1)
U/D counter ch.2 ZIN input pin(0)
U/D counter ch.2 ZIN input pin(1)
U/D counter ch.3 AIN input pin(0)
U/D counter ch.3 BIN input pin(0)
U/D counter ch.3 ZIN input pin(0)
118
Pin
Name
Pin
Name
AIN0_0
AIN0_1
BIN0_0
BIN0_1
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
BIN1_0
BIN1_1
ZIN1_0
ZIN1_1
AIN2_0
AIN2_1
BIN2_0
BIN2_1
ZIN2_0
ZIN2_1
AIN3_0
BIN3_0
ZIN3_0
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
20
53
21
52
22
51
19
23
50
24
49
25
48
-
24
67
25
66
26
63
23
29
62
30
60
31
59
-
28
79
29
78
30
75
27
33
74
34
72
35
71
40
65
41
66
42
67
200
201
202
PAB
416
R1
AF14
R2
AC13
T1
AC12
R4
T2
AE12
U1
AC11
U2
AD11
V4
AE6
W4
AC8
Y4
AE7
D9
D8
D7
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
9.1.9.
Pins of Output Compare (ch.0 to ch.5: 16bit, ch.6 to
ch.13: 32bit)
Function
Pin
Name
Pin Number
Noise
Filter
PAB
416
Output compare ch.6 output pin(0)
OCU6_0
104
127
148
H23
Output compare ch.6 output pin(1)
OCU6_1
22
26
30
T1
Output compare ch.7 output pin(0)
OCU7_0
105
128
149
D26
Output compare ch.7 output pin(1)
OCU7_1
21
25
29
R2
Output compare ch.8 output pin(0)
OCU8_0
106
129
150
E25
Output compare ch.8 output pin(1)
OCU8_1
20
24
28
R1
Output compare ch.9 output pin(0)
OCU9_0
107
131
155
E23
Output compare ch.9 output pin(1)
OCU9_1
19
23
27
R4
Output compare ch.10 output pin(0)
OCU10_0
111
137
161
D20
Output compare ch.10 output pin(1)
OCU10_1
18
22
26
R3
Output compare ch.11 output pin(0)
OCU11_0
112
138
162
A22
Output compare ch.11 output pin(1)
OCU11_1
17
21
25
L2
Output compare ch.12 output pin(0)
OCU12_0
163
B21
Output compare ch.13 output pin(0)
OCU13_0
164
C20
(Note) 16-bit output compare has no dedicated output pins. There is only the output through the wave generator.
9.1.10.
144
176
208
Pins of Input Capture (ch.0 to ch.3: 16bit, ch.4 to ch.11:
32bit)
Function
Input capture ch.0 input pin(0)
Input capture ch.0 input pin(1)
Input capture ch.0 input pin(2)
Input capture ch.0 input pin(3)
Input capture ch.1 input pin(0)
Input capture ch.1 input pin(1)
Input capture ch.1 input pin(2)
Input capture ch.1 input pin(3)
Input capture ch.2 input pin(0)
Input capture ch.2 input pin(1)
Input capture ch.2 input pin(2)
Input capture ch.2 input pin(3)
Input capture ch.3 input pin(0)
Input capture ch.3 input pin(1)
Pin
Name
ICU0_0
ICU0_1
ICU0_2
ICU0_3
ICU1_0
ICU1_1
ICU1_2
ICU1_3
ICU2_0
ICU2_1
ICU2_2
ICU2_3
ICU3_0
ICU3_1
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
74
39
54
19
75
41
55
18
76
46
56
17
77
47
92
49
68
23
93
51
69
22
94
57
70
21
96
58
108
57
80
27
109
59
81
26
110
69
82
25
112
70
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
AB24
AE3
AE14
R4
AB25
AE5
AD14
R3
Y23
AE8
AC14
L2
W23
AC10
119
Chapter 1: Overview
Pin
Name
Function
Input capture ch.3 input pin(2)
Input capture ch.3 input pin(3)
Input capture ch.4 input pin(0)
Input capture ch.4 input pin(1)
Input capture ch.4 input pin(2)
Input capture ch.5 input pin(0)
Input capture ch.5 input pin(1)
Input capture ch.6 input pin(0)
Input capture ch.6 input pin(1)
Input capture ch.7 input pin(0)
Input capture ch.7 input pin(1)
Input capture ch.8 input pin(0)
Input capture ch.8 input pin(1)
Input capture ch.9 input pin(0)
Input capture ch.9 input pin(1)
Input capture ch.10 input pin(0)
Input capture ch.11 input pin(0)
9.1.11.
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
57
16
78
29
77
81
28
47
27
127
26
41
25
39
24
-
71
20
97
35
96
100
34
58
33
155
32
51
31
49
30
-
83
24
113
43
112
116
38
70
37
183
36
59
35
57
34
117
118
ICU3_2
ICU3_3
ICU4_0
ICU4_1
ICU4_2
ICU5_0
ICU5_1
ICU6_0
ICU6_1
ICU7_0
ICU7_1
ICU8_0
ICU8_1
ICU9_0
ICU9_1
ICU10_0
ICU11_0
PAB
416
AF15
L1
AA26
W2
W23
Y26
W1
AC10
V2
D14
V1
AE5
U2
AE3
U1
W25
U23
Pins of Free-run Timer (ch.0 to ch.2: 16bit, ch.3 to ch.10:
32bit)
Function
Free-run timer 0 clock input pin(0)
Free-run timer 1 clock input pin(0)
Free-run timer 1 clock input pin(1)
Free-run timer 2 clock input pin(0)
Free-run timer 3 clock input pin(0)
Free-run timer 3 clock input pin(1)
Free-run timer 4 clock input pin(0)
Free-run timer 4 clock input pin(1)
Free-run timer 5 clock input pin(0)
Free-run timer 5 clock input pin(1)
Free-run timer 6 clock input pin(0)
Free-run timer 7 clock input pin(0)
Free-run timer 8 clock input pin(0)
Free-run timer 9 clock input pin(0)
Free-run timer 10 clock input pin(0)
120
Pin Number
Noise
Filter
Pin Number
Pin
Name
Noise
Filter
144
176
208
FRCK0_0
FRCK1_0
FRCK1_1
FRCK2_0
FRCK3_0
FRCK3_1
FRCK4_0
FRCK4_1
FRCK5_0
FRCK5_1
FRCK6_0
FRCK7_0
FRCK8_0
FRCK9_0
FRCK10_0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
48
49
63
50
51
52
53
-
59
60
79
62
63
126
66
121
67
120
-
71
72
95
74
75
147
78
142
79
141
67
68
88
89
90
PAB
416
AD11
AC11
AE20
AE12
AC12
J23
AC13
J25
AF14
H26
AE7
AD8
AF17
AE17
AF19
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
9.1.12.
Pins of Base Timer (ch.0, ch.1)
Function
Base timer ch.0 TIOA output pin(0)
Base timer ch.0 TIOA output pin(1)
Base timer ch.0 TIOB input pin (0)
Base timer ch.0 TIOB input pin (1)
Base timer ch.1 TIOA I/O pin (0)
Base timer ch.1 TIOA I/O pin (1)
Base timer ch.1 TIOB input pin (0)
Base timer ch.1 TIOB input pin (1)
9.1.13.
Pin
Name
TIOA0_0
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_0
TIOA1_1
TIOB1_0
TIOB1_1
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
140
131
141
133
142
132
143
134
171
159
172
161
174
160
175
162
203
187
204
189
206
188
207
190
PAB
416
B6
A10
A5
A9
B5
B10
A4
B9
Pins of Reload Timer (ch.0 to ch.7)
Function
Reload timer ch.0 output pin(0)
Reload timer ch.0 output pin(1)
Reload timer ch.0 event input pin(0)
Reload timer ch.0 event input pin(1)
Reload timer ch.0 event input pin(2)
Reload timer ch.1 output pin(0)
Reload timer ch.1 output pin(1)
Reload timer ch.1 output pin(2)
Reload timer ch.1 event input pin(0)
Reload timer ch.1 event input pin(1)
Reload timer ch.2 output pin(0)
Reload timer ch.2 output pin(1)
Reload timer ch.2 event input pin(0)
Reload timer ch.2 event input pin(1)
Reload timer ch.3 output pin(0)
Reload timer ch.3 output pin(1)
Reload timer ch.3 event input pin(0)
Reload timer ch.3 event input pin(1)
Reload timer ch.3 event input pin(2)
Reload timer ch.4 output pin(0)
Reload timer ch.4 event input pin(0)
Reload timer ch.4 event input pin(1)
Reload timer ch.5 output pin(0)
Reload timer ch.5 output pin(1)
Pin
Name
TOT0_0
TOT0_1
TIN0_0
TIN0_1
TIN0_2
TOT1_0
TOT1_1
TOT1_2
TIN1_0
TIN1_1
TOT2_0
TOT2_1
TIN2_0
TIN2_1
TOT3_0
TOT3_1
TIN3_0
TIN3_1
TIN3_2
TOT4_0
TIN4_0
TIN4_1
TOT5_0
TOT5_1
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
12
76
8
5
13
28
9
14
77
10
74
15
78
11
75
30
20
16
38
21
46
15
94
10
90
7
17
95
34
11
91
18
96
12
92
19
97
14
93
37
24
20
46
25
57
15
110
10
106
7
17
111
38
11
107
18
112
12
108
19
113
14
109
45
28
24
54
29
69
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
J1
Y23
F2
AD26
E1
J2
AB26
W1
G1
AC25
K1
W23
G2
AB24
K2
AA26
H1
AB25
Y1
R1
L1
AF3
R2
AE8
121
Chapter 1: Overview
Function
Reload timer ch.5 event input pin(0)
Reload timer ch.5 event input pin(1)
Reload timer ch.6 output pin(0)
Reload timer ch.6 output pin(1)
Reload timer ch.6 event input pin(0)
Reload timer ch.6 event input pin(1)
Reload timer ch.7 output pin(0)
Reload timer ch.7 output pin(1)
Reload timer ch.7 event input pin(0)
9.1.14.
TIN5_0
TIN5_1
TOT6_0
TOT6_1
TIN6_0
TIN6_1
TOT7_0
TOT7_1
TIN7_0
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
17
39
22
47
18
41
23
48
19
21
49
26
58
22
51
29
59
23
25
57
30
70
26
59
33
71
27
PAB
416
L2
AE3
T1
AC10
R3
AE5
T2
AD11
R4
Pins of External Bus Interface
Function
External bus address bit0 output pin
External bus address bit1 output pin
External bus address bit2 output pin
External bus address bit3 output pin
External bus address bit4 output pin
External bus address bit5 output pin
External bus address bit6 output pin
External bus address bit7 output pin
External bus address bit8 output pin
External bus address bit9 output pin
External bus address bit10 output pin
External bus address bit11 output pin
External bus address bit12 output pin
External bus address bit13 output pin
External bus address bit14 output pin
External bus address bit15 output pin
External bus address bit16 output pin
External bus address bit17 output pin
External bus address bit18 output pin
External bus address bit19 output pin
External bus address bit20 output pin
External bus address bit21 output pin
External bus address strobe output pin
External bus system clock output pin
External bus chip select 0 output pin
122
Pin
Name
Pin
Name
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
ASX
SYSCLK
CS0X
Pin Number
Noise
Filter
144
176
208
-
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
5
35
6
14
15
17
18
19
20
21
24
25
26
29
30
31
32
33
34
35
37
39
40
41
42
7
43
8
14
15
17
18
19
24
25
28
29
30
33
34
35
36
37
38
43
45
47
48
49
50
7
51
8
PAB
416
H1
J1
J2
K1
K2
L1
L2
R1
R2
T1
T2
U1
U2
V1
V2
W1
W2
Y1
Y2
AA1
AA2
AB1
E1
AB2
E2
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
External bus chip select 1 output pin
External bus chip select 2 output pin
External bus chip select 3 output pin
External bus data bit16 I/O pin
External bus data bit17 I/O pin
External bus data bit18 I/O pin
External bus data bit19 I/O pin
External bus data bit20 I/O pin
External bus data bit21 I/O pin
External bus data bit22 I/O pin
External bus data bit23 I/O pin
External bus data bit24 I/O pin
External bus data bit25 I/O pin
External bus data bit26 I/O pin
External bus data bit27 I/O pin
External bus data bit28 I/O pin
External bus data bit29 I/O pin
External bus data bit30 I/O pin
External bus data bit31 I/O pin
External bus write strobe 0 output pin
External bus write strobe 1 output pin
External bus read strobe output pin
External bus RDY input pin (0)
External bus RDY input pin (1)
9.1.15.
Pin
Name
CS1X
CS2X
CS3X
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
WR0X
WR1X
RDX
RDY_0
RDY_1
Pin Number
Noise
Filter
144
176
208
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
7
38
39
131
132
133
134
135
136
137
138
139
140
141
142
143
2
3
4
9
10
8
41
18
9
46
49
159
160
161
162
163
165
167
168
170
171
172
174
175
2
3
5
11
12
10
51
22
9
54
57
187
188
189
190
191
193
195
196
198
203
204
206
207
2
3
5
11
12
10
59
26
PAB
416
F1
AF3
AE3
A10
B10
A9
B9
A8
B8
A7
B7
A6
B6
A5
B5
A4
C1
D1
D2
G1
G2
F2
AE5
R3
Pins of Waveform Generator (ch.0 to ch.5)
Function
Pin Name
Pin Number
Noise
Filter
144
176
208
PAB
416
DTTI_0
Waveform generator ch.0-ch.5 input pin(0)
(Unavailable with
sub oscillation)
Yes
121
149
177
A17
Waveform generator ch.0-ch.5 input pin(1)
Waveform generator ch.0-ch.5 input pin(2)
Waveform generator ch.0 output pin(0)
Waveform generator ch.0 output pin(1)
Waveform generator ch.1 output pin(0)
Waveform generator ch.1 output pin(1)
Waveform generator ch.2 output pin(0)
DTTI_1
DTTI_2
RTO0_0
RTO0_1
RTO1_0
RTO1_1
RTO2_0
Yes
Yes
-
19
39
98
17
99
16
100
23
49
118
21
119
20
122
27
57
139
25
140
24
143
R4
AE3
K26
L2
K25
L1
K23
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
123
Chapter 1: Overview
Function
Pin Name
Waveform generator ch.2 output pin(1)
Waveform generator ch.3 output pin(0)
Waveform generator ch.3 output pin(1)
Waveform generator ch.4 output pin(0)
Waveform generator ch.4 output pin(1)
Waveform generator ch.5 output pin(0)
Waveform generator ch.5 output pin(1)
9.1.16.
Clock monitor output pin
176
208
-
15
101
12
102
9
103
5
19
123
15
124
11
125
7
19
144
15
145
11
146
7
RTO2_1
RTO3_0
RTO3_1
RTO4_0
RTO4_1
RTO5_0
RTO5_1
PAB
416
K2
F26
J1
G25
G1
H24
E1
Pin Number
Pin
Name
Noise
Filter
144
176
208
PAB
416
MONCLK
-
55
69
81
AD14
Pins of FlexRay (1 Unit ch.A, ch.B)
Function
FlexRay ch.A data input(0)
FlexRay ch.A data input(1)
FlexRay ch.A data output(0)
FlexRay ch.A data output(1)
FlexRay ch.A operation enable output(0)
FlexRay ch.A operation enable output(1)
FlexRay ch.B data input(0)
FlexRay ch.B data input(1)
FlexRay ch.B data output(0)
FlexRay ch.B data output(1)
FlexRay ch.B operation enable output(0)
FlexRay ch.B operation enable output(1)
FlexRay stopwatch input(0)
FlexRay stopwatch input(1)
124
144
Pin of Clock Monitor
Function
9.1.17.
Pin Number
Noise
Filter
Pin Number
Pin Name
Noise
Filter
144
176
208
RXDA_0
RXDA_1
TXDA_0
TXDA_1
TXENA_0
TXENA_1
RXDB_0
RXDB_1
TXDB_0
TXDB_1
TXENB_0
TXENB_1
STOPWT_0
STOPWT_1
No
No
No
No
Yes
Yes
136
94
135
93
134
92
139
100
138
99
137
98
141
107
165
114
163
113
162
111
170
122
168
119
167
118
172
131
193
133
191
132
190
130
198
143
196
140
195
139
204
155
PAB
416
B8
L26
A8
N23
B9
P23
A6
K23
B7
K25
A7
K26
A5
E23
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
9.1.18.
Pins of JTAG
Function
JTAG test clock input
JTAG test data input
Pin
Name
TCK
TDI
Noise
Filter
No
No
JTAG test data output
TDO
-
JTAG test mode state input
TMS
No
JTAG test reset input
TRST
No
9.1.19.
Pin Number
144
176
208
115
141
169
PAB
416
-
-
-
-
AC20
113
139
167
-
-
-
-
AD20
114
140
168
-
-
-
-
AE21
112
138
162
-
-
-
-
AE23
111
137
161
-
-
-
-
AE22
Pins of Port Function (General-Purpose I/O)
Function
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
Pin Name
P000
P001
P002
P003
P004
P005
P006
P007
P010
P011
P012
P013
P014
P015
P016
P017
P020
P021
P022
P023
P024
P025
P026
P027
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
131
132
133
134
135
136
137
138
139
140
141
142
143
2
3
4
5
6
7
8
9
10
11
12
159
160
161
162
163
165
167
168
170
171
172
174
175
2
3
5
7
8
9
10
11
12
14
15
187
188
189
190
191
193
195
196
198
203
204
206
207
2
3
5
7
8
9
10
11
12
14
15
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
A10
B10
A9
B9
A8
B8
A7
B7
A6
B6
A5
B5
A4
C1
D1
D2
E1
E2
F1
F2
G1
G2
H1
J1
125
Chapter 1: Overview
Function
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
126
Pin Name
P030
P031
P032
P033
P034
P035
P036
P037
P040
P041
P042
P043
P044
P045
P046
P047
P050
P051
P052
P053
P054
P055
P056
P057
P060
P061
P062
P063
P064
P065
P066
P067
P070
P071
P072
P073
P074
P075
P076
P077
P080
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
13
14
15
16
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
38
39
41
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
64
17
18
19
20
21
24
25
26
29
30
31
32
33
34
35
37
39
40
41
42
43
46
49
51
57
58
59
60
62
63
66
67
68
69
70
71
74
75
76
77
80
17
18
19
24
25
28
29
30
33
34
35
36
37
38
43
45
47
48
49
50
51
54
57
59
69
70
71
72
74
75
78
79
80
81
82
83
86
91
92
93
96
PAB
416
J2
K1
K2
L1
L2
R1
R2
T1
T2
U1
U2
V1
V2
W1
W2
Y1
Y2
AA1
AA2
AB1
AB2
AF3
AE3
AE5
AE8
AC10
AD11
AC11
AE12
AC12
AC13
AF14
AE14
AD14
AC14
AF15
AC16
AE18
AD17
AF20
AC18
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
Pin Name
P081
P082
P083
P084
P085
P086
P087
P090
P091
P092
P093
P094
P095
P096
P097
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P114
P115
P116
P117
P120
P121
P122
P123
P124
P125
P126
P127
P130
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
65
66
67
68
69
70
71
74
75
76
77
78
79
80
81
85
86
87
88
89
90
91
92
96
97
98
99
100
101
102
103
104
105
106
107
111
112
113
114
115
81
82
83
84
85
86
87
92
93
94
96
97
98
99
100
104
105
106
107
108
109
110
111
116
117
118
119
122
123
124
125
127
128
129
131
137
138
139
140
141
97
98
99
100
101
102
103
108
109
110
112
113
114
115
116
123
124
125
126
127
128
129
130
137
138
139
140
143
144
145
146
148
149
150
155
161
162
167
168
169
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
AF22
AC19
AC21
AF23
AD23
AC22
AD25
AB24
AB25
Y23
W23
AA26
Y25
V23
Y26
T25
T23
R26
R25
R23
P25
P24
P23
L23
J26
K26
K25
K23
F26
G25
H24
H23
D26
E25
E23
D20
A22
C18
C17
D17
127
Chapter 1: Overview
Function
Pin Name
Pin Number
Noise
Filter
144
176
208
General-purpose I/O port
General-purpose I/O port
P133
P134
P135
Yes
Yes
126
127
154
155
182
183
PAB
416
D15
D14
General-purpose I/O port
(Only without
sub oscillation)
Yes
121
149
177
A17
P136
128
General-purpose I/O port
(Only without
sub oscillation)
Yes
122
150
178
A16
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
P150
P151
P152
P153
P154
P155
P160
P161
P162
P163
P164
P165
P166
P167
P170
P171
P172
P173
P174
P175
P176
P177
P180
P181
P182
P183
P184
P185
P186
P187
P190
P191
P192
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
18
19
62
63
93
94
-
22
23
78
79
113
114
135
136
142
143
164
166
169
173
4
6
13
16
27
28
36
38
47
48
56
61
64
65
72
73
90
91
95
26
27
94
95
132
133
159
160
170
171
192
194
197
205
4
6
13
16
31
32
44
46
55
56
64
73
76
77
84
85
106
107
111
R3
R4
AF21
AE20
N23
L26
C22
D21
C16
D16
D12
C11
D10
D6
E3
F4
K3
K4
T4
U4
AA3
AA4
AC5
AC6
AC7
AF12
AF13
AE13
AF16
AE16
AD26
AC25
AB26
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Function
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
Pin Name
P193
P194
P195
P196
P197
P200
P201
P202
P203
P204
P205
P206
P207
P210
P211
P212
P213
P214
P215
P216
P217
P220
P221
P222
P225
P226
P227
P230
P231
P232
P233
P234
P235
P236
P237
P240
P241
P242
P243
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
112
120
121
126
130
-
131
141
142
147
154
20
21
22
23
39
40
41
42
65
66
67
68
87
88
89
90
117
118
119
151
152
153
163
164
165
166
199
200
201
202
-
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
PAB
416
P26
H26
J25
J23
F23
L3
L4
M3
M4
V3
V4
W4
Y4
AE6
AC8
AE7
AD8
AF18
AF17
AE17
AF19
W25
U23
V25
G23
D25
E24
B21
C20
D19
C19
C9
D9
D8
D7
D3
E4
G4
H4
129
Chapter 1: Overview
Function
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
130
Pin Name
P244
P245
P250
P251
P252
P253
P254
P255
P256
P262
P263
P264
P265
P266
P267
P270
P271
P272
P273
P275
P276
P277
P280
P281
P282
P283
P284
P285
P286
P287
P290
P291
P292
P293
P294
P295
P296
P297
Pin Number
Noise
Filter
144
176
208
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
PAB
416
J3
J4
AB3
AB4
AC1
AC2
AE4
AD5
AD6
AE15
AC15
AE19
AC17
AC24
AB23
AA23
AC26
AA25
Y24
U24
U25
L24
G26
H25
E26
F25
C25
D22
B22
C21
D18
B18
D11
C10
C6
C5
C4
D5
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
9.1.20.
Other Pins
Pin
Name
Main clock oscillation input pin
Main clock oscillation output
pin
Sub clock oscillation input pin
Sub clock oscillation output pin
Mode pin 0
Mode pin 1
Interrupt input pin without
mask
DEBUGIF I/O pin for debug
(OCD)
External reset input pin
External capacity connection
output pin
Power supply (1)
Power supply (2)
Pin Number
Noise
Filter
144
176
208
X0
Yes
118
146
174
PAB
416
A20
X1
-
119
147
175
A19
X0A
X1A
MD0
MD1
Yes
-
122
121
116
117
150
149
144
145
178
177
172
173
A16
A17
B23
A23
NMIX
Yes
95
115
136
L25
DEBUGIF
Yes
110
134
158
C26
RSTX
Yes
123
151
179
B15
-
130
158
186
A13
-
45
55
63
-
-
-
-
-
72
88
104
-
-
-
134
-
109
133
157
-
124
152
180
-
-
-
-
-
36
44
52
-
128
156
184
-
144
176
208
Function
C
VCC
VCCE
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
AF10,
AF11
AE10,
AE11
AE24,
AF24
N25,
N26
A24,
B24
A14,
B14
M1,
M2
AD2,
AD1
A11,
B11
B3,
A3
131
Chapter 1: Overview
Function
GND
GND
132
Pin
Name
VSS
VSS
Pin Number
Noise
Filter
144
176
208
-
1
1
1
-
-
-
-
-
37
45
53
-
44
54
62
-
-
-
-
-
73
89
105
-
-
-
135
-
108
132
156
-
120
148
176
A21,
A18
-
125
153
181
B16,
A15
-
129
157
185
A12,
B12
-
A2,A25
B1,B4,
B13B17,
B19,B20
B26
C2,C3
C7,C8
C12-C15
C23,C24
D4,D13
D23,D24
F3,F24
G3,G24
H2,H3
J24
K10-K17,K24
L10-L17
M10-M17
M23,M24
N1-N4
N10-N17,N24
P3,P4
P10-P17
R10-R17,R24
-
-
-
PAB
416
A1,
B2
P1,
P2
AF1,
AE2
AF8,
AF9
AE9,
AD10
AF26,
AE25
M26,
M25
A26,
B25
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Pin
Name
Function
GND
VSS
Noise
Filter
Pin Number
144
-
-
176
208
PAB
416
-
T3,T10-T17,
T24
U3,U10-U17
V24
W3,W24
Y3
AA24
AC3,AC4
AC9,AC23
AD3,AD4
AD7,AD9
AD12,AD13
AD15,AD16
AD18,AD19
AD21,AD22
AD24
AE1,AE26
AF2,AF25
-
10. I/O Circuit Types
This section shows I/O Circuit Types.
Figure 10-1 I/O Circuit Types
Type
Circuit
A
Pull-up control
Digital output
Remarks
- General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- Automotive input
Digital output
Automotive input
Standby control
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
133
Chapter 1: Overview
Type
B
Circuit
Pull-up control
Digital output
Remarks
- Analog input, General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- Automotive input
Digital output
Automotive input
Standby control
Analog input
C
Pull-up control
Digital output
Digital output
- DAC output, General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- Automotive input
Automotive input
Standby control
DAC output
D
Pull-up control
Digital output
- I2C Analog input, General-purpose I/O port
- Output 3mA
- Pull-up resistor control 50kΩ
- I2C hysteresis input
Digital output
I2C input
Standby control
Analog input
E
Pull-up control
Digital output
- I2C,General-purpose I/O port
- Output 3mA
- Pull-up resistor control 50kΩ
- I2C hysteresis input
Digital output
I2C input
Standby control
134
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Type
F
Circuit
Pull-up control
Digital output
Remarks
- General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
Digital output
CMOS-hys input
Standby control
G
Pull-up control
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
Digital output
CMOS-hys input
Standby control
Analog input
H
Pull-up control
Digital output
- Analog input, General-purpose I/O port
- Output 12mA
- Pull-up resistor control 50kΩ
- Automotive input
Digital output
Automotive input
Standby control
Analog input
I
Digital output
- General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Digital output
CMOS-hys input
Standby control
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
135
Chapter 1: Overview
Type
Circuit
Remarks
J
- Analog input, General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Digital output
Digital output
CMOS-hys input
Standby control
Analog input
- Mode I/O
- CMOS hysteresis input
K
Mode input
Control
L
- Open-drain I/O
- Output 25mA (Nch open drain)
- TTL input
Digital output
TTL input
M
- Hysteresis input
- Pull-up resistor 50k
CMOS-hys input
N
Input
- Main oscillation I/O
Standby control
136
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Type
O
Circuit
Remarks
Input
- Sub oscillation I/O
Standby control
P
Pull-up control
Digital output
Digital output
- General-purpose I/O port
- Output 4mA
- Output 3mA (Nch open drain)
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
CMOS-hys input
Standby control
Q
Pull-up control
Digital output
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Output 3mA (Nch open drain)
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
CMOS-hys input
Standby control
Analog input
R
Pull-up control
Digital output
Digital output
- General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- Automotive input
- CMOS hysteresis input
Automotive input
Standby control
CMOS-hys input
Standby control
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
137
Chapter 1: Overview
Type
S
Circuit
Pull-up control
Digital output
Digital output
Remarks
- Analog input, General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- Automotive input
- CMOS hysteresis input
Automotive input
Standby control
CMOS-hys input
Standby control
Analog input
T
Pull-up control
Digital output
Digital output
- General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
CMOS-hys input
Standby control
U
Pull-up control
Digital output
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- Automotive input
Automotive input
Standby control
Analog input
V
- CMOS hysteresis input
CMOS-hys input
Standby control
138
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 1: Overview
Type
Circuit
W
Remarks
- Output 4mA
Digital output
Digital output
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
139
Chapter 2: Handling The Device
This chapter explains the notes on using this series.
1.
Handling Precautions
2.
Handling Device
3.
Application Notes
Code : HANDLING-1v1-91528-3-E
140
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 2: Handling The Device
1. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by
the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes
precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress
semiconductor devices.
1.1.
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum rating. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges
may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their sales representative
beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply
and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage
or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large
current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins
should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large
current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called
latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause
injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to
abnormal noise, surge levels, etc.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
141
Chapter 2: Handling The Device
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the
design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely high
levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle
operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before
such use. The company will not be responsible for damages arising from such use without prior approval.
1.2.
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount
conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering
on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and
using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually
causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting
processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to
contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket
contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more
easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased
susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a
ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
142
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 2: Handling The Device
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5 °C and 30 °C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,
with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress
recommended conditions for baking.
Condition: 125 °C /24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the
following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on
the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock
loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
1.3.
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity
levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In
such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect
the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the
devices.
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Chapter 2: Handling The Device
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances.
If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
2. Handling Device
This section explains the handling device.
Notes on Handling Device
This section explains the latch-up prevention and pin processing.
For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the
ratings is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power
supply current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage
from exceeding the maximum ratings in device application.
Also, the analog power supply (AVcc, AVRH) and analog input must not be exceed the digital power supply (Vcc)
when the power supply to the analog system is turned on or off.
In the correct power-on sequence in the microcontroller, turn on the digital power supply (Vcc) and analog power
supplies (AVcc, AVRH), simultaneously. Or, turn on the digital power supply (Vcc5), and then turn on analog power
supplies (AVcc, AVRH).
Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up.
Connect a 2kΩ resistor or more to each of unused pins for pull-up or pill-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state
and treated in the same way as for the input pins.
Power supply pins
The device is designed to prevent latch-up or other malfunctions by interconnecting VCC or VSS pins that should be
kept at the same potential when the drive has multiple VCC or VSS pins. Be sure to connect all of these pins to an
external power supply and ground to reduce unwanted radiation, prevent strobe signal malfunctioning due to a raised
ground level, be in compliance with the total output current standard, etc. As shown in Figure 2-1, all Vss power
supply pins must be treated in the same way. If multiple Vcc or Vss systems are connected, the device cannot operate
correctly even within the guaranteed operating range.
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Figure 2-1 Power Supply Input Pins
Vcc
Vss
Vss
Vss
Ｖ
ｓ
ｓ
Ｖ
ｃ
ｃ
Vcc
Ｖ
ｓ
ｓ
Vcc
Ｖ
ｃ
ｃ
Vss
The power supply pins should be connected to VCC and VSS of this device at the low impedance from the power
supply source.
We recommend using a ceramic capacitor with a capacitance exceeding that of the C pin as a bypass capacitor
between the VCC and VSS pins, in areas close to this device.
Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to
lay out X0 and X1 pins, crystal resonator (or ceramic resonator), and the bypass capacitor to be grounded to the close
position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins with ground circuits.
Mode pins (MD1, MD0)
Connect the MD1and MD0 mode pins to the VCC or VSS pin directly. To prevent an erroneous selection of test mode
caused by the noise, reduce the pattern length between each mode pin and VCC or VSS pin on the printed circuit
board. Also, use the low-impedance pin connection.
During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, the voltage rising must be monotonic
during power-on.
Note during PLL clock operation
If the oscillator is disconnected or input stopped when the PLL clock has been selected, this clock may continue to
operate at the free running frequency of the self oscillator circuit built in the PLL clock. This operation is not
guaranteed.
Treatment of A/D converter power supply pins
Connect the pins to have AVcc=AVRH=Vcc and AVss/AVRL=Vss even if the A/D converter is not used.
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External clock is not supported
None of the external direct clock input can be used for both main clock and sub clock.
Power-on sequence of A/D converter power supplies and analog inputs
Be sure to turn on the digital power supply (Vcc) first, and then turn on the A/D converter power supplies (AVcc,
AVRH, AVRL) and analog inputs (AN0 to AN63). Also, turn off the A/D converter power supplies and analog inputs
first, and then turn off the digital power supply (Vcc). When the AVRH is turned on or off, it must not exceed AVcc.
Even if a common analog input pin is used as an input port, its input voltage must not exceed AVcc. (However, the
analog power supply and digital power supply can be turned on or off simultaneously.)
Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the
internal stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the
latest data sheet.
Note:
For the detailed specifications of operating voltages, see the latest data sheet.
3. Application Notes
This section explains application notes.
3.1 Function Switching of a Multiplexed Port
3.2 Low-power Consumption Mode
3.3 Notes When Writing Data in a Register that Includes the Status Flag
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3.1.
Function Switching of a Multiplexed Port
Function switching of a multiplexed port is shown.
To switch between the PORT function and the multiplexed pin function, use the PFR (port function register).
However, if a multiplexed pin is also used as an external bus, its function is switched by the external bus setting. For
details, see "Chapter: I/O Ports".
3.2.
Low-power Consumption Mode
This section explains low-power consumption mode.
To transit to the sleep mode, watch mode, stop mode, watch mode(power-shutdown) or stop mode(power-shutdown),
follow the procedure explained in the "Activating the sleep mode, watch mode, or stop mode" or the "Activating the
watch mode (power-shutdown) or stop mode(power-shutdown)" of "Chapter: Power Consumption Control".
Take the following notes when using a monitor debugger.
• Do not set a break point when the low-power consumption transition program operate.
• Do not execute an operation step when the low-power consumption transition program operate.
3.3.
Notes When Writing Data in a Register that Includes the
Status Flag
This section explains notes when writing data in a register that includes the status flag.
When writing data in a register that has a status flag (especially, an interrupt request flag) to control a function, it is
important that care be taken to avoid erroneously clearing the status flag.
In other words, exercise caution when writing data so that the flag is not cleared for the status bit and the control bits
have the desired value.
Especially, since the bit instruction cannot be used when the control bits are configured using multiple bits (the bit
instruction can access a single bit only), data is written to the control bits and status flag simultaneously via Byte,
Half-word, or Word access. However, during this time, take care not to erroneously clear any other non-targeted bits
(in this case, the status flag bits).
Note:
With the bit instruction, there is no need to exercise caution because it takes this point into account.
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Chapter 3: CPU
This chapter explains the CPU.
1.
Overview
2.
Features
3.
CPU Operating Description
4.
Pipeline Operation
5.
Floating Point Operation Processing
6.
Data Structure
7.
Addressing
8.
Programming Model
9.
Reset and EIT Processing
10.
Memory Protection Function (MPU)
Code : FR81S10-1v1-91528-2-E
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1. Overview
This section explains the overview of the CPU.
The FR81 architecture is a microcontroller architecture that uses the FR family instruction set with improved floating
point functionality, memory protection functionality and on-chip debugging functionality.
The integer family instruction set is compatible with the FR80 series.
For details, see "FR Family FR81 32-bit Microcontroller Programming Manual".
2. Features
This section explains features of the CPU.
The FR family is a CPU core for 32-bit RISC-based controllers equipped with a custom Cypress architecture. In
particular, this architecture is optimal as the CPU core in microcontrollers designed for embedded control applications
that require high-speed control.
General
General-purpose register architecture (32-bit × 16)
32-bit address space (4GB)
16-bit fixed instruction length (excluding immediate data transfer instructions)
High-speed processing of basic instructions at one instruction per cycle using a 5-stage pipeline architecture
32-bit × 32-bit multiplication instruction that completes in 5 cycles
32-bit/32-bit division instruction by stepped division
Direct addressing instructions for accessing peripherals
High-speed interrupt processing that finishes in six cycles
Single precision floating point arithmetic instructions
Floating point register 32-bit 16
Privilege mode and user mode
FPU, instruction access, and data access exception functions
FPU exceptions
Instruction access protection violation exception
Data access protection violation exception
Illegal instruction exception (changed from undefined instruction exception)
Data access error exception
Non-existent FPU exception
Memory Protection Function (MPU)
Eight protection areas can be specified common to instructions and data
The protection areas are determined in a fixed order of precedence.(The areas can overlap)
Areas are specified by a page address and a page size
Page size: Can be specified as 2n bytes from 16 bytes
Page address: Misaligned address also supported
The following access privileges are controlled using privilege mode and user mode
Instruction fetch (execution) permitted / forbidden
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Chapter 3: CPU
Read permitted / forbidden
Write permitted / forbidden
The following attributes can be specified for each area
Bufferable/Non-Bufferable
Access privileges and attributes can be specified for unset areas
On protection violation, an instruction access protection violation exception or data access protection violation
exception occurs
Floating Point Operations
IEEE754 compliant
Support single precision
Six exception sources are supported.
Underflow
Overflow
Division-by-zero
Invalid operation
Inexact
Inputs an denormalized number
The only rounding mode supported is nearest value
Denormalized numbers are truncated to 0 or generate an exception
Floating-point register: 32-bit × 16 sets
Multiply and Add, Multiply and Sub instructions supported
Division and square root operations supported
3. CPU Operating Description
This section explains the operation of the CPU.
3.1 CPU Operating Status
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Chapter 3: CPU
3.1.
CPU Operating Status
The CPU operating status is shown below.
The CPU operation state includes the following states: reset state, normal run state, low-power consumption state, and
debug run state.
The operating state transitions are shown below.
Figure 3-1 CPU Operating State Transition Diagram
Reset state
DSU directive
ICE not connected
DSU directive
Reset
Privilege mode
Privilege mode
Break
DSU directive
RETI
EIT
RETI
User mode
User mode
Normal Run State
Debug state
EIT
RETI
User State
Debug Run State
EIT
EIT
Low-power consumption mode
transition sequence execution
Low-power consumption mode
transition sequence execution
Low-power
consumption
state
3.1.1.
Reset State
The reset state is shown below.
The reset state is the state when the CPU is being reset. Resets consist of two levels: initialize level and reset level.
When an initialize level reset is issued, everything in the chip is initialized. For the reset level, others exclusive of the
debug control functions, clocks, and reset control functions are initialized.
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3.1.2.
Normal Run State
The normal run state is shown below.
The normal run state is the state when sequential instruction and EIT processing are executed. The normal run state
has privilege mode and user mode.
In user mode, there are restrictions on instructions and access destination, and there are instructions and access
destinations that can only be executed in privilege mode. When the CPU enters the normal run state after reset is
released, the CPU enters privilege mode, and changes to user mode when RETI is executed. The transition from user
mode to privilege mode in the normal run state is triggered by reset or the EIT execution, and transition from
privilege mode to user mode is triggered by the RETI execution.
3.1.3.
Low-power Consumption State
The low-power consumption state is shown below.
The low-power consumption state is the state when the CPU is stopped to reduce the power consumption. The
transition to the low-power consumption state is carried out by the standby control of the clock control unit. The
low-power consumption state has three modes: sleep, stop and watch mode. Recovery from the low-power
consumption state is carried out by interrupts.
3.1.4.
Debug Run State
The debug run state is shown below.
The debug run state is the state when the CPU is connected to ICE and debug related functions are enabled. The
debug run state has two states: a user state and a debug state. The transition between the debug run state and other
states is basically carried via the reset state. However, the transition from the normal run state to the debug run state
forcefully is also enabled.
The user state has a privilege mode and a user mode as the normal run state. However, when a break for debugging is
carried out, the state changes to the debug state. In the debug state, instructions are executed in a privilege mode and
all registers and memory can be accessed under the state when the memory protection function, etc. is disabled. The
transition from a debug state to a user state is carried by the RETI instruction.
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4. Pipeline Operation
This section explains the pipeline operation of the CPU.
In FR81, the common pipeline processing is carried out by the decode stage, and there are two types of pipelines such
as an integer pipeline and a floating point pipeline from the execution stage. Although the completion between each
pipeline processing differs from the sequence of instruction issuances, the processing results based on the program
sequence are guaranteed.
For details, see "FR Family FR81 32-bit Microcontroller Programming Manual".
5. Floating Point Operation Processing
The floating point operation processing for the CPU is shown.
This series incorporates FPU.
For details, see "FR Family FR81 32-bit Microcontroller Programming Manual".
6. Data Structure
This section explains the data structure of the CPU.
The data types which can be handled with FR81 family CPU are the integer type, which can be handled with FR80
family or earlier, and the single precision floating point type.
For the integer type, little endian as the bit ordering and big endian as the byte ordering are used.
For details, see "FR Family FR81 32-bit Microcontroller Programming Manual".
7. Addressing
This section explains addressing of the CPU.
A memory space is 32-bit linear.
The CPU manages the address space in bytes. Specify a value of 32-bit for the address on the address space to access
from the CPU. Figure 7-1 shows the address space.
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Chapter 3: CPU
Figure 7-1 Memory Map
0x0000 0000
Byte
data
0x0000 0100
Direct addressing
area
Half-word data
0x0000 0200
Word data
0x0000 0400
--
TBR
--
20-bit
Addressing area
Vector table
0x000F FC00
0x0010 0000
--
--
32-bit
Addressing area
0xFFFF FFFF
The address space is also called memory space. The address space is the CPU-based logical address space. Address
conversion is not performed. The CPU-based logical address is same as the physical address where memory and I/O
are actually located.
For details, see "FR Family FR81 32-bit Microcontroller Programming Manual".
8. Programming Model
This section explains the programming model of the CPU.
The CPU of FR81 has general-purpose registers, dedicated registers, and floating point registers. Besides these
registers, the FR81 core has address-mapped system registers.
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Chapter 3: CPU
8.1.
General-purpose Registers, Dedicated Registers, and
Floating Point Registers
This section explains general-purpose registers, dedicated registers, and floating point registers.
Figure 8-1 shows the initial values for this series. For details of each register, see "FR Family FR81 32-bit
Microcontroller Programming Manual".
Figure 8-1 Initial Values of General-purpose Registers, Dedicated Registers, and Floating Point
Registers
Configuration and initial values of
general-purpose registers
Configuration and initial values of
dedicated registers
32 bit
32 bit
[Initial value]
[Initial value]
R0
XXXX XXXX H
R1
XXXX XXXX H
R2
XXXX XXXX H
R3
XXXX XXXX H
R4
XXXX XXXX H
R5
XXXX XXXX H
R6
XXXX XXXX H
R7
XXXX XXXX H
R8
XXXX XXXX H
R9
XXXX XXXX H
R10
XXXX XXXX H
R11
XXXX XXXX H
R12
XXXX XXXX H
R13
ACAC
XXXX XXXX H
R14
FP
XXXX XXXX H
R15
SP
0000 0000 H
Program counter
PC
XXXX XXXX H
Program status
PS
SSR=0011
SCR=XX0
B H
B H
ILM=01111
CCR=XX00XXXX
B H
B H
Table base register
Return pointer
TBR
RP
000F FC00 H
XXXX XXXX H
System stack pointer
SSP
0000 0000 H
User stack pointer
USP
XXXX XXXX H
Multiplication and
division result register
MDH
XXXX XXXX H
MDL
XXXX XXXX H
BP
XXXX XXXX H
FPU control register
FCR
XXXX XXXX H
Exception status register
ESR
0000 0000 H
Base pointer
Configuration and initial values of
floating point registers
32 bit
[Initial value]
FR0
XXXX XXXX H
FR1
XXXX XXXX H
FR2
XXXX XXXX H
FR3
XXXX XXXX H
FR4
XXXX XXXX H
FR5
XXXX XXXX H
FR6
XXXX XXXX H
FR7
XXXX XXXX H
FR8
XXXX XXXX H
FR9
XXXX XXXX H
FR10
XXXX XXXX H
FR11
XXXX XXXX H
FR12
XXXX XXXX H
FR13
XXXX XXXX H
FR14
XXXX XXXX H
FR15
XXXX XXXX H
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8.2.
System Register
The system register is shown below.
System register is an address mapping register for controlling system. These registers can be accessed only in the
privilege mode. There are system registers as follows.
Clock control-related register
Reset control-related register
Debug control-related register
Memory protection-related register
DMA-related register
Watchdog timer register
Wildregister control register
FLASH control register
TimingProtectionUnit register
When these registers are written and/or read in the user mode, the illegal instruction exception (data access error)
occurs.
The access protection to system registers is judged on a priority bases than the memory protection function. Therefore,
when user access to the system register area is enabled in the memory protection function and access is disabled in the
privilege mode, those settings are disabled. Read and/or write is enabled only in the privilege mode and read and/or
write is disabled in the user mode.
9. Reset and EIT Processing
This section explains reset and EIT processing.
Reset and EIT processing is the processing that is carried out by other than normal programs when Reset, Exception,
Interrupt and Trap are detected.
For details, see "FR Family FR81 32-BIT MICROCONTROLLER PROGRAMMING MANUAL".
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Chapter 3: CPU
9.1.
Reset
The reset is shown below.
Reset forcibly suspends operations currently running, initializes the device and restarts the program from the reset
vector entry address.
Note:
In this series, the FixedVector function returns not the value written in the address of 0xF_FFFC on flash memory but
the first address of + 0x0024 on flash memory to reset vector. See "CHAPTER: FIXEDVECTOR FUNCTION" for
details.
9.2.
EIT Processing
The EIT processing is shown below.
The EIT processing suspends operations currently running, stores resumable information into memory and transfers
control to the predetermined processing program.
9.3.
Vector Table
The vector table is shown.
Table 9-1 Vector Table
Interruption Factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Instruction access protection violation
exception
Data access protection violation
exception
Data access error interrupt
INTE instruction
Interrupt Vector
Number
Hexa
Decimal
decimal
Interrupt
Level
Offset
Address at
TBR Initial
Value
0
1
2
3
4
5
00
01
02
03
04
05
-
0x3FC
0x3F8
0x3F4
0x3F0
0x3EC
0x3E8
0x000FFFFC
0x000FFFF8
0x000FFFF4
0x000FFFF0
0x000FFFEC
0x000FFFE8
6
06
-
0x3E4
0x000FFFE4
7
07
-
0x3E0
0x000FFFE0
8
9
08
09
-
0x3DC
0x3D8
0x000FFFDC
0x000FFFD8
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Interruption Factor
Instruction break
System reserved
System reserved
System reserved
Illegal instruction exception
NMI request
Peripheral interrupt #0
Peripheral interrupt #1
Peripheral interrupt #2
Peripheral interrupt #3
Peripheral interrupt #4
Peripheral interrupt #5
Peripheral interrupt #6
Peripheral interrupt #7
Peripheral interrupt #8
Peripheral interrupt #9
Peripheral interrupt #10
Peripheral interrupt #11
Peripheral interrupt #12
Peripheral interrupt #13
Peripheral interrupt #14
Peripheral interrupt #15
Peripheral interrupt #16
Peripheral interrupt #17
Peripheral interrupt #18
Peripheral interrupt #19
Peripheral interrupt #20
Peripheral interrupt #21
Peripheral interrupt #22
Peripheral interrupt #23
Peripheral interrupt #24
Peripheral interrupt #25
Peripheral interrupt #26
Peripheral interrupt #27
Peripheral interrupt #28
Peripheral interrupt #29
Peripheral interrupt #30
Peripheral interrupt #31
Peripheral interrupt #32
Peripheral interrupt #33
Peripheral interrupt #34
Peripheral interrupt #35
Peripheral interrupt #36
Peripheral interrupt #37
Peripheral interrupt #38
158
Interrupt Vector
Number
Hexa
Decimal
decimal
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
Interrupt
Level
Offset
Address at
TBR Initial
Value
15(0xF)Fixed
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
0x3D4
0x3D0
0x3CC
0x3C8
0x3C4
0x3C0
0x3BC
0x3B8
0x3B4
0x3B0
0x3AC
0x3A8
0x3A4
0x3A0
0x39C
0x398
0x394
0x390
0x38C
0x388
0x384
0x380
0x37C
0x378
0x374
0x370
0x36C
0x368
0x364
0x360
0x35C
0x358
0x354
0x350
0x34C
0x348
0x344
0x340
0x33C
0x338
0x334
0x330
0x32C
0x328
0x324
0x000FFFD4
0x000FFFD0
0x000FFFCC
0x000FFFC8
0x000FFFC4
0x000FFFC0
0x000FFFBC
0x000FFFB8
0x000FFFB4
0x000FFFB0
0x000FFFAC
0x000FFFA8
0x000FFFA4
0x000FFFA0
0x000FFF9C
0x000FFF98
0x000FFF94
0x000FFF90
0x000FFF8C
0x000FFF88
0x000FFF84
0x000FFF80
0x000FFF7C
0x000FFF78
0x000FFF74
0x000FFF70
0x000FFF6C
0x000FFF68
0x000FFF64
0x000FFF60
0x000FFF5C
0x000FFF58
0x000FFF54
0x000FFF50
0x000FFF4C
0x000FFF48
0x000FFF44
0x000FFF40
0x000FFF3C
0x000FFF38
0x000FFF34
0x000FFF30
0x000FFF2C
0x000FFF28
0x000FFF24
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Interruption Factor
Peripheral interrupt #39
Peripheral interrupt #40
Peripheral interrupt #41
Peripheral interrupt #42
Peripheral interrupt #43
Peripheral interrupt #44
Peripheral interrupt #45
Peripheral interrupt #46
Delay interrupt
System reserved (For REALOS use)
System reserved (For REALOS use)
For INT instruction use
Interrupt Vector
Number
Hexa
Decimal
decimal
55
56
57
58
59
60
61
62
63
64
65
66
|
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
|
255
FF
Interrupt
Level
Offset
Address at
TBR Initial
Value
0x320
0x31C
0x318
0x314
0x310
0x30C
0x308
0x304
0x300
0x2FC
0x2F8
0x2F4
|
0x000FFF20
0x000FFF1C
0x000FFF18
0x000FFF14
0x000FFF10
0x000FFF0C
0x000FFF08
0x000FFF04
0x000FFF00
0x000FFEFC
0x000FFEF8
0x000FFEF4
|
0x000
0x000FFC00
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
-
10. Memory Protection Function (MPU)
This section explains the memory protection function (MPU) of the CPU.
10.1 Overview
10.2 List of Registers
10.3 Description of Registers
10.4 Operations of Memory Protection Function
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10.1. Overview
This section explains the overview of memory protection function (MPU) of the CPU.
This architecture supports a memory protection function. The memory protection function is a function that monitors
access to a specified area and generates an exception on prohibited access. However, protection specified on system
registers is ignored.
Eight protection areas can be specified that are shared by instructions and data
The protection area with the highest priority is area 0, with the priority decreasing for areas 1, 2, 3, etc. (The areas
can overlap)
Areas are specified by a page address and a page size
Page size: Can be specified in units of 2n bytes from 16 bytes
Page address: Misaligned addresses also supported
The following access privileges are controlled using privilege mode and user mode
Instruction fetch: Enabled/ Disabled
Data Read:
Enabled/ Disabled
Data Write:
Enabled/ Disabled
Attributes are specified for each area
Buffer:
Enabled/ Disabled
The access rights and attributes of undefined areas are controlled as a default area
Protection violation exceptions occur when a protection violation occurs
The register for the memory protection function can only be accessed in a privilege mode as system registers
Data access error notification function
I/O area (00000000H to 0000FFFFH) is fixed buffer disabled
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10.2. List of Registers
The list of registers is shown.
Table 10-1 Registers Map
Address
0x0310
Registers
+0
+1
+2
Reserved
MPUCR
0x0314
Reserved
0x0318
Reserved
0x031C
Reserved
0x0320
DPVAR
0x0324
Reserved
0x0328
0x032C
DEAR
0x0330
0x0334
PABR0
0x0338
0x033C
PABR1
0x0340
0x0344
PABR2
0x0348
0x034C
PABR3
0x0350
0x0354
PABR4
0x0358
0x035C
PABR5
0x0360
0x0364
PABR6
0x0368
0x036C
Protection area control register 5
Protection area base address register 6
PACR6
PABR7
Reserved
Protection area control register 4
Protection area base address register 5
PACR5
Reserved
Protection area control register 3
Protection area base address register 4
PACR4
Reserved
Protection area control register 2
Protection area base address register 3
PACR3
Reserved
Protection area control register 1
Protection area base address register 2
PACR2
Reserved
Protection area control register 0
Protection area base address register 1
PACR1
Reserved
Data access error status register
Protection area base address register 0
PACR0
Reserved
Data access protection violation status register
Data access error address register
DESR
Reserved
MPU Control Register
Data access protection violation address register
DPVSR
Reserved
Register function
+3
Protection area control register 6
Protection area base address register 7
PACR7
Protection area control register 7
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10.3. Description of Registers
Registers are shown.
10.3.1 MPU Control Register : MPUCR
10.3.2 Instruction Access Protection Violation Address Register : IPVAR
10.3.3 Instruction Access Protection Violation Status Register : IPVSR
10.3.4 Data Access Protection Violation Address Register :DPVAR
10.3.5 Data Access Protection Violation Status Register : DPVSR
10.3.6 Data Access Error Address Register : DEAR
10.3.7 Data Access Error Status Register : DESR
10.3.8 Protection Area Base Address Register 0 to 7 : PABR0 to PABR7
10.3.9 Protection Area Control Register 0 to 7 : PACR0 to PACR7
10.3.1. MPU Control Register : MPUCR
The bit configuration of the MPU control register (MPUCR) is shown.
The MPU control register controls whether the MPU is enabled or disabled, and configures the access permissions in
privilege mode and user mode to default areas (areas not specified as protection areas).
MPUCR : Address 0312H (Access: Half-word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PIE
PRE
PWE
UIE
URE
UWE
Reserved
BE
0
0
0
0
0
0
-
0
R/W
R/W
R/W
R/W
R/W
R/W
R0,W0
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DEE
MPE
Reserved
Initial value
-
Attribute R0,W0
162
PAN[1:0]
-
-
-
0
1
0
0
R0,W0
R0,W0
R0,W0
R0,WX
R1,WX
R/W
R/W
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[bit15] PIE (Privilege Mode Instruction Fetch Enable)
This bit is for permitting instruction fetch in privilege mode from the default areas (areas that have not been specified
as protection areas).
PIE
Access to default area
0
Instruction fetch not permitted in privilege mode (Initial value)
1
Instruction fetch permitted in privilege mode
[bit14] PRE (Privilege Mode Read Access Enable)
This bit is for permitting data read access in privilege mode from the default areas (areas that have not been specified
as protection areas).
PRE
Access to default area
0
Read access not permitted in privilege mode (Initial value)
1
Read access permitted in privilege mode
[bit13] PWE (Privilege Mode Write Access Enable)
This bit is for permitting data write access in privilege mode to the default areas (areas that have not been specified as
protection areas).
PWE
Access to default area
0
Write access not permitted in privilege mode (Initial value)
1
Write access permitted in privilege mode
[bit12] UIE (User Mode Instruction Fetch Enable)
This bit is for permitting instruction fetch in user mode from the default areas (areas that have not been specified as
protection areas).
UIE
Access to default area
0
Instruction Fetch not enable at User Mode (Initial value)
1
Instruction Fetch enable at User Mode
[bit11] URE (User Mode Read Access Enable)
This bit is for permitting data read access in user mode from the default areas (areas that have not been specified as
protection areas).
URE
Access to default area
0
Read access not permitted in user mode (Initial value)
1
Read access permitted in user mode
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[bit10] UWE (User Mode Write Access Enable)
This bit is for permitting data write access in user mode to the default areas (areas that have not been specified as
protection areas).
UWE
Access to default area
0
Write access not permitted in user mode (Initial value)
1
Write access permitted in user mode
[bit9] Reserved
Always write "0" when writing. This bit reads out "0".
[bit8] BE (Buffer Enable)
The bit permits buffering to be used when performing data access to default areas (areas that are not specified as
protection areas). When the use of buffering is forbidden, the CPU stops pipeline operation and waits for the data
access to finish before starting the next operation. As a result, although the data access efficiency decreases, it is
possible to perform data access synchronized to the instruction. Illegal instruction exceptions occur when there is an
error during data access only if buffering is forbidden. When buffering is permitted, data access errors can be notified
as interrupts.
BE
Buffer enable specification for the default area
0
Buffer disabled (Initial value)
1
Buffer enabled
[bit7 to bit4] Reserved
These bits are reserved. Always write "0" when writing.
[bit3, bit2] PAN (Protection Area Number)
Indicates the number of configurable protection areas that can be specified. This bit is read-only and indicates the
number of areas implemented in hardware.
PAN[1:0]
Number of memory protection areas implemented
00
Reserved
01
8 areas
10
12 areas
11
16 areas
[bit1] DEE (Data Access Error Interrupt Enable)
This bit permits interrupts to occur when a data access error occurs in areas where buffer operation is enabled. If a
data access error occurs in an area where buffer operation is permitted while this bit is enabled, a data access error
interrupt occurs. At this time, the address where the error occurred is stored in the data access error address register
(DEAR), and the details of the access are stored in the data access error status register (DESR). If interrupts are
disabled, the above registers are updated only.
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DEE
Data access error interrupt enabled
0
Data access error interrupt disabled (Initial value)
1
Data access error interrupt enable
[bit0] MPE (Memory Protection Unit Enable)
This bit is for enabling the memory protection function. If the memory protection function is disabled, buffering is
configured as disabled for accesses to all areas.
MPE
Memory protection function
0
Memory protection function disabled (Initial value)
1
Memory protection function enabled
10.3.2. Instruction Access Protection Violation Address
Register : IPVAR
The bit configuration of the instruction access protection violation address register is shown.
This register stores the address where an instruction access protection violation occurred.
Also see "10.4.2. Instruction Access Protection Violation" and "10.4.7. Notes".
IPVAR : Address 0318H (Access: Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
IPVA[31:0]
Initial value
Attribute
X
X
•
•
•
X
X
X
R,WX
R,WX
•
•
•
R,WX
R,WX
R,WX
[bit31 to bit0] IPVA[31:0] (Instruction fetch Protection Violation Address)
This register stores the address where an instruction access protection violation occurred when a violation has not
occurred in the instruction access protection violation status register (IPVSR.IPV =0). This is not aligned.
Note:
Using this register is prohibited.
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10.3.3. Instruction Access Protection Violation Status Register :
IPVSR
The bit configuration of the instruction access protection violation status register is shown.
This register indicates the status when an instruction access protection violation occurs.
The content of this register is updated by hardware only when IPV=0. Only writing "0" to the IPV bit has an effect.
Writes to any other bits and writing "1" to IPV are ignored.
Also see "10.4.2. Instruction Access Protection Violation" and "10.4.7. Notes".
IPVSR : Address 031EH (Access : Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
-
Attribute R0,W0
-
-
-
-
-
-
-
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
Reserved
Initial value
-
Attribute R0,W0
SZ[1:0]
MD
Reserved
IPV
-
0
0
0
-
-
0
R0,W0
R,WX
R,WX
R,WX
R0,W0
R0,W0
R,W
[bit15 to bit6, bit2, bit1] Reserved
These bits are reserved. Always write "0" to these bits.
[bit5, bit4] SZ[1:0]
The access size when the violation occurred.
SZ[1:0]
166
Access size
00
Byte
01
Half-word
10
Word
11
Reserved
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[bit3] MD
Indicates the mode of the access.
MD
Operation mode
0
Access in user mode
1
Access in privilege mode
[bit0] IPV (Instruction fetch Protection Violation)
This bit indicates that an instruction access protection violation occurred. In order to save the details of new
protection violations, clear this bit.
IPV
Instruction access protection violation
0
Instruction access protection violation not detected (initial value)
1
Instruction access protection violation detected
Note:
This register is a prohibition of use.
10.3.4. Data Access Protection Violation Address
Register :DPVAR
The bit configuration of the data access Protection violation address register is shown.
The address where the violation of the data access protection occurs is saved .
DPVAR : Address 0320H (Access : Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
DPVA[31:0]
Initial value
Attribute
X
X
•
•
•
X
X
X
R,WX
R,WX
•
•
•
R,WX
R,WX
R,WX
[bit31 to bit0] DPVA[31:0] (Data Access Protection Violation Address)
This register stores the address where a data access protection violation occurred when a violation has not occurred in
the data access protection violation status register (DPVSR.DPV =0). This register indicates the address requested by
the CPU, and the address is not aligned.
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10.3.5. Data Access Protection Violation Status Register :
DPVSR
The bit configuration of the data access protection violation status register is shown.
This register indicates the status when a data access protection violation occurs.
The content of this register is updated by hardware only when DPV=0. Writing "0" to DPV only is valid.
Writes to any other bits and writing "1" to DPV are ignored.
DPVSR : Address 0326H (Access : Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
0
Attribute R0,W0
bit7
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RW[1:0]
Initial value
Attribute
SZ[1:0]
MD
Reserved
DPV
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R0,W0
R0,W0
R,W
[bit15 to bit8, bit2, bit1] Reserved
These bits are reserved. Always write 0 to these bits.
[bit7, bit6] RW[1:0] (Read/Write)
The access type when the violation occurred. When a read-modify-write is executed, because both read and write
access rights are required and the determination is made in the initial read cycle, RW=01B read (read-modify-write)
even if the violation occurs in the write part of the read-modify-write.
RW[1:0]
168
Access type
00
Read
01
Read (Read-modify-write)
10
Write
11
Reserved
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[bit5, bit4] SZ[1:0]
The access size when the violation occurred.
SZ[1:0]
Access size
00
Byte
01
Half word
10
Word
11
Reserved
[bit3] MD
Indicates the mode of the access.
MD
Operation mode
0
Access in user mode
1
Access in privilege mode
[bit0] DPV (Data Access Protection Violation)
This bit indicates that a data access protection violation occurred. In order to save the details of new protection
violations, clear this bit.
Writing "0" to this bit only is valid. Writing "1" to the bit is ignored.
DPV
Data access protection violation
0
Data access protection violation not detected (initial value)
1
Data access protection violation detected
10.3.6. Data Access Error Address Register : DEAR
The bit configuration of the data access error address register is shown.
This register stores the address where a data access error occurred.
DEAR : Address 0328H (Access : Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
DEA[31:0]
Initial value
Attribute
X
X
•
•
•
X
X
X
R,WX
R,WX
•
•
•
R,WX
R,WX
R,WX
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[bit31 to bit0] DEA[31:0] (Data Access Error Address)
This register stores the address where a data access error occurred when a violation has not occurred in the data
access error status register (DESR.DAE =0). If the protection violation occurred while accessing system registers, the
access address from the CPU is stored as it is without being aligned. If the result of performing a bus access is an
error, the address is aligned.
10.3.7. Data Access Error Status Register : DESR
The bit configuration of the data access error status register is shown.
This register indicates the status when a data access error occurs. The content of this register is updated by hardware
only when DAE=0. Writing 0 to DAE only is valid. Writes to any other bits and writing 1 to DAE are ignored.
DESR : Address 032EH (Access : Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
0
Attribute R0,W0
bit7
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RW[1:0]
Initial value
Attribute
SZ[1:0]
MD
Reserved
DAE
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R0,W0
R0,W0
R,W
[bit15 to bit8, bit2, bit1] Reserved
These bits are reserved. Always write 0 to these bits. These bits read out "0".
[bit7, bit6] RW[1:0] (Read/Write)
The access type when the error occurred.
RW[1:0]
170
Access type
00
Read
01
Read (Read-modify-write)
10
Write
11
Reserved
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[bit5, bit4] SZ[1:0]
The access size when the error occurred.
SZ[1:0]
Access size
00
Byte
01
Half-word
10
Word
11
Reserved
[bit3] MD
This bit indicates the mode of the access.
MD
Operation mode
0
Access in user mode
1
Access in privilege mode
[bit0] DAE (Data Access Error)
This bit indicates that a data access error occurred. In order to save the details of new data errors, clear this bit.
The interrupt request is withdrawn by clearing this bit when the data access error interrupt is effectively done. Only 0
writing is effective to this bit. 1 writing is invalid.
DAE
Data access error
0
Data Access Error not detected (Initial value)
1
Data Access Error detected
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10.3.8. Protection Area Base Address Register 0 to 7 : PABR0 to
PABR7
The bit configuration of protection area base address register 0 to 7 is shown.
These registers set the base addresses of the protection areas for each MPU channel.
PABR0 to PABR7 : Address 0330H , 0338H , 0340H •
bit31
•
bit30
•
•
•
• (Access : Word)
bit10
Bit9
bit8
PABR[31:8]
Initial value
Attribute
X
X
•
•
•
X
X
X
R/W
R/W
•
•
•
R/W
R/W
R/W
bit7
bit6
bit2
bit1
bit0
bit5
bit4
bit3
PABR[7:0]
Initial value
Attribute
X
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
R0,WX
R0,WX
R0,WX
R0,WX
[bit31 to bit0] PABR[31:0] (Protection Area Base Address Register)
These registers point to the base address of the protection area. The area from the address specified here to the size
specified by the protection area control registers (PACR0 to PACR7) is the protection area. The address does not
need to be aligned to the protection area size.
The lower 4 bits of the PABR register are fixed at 0000B.
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10.3.9. Protection Area Control Register 0 to 7 : PACR0 to
PACR7
The bit configuration of protection area control register 0 to 7 is shown.
These registers set access permissions and restrictions for each MPU channel.
PACR0 to PACR7 : Address 0336H , 033EH , 0346H • • • (Access : Half-word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PIE
PRE
PWE
UIE
URE
UWE
Reserv
ed
BE
0
0
0
0
0
0
-
0
R/W
R/W
R/W
R/W
R/W
R/W
R0,W0
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ASZ[4:0]
Initial value
Attribute
Reserved
PAE
0
0
0
0
0
-
-
0
R/W
R/W
R/W
R/W
R/W
R0,W0
R0,W0
R/W
[bit15] PIE (Privilege Mode Instruction Fetch Enable)
This bit is for enabling instruction fetch in privilege mode for the specified protection area.
PIE
Access to the specified protection area
0
Instruction fetch not permitted in privilege mode (Initial value)
1
Instruction fetch permitted in privilege mode
[bit14] PRE (Privilege Mode Read Access Enable)
This bit is for enabling data read access in privilege mode for the specified protection area.
PRE
Access to the specified protection area
0
Read access not permitted in privilege mode (Initial value)
1
Read access permitted in privilege mode
[bit13] PWE (Privilege Mode Write Access Enable)
This bit is for enabling data write access in privilege mode for the specified protection area.
PWE
Access to the specified protection area
0
Write access not permitted in privilege mode (initial value)
1
Write access permitted in privilege mode
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[bit12] UIE (User Mode Instruction Fetch Enable)
This bit is for enabling instruction fetch in user mode for the specified protection area.
UIE
Access to the specified protection area
0
Instruction fetch not permitted in user mode (initial value)
1
Instruction fetch permitted in user mode
[bit11] URE (User Mode Read Access Enable)
This bit is for enabling data read access in user mode for the specified protection area.
URE
Access to the specified protection area
0
Read access not permitted in user mode (initial value)
1
Read access permitted in user mode
[bit10] UWE (User Mode Write Access Enable)
This bit is for enabling data write access in user mode for the specified protection area.
UWE
Access to the specified protection area
0
Write access not permitted in user mode (initial value)
1
Write access permitted in user mode
[bit9] Reserved
Always write "0" to this bit. This bit reads out "0".
[bit8] BE (Buffer Enable)
This bit permits buffering to be used during data access for the specified protection area. When the use of buffering is
forbidden, the CPU stops pipeline operation and waits for the data access to finish before starting the next operation.
As a result, although the data access efficiency decreases, it is possible to perform data access synchronized to the
instruction. Illegal instruction exceptions occur when there is an error during data access only if buffering is forbidden.
When buffering is permitted, data access errors can be notified as interrupts.
BE
Bufferable specification for the specified protection area
0
Buffer Disable (Initial value)
1
Buffer Enable
[bit7 to bit3] ASZ[4:0] (Area Size)
These bits specify the size of the specified protection area. The specified address does not need to be aligned to the
sizes described below. Furthermore, if the lower limit of the area specified by the address and size exceeds
FFFFFFFFH, the lower limit of the area is treated as FFFFFFFFH.
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ASZ[4:0]
Size of the specified
protectorate area
00000B
Reserved
00001B
Reserved
00010B
Reserved
00011B
16B
00100B
32B
00101B
64B
00110B
128B
00111B
256B
01000B
512B
01001B
1KB
01010B
2KB
01011B
4KB
01100B
8KB
01101B
16KB
01110B
32KB
01111B
64KB
10000B
128KB
10001B
256KB
10010B
512KB
10011B
1MB
10100B
2MB
10101B
4MB
10110B
8MB
10111B
16MB
11000B
32MB
11001B
64MB
11010B
128MB
11011B
256MB
11100B
512MB
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ASZ[4:0]
Size of the specified
protectorate area
11101B
1GB
11110B
2GB
11111B
4GB
[bit2, bit1] Reserved
These bits are reserved. Always write 0 when writing.
[bit0] PAE (Protection Area Enable)
This bit is for enabling the memory protection function.
PAE
Memory protection area
0
Specified memory protection area disabled (Initial value)
1
Specified memory protection area enabled
10.4. Operations of Memory Protection Function
The memory protection function is shown below.
10.4.1 Setting Up Memory Protection Areas
10.4.2 Instruction Access Protection Violation
10.4.3 Data Access Protection Violation
10.4.4 Data Access Errors
10.4.5 Memory Protection Operation by Delay Slot
10.4.6 DEAR and DESR Update
10.4.7 Notes
10.4.1. Setting Up Memory Protection Areas
The setting up memory protection areas of the CPU is shown below.
The memory protection function is configured by settings whether instructions, data reads, and data writes are
permitted or forbidden in privilege mode and user mode for a maximum of eight protection areas specified by address
and size, and default areas that are not contained in these protection areas. The buffer permitted or forbidden setting
can also be configured for each area at the same time.
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Chapter 3: CPU
If there are overlaps between specified protection areas, the area with the smallest number takes precedence.
When the memory protection function is disabled (MPUCR.MPE =0), access is performed with access permitted to
all areas and buffering disabled.
10.4.2. Instruction Access Protection Violation
The instruction access protection violation of the CPU is shown below.
The memory protection unit (MPU) monitors CPU instruction fetches and determines whether instruction fetches are
permitted to the accessed areas. The instruction address when an instruction access protection violation exception
occurs can be determined from the PC value saved on the system stack.
10.4.3. Data Access Protection Violation
The data access protection violation of the CPU is shown below.
The memory protection unit (MPU) monitors CPU data accesses and determines whether accesses (reads and writes)
to the corresponding area are permitted. If an access was not permitted, the MPU stores that address and access
information in the data access protection violation address register (DPVAR) and the data access protection violation
status register (DPVSR). However, if data access protection violation information already exists in the above register
(DPVSR.DPV =1), this is not overwritten. The data access that caused the violation at this time is not performed.
If a data access protection violation occurs during the execution of an instruction that performs multiple data accesses,
the data accesses that had executed up until the violation occurred are not cancelled. If a data access protection
violation exception occurs during the LDM0, LDM1, STM0, STM1, FLDM, or FSTM instructions, the list of
remaining registers is stored in the exception status register ESR.RL.
If a data access protection violation occurs during the EIT processing sequence or the RETI instruction, the CPU is
halted and can only be recovered by break interrupt or reset.
10.4.4. Data Access Errors
This section explains data access errors of the CPU.
If the following conditions are satisfied during a data access, this is treated as a data access error and the access
information at that time are stored in the data access error address register (DEAR) and data access error status
register (DESR). However, if data access error information already exists in the above register (DESR.DAE =1), this
is not overwritten.
System register access in user mode
Bus error during data access
The operation after a bus error occurs during data access differs between accesses with buffering enabled and
accesses with buffering disabled. System register accesses in user mode are always processed as illegal instruction
exceptions (data access).
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177
Chapter 3: CPU
If a data access error occurs during access to an unbufferable area, the CPU processes this as an illegal instruction
exception (data access error).
If a data access error occurs during access to a bufferable area, and if the data access error interrupt is enabled by
MPU control register MPUCR.DEE =1, the data access error interrupt is triggered and the CPU performs data access
error interrupt processing. If a data access error occurs during access to a bufferable area, because the CPU is
executing a subsequence instruction, the PC saved when the data access error interrupt occurs is not the PC value for
the instruction that performed the data access.
If an illegal instruction exception (data access error) occurs during the execution of an instruction that performs
multiple data accesses, the data accesses that had executed up until the error occurred are not cancelled. If an illegal
instruction exception (data access error) occurs during the LDM0, LDM1, STM0, STM1, FLDM, or FSTM
instructions, the list of remaining registers is stored in the exception status register ESR.RL, and the bit indicating a
data access error ESR.INV6 is set.
If an illegal instruction exception (data access error) occurs during the EIT processing sequence or the RETI
instruction, the CPU is halted and can only be recovered by break interrupt or reset.
10.4.5. Memory Protection Operation by Delay Slot
The memory protection operation by a delay slot is shown.
The instruction arranged in the delay slot is processed as 16-bit. Therefore, the exception is generated as an illegal
instruction exception (instruction that cannot be arranged in the delay slot) even if there are an instruction access
protection violation factor and an instruction access error factor in the lower 16-bit by arranging 32-bit instruction in
the delay slot.
10.4.6. DEAR and DESR Update
The DEAR and the DESR update are shown.
The data access error address register (DEAR) and the data access error status register (DESR) are renewed in the
following cases.
System register access in user mode (illegal instruction exception)
Bus error in buffer prohibition area access (illegal instruction exception)
Bus error in buffer permission area access (data access error interrupt)
DEAR and DESR are renewed in the instruction that did the corresponding access and it is renewed to the
asynchronization with the instruction operation in the case where the data access error interrupt is generated in the
case where the illegal instruction exception is generated. It gives priority to the illegal instruction exception factor
when the factor is generated at the same time.
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Chapter 3: CPU
10.4.7. Notes
This section explains notes of the Memory Protection Function (MPU).
Access protection violation exception will occur when an instruction of access protection violation is executed. For
details, see "FR Family FR81 32-bit Microcontroller Programming Manual". For details of the instruction access
protection violation and the instruction access protection violation exception, also see "10.4.2. Instruction Access
Protection Violation".
If the boundary of delay slot is different from that of instruction access protection area, the instruction access
protection violation occurs regardless of whether the branch is established or not. PC with occurrence of exception
is PC of delayed branch instruction.
BEQ:D L_MYPROC2
NOP
Protection specified
(instruction fetch)
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179
Chapter 4: Operation Mode
This chapter explains the operation mode.
1.
Overview
2.
Features
3.
Configuration
4.
Register
5.
Operation
Code : BMODED-2v0-91528-2-E
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Chapter 4: Operation Mode
1. Overview
This section explains the overview of the operation mode.
This chapter explains the operation mode of this type of item decided after reset is released. See "CHAPTER:
POWER CONSUMPTION CONTROL" for the mode of each power consumption control and the mode of each
clock selection.
2. Features
This section explains features of the operation mode.
This device supports the following operation modes.
User mode
The external bus interface can be used.
The program starts from the built-in Flash.
Serial writer mode
The built-in Flash memory is programmed by using the serial writer.
3. Configuration
This section explains the configuration of the operation mode.
Figure 3-1 Block Diagram
Reset control
circuit
MD0, MD1
External pin
On-chip bus
address decoder
3
I/O function selector
according to mode
Mode decision
circuit
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
P006
External pin
181
Chapter 4: Operation Mode
4. Register
This section explains the register of the operation mode.
Register
Address
Register function
+0
0x07FC
+1
+2
+3
BMODR Reserved Reserved Reserved Bus mode data register
4.1. Bus Mode Register : BMODR (Bus MODe Register)
The bit configuration of the bus mode register is shown.
This register indicates the mode that has been set during startup. The register data can be read only.
Data writing does not affect on this register value.
BMODR : Address 07FCH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BMOD[7:0]
Initial value
*
*
Attribute R,WX
R,WX
*: It depends on operation mode.
*
*
*
*
*
*
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit7 to bit0] BMOD[7:0] : Operation mode
These bits indicate the current operation mode. Data writing is ineffective.
BMOD[7:0]
Operation mode
0101xxxx
User mode
0111xx1x
Serial writer mode
5. Operation
This section explains operations of the operation mode.
5.1 MD0, MD1, P006 Pins Settings
5.2 Fetching the Operation Mode
5.3 Explanation of Each Operation Mode
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Chapter 4: Operation Mode
5.1.
MD0, MD1, P006 Pins Settings
MD0, MD1 and P006 pins settings are shown.
Table 5-1 Pin Settings
Operation mode
MD1
MD0
P006
User mode
0
1
-
Serial writer mode
1
0
1
Settings other than those shown in the table are prohibited.
Table 5-2 Correspondence of P006 Pin and Package
Package Type
Pin Number
Port Name
PAB416
B9
P006
LQR208/LER208
195
P006
LQP176/LEP-176
167
P006
LQS144/LQN144/LES144
137
P006
5.2.
Fetching the Operation Mode
The fetching the operation mode is shown.
The operation mode is fetched by sampling the RST (Reset). During the time when an RST is issued and when it is
released, the MD0, MD1 and P006 pin inputs must be determined. In User mode, the P006 pin does not need to be
determined.
The following shows an operation sequence from an occurrence of reset cause to the determination of an operation
mode.
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183
Chapter 4: Operation Mode
Figure 5-1 Operation Mode Fetch Timing Chart
When the initialization reset (INIT) occurs;
Chip reset sequence
*
"L"
RST
(Setting
initialization
reset)
*
* : Continue fixing MD0 and MD1 pins even after operating mode determined.
Note:
When in serial writer mode, the P006 pin needs not be fixed after operating mode determined.
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Chapter 4: Operation Mode
5.3.
Explanation of Each Operation Mode
The each operation mode is shown.
The following details each operation mode.
5.3.1 User Mode
5.3.2 Serial Writer Mode
5.3.1.
User Mode
The user mode is shown.
An external bus pin is reset immediately when a reset is entered for the external reset pin. For details, see "Pin Status
Table" in "APPENDIX".
5.3.2.
Serial Writer Mode
The serial writer mode is shown.
Table 5-3 Setting Pins in Serial Writer Mode
Pin number
Serial writer mode
Pin
PAB
Pin device/connection destination
Input
name
144 176
208
416
(for on-board programming)
level
116
117
123
118
119
144
145
151
146
147
172
173
179
174
175
B22
B21
A14
A22
A21
MD0
MD1
RSTX
X0
X1
137
167
195
B9
P006
113
139
167
D16
P126
SIN0_0
114
140
168
A15
P127
SOT0_0
GND
VCC (Pull-up)
Reset input
Oscillation pin
Oscillation pin
Serial writer mode is started by adding
pull-up resistor to external and, after
releasing reset, setting level "H".
Setting the input of this pin to "H" until
the start of communication enables clock
asynchronous communication mode,
while setting it to "L" enables clock
synchronous communication mode.
Serial writer mode starts, and at the point
at which communication starts, this pin is
used as a UART serial data input pin.
Serial writer mode starts and, at the point
at which communication starts, this pin
becomes a serial data output pin.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Output
level
Hys.
Hys.
Hys.
-
-
Auto
CMOS
Hys.
CMOS
Auto
CMOS
185
Chapter 4: Operation Mode
Pin number
144
115
176
141
208
169
45,
72,
109,
124
55,
88,
133,
152
104,
134,
157,
180
36,
128,
144
44,
156,
176
184,
208
1,
37,
44,
73,
108,
120,
125,
129
40,
84
1,
45,
54,
89,
132,
148,
153,
157
50,
103
53,
62,
105,
135,
156,
176,
181,
185
58,
122
PAB
416
B15
AF10,
AF11,
AF12,
AF13,
AF23,
AF24,
P26,
N26,
D26,
C26,
A16,
B16
M1,
N1,
AC1,
AD1,
A13,
A12,
A4,
A3
*
AF4,
T26
AF7,
43,
53,
61,
AF6,
82
101
120
W26,
V26
42,
52,
60,
AF5,
83
102
121
U26
* : See CHAPTER: OVERVIEW.
186
Pin
name
P130
SCK0_0
Serial writer mode
Pin device/connection destination
Input
(for on-board programming)
level
When the communication mode is clock
synchronous communication mode, this
pin becomes the serial clock input/output
pin.
Output
level
Hys.
CMOS
VCC
+5.0v power supply
-
-
VCCE
+5.0v power supply
-
-
GND
-
-
VCC
-
-
VSS
-
-
VCC
-
-
VSS
AVCC1
AVCC0
AVSS1
AVRL1
AVSS0
AVRL0
AVRH1
AVRH0
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Chapter 4: Operation Mode
Figure 5-2 Example of Connection for Serial Writer Mode Using Clock Synchronous Serial Writer
MB91F52x
1
1 when in ブートプログラムモード時
boot program mode
4.7 k Ω
MD1
MD0
X0
X1
RSTX
Clock
クロック同期
synchronous
シリアルライタ
serial writer
4.7 k Ω
SIN0_0
SOT0_0
SCK0_0
P006
Communication via clock synchronous serial writer
The pull-up resistance value is an example. Select the most appropriate resistance value for each system.
The pull-up resistance value is an example. Select the most appropriate resistance value for each system.
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187
Chapter 4: Operation Mode
Figure 5-3 Example of Connection for Serial Writer Mode Using Clock Asynchronous Serial Writer
MB91F52x
1 when ブートプログラムモード時
in boot program mode 1
4.7 k Ω
MD1
MD0
4MHz,8MHz,16MHz
X0
X1
RSTX
4.7 k Ω
Clock
クロック非同期
asynchronous
シリアルライタ
serial writer
RS-232C
SIN0_0
SOT0_0
4.7 k Ω
P006
Communication via clock asynchronous serial writer
クロック非同期シリアルによる通信
The pull-up resistance value is an example. Select the most appropriate resistance value for each system.
The pull-up resistance value is an example. Select the most appropriate resistance value for each system.
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Chapter 5: Clock
This chapter explains the clock.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : BG4ACCTL-1v1-91528-3-E
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189
Chapter 5: Clock
1. Overview
This section explains the overview of the clock.
The built-in oscillation circuit generates a dual clock product, which generates individual clock systems on the chip.
This product also implements the CR oscillation circuit that can be used as sub-clock.
External pins for the built-in oscillation circuit :
Main clock
: Connects to the crystal resonator
Sub clock
: Connects to the crystal resonator
Generation of source clocks : Selects from the clocks which are multiplied by PLL/SSCG of main clock
(MCLK) or divided by 2 of main clock, or sub clock (SBCLK).
Division of source clock : Divides the source clock and generates operating clocks for supplying to each
unit.
For details of the FlexRay dedicated clock, see the "FlexRay DEDICATED CLOCK" chapter.
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Chapter 5: Clock
Figure 1-1 Diagram of the Clock Generation System
Main clock (MCLK)
PLL clock (PLLCLK)
* Non spread spectrum clock
Sub clock (SBCLK)
PLL/SSCG clock (PLLSSCLK)
Source clock (SRCCLK)
* Selectable non spread spectrum
clock or spread spectrum clock
Sub clock/WDT1(Hardware watchdog)
CR oscillation
for WDT1
CR oscillation circuit (100 kHz)
WDT1 calibration
Main clock
generation
unit
Main clock (MCLK)
Sub clock
generation
unit
Sub clock (SBCLK)
divided by 2
RTC clock (WATCLK)
Watch and Power
management
clock generation unit
To Real Time Clock
PMU clock (PMUCLK)
For DEBUG I/F
Main clock (M_MCLK)
On-chip debugger (OCD)
CR
oscillation
FlexRay PLL
clock generation
unit
Clock generation unit
For DEBUG I/F
PLL clock (M_PCLK)
FlexRay
FlexRay clock
clock generation unit
PLL/SSCG
clock generation
unit
CAN prescaler
Clock selection unit
divided by 2
Peripheral clock
divider
control unit
CAN prescaler clock
Selector
Peripheral clock (PCLK2)
Source clock select unit
Clock divider
control unit
MCLK÷2 / SBCLK / PLLSSCLK
On-chip bus clock (HCLK)
CPU clock (CCLK)
Peripheral clock (PCLK1)
External bus clock (TCLK)
To Main, Sub, or PLL/SSCG clock generation unit
From Main, Sub, or PLL/SSCG clock generation unit
Oscillation stop request/
Oscillation stop release request
Oscillation stabilization wait
timer interrupt
Clock control
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191
Chapter 5: Clock
2. Features
This section explains features of the clock.
2 system on-chip oscillators are implemented.
The main clock (MCLK) is multiplied by on-chip PLL/SSCG.
Each clock has been forced not to supply by using the timer until it becomes stabilized (oscillation stabilization
wait timer).
Oscillation stabilization wait end interrupt can be generated.
Main clock oscillation stabilization wait timer (main timer) and sub clock oscillation stabilization wait timer (sub
timer) can be used as a general-purpose interrupt interval timer after the oscillation stabilization of each clock for
main, and sub takes place.
The clock for the real time clock can be selected from the main clock (MCLK) and the sub clock (SBCLK).
Implements a CR oscillation circuit for 100 kHz WDT1 clock.
In a single clock product, the CR oscillation clock can be used as a sub-clock source. Refer to the "CHAPTER:
CLOCK SUPERVISOR" for the selection method.
Generates the clock for CAN prescaler. The clock can be selected from PLL clock (PLLCLK) [non spread
spectrum clock] and main clock (MCLK). When PLL stops when PLL clock is selected, on-chip bus clock (HCLK)
is used.
For the noise decrement, the SSCG clock [spread spectrum clock] can be selected as CPU and a clock of the
resource.
Note:
If main timer or sub timer is used as source for recovering from the watch mode with power-shutdown, set the
interrupt level to ‘31’, before CPU state changes to the watch mode with power-shutdown.
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Chapter 5: Clock
3. Configuration
This section explains the configuration of the clock.
Figure 3-1 Connection Diagram of Clock (1)-1 Main Clock Generation Unit
CSELR:
MTMCR:
MTMCR:
CSTBR:
MTMCR:
MCEN
MTE
MTC
MOSW
MTS
MTMCR:
MTIE
ICR30
Main timer
Interrupt
Main
Timer
MTMCR:
MTIF
STOP mode
Oscillation stop request
CMONR:
MCRDY
MCLK
Main clock
X0
X1
Figure 3-2 Connection Diagram of Clock (1)-2 Sub Clock Generation Unit
CSELR:
SCEN
STMCR: STMCR:
STE
STC
CSTBR: STMCR: STMCR:
SOSW
STS
STIE
Sub
Timer
STMCR:
STIF
ICR30
Sub timer
Interrupt
STOP mode
Oscillation stop request
X0A
CMONR:
SCRDY
SBCLK
Sub clock
X1A
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193
Chapter 5: Clock
Figure 3-3 Connection Diagram of Clock (1)-3 PLL/SSCG Clock Generation Unit
CSELR.
PCEN
PLLCR.
POSW
PTMCR.
PTIE
PLL
Timer
ICR30
PLL timer
Interrupt
PTMCR.
PTIF
CCPSSELR.
PCSEL
CMONR.
PCRDY
SSCGCLK
SSCG clock
SSCG Enable
Divider
SSCG-PLL
PLLSSCLK
PLL/SSCG clock
1
Clock gear
0
CCPSDIVR.
SODS
CCSSFBR0
CCCGRCR0
CCSSFBR1
CCCGRCR1
CCSSCCR0
CCCGRCR2
CCSSCCR1
PLL Enable
PLL
(Non-SSCG)
MCLK
Main clock
PLLCLK
PLL clock
Divider
Divider
PLLCR.
PDS
CCPSDIVR.
PODS
CCPLLFBR.
IDIV
Figure 3-4 Connection Diagram of Clock (2) Source Clock Selection Unit
MCLK
Main clock
Divider
(1/2)
MCLK2
Main clock 2 division
PLLSSCLK
PLL/SSCG clock
01
SBCLK
Sub clock
11
CSELR.
CKS
194
00
01
Clock selection control
MCLK2/PLLSSCLK/SBCLK
Source clock
CMONR.
CKM
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Chapter 5: Clock
Figure 3-5 Connection Diagram of Clock (3) Divider Control
Peripheral clock divider control unit
1/1 to 1/16
（PICD.PDIV）
Selector
Peripheral clock (PCLK2)
(SACR.M)
Clock divider control unit
×1
On-chip bus clock (HCLK)
×1
CPU clock (CCLK)
1/1 to 1/16
(DIVR2.DIVP)
Peripheral clock (PCLK1)
1/1 to 1/8
(DIVR1.DIVT)
External bus clock (TCLK)
1/1 to 1/8
(DIVR0.DIVB)
Source clock (SRCCLK)
Base clock
PLL clock (PLLCLK)
*: Non spread spectrum clock
Figure 3-6 Connection Diagram of Clock (4) CAN Prescaler Clock Generation
CAN prescaler clock selection unit
PLL/SSCG oscillation enables
(CSELR:PCEN)
PLL clock (PLLCLK)
*: Non spread spectrum clock
On chip bus clock (HCLK)
Main clock (MCLK)
CAN prescaler clock
selection
(CANPRE:CPCKS)
1
0
CAN prescaler clock
0
1
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195
Chapter 5: Clock
Figure 3-7 Connection Diagram of Clock (5) Watch/Power Management Clock Generation
CCRTSELR:CSC
MCLK
0
SBCLK
1
RTC clock
(WATCLK)
Main clock
divider (F-divider)
0
PMU clock
divider (G-divider)
1
(1 to 32division)
(128 to 512division)
CCPMUCR0:FDIV
196
PMU clock
(PMUCLK)
CCPMUCR1:GDIV
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Chapter 5: Clock
Figure 3-8 Diagram of the Clock System
CPU Clock (CCLK)
Regulator
On Chip Bus Clock (HCLK)
FR81s CPU core
Peripheral Clock (PCLK1)
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Peripheral Clock (PCLK2)
Data
CAN Prescaler Clock
JTAG I/F
XBS
Main Clock (MCLK)
XBS Crossbar Switch
Wild register
CR Oscillation
PLL Output (PLLCLK)
Timing Protection
Unit
Ext-Bus Clock (TCLK)
Flex Ray Clock
Flash
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Sub Clock (SCLK)
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
FlexRay(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
16
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
32
BackUp
RAM 16KB
Async Bus Bridge (PCLK1 PCLK2)
FlexRay Clock Control
HCLK
Ｉ/Ｏ port setting
16bit Peripheral Bus
CAN prescaler
RTC／WDT1 Calibration
Operation mode
register
Async Bus Bridge (PCLK1 PCLK2)
CRC
Wave generator (6ch)
I / O Port
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 32ch)
32bit Input capture(8ch)
Multi-function serial interface (20ch)
32bit Output compare(8ch)
TIOA,TIOB
FRCK
16bit Input capture (4ch)
ICU
OCU
DTTI,RTO
16bit Free-run timer (3ch)
32bit Free-run timer(8ch)
FRCK
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Bus Bridge (32bit 16bit)
Base timer (2ch)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
PPG(88ch)
U/D counter (4ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input(24ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Clock supervisor
Watchdog timer(SW and HW)
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control （divide control）
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
（External power supply low voltage detection）
Low voltage detection
（Internal power supply low voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
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Table 3-1 List of functions that use PCLK1/PCLK2
Functions that use PCLK1
Functions that use PCLK2
RAM ECC Control (BackUp RAM)
BackUp RAM
Watchdog timer (SW and HW)
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
Reset control register
Low-power consumption setting register
Delay interrupt
Interrupt controller
External interrupt input (24ch)
Real time clock
Clock supervisor
NMI
Low-voltage detection
(External power supply low-voltage
detection)
Low-voltage detection
(Internal power supply low-voltage detection)
Clock control
(Clock setting, Main timer, Sub timer, PLL
timer)
-
198
CAN prescaler
RTC/WDT1 Calibration
I/O port setting
32bit Free-run timer (8ch)
32bit Input capture (8ch)
32bit Output compare (8ch)
Base timer (2ch)
U/D counter (4ch)
Reload timer (8ch)
8bit DA converter (2ch)
Clock monitor
CRC
Wave generator (6ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
16bit Output compare (6ch)
12bit AD converter (32ch + 32ch)
Multi-function serial interface (20ch)
PPG (88ch)
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Chapter 5: Clock
4. Registers
This section explains registers of the clock.
Table 4-1 Registers Map
Address
0x0488
0x0510
Registers
Register function
+0
+1
+2
+3
DIVR0
DIVR1
DIVR2
Reserved
Division Configuration Register 0
Division Configuration Register 1
Division Configuration Register 2
STMCR
Clock Source Configuration Register
Clock Source Monitor Register
Main Timer Control Register
Sub Timer Control Register
PTMCR
PLL Setting Register
Oscillation Stabilization Wait Setting Register
PLL Oscillation Stabilization Wait Timer
Control Register
CSELR
0x0514
CMONR
PLLCR
MTMCR
CSTBR
0x0520
CCPSSELR
Reserved
Reserved
PLL/SSCG Clock Selection Register
CCPSDIVR PLL/SSCG Output Clock Division Setting
Register
0x0524
Reserved
CCPLLFBR
CCSSFBR0
PLL Feedback Division Setting register
CCSSFBR1 SSCG Feedback Division Setting register 0
SSCG Feedback Division Setting register 1
0x0528
Reserved
CCSSCCR0
0x052C
Reserved
Clock Gear Configuration setting Register 0
CCCGRCR0 CCCGRCR1 CCCGRCR2 Clock Gear Configuration setting Register 1
Clock Gear Configuration setting Register 2
CCSSCCR1
SSCG configuration setting register 0
SSCG configuration setting register 1
RTC/PMU Clock Selection Register
PMU Clock Division Configuration
CCPMUCR0 CCPMUCR1 Register 0
PMU Clock Division Configuration
Register 1
0x0530
CCRTSELR
Reserved
0x0534
Reserved
Reserved
Reserved
Reserved
Reserved
0x0538
Reserved
Reserved
Reserved
Reserved
Reserved
0x053C
Reserved
Reserved
Reserved
Reserved
Reserved
0x1000
SACR
PICD
Reserved
Reserved
Sync/Async Control Register
Peripheral Interface Clock Divider
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4.1.
Division Configuration Register 0 : DIVR0 (DIVision clock
configuration Register 0)
The bit configuration of the division configuration register 0 is shown.
This register controls division of clocks.
DIVR0 : Address 0488H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
DIVB[2:0]
Initial value
Attribute
bit2
bit1
bit0
Reserved
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] DIVB[2:0] (DIVision ratio of Baseclock) : Base clock division setting
These bits configure a division in the area where the base clock is generated from the source clock as follows.
The CPU operation clock and the on-chip bus clock (HCLK) have the same frequency as that of the base clock.
DIVB[2:0]
Division ratio
000
No divide (Initial value)
001
2 division
010
3 division
011
4 division
100
5 division
101
6 division
110
7 division
111
8 division
[bit4 to bit0] (Reserved)
200
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Chapter 5: Clock
4.2.
Division Configuration Register 1 : DIVR1 (DIVision clock
configuration Register 1)
The bit configuration of the division configuration register 1 is shown.
This register controls division of clocks.
DIVR1 : Address 0489H (Access : Byte, Half-word, Word)
bit7
bit6
TSTP
Initial value
Attribute
bit5
bit4
bit3
bit2
DIVT[2:0]
bit1
bit0
Reserved
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7] TSTP (TCLK SToP) : External bus clock stop enable
This bit configures whether to stop the external bus clock (TCLK) when going into sleep mode.
TSTP
TCLK in sleep mode
0
No stop (Initial value)
1
Stop
[bit6 to bit4] DIVT[2:0] (DIVide ratio of TCLK) : External bus clock division setting
These bits configure the division ratio when generating the external bus clock (TCLK) from the base clock.
DIVT[2:0]
Base clock → TCLK division ratio
000
No divide
001
2 division (Initial value)
010
3 division
011
4 division
100
5 division
101
6 division
110
7 division
111
8 division
Note:
Set this register so that the external bus clock (TCLK) definitely becomes 40 MHz or less.
[bit3 to bit0] (Reserved)
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4.3.
Division Configuration Register 2 : DIVR2 (DIVision clock
configuration Register 2)
The bit configuration of the division configuration register 2 is shown.
This register controls division of clocks.
DIVR2 : Address 048AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
DIVP[3:0]
Initial value
Attribute
bit1
bit0
Reserved
0
0
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit4] DIVP[3:0] (DIVision ratio of PCLK) : Peripheral clock division setting
These bits configure the division ratio when generating the peripheral clock (PCLK) from the base clock.
DIVP[3:0]
Base clock → PCLK division ratio
0000
No divide
0001
2 division
0010
3 division
0011
4 division (Initial value)
0100
5 division
0101
6 division
0110
7 division
0111
8 division
1000
9 division
1001
10 division
1010
11 division
1011
12 division
1100
13 division
1101
14 division
1110
15 division
1111
16 division
Note:
Set this register to peripheral clock (PCLK) to be sure to become 40 MHz or less.
[bit3 to bit0] (Reserved)
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Chapter 5: Clock
4.4.
Clock Source Selection Register : CSELR (Clock source
SELection Register)
The bit configuration of the division selection register 0 is shown.
This register controls each clock source and selects a source clock (SRCCLK).
CSELR : Address 0510H (Access : Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
SCEN
PCEN
MCEN
*
0
1
bit4
bit3
bit2
bit1
Reserved
0
0
bit0
CKS[1:0]
0
0
0
Attribute
R,W
R,W
R,W
R0,WX
R0,WX
R0,WX
R,W
R,W
*: This bit is initialized to "0". But this bit is not initialized by the return from the watch mode (power-shutdown).
Note:
The value set for this register and the value read out from this register are not actually controlled and selected. You
can make sure that the value set for this register would really take effect by reading out CMONR. After making sure
that the value of this register is the same as that of CMONR, rewrite the register. While switching clocks is in
progress (CKS[1:0] ≠ CKM[1:0]), a write operation to this register will be ignored.
[bit7] SCEN (Sub Clock ENable) : Sub clock oscillation enable
This bit controls an oscillation circuit for sub clock (SBCLK) as follows.
SCEN
Oscillation control for sub clock
0
Stop oscillation (Initial value)
1
Oscillate
This bit cannot be rewritten when a sub clock (SBCLK) is selected as the source clock.
The oscillation circuit for sub clock always stops in stop mode regardless of the value of this bit.
The sub timer is cleared when this bit is set to "0".
[bit6] PCEN (PLL Clock ENable) : PLL oscillation enable
This bit controls the PLL/SSCG clock oscillation circuit as follows.
PCEN
Oscillation control for PLL/SSCG clock (PLLSSCLK)
0
Stop oscillation (Initial value)
1
Oscillate
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This bit cannot be rewritten when a PLL/SSCG clock (PLLSSCLK) is selected as the source clock. Also, this bit
cannot be rewritten when the main oscillation is stopped or during the main oscillation stabilization wait time
(CMONR. MCRDY=0).
Set this bit to "0" before switching to the stop mode.
Rewriting the MCEN bit with "0" causes this bit to set to "0".
Note:
PLL enters the status of the oscillation enable regardless of the value of this bit while communicating the MDI in
high-speed.
[bit5] MCEN (Main Clock ENable) : Main clock oscillation enable
This bit controls an oscillation circuit for main clock as follows.
MCEN
Oscillation control for main clock
0
Stop oscillation
1
Oscillate (Initial value)
This bit cannot be rewritten when a main clock (MCLK) or PLL/SSCG clock (PLLSSCLK) is selected as the source
clock.
The oscillation circuit for main clock always stops regardless of the value of this bit when the stop mode is set.
The main timer is cleared when this bit is set to "0".
Note:
The main clock enters the status of the oscillation enable regardless of the value of this bit while communicating the
MDI in low-speed.
[bit4 to bit2] (Reserved)
[bit1, bit0] CKS[1:0] (ClocK Select) : Source clock selection
These bits select the source clock (SRCCLK) as follows.
CKS
204
Source selection
00
Division of the main clock (MCLK) by 2(Initial value)
01
Division of the main clock (MCLK) by 2
10
PLL/SSCG clock (PLLSSCLK)
11
Sub clock (SBCLK)
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Chapter 5: Clock
However, when CKS[1:0] ≠ CKM[1:0], these bits cannot be rewritten. When the clock oscillation which you are
trying to switch operations by these bits stops or is waiting for a stabilization (CMONR.xCRDY=0), this bit cannot
also be rewritten.
A direct switch from PLL/SSCG clock (PLLSSCLK) to the sub clock (SBCLK) or vice versa cannot be performed.
Possible combinations for changing these bits are shown below.
CKS value before
change
Eligible values
Rewritten
conditions
00, 01
MCRDY=1
10
PCRDY=1
00, 01
MCRDY=1
11
SCRDY=1
00
MCRDY=1
10
PCRDY=1
01
MCRDY=1
11
SCRDY=1
Ineligible values
00
11
01
10
10
01,11
11
00,10
Do not write the values which cannot be rewritten.
4.5.
Clock Source Monitor Register : CMONR (Clock source
MONitor Register)
The bit configuration of the clock source monitor register is shown.
This register displays the status of each clock source and the selected source clock (SRCCLK).
You can confirm that the value set at CSELR is really reflected in the actual status by reading this register.
CMONR: Address 0511H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
SCRDY PCRDY MCRDY
Initial value
*
0
1
bit3
bit2
Reserved
0
0
bit1
bit0
CKM[1:0]
0
0
0
Attribute R,WX
R,WX
R,WX
R0,WX R0,WX R0,WX
R,WX
R,WX
*: This bit is initialized to "0". But this bit is not initialized by the return from the watch mode (power-shutdown).
Note:
If you have changed CSELR, do not write next value on CSELR until CMONR is equal to CSELR.
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Chapter 5: Clock
[bit7] SCRDY (Sub Clock ReaDY) : Sub clock ready
This bit shows the sub clock (SBCLK) status as follows.
SCRDY
0
Sub clock (SBCLK) status
Oscillation stops or in the oscillation stabilization wait status.
It is in the oscillation stabilization status and available for the source
clock.
You cannot select a sub clock (SBCLK) as the source clock when this bit is set to "0".
1
Note:
SCRDY=1 may be read immediately after changing SCEN=1 to 0.
[bit6] PCRDY (PLL Clock ReaDY) : PLL clock ready
This bit shows the PLL/SSCG clock (PLLSSCLK) status as follows.
PCRDY
0
PLL/SSCG clock (PLLSSCLK) status
Oscillation stops or in the oscillation stabilization wait status.
It is in the oscillation stabilization status and available for the source
clock.
You cannot select a PLL/SSCG clock (PLLSSCLK) as the source clock when this bit is set to "0".
1
Note:
PCRDY=1 may be read immediately after changing PCEN=1 to 0.
PLL enters the status of the oscillation enable regardless of the value of this bit while communicating the MDI in
high-speed.
[bit5] MCRDY (Main Clock ReaDY) : Main clock ready
This bit shows the main clock (MCLK) status as follows.
MCRDY
0
Main clock (MCLK) status
Oscillation stops or in the oscillation stabilization wait status.
It is in the oscillation stabilization status and available for the source
clock.
You cannot select a main clock (MCLK) or a PLL/SSCG clock (PLLSSCLK) as the source clock when this bit is set
to "0".
The initial value of "1" for this bit means that it is oscillation stabilized at the first reset vector fetch after power-on
reset, not that it is already oscillation stabilized immediately after power-on reset.
1
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Chapter 5: Clock
Note:
MCRDY=1 may be read immediately after changing MCEN=1 to 0.
The main clock enters the status of the oscillation enable regardless of the value of this bit while communicating the
MDI in high-speed.
[bit4 to bit2] (Reserved)
[bit1, bit0] CKM[1:0] (ClocK Monitor) : Source clock display
These bits show the source clock (SRCCLK) currently selected.
CKM[1:0]
4.6.
Source selection
00
Division of main clock (MCLK) by 2
01
Division of main clock (MCLK) by 2
10
PLL/SSCG clock (PLLSSCLK)
11
Sub clock (SBCLK)
Main Timer Control Register : MTMCR (Main clock TiMer
Control Register)
The bit configuration of the main timer control register is shown.
This register controls the main timer which runs with the main clock (MCLK).
MTMCR : Address 0512H (Access : Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
bit4
MTIF
MTIE
MTC
MTE
0
0
0
0
1
1
1
1
R/W
R(RM0),W
R/W
R1,WX
R/W
R/W
R/W
Attribute R(RM1),W
bit3
bit2
bit1
bit0
MTS[3:0]
Because the main timer is used for generating the oscillation stabilization wait time for main clock (MCLK), it can be
used only after the main clock oscillation is stabilized.
The main timer is cleared when the main clock oscillation stops (MCEN=0) or it is in the stop mode.
When the operation of the main timer is not allowed (MTE=0), the main timer stops except that it is waiting for a
main clock oscillation stabilization. The write operation to this register becomes enabled only when MCRDY=1
except for MTIE. Thus a main timer clear executed by MTC=1 in main clock oscillation stabilization wait status
(MCEN=1 and MCRDY=0) is not effective.
When the main timer stops (MTE=0) it will be cleared and while being cleared MTC=1 will be read out.
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Chapter 5: Clock
At that time the main timer interrupt flag is not set. The main timer overflow period (MTS[3:0]) should be changed at
the time when the main timer stops (MTE=0).
When rewriting MTE=1 with 0, the main timer will continue to operate until the MTC bit is set to "0". In this interval,
the main timer interrupt flag may turn to "1". When writing MTC=1, the main timer will continue to operate until the
MTC bit is set to "0". In this interval, the main timer interrupt flag may turn to "1". If a MTE=0 to 1 rewrite and a
MTC=1 write occur at the same time, the operation starts after a clear takes place, so the start will be delayed.
[bit7] MTIF (Main clock Timer Interrupt Flag) : Main timer interrupt flag
The flag to indicate that an overflow happens in the interval for which the main timer has selected.
When the MTIE bit is "1" and this bit is set, a main timer interrupt request is generated.
Clear
factor
"0" write
A DMA transfer is generated by the main timer interrupt.
An overflow occurred in the interval set by MTS[3:0]
The end of oscillation stabilization wait time of the main clock after setting MCEN=0
to 1.
Set factor
The end of oscillation stabilization wait time of the main clock (MCLK) after exiting
the stop mode. (A set will not take place at the end of oscillation stabilization wait
time after reset by SINIT.)
Writing "1" to this bit is ineffective.
When the MTIE bit is set to "0", this bit will not be cleared by DMA transfer.
For read-modify-write instructions, "1" will be read out.
If a set factor and a clear factor occur at the same time, the set factor will take precedence.
An internal reset is issued at the return from standby mode (power-shutdown), and the main timer interrupt flag is not
set.
[bit6] MTIE (Main clock Timer Interrupt Enable) : Main timer interrupt enable
This bit controls interrupts by main timer overflow as follows.
MTIE
Main timer interrupt
0
Interrupt disabled (Initial value)
1
Interrupt enabled (outputs the interrupt request at the time when the MTIF bit
is "1")
[bit5] MTC (Main clock Timer Clear) : Main timer clear
This bit clears the main timer.
MTC
Write
Read
0
Does nothing.
Operating normally
1
Clear the main timer.
Clearing the main timer
This bit automatically returns to "0" after writing "1".
For read-modify-write instructions, "0" will be read out.
When writing MTC=1 at the time of MTC=1, the second write will be ignored.
[bit4] MTE (Main clock Timer Enable) : Main timer operation enable
This bit controls the operation of the main timer as follows.
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Chapter 5: Clock
MTE
Main timer operation
0
Operation disabled (Initial value)
1
Operation enabled
At the time of MTC=1, MTE=1 write is prohibited.
When you perform a PLL/SSCG clock oscillation stabilization wait, make sure to set this bit to "0" and stop the main
timer.
[bit3 to bit0] MTS[3:0] (Main clock Timer interval Selection) : Main timer interval selection
These bits select the overflow interval of the main timer as follows.
MTS[3:0]
1000
Main timer overflow interval
At 4 MHz
9
128.0[μs]
10
2 × main clock cycle
1001
2 × main clock cycle
256.0[μs]
1010
211 × main clock cycle
512.0[μs]
1011
212 × main clock cycle
1024.0[μs]
1100
13
2048.0[μs]
14
2 × main clock cycle
1101
2 × main clock cycle
4096.0[μs]
1110
215 × main clock cycle
8192.0[μs]
1111
216 × main clock cycle (Initial value)
16384.0[μs]
The MTS[3] always reads "1".
Change MTS[3:0] at the time when the main timer stops (MTE=0).
4.7.
Sub Timer Control Register : STMCR (Sub clock TiMer
Control Register)
The bit configuration of the sub timer control register is shown.
This register controls the sub timer which runs with the sub clock.
STMCR: Address 0513H (Access : Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
bit4
bit3
STIF
STIE
STC
STE
Reserved
0
0
0
0
0
1
1
1
R/W
R(RM0),W
R/W
R0,WX
R/W
R/W
R/W
Attribute R(RM1),W
bit2
bit1
bit0
STS[2:0]
Because the sub timer is used for generating the oscillation stabilization wait time for the sub clock (SBCLK), it can
be used only after the sub clock oscillation is stabilized.
The sub timer is cleared when the sub clock oscillation stops (SCEN=0) or it is in the stop mode.
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Chapter 5: Clock
When the operation of the sub timer is not allowed (STE=0), the sub timer stops except that it is waiting for a sub
clock oscillation stabilization. The write operation to this register becomes enabled only when SCRDY=1 except for
STIE. Thus a sub timer clear executed by STC=1 in sub clock oscillation stabilization wait status (SCEN=1 and
SCRDY=0) is not effective.
When the sub timer stops (STE=0) it will be cleared and while being cleared STC=1 will be read out. At that time the
sub timer interrupt flag is not set. The sub timer overflow period (STS[2:0]) should be changed at the time when the
sub timer stops (STE=0).
When rewriting STE=1 with 0, the sub timer will continue to operate until STC is set to "0". In this interval, the sub
timer interrupt flag may turn to "1". When writing STC=1, the sub timer will continue to operate until STC is set to
"0". In this interval, the sub timer interrupt flag may turn to "1". If a STE=0 to 1 rewrite and a STC=1 write occur at
the same time, the operation starts after a clear takes place, so the start will be delayed.
[bit7] STIF (Sub clock Timer Interrupt Flag) : Sub timer interrupt flag
This flag indicates that an overflow happens in the interval for which the sub timer has selected.
If this bit is set when the STIE bit is "1", a sub timer interrupt request is generated.
"0" write
A DMA transfer is generated by the sub timer interrupt.
Clear
factor
An overflow occurred in the interval set by STS[2:0].
The end of oscillation stabilization wait time of the sub clock after setting SCEN=0
to 1.
Set factor
The ends of oscillation stabilization wait time of the sub clock after exiting the stop
mode.
Writing "1" to this bit is ineffective.
When the STIE bit is set to "0", this bit will not be cleared by DMA transfer.
For read-modify-write instructions, "1" will be read out.
If a set factor and a clear factor occur at the same time, the set factor will take precedence.
An internal reset is issued at the return from standby mode (power-shutdown), and the sub timer interrupt flag is not
set.
[bit6] STIE (Sub clock Timer Interrupt Enable) : Sub timer interrupt enable
This bit controls interrupts by sub timer overflow as follows.
STIE
Sub timer interrupt
0
Interrupt disabled (Initial value)
1
Interrupt enabled (output the interrupt request at the time STIF bit is
"1")
[bit5] STC (Sub clock Timer Clear) : Sub timer clear
This bit clears the sub timer.
STC
210
Write
Read
0
Does nothing.
Operating normally
1
Clear the sub timer.
Clearing the sub timer
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Chapter 5: Clock
This bit automatically returns to "0" after writing "1".
For read-modify-write instructions, "0" will be read out.
When writing STC=1 at the time of STC=1, the second write will be ignored.
[bit4] STE (Sub clock Timer Enable) : Sub timer operation enable
This bit controls the operation of the sub timer as follows.
STE
0
Sub timer operation
Operation disabled (Initial value)
1
Operation enabled
At the time of STC=1, STE=1 write is prohibited.
[bit3] (Reserved)
[bit2 to bit0] STS[2:0] (Sub clock Timer interval Selection) : Sub timer interval selection
These bits select the overflow interval of the sub timer as follows.
STS[2:0]
Sub timer overflow interval
At 32 kHz
At CR clock
selected
000
28 × sub clock cycle
8[ms]
5.12[ms]
001
29 × sub clock cycle
16[ms]
10.24[ms]
010
210 × sub clock cycle
32[ms]
20.48[ms]
011
211 × sub clock cycle
64[ms]
40.96[ms]
100
212 × sub clock cycle
128[ms]
81.92[ms]
101
213 × sub clock cycle
0.256[s]
163.84[ms]
110
214 × sub clock cycle
0.512[s]
327.68[ms]
111
215 × sub clock cycle (Initial value)
1.024[s]
655.36[ms]
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Chapter 5: Clock
4.8.
PLL Setting Register : PLLCR (PLL Configuration
Register)
The bit configuration of the PLL setting register is shown.
This register configures the multiplication rate or division ratio in the PLL/SSCG clock oscillation circuit and the
oscillation stabilization wait time.
PLLCR: Address 0514H (Access : Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,WX
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
POSW[3:0]
Initial value
Attribute
PDS[3:0]
1
1
1
1
0
0
0
0
R1,WX
R,W
R,W
R,W
R,W
R,W
R,W
R,W
This register configures the multiplication rate in the PLL/SSCG clock oscillation circuit generating the PLL/SSCG
clock (PLLSSCLK) from the main clock (MCLK).
When PLL/SSCG clock oscillation is allowed (CSELR.PCEN=1), writing to this register has no effect.
[bit15, bit14] (Reserved)
Always write "0".
[bit13] (Reserved)
[bit12 to bit8] (Reserved)
Always write "0".
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Chapter 5: Clock
[bit7 to bit4] POSW[3:0] (Pll clock OSc Wait) : PLL oscillation stabilization wait selection
These bits select the oscillation stabilization wait time for the PLL/SSCG clock (PLLSSCLK) as follows.
PLL/SSCG clock oscillation
stabilization wait time
POSW[3:0]
At 4 MHz
At 8 MHz
1000
29 × main clock cycle
128.0[μs]
64.0[μs]
1001
210 × main clock cycle
256.0[μs]
128.0[μs]
1010
211 × main clock cycle
512.0[μs]
256.0[μs]
1011
212 × main clock cycle
1024.0[μs]
512.0[μs]
1100
213 × main clock cycle
2048.0[μs]
1024.0[μs]
1101
214 × main clock cycle
4096.0[μs]
2048.0[μs]
1110
215 × main clock cycle
8192.0[μs]
4096.0[μs]
1111
216 × main clock cycle (Initial value)
16384.0[μs]
8192.0[μs]
POSW3 always reads "1".
Note:
The PLL/SSCG clock lock up time wait time specification in this product is 200[μs]. Reserve the 200[μs] wait time or
more by either of the following methods.
Select 256[μs] POSW[3:0] or more.
Reserve the 200[μs] wait time or more by software processing, regardless of POSW[3:0] settings.
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[bit3 to bit0] PDS[3:0] (Pll input clock Divider Selection) : PLL input clock divider selection
These bits select the main clock (MCLK) division for the PLL/SSCG input clock as follows.
PDS[3:0]
PLL/SSCG input clock divider select
0000
PLL/SSCG input clock = Main clock / 1
0001
PLL/SSCG input clock = Main clock / 2
0010
PLL/SSCG input clock = Main clock / 3
0011
PLL/SSCG input clock = Main clock / 4
0100
PLL/SSCG input clock = Main clock / 5
0101
PLL/SSCG input clock = Main clock / 6
0110
PLL/SSCG input clock = Main clock / 7
0111
PLL/SSCG input clock = Main clock / 8
1000
PLL/SSCG input clock = Main clock / 9
1001
PLL/SSCG input clock = Main clock / 10
1010
PLL/SSCG input clock = Main clock / 11
1011
PLL/SSCG input clock = Main clock / 12
1100
PLL/SSCG input clock = Main clock / 13
1101
PLL/SSCG input clock = Main clock / 14
1110
PLL/SSCG input clock = Main clock / 15
1111
PLL/SSCG input clock = Main clock / 16
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
Notes:
Follow the configuration steps for your appropriate PLL/SSCG and system specifications.
See "5.1.3 PLL/SSCG Clock (PLLSSCLK)" for configuration samples.
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Chapter 5: Clock
4.9.
Clock Stabilization Selection Register : CSTBR (Clock
STaBilization selection Register)
The bit configuration of the oscillation stabilization selection register is shown.
This register configures the oscillation stabilization wait for each clock source.
The oscillation stabilization wait time set by this register will be used at the time when returning from the stop/watch
mode. It will also be used for a period from the time when the oscillation of a clock which have not been selected as
the source clock is allowed until the ready status (CMONR:*CRDY) of that clock switches to "1". If an oscillation
stabilization wait is necessary at reset, it will always be set to the stabilization wait time selected as an initial value by
this register. Write operations to MOSW[3:0] will not be effective at the main clock oscillation stabilization wait time
(MCEN=1 and MCRDY=0).
Write operations to SOSW[2:0] will not be effective at the sub clock oscillation stabilization wait time (SCEN=1 and
SCRDY=0).
CSTBR: Address 0516H (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
bit3
SOSW[2:0]
bit2
bit1
bit0
MOSW[3:0]
0
0
0
0
0
0
0
0
R0,WX
R,W
R,W
R,W
R,W
R,W
R,W
R,W
[bit7] (Reserved)
[bit6 to bit4] : SOSW[2:0] (Sub clock OSc Wait) : Sub clock oscillation stabilization wait selection
These bits select the oscillation stabilization wait time for the sub clock (SBCLK) as follows.
SOSW[2:0]
Sub clock oscillation
stabilization wait time
At 32 kHz
At CR clock
selected
000
28 × sub clock cycle (Initial value)
8[ms]
5.12[ms]
001
29 × sub clock cycle
16[ms]
10.24[ms]
010
210 × sub clock cycle
32[ms]
20.48[ms]
011
211 × sub clock cycle
64[ms]
40.96[ms]
100
212 × sub clock cycle
128[ms]
81.92[ms]
101
213 × sub clock cycle
0.256[s]
163.84[ms]
110
214 × sub clock cycle
0.512[s]
327.68[ms]
111
215 × sub clock cycle
1.024[s]
655.36[ms]
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[bit3 to bit0] MOSW[3:0] (Main clock OSc Wait) : Main clock oscillation stabilization wait selection
The main timer interval is set by the set value for MOSW[3:0].
These bits select the oscillation stabilization wait time for the main clock (MCLK) as follows.
MOSW[3:0]
Main clock oscillation stabilization
wait time
At 4 MHz
0000
215 × main clock cycle (Initial value)
0001
21 × main clock cycle
500[ns]
0010
25 × main clock cycle
8[μs]
0011
26 × main clock cycle
16[μs]
0100
27 × main clock cycle
32[μs]
0101
28 × main clock cycle
64[μs]
0110
29 × main clock cycle
128[μs]
0111
210 × main clock cycle
256[μs]
1000
211 × main clock cycle
512[μs]
1001
212 × main clock cycle
1[ms]
1010
213 × main clock cycle
2[ms]
1011
214 × main clock cycle
4[ms]
1100
217 × main clock cycle
33[ms]
1101
219 × main clock cycle
131[ms]
1110
221 × main clock cycle
524[ms]
1111
223 × main clock cycle
2[s]
8[ms]
Note:
Note that the determination detection is done while waiting for the oscillation stability when the cycle of the
determination detection is shorter than a set cycle of this register when the Clock supervisor function is effective.
The period of the failure detection cycle is as follow.
212 ×CR Oscillation time = approx. 40.96 ms
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Chapter 5: Clock
4.10. PLL Oscillation Timer Control Register : PTMCR (PLL
clock osc TiMer Control Register)
The bit configuration of the PLL Oscillation timer control register is shown.
This register controls the timer that works with the main clock that enters PLL/SSCG clock oscillation stabilization
wait.
The PLL/SSCG clock oscillation stabilization wait timer is used only at the oscillation stabilization wait time of the
PLL/SSCG clock.
The PLL/SSCG clock oscillation stabilization wait time becomes time set by PLLCR:POSW[3:0].
When PLL/SSCG clock oscillation is enabled(CSELR.PCEN="1"), PLL/SSCG clock stabilization timer starts
counting up. After the oscillation stabilization time elapses, PLL/SSCG clock stabilization timer stops. Moreover,
when PLL/SSCG clock oscillation stop (CSELR.PCEN ="0") is done, it is cleared.
PTMCR: Address 0517H (Access : Byte, Half-word, Word)
Initial value
bit7
bit6
PTIF
PTIE
0
0
0
0
0
R/W
R0,WX
R0,WX
R0,WX
Attribute R(RM1),W
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] PTIF (Pll clock osc wait Timer Interrupt Flag) : PLL oscillation stabilization wait timer interrupt flag
This flag shows that the overflow at the time set by PLL oscillation stabilization wait selection (PLLCR: POSW
[3:0]) was generated. If this bit is set when the PTIE bit is "1", PLL/SSCG clock oscillation stabilization wait timer
interrupt request is generated.
"0" write
Generation of DMA transfer with PLL/SSCG oscillation stabilization wait timer
Clear
factor
Set factor
End of the oscillation stabilization wait time for PLL/SSCG clock oscillation
stabilization wait clock after PCEN=0 to 1
Writing "1" to this bit is ignored.
When the PTIE bit is "0", the clearness of this bit by the DMA forwarding is not done.
In the read modify write instruction, "1" is read.
The set factor is given priority when a set factor and a clear factor are generated at the same time.
[bit6] PTIE (Pll clock osc wait Timer Interrupt Enable) : PLL oscillation stabilization wait timer interrupt enable
This bit controls the interrupt by the overflow of PLL/SSCG clock oscillation stabilization wait timer as follows.
PTIE
Operation
0
Interrupt disabled (Initial value)
1
Interrupt enabled
(The interrupt request is output when the PTIF bit is "1".)
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[bit5 to bit0] (Reserved)
4.11. PLL/SSCG Clock Selection Register : CCPSSELR (CCtl
Pll/Sscg clock SELection Register)
The bit configuration of the PLL/SSCG clock selection register is shown.
This register selects which to use, PLL or SSCG.
It can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCPSSELR: Address 0520H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
Attribute
bit0
PCSEL
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit7 to bit1] (Reserved)
[bit0] PCSEL (Pll Clock source SELection) : PLL/SSCG Clock source selection
It selects the PLL/SSCG clock source.
PCSEL
PLL or SSCG
0
Select PLL
1
Select SSCG
Note:
SSCG (Because it is unused) always becomes a reset status for PCSEL=0.
The PLL clock is supplied to CAN and OCDU for PCSEL=1.
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Chapter 5: Clock
4.12. PLL/SSCG Output Clock Division Setting Register :
CCPSDIVR (CCtl Pll/Sscg clock DIVision Register)
The bit configuration of the PLL/SSCG output clock division setting register is shown.
This register sets the ratio of dividing frequency of the PLL/SSCG clock.
It can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCPSDIVR: Address 0523H (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
PODS[2:0]
bit3
bit2
Reserved
bit1
bit0
SODS[2:0]
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
[bit7] (Reserved)
[bit6 to bit4] PODS (Pll Oscillator Divider Selection) : Selection of PLL macro oscillation clock dividing
frequency ratio
These bits set the ratio of dividing frequency of the PLL clock.
PODS[2:0]
Dividing frequency ratio setting
000
PLL clock = PLL macro oscillation clock /2
001
PLL clock = PLL macro oscillation clock /4
010
PLL clock = PLL macro oscillation clock /6
011
PLL clock = PLL macro oscillation clock /8
100
PLL clock = PLL macro oscillation clock /10
101
PLL clock = PLL macro oscillation clock /12
110
PLL clock = PLL macro oscillation clock /14
111
PLL clock = PLL macro oscillation clock /16
Note:
These bits can set only the even number dividing frequency. They cannot set the odd number dividing frequency.
Duty of the output clock becomes 50%.
Please set the PLL clock to the following frequencies:
∙ MB91F52xR (144pin) : 80 MHz or less (LQS144/LQN144) / 128 MHz or less (LES144)
∙ MB91F52xU (176pin) : 80 MHz or less (LQP176) / 128 MHz or less (LEP176)
∙ MB91F52xM (208pin) : 128 MHz or less (LQR208/LER208)
∙ MB91F52xY (416pin) : 128 MHz or less (PAB416)
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The operation is not guaranteed if a frequency exceeding the above is set.
[bit3] (Reserved)
[bit2 to bit0] SODS[2:0] (Sscg Oscillator Divider Selection) : Selection of SSCG macro oscillation clock dividing
frequency ratio
These bits set the ratio of the dividing frequency of the SSCG clock.
SODS[2:0]
Dividing frequency ratio setting
000
SSCG clock = SSCG macro oscillation clock /2
001
SSCG clock = SSCG macro oscillation clock /4
010
SSCG clock = SSCG macro oscillation clock /6
011
SSCG clock = SSCG macro oscillation clock /8
100
SSCG clock = SSCG macro oscillation clock /10
101
SSCG clock = SSCG macro oscillation clock /12
110
SSCG clock = SSCG macro oscillation clock /14
111
SSCG clock = SSCG macro oscillation clock /16
Note:
These bits can set only the even number dividing frequency. They cannot set the odd number dividing frequency.
Duty of the output clock becomes 50%.
Please set the SSCG clock to the following frequencies:
∙ MB91F52xR (144pin) : 80 MHz or less (LQS144/LQN144) / 128 MHz or less (LES144)
∙ MB91F52xU (176pin) : 80 MHz or less (LQP176) / 128 MHz or less (LEP176)
∙ MB91F52xM (208pin) : 128 MHz or less (LQR208/LER208)
∙ MB91F52xY (416pin) : 128 MHz or less (PAB416)
The operation is not guaranteed if a frequency exceeding the above is set.
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
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Chapter 5: Clock
4.13. PLL Feedback Division Setting Register : CCPLLFBR (CCtl
PLL FB clock division Register)
The bit configuration of the PLL feedback division setting register is shown.
This register sets the multiple ratio of PLL.
It can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCPLLFBR: Address 0525H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
bit2
bit1
bit0
IDIV[6:0]
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7] (Reserved)
[bit6 to bit0] IDIV[6:0] (pll feedback Input DIVider ratio settings) : PLL macro FB input dividing frequency ratio
setting
These bits set the PLL multiple ratio.
IDIV[6:0]
Dividing frequency ratio setting
0000000 to
0001011
Setting is prohibited
0001100
13
0001101
14
0001110
15
…
……
1100010
99
1100011
100
1100100 to
1111111
Setting is prohibited
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
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4.14. SSCG Feedback Division Setting Register 0 : CCSSFBR0
(CCtl SScg FB clock division Register 0)
The bit configuration of the SSCG feedback division setting register 0 is shown.
This register sets the multiple ratio N of SSCG. The multiple ratio of SSCG becomes P × N together with the setting
of CCSSFBR1.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCSSFBR0: Address 0526H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
NDIV[5:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, bit6] (Reserved)
[bit5 to bit0] NDIV[5:0] (sscg feedback input N-DIVider ratio settings) : SSCG macro FB input N dividing
frequency ratio setting
These bits set the SSCG multiple ratio N.
NDIV[5:0]
Dividing frequency ratio setting
000000
Setting is prohibited
000001
2
000010
3
…
……
111101
62
111110
63
111111
Setting is prohibited
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
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Chapter 5: Clock
4.15. SSCG Feedback Division Setting Register 1 : CCSSFBR1
(CCtl SScg FB clock division Register 1)
The bit configuration of the SSCG feedback division setting register 1 is shown.
This register sets the multiple ratio P of SSCG. The multiplication ratio of SSCG becomes P × N along with the
setting of CCSSFBR0.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCSSFBR1: Address 0527H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
PDIV[4:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] (Reserved)
[bit4 to bit0] PDIV[4:0] (sscg feedback input P-DIVider ratio settings) : SSCG macro FB input P divider
frequency ratio setting
These bits set the SSCG multiple ratio P.
PDIV[4:0]
Dividing frequency ratio setting
00000
1
00001
2
00010
3
…
……
11101
30
11110
31
11111
Setting is prohibited
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
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4.16. SSCG Configuration Setting Register 0 : CCSSCCR0 (CCtl
SSCg Config. Register 0)
The bit configuration of the SSCG configuration setting register 0 is shown.
This register sets various settings of SSCG.
It can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0")
CCSSCCR0: Address 0529H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
bit2
SFREQ[1:0]
bit1
bit0
SMODE
SSEN
0
0
0
1
0
0
0
0
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] (Reserved)
[bit4] (Reserved)
Writing has no effect on operation.
[bit3, bit2] SFREQ[1:0] (Spread spectrum modulation FREQuency settings) : Spread spectrum modulation
frequency settings
These bits set the spread spectrum modulation frequency of SSCG.
SFREQ[1:0]
Modulation frequency
00
1/1024
01
1/2048
1x
1/4096
[bit1] SMODE (Spread spectrum modulation MODE settings) : Spread spectrum modulation mode settings
This bit sets the spread spectrum modulation mode of SSCG.
224
SMODE
Modulation mode
0
Down Spread
1
Center Spread
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Chapter 5: Clock
Down Spread
Cycle to cycle jitter
Target
modulation rate
time
Period
1/Modulation frequency
Center Spread
Cycle to cycle jitter
modulation rate
Target
time
Period
1/Modulation frequency
[bit0] SSEN (Spread Spectrum ENable) : Spread spectrum enable
This bit enables spread spectrum of SSCG.
SSEN
Spread spectrum enable
0
Spread spectrum disabled
1
Spread spectrum enabled
Note:
Spread spectrum modulation rate becomes 0% regardless of a setting of the CCSSCCR1:RATESEL when SSEN is set
disabled.
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4.17. SSCG Configuration Setting Register 1 : CCSSCCR1 (CCtl
SSCg Config. Register 1)
The bit configuration of the SSCG configuration setting register 1 is shown.
This register sets various settings of SSCG.
It can be written only when PLL/SSCG clock oscillation stops. (CSELR.PCEN = "0").
CCSSCCR1: Address 052AH (Access : Half-word, Word)
bit15
bit14
bit13
bit12
bit11
RATESEL[2:0]
Initial value
Attribute
bit10
bit9
bit8
Reserved
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R0,WX
R0,WX
R0,WX
R/W0
R/W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
[bit15 to bit13] RATESEL[2:0] (spread spectrum modulation RATE SELection) : Spread spectrum modulation
rate selection
These bits set the spread spectrum modulation rate of SSCG.
RATESEL[2:0]
Modulation rate
00x
0.5%
010
1%
011
2%
100
3%
101
4%
110
5%
111
Setting is prohibited
[bit12 to bit10] (Reserved)
Writing to these bits has no effect.
[bit9 to bit0] (Reserved)
Always write "0" to these bits.
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Chapter 5: Clock
4.18. Clock Gear Configuration Setting Register 0 : CCCGRCR0
(CCtl Clock GeaR Config. Register 0)
The bit configuration of the clock gear configuration setting register 0 is shown.
This register sets various settings of clock gear.
CCCGRCR0: Address 052DH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
GRSTS[1:0]
Initial value
Attribute
bit3
bit2
Reserved
bit1
bit0
GRSTR
GREN
0
0
0
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R(RM0),W1
R/W
[bit7, bit6] GRSTS[1:0] (clock GeaR STatuS flags) : Clock gear status flags
These bits display the status of Clock gear.
GRSTS[1:0]
Status
00
Stop in the state of clock gear low-speed oscillation or
No use of clock gear (CCCGRCR0.GREN=0) or
In the status of PLL/SSCG reset (CSELR.PCEN=0)
01
In operation of GEAR UP
10
Stop in the status of clock gear high-speed oscillation
11
In operation of GEAR DOWN
[bit5 to bit2] (Reserved)
[bit1] GRSTR (clock GeaR STaRt) : Clock gear start
Writing "1" to this bit starts the operation of clock gear.
The operation of clock gear depends on the value of the GRSTS bits. (Gear up or gear down)
When GRSTS=00
GRSTR
Operation
"0" write
Not affect the operation
"1" write
Start the operation of gear up
When GRSTS=01/11
GRSTR
Operation
"0" write
Not affect the operation
"1" write
Not affect the operation
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When GRSTS=10
GRSTR
Operation
"0" write
Not affect the operation
"1" write
Start the operation of gear down
Notes:
This bit can be written only when CSELR.CKS=10 (PLL/SSCG clock (PLLSSCLK) selection) and
CCCGRCR0.GREN=1 (clock gear enable).
This bit is automatically cleared to "0" after the operation of clock gear up (down) complete. Also, this bit is
cleared to "0" when CSELR.PCEN=0 (PLL/SSCG clock oscillation stopped).
If a read-modify-write instruction is executed, "0" is always read from this bit. When writing is executed while
this bit is "1", writing for the second and subsequent times is ignored.
[bit0] GREN (clock GeaR ENable) : Clock gear enable
This bit enables the operation of clock gear.
GREN
Operation
0
No use of clock gear
1
Use of clock gear
Note:
This bit can be written only when PLL/SSCG clock oscillation is stopped (CSELR.PCEN = "0").
4.19. Clock Gear Configuration Setting Register 1 : CCCGRCR1
(CCtl Clock GeaR Config. Register 1)
The bit configuration of the clock gear configuration setting register 1 is shown.
This register sets various settings of clock gear.
It can be written only when PLL/SSCG clock oscillation is stopped (CSELR.PCEN = "0").
CCCGRCR1 : Address 052EH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
GRSTP[1:0]
Initial value
Attribute
228
bit3
bit2
bit1
bit0
GRSTN[5:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Chapter 5: Clock
[bit7, bit6] GRSTP[1:0] (clock GeaR STeP selection) : Clock gear step selection
These bits select the step number at the time of clock gear up/down (the number of increment /decrement).
GRSTP[1:0]
Step number
00
1
01
2
10
3
11
4
[bit5 to bit0] GRSTN[5:0] (clock GeaR STart step Number selection) : Clock gear start step number selection
These bits select the step number at the start of clock gear operation between 0 and 63.
GRSTN[5:0]
Step number
000000
0
000001
1
000010
2
…
……
111101
61
111110
62
111111
63
Note:
The gear does not operate at GRSTN =111111(number 63 of steps) setting.
4.20. Clock Gear Configuration Setting Register 2 : CCCGRCR2
(CCtl Clock GeaR Config. Register 2)
The bit configuration of the division setting register 0 is shown.
This register sets various settings of clock gear.
It can be written only when PLL/SSCG clock oscillation is stopped. (CSELR.PCEN = "0").
CCCGRCR2 : Address 052FH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
GRLP[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Chapter 5: Clock
[bit7 to bit0] GRLP[7:0] (clock GeaR LooP number selection) : Clock gear loop number selection
These bits select the loop number of one step. The setting enabled number of iteration is between 1 to 256. Step is
incremented/decremented when the number set to this bit is completed.
GRLP[7:0]
Loop number
0000_0000
1
0000_0001
2
0000_0010
3
…
……
1111_1101
254
1111_1110
255
1111_1111
256
4.21. RTC/PMU Clock Selection Register : CCRTSELR (CCtl RTc
pmu clock SELection Register)
The bit configuration of the division setting register 0 is shown.
This register selects the RTC/PMU clock source.
CCRTSELR : Address 0530H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
CST
Initial value
bit3
bit2
bit1
Reserved
*
0
0
0
bit0
CSC
0
0
0
*
Attribute R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
*: These bits are initialized to "0". But these bits are not initialized by the return from the watch mode
(power-shutdown).
[bit7] CST (Clock source selection STatus monitor): Clock source selection status monitor
A time lag by clock switch occurs until the CSC register is written and the clock switch completes. Whether the
switch completes or not is monitored by this bit.
CST
Monitor
0
Completion of clock switch
1
During clock switch
Note:
Normally, switch completes by main clock × about 3 cycles + sub clock × about 3 cycles.
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Chapter 5: Clock
[bit6 to bit1] (Reserved)
[bit0] CSC (Clock SourCe selection) : Clock source selection
Selects clock of RTC/PMU.
CSC
Clock source
0
Main oscillation clock
1
Sub oscillation clock
Notes:
The CSC register can be rewritten only when SCRDY=1 and MCRDY=1.
It takes main clock × about 3 cycles + sub clock × about 3 cycles until the switch operation of RTC and PMU
clock completes after rewriting the CSC register. When main clock and sub clock oscillation are stopped during
the switching operation, the switching operation does not complete correctly. The oscillation must always be
stopped in the status that the CST register is "0" (the status of the completion of switching).
[MB91F52xxxC/MB91F52xxxE]
The CSC bit and the CST bit are not initialized by the return from the standby watch mode (power-shutdown).
Moreover, any reset factors other than those, caused by power on reset/internal low-voltage reset/RSTX-NMIX
simultaneous assertion, cannot be accepted because an internal reset signal is generated while returning from
the standby watch mode (power-shutdown). At this time the CSC bit and the CST bit are not initialized.
Initialize these bits in case of need, when the reset signal comes from RSTX terminal input or external
low-voltage detection is flagged after the return from power-shutdown.
[MB91F52xxxD]
The CSC bit and the CST bit are not initialized by the return from the standby watch mode
(power-shutdown).Moreover, any reset factors other than those, caused by power on reset/internal low-voltage
reset/RSTX assertion, cannot be accepted because an internal reset signal is generated while returning from the
standby watch mode (power-shutdown). At this time the CSC bit and the CST bit are not initialized. Initialize
these bits in case of need, when the reset signal comes from RSTX terminal input or external low-voltage
detection is flagged after the return from power-shutdown.
4.22. PMU Clock Division Setting Register 0 : CCPMUCR0 (CCtl
PMU Clock division Register 0)
The bit configuration of the division setting register 0 is shown.
This register sets the clock dividing frequency of the PMU.
CCPMUCR0 : Address 0532H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
FST
Initial value
Attribute
bit4
bit3
bit2
bit1
Reserved
bit0
FDIV[1:0]
0
0
0
0
0
0
0
0
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
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Chapter 5: Clock
[bit7] FST (F-divider STatus monitor): F-divider status monitor
A time lag by clock switch occurs until FDIV[1:0] register is written and the written value is reflected. Whether the
setting value is reflected can be monitored by this bit.
Normally, it takes RTC clock × about 4 cycles + PCLK1 × about 4 cycles to reflect the setting value of the register.
FST
Monitor
0
Completion of reflecting the written value
1
During reflecting the written value
[bit6 to bit2] (Reserved)
[bit1, bit0] FDIV[1:0] (F-DIVide ratio setting): F-divide ratio setting
These bits set the division rate of F-divider. The clock equal to or less than 32 kHz must be provided with PMU.
When CCRTSELR.CSC=0 (selection of main clock), this bit is set to be equal to or less than 32 kHz by F divider.
FDIV[1:0]
Division rate
Target main oscillation frequency
00
Divided by 128 (Initial value)
4 MHz
01
Divided by 256
8 MHz
10
Divided by 384
12 MHz
11
Divided by 512
16 MHz
Note:
Writing to this bit is ignored while the CCPMUCR0.FST bit is "1".
When CCRTSELR.CSC=1 (selection of sub oscillation clock), the F-division rate becomes undivided in spite of the
value of this bit.
4.23. PMU Clock Division Setting Register 1 : CCPMUCR1 (CCtl
PMU Clock division Register 1)
The bit configuration of the division setting register 0 is shown.
This register sets the clock dividing frequency of the PMU.
CCPMUCR1 : Address 0533H (Access : Byte, Half-word, Word)
bit7
bit6
GST
Initial value
Attribute
232
bit5
bit4
bit3
Reserved
bit2
bit1
bit0
GDIV[4:0]
0
0
0
0
0
0
0
0
R,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
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Chapter 5: Clock
[bit7] GST (G-divider STatus monitor): G-divider status monitor
A time lag by clock switch occurs until GDIV[4:0] register is written and the written value is reflected. Whether the
setting value is reflected can be monitored by this bit.
Normally, it takes RTC clock × about 4 cycles + PCLK1 × about 4 cycles to reflect the setting value of the register.
GST
Monitor
0
Completion of reflecting the written value
1
During reflecting the written value
Note:
Writing to CCPMUCR1.GDIV[4:0] is ignored while this bit is "1".
[bit6, bit5] (Reserved)
[bit4 to bit0] GDIV[4:0] (G-DIVide ratio setting) : G-divide ratio setting
These bits set the division rate of G-divider. The period of the PMU clock must be equal to or greater than four times
the period of the bus clock (APB) which is provided with PMU. The division rate of the PMU clock is set by this
divider to meet the above relation.
GDIV[4:0]
Division rate
00000
No divide (Initial value)
00001
2
00010
3
…
……
11101
30
11110
31
11111
32
Note:
Writing to this bit is ignored while CCPMUCR1.GST bit is "1".
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Chapter 5: Clock
4.24. Sync/Async Control Register : SACR
The bit configuration of the sync/async control register is shown.
This register selects the peripheral clock.
SACR : Address 1000H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
Attribute
bit0
M
1
1
1
1
1
1
1
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
[bit7 to bit1] (Reserved)
[bit0] M : Synchronous/asynchronous setting register of peripheral clock
This bit switches the peripheral clock when CPU selects the SSCG clock.
M
Synchronous/asynchronous setting
0
Synchronous (PLL/SSCG clock for CPU/peripheral)
1
Asynchronous (PLL/SSCG clock for CPU, PLL clock for peripheral)
4.25. Peripheral Interface Clock Divider : PICD
The bit configuration of peripheral interface clock divider is shown.
This register sets the dividing frequency of the peripheral clock.
PICD : Address 1001H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
1
Attribute R1,WX
bit1
bit0
PDIV[3:0]
1
1
1
0
0
1
1
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
[bit7 to bit4] (Reserved)
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Chapter 5: Clock
[bit3 to bit0] PDIV[3:0] : Peripheral clock division radio setting
These bits set the ratio of dividing frequency of the peripheral clock (PCLK2) from the PLL clock (PLLCLK) [non
spread spectrum clock] at SACR.M=1.
PDIV[3:0]
PLL clock (PLLCLK)[non spread spectrum clock]
→ PCLK2 division ratio
0000
No divide
0001
2 division
0010
3 division
0011
4 division (initial value)
0100
5 division
0101
6 division
0110
7 division
0111
8 division
1000
9 division
1001
10 division
1010
11 division
1011
12 division
1100
13 division
1101
14 division
1110
15 division
1111
16 division
Note:
Set this register so that the peripheral clock (PCLK2) definitely becomes 40 MHz or less.
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Chapter 5: Clock
5. Operation
This section explains operations of clock.
5.1Oscillation Control
5.2Oscillation Stabilization Wait
5.3Selecting the Source Clock (SRCCLK)
5.4Timer
5.5Notes when Clocks Conflict
5.6The Clock Gear Circuit
5.7Operations during MDI Communications
5.8About PMU clock (PMUCLK)
5.1.
Oscillation Control
This section explains oscillation control.
5.1.1.
Main Clock (MCLK)
The main clock (MCLK) is shown.
The oscillation of the main clock stops on any of the following conditions.
SINIT reset (See "CHAPTER: RESET")
During the stop mode
While the sub clock (SBCLK) is selected as the source clock and "0" is set to CSELR.MCEN
After all the above conditions of the oscillation stop are cancelled and then the oscillation stabilization wait time
which is set to CSTBR.MOSW[3:0] goes by, supplying the clock starts. The oscillation stabilization wait time
specified by the initial value is required because CSTBR.MOSW[3:0] is initialized at the time of return from the reset
input.
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Chapter 5: Clock
5.1.2.
Sub Clock (SBCLK)
The sub clock (SBCLK) is shown.
The oscillation of the sub clock stops on any of the following conditions.
After the occurrence of reset (the bus idle wait time before stop is required. See "CHAPTER: RESET".)
During the stop mode
While a clock other than the sub clock (SBCLK) are selected as the source clock and "0" is set to CSELR.SCEN
bit.
When the clock is used as a port because the clock is used for sub oscillation and port (in cases without sub
oscillation).
After all the above conditions of the oscillation stop are cancelled and then the oscillation stabilization wait time
which is set to CSTBR.SOSW[2:0] goes by, supplying the clock starts. The sub clock oscillation stops until "1" is set
to because CSELR.SCEN is initialized to "0" at the time of return from the reset input or the INIT status.
5.1.3.
PLL/SSCG Clock (PLLSSCLK)
The PLL/SSCG clock (PLLSSCLK) is shown.
This LSI has PLL and SSCG (PLL which generates spread spectrum clock) and can select SSCG for reducing noise.
The combinations of clocks which CPU and peripheral functions can select are as follows.
Table 5-1 Clock Mode
Clock mode
RUN1
RUN2
RUN3
CPU
PLL
SSCG
SSCG
CAN
PLL
PLL
PLL
Peripheral
PLL
SSCG
PLL
OCDU
PLL
PLL
PLL
The CPU/Peripheral (timer/communication) clock is selected by CCPSSELR.PCSEL. Also, when CPU is operated by
the SSCG clock, peripheral (timer/communications) can be operated by the PLL clock. In this case, the peripheral
clock is selected by SACR.M and divided by PICD.PDIV[3:0].
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Chapter 5: Clock
Note:
When the CPU is operated by SSCG and the peripherals are operated by PLL, because the asynchronization transfer
enters between CPU/ Peripheral, the penalty of 5 ×PCLK2 to 8×PCLK2 is added to the access cycle. In this case, the
frequency of PCLK2 must be same as that of PCLK1. Select synchronization with SACR:M when you want to make
both CPU/Peripheral operation with the PLL clock.
The oscillation of the PLL/SSCG clock (PLLSSCLK) stops on any of the following conditions.
After the occurrence of reset (the bus idle wait time before stop is required. See "CHAPTER: RESET".)
While the main clock oscillation stops (PCEN=0)
During the time of main clock oscillation stabilization wait (PCEN=0)
During the watch mode
While a clock other than the PLL/SSCG clock (PLLSSCLK) are selected as the source clock and "0" is set to
CSELR.PCEN.
After all the above conditions of the oscillation stop are cancelled and then PLL/SSCG clock lock wait time which is
set to PLLCR.POSW[3:0] goes by, supplying the clock starts. The PLL/SSCG clock oscillation stops until "1" is set
to because CSELR.PCEN is initialized to "0" at the time of return from the reset input or the INIT status.
The formula for calculating the clock frequency and the multiplication rate related to PLL/SSCG is as follows:
(PLL/SSCG setting in Microcontroller unit)
PLL/SSCG input clock frequency = (main oscillation frequency) / (PLLCR.PDS[3:0] division ratio)
PLL multiplication rate = (CCPLLFBR.IDIV[6:0] FB input division ratio)
SSCG multiplication rate = (CCSSFBR0.NDIV[5:0] FB input division ratio) (CCSSFBR1.PDIV[4:0] FB
input division ratio)
PLL macro oscillation clock frequency = (PLL/SSCG input clock frequency) PLL multiplication rate
SSCG macro oscillation clock frequency = (PLL/SSCG input clock frequency) SSCG multiplication rate
PLL clock frequency = (PLL macro oscillation clock frequency) / (CCPSDIVR.PODS[2:0] division ratio)
SSCG clock frequency = (SSCG macro oscillation clock frequency) / (CCPSDIVR.SODS[2:0] division ratio)
Figure 5-1 PLL Peripheral Block Diagram
PLLCR.
PDS[3:0]
PLL
CCPSDIVR.
PODS[2:0]
CCPLLFBR.
IDIV[6:0]
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Chapter 5: Clock
Figure 5-2 SSCG Peripheral Block Diagram
SSCG
PLLCR.
PDS[3:0]
CCPSDIVR.
SODS[2:0]
CCSSFBR0.NDIV[5:0]
×
CCSSFBR1.PDIV[4:0]
PLL/SSCG input clock, PLL/SSCG multiplication rate and PLL/SSCG macro oscillation clock must be set within the
operating condition ranges for built-in PLL/SSCG in this series.
For the operating condition ranges of PLL/SSCG, see the following notes.
Notes:
In debug operation, PLL cannot stop because always supplying the PLL clock is required for MDI communication.
Interrupts cannot be transferred normally in switching PLL-SSCG. Therefore, when switching PLL-SSCG
synchronous/asynchronous, disable the interrupt from resource.
The PLL/SSCG macro oscillation clock frequency has the upper bound and the lower bound.
Set the multiplication rate of PLL/SSCG so as not to exceed the following range.
PLL/SSCG in Microcontroller unit :
200 MHz ≤ PLL macro oscillation clock frequency ≤ 320 MHz
200 MHz ≤ SSCG macro oscillation clock frequency ≤ 320 MHz (Down Speed)
5.1.4.
Limitations when PLL/SSCG Clock is used
The limitations of the PLL/SSCG clock used are shown.
Use the PLL/SSCG clock according to the following limitations.
Clock Control PLL Clock Frequency
Frequency
FCTLR:FAW
(max)
128 MHz
80 MHz
01
00
CCPSSELR:
PCSEL
Remarks
0
0
Note:
Set PLLCR or CCPSDIVR and CCPLLFBR so as not to exceed frequency (max).
The frequency (max) is as follows:
∙ MB91F52xR (144 pin): 80 MHz (LQS144/LQN144) / 128 MHz (LES144)
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Chapter 5: Clock
∙ MB91F52xU (176 pin): 80 MHz (LQP176) / 128 MHz (LEP176)
∙ MB91F52xM (208 pin): 128 MHz (LQR208/LER208)
∙ MB91F52xY (416 pin): 128 MHz (PAB416)
Microcontroller Unit Clock Control SSCG Clock Frequency
FCTL CCPSSEL CCSSCC
CCSSCC
Frequency
R:
R:
R0:
R0:
(max)
FAW
PCSEL
SSEN
SMODE
CCSSCC
R1:
RATESEL
128 MHz
116 MHz
116 MHz
01
01
01
1
1
1
0
1
1
0/1
0
1
000 to 110
000 to 110
000
116 MHz
115 MHz
115 MHz
114 MHz
114 MHz
80 MHz
72 MHz
01
01
01
01
01
00
00
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0/1
0
010
011
100
101
110
000 to 110
000 to 110
72 MHz
00
1
1
1
000
72 MHz
72 MHz
71 MHz
71 MHz
70 MHz
00
00
00
00
00
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010
011
100
101
110
Remarks
Spread 0%
Down Spread
Center Spread
(0.5%)
Center Spread (1%)
Center Spread (2%)
Center Spread (3%)
Center Spread (4%)
Center Spread (5%)
Spread 0%
Down Spread
Center Spread
(0.5%)
Center Spread (1%)
Center Spread (2%)
Center Spread (3%)
Center Spread (4%)
Center Spread (5%)
Note:
Set CCPSDIVR, CCSSFBR0 and CCSSFBR1 so as not to exceed frequency (max).
The frequency (max) is as follows:
∙ MB91F52xR (144 pin): 80 MHz (LQS144/LQN144) / 128 MHz (LES144)
∙ MB91F52xU (176 pin): 80 MHz (LQP176) / 128 MHz (LEP176)
∙ MB91F52xM (208 pin): 128 MHz (LQR208/LER208)
∙ MB91F52xY (416 pin): 128 MHz (PAB416)
Relation between Modulation Rate and Division Ratio when SSCG is Used
CCSSCCR1:RATESEL[2:0]
CCSSFBR0:NDIV[5:0]
Set
Range of
Set value
Set value
Modulation rate
value
division ratio
lower limit
upper limit
0.50%
1.00%
2.00%
3.00%
4.00%
5.00%
240
00x
010
011
100
101
110
8 - 60
8 - 60
8 - 48
8 - 31
8 - 23
8 - 18
7H
7H
7H
7H
7H
7H
3BH
3BH
2FH
1EH
16H
11H
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Chapter 5: Clock
5.2.
Oscillation Stabilization Wait
Oscillation stabilization wait is shown.
This section describes oscillation stabilization wait for each clock input.
5.2.1.
Conditions for Generating Stabilization Wait Time
Conditions for generating stabilization wait time are shown.
The cancellation of the oscillation stop control for each clock enters the oscillation stabilization wait status. After the
oscillation stabilization wait time specified by each clock, the oscillation stabilization wait status is cancelled and
supplying clock restarts.
The main (MCLK) clock enters the oscillation stabilization wait status when the oscillation stops before cancellation
of reset because the setting register is initialized by reset. The main clock does not enter the oscillation stabilization
wait status when the main clock oscillates by reset of INIT and RST level because the main clock oscillation does not
stop by reset of INIT and RST level.
5.2.2.
Selecting Stabilization Wait Time
Selecting the stabilization wait time is shown.
The stabilization wait time for each clock can be changed by setting of CSTBR and PLLCR.
Initial values after reset for clock oscillation stabilization wait time
Main clock
PLL/SSCG clock
Sub clock
: CSTBR.MOSW[3:0] bit
: PLLCR.POSW[3:0] bit
: CSTBR.SOSW[2:0] bit
215× main clock period
216× main clock period
28× sub clock period
The main oscillation stabilization wait time is always specified by the initial value because CSTBR.MOSW[3:0] is
initialized by reset (INIT or RST). Except that case, the main oscillation stabilization wait time can be changed by
setting to CSTBR.MOSW[3:0].
The PLL/SSCG clock lock wait time is always specified by the initial value because PLLCR.POSW[3:0] is initialized
by reset (INIT or RST). Except that case, the PLL/SSCG clock lock wait time can be changed by setting to
PLLCR.POSW[3:0]. Set "1" to CSELR.PCEN after setting to PLLCR.POSW[3:0]. For details, see the explanation of
POSW in "4.8 PLL Setting Register : PLLCR (PLL Configuration Register)".
The sub oscillation stabilization wait time is always specified by the initial value because CSTBR.SOSW[2:0] is
initialized by reset (INIT or RST). Except that case, the sub oscillation stabilization wait time can be changed by
setting to CSTBR.SOSW[2:0].
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Chapter 5: Clock
5.2.3.
End of the Stabilization Wait Time
The end of the stabilization wait time is shown.
The operations are stopped while the clock which is selected as a source clock is the status of the oscillation
stabilization wait time. The operations restart after the end of the oscillation stabilization wait time. You can verify
that the clock which is not selected as the source clock has entered the oscillation stabilization wait time by checking
the value of the ready bit corresponding to each clock for CMONR register when each clock is enabled.
Display of the clock oscillation stabilization wait status
Main clock
: CMONR:MCRDY ="0" ,
PLL/SSCG clock (PLLSSCLK) : CMONR:PCRDY ="0" ,
Sub clock (SBCLK)
: CMONR:SCRDY ="0" ,
5.3.
Display of the oscillation stabilization status
CMONR:MCRDY ="1"
CMONR:PCRDY ="1"
CMONR:SCRDY ="1"
Selecting the Source Clock (SRCCLK)
Selecting the source clock (SRCCLK) is shown.
This section explains the selection control of the source clock (SRCCLK) which functions as the operation clock.
5.3.1.
Selecting the Source Clock at the Time of Initialization
Selecting the source clock at the time of initialization is shown.
After reset (RST) the main clock (MCLK) divided by 2 is selected as the source clock. After program operation the
source clock can be changed by setting CSELR.CKS[1:0].
5.3.2.
Procedure of switching the source clock
The procedure of switching the source clock is shown.
The source clock (SRCCLK) cannot be directly switched from the PLL/SSCG clock (PLLSSCLK) to the sub clock
(SBCLK) and from the sub clock to the PLL/SSCG clock. Switch the main clock divided by 2 once. Set the
oscillation stop as necessary because the value of the oscillation enable bit (CSELR.xCEN) is held, even though the
source clock is switched.
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Chapter 5: Clock
Figure 5-3 Procedure of Switching the Source Clock
Division of main
clock by 2
Sub clock
PLL/SSCG
clock
×
1. The main clock divided by 2→PLL/SSCG clock
While selecting the main clock divided by 2 as the source clock (CMONR.CKM[1:0]=00)
↓
PLL/SSCG multiplication rate, SSCG modulation, PLL/SSCG selection, setting PLL/SSCG clock lock wait time
(setting PLLCR/ CCPSSELR/ CCPSDIVR/ CCPLLFBR/ CCSSFBR0/ CCSSFBR1/ CCSSCCR0/
CCSSCCR1) --when PLL oscillation is not enabled-↓
Sets clock gear (CCCGRCR0.GREN/CCCGRCR1/CCCGRCR2)
↓
Clears PLL/SSCG clock oscillation stabilization wait timer interrupt source (PTIF=0)
↓
(as necessary) Sets PLL/SSCG clock oscillation stabilization wait timer interrupt enable (PTIE=1)
↓
PLL/SSCG clock oscillation begins (PCEN=0 to 1)
↓
PLL/SSCG clock lock wait loop (loop until when PCRDY=1), or interrupt wait
↓
PLL/SSCG clock oscillation stabilization wait timer interrupt clear (PTIF=0, PTIE=0)
↓
Switches from the source clock to PLL/SSCG clock (CSELR.CKS[1:0]=00 to 10)
↓
The clock gear begins (CCCGRCR0.GRSTR=1)
↓
Verifies that the clock gear high-speed oscillation is stopped (CCCGRCR0.GRSTS[1:0]=10)
↓
While selecting PLL/SSCG clock as the source clock (CMONR.CKM[1:0]=10)
2. PLL/SSCG clock→the main clock divided by 2
While selecting PLL/SSCG clock as the source clock (CMONR.CKM[1:0]=10)
↓
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Chapter 5: Clock
Clock gear begins (CCCGRCR0.GRSTR=1)
↓
Verifies that the clock gear low-speed oscillation is stopped (CCCGRCR0.GRSTS[1:0]=00)
↓
Switches the source clock to the main clock divided by 2 (CSELR.CKS[1:0]=10 to 00)
↓
While selecting the main clock as the source clock (CMONR.CKM[1:0]=00)
3. The main clock divide by 2→sub clock
While selecting the main clock divided by 2 as the source clock (CMONR.CKM[1:0]=01)
↓
Sets the sub clock oscillation stabilization wait time (sets CSTBR.SOSW[2:0])
–when sub oscillation is not enabled–
↓
Clears the sub timer interrupt source (STIF=0)
↓
(as necessary) Sets sub timer interrupt enable (STIE=1)
↓
In a single clock product, selecting the CR clock as a sub-clock source
(CSVCR.SCKS=1)
↓
The sub clock oscillation begins (SCEN=0 to 1)
↓
Sub clock oscillation stabilization wait loop (loop until when SCRDY=1), or interrupt wait
↓
Clears sub timer interrupt (STIF=0)
↓
Switches the source clock to the sub clock (CSELR.CKS[1:0]=01 to 11)
↓
While selecting the sub clock as the source clock (CMONR.CKM[1:0]=11)
4. The sub clock→the main clock divided by 2
While selecting the sub clock as the source clock (CMONR.CKM[1:0]=11)
↓
Sets the main clock oscillation stabilization wait time (sets CSTBR.MOSW[3:0])
– when the main oscillation is not enabled–
↓
Clears the main timer interrupt source (MTIF=0)
↓
(as necessary) Sets the main timer interrupt enable (MTIE=1)
↓
The main clock oscillation begins (MCEN=0 to 1)
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Chapter 5: Clock
↓
The main clock oscillation stabilization wait loop (loop until MCRDY=1), or interrupt wait
↓
Clears the main timer interrupt (MTIF=0)
↓
Switches the source clock to the main clock divided by 2 (CSELR.CKS[1:0]= 11 to 01)
↓
While selecting the main clock as the source clock (CMONR.CKM[1:0]=01)
↓
In a single clock product, returning the sub clock source setting
The sub clock oscillation stops (CSELR:SCEN=1 to 0)
↓
The CR clock is not selected as a sub-clock (CSVCR:SCKS=1 to 0)
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Chapter 5: Clock
Figure 5-4 Example of PLL/SSCG Mode Setting Main PLL/SSCG
Start
Main clock mode is confirmed
CSELR.CKS=00
CMONR.CKM=00
No
Yes
Yes
PLLCR.POSW
PLL/SSCG clock stabilization wait time is set
No
Is the SSCG used?
The SSCG use is judged
Yes
Yes
SSCG is selected
PLLCR.PDS
CCPSDIVR.PODS
CCPLLFBR.IDIV
Multiplication rate of PLL is set
CCPSSELR.PCSEL=1
PLL is selected
CCPSSELR.PCSEL=0
Multiplication rate of PLL is set
PLLCR.PDS
CCPSDIVR.PODS
CCPLLFBR.IDIV
(For CAN and OCD)
Multiplication rate of SSCG is set
CCPSDIVR.SODS
CCSSFBR0.NDIV
CCSSFBR1.PDIV
The method of SSCG's spread is set
CCSSCCR0.SFREQ
CCSSCCR0.SMODE
CCSSCCR0.SSEN
CCSSCCR1.RATESEL
No
The gear use is judged
Is the gear used?
Yes
Yes
CCCGRCR0.GREN=1
The gear is set to the valid status
The gear step is set
CCCGRCR1.GRSTP
CCCGRCR1.GRSTN
CCCGRCR2.GRLP
Is the interrupt used?
The gear is set to the invalid status
CCCGRCR0.GREN=0
No
Yes
PLL/SSCG clock oscillation stabilization wait timer
interrupt flag is cleared
Yes
PTMCR.PTIF=0
PTMCR.PTIE=0
PLL/SSCG clock oscillation stabilization
wait timer interrupt is set effective
CSELR.PCEN=1
The operation of PLL/SSCG is started
CSELR.PCEN=1
PLL/SSCG clock oscillation
stabilization is fixed
CMONR.PCRDY=1
PLL Oscillation stabilization
wait timer interrupt generation
The operation of PLL/SSCG is started
The PLL/SSCG clock operation stability is judged
No
Yes
DIVR0.DIVB
DIVR2.DIVP
Peripheral resource
Asynchronously ?
Dividing various clocks (CPU/Peripheral) is set
No
When SSCG is used, whether peripheral resource operates with PLL clock is judged
When PLL is used, synchronization is always selected
Yes
Yes
PICD.PDIV
Dividing the asynchronous peripheral clock is set
SACR.M=1
The relation of the CPU/peripheral clock
is set asynchronously
FCTLR.FAW
The relation of the CPU/peripheral clock is set
synchronously
When PLL/SSCG clock exceeds 80 MHz, wait cycle is inserted into FLASH access
The source clock is changed to the PLL/SSCG clock
CSELR.CKS=10
CMONR.CKM=10
SACR.M=0
No
It is confirmed that the source clock is switched to PLL/SSCG
Yes
No
Is the gear used?
When the gear is used, the gear is started
Yes
CCCGRCR0.GRSTS=00
No
It is confirmed that the clock
is stopped at low-speed
Yes
Yes
CCCGRCR0.GRSTR=1
CCCGRCR0.GRSTS=10
Gear is started
No
The gear completion is confirmed
Yes
Yes
PLL/SSCG operation
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Chapter 5: Clock
Figure 5-5 Example of PLL/SSCG Mode Setting PLL/SSCG Main
Start
No
CSELR.CKS=10
CMONR.CKM=10
PLL/SSCG clock mode is confirmed
Yes
No
Is the gear used?
The gear use is judged
Yes
CCCGRCR0.GRSTS=10
No
It is confirmed that the clock is stopped at high-speed
Yes
CCCGRCR0.GRSTR=1
Gear is started
No
The gear completion is confirmed
CCCGRCR0.GRSTS=00
Yes
CSELR.CKS=00
The source clock is changed to the main clock
No
CMONR.CKM=00
It is confirmed that the source clock is switched to the main clock
Yes
CSELR.PCEN=0
The operation of PLL/SSCG is stopped
FCTLR.FAW
When PLL/SSCG clock exceeds 80 MHz, FLASH access is set to no wait, again
DIVR0.DIVB
DIVR2.DIVP
Dividing various clocks (CPU/Peripheral) is set
When SSCG is used, whether peripheral resource operates with PLL clock is judged
Peripheral resource
Asynchronously ?
No
When PLL is used, it is always synchronization
Yes
SACR.M=0
The relation of the CPU/peripheral clock is set synchronously
Main operation
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Chapter 5: Clock
5.4.
Timer
The timer is shown.
5.4.1.
Main Clock Oscillation Stabilization Wait Timer (Main
Timer)
The main clock oscillation stabilization wait timer (Main Timer) is shown.
The main timer is operated by the main clock (MCLK). This timer is used for the generation of the main clock
oscillation stabilization wait time, and in main clock stabilization statuses other than those for oscillation stabilization
wait, it can be used as the timer that generates an interrupt after the specified period.
Note:
If main timer is used as source for recovering from the watch mode with power-shutdown, set the interrupt
level to ‘31’, before CPU state changes to the watch mode with power-shutdown.
5.4.2.
Sub Clock Oscillation Stabilization Wait Timer (Sub
Timer)
The sub clock oscillation stabilization wait timer (Sub Timer) is shown.
The sub timer is operated by the sub clock (SBCLK). This timer is used for the generation of the main clock
oscillation stabilization wait time, and in main clock stabilization statuses other than those for oscillation stabilization
wait, it can be used as the timer that generates an interrupt after the specified period.
Note:
If sub timer is used as source for recovering from the watch mode with power-shutdown, set the interrupt
level to ‘31’, before CPU state changes to the watch mode with power-shutdown.
5.4.3.
PLL/SSCG Clock Oscillation Stabilization Wait timer
(PLL Timer)
The PLL/SSCG clock oscillation stabilization wait timer (PLL Timer) is shown.
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Chapter 5: Clock
The PLL timer is operated by the main clock and only for generation of the PLL/SSCG oscillation stabilization wait
time. This timer cannot be used for a general-purposed timer.
5.4.4.
Setting
Setting is shown.
If the main timer operation is enabled (MTMCR.MTE=1), the count operation of the main timer starts. If the main
timer operation is disabled (MTMCR.MTE=0), the count operation of the main timer stops and the main timer is
cleared.
If the main timer is set to clear (MTMCR.MTC=1), it is cleared. MTMCR.MTC=1 is read until clear. The period of
interrupt can be set by MTMCR.MTS[3:0]. When MTMCR.MTIE=1, if MTMCR.MTIF=1, the main timer interrupt
occurs. MTMCR.MTIF is cleared by writing "0".
If the sub timer operation is enabled (STMCR.STE=1), the count operation of the sub timer starts. If the sub timer
operation is disabled (STMCR.STE=0), the count operation of the sub timer stops and the sub timer is cleared.
If the sub timer is cleared (STMCR.STC=1), the sub timer is cleared. STMCR.STC=1 is read until clear. The period
of interrupt can be set by STMCR.STS[2:0]. When STMCR.STIE=1, if STMCR.STIF=1, the sub timer interrupt
occurs. STMCR.STIF is cleared by writing "0".
Note:
For setting the period of the timer interrupt (MTS and STS), set the period to equal to or greater than PCLK x 5 clock.
When the period of the timer interrupt is set to the extremely short time, the interrupt factor may not be set.
5.4.5.
Procedure for Setting the Timer Interrupt
The procedure for setting the timer interrupt is shown.
This section describes the procedure for setting interrupt. The examples of the procedure for setting interrupt are
shown as follows.
Sets the timer interrupt disable (MTMCR.MTIE=0)/(STMCR.STIE=0)
and the interrupt flag clear(MTMCR.MTIF=0)/(STMCR.STIF=0)
↓
Sets the timer operation disable (MTMCR.MTE=0)/(STMCR.STE=0)
↓
Verifies MTC=0/STC=0
↓
Sets the period of the timer (MTMCR.MTS=1000 to 1111)/(STMCR.STS=000 to 111)
↓
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Chapter 5: Clock
Sets the timer interrupt enable (MTMCR.MTIE=1)/(STMCR.STIE=1)
↓
Sets the timer operation enable (MTMCR.MTE=1)/(STMCR.STE=1)
↓
The interrupt occurs after setting time
↓
To the interrupt routine
↓
Sets the interrupt flag clear (MTMCR.MTIF=0)/(STMCR.STIF=0)
↓
Verifies the interrupt flag (MTMCR.MTIF=0)/(MTMCR.STIF=0)
↓
Program operations
↓
RETI
Note:
Repeat reading until "0" is read because actual setting of the interrupt flag clear is delayed.
5.4.6.
Timer Operations
Timer operations are shown.
While MTMCR.MTE=1, the main timer counts up by the main clock (MCLK). If the timer overflows by the period
which is selected by MTMCR.MTS[3:0], MTMCR.MTIF is "1".
While STMCR.STE=1, the sub timer counts up by the sub clock (SBCLK). If the timer overflows by the period
which is selected by STMCR.STS[2:0], STMCR.STIF is "1".
5.4.7.
Watch Mode and Timer Interrupt
Watch mode and timer interrupt are shown.
Watch mode stops the specific functions and all operations other than timer. (See "CHAPTER: POWER
CONSUMPTION CONTROL") The wake-up from the watch mode is enabled by using main/sub timer interrupt or
RTC interrupt. The example for switching of the watch mode in the setting of wake-up from the sub timer is shown as
follows.
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Chapter 5: Clock
Figure 5-6 Wake-up from the Watch Mode
Sub clock selection
Sub timer setting
Watch mode setting
Sub watch mode
Wakeup
Sub timer
OVF
Interrupt
Wakeup
Note:
If main/sub timer or real-time clock is used as source for recovering from the watch mode with
power-shutdown, set the interrupt level to ‘31’, before CPU state changes to the watch mode with
power-shutdown.
5.5.
Notes when Clocks Conflict
Notes when clocks conflict is shown.
Note that if peripheral interrupt activated by the very low frequency lower than the CPU clock (CCLK) in the
interrupt handler is cleared and the interrupt handler is immediately stopped, the peripheral cannot complete the
internal process within the period of interrupt handler and the interrupt handler may be called in duplicate.
5.6.
The Clock Gear Circuit
The clock gear circuit is shown.
When the main clock is switched to the PLL/SSCG clock or the PLL/SSCG clock is switched to the main clock, the
power supply current fluctuates widely because the frequency fluctuates rapidly. Using the clock gear circuit in the
part of the clock switching can gradually fluctuate the operating frequency from a low frequency to a high frequency
or from a high frequency to a low frequency and therefore can reduce the fluctuation of the power supply current.
5.6.1.
Procedure of Gear Up
The procedure of gear up is shown.
1.
2.
3.
The clock of the start step set to the clock gear start step selection is output after the oscillation stabilization
wait timer completes.
When the clock gear start (CCCGRCR0:GRSTR) is set to "1" and the rising is detected, the clock gear status
flag (CCCGRCR0:GRSTS[1:0]) transits from "00" to "01" (gear up start).
The gear up is executed according to the clock gear step selection and the repeat number selection. The step
number is the smaller and the repeat number is the larger that the operation changes the more gradually.
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Chapter 5: Clock
4.
5.
5.6.2.
When the clock reaches the maximum step, the clock gear status flag (CCCGRCR0.GRSTS[1:0]) transits from
"01" to "10" (the end of gear up, the gear stops).
After this, a clock is output at the maximum step (64 steps).
After the gear stops, the clock gear start (CCCGRCR0.GRSTR) is cleared to "0" by hardware.
Procedure of Gear Down
The procedure of gear down is shown.
1.
2.
3.
4.
5.7.
When the clock gear start (CCCGRCR0.GRSTR) is set to "1" and the rising is detected, the clock gear status
flag (CCCGRCR0.GRSTS[1:0]) transits from "10" to "11" (gear down start).
The gear down is executed according to the clock gear step selection and the repeat number selection. The step
number is the smaller and the repeat number is the larger that the operation changes the more gradually.
When the clock reaches the minimum step, the clock gear status flag (CCCGRCR0.GRSTS[1:0]) transits from
"11" to "00" (the end of gear down, the gear stops).
After this, the clock of the start step set for the clock gear start step selection is output.
After the gear stops, the clock gear start (CCCGRCR0.GRSTR) is cleared to "0" by hardware.
Operations during MDI Communications
Operations during MDI communications are shown.
The main oscillation is controlled so as not to be stopped during MDI communications even if the stop mode is
transited to.
Moreover, during MDI high speed communication, the main oscillation is controlled so that the PLL reference clock
is supplied even if CSELR.PCEN is cleared. The value of the register related to PLL is maintained and not updated.
However, when software sets PLLCR.PCEN=0, the value of the register related to PLL can be freely updated (write).
When a value set to the register related to PLL last time and a different value are written and the PLL/SSCG clock
oscillation permission is assumed to be effective (CSELR.PCEN=1), the frequency of the PLL clock is not updated.
(PLL : because it maintains the locked status.)
Normally, always write the same value in the register related to PLL.
Note:
The registers related to PLL are as follows.
CCPSDIVR.PODS
CCPLLFBR.IDIV
PLLCR.PDS
5.8.
About PMU clock (PMUCLK)
The PMU clock (PMUCLK) is shown.
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Chapter 5: Clock
The PMU clock is an operation clock of power management unit (PMU). Complete the setting of this clock before
controlling the standby mode.
Figure 5-7 Watch/Power Management Clock Generation Unit
CCRTSELR.CSC
MCLK
0
SBCLK
1
RTC clock
(WATCLK)
Main clock
divider (F-divider)
0
PMU clock
divider (G-divider)
1
(1 to 32division)
(128 to 512division)
CCPMUCR0:FDIV
PMU clock
(PMUCLK)
CCPMUCR1:GDIV
The frequency of the PMU clock can be calculated by the following expressions.
When CCRTSELR:CSC=0 (main clock is selected)
PMU clock frequency=
(Main clock frequency) / (CCPMUCR0: FDIV [1:0] division ratio) / (CCPMUCR1:GDIV[4:0]
division ratio)
When CCRTSELR:CSC=1 (sub clock is selected)
PMU clock frequency=(Sub clock frequency) / (CCPMUCR1:GDIV[4:0] division ratio)
Moreover, observe the following specification limitation to the PMU clock. (There is a possibility that the shutdown
processing is not normally done when this limitation is not defended.)
(1) CCRTSELR:CSC must be set to select active clock that is under oscillation.
(2) F-divider must be set so that the PMU clock frequency become 32 kHz or less.
(3) G-divider must be set so that PMU clock frequency become 1/4 or less of the peripheral clock frequency
(PCLK1).
The following explains each specification limitation.
(1) Select the clock under oscillation by setting the CCRTSELR:CSC bit.
Please confirm the CMONR: MCRDY bit and the CMONR: SCRDY bit to the oscillation of the main clock and a
sub-clock. Moreover, when the CCRTSELR:CSC bit is rewritten, the processing of the handshaking of the main
clock and a sub-clock (clock transfer) is generated. During this period, if both clocks are not oscillating
(CMONR:MCRDY=CMONR:SCRDY=1), the change operation is not normally completed. Please confirm the
status of the clock transfer by the CCRTSELR:CST bit.
(2) Set F-divider so that the PMU clock frequency become 32 kHz or less.
The PMU clock must be used to control the power switch, and the frequency of 32 kHz or less for the reasons for
the stabilization at the pressure rise time when the power supply is input etc.
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Chapter 5: Clock
As for the PMU clock, the main clock is selected for CCRTSELR:CSC=0 as a source clock. Please set the
CCPMUCR0:FDIV register so that the frequency of the PMU clock may become 32 kHz or less. When
CCRTSELR:CSC=1, the F-divider does not affect the operation.
FDIV[1:0]
Division rate
Target main oscillation
frequency
00
128 division(initial value)
4 MHz
01
256 division
8 MHz
10
384 division
12 MHz
11
512 division
16 MHz
(3) Set G-divider so that PMU clock frequency become 1/4 or less of the peripheral clock frequency (PCLK1).
Clock transfer between peripheral clock (PCLK1) and PMU clock (PMUCLK) needs 4 PMU clock cycles.
When the source clock of peripheral clock(PCLK1) is sub oscillation clock (CMONR.CKM="10"), set the
CCPMUCR1.GDIV register so that the frequency of peripheral clock(PCLK1) is quadruple or higher the
frequency of PMU clock.
Also, even when the source clock of the peripheral clock (PCLK1) is the main clock divided by 2
(CMONR.CKM="00" or CMONR.CKM="01"), and when the peripheral clock (PCLK1) is equal to or less than
128 kHz (32 kHz × 4) in the setting of DIVR0.DIVB and DIVR2.DIVP, CCPMUCR1.GDIV register should be
set similarly.
GDIV[4:0]
Division ratio
00000
No divide (initial value)
00001
2 division
•••
•••
11110
31 division
11111
32 division
[Reference]
The frequency of the peripheral clock (PCLK1) can be calculated by the following expressions.
Peripheral clock (PCLK1) frequency=(Clock frequency selected by CMONR.CKM) / (DIVR0.DIVB[2:0] division
ratio) /(DIVR2.DIVP[3:0] division ratio)
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Chapter 6: FlexRay Dedicated Clock
This chapter describes the FlexRay dedicated clock.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Settings
6.
Clock Auto-Gear Up/Down
7.
Operation
8.
Notes
Code : BERAYPLL-1v0-91528-3-E
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255
Chapter 6: FlexRay Dedicated Clock
1. Overview
This section provides an overview of the FlexRay dedicated clock.
This model is equipped with a PLL for FlexRay in addition to a PLL for the source clock of the CPU core.
This product performs PLL oscillation control and clock control for FlexRay.
Figure 1-1 Block Diagram
On-chip bus clock
(HCLK)
FlexRay
on-chip bus clock
(HCLK)
PLL clock
(PLLCLK)
Clock
source
selection
Main clock
(MCLK)
FlexRay
system clock
(SCLK)
FlexRay
PLL control
FlexRay PLL output
FlexRay PLL auto gear output
(for clock monitor output)
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Chapter 6: FlexRay Dedicated Clock
2. Features
This section describes the features of the FlexRay dedicated clock.
・ Freely programmable PLL multiplication rate
・ Clock auto gear up/down function for preventing voltage drops and surges
・ FlexRay system clock (SCLK) source selection function
・ Interrupt generation function that responds to detection of FlexRay PLL macro deadlock state
3. Configuration
This section describes the configuration of the FlexRay dedicated clock.
FlexRay
on-chip bus clock
(HCLK)
On-chip bus clock
(HCLK)
PLL clock
(PLLCLK)
PLL2DIVK:
Function
DVK
0
No division
1
Division by 2
Main clock
(MCLK)
PLL2DIVG
PLL2MULG
CLKPLL
(FlexRay)
FlexRay
system clock
(SCLK)
Clock
source
selection
CLKVCO Division
Division
by K
by G
Division
FlexRay
PLL
M
U
X
by M
PLL2DIVM
CLKR2:
CLKS1-0
00
01
10
11
Function
HCLK
PLLCLK
CLKPLL (FlexRay)
Reserved
PLL2DIVN
FlexRay PLL auto gear output
(for clock monitor output)
CLKR2:
PLL2EN
0
1
Function
Stops PLL
Enables PLL
FlexRay PLL output
(for clock monitor output)
Note:
If "FlexRay PLLCLK"(CLKR2:CLKS[1:0]=10) is selected as the clock source, the values of registers PLL2DIVM,
PLL2DIVN, PLL2DIVG, and PLL2MULG cannot be changed.
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Chapter 6: FlexRay Dedicated Clock
4. Registers
This section provides an overview of the registers of the FlexRay dedicated clock.
Table 4-1 Registers Map
Address
Registers
+0
+1
+2
+3
Register Function
0x04D0
FlexRay PLL multiplication rate
(divide-by-M) selection register
FlexRay PLL multiplication rate
(divide-by-N) selection register
PLL2DIVM PLL2DIVN PLL2DIVG PLL2MULG
FlexRay PLL auto gear multiplication rate
(divide-by-G) selection register
FlexRay PLL divide-by-G step
multiplication rate selection register
0x04D4
Auto gear control register
FlexRay PLL multiplication rate
(divide-by-K) selection register
FlexRay PLL clock output control register
258
PLL2CTRL PLL2DIVK
CLKR2
Reserved
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Chapter 6: FlexRay Dedicated Clock
4.1.
FlexRay PLL Division (Divide-by-M) Selection Register:
PLL2DIVM
This section describes the bit configuration of the FlexRay PLL frequency division (divide-by-M)
selection register.
This register selects the FlexRay PLL clock frequency division.
PLL2DIVM: 04D0H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial
value
Attribute
bit3
bit2
bit1
bit0
DVM3
DVM2
DVM1
DVM0
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit7 to bit4] (Reserved)
"0" is always read from these bits. Writing to these bits has no effect on the operation.
[bit3 to bit0] DVM3 to DVM0: CLKVCO divide-by-M selection
DIM3 to DIM0
CLKVCO Divided by M (Generation Φ : CLKPLL)
0000
CLKVCO:1 (no division)
0001
CLKVCO:2 (division by 2)
0010
CLKVCO:3 (division by 3)
0011
CLKVCO:4 (division by 4)
0100
CLKVCO:5 (division by 5)
0101
CLKVCO:6 (division by 6)
0110
CLKVCO:7 (division by 7)
0111
CLKVCO:8 (division by 8)
...
1111
...
CLKVCO:16 (division by 16)
Notes:
・ The output clock generated is in an odd clock duty ratio (PLL direct output). Always select a division ratio of at
least "1" or more and an even division ratio (:2, :4, :6, etc.) for the divide-by-M counter.
・ The output clock generated is in an odd clock duty ratio. Always select an even division ratio (:2, :4, :6, etc.) for
the divide-by-M counter.
・ If CLKPLL(FlexRay) is selected as the clock source, the register value cannot be changed
(CLKR2:CLKS[1:0]=10).
・ When changing the PLL2DIVM and PLL2DIVN registers, you must stop the PLL(CLKR2:PLL2EN=0), and then
enabling the PLL(CLKR2:PLL2EN=1).
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Chapter 6: FlexRay Dedicated Clock
4.2.
FlexRay PLL Multiplication Rate (Divide-by-N) Selection
Register: PLL2DIVN
This section describes the bit configuration of the FlexRay PLL multiplication rate (divide-by-N)
selection register.
This register selects the multiplication rate from the PLL input clock to the FlexRay PLL clock.
PLL2DIVN: 04D1H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
DVN6
DVN5
DVN4
DVN3
DVN2
DVN1
DVN0
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
value
Attribute
[bit7] (Reserved)
"0" is always read from this bit. Writing to this bit has no effect on the operation.
[bit6 to bit0] DVN6 to DVN0: CLKVCO divide-by-N selection
DVN6 to DVN0
CLKVCO Divided by N
0000000
CLKVCO:1 (no division)
0000001
CLKVCO:2 (division by 2)
0000010
CLKVCO:3 (division by 3)
0000011
CLKVCO:4 (division by 4)
0000100
CLKVCO:5 (division by 5)
0000101
CLKVCO:6 (division by 6)
0000110
CLKVCO:7 (division by 7)
0000111
CLKVCO:8 (division by 8)
...
1111111
...
CLKVCO:128 (division by 128)
Notes:
・ If CLKPLL(FlexRay) is selected as the clock source, the register value cannot be changed
(CLKR2:CLKS[1:0]=10).
・ When changing the PLL2DIVM and PLL2DIVN registers, you must stop the FlexRay PLL(CLKR2:PLL2EN=0),
and then enabling the FlexRay PLL(CLKR2:PLL2EN=1).
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4.3.
FlexRay PLL Auto Gear Multiplication Rate (Divide-by-G)
Selection Register: PLL2DIVG
This section describes the bit configuration of the FlexRay PLL auto gear multiplication rate
(divide-by-G) selection register.
This register selects the multiplication rate for the FlexRay PLL clock gear.
PLL2DIVG: Address 04D2H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial
value
Attribute
bit3
bit2
bit1
bit0
DVG3
DVG2
DVG1
DVG0
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit7 to bit4] (Reserved)
"0" is always read from these bits. Writing to these bits has no effect on the operation.
[bit3 to bit0] DVG3 to DVG0: PLL auto gear start/end divide-by-G selection
DVG3 to DVG0
PLL Output Divide-by-G Start/End Frequency
0000
Auto gear disabled (initial value)
0001
CLKVCO:2 (division by 2)
0010
CLKVCO:3 (division by 3)
0011
CLKVCO:4 (division by 4)
0100
CLKVCO:5 (division by 5)
0101
CLKVCO:6 (division by 6)
0110
CLKVCO:7 (division by 7)
0111
CLKVCO:8 (division by 8)
...
1111
...
CLKVCO:16 (division by 16)
Notes:
・ For details on how to use this function, see the section "Clock Auto-Gear Up/Down".
・ Always select an even division ratio (:2, :4, :6, etc.) for divide-by-G counter.
・ The register value cannot be changed once CLKPLL(FlexRay) is selected as the clock source
(CLKR2:CLKS[1:0]=10).
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4.4.
FlexRay PLL Divide-by-G Step Multiplication Rate
Selection Register: PLL2MULG
This section describes the bit configuration of the FlexRay PLL divide-by-G step multiplication rate
selection register.
This register selects the step multiplication rate for the auto gear.
PLL2MULG: Address 04D3H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MLG7
MLG6
MLG5
MLG4
MLG3
MLG2
MLG1
MLG0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
value
Attribute
[bit7 to bit0] MLG7 to MLG0: PLL auto gear divide-by-G step multiplication rate selection
MLG7 to MLG0
Divide-by-G Step Multiplication Rate
00000000
Divide-by-G step x 1 (multiplication by 1)
00000001
Divide-by-G step x 2 (multiplication by 2)
00000010
Divide-by-G step x 3 (multiplication by 3)
00000011
Divide-by-G step x 4 (multiplication by 4)
00000100
Divide-by-G step x 5 (multiplication by 5)
00000101
Divide-by-G step x 6 (multiplication by 6)
00000110
Divide-by-G step x 7 (multiplication by 7)
00000111
Divide-by-G step x 8 (multiplication by 8)
...
11111111
...
Divide-by-G step x 256 (multiplication by 256)
Notes:
・ For details on how to use this function, see the section "Clock Auto-Gear Up/Down".
・ If the CLKPLL(FlexRay) is selected as the clock source, the register value cannot be changed
(CLKR2:CLKS[1:0]=10).
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Chapter 6: FlexRay Dedicated Clock
4.5.
Auto Gear Control Register: PLL2CTRL
This section describes the bit configuration of the auto gear control register.
This register sets the operation control of the auto gear.
PLL2CTRL: Address 04D4H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial
value
Attribute
bit3
bit2
bit1
bit0
IEDN
GRDN
IEUP
GRUP
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R(RM1),W
R/W
R(RM1),W
[bit7 to bit4] (Reserved)
"0" is always read from these bits. Writing to these bits has no effect on the operation.
[bit3] IEDN: Interrupt enable gear down
IEDN
Function
0
Disable gear down interrupt (initial value)
1
Enable gear down interrupt
・ If you need to receive an interrupt after switching to gear down, make the setting to enable interrupts.
[bit2] GRDN: Interrupt flag gear down
GRDN
Function
0
Deactivate gear down interrupt (initial value)
1
Activate gear down interrupt
・ If the divide-by-G counter reaches the programmed end value, this flag is set when switching from clock
source:CLKPLL(FlexRay) to clock source:HCLK.
・ With a read-modify-write instruction, "1" is read from this bit. Writing "1" to this bit has no effect on the operation.
[bit1] IEUP: Interrupt enable gear up
IEUP
Function
0
Disable gear up interrupt (initial value)
1
Enable gear up interrupt
・ If you need to receive an interrupt after switching to gear up, make the setting to enable interrupts.
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Chapter 6: FlexRay Dedicated Clock
[bit0] GRUP: Interrupt flag gear up
GRUP
Function
0
Deactivate gear up interrupt (initial value)
1
Activate gear up interrupt
・ If the divide-by-G counter reaches the end value defined by the divide-by-M counter, this flag is set when
switching from clock source:HCLK to clock source:CLKPLL(FlexRay).
・ With a read-modify-write instruction, "1" is read from this bit. Writing "1" to this bit has no effect on the operation.
4.6.
FlexRay PLL Multiplication Rate (Divide-by-K) Selection
Register: PLL2DIVK
This section describes the bit configuration of the FlexRay PLL multiplication rate (divide-by-K)
selection register.
This register selects FlexRay PLL clock division.
PLL2DIVK: 04D5H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial
value
Attribute
bit0
DVK
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit7 to bit1] (Reserved)
"0" is always read from these bits. Writing to these bits has no effect on the operation.
[bit0] DVK: MCLK divide-by-K selection
This bit selects the division of the main clock of the FlexRay PLL input clock (MCLK) as follows:
DVK
MCLK (PLL Input Clock) Divided by K
0
MCLK / 1 (no division)
1
MCLK / 2 (division by 2)
Notes:
・ If CLKPLL(FlexRay) is selected as the clock source, the register value (CLKR2:CLKS[1:0]=10) cannot be
changed.
・ If you set the main clock (MCLK) of the FlexRay PLL input clock to 16 MHz, set this bit to "1". For a setting
example, see the section " ".
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Chapter 6: FlexRay Dedicated Clock
4.7.
FlexRay PLL Clock Output Control Register: CLKR2
This section describes the bit configuration of the FlexRay PLL clock output control register.
This register sets the operation control of FlexRay.
CLKR2: Address 04D6H (Access: Byte, Half-word, Word)
bit7
FPOVF
Initial
value
Attribute
bit6
bit5
FPOVIR FPOVIE
bit4
bit3
Reserved
bit2
bit1
bit0
PLL2EN
CLKS1
CLKS0
0
0
0
0
0
0
0
0
R,WX
R(RM1),W
R/W
R/W0
R0,W0
R/W
R/W
R/W
[bit7] FPOVF: FlexRay PLL alarm flag
This flag indicates that the FlexRay PLL macro detected the deadlock state.
FPOVF
Detection of FlexRay PLL Deadlock State
0
Normal lock state
1
Deadlock state
[bit6] FPOVIR: FlexRay PLL alarm interrupt request flag
This flag indicates a request for the FlexRay PLL macro alarm interrupt. When this bit is "1" and the FlexRay PLL
alarm interrupt request (FPOVIE) is "1", a FlexRay PLL alarm interrupt is generated. When a read-modify-write
instruction is performed, "1" is read.
FPOVIR
When Reading
When Writing
0
Normal lock state
Clears flag
1
Deadlock state
Invalid
[bit5] FPOVIE: FlexRay PLL alarm interrupt request enable
This bit sets whether to generate a FlexRay PLL alarm interrupt request when the FlexRay PLL alarm interrupt
request flag becomes "1".
FPOVIE
FlexRay PLL Alarm Interrupt Request Enable
0
Disable interrupt request
1
Enable interrupt request
[bit4, bit3] (Reserved)
Always write "0" to these bits.
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Chapter 6: FlexRay Dedicated Clock
[bit2] PLL2EN: FlexRay PLL selection enable
This bit sets the operation of the FlexRay PLL as follows:
PLL2EN
Function
0
Stop FlexRay PLL (initial value)
1
Enable FlexRay PLL operation
・ When the CLKPLL(FlexRay) is selected as the clock source (CLKS[1:0]=10), changing the FlexRay PLL
operation enable bit (PLL2EN) is prohibited.
[bit1, bit0] CLKS1, CLKS0: SCLK output selection
These bits set the selection of SCLK output from the FlexRay PLL-I/F as follows.
CLKS1, CLKS0
Function (SCLK Output Selection)
00
HCLK (initial value)
01
PLLCLK
10
CLKPLL (FlexRay)
11
Reserved
・ When you use FlexRay, set CLKS[1:0]=10.
5. Settings
This section describes the settings for the FlexRay dedicated clock.
FlexRay PLL-I/F settings
Main Clock
(MCLK)
[MHz]
Clock Gear
Parameter
PLL2DIVN:
DVN
PLL2DIVG:
DVG
PLL2MULG:
MLG
FlexRay PLL
Output
(CLKVCO)
[MHz]
0011
100_1111
0000
0000_0000
320
80
0011
010_0111
0000
0000_0000
320
80
Frequency Parameter
PLL2DIVK:
DVK
PLL2DIVM:
DVM
4
0
16
1
FlexRay Clock
(SCLK)
[MHz]
・ When you use FlexRay, you set the values in the table above.
Note:
Set the FlexRay dedicated clock to 80 MHz.
Frequency Calculation
・ FlexRay PLL input frequency = (Main clock frequency)/(PLL2DIVK.DVK division ratio)
・ FlexRay PLL multiplication rate = (PLL2DIVN.DVN[6:0] multiplication rate)
・ FlexRay PLL output frequency = (FlexRay PLL input clock frequency) x FlexRay PLL multiplication rate
・ FlexRay clock frequency = (FlexRay PLL macro oscillation clock frequency) / (PLL2DIVM.DVM[3:0] division
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Chapter 6: FlexRay Dedicated Clock
ratio)
PLL2DIVK.
DVK
FlexRay
PLL
PLL2DIVM.
DVM[3:0]
PLL2DIVN.
DVN[6:0]
Note:
The FlexRay PLL macro oscillation clock frequency has an upper limit and a lower limit. Set the PLL multiplication
rate so that it stays within the following upper and lower limits:
200 MHz PLL macro oscillation clock frequency 400 MHz
6. Clock Auto-Gear Up/Down
This section describes the up/down operation of the clock auto gear of the FlexRay dedicated clock.
To avoid voltage drops and surges when you switch the clock source from oscillation to high frequency PLL output
(or vice versa), the FlexRay PLL interface is equipped with a circuit that performs smooth clock gear up and gear
down.
The main functions are implemented using two division counters (divide-by-M counter and divide-by-G counter).
With the divide-by-M counter, the target frequency is specified for PLL feedback.
Conversely, with the divide-by-G counter, the frequency rises from a programmable division specified with the
divide-by-G setting (PLL2DIVG:DVG) to the target frequency specified with the divide-by-M setting
(PLL2DIVM:DVM), and falls from the divide-by-M setting (PLL2DIVM:DVM) down to the programmable end
frequency (PLL2DIVG:DVG).
When you change the system clock from a low frequency to a high frequency (gear up) or from a high frequency to a
low frequency (gear down), only the setting of PLL2DIVG:DVG > PLL2DIVM:DVM is the valid clock gear
specification.
Frequency step is performed with a multiplier of the PLL output frequency as follows:
Oscillator = 4 MHz, M = 4, N = 80 (This means, assuming that PLL output = 320 MHz and frequency output to C
unit = 80 MHz, the frequency multiplier is N = 80.)
The gear divider can be set to an arbitrary even divider.
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Chapter 6: FlexRay Dedicated Clock
Setting Example
If PLL2DIVG:DVG=4 and PLL2MULG:MLG=20, following gear up is performed when switch is made from
oscillation to PLL.
1. Step: 1-cycle 16.0 MHz (16.0 MHz results in a 20-cycle PLL output.)
2. Step: 2-cycle 16.8 MHz (16.8 MHz results in a 19-cycle PLL output.)
3. Step: 3-cycle 17.8 MHz (17.8 MHz results in an 18-cycle PLL output.)
:
16. Step: 16-cycle 64.0 MHz (64.0 MHz results in a 5-cycle PLL output.)
17. Step: 17-cycle 80.0 MHz (80.0 MHz results in a 4-cycle PLL output.)
18. Step: 18-cycle 106.7 MHz (106.7 MHz results in a 3-cycle PLL output.)
19. Step: 19-cycle 160.0 MHz (160.0 MHz results in a 2-cycle PLL output.)
-> Target frequency reached in the transition to the final step (from 16. to 17. in this case)
Each step can be multiplied by setting a multiplication rate in the gear multiplication rate register.
The duration from generating the start frequency up to reaching the target frequency can be calculated by the following
formula.
𝑖
𝑖
duration = mul⋅t⋅ [∑ 𝑘 ⋅ (𝑖 − 𝑘 + 1) − ∑ 𝑘 ⋅ (𝑖 − 𝑘 + 1)]
𝑘=1
𝑘=𝑗+1
This formula equals the following formula (resolved closed arithmetic series of the first sum term):
𝑖
𝑖 ⋅ (𝑖 + 1) ⋅ (𝑖 + 2)
duration = mul⋅t⋅ [
− ∑ 𝑘 ⋅ (𝑖 − 𝑘 + 1)]
6
𝑘=𝑗+1
i = G, j = G - M, mul = PLL2MULG:MLG, t = 1/f(PLLOUT)
For the above setting, this equals 1483 PLL output clock cycles with a duration from the start frequency to the target
frequency of 9262500 ps (about 9.3 ms).
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Chapter 6: FlexRay Dedicated Clock
7. Operation
This section describes the setting of the FlexRay PLL clock.
Procedure for setting the clock (Example)
Start
Set PLL divided by K (PLL2DIVK)
Set PLL divided by M (PLL2DIVM)
Set PLL divided by N (PLL2DIVN)
Select PLL auto gear start/stop divided by G (PLL2DIVG)
Set only when using gear function.
Select PLL auto gear divide-by-G step multiplication rate (PLL2MULG)
Enable FlexRay PLL operation (CLKR2:PLL2EN)
NO
Is PLL oscillation stable?
YES
Switch clock supplied to FlexRay (SCLK) to PLLCLK(FlexRay)
(CLKR2:CLKS[1:0] = 10)
End
・ Use the main timer to wait for FlexRay PLL stabilization, and wait for the switching time.
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Chapter 6: FlexRay Dedicated Clock
8. Notes
This section describes notes on the FlexRay dedicated clock.
Clock Auto Gear
When you use the clock auto gear function, you must use the gear-up and gear-down flags (PLL2CTRL:GRUP,
PLL2CTRL:GRDN) to confirm the current state of this function. Doing so will enable you to prevent malfunctions in
the clock system caused by setting changes prior to completion.
Procedure Example:
(1) Set the FlexRay PLL interface registers (PLL2DIVN, PLL2DIVM, PLL2DIVG, PLL2MULG) according to the
selected frequency and the gear duration.
(2) Set the FlexRay PLL to on (CLKR2:PLL2EN=1).
(3) If any interrupts are received after the gearing up or gearing down, enable the corresponding interrupts as well
(PLL2CTRL:IEUP, PLL2CTRL:IEDN).
(4) Wait for PLL stabilization time. The stabilization wait time is 200µs.
(5) Switch the clock source to PLLCLK2 (CLKR2:CLKS[1:0] "00" -> "10").
(6) Wait for the PLL2CTRL:GRUP gear up flag (by polling or interrupt) before returning the clock source back to
HCLK, or check the setting of PLL2CTRL:GRUP = 1 before changing the bits in the CLKR2 register.
(7) Switch the clock source to HCLK (CLKR2:CLKS[1:0] "10" -> "00").
(8) Wait for the PLL2CTRL:GRDN gear down flag (by polling or interrupt) before returning the clock source back
to PLLCLK2, or check the setting of PLL2CTRL:GRDN = 1 before changing the bits in the CLKR2 register.
(9) Set the FlexRay PLL off (CLKR2:PLL2EN = 0).
FlexRay PLL Control
After the initialization, the oscillation of the FlexRay PLL stops. While it is stopped, you cannot select the FlexRay
PLL output as the clock source.
After the program starts, first make the setting for the multiplier of FlexRay PLL to be used as the clock source, wait
until the FlexRay PLL is locked, and then change the clock source. If you wait until the FlexRay PLL is locked, you
must use a main timer interrupt.
If the FlexRay PLL output is selected as the clock source, you cannot stop the FlexRay PLL.
Writing to the register has no effect. If you need to stop the FlexRay PLL such as when switching to the stop mode
etc., first select the on-chip bus clock (HCLK) as the clock source, and then stop the FlexRay PLL.
FlexRay PLL multiplier
When you change the setting for the FlexRay PLL multiplier to a value other than the initial value, you need to do it
at the same time that you enable the FlexRay PLL or before it after the start of the program execution.
After you have changed the multiplier setting, wait for the FlexRay PLL lock time, and then switch the clock source.
If you wait until the FlexRay PLL is locked, you must use a main timer interrupt.
To change the setting for the FlexRay PLL multiplier during normal operation, first change the clock source to
something other than the FlexRay PLL. In a similar way to the above case, first change the setting for the multiplier,
wait for the FlexRay PLL lock time, and then change the clock source.
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Chapter 7: Clock Reset State Transitions
This chapter explains clock reset state transitions.
1.
Overview
2.
Device States and Transitions
3.
Device State and Regulator Mode Corresponding to those States
Code : CRST-1v0-91528-3-E
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Chapter 7: Clock Reset State Transitions
1. Overview
This section explains the overview of clock reset state transitions.
This chapter explains state transition of clock and reset. For features and settings of power consumption control state,
see "CHAPTER: POWER CONSUMPTION CONTROL". For the operations of reset, see "CHAPTER: RESET". For
the regulator mode, see "CHAPTER: REGULATOR CONTROL".
2. Device States and Transitions
This section explains device states and transitions of clock reset state transitions.
2.1. Diagram of State Transitions
2.2. Explanation of Each States
2.3. Priority of State Transition Requests
2.1.
Diagram of State Transitions
This section shows diagram of state transitions.
The device state transitions for this series are shown below.
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Chapter 7: Clock Reset State Transitions
Figure 2-1 Diagram of Device State Transitions [MB91F52xxxC/MB91F52xxxE]
Power on
or Low-voltage
detect
Initialization
(SINIT)
Main oscillation
stabilization wait
(RESET)
PLL clock mode
Setting
initialization
(INIT) *1
PLL
sleep
Program
reset
(RST)
PLL
RUN
Main clock mode
Sub clock mode
Sub watch
mode
(Shutdown)
Main
watch mode
(shutdown)
⑳
Main
watch
mode
Main
RUN
Main stop
(Shutdown)
Main
stop
Main
oscillation
wait
1
○
2
○
3
○
4
○
5
○
6
○
7
○
8
○
9
○
10
○
11
○
12
○
13
○
14
○
15
○
16
○
17
○
18
○
19
○
20
○
Sub
sleep
Main
sleep
Sub
RUN
Sub watch
mode
Sub
stop
Sub stop
(Shutdown)
Sub
oscillation
wait
Power-on reset or internal low-voltage detection or external reset and simultaneous assertion of NMI
Power-on reset release and internal low-voltage release and external reset and release simultaneous assertion of NMI
End of oscillation stabilization wait
End of oscillation stabilization wait (if the reset factor is
7 or ○
9 )
○
INIT release
RST release
Software reset/
Software watchdog reset (including irregular) or software reset (irregular)
External reset input (NMI disabled ) or external low-voltage detection
External reset input (NMI disabled + irregular) or external low-voltage detection (irregular)
Hardware watchdog reset (including irregular)
Sleep mode (write instruction)
Stop mode (write instruction)
Watch mode (write instruction)
Interrupt (including
16 and ○
17 )
○
Interrupt (clock not required)/NMI
Main timer interrupt/Sub timer interrupt/RTC interrupt
Switch from main to sub (write instruction)
Switch from sub to main (write instruction)
Switch from main to PLL (write instruction)
(21) Switch from PLL to main (write instruction)
(22) Illegal standby mode transition
(23) Illegal standby mode transition detection reset
(24) Stop mode and shutdown (write instruction)
(25) Watch mode and shutdown (write instruction)
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Chapter 7: Clock Reset State Transitions
Figure 2-2 Diagram of Device State Transitions [MB91F52xxxD]
Power on
or Low-voltage
detect
Initialization
(SINIT)
Main oscillation
stabilization wait
(RESET)
PLL clock mode
Setting
initialization
(INIT) *1
PLL
sleep
Program
reset
(RST)
PLL
RUN
Main clock mode
Sub clock mode
Sub watch
mode
(Shutdown)
Main
watch mode
(shutdown)
⑳
Main
watch
mode
Main
RUN
Main stop
(Shutdown)
Main
stop
Main
oscillation
wait
1
○
2
○
3
○
4
○
5
○
6
○
7
○
8
○
9
○
10
○
11
○
12
○
13
○
14
○
15
○
16
○
17
○
18
○
19
○
20
○
Main
sleep
Sub
sleep
Sub
RUN
Sub watch
mode
Sub
stop
Sub stop
(Shutdown)
Sub
oscillation
wait
Power-on reset or internal low-voltage detection or external reset
Power-on reset release and internal low-voltage release and external reset release
End of oscillation stabilization wait
End of oscillation stabilization wait (if the reset factor is
7 or ○
9 )
○
INIT release
RST release
Software reset/
Software watchdog reset (including irregular) or software reset (irregular)
External low-voltage detection
External low-voltage detection (irregular)
Hardware watchdog reset (including irregular)
Sleep mode (write instruction)
Stop mode (write instruction)
Watch mode (write instruction)
Interrupt (including
16 and ○
17 )
○
Interrupt (clock not required)/NMI
Main timer interrupt/Sub timer interrupt/RTC interrupt
Switch from main to sub (write instruction)
Switch from sub to main (write instruction)
Switch from main to PLL (write instruction)
(21) Switch from PLL to main (write instruction)
(22) Illegal standby mode transition
(23) Illegal standby mode transition detection reset
(24) Stop mode and shutdown (write instruction)
(25) Watch mode and shutdown (write instruction)
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Chapter 7: Clock Reset State Transitions
* : There is a register not reset when returning from the watch mode (Shutdown) and returning from the stop mode
(Shutdown). See "Restrictions on Power-Shutdown and Normal Standby Control" in "CHAPTER : POWER
CONSUMPTION CONTROL" for detail.
Note:
The transition may be different from above diagram when connecting to OCD tool. See "CHAPTER: ON CHIP
DEBUGGER (OCD)" for details.
2.2.
Explanation of Each States
This section explains each state.
Device operation states for this series are shown below.
RUN State (Normal Operation)
The program is running. All internal clocks supply and all circuits are ready to operate. High-impedance controls for
the external pins in the stop state and watch mode state will be released.
Sleep Mode
The program is not running. The state transits by program operations. There are some settings; one to stop program
execution of the CPU only (CPU sleep mode) and the other to stop the CPU, on-chip bus and on-chip bus clock
(HCLK) driven peripheral (bus sleep mode). For details, see "CHAPTER: POWER CONSUMPTION CONTROL".
Watch Mode State
The devices are not running. The state transits by program operations. Internal circuits other than oscillation circuits
(main clock generation unit, sub clock generation unit) stop. Stop PLL oscillation before going into the watch mode
state. It is also possible to use the external pins altogether (except for some pins) for high impedance by the settings.
Transits to the RUN state by some specific (no clock required) effective interrupts, main timer interrupts, sub timer
interrupts and watch counter interrupts. For details, see "CHAPTER: POWER CONSUMPTION CONTROL".
Watch Mode (Power Shutdown) State
The device is stopped while the power supply unnecessary for the watch mode is turned off. The state transits by
program operation. The power supply for the internal circuit is turned off and the internal circuits other than the
oscillation circuits (the main clock generation unit and the sub clock generation unit) are stopped. Stop PLL
oscillation before going into the watch mode (power shutdown) state. It is also possible to use the external pins
altogether (except for some pins) for high impedance by the settings. Transits to the setting initialization (INIT) state
by some specific (no clock required) effective interrupts, the main timer interrupt, the sub timer interrupt and the
watch counter interrupt. For details, see "CHAPTER: POWER CONSUMPTION CONTROL".
Stop State
The devices are not running. The state transits by program operations. All internal circuits will stop. Stop PLL
oscillation before going into the stop mode state. It is also possible to use the external pins altogether (except for
some pins) for high-impedance by the settings. Transits to the oscillation stabilization wait RUN state by NMI
interrupt and external interrupt. For details, see "CHAPTER: POWER CONSUMPTION CONTROL".
Stop (Power Shutdown) State
The device is stopped while the power supply unnecessary for the stop state is turned off. The state transits by
program operation. The power supply for the internal circuit is turned off and all the internal circuits are stopped.
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Chapter 7: Clock Reset State Transitions
Stop PLL oscillation before going into the stop (power shutdown) state. It is also possible to use the external pins
altogether (except for some pins) for high impedance by the settings. Transits to the main oscillation stabilization wait
(reset) state by NMI interrupt. For details, see "CHAPTER: POWER CONSUMPTION CONTROL".
Main Oscillation Stabilization Wait, Sub Oscillation Stabilization Wait (RUN) State
The devices are not running. Transits after returning from the stop state. All the internal circuits except for the timer
operations for oscillation stabilization wait will stop. All internal clocks stop but the enabled oscillation circuits will
still be running. After the elapse of the oscillation stabilization wait time interval set, transits to the RUN state
(normal operation).
Main Oscillation Stabilization Wait (Reset) State
The devices are not running. Transits after returning from the initialization (SINIT) state. All the internal circuits
except for the timer operations for oscillation stabilization wait will stop. All internal clocks stop but the main
oscillation circuit will still be running. Outputs the program reset (RST) to the internal circuits. When the accepted
reset level is an initialization reset, outputs also the setting initialization reset (INIT). After the elapse of the main
clock oscillation stabilization wait time (215 × main clock cycle), transits to the setting initialization (INIT) state.
Program Reset (RST) State
The program is initialized. Transits after accepting the operation initialization reset (RST) request or at the end of the
setting initialization (INIT) state. Outputs the program reset (RST) to the internal circuits. When transiting from the
INIT state, OCD chip reset sequence (1026+3 PCLK cycles) will be performed.
Transits to the RUN state (normal operation) when removing the operation initialization reset (RST) request. For
details, see "CHAPTER: RESET".
Setting Initialization (INIT) State
All settings are initialized. Transits after accepting a setting initialization (INIT) request. The main oscillation circuit
continues to run but the sub oscillation circuit and PLL will stop operations. Outputs a setting initialization (INIT)
and a program reset (RST) to the internal circuits. Transits to the program reset (RST) state when removing the
setting initialization (INIT) request and this state being released. For details, see "CHAPTER: RESET".
2.3.
Priority of State Transition Requests
Priority of state transition requests is shown.
The state transition requests are prioritized in the following order in any states. However, since some requests are
generated only in the specific states, they are enabled only in those states.
[Highest priority]
↓
↓
↓
↓
↓
↓
[ Lowest priority]
276
Initialization (SINIT) request
Setting initialization (INIT) request
The end of the oscillation stabilization wait time
(generates an oscillation stabilization wait reset state and an oscillation
stabilization wait RUN state only.)
Program reset (RST) request
Effective interrupt request
(generates RUN, sleep, stop, watch mode states only)
Stop mode request (register write) (generates RUN state only)
Watch mode request (register write) (generates RUN state only)
Sleep mode request (register write) (generates RUN state only)
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Chapter 7: Clock Reset State Transitions
3. Device State and Regulator Mode Corresponding to those
States
Device state and regulator mode corresponding to those states are shown.
The regulator mode corresponding to each device state is shown in the following table. For regulator mode, see
"CHAPTER: REGULATOR CONTROL".
Table 3-1 Relationship between Device State and Regulator Mode (single clock product)
Device state
Main clock
Regulator mode
Main RUN
Oscillation
Main mode
Main sleep
Oscillation
Main mode
Main watch mode
Oscillation
Main mode
Main watch mode (Shutdown)
Oscillation
Standby mode
Main stop
Stop
Main mode
Main stop (Shutdown)
Stop
Standby mode
Main Oscillation wait
Oscillation
Main mode
PLL RUN
Oscillation
Main mode
PLL sleep
Oscillation
Main mode
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Chapter 7: Clock Reset State Transitions
Table 3-2 Relationship between Device State and Regulator Mode (dual clock product)
Device state
Main clock
Sub clock
Regulator mode
Main RUN
Oscillation
Oscillation or Stop
Main mode
Main sleep
Oscillation
Oscillation or Stop
Main mode
Main watch mode
Oscillation
Oscillation or Stop
Main mode
Main watch mode(Shutdown)
Oscillation
Oscillation or Stop
Standby mode
Main stop
Stop
Stop
Main mode
Main stop (Shutdown)
Stop
Stop
Standby mode
Main Oscillation wait
Oscillation
Oscillation or Stop
Main mode
Sub RUN 1
Oscillation
Oscillation
Main mode
Sub RUN 2
Stop
Oscillation
Main mode
Sub sleep 1
Oscillation
Oscillation
Main mode
Sub sleep 2
Stop
Oscillation
Main mode
Sub watch mode
Oscillation or Stop
Oscillation
Main mode
Sub watch mode (Shutdown)
Oscillation or Stop
Oscillation
Standby mode
Sub stop
Stop
Stop
Main mode
Sub stop (Shutdown)
Stop
Stop
Standby mode
Sub Oscillation wait 1
Oscillation
Oscillation
Main mode
Sub Oscillation wait 2
Stop
Oscillation
Main mode
PLL RUN
Oscillation
Oscillation or Stop
Main mode
PLL sleep
Oscillation
Oscillation or Stop
Main mode
Note:
When OCD tool is connected, the regulator mode is a main mode in the above any tables.
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Chapter 8: Reset
This chapter explains the reset.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : RST-1v1-91528-3-E
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Chapter 8: Reset
1. Overview
This section explains the overview of the reset.
When a reset factor is generated, the device terminates all programs and most of the hardware operations and
initializes the state. This state is referred to as a reset.
2. Features
This section explains features of the reset.
This product, which has the following reset factors, issues a reset by accepting each factor to initialize the
components in the device.
Power-on reset
RSTX pin Input
Watchdog reset 0 (Software watchdog)
Watchdog reset 1 (Hardware watchdog)
Software reset
Illegal standby mode transition detection reset
Flash security violation
Internal low-voltage detection
External low-voltage detection
Clock supervisor reset
Recovery reset from stand by (power shutdown)
Other than the case of irregular reset (see "4.1 Reset Source Register : RSTRR (ReSeT Result Register)"), the
contents of memory being accessed by the reset (RAM, Flash) will not be destroyed since all resets are issued once
the completion of all bus accesses have been confirmed.
To issue a forced reset in case the bus does not return the response within a certain time frame, the device waits for
the reset issue delay counter. If there is no response within the specified time frame, a reset will be issued whether or
not the bus has responded. (Reset timeout)
See "CHAPTER : CLOCK SUPERVISOR" for clock supervisor reset.
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Chapter 8: Reset
3. Configuration
This section explains the configuration of the reset.
Figure 3-1 Configuration Diagram of Reset [MB91F52xxxC/MB91F52xxxE]
*2
Isolator
Return from power
shutdown and
shutdown
CPU
I/O
MDI
Always Power supply ON Block
Synchronous
reset factor
Asynchronous
reset factor *1
Isolator
Synchronous reset
HWWD reset
Other always Power
supply ON Block
Reset control
I/O
CSV reset
Power-on reset
External
reset /
NMI reset
Clock control
RTC
AND
External interrupt
AND
PMU
Reset mask (RTC)
Reset mask
(External interrupt)
*1: Power-on reset is contained
*2: Active at return from power shutdown and shutdown
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281
Chapter 8: Reset
Figure 3-2 Configuration Diagram of Reset [MB91F52xxxD]
*2
Isolator
Return from power
shutdown and
shutdown
CPU
I/O
MDI
Synchronous
reset factor
Always Power supply ON Block
Asynchronous
reset factor *1
Isolator
Synchronous reset
HWWD reset
Other always Power
supply ON Block
Reset control
I/O
External
reset
CSV reset
Power-on reset
Clock control
RTC
AND
External interrupt
AND
PMU
Reset mask (RTC)
Reset mask
(External interrupt)
*1: Power-on reset is contained
*2: Active at return from power shutdown and shutdown
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Chapter 8: Reset
Figure 3-3 Configuration Diagram of Reset (Reset Control) [MB91F52xxxC/MB91F52xxxE]
Reset request by simultaneously assert of RSTX and NMIX
Re se t request
S
RDLY
On-chip
On-chipbus
bus
P CLK
De lay
se lector
4bit
Generate rese t
P CLK
De lay counter
>
Re se t
(RST)
Q
R
RS TCR
8bi t
In debug
state
Ex tend counter
Bu s idle response
In itialize rese t
(INI T)
Po we r-on rese t
Low-voltage detec tion ( interna l powe r lo w-voltage detect ion)
NMIX pin
S
No ise
filter
2bit
P CLK
RS TX pin
No ise
filter
Reset request fro m OCD tool
No ise
filter
Factor extend counter
Q
P CLK
4bit
Ex tend counter
R
Re se t
request fla g
Generate rese t
In debug
state
S
Q
R
Low vol tage d etection( external pow er
sup pl y low-vo ltage detection)
Ill egal standby transi tion de tection re se t
factor
2bi t
P CLK
Factor ext end counter
Clock supervisor reset
Re se t
request fla g
Generate rese t
In debug
state
Wa tchdog rese t 1
S
Q
R
CPUAR: HW DF
2bi t
P CLK
Factor extend counter
Re se t
request fla g
Generate rese t
In debug
state
Wa tchdog rese t 0
S
2bi t
P CLK
Factor extend counter
Q
RS TRR
R
IR R ST
Re se t
request fla g
ER S T
Generate rese t
WD G0
In debug
state
Unused (1・b0)
S
WD G1
Q
U nus ed
U nus ed
R
2bi t
P CLK
Factor ext end counter
SCR T
Re se t
request fla g
S R ST
Generate rese t
RS TRR
Re ad
In debug
state
Unused (1・b0)
S
Cle ared when re ad
Q
R
2bi t
P CLK
Factor extend counter
Re se t
request fla g
Generate rese t
In debug
state
Flash sec urity violation
rese t factor
S
2bi t
P CLK
Factor extend counter
S oftw are re se t re quest
SR ST
RS TCR
Q
R
Re se t
request fla g
: bit nam e of regis ter
Ge nerate rese t
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Chapter 8: Reset
Figure 3-4 Configuration Diagram of Reset (Reset Control) [MB91F52xxxD]
Reset request by simultaneously assert of RSTX and NMIX
Re se t request
S
RDLY
bus
On-chip
On-chip bus
P CLK
De lay
se lector
4bit
Generate rese t
P CLK
De lay counter
>
Re se t
(RST)
Q
R
RS TCR
8bi t
In debug
state
Ex tend counter
Bu s idle response
In itialize rese t
(INI T)
Po we r-on rese t
Low-voltage detec tion ( interna l powe r lo w-voltage detect ion)
NMIX pin
S
No ise
filter
2bit
P CLK
RS TX pin
No ise
filter
Reset request fro m OCD tool
No ise
filter
Factor extend counter
Q
P CLK
4bit
Ex tend counter
R
Re se t
request fla g
Generate rese t
In debug
state
S
Q
R
Low vol tage d etection( external pow er
sup pl y low-vo ltage detection)
Ill egal standby transi tion de tection re se t
factor
2bi t
P CLK
Factor ext end counter
Clock supervisor reset
Re se t
request fla g
Generate rese t
In debug
state
Wa tchdog rese t 1
S
Q
R
CPUAR: HW DF
2bi t
P CLK
Factor extend counter
Re se t
request fla g
Generate rese t
In debug
state
Wa tchdog rese t 0
S
Q
RS TRR
R
2bi t
P CLK
Factor extend counter
IR R ST
Re se t
request fla g
ER S T
Generate rese t
WD G0
In debug
state
Unused (1・b0)
S
WD G1
Q
U nus ed
U nus ed
R
2bi t
P CLK
Factor ext end counter
SCR T
Re se t
request fla g
S R ST
Generate rese t
RS TRR
Re ad
In debug
state
Unused (1・b0)
S
Cle ared when re ad
Q
R
2bi t
P CLK
Factor extend counter
Re se t
request fla g
Generate rese t
In debug
state
Flash sec urity violation
rese t factor
S
S oftw are re se t re quest
SR ST
RS TCR
Q
R
2bi t
P CLK
Factor extend counter
Re se t
request fla g
: bit nam e of regis ter
Ge nerate rese t
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Chapter 8: Reset
Figure 3-5 Generation Diagram of Illegal Standby Mode Transition Detection Reset Factor
set
When the PLL/SSCG clock is
selected as a clock source
CPUAR.
PSTF
Transition to watch mode or
stop mode is generated
Illegal standby mode
transition detection
reset factor
CPUAR.
PSTRE
4. Registers
This section explains the registers of the reset.
Table 4-1 Registers Map
Address
Registers
Register function
+0
+1
+2
+3
0x0480
RSTRR
RSTCR
Reserved
Reserved
Reset Source Register
Reset Control Register
0x0518
Reserved
Reserved
CPUAR
Reserved
CPU Abnormal Operation
Register
0x0590
PMUSTR
Reserved
Reserved
Reserved
PMU Status Register
Note:
Please note that the register of "CHAPTER : POWER CONSUMPTION CONTROL" is allocated in address 0x0482,
0x0591, and 0x0592.
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Chapter 8: Reset
4.1.
Reset Source Register : RSTRR (ReSeT Result Register)
The bit configuration of the reset source register is shown.
This register displays various reset factors generated until just before.
RSTRR : Address 0480H (Access : Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
bit4
IRRST
ERST
WDG1
WDG0
*
*
*
*
bit3
bit2
bit1
bit0
SCRT
SRST
-
*
*
RX,WX
R,WX
R,WX
Reserved
-
Attribute R,WX
R,WX
R,WX
R,WX
RX,WX
*: Due to a reset factor.
*: These bits other than IRRST bit are undefined at power-on reset.
Note:
When this register is read out, all bits will be cleared.
This register is not cleared in reading in the debugging state.
Because each reset factor is masked in the debugging state, this register does not detect the reset factor either.
[bit7] IRRST (IRregular ReSeT) : Irregular reset
[MB91F52xxxC/MB91F52xxxE] This bit indicates that any of power-on reset, internal low-voltage detection, reset
timeout, or simultaneous assertion of RSTX and NMIX external pins has occurred, so that the bus access state when
issuing a reset cannot be guaranteed. When this bit is "0" after the reset, no bus access was executed at the previous
reset, which guarantees that memory contents have not been destroyed by the reset. When this bit is "1" after the reset,
it is possible that a bus access was executed at the previous reset, which does not guarantee that memory contents
have not been destroyed by the reset.
[MB91F52xxxD] This bit indicates that any of power-on reset, internal low-voltage detection, reset timeout, or
assertion of RSTX external pins has occurred, so that the bus access state when issuing a reset cannot be guaranteed.
When this bit is "0" after the reset, no bus access was executed at the previous reset, which guarantees that memory
contents have not been destroyed by the reset. When this bit is "1" after the reset, it is possible that a bus access was
executed at the previous reset, which does not guarantee that memory contents have not been destroyed by the reset.
IRRST
Irregular reset detected
0
Irregular reset undetected
1
Irregular reset detected
This bit will be cleared when it is read out.
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Chapter 8: Reset
[bit6] ERST (External ReSeT) :
[MB91F52xxxC/MB91F52xxxE] Reset pin input, illegal standby mode transition detection, external low-voltage
detection, clock supervisor reset, simultaneous assertion of RSTX and NMIX external pins
This bit indicates that there was a reset input from RSTX pin input, illegal standby mode transition detection reset,
external low-voltage detection, clock supervisor reset or simultaneous assertion of RSTX and NMIX external pins.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
ERST
RSTX pin reset detection, illegal standby mode
transition detection, clock supervisor reset, low-voltage
detection (external low-voltage detection) or simultaneous
assertion of RSTX and NMIX external pins
0
Undetected
1
Detected
This bit will be cleared when it is read out.
[MB91F52xxxD] Reset pin input, illegal standby mode transition detection, external low-voltage detection,
clock supervisor reset.
This bit indicates that there was a reset input from RSTX pin input, illegal standby mode transition detection reset,
external low-voltage detection, clock supervisor reset.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
ERST
RSTX pin reset detection, illegal standby mode
transition detection, clock supervisor reset, low-voltage
detection (external low-voltage detection)
0
Undetected
1
Detected
This bit will be cleared when it is read out.
[bit5] WDG1 (WatchDoG reset 1) : Watchdog Reset 1
This bit indicates a reset from the watchdog timer 1.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
WDG1
0
Watchdog timer 1 reset
Undetected
Detected
1
This bit will be cleared when it is read out.
The CPUAR register also has a flag that indicates a reset factor generation by the watchdog reset 1. The bit will not
be cleared when the CPUAR register is read.
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Chapter 8: Reset
[bit4] WDG0 (WatchDoG reset 0) : Watchdog Reset 0
This bit indicates a reset from the watchdog timer 0.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
WDG0
0
Watchdog timer 0 reset
Undetected
Detected
1
This bit will be cleared when it is read out.
[bit1] SCRT (flash SeCuRiTy violation) : Flash security violation reset
This bit indicates that a flash memory security violation reset has occurred.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
SCRT
0
Flash security violation reset
Undetected
Detected
1
This bit will be cleared when it is read out.
[bit0] SRST (Software ReSeT) : Software reset
This bit indicates a reset by writing "1" to the RSTCR:SRST bit.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
SRST
0
Software reset
Undetected
Detected
1
This bit will be cleared when it is read out.
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Chapter 8: Reset
4.2.
Reset Control Register : RSTCR (ReSeT Control Register)
The bit configuration of the reset control register is shown.
This register controls various types of reset issuance.
RSTCR : Address 0481H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
RDLY[2:0]
Initial value
Attribute
bit2
bit1
Reserved
bit0
SRST
1
1
1
0
0
0
0
0
R,W
R,W
R,W
R/W
R/W
R/W
R/W
R,W
[bit7 to bit5] RDLY[2:0] (Reset DeLaY) : Reset issue delay
These bits set the reset timeout value. A reset will be issued if all bus operations become idle or the timer has counted
to the reset timeout by this bit after a reset factor has been detected. (The latter is a case of irregular reset). These bits
can be written for only once after the reset.
RDLY[2:0]
Reset timeout value
000
PCLK × 2 cycles
001
PCLK × 4 cycles
010
PCLK × 8 cycles
011
PCLK × 16 cycles
100
PCLK × 32 cycles
101
PCLK × 64 cycles
110
PCLK × 128 cycles
111
PCLK × 256 cycles (Initial value)
[bit4 to bit1] Reserved
This has no effect on both writing and reading.
[bit0] SRST (Software ReSeT) : Software reset
You will be able to generate a software reset request by reading RSTCR after writing "1" to this bit.
After you have written "1" to this bit, any values written to RSTCR will be ignored until a reset is generated, which
means that register values cannot be changed.
In the RSTCR reading in the debugging state, reset is not generated.
SRST
Software reset
0
No output (initial value)
1
The reset request is output by RSTCR reading.
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Chapter 8: Reset
4.3.
CPU Abnormal Operation Register : CPUAR (CPU
Abnormal operation Register)
The bit configuration of the CPU abnormal operation register is shown.
This register indicates the status and settings associated with the abnormal operation of CPU.
CPUAR : Address 051AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
PSTRE
Initial value
bit4
bit3
Reserved
0
0
0
0
*
bit2
bit1
bit0
PMDF
PSTF
HWDF
*
*
*
R(RM1),
W
* : It will be initialized to "0" by RSTX pin asserts (including simultaneous assert with NMIX). It will not be
initialized by the other reset factors.
Attribute
R/W
R0,WX
R0,WX
R0,WX
RX,WX R(RM1),W R(RM1),W
[bit7] PSTRE (illegal PLL-run to STandby Reset Enable) : Illegal standby mode transition detection reset
enable
This bit configures whether or not to issue a reset when a watch mode or a stop mode transition has been detected
(illegal standby mode transition) with the PLL clock selected as a clock source.
When enabled, a reset due to the illegal standby mode transition detection factor will be generated at a transition from
the PLL-run state to watch mode or stop mode.
PSTRE
Description
0
Reset will not be generated (initial value)
1
Reset generation enabled
Note:
When you set this bit, make sure to clear the PSTF bit by writing "0" to the PSTF bit before setting this bit. If you set
this bit before clearing the PSTF bit, a reset may be generated since the value of the PSTF bit after the power-on reset
is indefinite.
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Chapter 8: Reset
[bit2] PMDF (PLL mode Main clock Down detection Flag) : PLL mode main oscillation determination detection
flag
When the clock supervisor does the main oscillation determination detection when PLL output is selected as a clock
source, this bit is set. Moreover, the source clock is written automatically in main mode (CKS= CKM=00), and reset
(RST level) is generated at once.
If a read-modify-write instruction is executed, "1" will be read out.
PMDF
Read
Write
0
The main oscillation determination detection is not in PLL
mode. (initial value)
1
The main oscillation determination detection is in PLL mode. No effect
Clear this bit
[bit1] PSTF (illegal PLL-run to STandby Flag) : Illegal standby mode transition detection flag
This bit will be set when a watch mode or a stop mode transition has been detected (illegal standby mode transition)
with the PLL clock selected as a clock source. Moreover, the source clock is written automatically in main mode
(CKS=CKM=00). When the PSTRE bit is "1", reset (RST level) is generated.
This bit is cleared by writing "0".
If a read-modify-write instruction is executed, "1" will be read out.
PSTF
Read
Write
0
No illegal standby mode transition has been detected
Clear this bit
1
Illegal standby mode transition has been detected.
No effect
[bit0] HWDF (Hardware WatchDog Flag) : Hardware watchdog detection flag
When a reset factor for the watchdog timer 1 (Hardware watchdog) has been detected, this bit will be set.
This bit is cleared by writing "0".
If a read-modify-write instruction is executed, "1" will be read out.
HWDF
0
Read
No watchdog timer1 (Hardware watchdog) reset factor has
been generated.
Write
Clear this bit
Watchdog timer1 (Hardware watchdog) reset factor has been
No effect
generated.
The set factor is given to priority when a set factor and a clear factor are generated at the same time.
1
Note:
There is a detection flag also in RSTRR.WDG1, and the factor disappears when read once because it is read clear.
Because CPUAR.HWDF is maintained, the factor is maintained until clearing.
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4.4.
PMU Status Register : PMUSTR (Power Management Unit
STatus Register)
The bit configuration of the PMU status register is shown.
This register indicates the PMU status.
PMUSTR : Address0590H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
PMUST
bit4
bit3
bit2
Reserved
bit1
bit0
PONR_F
RSTX_F
Initial value
0
0
0
0
0
0
1
*
Attribute
R,W
R0,W0
R0,W0
R0,W0 R0,W0
R0,W0
R,W
R,W
* : It will be initialized to "1" by RSTX pin asserts (including simultaneous assert with NMIX). It will not be
initialized by the other reset factors.
[bit7] PMUST (Power Management Unit STatus)
Displays information on whether the immediately preceding status was shutdown mode.
PMUST
PMU status
0
Operation return from initial state and initialization reset
1
Operation return from Shutdown mode
This bit is cleared by writing "0". Writing "1" to this bit is ignored.
[MB91F52xxxC/MB91F52xxxE] This bit is initialized only by power-on reset, internal low-voltage detection reset,
and simultaneous assertion of RSTX and NMIX. So, check other reset factors before checking the recovery from
shutdown using this bit.
[MB91F52xxxD] This bit is initialized only by power-on reset, internal low-voltage detection reset, and assertion of
RSTX. So, check other reset factors before checking the recovery from shutdown using this bit.
[bit6 to bit2] Reserved
"0" is always read. Please be sure to write "0".
[bit1] PONR_F (Power ON Reset Flag)
This bit is a power-on reset or internal low-voltage detection reset detection flag.
PONR_F
Power-on reset
0
No detection
1
Detection
This bit is cleared by writing "0". Writing "1" to this bit is ignored.
This bit is not initialized in reset factors other than power-on reset.
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[bit0] RSTX_F (ReSeTX input Flag)
This bit is an external reset detection flag.
RSTX_F
RSTX input reset
0
No detection
1
Detection
This bit is cleared by writing "0". Writing "1" to this bit is ignored.
This bit is not initialized by the power-on reset. Be sure to use after clear.
5. Operation
This section explains the reset operation.
This section explains each of the reset operations for this product.
5.1. Reset Level
5.2. Reset Factor
5.3. Reset Acceptance
5.4. Reset Issue
5.5. Reset Sequence
5.6. Notes
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5.1.
Reset Level
The reset level is explained.
The following two levels of resets are available with this product.
Initialize reset (INIT)
Reset (RST)
Note:
Except the registers for debug interface (OCDU), the registers initialized by the reset of both levels are the same for
this product.
5.1.1.
Initialize Reset (INIT)
Initialize reset (INIT) is explained.
It initializes the CPU and all registers except the ones initialized only by the power-on reset or super initialize reset
(SINIT) and registers with undefined initial value. It terminates the CPU programs running, and the program counter
will be initialized. All peripheral circuits will be initialized. A main oscillation circuit continues to run. If it was
inactive, it starts running again. In this case, a sub oscillation circuit and PLL become inactive.
This reset level is applied at a reset by the following reset factors.
Irregular reset
Watchdog reset 0, 1
Only the following register will be initialized by this reset level.
Register of the debug interface (OCDU)
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5.1.2.
Reset (RST)
The reset (RST) is explained.
It initializes the CPU and all registers except the ones initialized only by the power-on reset, SINIT or INIT and
registers with undefined initial value. It terminates the CPU programs running, and the program counter will be
initialized. All peripheral circuits will be initialized.
When an initialize reset (INIT) is issued, a reset (RST) is issued at the same time.
The reset in the entire document indicates this reset level unless otherwise specified.
5.2.
Reset Factor
This section explains the reset factor.
This section explains each of the reset factors for this product.
5.2.1.
Power-on Reset
Power-on reset is shown.
It is a reset factor generated when detecting the power has turned on.
All resets due to this reset factor are detected as an irregular reset and issue an initialize reset (INIT).
5.2.2.
RSTX Pin Input
The RSTX pin input is shown.
It is a hardware reset input from the outside of the device.
[MB91F52xxxC/MB91F52xxxE] Reset by this reset factor is detected as irregular reset only at the reset timeout or
simultaneous assert of the NMIX pin.
Other than the irregular reset detection, a reset (RST) will be issued.
[MB91F52xxxD] Reset by this reset factor is detected as irregular reset.
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5.2.3.
Watchdog Reset 0
The watchdog reset 0 is shown.
It is a hardware reset input from the FR81S-core built-in watchdog timer 0 (software watchdog).
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Whether or not an
irregular reset has been detected, an initialize reset (INIT) will be issued.
5.2.4.
Watchdog Reset 1
The watchdog reset 1 is shown.
It is a hardware reset input from the FR81S-core built-in watchdog timer 1 (hardware watchdog).
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Whether or not an
irregular reset has been detected, an initialize reset (INIT) will be issued.
5.2.5.
External Low-Voltage Detection Reset
The external low-voltage detection reset is shown.
Low-voltage detection (external voltage) is a hardware reset input from the low-voltage detection circuit located
inside of the device.
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the
irregular reset detection, a reset (RST) will be issued.
See "CHAPTER : LOW VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION)" for details on
voltage detection.
5.2.6.
Illegal Standby Mode Transition Detection Reset
The illegal standby mode transition detection reset is shown.
It is a hardware reset generated when a watch mode or a stop mode transition has been detected (illegal standby mode
transition) with the PLL clock selected as a clock source.
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the
irregular reset detection, a reset (RST) will be issued
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5.2.7.
Internal Low-Voltage Detection Reset
The internal low-voltage detection reset is shown.
Low-voltage detection (internal voltage) is a hardware reset input from the low-voltage detection circuit located
inside of the device.
Resets due to this reset factor will be detected as an irregular reset and an initialize reset (INIT) will be issued.
See "CHAPTER : LOW VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION)" for details on
voltage detection.
5.2.8.
Flash Security Violation Reset
The Flash security violation reset is shown.
It is a reset issued when a violation of flash memory security protection has occurred.
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the
irregular reset detection, a reset (RST) will be issued.
5.2.9.
Software Reset (RSTCR:SRST)
The software reset (RSTCR:SRST) is shown.
It is a software reset generated inside of the device.
This reset will be issued when you read RSTCR after writing "1" to the bit0: SRST bit of the RSTCR.
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the
irregular reset detection, a reset (RST) will be issued.
[Example] Sample program of a software reset issue
LDI
LDI
STB
LDUB
MOV
NOP
#value_of_reset, R0
#_RSTCR, R12
R0, @R12
@R12, R0
R0, R0
; SRST bit="1"
;
; Write
; Read (generation of a software reset request)
; Dummy processing for pipeline adjustment
; Dummy processing for pipeline adjustment
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5.2.10. Recovery from Standby (Power Shutdown)
Recovery from standby (power shutdown) is shown.
For a majority of the block including the microcontroller, the operation similar as super initialize reset (SINIT) is
executed by the start from the standby. However, power-on reset factor is always at the power-on block, the detection
is not displayed in the reset source register (RSTRR) . The factors are displayed in the PMU status register
(PMUSTR), and please confirm this register, when the microcontroller reactivates.
Resets due to this reset factor will issue an initialization reset (INIT).
5.3.
Reset Acceptance
This section explains the reset acceptance.
This section explains the acceptance processing of each reset factor.
5.3.1.
Generation of Reset Request
The generation of a reset request is shown.
A reset request will be generated when at least one reset factor is retrieved. The reset request will be notified to the
internal bus controller, and the following processing will be executed.
Stop the CPU programs running (same processing as sleep mode)
Acquire bus control right of the on-chip bus
Confirm that idle request has been notified to all busses
5.3.2.
Acceptance of Reset Request
Acceptance of a reset request is shown.
Once all processing for the reset request completes, the component where a reset is issued accepts the reset request
and issues a reset of which level corresponds to the reset factor. If the reset issue delay counter overflows (= reset
timeout occurs), the reset request is accepted without waiting for the completion of reset request processing, and an
irregular reset will be issued.
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5.3.3.
Reset Issue Delay Counter
The reset issue delay counter is shown.
As soon as a reset request is generated, the 8-bit reset issue delay counter starts counting. If the delay cycle specified
by the bit7 to bit5: RDLY[2:0] bits of the RSTCR register has elapsed without a reset being issued and the counter
overflows (= reset timeout occurs), an irregular reset will be issued.
The RDLY[2:0] bit of the RSTCR will be initialized by a reset. This bit can be rewritten for once only after a reset is
released. If the delay cycle is set for a short time, it is more likely to generate an irregular reset. If the delay cycle is
set for a long time, it might take a long time for a reset to be issued since the generation of a reset factor.
5.3.4.
Irregular Reset
The irregular reset is shown.
If a reset is issued without confirming the completion of reset request processing, an irregular request will be
generated. Once an irregular reset is generated, the following processing will be executed.
Issue initialize reset (INIT) regardless of the type of reset factor.
Set the bit7: IRRST bit of RSTRR register to "1".
When an irregular reset occurs, there is no guarantee that memory contents were not destroyed by the reset since a
bus access may have been executed at the time of inputting the reset. The irregular reset does not necessarily mean
that the memory contents were destroyed, but how the bus access was executed cannot be identified.
5.4.
Reset Issue
This section explains reset issue.
A reset will be issued after a reset request has been accepted. This section explains each type of reset issue.
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Chapter 8: Reset
5.4.1.
Super Initialize Reset (SINIT)
The super initialize reset (SINIT) is shown.
[MB91F52xxxC/MB91F52xxxE] The super initialize reset (SINIT) will be issued first for power-on reset, internal
low-voltage detection, or simultaneous assertion of RSTX and NMIX.
[MB91F52xxxD] The super initialize reset (SINIT) will be issued first for power-on reset, internal low-voltage
detection, or assert of RSTX.
This reset is exclusively used for initializing the indefinite state of division circuits and so on.
While this reset is being issued, all clocks become inactive.
When this reset is issued, an initialize reset (INIT) and a reset (RST) will be always issued at the same time.
This reset initializes the clock control register.
This reset involves the wait time of main clock oscillation to be stabilized. Along with the control register
initialization, the oscillation stabilization wait time is 215× main clock cycle.
Table 5-1 Oscillation Stabilization Wait Time (SINIT)
Type
Main clock oscillation stabilization wait time
Power-on reset
215× Main clock cycle
Internal low-voltage detection
215× Main clock cycle
[MB91F52xxxC/MB91F52xxxE]
Simultaneous assertion of RSTX and NMIX
215× Main clock cycle
[MB91F52xxxD] Assertion of RSTX
215× Main clock cycle
Note:
The oscillation stabilization wait time shown in the above table does not include the regulator stabilization wait time
associated with the power-on and voltage restore. These stabilization wait time (300μs to 1200μs and maximum
580μs) are needed at power-on reset.
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Chapter 8: Reset
Figure 5-1 Oscillation Stabilization Wait Time for Power-on Reset
Vcc
15
300μs to 1200μs
2 × main
clock period
Max.580μs
CLK
INIT
CPU operation (RST)
Step-down circuit
stabilization wait
time
Oscillation
stabilization
wait time
(PCLK× (1134+3) cycles)
Flash step-down
OCDU chip reset
circuit
circuitstabilization
sequence
wait time
The following describes each reset issue sequence after reset factors of this reset have been released.
Figure 5-2 Super Initialize Reset (SINIT) Sequence
Factor
INIT
15
CPU operation
(RST)
2 × main clock
period
Oscillation stabilization
wait time
Max. 580μs
PCLK × (1134 + 3) cycles
Flash step-down
circuit stabilization
wait time
OCDU chip reset
sequence
Because the clock settings register is initialized by reset, the period of the peripheral clock (PCLK) is 8 times the
period of the main clock (MCLK).
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5.4.2.
Initialize Reset (INIT)
Initialize reset (INIT) is shown.
If a reset factor of the initialize reset (INIT) level occurs, an initialize reset (INIT) and a reset (RST) will be issued at
the same time. This reset is exclusively used for initializing the registers that cannot be initialized by a reset (RST).
While this reset is being issued, all clocks become active. When this reset is issued, a reset (RST) will be always
issued at the same time. Although this reset initializes the clock control register, the oscillation of the clock does not
change while the main clock (MCLK) is oscillating.
If the main clock is inactive such as in a stop mode, it takes the main clock oscillation stabilization wait time. Since
the register of the clock control part will be initialized by a reset, the oscillation stabilization wait time is the default
value of this product (215× main clock cycle).
Table 5-2 Oscillation Stabilization Wait Time (INIT)
Is main clock oscillation
inactive before inputting
Main clock oscillation stabilization wait time
a reset?
No
None
Yes
215× Main clock cycle
The following describes each reset issue sequence after reset factors of this reset have been released.
Figure 5-3 Initialize Reset (INIT) Sequence
Factor
INIT
CPU operation
(RST)
PCLK × (1134 + 3) cycles
OCDU chip reset
sequence
Additional oscillation stabilization wait time in the
event that main clock oscillation stabilization wait
time is required.
Step-down circuit stabilization wait time (580 μs)
is required additionally at return from standby.
Because the clock settings register is initialized by reset, the period of the peripheral clock (PCLK) is 8 times the
period of the main clock (MCLK).
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5.4.3.
Reset (RST)
The reset (RST) is shown.
If a reset factor that is not the SINIT or INIT level occurs, only a reset (RST) will be issued.
This reset is used for initializing the CPU and all registers except some registers (see "5.1.1. Initialize Reset (INIT)").
While this reset is being issued, all clocks become active.
If the main clock is inactive such as in a stop mode before the reset, it takes the main clock oscillation stabilization
wait time. Since the register of the clock control part will be initialized by a reset, the oscillation stabilization wait
time is the default value of this product (215× main clock cycle).
Table 5-3 Oscillation Stabilization Wait Time (RST)
Is main clock oscillation
inactive before inputting
Main clock oscillation stabilization wait time
a reset?
No
None
15
Yes
2 ×Main clock cycle
The following describes each reset issue sequence after reset factors of this reset have been released.
Figure 5-4 Reset (RST) Sequence
Factor
INIT
L
RST
PCLK × 4 cycles
PCLK × 16 cycles
Additional oscillation stabilization wait time in the
event that main clock oscillation stabilization wait
time is required.
Step-down circuit stabilization wait time (580 μs)
is required additionally at return from standby.
Because the clock settings register is initialized by reset, the period of the peripheral clock (PCLK) is 8 times the
period of the main clock (MCLK).
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Chapter 8: Reset
5.5.
Reset Sequence
The reset sequence is shown.
This product transits from the initial state to start running the programs and hardware by disappearance of reset factors. A
series of operations from this reset to the start of operation is called a reset sequence. This section explains the reset
sequence.
Figure 5-5 Reset Sequence [MB91F52xxxC/MB91F52xxxE]
Generate reset factor (ii)
Generate reset factor (i)
Watchdog reset 1 (HW)
Watchdog reset 0 (SW)
Power-on reset
Internal low-voltage detection reset
External reset + NMIX assert
Issue super initialize
reset (SINIT)
(iv)
Generate reset factor (iii)
External reset
External low-voltage detection reset
Illegal standby mode transition detection reset
Software reset
Flash security violation reset
Clock supervisor reset
Wait for bus idle
(v)
Reset
time out
Bus idle
Generate reset factor (A)
Recovery reset from standby
(power shutdown)
Wait for bus idle
(vi)
Reset
time out
Mask reset (B)
Bus idle
Issue initialize reset (D)
Issue initialize reset (vii)
Issue reset (E)
(Chip reset sequence)
Release only asynchronous reset
Issue reset (viii)
(Chip reset sequence)
Issue reset (ix)
Release mask of reset (F)
Release synchronous reset
Transition of Bus Control
Fetch reset vector(x)
Start the program
Notes:
-If (i) occurs after (vii) or during (v) or (vi), the sequence restarts from (i).
If (i) occurs after (B), the sequence restarts from (i).
Refer to "Figure 2-1 Diagram of Device State Transitions" in CHAPTER of "CLOCK RESET STATE TRANSITIONS" for details.
-The main clock oscillation stabilization wait time is taken during (iv).
-The main clock oscillation stabilization wait time is taken during (vii), (viii), or (ix) if necessary (CMONR.MCRDY=0).
-Refer to CHAPTER of "FIXEDVECTOR FUNCTION" for details on (x).
-At illegal standby mode transition detection reset, the status is a bus idle status after generating reset factor, so the status move to (ix).
-Super initialize reset (SINIT) is issued at the recovery from standby (power shutdown) (A). However, because of preventing a reset to
following block, the reset without SINIT to this block will be masked (B) during the reset period.
(1) RTC (only watch mode)
(2) External interrupt block
(3) Power management unit
(4) Clock generation block (only sub-clock selection register)
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Figure 5-6 Reset Sequence [MB91F52xxxD]
Generate reset factor (ii)
Generate reset factor (i)
Watchdog reset 1 (HW)
Watchdog reset 0 (SW)
Power-on reset
Internal low-voltage detection reset
External reset
Issue super initialize
reset (SINIT)
(iv)
Generate reset factor (iii)
External low-voltage detection reset
Illegal standby mode transition detection reset
Software reset
Flash security violation reset
Clock supervisor reset
Wait for bus idle
(v)
Reset
time out
Bus idle
Generate reset factor (A)
Recovery reset from standby
(power shutdown)
Wait for bus idle
(vi)
Reset
time out
Mask reset (B)
Bus idle
Issue initialize reset (D)
Issue initialize reset (vii)
Issue reset (E)
(Chip reset sequence)
Release only asynchronous reset
Issue reset (viii)
(Chip reset sequence)
Issue reset (ix)
Release mask of reset (F)
Release synchronous reset
Transition of Bus Control
Fetch reset vector(x)
Start the program
Notes:
-If (i) occurs after (vii) or during (v) or (vi), the sequence restarts from (i).
If (i) occurs after (B), the sequence restarts from (i).
Refer to "Figure 2-1 Diagram of Device State Transitions" in CHAPTER of "CLOCK RESET STATE TRANSITIONS" for details.
-The main clock oscillation stabilization wait time is taken during (iv).
-The main clock oscillation stabilization wait time is taken during (vii), (viii), or (ix) if necessary (CMONR.MCRDY=0).
-Refer to CHAPTER of "FIXEDVECTOR FUNCTION" for details on (x).
-At illegal standby mode transition detection reset, the status is a bus idle status after generating reset factor, so the status move to (ix).
-Super initialize reset (SINIT) is issued at the recovery from standby (power shutdown) (A). However, because of preventing a reset to
following block, the reset without SINIT to this block will be masked (B) during the reset period.
(1) RTC (only watch mode)
(2) External interrupt block
(3) Power management unit
(4) Clock generation block (only sub-clock selection register)
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5.5.1.
Reset Cycle
The reset cycle is shown.
After the release of reset factors, the reset request is extended during the 4 × peripheral clock (PCLK) cycle.
After that, a reset cycle will be maintained by the period of peripheral clock (PCLK) × 16 cycles for each reset level.
Thus, the minimum number of issue cycles for each reset is 20 cycles. If it requires the main clock oscillation
stabilization wait time, the cycle will be extended for the time required.
5.5.2.
Reset Release
The reset release is shown.
Once a reset cycle has completed, each reset will be released and each hardware starts running. Right after the reset
release, the mode control circuit functions as a bus master of on-chip bus.
5.5.3.
Operating Mode Fix
Operating mode fix is shown.
The mode control circuit as a bus master will notify the operating mode, which was determined based on the mode
setting value acquired, to each hardware component. Then, it will release the bus control of on-chip bus.
5.5.4.
Transition of Bus Control
Transition of bus control is shown.
After the mode control circuit releases the bus control of on-chip bus, the CPU acquires the bus control and starts
running bus operations by the CPU.
5.5.5.
Reset Vector Fetch
Reset vector fetch is shown.
After the reset release, the CPU starts fetching the reset vector.
After CPU acquires the bus control, the CPU accesses the reset vector through on-chip bus and retrieves the acquired
reset vector to the PC to start running programs.
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5.5.6.
Reset and Forced Break
Reset and forced break are shown.
If a forced break has occurred during the reset release, it accepts the forced break upon completion of the reset vector
fetch. Thus, the PC value by the reset vector acquired will be saved at the emulator space side.
5.6.
Notes
Notes are shown.
[MB91F52xxxC/MB91F52xxxE] During return form standby watch mode (power-shutdown) and standby stop mode
(power-shutdown), an internal reset is issued. Therefore any reset factor without power-on reset, internal low-voltage
detection reset, reset by simultaneous assertion of RSTX and NMIX will not be accepted.
[MB91F52xxxD] During return form standby watch mode (power-shutdown) and standby stop mode
(power-shutdown), an internal reset is issued. Therefore any reset factor without power-on reset, internal low-voltage
detection reset, reset by assertion of RSTX will not be accepted.
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Chapter 9: DMA Controller (DMAC)
This chapter explains the DMA controller (DMAC).
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
DMA Usage Examples
Code : FR81S10_DMA-1v1-91528-3-E
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Chapter 9: DMA Controller (DMAC)
1. Overview
This section explains the overview of the DMA controller (DMAC).
DMAC is the module which performs the DMA (Direct Memory Access) transfer. DMA transfer controlled by this
module enables the high speed transfer of variety of data without any interventions of a CPU, thus increases the
system performance.
2. Features
This section explains the features of the DMA controller (DMAC).
Channels: 16 channels
Address space: 32-bit address space (4 GB)
Transfer mode: Block/burst transfer
Address update: Increment/Decrement/Fixed (Address increment/decrement range : 1, 2, 4)
Transfer size : 8-bits, 16-bits, 32-bits
Block size: 1 to 16
Transfer count: 1 to 65535
Transfer request:
Software transfer requests
Transfer requests by peripheral interrupt (for the transfer request by peripheral interrupt, you should select
interrupt by channels. See "CHAPTER: GENERATION AND CLEARING OF DMA TRANSFER
REQUESTS".)
Transfer requests by on-chip bus IPs (A DMAC channel number corresponding to each on-chip bus IP cannot
be selected. See "5.2 Table for On-chip Bus IPs and Corresponding DMAC Channels".)
Transfer stop request : Transfer stop request by interrupts
Reload function : All channels can be specified for reload
Transfer source address reload
Transfer destination address reload
Transfer count reload
Priority :
Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ch.4 > ch.5 > ch.6 > ch.7 > ch.8 > ch.9 > ch.10 > ch.11 > ch.12 > ch.13 >
ch.14 > ch.15)
Or round robin
Interrupt request : Normal completion interrupt requests, abnormal completion interrupt requests, and transfer
suspend interrupt requests by transfer stop requests can be generated
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Chapter 9: DMA Controller (DMAC)
3. Configuration
This section explains the configuration of the DMA controller (DMAC).
Figure 3-1 Block Diagram
CPU
FLASH
RAM
On-chip
bus IP
DMA transfer
request caused
by on-chip bus
IP/clear circuit
On-chip bus
Peripheral
bus bridge
Master interface
Slave interface
Peripheral
Interrupt clear request
Interrupt request
Engine/Read
transfer
destination
Write transfer
destination
Data
buffer
Register
レジスタ
レジスタ
レジスタ
レジスタ
Register
control
Determining
priorities
Interrupt
controller
DMA transfer
request
caused by interrupt/
clear circuit
Accept
転送要求
転送要求
転送要求
転送要求
受付
transfer
受付
受付
受付
request
Transfer
転送承認
転送承認
転送承認
転送承認
acceptance/
／
／
／
／
Transfer
転送終了
転送終了
転送終了
転送終了
termination
DMAC
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Chapter 9: DMA Controller (DMAC)
4. Registers
This section explains registers of the DMA controller (DMAC).
Table 4-1 Registers Map
Registers
Address
Register function
+0
+1
0x0C00
0x0C04
+2
+3
DCCR0
DCSR0
DMA channel control register 0
DTCR0
DMA channel status register 0
DMA transfer count register 0
0x0C08
DSAR0
DMA transfer source address register 0
0x0C0C
DDAR0
DMA transfer destination address register 0
0x0C10
DCCR1
DMA channel control register 1
0x0C14
DCSR1
DTCR1
DMA channel status register 1
DMA transfer count register 1
0x0C18
DSAR1
DMA transfer source address register 1
0x0C1C
DDAR1
DMA transfer destination address register 1
0x0C20
DCCR2
DMA channel control register 2
0x0C24
DCSR2
DTCR2
DMA channel status register 2
DMA transfer count register 2
0x0C28
DSAR2
DMA transfer source address register 2
0x0C2C
DDAR2
DMA transfer destination address register 2
0x0C30
DCCR3
DMA channel control register 3
0x0C34
DCSR3
DTCR3
DMA channel status register 3
DMA transfer count register 3
0x0C38
DSAR3
DMA transfer source address register 3
0x0C3C
DDAR3
DMA transfer destination address register 3
0x0C40
DCCR4
DMA channel control register 4
0x0C44
DCSR4
DTCR4
DMA channel status register 4
DMA transfer count register 4
0x0C48
DSAR4
DMA transfer source address register 4
0x0C4C
DDAR4
DMA transfer destination address register 4
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Chapter 9: DMA Controller (DMAC)
Registers
Address
Register function
+0
+1
0x0C50
0x0C54
+2
+3
DCCR5
DCSR5
DMA channel control register 5
DTCR5
DMA channel status register 5
DMA transfer count register 5
0x0C58
DSAR5
DMA transfer source address register 5
0x0C5C
DDAR5
DMA transfer destination address register 5
0x0C60
DCCR6
DMA channel control register 6
0x0C64
DCSR6
DTCR6
DMA channel status register 6
DMA transfer count register 6
0x0C68
DSAR6
DMA transfer source address register 6
0x0C6C
DDAR6
DMA transfer destination address register 6
0x0C70
DCCR7
DMA channel control register 7
0x0C74
DCSR7
DTCR7
DMA channel status register 7
DMA transfer count register 7
0x0C78
DSAR7
DMA transfer source address register 7
0x0C7C
DDAR7
DMA transfer destination address register 7
0x0C80
DCCR8
DMA channel control register 8
0x0C84
DCSR8
DTCR8
DMA channel status register 8
DMA transfer count register 8
0x0C88
DSAR8
DMA transfer source address register 8
0x0C8C
DDAR8
DMA transfer destination address register 8
0x0C90
DCCR9
DMA channel control register 9
0x0C94
DCSR9
DTCR9
DMA channel status register 9
DMA transfer count register 9
0x0C98
DSAR9
DMA transfer source address register 9
0x0C9C
DDAR9
DMA transfer destination address register 9
0x0CA0
DCCR10
DMA channel control register 10
0x0CA4
DCSR10
DTCR10
DMA channel status register 10
DMA transfer count register 10
0x0CA8
DSAR10
DMA transfer source address register 10
0x0CAC
DDAR10
DMA transfer destination address register 10
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Chapter 9: DMA Controller (DMAC)
Registers
Address
Register function
+0
+1
0x0CB0
0x0CB4
+2
+3
DCCR11
DCSR11
DMA channel control register 11
DTCR11
DMA channel status register 11
DMA transfer count register 11
0x0CB8
DSAR11
DMA transfer source address register 11
0x0CBC
DDAR11
DMA transfer destination address register 11
0x0CC0
DCCR12
DMA channel control register 12
0x0CC4
DCSR12
DTCR12
DMA channel status register 12
DMA transfer count register 12
0x0CC8
DSAR12
DMA transfer source address register 12
0x0CCC
DDAR12
DMA transfer destination address register 12
0x0CD0
DCCR13
DMA channel control register 13
0x0CD4
DCSR13
DTCR13
DMA channel status register 13
DMA transfer count register 13
0x0CD8
DSAR13
DMA transfer source address register 13
0x0CDC
DDAR13
DMA transfer destination address register 13
0x0CE0
DCCR14
DMA channel control register 14
0x0CE4
DCSR14
DTCR14
DMA channel status register 14
DMA transfer count register 14
0x0CE8
DSAR14
DMA transfer source address register 14
0x0CEC
DDAR14
DMA transfer destination address register 14
0x0CF0
DCCR15
DMA channel control register 15
0x0CF4
DCSR15
DTCR15
DMA channel status register 15
DMA transfer count register 15
0x0CF8
DSAR15
DMA transfer source address register 15
0x0CFC
DDAR15
DMA transfer destination address register 15
0x0DF4
Reserved Reserved DNMIR DILVR
0x0DF8
DMACR
DMA control register
0x0DFC
Reserved
Reserved
DMA transfer suppression NMI flag register
DMA transfer suppression interrupt level register
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Chapter 9: DMA Controller (DMAC)
4.1.
DMA Control Register: DMACR (DMA Control Register)
This section explains the DMA control register.
The DMA control register is a 32-bit register to control the entire DMAC (all channels). This register must be
accessed as a 32-bit data.
DMACR : Address 0DF8H (Access: Word)
bit31
bit30
bit29
bit28
DME
Initial value
Attribute
bit27
bit26
bit25
bit24
Reserved
0
0
0
0
0
0
0
0
R/W
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit22
bit21
bit20
bit19
bit18
bit17
bit16
bit23
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AT
Initial value
Attribute
Reserved
0
0
0
0
0
0
0
0
R/W
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit3
bit2
bit1
bit0
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
[bit31] DME (DMA Enable) : DMA operation enable
This bit controls the operation of the entire DMAC. When this bit is "0", a DMA transfer will not be performed even
if operation of each channel is enabled. When this bit is "1", operations according to the settings for each channel are
performed.
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Chapter 9: DMA Controller (DMAC)
If "0" is written while a DMA transfer is in progress, the transfer is stopped in blocks specified in DCCRx.BLK.
DME
DMA operation enable
0
DMA operation disabled (Initial value)
1
DMA operation enabled
[bit30 to bit16] Reserved
Always write "0" to these bits. The read value is "0".
[bit15] AT (Arbitration Type) : Priority setting
This bit configures how to determine priority for each channel. If the priority is set to "fixed" (AT = 0), ascending
order, ch.0 > ch.1 > ch.2 > ch.3, is taken. If the priority is set to "round robin" (AT = 1), DMAC makes the priority of
the channel which started the transfer the lowest and raises the priority of following channels one by one. The
decision on priority is made on each transfer of a block unit specified in DCCRx.BLK regardless of the priority
setting.
AT
Priority setting
0
Fixed (initial value)
1
Round robin
[bit14 to bit0] Reserved
Always write "0" to these bits. The read value is "0".
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Chapter 9: DMA Controller (DMAC)
4.2.
DMA Channel Control Register 0 to 15: DCCR0 to 15 (DMA
Channel Control Register 0 to 15)
This section explains the bit configuration for DMA channel control register 0 to 15.
DMA channel control registers are 32-bit registers to control the operation of DMAC channels, which exists
independently for each channel. This register must be accessed as a 32-bit data.
DCCR0 to 15 : Address BASE + 0000H (Access: Word)
bit31
bit30
bit29
CE
Initial value
Attribute
Attribute
Initial value
Attribute
Initial value
Attribute
316
bit27
Reserved
bit26
bit25
bit24
AIE
SIE
NIE
0
0
0
0
0
0
0
0
R,W
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Reserved
Initial value
bit28
RS[1:0]
Reserved
TM[1:0]
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ST
SAR
DT
DAR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit2
bit1
bit0
SAC[1:0]
bit5
bit4
bit3
DAC[1:0]
bit7
bit6
TCR
Reserved
0
0
0
0
0
0
0
0
R/W
R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
TS[1:0]
BLK[3:0]
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Chapter 9: DMA Controller (DMAC)
[bit31] CE (Channel Enable) : Channel operation enable
This bit controls the operation of the channels. If the request source is set to "software", writing "1" to this bit starts a
DMA transfer according to the configuration. In this case, the CE bit is automatically cleared when the transfer
according to the transfer request completed.
If the request source is other than software, writing "1" to this bit makes channel operation enabled. After enabling
operation, a DMA transfer starts when the corresponding transfer request is detected. In case of a request other than
software, the CE bit will not be automatically cleared if transfer count reload (DCCRx.TCR) is specified. When
transfer count reload is disabled, the CE bit will be cleared when all transfers are finished.
If "0" is written while the operation is going on regardless of the request source, stop transfer in blocks specified in
DCCRx.BLK. When writing "1" again and detecting a new transfer request, the operation restarts.
CE
Channel operation enable
0
Disabled (initial value)
1
Enabled
[bit30 to bit27] Reserved
Always write "0" to these bits. The read value is "0".
[bit26] AIE (Abnormal completion Interrupt Enable) : Abnormal completion interrupt enable
This bit controls the generation of interrupts when setting the prohibited values to the DMA channel control register
(DCCR). The items not allowed to set to registers are listed below.
Transfer mode: DCCRx.TM = 10B
Transfer source address count: DCCRx.SAC = 10B
Transfer destination address count: DCCRx.DAC = 10B
Transfer size: DCCRx.TS = 11B
Demand transfer mode by software request: DCCRx.RS = 00B and DCCRx.TM = 11B
As for the interrupt factor, refer to the status register (DCSRx).
AIE
Abnormal completion interrupt enable
0
Disabled (initial value)
1
Enabled
[bit25] SIE (Stop Interrupt Enable) : Transfer suspend interrupt enabled by transfer stop requests
This bit controls the generation of interrupts when a DMA transfer is suspended by a transfer stop request from the
transfer request source. As for the interrupt factor, refer to the status register (DCSRx).
SIE
Transfer suspend interrupt enable
0
Disabled (initial value)
1
Enabled
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Chapter 9: DMA Controller (DMAC)
[bit24] NIE (Normal completion Interrupt Enable) : Normal completion interrupt enable
This bit controls the generation of interrupts when completing DMA transfers successfully. After completing transfers
as many times as set by transfer count (DTCRx.DTC) or when writing "1" to the corresponding channel's DCCRx.CE
bit at the time the transfer count is "0", the operation will complete normally. As for the interrupt factor, see the status
register (DCSRx).
NIE
Normal completion interrupt enable
0
Disabled (initial value)
1
Enabled
[bit23, bit22] Reserved
Always write "0" to these bits. The read value is "0".
[bit21, bit20] RS (Request Source) : DMA transfer request source
These bits select the transfer request source for the channel.
Setting RS[1:0] = 2'b11 is prohibited because there will be no transfers requested by an on-chip bus IP on ch.2 to
ch.15
RS[1:0]
DMA transfer request source
00
Software (initial value)
01
Interrupts
10
Reserved (setting is prohibited)
11
On-chip bus IP
[bit19, bit18] Reserved
Always write "0" to these bits. The read value is "0".
[bit17, bit16] TM (Transfer Mode) : Transfer mode
These bits specify the DMA transfer mode.
TM[1:0]
Transfer mode
00
Block transfer (initial value)
01
Burst transfer
10
Reserved (setting is prohibited)
11
Reserved (setting is prohibited)
[bit15] ST (Source Type) : Transfer source type
The setting values are different depending on the combinations of DMA transfer request source (DCCR.RS[1:0]),
transfer source address (DSAR), and transfer destination address (DDAR). As for the setting, see " Setting the ST
Bit (Transfer source type) and DT Bit (Transfer destination type)".
ST
Transfer source type
0
See " Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination
type)".
1
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Chapter 9: DMA Controller (DMAC)
[bit14] SAR (Source Address Reload) : Transfer source address reload
This bit specifies the transfer source address register reload. When specifying a reload, the transfer source address
register value is returned to the initial value at the end of the transfer. When disabling a reload, the transfer source
address register will point to the next access address to the last address at the end of the transfer.
SAR
Transfer Source address reload specified
0
Reload disabled (initial value)
1
Reload
[bit13, bit12] SAC (Source Address Count) : Transfer source address count
These bits specify the address update once for each transfer of the transfer source address. The update values when
specifying "increment/decrement" will be one of the values, 1, 2, 4 depending on the transfer size (DCCRx.TS).
SAC[1:0]
Transfer Source address count
00
Address increment (initial value)
01
Address decrement
10
Reserved (setting is prohibited)
11
Address fixed
[bit11] DT (Destination Type) : Transfer destination type
The setting values are different depending on the combinations of DMA transfer request source (DCCR.RS[1:0]),
transfer source address (DSAR), and transfer destination address (DDAR). As for the setting, see "Setting the ST
Bit (Transfer source type) and DT Bit (Transfer destination type)".
DT
Transfer destination type
0
See " Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination
type)".
1
[bit10] DAR (Destination Address Reload) : Transfer destination address reload
This bit specifies the transfer destination address register reload. When specifying a reload, the transfer destination
address register value is returned to the initial value at the end of the transfer. When disabling a reload, the transfer
destination address register will point to the next access address to the last address at the end of the transfer.
DAR
Transfer destination address reload specified
0
Reload disabled (initial value)
1
Reload
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Chapter 9: DMA Controller (DMAC)
[bit9, bit8] DAC (Destination Address Count) : Transfer destination address count
These bits specify the address update once for each transfer of the transfer destination address. The update values
when specifying "increment/decrement" will be one of the values, 1, 2, 4 depending on the transfer size (DCCRx.TS).
DAC[1:0]
Transfer destination address count
00
Address increment (initial value)
01
Address decrement
10
Reserved (setting is prohibited)
11
Address fixed
[bit7] TCR (Transfer Count Reload) : Transfer count reload
This bit specifies the transfer count register reload.
When specifying a reload, the transfer count register value is returned to the initial value at the end of the transfer. If
the transfer request source is set other than "software", DCCRx.CE bit will not be cleared at the end of the transfer
and the operation will go into the transfer request wait state. When disabling a reload, the transfer count register value
at the end of the transfer will point to "0". In this case, DCCRx.CE bit will be cleared at the end of the transfer
regardless of the transfer request source.
TCR
Transfer count reload
0
Reload disabled (initial value)
1
Reload
[bit6] Reserved
Always write "0" to this bit. The read value is "0".
[bit5, bit4] TS (Transfer Size) : Transfer size
These bits specify the transfer size. DMA transfers will be performed once with the bit width specified here.
TS[1:0]
Transfer size
00
8-bit :byte (initial value)
01
16-bit :half-word
10
32-bit :word
11
Reserved (setting is prohibited)
Set values to DSARx and DDARx registers so as not to cause a misalignment for the transfer size specified in these
bits.
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Chapter 9: DMA Controller (DMAC)
[bit3 to bit0] BLK (BlocK size) : Block size
These bits specify the block size. 1 block transfer will be repeated for the number of blocks of the transfer size
specified with DCCRx.TS bit.
BLK[3:0]
Transfer count
0000
Once (initial value)
0001
Twice
0010
3 times
0011
4 times
0100
5 times
0101
6 times
0110
7 times
0111
8 times
1000
9 times
1001
10 times
1010
11 times
1011
12 times
1100
13 times
1101
14 times
1110
15 times
1111
16 times
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Chapter 9: DMA Controller (DMAC)
4.3.
DMA Channel Status Register 0 to 15 : DCSR0 to 15: (DMA
Channel Status Register 0 to 15)
This section explains the bit configuration for DMA channel status register 0 to 15.
These registers are 16-bit registers to indicate the status for each DMAC channel, which exist independently for each
channel. These registers must be accessed as a 16-bit data.
DCSR0 to 15: Address BASE + 0004H (Access: Half-word)
bit15
bit14
bit13
bit12
CA
Initial value
Attribute
bit11
bit9
bit8
Reserved
0
0
0
0
0
0
0
0
R,WX
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AC
SP
NC
Reserved
Initial value
Attribute
bit10
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R,W
R,W
R,W
[bit15] CA (Channel Active) : Channel active
This bit indicates the channel operating state. Writing "1" to the corresponding DCCRx.CE bit for the channel makes
it in the operating state. Completing transfers for as many times as set transfer count or writing "0" to DCCRx.CE
makes the operation stop.
Writing this bit is ignored.
CA
Channel operating state
0
Stop state (initial value)
1
Channel operating
[bit14 to bit3] Reserved
Always write "0" to these bits. The read value is "0".
[bit2] AC (Abnormal Completion) : Abnormal completion state
This bit indicates that a prohibited value has been set to the DMA channel control register (DCCR). The items not
allowed to set to registers are listed below.
Transfer mode: DCCRx.TM = 10B
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Transfer source address count: DCCRx.SAC = 10B
Transfer destination address count: DCCRx.DAC = 10B
Transfer size: DCCRx.TS = 11B
Demand transfer mode by software request: DCCRx.RS = 00B and DCCRx.TM = 11B
When having allowed the abnormal completion interrupt (DCCRx.AIE), writing "0" to this bit clears the interrupt.
Writing "1" to this bit is ignored.
Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically.
AC
Abnormal completion state
0
Abnormal completion undetected (initial value)
1
Abnormal completion
[bit1] SP (StoP) : Transfer suspend state by the transfer stop request
This bit indicates that a DMA transfer has been suspended by a transfer stop request from the transfer request source.
When having allowed the transfer suspension interrupt (DCCRx.SIE), writing "0" to this bit clears the interrupt.
Writing "1" to this bit is ignored.
Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically.
SP
Transfer suspend state
0
Transfer suspend undetected (initial value)
1
Transfer suspend
[bit0] NC (Normal Completion) : Normal completion state
This bit indicates that DMA transfer has been completed successfully. After completing transfers as many times as set
by transfer count or when writing "1" to the corresponding channel's "DCCRx.CE" bit at the time the transfer count is
"0", the operation will complete normally. When having allowed the normal completion interrupt (DCCRx.NIE),
writing "0" to this bit clears the interrupt. Writing "1" to this bit is ignored.
Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically.
NC
Normal completion state
0
Normal completion undetected (initial value)
1
Normal completion
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Chapter 9: DMA Controller (DMAC)
4.4.
DMA Transfer Count Register 0 to 15 : DTCR0 to 15: (DMA
Transfer Count Register 0 to 15)
This section explains the bit configuration for DMA transfer count register 0 to 15.
These registers are 16-bit registers to indicate the transfer count for each DMAC channel, which exist independently
for each channel. These registers must be accessed as a 16-bit data.
DTCR0 to 15: Address BASE + 0006H (Access: Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DTC[15:8]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTC[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
[bit15 to bit0] DTC (DMA Transfer Count) : DMA transfer count
These registers indicate the number of transfers. DMAC decreases a transfer count at the end of each block transfer
and stops the transfer when the transfer count becomes "0". If "0" is set for transfer count, transfer will not be
performed. Also, the dedicated reload register is provided. If DCCRx.TCR is "1", the value is returned to the initial
value after data transfer.
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Chapter 9: DMA Controller (DMAC)
4.5.
DMA Transfer Source Register 0 to 15 : DSAR0 to 15: (DMA
Source Address Register 0 to 15)
This section explains the bit configuration for DMA transfer source register 0 to 15.
These registers are 32-bit registers to indicate the transfer source address of each DMAC channel, which exist
independently for each channel. These registers must be accessed as a 32-bit data.
DSAR0 to 15: Address BASE + 0008H (Access: Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
DSA[31:24]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
DSA[23:16]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DSA[15:8]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DSA[7:0]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
[bit31 to bit0] DSA[31:0] (DMA Source Address) : DMA transfer source address
These registers indicate the transfer source address. If an increment or a decrement is set by DCCRx.SAC, the address
is updated according to the transfer size (DCCRx.TS). Also, the dedicated reload register is provided. If DCCRx.SAR
is "1", the value is returned to the initial value after data transfer.
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Chapter 9: DMA Controller (DMAC)
Set a value in these registers not to cause a misalignment against the transfer size to be set by DCCRx.TS.
If the DMA transfer request source has a peripheral interrupt (DCCRx.RS[1:0]=01), at least either the transfer source
address (DSAR) or the transfer destination address (DDAR) must be within the address range of peripheral under
control of 16-bit peripheral bus or 32-bit peripheral bus. For details, see " Setting the ST Bit (Transfer source type)
and DT Bit (Transfer destination type)".
4.6.
DMA Transfer Destination Register 0 to 15 : DDAR0 to 15
(DMA Destination Address Register 0 to 15)
This section explains the bit configuration for DMA transfer destination register 0 to 15.
These registers are 32-bit registers to indicate the transfer destination address of each DMAC channel, which exist
independently for each channel. These registers must be accessed as a 32-bit data.
DDAR0 to 15: Address BASE + 000CH (Access: Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
DDA[31:24]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
DDA[23:16]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DDA[15:8]
Initial value
Attribute
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DDA[7:0]
Initial value
Attribute
326
X
X
X
X
X
X
X
X
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
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Chapter 9: DMA Controller (DMAC)
[bit31 to bit0] DDA[31:0] (DMA Destination Address) : DMA transfer destination address
These registers indicate the transfer destination address. If an increment or a decrement is set by DCCRx.DAC, the
address is updated according to the transfer size (DCCRx.TS). Also, the dedicated reload register is provided. If
DCCRx.DAR is "1", the value is returned to the initial value after data transfer.
Set a value in these registers not to cause a misalignment against the transfer size to be set by DCCRx.TS.
If the DMA transfer request source has a peripheral interrupt (DCCRx.RS[1:0]=01), at least either the transfer source
address (DSAR) or the transfer destination address (DDAR) must be within the address range of peripheral under
control of 16-bit peripheral bus or 32-bit peripheral bus. For details, see " Setting the ST Bit (Transfer source type)
and DT Bit (Transfer destination type)".
4.7.
DMA Transfer Suppression NMI Flag Register : DNMIR
(DMA-halt by NMI Register)
This section explains the bit configuration for DMA transfer suppression flag register.
This register is 8-bit register to suppress DMA transfer by the user NMI. This register must be accessed as a 8-bit
data.
DNMIR: Address 0DF6H (Access: Byte)
bit7
bit6
bit5
NMIH
Initial value
Attribute
bit4
bit3
bit2
bit1
Reserved
bit0
NMIHD
0
0
0
0
0
0
0
0
R,W
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
[bit7] NMIH (NMI Halt) : DMA suppression flag (by NMI factor)
If the NMIHD bit is "0", this flag shows an occurrence of the user NMI request. The "H" level of NMI is detected,
and this bit is set to "1". To restart DMA transfer, set this bit to "0".
Writing "1" to this bit is ignored.
NMIH
DMA suppression flag
0
DMA transfer is not suppressed. (Initial value)
1
The DMA transfer has been stopped by user NMI.
[bit6 to bit1] Reserved
Always write "0" to these bits. The read value is "0".
[bit0] NMIHD (NMI Halt Disable) : DMA suppression control (by NMI factor)
The control bit that stops DMA transfer if a user NMI request is generated.
If an NMI occurs when this bit is "0", the DMAC does not restart a new DMA transfer. During DMA transfer, the
controller stops the current DMA transfer when a block unit transfer has completed.
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NMIHD
4.8.
DMA suppression control
0
Stops the DMA transfer by the user NMI. (initial value)
1
Does not stop the DMA transfer by the user NMI.
DMA Transfer Suppression Level Register : DILVR
(DMA-halt by Interrupt Level Register)
This section explains the bit configuration for DMA transfer suppression level register.
This register is 8-bit register to control the DMA transfer suppression by peripheral interrupts. This register must be
accessed as a 8-bit data.
DILVR: Address 0DF7H (Access: Byte)
bit7
bit6
bit5
Reserved
Initial value
Attribute
bit4
bit3
bit2
LVL4
bit1
bit0
LVL[3:0]
0
0
0
1
1
1
1
1
R0,W0
R0,W0
R0,W0
R1,WX
R/W
R/W
R/W
R/W
[bit7 to bit5] Reserved
Always write "0" to these bits. The read value is "0".
[bit4 to bit0] LVL (Level) : DMA suppression interrupt level
These bits set an interrupt level for suppression of DMA transfer. If a peripheral interrupt having an interrupt level
higher than the one specified by this register occurs, the DMA transfer is suppressed. LVL4 is fixed to "1", but
LVL[3:0] can be set to any level.
LVL[4:0]
328
DMA suppression control
11111
Suppresses the DMA transfer when any peripheral interrupt request is issued.
(initial value)
11110
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1EH is issued.
11101
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1DH is issued.
11100
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1CH is issued.
11011
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1BH is issued.
11010
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1AH is issued.
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Chapter 9: DMA Controller (DMAC)
LVL[4:0]
DMA suppression control
11001
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 19H is issued.
11000
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 18H is issued.
10111
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 17H is issued.
10110
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 16H is issued.
10101
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 15H is issued.
10100
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 14H is issued.
10011
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 13H is issued.
10010
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 12H is issued.
10001
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 11H is issued.
10000
Does not suppress the DMA transfer when a peripheral interrupt request is issued.
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Chapter 9: DMA Controller (DMAC)
5. Operation
This section explains the operation of the DMA controller (DMAC).
5.1. Configuration
5.1.
Configuration
This section explains the configuration for DMAC operation.
The following explains the setting items common to all channels and the items to be set separately for each channel.
5.1.1.
Common Items for All Channels
The common Items for all channels is shown below.
This section explains the register settings for control of the entire DMAC.
DMA Operation Enable
The entire DMAC operation can be controlled using the DMACR.DME.
DMA operation disabled (DMACR.DME = 0)
DMA operation enabled (DMACR.DME = 1)
Channel Priority
A channel priority can be set by the DMACR.AT.
Fixed priority (DMACR.AT = 0)
Round robin (DMACR.AT = 1)
DMA Transfer Suppression Setting for Interrupt Occurrence
The DMA transfer suppression control during user NMI occurrence can be set by the DNMIR.NMIHD.
Stops DMA transfer by the user NMI. (DNMIR.NMIHD = 0)
Does not stop DMA transfer by the user NMI. (DNMIR.NMIHD = 1)
Also, an interrupt level, which precedes the DMA transfer when an interrupt occurs, can be set by DILVR.LVL.
Allowed interrupt levels are 0x1F to 0x10.
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Chapter 9: DMA Controller (DMAC)
5.1.2.
Separate Items for Each Channel
The items set separately for each channel are shown.
The following explains both the items to be set separately for each channel and the register setup procedure.
Register Setup Procedure
The channel registers must be set in the following procedure. When you set the DCCRx.CE bit to "1", be sure to set
the DTCRx to 1 or a higher value.
1. Clear the DCCRx.CE bit to disable the channel operation.
2. Clear each bit of DCSRx register to initialize the channel status flag.
3. Set the transfer source address (to be used when the transfer starts) in the DSARx register.
4. Set the transfer destination address (to be used when the transfer starts) in the DDARx register.
5. Set the transfer count in the DTCRx register. This count must be 1 or a larger value.
6.1 If transfer is started by a peripheral interrupt, the occurrence of each peripheral interrupt must be enabled and the
ICSEL and IORR registers must be set. (See the "CHAPTER: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS" about the ICSEL and IORR registers.)
6.2 If transfer is started by an on-chip bus IP, enable DMA transfer requests by each on-chip bus IP.
7. Set the DCCRx register. During this time, the channel operation is enabled when the DCCRx.CE bit is set.
Figure 5-1 Channel Register Setup Procedure
Start settings
1. Clear DCCRx.CE bit
2. Clear DCSRx to the initial state
3. Set DSARx
4. Set DDARx
5. Set DTCRx
6.1 Settings for activation by interrupt
6.2 Settings for activation by on-chip
bus IP
7. Set DCCRx
End settings
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Transfer Source Address and the Transfer Destination Address Setting
Set the transfer source address (to be used when the transfer starts) using the DSARx.DSA.
Set the transfer destination address (to be used when the transfer starts) using the DDARx.DDA.
Align the transfer source and destination addresses based on the transfer size (DCCRx.TS), and ignore the lower 1 bit
or lower 2 bits for 16-bit or 32-bit transfer size respectively.
Transfer Count Setting
Set the number of times of block transfer (repeated to the end of transfer) using the DTCRx.DTC. The transfer count
can be 1 to 65535 times. The DMAC transfers data (1 block data), whose length in bytes is set by the transfer size and
block size (see " Transfer Size and Block Size Setting") for the specified number of times.
Channel Operation Enable
Set the channel operation control using the DCCRx.CE.
Disable the channel operation (DCCRx.CE = 0)
Enable the channel operation (DCCRx.CE = 1)
When the software is selected at the transfer request source and when the DCCRx.CE bit is set, the channel operation
is enabled and data transfer is started.
Interrupt Enable Setting
Enable an interrupt during abnormal completion, using the DCCRx.AIE.
Disable an abnormal completion interrupt (DCCRx.AIE = 0)
Enable an abnormal completion interrupt (DCCRx.AIE = 1)
Using the DCCRx.SIE, enable an interrupt to occur if data transfer is suspended by a transfer stop request.
Disable a transfer suspend interrupt during detection of transfer stop request (DCCRx.SIE = 0)
Enable a transfer suspend interrupt during detection of transfer stop request (DCCRx.SIE = 1)
Enable an interrupt during normal completion, using the DCCRx.NIE.
Disable a normal completion interrupt (DCCRx.NIE = 0)
Enable a normal completion interrupt (DCCRx.NIE = 1)
Transfer Request Source setting
Set the transfer request source to accept a transfer request using the DCCRx.RS.
Request by software (DCCRx.RS = 00)
Request by an interrupt (DCCRx.RS = 01)
Request by an on-chip bus peripheral (DCCRx.RS = 11) (* x is 0 or 1)
Transfer Mode Setting
Set the DMA transfer mode using the DCCRx.TM.
Block transfer (DCCRx.TM = 00)
Burst transfer (DCCRx.TM = 01)
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Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination type)
Set them by following the table definition below. The DMA transfer is not supported in combinations (5) and (9).
Table 5-1 ST Bit (Transfer Source Type) and DT Bit (Transfer Destination Type) Setting
Combination of transfer request source, transfer
source, and transfer destination
Transfer request source
(DCCR.RS[1:0])
(1)
Request by software
(DCCR.RS[1:0] = 00)
Transfer
source
(DSAR)
Transfer
destination
(DDAR)
Any combination
DMA
transfer
support
ST and DT bit setting
Supported
ST= 0, DT= 0
Supported
ST= 1, DT= 0
Supported
ST= 0, DT= 1
Supported
ST= 0, DT= 1
(5)
Not
supported
-
(6)
Supported
ST= 1, DT= 0
Supported
ST= 0, DT= 1
Supported
ST= 0, DT= 1
Not
supported
-
(2)
(3)
(4)
(7)
(8)
Peripheral bus peripheral
interrupt
(DCCR.RS = 01)
On-chip bus peripheral
interrupt
(DCCR.RS = 11)
(9)
: Address range of the peripheral under control of 16-bit peripheral bus or 32-bit peripheral bus
: Other address range
: Address range of peripheral under control of on-chip bus
: Other address range
If the ST and DT bits are set in a combination other than above, the interrupt may not be cleared automatically after
occurrence of the DMA transfer request.
Peripheral Bus Area
Address Area
000000H to 0002FFH
000400H to 0005FFH
000E00H to 001FFFH
On-chip Bus Area
000900H to 000AFFH
002000H to 00EFFFH
Transfer Address Reload Setting
Using the DCCRx.SAR, set the reload control of transfer source address at the end of transfer.
The transfer source address is not reloaded after the transfer. (The next access address after the last address is
shown.) (DCCRx.SAR=0)
The transfer source address is returned to the initial value at the end of transfer. (DCCRx.SAR=1)
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Chapter 9: DMA Controller (DMAC)
Using the DCCRx.DAR, set the reload control of transfer destination address at the end of transfer.
The transfer destination address is not reloaded after the transfer. (The next access address after the last address is
shown.) (DCCRx.DAR=0)
The transfer destination address is returned to the initial value at the end of transfer. (DCCRx.DAR=1)
Transfer Address Update Setting
Using the DCCRx.SAC, set the updating of transfer source address for DMA transfer.
Address is increased. (DCCRx.SAC = 00)
Address is decreased. (DCCRx.SAC = 01)
Address is fixed. (DCCRx.SAC = 11)
Using the DCCRx.DAC, set the updating of transfer destination address for DMA transfer.
Address is increased. (DCCRx.DAC = 00)
Address is decreased. (DCCRx.DAC = 01)
Address is fixed. (DCCRx.DAC = 11)
Transfer Count Reload Setting
Using the DCCRx.TCR, set the reload control of transfer count at the end of transfer.
The transfer count is not reloaded after the transfer. (After the normal completion of transfer, the transfer count is
set to 0.) (DCCRx.TCR=0)
The transfer count is returned to the initial value at the end of transfer. (DCCRx.TCR=1)
Transfer Size and Block Size Setting
To set a transfer unit for DMA transfer (the byte count to be transferred as 1 block), set the transfer size and block
size.
Using the DCCRx.TS, set the size of data to be sent by a single DMA transfer (8-bit/16-bit/32-bit).
8-bit (DCCRx.TS = 00)
16-bit (DCCRx.TS = 01)
32-bit (DCCRx.TS = 10)
Using the DCCRx.BLK, set the DMA transfer count for 1-block data transfer. The block size can be 1 to 16 times. In
the 1-block transfer, data having the bit width being set by the transfer size (DCCRx.TS), is transferred for the
number of times being set by the block size.
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5.1.3.
Operations
This section explains DMAC operations.
This section explains the DMAC operations as follows.
(1) Channel status check
(2) Data transfer
Channel Status Check
Each DMAC channel status can be checked using the DCSRx register.
When the channel operation is enabled (the channel is active), the DCSRx.CA bit is "1". When the channel is
stopped, its status is shown as "0".
If data transfer terminates abnormally, the DCSRx.AC bit is set to "1".
If data transfer is suspended by the transfer stop request, the DCSRx.SP bit is set to "1".
When data transfer terminates normally, the DCSRx.NC bit is set to "1".
Data writing to the DCSRx.CA bit is ignored.
The DCSRx.AC, DCSRx.SP, and DCSRx.NC bits must be cleared before the DMA transfer is allowed because these
bits are not cleared automatically.
Data Transfer
The DMAC starts DMA transfer when the transfer source address and transfer destination address are set. By
receiving a transfer source read instruction, this controller reads the data, having the bit width (8-bit/16-bit/32-bit)
being set by DCCRx.TS, from the transfer source address, and temporarily stores it in the data buffer inside of the
DMAC. By receiving a transfer destination write instruction, the controller writes the data temporarily stored in the
DMAC into the transfer destination address.
Transfer Mode
The transfer mode has block transfer mode or burst transfer mode.
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Block Transfer Mode
1-time transfer request causes the 1 block transfer. When a transfer request is detected after the block transfer, the
next 1-block transfer occurs. These operations are repeated until the end of data transfer. During 1-block data transfer,
the data having the size specified by the DCCRx.TS bit is transferred for the number of times being set by the block
size.
Figure 5-2 Each Transfer Mode (Block Transfer)
Start
Set DMACR, DNMIR, DILVR,
DSAR, DDAR, DCSR, DTCR,
DCCR
NO
Transfer request?
Transfer request wait
YES
NO
Priority?
Priority wait
YES
Transfer source access
NO
Transfer destination access
NO
BLK count?
YES
DTC count?
YES
Transfer end
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Chapter 9: DMA Controller (DMAC)
Burst transfer mode
1-time transfer request causes the continuous data transfer until the end of transfer. (Data having the size set by the
DCCRx.TS bit is transferred continuously for the block size × number of transfers.)
Figure 5-3 Each Transfer Mode (Burst Transfer)
Start
Set DMACR, DNMIR, DILVR,
DSAR, DDAR, DCSR, DTCR,
DCCR
NO
Transfer request wait
Transfer request?
YES
Priority wait
Priority?
NO
YES
Transfer source access
Transfer destination access
BLK count ?
NO
YES
NO
DTC count ?
YES
Transfer end
Transfer request
The transfer request has a request by software or a request by interrupt. The following explains the relationship
between the transfer request detection conditions and the transfer mode.
Request by software
If the DCCRx.CE bit is set to "1", a transfer request is detected. When the DMA operation is enabled
(DMACR.DME=1), the priority is determined and the data transfer is started immediately. When the data transfer by
the transfer request has terminated, the DCCRx.CE bit is cleared automatically.
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Request by interrupt
If the channel operation is enabled (DCCRx.CE=1), a transfer request is awaited. If a peripheral interrupt, being set
by the interrupt controller, has occurred, its transfer request is detected. When the DMA operation is enabled
(DMACR.DME=1), the priority is determined and the data transfer is started immediately.
When a transfer stop request is asserted from the peripheral, a transfer request is not detected.
Also, an interrupt vector to be used for transfer request must be set for each channel. See the section "CHAPTER:
GENERATION AND CLEARING OF DMA TRANSFER REQUESTS".
Note:
As the interrupt request from peripherals is detected by an edge, the transfer request cannot be detected even if the CE
bit is reset from "0" to "1" while the interrupt request is enabled. The interrupt of the peripheral function should be
enabled after the CE bit is set to "1".
Table 5-2 Relationship between Transfer Request Detection Conditions and Transfer Mode
Block transfer
Burst transfer
Request by software
Set the DCCRx.CE bit to "1".
Set the DCCRx.CE bit to
"1".
Request by interrupt
Edge detection
Edge detection
Request by on-chip bus IP
Edge detection
Edge detection
Also, the relationship between the detected transfer request and the DMACR.DME and DCCRx.CE bits is given on
Table 5-3. If the DME bit or CE bit is cleared during transfer, the block transfer is stopped.
Table 5-3 Relationship between Transfer Requests and DME/CE Bits
DME bit
The already detected transfer request is
not cleared.
DME/CE clear
DME/CE
setting after
the transfer
interrupt
Block transfer
Burst transfer
CE bit
The already detected transfer
request is cleared.
When a new transfer request is detected,
the data transfer is restarted based on the
priority.
When a new transfer request is
detected, the data transfer is
When the DME bit is set, the data transfer restarted based on the priority.
is restarted immediately based on the
priority.
Standby recovery request by DMA transfer request
If the MCU receives a transfer request in the standby mode, the DMAC requests the MCU to recover from the
standby mode. If data transfer is enabled and if a transfer request is asserted by the transfer request source, a standby
recovery is requested.
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Channel priority
If multiple transfer requests are issued, the DMAC starts data transfer on the channel having the highest priority. The
channel priority can be fixed or can be set by round robin. The priority is determined for each block transfer or when
data transfer ends.
Fixed priority (DMACR.AT = 0)
The channel priority is fixed in the sequence of "ch.0 > ch.1 > ch.2 > ch.3". The following gives an example.
Example 1 : If transfer requests are issued on ch.0, ch.1 and ch.3 simultaneously, data transfer starts from ch. 0. When
data transfer ends on ch.0, the next data transfer starts on ch.1. After data transfer on ch.1, the next data transfer starts
on ch.3. The following gives transfer examples. Dotted lines in the figure show the block delimiters.
Transfer request : Requests are issued for ch.0, ch.1 and ch.3 simultaneously.
Setting : Ch.0, ch.1 and ch.3 are set to the burst transfer mode, and a data transfer count of 3.
Figure 5-4 Data Transfer Example 1 If Channel Priority Is Fixed
Transfer request is generated
on ch.0, ch.1, ch.3
ch.0
ch.1
ch.3
ch.0
transfer end
ch.1
transfer end
ch.3
transfer end
Example 2: If transfer requests are issued simultaneously for ch.1 and ch.3 and if a transfer request on ch.0 is issued
during data transfer on ch.1, the data transfer on ch.1 is temporarily stopped and data transfer on ch.0 is started.
During this time, the channel transition occurs in units of blocks. When the requested data transfer ends on ch.0, the
data transfer is started on ch.1. Dotted lines in the figure show the block delimiters.
Transfer request : Requests are issued for ch.1 and ch.3 simultaneously. When data is transferred on ch.1, another
request for transfer on ch.0 is issued.
Setting : Ch.0, ch.1 and ch.3 are set to the burst transfer mode, and data transfer count of 3.
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Figure 5-5 Data Transfer Example 2 If Channel Priority Is Fixed
Transfer request is generated on ch.1, ch.3
Transfer request is generated on ch.0
ch.0
ch.1
ch.3
ch.1 transfer end
ch.3 transfer end
ch.0 transfer end
Round robin (DMACR.AT = 1)
When data transfer is started on a channel, its priority is set to the lowest level. A channel priority below this level
is raised by one level. In the round robin, data transfer starts on a channel having the highest priority when a
transfer request is issued. The priority of the channel where data transfer has started is dropped to the lowest level.
The priority is determined for each of block data transfer, and data transfer is started on the channel having the
highest priority. The following gives a transfer example. Dotted lines in the figure show the block delimiters.
Example : Transfer request : Requests are issued for ch.0, ch.1 and ch.3 simultaneously.
Setting
340
: Ch.0, ch.1 and ch.3 are set to the burst transfer mode; and data transfer count of 3.
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Figure 5-6 Data Transfer Example If Channel Priority Is Set by Round Robin
ch.0 transfer end
ch.1 transfer end
Transfer request
is generated on
ch.3 transfer end
ch.0
ch.1
ch.3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Channel priority for each block
(1) ch.0 > ch.1 > ch.2 > ch.3
(2) ch.1 > ch.2 > ch.3 > ch.0
(3) ch.2 > ch.3 > ch.0 > ch.1
(4) ch.2 > ch.0 > ch.1 > ch.3
(5) ch.2 > ch.1 > ch.3 > ch.0
(6) ch.2 > ch.3 > ch.0 > ch.1
(7) ch.2 > ch.0 > ch.1 > ch.3
(8) ch.2 > ch.1 > ch.3 > ch.0
(9) ch.2 > ch.3 > ch.0 > ch.1
(10) ch.2 > ch.0 > ch.1 > ch.3
Updating of transfer address
The transfer source address and transfer destination address are updated each time data which size has been set by the
DCCRx.TS is transferred. The address updating can be increasing, decreasing, or fixed. When increasing or
decreasing, its address amount is determined by the transfer size (DCCRx.TS). If fixed, the address value does not
change. Table 5-4 shows the address increasing or decreasing width during address updating. If an overflow occurs
due to address updating, the relevant bit is discarded.
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Table 5-4 Updating of Transfer Source Address and Transfer Destination Address
Address setting
Transfer source
(SAC)
Transfer destination
(DAC)
Increments ("00")
Increments ("00")
Decrements ("01")
Fixed ("11")
Increments ("00")
Decrements ("01")
Decrements ("01")
Fixed ("11")
Increments ("00")
Fixed ("11")
Decrements ("01")
Transfer size (TS)
Address updating for each data
transfer
Transfer source
(DSA)
Transfer
destination (DDA)
8-bit ("00")
Increments by 1
Increments by 1
16-bit ("01")
Increments by 2
Increments by 2
32-bit ("10")
Increments by 4
Increments by 4
8-bit ("00")
Increments by 1
Decrements by 1
16-bit ("01")
Increments by 2
Decrements by 2
32-bit ("10")
Increments by 4
Decrements by 4
8-bit ("00")
Increments by 1
16-bit ("01")
Increments by 2
32-bit ("10")
Increments by 4
8-bit ("00")
Decrements by 1
Increments by 1
16-bit ("01")
Decrements by 2
Increments by 2
32-bit ("10")
Decrements by 4
Increments by 4
8-bit ("00")
Decrements by 1
Decrements by 1
16-bit ("01")
Decrements by 2
Decrements by 2
32-bit ("10")
Decrements by 4
Decrements by 4
8-bit ("00")
Decrements by 1
16-bit ("01")
Decrements by 2
32-bit ("10")
Decrements by 4
Not updated
Not updated
8-bit ("00")
Increments by 1
16-bit ("01")
Increments by 2
32-bit ("10")
Increments by 4
8-bit ("00")
Decrements by 1
16-bit ("01")
32-bit ("10")
Not updated
Decrements by 2
Decrements by 4
8-bit ("00")
Fixed ("11")
16-bit ("01")
Not updated
32-bit ("10")
Reloading of transfer address
The DMAC can reload the transfer address after the specified number of data transfer has completed.
Reloading of transfer source address
If the reloading of transfer source address has been set, the DSARx.DSA bit is returned to the initial value after
the data transfer.
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If the reloading of transfer source address is disabled, the DSARx.DSA bit indicates the next access address of the
last address after the current data transfer.
If the specified number of transfers is suspended or abnormally terminated, the DSARx.DSA bit indicates the next
access address (after the terminated address) regardless of the reload setting of the transfer source address.
Figure 5-7 Reloading of Transfer Source Address Register
Register settings
(register write)
Transfer source
address register
Transfer source
address reload register
Reload after the transfer
Update register
Reloading of transfer destination address register
If the reloading of the transfer destination address has been set, the DDARx.DDA bit is returned to the initial
value after the data transfer.
If the reloading of the transfer destination address is disabled, the DDARx.DDA bit indicates the next access
address of the last address after the current data transfer.
If the specified number of transfers is suspended or abnormally terminated, the DDARx.DDA bit indicates the
next access address (after the terminated address) regardless of the reload setting of the transfer destination
address.
Figure 5-8 Reloading of Transfer Destination Address Register
Register settings
(register write)
Transfer destination
address register
Transfer destination
address reload register
Reload after the transfer
Update register
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Reloading of transfer count
If the reloading of the transfer count has been set, the DTCRx.DTC bit is returned to the initial value after the data
transfer.
If reloading of the transfer count is disabled, the DTCRx.DTC bit is set to "0" after the data transfer.
If the specified number of transfers is suspended or abnormally terminated, the DTCRx.DTC bit indicates the
remaining transfer count regardless of the reload setting of the transfer count.
Figure 5-9 Reloading of Transfer Count Register
Register settings
(register write)
Transfer count
reload register
Transfer count register
Reload after the transfer
Update register (-1)
The DCCRx.CE bit status varies after the data transfer, depending on the reload setting of the transfer count. The
following explains the relation between the transfer count reload setting and the transfer request source.
Table 5-5 DCCRx.CE Bit at the End of Transfer
Software request
Non-software request
If the reloading of transfer
count is set
The DCCRx.CE bit is cleared
The DCCRx.CE bit is not cleared
If the reloading of transfer
count is disabled
The DCCRx.CE bit is cleared
The DCCRx.CE bit is cleared
Transfer suspension
The DMAC suspends the DMA transfer due to the following causes.
A suspension as the DMACR.DME bit is cleared
A suspension as the DCCRx.CE bit is cleared
A suspension caused by the transfer stop request by the transfer request source peripheral
Data transfer is suspended in units of blocks. If data transfer is suspended, the next transfer is not started. Data
transfer is stopped. The settings to restart data transfer vary depending on the suspension cause.
A suspension as the DMACR.DME bit is cleared
If the DMACR.DME bit is cleared, all channels are stopped from operating. After a block of data has been
transferred on the current channel, the data transfer is suspended. To restart data transfer, set the DMACR.DME
bit.
A suspension as the DCCRx.CE bit is cleared
If the DCCRx.CE bit is cleared, the channel is stopped from operating. After a block of data has been transferred,
the data transfer is suspended. Also, as the DCCRx.CE bit is cleared, the already detected transfer request is
cleared. To restart data transfer, set the DCCRx.CE bit for the stopped channel and issue a new transfer request.
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A transfer stop request from the transfer request source peripheral
The following peripherals can issue a transfer stop request under certain conditions.
(A) Multi-function serial interface
If a PE, FRE, or ORE flag is set
(B) LIN
If a PE, FRE, or ORE flag is set
If a transfer stop request is issued, the transfer is suspended after one block of the current data has been transferred. If
the data transfer is suspended, the following occur.
The SP bit of DMA channel status registers (DCSR0 to DCSR15) is set to "1".
The CE bit of DMA channel control registers (DCCR0 to DCCR15) is set to "0".
The already detected transfer request is cleared.
While a transfer stop request being issued, a new transfer request is rejected. Restart the DMA transfer in the
following procedure.
1.
2.
3.
4.
Clear the flags described in paragraphs (A) and (B) to make the transfer stop request invalid.
Set the SP bit of DMA channel status registers (DCSR0 to DCSR15) of the corresponding channel to "0".
Set the CE bit of DMA channel control registers (DCCR0 to DCCR15) to "1".
Issue a new transfer request.
Table 5-6 Settings to Restart the Suspended Data Transfer
DME clear
Setting to
restart
transfer
(1) Set the DME bit
CE clear
(1) Set the CE bit
(2) Issue a transfer
request
If a transfer stop request from transfer
request source peripheral is detected
(1) The transfer request is negated
(2) The SP bit is cleared
(3) The CE bit is set
(4) Issue a transfer request
Transfer termination
Data transfer can terminate normally or abnormally.
Normal termination
The transfer terminates normally at the time when the transfers for the number of times set by the transfer count
(DTCRx.DTC) end. When terminated normally, the DCSRx.NC bit of the corresponding channel is set. Also, the
DCCRx.CE bit is cleared and data transfer is stopped. However, if the reloading of the transfer count has been set
by non-software transfer request source, the DCCRx.CE bit of the channel is not cleared.
If writing "1" to the corresponding channel's DCCRx.CE bit at the time the transfer count (DTCRx.DTC) is "0",
the DCSRx.NC bit is set in the similar way as for the normal termination. Before setting the DCCRx.CE bit to "1",
be sure to set the DTCRx.DTC bit to "1" or a larger value.
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Abnormal termination
If an inhibited value is set in the register, data transfer terminates abnormally. When terminated abnormally, the
DCSRx.AC bit of the corresponding channel is set. Also, the DCCRx.CE bit is cleared and data transfer is
stopped.
The items not allowed to set to registers are listed below.
Transfer mode
Transfer source address count
Transfer destination address count
Transfer size
Demand transfer mode by software request
: DCCRx.TM = 10
: DCCRx.SAC = 10
: DCCRx.DAC = 10
: DCCRx.TS = 11
: DCCRx.RS = 00 and DCCRx.TM = 11
Interrupt request
The DMAC can issue an interrupt request at normal termination of data transfer, at abnormal termination of data
transfer, or at transfer suspension by a transfer stop request. When issuing an interrupt request, set the interrupt
controller as well.
Use the DMA channel status register (DCSRx) to check the interrupt request factor or to clear the interrupt request.
Interrupt request at normal termination
If the normal termination interrupt of a channel is enabled (DCCRx.NIE=1), the DMAC issues the interrupt
request at the normal termination.
However, the DCSRx.NC bit of the corresponding channel must be set regardless of the normal termination
interrupt setting (DCCRx.NIE).
Clear the interrupt request by clearing the DCSRx.NC bit of the corresponding channel.
Interrupt request at abnormal termination
If the abnormal termination interrupt of a channel is enabled (DCCRx.AIE=1), the DMAC issues the interrupt
request at the abnormal termination. However, the DCSRx.AC bit of the corresponding channel is set regardless
of the abnormal termination interrupt (DCCRx.AIE) setting.
Clear the interrupt request by clearing the DCSRx.AC bit of the corresponding channel.
A transfer suspension interrupt request by a transfer stop request
If the transfer suspension interrupt of a channel is enabled (DCCRx.AIE=1), the DMAC issues the interrupt
request if data transfer is suspended by a transfer stop request. However, the DCSRx.SP bit of the corresponding
channel is set regardless of the transfer suspension interrupt (DCCRx.SIE) settings.
Clear the interrupt request by clearing the DCSRx.SP bit of the corresponding channel.
DMA transfer suppressing
The DMA transfer is suppressed due to the following causes.
A DMA transfer suppress request from DSU/OCD (for debugging)
NMI
Peripheral interrupt
The DMA transfer is suppressed in units of blocks. If data transfer is suppressed, new data transfer does not start.
Data transfer is stopped. The settings to restart data transfer vary depending on the DMA transfer suppress causes.
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DMA transfer suppressing request from DSU/OCD (for debugging)
When the DMA transfer suppressing request by DSU/OCD is asserted, a new transfer does not start and a current
transfer stops with the block unit. The acknowledge is not returned to the DMA transfer suppressing from
DSU/OCD.
DMA transfer suppressing by NMI
If the NMIHD bit is set to "0", DMAC sets NMIH flag when user NMI occurs and suppresses DMA transfer after
the current block has been transferred.
Write "0" in the NMIH flag when you restart transfer.
DMA transfer suppressing by peripheral interrupt
If an interrupt having the level higher than the one specified in the DILVR register occurs, the DMA transfer is
suppressed after the current block has been transferred.
When the interrupt request is cleared and the interrupt level drops to LVL[4:0] or lower level, the DMA transfer
restarts.
Table 5-7 LVL[4:0] Settings to Suppress DMA Transfer
LVL[4:0]
DMA suppress control
11111
Suppresses the DMA transfer when any peripheral interrupt request is issued. (initial value)
11110
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 1EH is issued.
11101
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 1DH is issued.
11100
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 1CH is issued.
11011
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 1BH is issued.
11010
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 1AH is issued.
11001
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 19H is issued.
11000
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 18H is issued.
10111
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 17H is issued.
10110
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 16H is issued.
10101
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 15H is issued.
10100
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 14H is issued.
10011
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 13H is issued.
10010
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 12H is issued.
10001
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 11H is issued.
10000
Does not suppress the DMA transfer when a peripheral interrupt request is issued.
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Chapter 9: DMA Controller (DMAC)
5.2.
Table for On-chip Bus IPs and Corresponding DMAC
Channels
The following on-chip bus IP is assigned to each DMAC channel.
Channel
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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On-chip Bus IP
Transfer request caused by FlexRay output buffer busy (CIF1.DREQO)
Transfer request caused by FlexRay input buffer host busy (CIF1.DREQI)
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
No corresponding on-chip bus IP
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Chapter 9: DMA Controller (DMAC)
6. DMA Usage Examples
This section explains DMA controller (DMAC) DMA usage examples.
The following gives an example of memcpy instruction in every 64-byte data using the DMA. This is the simplest
DMA transfer example.
Figure 6-1 Memcpy Example Using the DMA (ch.3 is used)
・
・
・
Configure DMA
・
・
Configure DMA transfer settings from software. (DCCR3)
Burst transfer; Transfer size: Word; Block size: 16 times
Configure the DMA transfer source address. (DSAR3)
Configure the DMA transfer destination address. (DSAR3)
(DDAR3)
Configure the number of transfers. (DTCR3)
Number of transfers: Amount of data to transfer (in bytes)/64
Permit and issue DMA request from software.
(DMACR, DCCR3)
Issue interrupt
request
・ The progress can be checked by reading the DSAR3, DDAR3, DTCR3
registers.
・ Transfer complete can be checked by reading the DCSR3 register.
Wait for DMA
to finish
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Chapter 9: DMA Controller (DMAC)
This is a communication example via the multi-function serial interface that uses the DMA. In this example, an
interrupt of the multi-function serial interface is occupied by the DMA transfer request. Therefore, the CPU polls the
status registers to check for an error occurrence.
Figure 6-2 Communication Example via the Multi-function Serial Interface That Uses DMA
Multi-function serial interface
CPU
DMAC
FIFO
UART
External device
Settings (DMA transfer conditions)
Settings (protocol, etc.)
Settings (FIFO interrupt conditions)
by interrupt
DMA request
requestby
Data transfer
Data
Data
Check for existence of error
by interrupt
DMA request
requestby
Data transfer
Check for existence of error
Settings (DMA disable)
Settings (communication disable)
Settings (clear each item)
Settings (reset)
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Chapter 10: Generation And Clearing Of DMA Transfer
Requests
This chapter explains the generation and clearing of DMA transfer requests.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : DMAREQ-1v0-91528-3-E
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
1. Overview
This section explains the overview of the generation and clearing of DMA transfer requests.
This product can activate DMA transfer using interrupt requests from peripheral functions. Registers used to select
interrupt requests that activate DMA transfer are provided for each DMA controller (DMAC) channel. If multiple
interrupt requests are assigned to one interrupt vector number, it is also necessary to specify what interrupt request
flag is to be cleared by the DMA controller (DMAC).
DMA controller (DMAC) registers allow DMA transfer request generation factors (transfer request sources) to be set
on interrupt requests from peripheral functions. The interrupt requests to be used can be selected by specifying the
value corresponding to the interrupt vector number.
2. Features
This section explains features of the generation and clearing of DMA transfer requests.
2.1. Transfer Request Generation Setting
2.2. Interrupt Clearing Setting
2.1.
Transfer Request Generation Setting
The transfer request generation setting is shown.
For each 16-channel DMA transfer request, you need to specify what interrupt from interrupt vector numbers 0x10
(16 in decimal notation) to 0x3F (63 in decimal notation) is used to generate the DMA transfer request.
2.2.
Interrupt Clearing Setting
The interrupt clearing setting is shown.
After the DMA transfer ends, the interrupt source peripheral that has issued the interrupt request to be cleared is
identified if the transfer request source is a vector number to which multiple interrupt source peripherals belong.
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3. Configuration
This section explains the configuration of the generation and clearing of DMA transfer requests.
DMAC ch.0 to ch.15
transfer requests
IOE
Interrupt clearing requests
to each peripherals
IORR
DMAC transfer completion
ch.0 to ch.15
ch.15
IOS
ch.1
ch.0
Interrupt requests
vector number 16 to 63
Figure 3-1 Block Diagram
Reverse the interrupt vector
number of which DMA
transfer completed.
Reverse peripheral
ICSEL
4. Registers
This section explains registers of the generation and clearing of DMA transfer requests.
Table 4-1 Registers Map
Registers
Address
+0
+1
+2
0x0400
0x0404
ICSEL0
ICSEL4
ICSEL1
ICSEL5
+3
Register function
ICSEL2
DMA clear request register 0 (for vector number #16)
DMA clear request register 1 (for vector number #17)
ICSEL3
DMA clear request register 2 (for vector number #18)
DMA clear request register 3 (for vector number #19)
ICSEL6
DMA clear request register 4 (for vector number #38)
DMA clear request register 5 (for vector number #39)
ICSEL7
DMA clear request register 6 (for vector number #40)
DMA clear request register 7 (for vector number #41)
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Address
0x0408
Registers
+0
+1
+2
+3
Register function
DMA clear request register 8 (for vector number #42)
DMA clear request register 9 (for vector number #43)
ICSEL10 ICSEL11
DMA clear request register 10 (for vector number #44)
DMA clear request register 11 (for vector number #46)
ICSEL8
ICSEL9
ICSEL12
DMA clear request register 12 (for vector number #47)
DMA clear request register 13 (for vector number #52)
ICSEL13 ICSEL14 ICSEL15
DMA clear request register 14 (for vector number #53)
DMA clear request register 15 (for vector number #54)
ICSEL16
DMA clear request register 16 (for vector number #55)
DMA clear request register 17 (for vector number #56)
ICSEL17 ICSEL18 ICSEL19
DMA clear request register 18 (for vector number #57)
DMA clear request register 19 (for vector number #58)
ICSEL20
DMA clear request register 20 (for vector number #59)
DMA clear request register 21 (for vector number #60)
ICSEL21 ICSEL22 ICSEL23
DMA clear request register 22 (for vector number #61)
DMA clear request register 23 (for vector number #45)
ICSEL24
DMA clear request register 24 (for vector number #49)
DMA clear request register 25 (for vector number #48)
ICSEL25 ICSEL26 ICSEL27
DMA clear request register 26 (for vector number #50)
DMA clear request register 27 (for vector number #51)
0x04D8
ICSEL28
DMA clear request register 28 (for vector number #28)
DMA clear request register 29 (for vector number #29)
ICSEL29 ICSEL30 ICSEL31
DMA clear request register 30 (for vector number #30)
DMA clear request register 31 (for vector number #31)
0x04DC
ICSEL32
ICSEL33
0x040C
0x0410
0x0414
0x0438
0x0490
0x0494
0x0498
0x049C
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IORR0
IORR4
IORR8
IORR12
IORR1
IORR5
IORR9
IORR13
Reserved Reserved
DMA clear request register 32 (for vector number #32)
DMA clear request register 33 (for vector number #33)
IORR3
IO transfer request register 0
IO transfer request register 1
IO transfer request register 2
IO transfer request register 3
IORR6
IORR7
IO transfer request register 4
IO transfer request register 5
IO transfer request register 6
IO transfer request register 7
IORR10
IO transfer request register 8
IO transfer request register 9
IORR11
IO transfer request register 10
IO transfer request register 11
IORR14
IO transfer request register 12
IO transfer request register 13
IORR15
IO transfer request register 14
IO transfer request register 15
IORR2
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
4.1.
DMA Request Clear Register 0 : ICSEL0 (Interrupt Clear
SELect register 0)
The bit configuration of DMA request clear register 0 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#16).
ICSEL0 : Address 0400H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
bit1
bit0
EISEL[2:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] EISEL[2:0] (External Interrupt request SELection) : Interrupt clear selection bits for external
interrupts 0 to 7
EISEL[2:0]
Clear target
000
External interrupt 0
001
External interrupt 1
010
External interrupt 2
011
External interrupt 3
100
External interrupt 4
101
External interrupt 5
110
External interrupt 6
111
External interrupt 7
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4.2.
DMA Request Clear Register 1 : ICSEL1 (Interrupt Clear
SELect register 1)
The bit configuration of DMA request clear register 1 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#17).
ICSEL1: Address 0401H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
0
Attribute R0,WX
bit2
bit1
bit0
EISEL[3:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit3 to bit0] EISEL[3:0] (External Interrupt request SELection) : Interrupt clear selection bits for external
interrupts 8 to 23
356
EISEL[3:0]
Clear target
0000
External interrupt 8
0001
External interrupt 9
0010
External interrupt 10
0011
External interrupt 11
0100
External interrupt 12
0101
External interrupt 13
0110
External interrupt 14
0111
External interrupt 15
1000
External interrupt 16
1001
External interrupt 17
1010
External interrupt 18
1011
External interrupt 19
1100
External interrupt 20
1101
External interrupt 21
1110
External interrupt 22
1111
External interrupt 23
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
4.3.
DMA Request Clear Register 2 : ICSEL2 (Interrupt Clear
SELect register 2)
The bit configuration of DMA request clear register 2 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #18).
ICSEL2: Address 0402H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
Attribute R0,WX
bit0
RTSEL0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] RTSEL0 (Reload Timer SELection) : Interrupt clear selection bit for reload timer 0/1
4.4.
RTSEL0
Clear target
0
Reload timer 0
1
Reload timer 1
DMA Request Clear Register 3 : ICSEL3 (Interrupt Clear
SELect register 3)
The bit configuration of DMA request clear register 3 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #19).
ICSEL3: Address 0403H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
Attribute R0,WX
bit0
RTSEL1
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] RTSEL1 (Reload Timer SELection) : Interrupt clear selection bit for reload timer 2/3
RTSEL1
Clear target
0
Reload timer 2
1
Reload timer 3
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4.5.
DMA Request Clear Register 4: ICSEL4 (Interrupt Clear
SELect register 4)
The bit configuration of DMA request clear register 4 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #38).
ICSEL4: Address 0404H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
Attribute R0,WX
bit0
RXSEL1
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] RXSEL1 (RX SELection): Interrupt clear selection bit for multi-function serial ch.7 and ch.15 reception
completion
RXSEL1
358
Clear target
0
Multi-function serial ch.7 reception completion
1
Multi-function serial ch.15 reception completion
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4.6.
DMA Request Clear Register 5 : ICSEL5 (Interrupt Clear
SELect register 5)
The bit configuration of DMA request clear register 5 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#39).
ICSEL5: Address 0405H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
SG_RX_SEL1[2:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] SG_RX_SEL1[2:0] (SG_RX SELection1) : Interrupt clear selection bits for 16-bit free-run timer 0
zero detection, compare clear, multi-function serial ch.7 and ch.15 transmission completion
SG_RX_SEL1[2:0]
Clear target
000
Reserved (Does not clear any interrupt)
001
Reserved (Does not clear any interrupt)
010
16-bit free-run timer 0 zero detection
011
16-bit free-run timer 0 compare clear
100
Multi-function serial ch.7 transmission completion
101
Multi-function serial ch.15 transmission completion
110 to 111
Reserved (Does not clear any interrupt)
Note:
Setting SG_RX_SEL1[2:0]= "000", "001" and "110" to "111" are prohibited. During this setting, no interrupt clear
will be selected.
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4.7.
DMA Request Clear Register 6 : ICSEL6 (Interrupt Clear
SELect register 6)
The bit configuration of DMA request clear register 6 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#40).
ICSEL6: Address 0406H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
PPGSEL0[3:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit3 to bit0] PPGSEL0[3:0] (PPG SELection0) : Interrupt clear selection bits for PPG0, 1, 10, 11, 20, 21, 16-bit
free-run timer 1 zero detection, compare clear
PPGSEL0[3:0]
Clear target
0000
PPG0
0001
PPG1
0010
PPG10
0011
PPG11
0100
PPG20
0101
PPG21
0110
Reserved (Does not clear any interrupt)
0111
Reserved (Does not clear any interrupt)
1000
16-bit free-run timer 1 zero detection
1001
16-bit free-run timer 1 compare clear
1010 to 1111
Reserved (Does not clear any interrupt)
Note:
Setting PPGSEL0[3:0]= "0110", "0111" and "1010" to "1111" are prohibited. During this setting, no interrupt clear
will be selected.
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4.8.
DMA Request Clear Register 7 : ICSEL7 (Interrupt Clear
SELect register 7)
The bit configuration of DMA request clear register 7 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#41).
ICSEL7: Address 0407H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
PPGSEL1[3:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit3 to bit0] PPGSEL1[3:0] (PPG SELection1) : Interrupt clear selection bits for PPG2, 3, 12, 13, 22, 23, 16-bit
free-run timer 2 zero detect, compare clear
PPGSEL1[3:0]
Clear target
0000
PPG2
0001
PPG3
0010
PPG12
0011
PPG13
0100
PPG22
0101
PPG23
0110
Reserved (Does not clear any interrupt)
0111
Reserved (Does not clear any interrupt)
1000
16-bit free-run timer 2 zero detection
1001
16-bit free-run timer 2 compare clear
1010 to 1111
Reserved (Does not clear any interrupt)
Note:
Setting PPGSEL1[3:0]= "0110", "0111" and "1010" to "1111" are prohibited. During this setting, no interrupt clear
will be selected.
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4.9.
DMA Request Clear Register 8 : ICSEL8 (Interrupt Clear
SELect register 8)
The bit configuration of DMA request clear register 8 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#42).
ICSEL8: Address 0408H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
bit1
bit0
PPGSEL2[1:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] PPGSEL2[1:0] (PPG SELection2) : Interrupt clear selection bits for PPG4, 5, 14, 15
PPGSEL2[1:0]
Clear target
00
PPG4
01
PPG5
10
PPG14
11
PPG15
4.10. DMA Request Clear Register 9 : ICSEL9 (Interrupt Clear
SELect register 9)
The bit configuration of DMA request clear register 9 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#43).
ICSEL9: Address 0409H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
362
bit1
bit0
PPGSEL3[1:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
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[bit1, bit0] PPGSEL3[1:0] (PPG SELection3) : Interrupt clear selection bits for PPG6, 7, 16, 17
PPGSEL3[1:0]
Clear target
00
PPG6
01
PPG7
10
PPG16
11
PPG17
4.11. DMA Request Clear Register 10 : ICSEL10 (Interrupt Clear
SELect register 10)
The bit configuration of DMA request clear register 10 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#44).
ICSEL10: Address 040AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
bit1
bit0
PPGSEL4[1:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] PPGSEL4[1:0] (PPG SELection4) : Interrupt clear selection bits for PPG8, 9, 18, 19
PPGSEL4[1:0]
Clear target
00
PPG8
01
PPG9
10
PPG18
11
PPG19
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4.12. DMA Request Clear Register 11 : ICSEL11 (Interrupt Clear
SELect register 11)
The bit configuration of DMA request clear register 11 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#46).
ICSEL11: Address 040BH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
PMSTSEL[2:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] PMSTSEL[2:0] (PLL, Main, Sub Timer SELection) : Interrupt clear selection for main timer / sub
timer / PLL timer, multi-function serial ch.8 and ch.16 transmission completion, 16-bit ICU2, ICU3
PMSTSEL[2:0]
Clear target
000
Main timer
001
Sub timer
010
PLL timer
011
Multi-function serial ch.8 transmission completion
100
16-bit ICU2
101
16-bit ICU3
110
Multi-function serial ch.16 transmission completion
111
Reserved (Does not clear any interrupt)
Note:
Setting PMSTSEL[2:0]= "111" is prohibited. During this setting, no interrupt clear will be selected.
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4.13. DMA Request Clear Register 12: ICSEL12 (Interrupt Clear
SELect register 12)
The bit configuration of DMA request clear register 12 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #47).
ICSEL12: Address 040CH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reseved
Initial value
0
0
0
bit0
RXSEL0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
0
0
R0,WX
R/W
[bit0] RXSEL0: Interrupt clear selection for multi-function serial ch.9 and ch.17 reception completion
RXSEL0
Clear target
0
Multi-function serial ch.9 reception completion
1
Multi-function serial ch.17 reception completion
4.14. DMA Request Clear Register 13 : ICSEL13 (Interrupt Clear
SELect register 13)
The bit configuration of DMA request clear register 13 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#52).
ICSEL13: Address 040DH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
ICUSEL0[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] ICUSEL0[1:0] : Interrupt clear selection for ICU ch.6, multi-function serial ch.10 and ch.18 reception
completion
ICUSEL0[1:0]
00
Clear target
Reserved (Does not clear any interrupt)
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ICUSEL0[1:0]
Clear target
01
32-bit ICU ch.6
10
Multi-function serial ch.10 reception completion
11
Multi-function serial ch.18 reception completion
Note:
Setting ICUSEL0[1:0]= "00" is prohibited. During this setting, no interrupt clear will be selected.
4.15. DMA Request Clear Register 14 : ICSEL14 (Interrupt Clear
SELect register 14)
The bit configuration of DMA request clear register 14 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#53).
ICSEL14: Address 040EH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
ICUSEL1[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] ICUSEL1[1:0] : Interrupt clear selection for ICU ch.7, multi-function serial ch.10 and ch.18
transmission completion
ICUSEL1[1:0]
Clear target
00
Reserved (Does not clear any interrupt)
01
32-bit ICU ch.7
10
Multi-function serial ch.10 transmission completion
11
Multi-function serial ch.18 transmission completion
Note:
Setting ICUSEL1[1:0]= "00" is prohibited. During this setting, no interrupt clear will be selected.
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4.16. DMA Request Clear Register 15 : ICSEL15 (Interrupt Clear
SELect register 15)
The bit configuration of DMA request clear register 15 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#54).
ICSEL15: Address 040FH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
ICUSEL2[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] ICUSEL2[1:0] : Interrupt clear selection for ICU ch.8, multi-function serial ch.11 and ch.19 reception
completion
ICUSEL2[1:0]
Clear target
00
Reserved (Does not clear any interrupt)
01
32-bit ICU ch.8
10
Multi-function serial ch.11 reception completion
11
Multi-function serial ch.19 reception completion
Note:
Setting ICUSEL2[1:0]= "00" is prohibited. During this setting, no interrupt clear will be selected.
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4.17. DMA Request Clear Register 16 : ICSEL16 (Interrupt Clear
SELect register 16)
The bit configuration of DMA request clear register 16 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#55).
ICSEL16: Address 0410H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
ICUSEL3[3:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R,W
R,W
R,W
R/W
[bit3 to bit0] ICUSEL3[3:0] : Interrupt clear selection for ICU ch.9, WG dead timer underflow 0, 1, 2, WG dead
timer reload 0, 1, 2, WG DTTI0
ICUSEL3[3:0]
Clear target
0000
Reserved (Does not clear any interrupt)
0001
32-bit ICU ch.9
0010
WG dead timer underflow 0
0011
WG dead timer underflow 1
0100
WG dead timer underflow 2
0101
WG dead timer reload 0
0110
WG dead timer reload 1
0111
WG dead timer reload 2
1000
WG DTTI0
1001 to 1111
Reserved (Does not clear any interrupt)
Note:
Setting ICUSEL3[3:0]= "0000" and "1001" to "1111" are prohibited. During this setting, no interrupt clear will be
selected.
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4.18. DMA Request Clear Register 17 : ICSEL17 (Interrupt Clear
SELect register 17)
The bit configuration of DMA request clear register 17 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#56).
ICSEL17: Address 0411H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
ICUSEL4[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] ICUSEL4[1:0] : Interrupt clear selection for ICU ch.4 and ch.10, multi-function serial ch.11 and ch.19
transmission completion
ICUSEL4[1:0]
Clear target
00
32-bit ICU ch.4
01
32-bit ICU ch.10
10
Multi-function serial ch.11 transmission completion
11
Multi-function serial ch.19 transmission completion
4.19. DMA Request Clear Register 18 : ICSEL18 (Interrupt Clear
SELect register 18)
The bit configuration of DMA request clear register 18 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#57).
ICSEL18: Address 0412H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
bit2
bit1
bit0
ICUSEL5[5:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
[bit5 to bit0] ICUSEL5[5:0] : Interrupt clear selection for ICU ch.5 and ch.11, A/D converter ch.32 to ch.63
ICUSEL5[5:0]
000000
Clear target
32-bit ICU ch.5
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ICUSEL5[5:0]
000001
32-bit ICU ch.11
000010
A/D converter ch.32
000011
A/D converter ch.33
000100
A/D converter ch.34
000101
A/D converter ch.35
000110
A/D converter ch.36
000111
A/D converter ch.37
001000
A/D converter ch.38
001001
A/D converter ch.39
001010
A/D converter ch.40
001011
A/D converter ch.41
001100
A/D converter ch.42
001101
A/D converter ch.43
001110
A/D converter ch.44
001111
A/D converter ch.45
010000
A/D converter ch.46
010001
A/D converter ch.47
010010
A/D converter ch.48
010011
A/D converter ch.49
010100
A/D converter ch.50
010101
A/D converter ch.51
010110
A/D converter ch.52
010111
A/D converter ch.53
011000
A/D converter ch.54
011001
A/D converter ch.55
011010
A/D converter ch.56
011011
A/D converter ch.57
011100
A/D converter ch.58
011101
A/D converter ch.59
011110
A/D converter ch.60
011111
A/D converter ch.61
100000
A/D converter ch.62
100001
A/D converter ch.63
100010 to 111111
370
Clear target
Reserved (Does not clear any interrupt)
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
Note:
Setting ICUSEL5[5:0]= "100010" to "111111" are prohibited. During this setting, no interrupt clear will be selected.
4.20. DMA Request Clear Register 19 : ICSEL19 (Interrupt Clear
SELect register 19)
The bit configuration of DMA request clear register 19 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#58).
ICSEL19: Address 0413H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
bit1
bit0
OCUSEL0[2:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] OCUSEL0[2:0] (OCU Selection0) : Interrupt clear selection bits for OCU6, 7, 10, 11
OCUSEL0[2:0]
Clear target
000
Reserved (Does not clear any interrupt)
001
Reserved (Does not clear any interrupt)
010
32-bit OCU6
011
32-bit OCU7
100
32-bit OCU10
101
32-bit OCU11
110
Reserved (Does not clear any interrupt)
111
Reserved (Does not clear any interrupt)
Note:
Setting OCUSEL0[2:0]= "000 to 001" and "110" to "111" are prohibited. During this setting, no interrupt clear will be
selected.
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4.21. DMA Request Clear Register 20 : ICSEL20 (Interrupt Clear
SELect register 20)
The bit configuration of DMA request clear register 20 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#59).
ICSEL20: Address 0414H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
bit1
bit0
OCUSEL1[2:0]
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] OCUSEL1[2:0] (OCU Selection1) : Interrupt clear selection bits for OCU8, 9, 12, and 13
OCUSEL1[2:0]
Clear target
000
Reserved (Does not clear any interrupt)
001
Reserved (Does not clear any interrupt)
010
Reserved (Does not clear any interrupt)
011
Reserved (Does not clear any interrupt)
100
32-bit OCU8
101
32-bit OCU9
110
32-bit OCU12
111
32-bit OCU13
Note:
Setting OCUSEL1[2:0]= "000" to "011" are prohibited. During this setting, no interrupt clear will be selected.
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4.22. DMA Request Clear Register 21 : ICSEL21 (Interrupt Clear
SELect register 21)
The bit configuration of DMA request clear register 21 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#60).
ICSEL21: Address 0415H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
BT_SG_SEL0[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] BT_SG_SEL0[1:0] (BT_SG Selection0) : Interrupt clear selection bits for Base Timer0 IRQ0, IRQ1
BT_SG_SEL0[1:0]
Clear target
00
Base Timer0 IRQ0
01
Base Timer0 IRQ1
10
Reserved (Does not clear any interrupt)
11
Reserved (Does not clear any interrupt)
Note:
Setting BT_SG_SEL0[1:0]= "10" and "11" are prohibited. During this setting, no interrupt clear will be selected.
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4.23. DMA Request Clear Register 22 : ICSEL22 (Interrupt Clear
SELect register 22)
The bit configuration of DMA request clear register 22 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#61).
ICSEL22: Address 0416H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
BT_SG_SEL1[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] BT_SG_SEL [1:0] (BT_SG_Selection1) : Interrupt clear selection bits for Base Timer1 IRQ0, IRQ1
BT_SG_SEL1[1:0]
Clear target
00
Base Timer1 IRQ0
01
Base Timer1 IRQ1
10
Reserved (Does not clear any interrupt)
11
Reserved (Does not clear any interrupt)
Note:
Setting BT_SG_SEL1[1:0]= "10" and "11" are prohibited. During this setting, no interrupt clear will be selected.
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4.24. DMA Request Clear Register 23 : ICSEL23 (Interrupt Clear
SELect register 23)
The bit configuration of DMA request clear register 23 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#45).
ICSEL23: Address 0417H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
MFS_SEL0[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] MFS_SEL0[1:0] (MFS_Selection) : Interrupt clear selection bits for MFS ch.8 and ch.16 (reception
completion) / ICU0 / ICU1
MFS_SEL0[1:0]
Clear target
00
Multi-function serial ch.8 reception completion
01
16-bit ICU0
10
16-bit ICU1
11
Multi-function serial ch.16 reception completion
4.25. DMA Request Clear Register 24 : ICSEL24 (Interrupt Clear
SELect register 24)
The bit configuration of DMA request clear register 24 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#49).
ICSEL24: Address 0438H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
MFS_SEL1[1:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] MFS_SEL1[1:0] (MFS_Selection1) : Interrupt clear selection bits for MFS ch.9 and ch.17
(transmission completion) / OCU0 / OCU1
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
MFS_SEL1[1:0]
Clear target
00
Multi-function serial ch.9 transmission completion
01
16-bit OCU0
10
16-bit OCU1
11
Multi-function serial ch.17 transmission completion
4.26. DMA Request Clear Register 25 : ICSEL25 (Interrupt Clear
SELect register 25)
The bit configuration of DMA request clear register 25 is shown below.
These bits select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number
#48).
ICSEL25: Address 0439H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
AD_SEL[4:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit4 to bit0] AD_SEL[4:0] (AD_Selection) : Interrupt clear selection bits for ADC ch.0 to ch.31
376
AD_SEL[4:0]
Clear target
00000
A/D converter ch.0
00001
A/D converter ch.1
00010
A/D converter ch.2
00011
A/D converter ch.3
00100
A/D converter ch.4
00101
A/D converter ch.5
00110
A/D converter ch.6
00111
A/D converter ch.7
01000
A/D converter ch.8
01001
A/D converter ch.9
01010
A/D converter ch.10
01011
A/D converter ch.11
01100
A/D converter ch.12
01101
A/D converter ch.13
01110
A/D converter ch.14
01111
A/D converter ch.15
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
AD_SEL[4:0]
Clear target
10000
A/D converter ch.16
10001
A/D converter ch.17
10010
A/D converter ch.18
10011
A/D converter ch.19
10100
A/D converter ch.20
10101
A/D converter ch.21
10110
A/D converter ch.22
10111
A/D converter ch.23
11000
A/D converter ch.24
11001
A/D converter ch.25
11010
A/D converter ch.26
11011
A/D converter ch.27
11100
A/D converter ch.28
11101
A/D converter ch.29
11110
A/D converter ch.30
11111
A/D converter ch.31
4.27. DMA Request Clear Register 26 : ICSEL26 (Interrupt Clear
SELect register 26)
The bit configuration of DMA request clear register 26 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #50).
ICSEL26: Address 043AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
Attribute R0,WX
bit0
OCU_SEL2
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] OCU_SEL2 (OCU_Selection2) : Interrupt clear selection bit for OCU2 / OCU3
OCU_SEL2
Clear target
0
16-bit OCU2
1
16-bit OCU3
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
4.28. DMA Request Clear Register 27 : ICSEL27 (Interrupt Clear
SELect register 27)
The bit configuration of DMA request clear register 27 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #51).
ICSEL27: Address 043BH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Initial value
0
Attribute R0,WX
OCU_SEL3
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] OCU_SEL3 (OCU_Selection3) : Interrupt clear selection bit for OCU4 / OCU5
OCU_SEL3
Clear target
0
16-bit OCU4
1
16-bit OCU5
4.29. DMA Request Clear Register 28: ICSEL28 (Interrupt Clear
SELect register 28)
The bit configuration of DMA request clear register 28 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #28).
ICSEL28: Address 04D8H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
0
Attribute R0,WX R0,WX
bit0
MFS_SEL2
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] MFS_SEL2 (MFS_Selection2): MFS4/MFS12 interrupt clear selection bit
MFS_SEL2
378
Clear target
0
Multi-function serial ch.4 reception completion
1
Multi-function serial ch.12 reception completion
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
4.30. DMA Request Clear Register 29: ICSEL29 (Interrupt Clear
SELect register 29)
The bit configuration of DMA request clear register 29 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #29).
ICSEL29: Address 04D9H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
0
Attribute R0,WX R0,WX
bit0
MFS_SEL3
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] MFS_SEL3 (MFS_Selection3): MFS4/MFS12 interrupt clear selection bit
MFS_SEL3
Clear target
0
Multi-function serial ch.4 transmission completion
1
Multi-function serial ch.12 transmission completion
4.31. DMA Request Clear Register 30: ICSEL30 (Interrupt Clear
SELect register 30)
The bit configuration of DMA request clear register 30 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #30).
ICSEL30: Address 04DAH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
0
Attribute R0,WX R0,WX
bit0
MFS_SEL4
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] MFS_SEL4 (MFS_Selection4): MFS5/MFS13 interrupt clear selection bit
MFS_SEL4
Clear target
0
Multi-function serial ch.5 reception completion
1
Multi-function serial ch.13 reception completion
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
4.32. DMA Request Clear Register 31: ICSEL31 (Interrupt Clear
SELect register 31)
The bit configuration of DMA request clear register 31 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #31).
ICSEL31: Address 04DBH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
0
Attribute R0,WX R0,WX
bit0
MFS_SEL5
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] MFS_SEL5 (MFS_Selection5) : MFS5/MFS13 interrupt clear selection bit
MFS_SEL5
Clear target
0
Multi-function serial ch.5 transmission completion
1
Multi-function serial ch.13 transmission completion
4.33. DMA Request Clear Register 32: ICSEL32 (Interrupt Clear
SELect register 32)
The bit configuration of DMA request clear register 32 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #32).
ICSEL32: Address 04DCH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
0
Attribute R0,WX R0,WX
bit0
MFS_SEL6
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] MFS_SEL6 (MFS_Selection6): MFS6/MFS14 interrupt clear selection bit
MFS_SEL6
380
Clear target
0
Multi-function serial ch.6 reception completion
1
Multi-function serial ch.14 reception completion
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
4.34. DMA Request Clear Register 33: ICSEL33 (Interrupt Clear
SELect register 33)
The bit configuration of DMA request clear register 33 is shown below.
This bit selects the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #33).
ICSEL33: Address 04DDH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
0
0
Attribute R0,WX R0,WX
bit0
MFS_SEL7
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit0] MFS_SEL7 (MFS_Selection7): MFS6/MFS14 interrupt clear selection bit
MFS_SEL7
Clear target
0
Multi-function serial ch.6 transmission completion
1
Multi-function serial ch.14 transmission completion
4.35. IO Transfer Request Setting Register 0 to 15 : IORR0 to 15
(IO triggered DMA Request Register for ch.0 to 15)
The bit configuration of IO transfer request setting register 0 to 15 is shown below.
If the DMA transfer request generation factor is specified as a peripheral interrupt request, these registers identify the
vector number of the interrupt request that has generated the DMA transfer request.
An instance of these registers is provided for each DMA controller (DMAC) channel.
IORR0 to 15: Address 0490H to 049FH (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
Reserved
IOE
0
0
0
0
0
R0,W0
R/W
R/W
R/W
R/W
bit2
bit1
bit0
0
0
0
R/W
R/W
R/W
IOS[5:0]
[bit6] IOE (IO Enabled) : Transfer request enable bit
When an interrupt request specified by the IOS5 to IOS0 bits has been generated, this bit is used to notify the DMA
controller (DMAC) for the pertinent channel whether to output the DMA transfer request.
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
IOE
Function
0
No DMA transfer request output -- The interrupt request generated by the
peripheral is not used as a DMA transfer request (Initial value).
1
DMA transfer request output
[bit5 to bit0] IOS[5:0] (IO triggered DMA transfer request Select) : Transfer request selection bits
These registers are used to identify the interrupt request of the vector number that is used as the transfer request
source by the DMA controller (DMAC) for the channel corresponding to these registers.
IOS[5:0]
Interrupt vector number (Hexadecimal)
000000
0x10 (Initial value)
000001
0x11
000010
0x12
000011
0x13
000100
0x14
000101
0x15
:
:
101100
0x3C
101101
0x3D
101110
0x3E
101111
0x3F
11xxxx
Reserved
Note:
You cannot configure setting that causes interrupt requests with the same interrupt vector number to be transfer
requests from multiple DMA channels (example: simultaneous setting of IORR0 = 0x42 and IORR1 = 0x42).
382
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Chapter 10: Generation And Clearing Of DMA Transfer Requests
5. Operation
This section explains the operation of the generation and clearing of DMA transfer requests.
5.1. Configuration
5.2. Notes
5.1.
Configuration
The configuration of the operation is shown.
The operating sequence is as follows:
1.
2.
3.
4.
5.2.
On the IORR, set the interrupt vector number of the transfer request source peripheral and the IOE bit.
Set ICSEL if multiple peripherals are assigned to the vector number selected in step 1.
Set the interrupt configuration-related registers for the peripheral.
Configure the DMAC.
Notes
The notes are shown.
Do not change the IORR and ICSEL registers when the DMAC enables DMA transfer requests issued by
peripherals.
Peripherals to which resource numbers (RN) are not assigned (see "APPENDIX") cannot use the feature for
clearing interrupts after the completion of DMA transfer. It should therefore be noted that once such a peripheral
has requested DMA transfer, the interrupt will not be cleared after the completion of the requested DMA transfer.
Interrupt requests used as transfer requests are considered as interrupt requests addressed to the CPU. Therefore,
configure the interrupt controller to disable interrupts. (ICR register)
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383
Chapter 11: FixedVector Function
This chapter explains the FixedVector function.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Notes
Code : FR81SFVEC-1v1-91528-2-E
384
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 11: FixedVector Function
1. Overview
This section explains the overview of the FixedVector function.
The FixedVector function is a function for returning the start address of flash memory + 0x0024 instead of the content
of flash memory at the address (0xF_FFFC) corresponding to the interrupt vector on reset.
2. Features
This section explains the features of the FixedVector function.
Interrupt vector on reset returned by the FixedVector function
MB91F527
0x0007_0024
MB91F528
0x0007_0024
3. Configuration
This section explains the configuration of the FixedVector function.
See "Figure 3-3" in "CHAPTER: FLASH MEMORY" for the configuration diagram.
4. Registers
This section explains the registers of the FixedVector function.
None.
5. Operation
This section explains the operation of the FixedVector function.
5.1. Operation After Reset Released
5.2. Usage
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385
Chapter 11: FixedVector Function
5.1.
Operation After Reset Released
The operation after reset released is shown below.
In the following flow, the start address of flash memory + 0x0024 is returned instead of the content of 0xF_FFFC in
flash memory when the reset is released.
Figure 5-1 Operation Flow after Reset
Reset released
The CPU fetches the reset vector (address 0xF_FFFC).
The flash memory interface returns the start address of
flash memory + 0x0024 instead of the content of flash
memory at address 0xF_FFFC.
Operation is executed from the start address of flash
memory ＋0x0024.
5.2.
Usage
The usage is shown below.
After the reset is released, this series executes from the start address of flash memory + 0x0024 instead of the value
written at address 0x000F_FFFC.
6. Notes
This section explains the notes of the FixedVector function.
During reads from addresses 0x000F_FFFC to 0x000F_FFFF other than reset vector fetch (Example: the call
destination when INT #00H is executed while TBR is its initial value (=0x000F_FC00)), the content of flash memory
at the addresses 0x000F_FFFC to 0x000F_FFFF is returned.
386
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Chapter 12: I/O Ports
This chapter explains the I/O ports.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : IO-1v0-91528-3-E
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387
Chapter 12: I/O Ports
1. Overview
This section explains the overview of the I/O ports.
This section explains the setting for assigning to the external pins (peripherals and external bus) and using external
pins as the I/O port.
2. Features
This section explains features of the I/O ports.
I/O multiplexing
If the I/O of multiple peripherals is assigned to one external pin, one of these peripherals is selected to be used.
I/O relocation
If one pin for one peripheral can serve multiple external pins for I/O, one of these external pins is selected to be used.
PORT function
External pins can be used for general-purpose I/O if they are used for output, their values can be set and if they are
used for input, input values assigned to them can be read.
Figure 2-1 Diagram of I/O Multiplexing, I/O Relocation
I/O multiplexing
I/O relocation
peripheral A
peripheral B
a peripheral
peripheral C
Key code function
This function is for error writing protection. If writing is not executed to the key code register (KEYCDR) according
to the specified method, writing to the target register will become invalid. Also, word access for the target register
cannot be executed. The following are the key code target registers.
388
Data direction register
Port function register
Extended port function register
Port pull-up/down enable register
Port input level selection register
Port input enable register
Analog input control register
DA control register
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Chapter 12: I/O Ports
3. Configuration
This section explains the configuration of the I/O ports.
No configuration diagram is provided.
4. Registers
This section explains registers of the I/O ports.
Address
Registers
+0
+1
+2
+3
0x0000
PDR00
PDR01
PDR02
PDR03
0x0004
PDR04
PDR05
PDR06
PDR07
0x0008
PDR08
PDR09
PDR10
PDR11
0x000C
PDR12
PDR13
PDR14
PDR15
0x0010
PDR20
PDR21
PDR22
PDR23
0x0014
PDR24
PDR25
PDR26
PDR27
0x0018
PDR16
PDR17
PDR18
PDR19
0x001C
PDR28
PDR29
Reserved
Reserved
0x0E00
DDR00
DDR01
DDR02
DDR03
0x0E04
DDR04
DDR05
DDR06
DDR07
0x0E08
DDR08
DDR09
DDR10
DDR11
0x0E0C
DDR12
DDR13
DDR14
DDR15
0x0E10
DDR20
DDR21
DDR22
DDR23
0x0E14
DDR24
DDR25
DDR26
DDR27
0x0E18
DDR16
DDR17
DDR18
DDR19
0x0E1C
DDR28
DDR29
Reserved
Reserved
0x0E20
PFR00
PFR01
PFR02
PFR03
0x0E24
PFR04
PFR05
PFR06
PFR07
0x0E28
PFR08
PFR09
PFR10
PFR11
0x0E2C
PFR12
PFR13
PFR14
PFR15
0x0E30
PFR20
PFR21
PFR22
PFR23
0x0E34
PFR24
PFR25
PFR26
PFR27
0x0E38
PFR16
PFR17
PFR18
PFR19
0x0E3C
PFR28
PFR29
Reserved
Reserved
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Register function
Port data register 00 to 29
Data direction register 00 to 29
(Key code target registers)
Port function register 00 to 29
(Key code target registers)
389
Chapter 12: I/O Ports
Address
Registers
+0
+1
+2
+3
0x0E40
PDDR00
PDDR01
PDDR02
PDDR03
0x0E44
PDDR04
PDDR05
PDDR06
PDDR07
0x0E48
PDDR08
PDDR09
PDDR10
PDDR11
0x0E4C
PDDR12
PDDR13
PDDR14
PDDR15
0x0E50
PDDR20
PDDR21
PDDR22
PDDR23
0x0E54
PDDR24
PDDR25
PDDR26
PDDR27
0x0E58
PDDR16
PDDR17
PDDR18
PDDR19
0x0E5C
PDDR28
PDDR29
Reserved
Reserved
0x0E60
EPFR00
EPFR01
EPFR02
EPFR03
0x0E64
EPFR04
EPFR05
EPFR06
EPFR07
0x0E68
EPFR08
EPFR09
EPFR10
EPFR11
0x0E6C
EPFR12
EPFR13
EPFR14
EPFR15
0x0E70
Reserved
Reserved
Reserved
Reserved
0x0E74
Reserved
Reserved
Reserved
Reserved
0x0E78
Reserved
Reserved
EPFR26
EPFR27
0x0E7C
EPFR28
EPFR29
Reserved
Reserved
0x0E80
Reserved
EPFR33
EPFR34
EPFR35
0x0E84
EPFR36
Reserved
Reserved
Reserved
0x0E88
Reserved
Reserved
EPFR42
EPFR43
0x0E8C
EPFR44
EPFR45
Reserved
Reserved
0x0E90
EPFR48
EPFR49
EPFR50
EPFR51
0x0E94
Reserved
Reserved
Reserved
Reserved
0x0E98
EPFR56
EPFR57
EPFR58
EPFR59
0x0E9C
EPFR60
EPFR61
EPFR62
EPFR63
0x0EA0
Reserved
Reserved
Reserved
Reserved
0x0EA4
Reserved
Reserved
Reserved
Reserved
0x0EA8
Reserved
Reserved
Reserved
Reserved
0x0EAC
Reserved
Reserved
Reserved
Reserved
0x0EB0
Reserved
Reserved
Reserved
Reserved
0x0EB4
Reserved
Reserved
Reserved
Reserved
390
Register function
Input data direct read register 00 to 29
Extended port function register 00 to
63 (Key code target registers)
Reserved
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Chapter 12: I/O Ports
Address
Registers
Register function
+0
+1
+2
+3
0x0EC0
PPER00
PPER01
PPER02
PPER03
0x0EC4
PPER04
PPER05
PPER06
PPER07
0x0EC8
PPER08
PPER09
PPER10
PPER11
0x0ECC
PPER12
PPER13
PPER14
PPER15
0x0ED0
PPER20
PPER21
PPER22
PPER23
0x0ED4
PPER24
PPER25
PPER26
PPER27
0x0ED8
PPER16
PPER17
PPER18
PPER19
0x0EDC
PPER28
PPER29
Reserved
Reserved
0x0EE0
PILR00
PILR01
Reserved
Reserved
0x0EE4
Reserved
PILR05
Reserved
Reserved
0x0EE8
Reserved
Reserved
Reserved
PILR11
0x0EEC
PILR12
Reserved
Reserved
PILR15
0x0EF0
Reserved
Reserved
Reserved
Reserved
0x0EF4
Reserved
Reserved
Reserved
Reserved
0x0EF8
Reserved
Reserved
Reserved
Reserved
0x0EFC
Reserved
Reserved
Reserved
Reserved
0x0F00
Reserved
Reserved
Reserved
Reserved
0x0F04
Reserved
Reserved
Reserved
Reserved
0x0F08
Reserved
Reserved
Reserved
Reserved
0x0F0C
Reserved
Reserved
Reserved
Reserved
0x0F10
Reserved
Reserved
Reserved
Reserved
0x0F14
Reserved
Reserved
Reserved
Reserved
0x0F18
Reserved
Reserved
Reserved
Reserved
0x0F1C
Reserved
Reserved
Reserved
Reserved
0x0F20
Reserved
Reserved
Reserved
Reserved
0x0F24
Reserved
Reserved
Reserved
Reserved
0x0F28
Reserved
Reserved
Reserved
Reserved
0x0F2C
Reserved
Reserved
Reserved
Reserved
0x0F30
Reserved
Reserved
Reserved
Reserved
0x0F34
Reserved
Reserved
Reserved
Reserved
0x0F38
Reserved
Reserved
Reserved
Reserved
0x0F3C
Reserved
Reserved
Reserved
Reserved
0x0F40
PORTEN
Reserved
Reserved
Reserved
Port input enable register
(Key code target registers)
Reserved
Reserved
Key cord register
0x0F44
KEYCDR
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Port pull-up/down enable register 00 to
29 (Key code target registers)
Port input level selection register 00 to
15 (Key code target registers)
Reserved
Reserved
Reserved
Reserved
Reserved
391
Chapter 12: I/O Ports
Address
Registers
+0
+1
+2
+3
0x01B8
EPFR64
EPFR65
EPFR66
EPFR67
0x01BC
EPFR68
EPFR69
EPFR70
EPFR71
0x01C0
EPFR72
EPFR73
EPFR74
EPFR75
0x01C4
EPFR76
EPFR77
EPFR78
EPFR79
0x01C8
EPFR80
EPFR81
EPFR82
EPFR83
0x01CC
EPFR84
EPFR85
EPFR86
EPFR87
0x01D0
EPFR88
EPFR89
EPFR90
EPFR91
0x01D4
EPFR92
EPFR93
EPFR94
EPFR95
0x01E0
EPFR96
EPFR97
EPFR98
EPFR99
0x01E4
EPFR100
EPFR101
EPFR102
EPFR103
0x01E8
EPFR104
EPFR105
EPFR106
EPFR107
0x01EC
EPFR108
EPFR109
EPFR110
EPFR111
392
Register function
Extended port function register 64 to
111(Key code target registers)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 12: I/O Ports
4.1.
Port Data Register 00 to 29 : PDR00 to 29 (Port Data
Register 00 to 29)
The bit configuration of port data register 00 to 29 is shown below.
These registers hold the output levels of the pins corresponding to individual ports that are in output mode.
PDR00 to PDR29 : Address 0000H, 0001H, (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
X
X
X
X
P[7:0]
Initial
value
X
X
X
X
Attribute R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W
[bit7 to bit0] P (Port) : Port data setting bits
These bits set the output level of external pins P000, P001, ..., when the ports are in output mode. PDR00.P[7:0] is
for external pins P007 to P000
PDR01.P[7:0] is for external pins P017 to P010
PDR02.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Output of "0"
1
Output of "1"
The value read by a read-modify instruction is determined based on the combination with the data direction register
(DDR).
DDR
Reading by read-modify
instruction
1
No
The PDR value can be read.
1
Yes
The PDR value can be read.
0
No
The pin value can be read.
0
Yes
The PDR value can be read.
PDR reading value
PDR13.P[7,2:1], PDR14.P[7:0], PDR15.P[7:6], PDR22.P[4:3], PDR24.P[7:6], PDR25.P[7], PDR26.P[1:0],
PDR27.P[4] are reserved bits. Both writing to and reading from these bits have no effect.
PDR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "Pins of Port
Function (General-Purpose I/O)" in "CHAPTER:OVERVIEW". As for those bits allocated in the missing ports, both
writing and reading have no effect.
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Chapter 12: I/O Ports
4.2.
Data Direction Register 00 to 29 : DDR00 to 29 (Data
Direction Register 00 to 29)
The bit configuration of data direction register 00 to 29 is shown below.
These registers set the I/O directions of the pins when they function as ports. If a pin is to be used for input for a
peripheral, the corresponding bit must be set for input.
DDR00 to DDR29 are key code target registers.
DDR00 to DDR29 : Address 0E00H, 0E01H, (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] P (Port) : Data direction selection bits
These bits set the I/O direction of external pins P000, P001, ..., when the ports are in output mode.
DDR00.P[7:0] is for external pins P007 to P000
DDR01.P[7:0] is for external pins P017 to P010
DDR02.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Input (Initial value)
1
Output
DDR13.P[7,2:1], DDR14.P[7:0], DDR15.P[7:6], DDR22.P[4:3], DDR24.P[7:6], DDR25.P[7], DDR26.P[1:0],
DDR27.P[4] are reserved bits. Both writing to and reading from these bits have no effect.
DDR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "Pins of Port
Function (General-Purpose I/O)" in "CHAPTER:OVERVIEW". As for those bits allocated in the missing ports, both
writing and reading have no effect.
394
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Chapter 12: I/O Ports
4.3.
Port Function Register 00 to 29 : PFR00 to 29 (Port
Function Register 00 to 29)
The bit configuration of port function register 00 to 29 is shown below.
These registers specify whether or not the pins are used to function as ports. If a pin is to be used as a peripheral's
input pin, the corresponding bit must be set for the port function.
PFR00 to PFR29 are key code target registers.
PFR00 to PFR29 : Address 0E20H, 0E21H, (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:Initial value of the each bits can be referred "I/O Map" in "APPENDIX".
[bit7 to bit0] P (Port) : Port function selection bits
These bits set the port function.
PFR00.P[7:0] is for external pins P007 to P000
PFR01.P[7:0] is for external pins P017 to P010
PFR02.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Port function or peripheral input pin (Initial value)
1
Peripheral I/O (bidirectional) pin, peripheral output pin or external bus
pin(set by EPFR)
PFR13.P[7,2:1], PFR14.P[7:0], PFR15.P[7:6], PFR22.P[4:3], PFR24.P[7:6], PFR25.P[7], PFR26.P[1:0], PFR27.P[4]
are reserved bits. Both writing to and reading from these bits have no effect.
PFR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "Pins of Port
Function (General-Purpose I/O)" in "CHAPTER:OVERVIEW". As for those bits allocated in the missing ports, both
writing and reading have no effect.
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395
Chapter 12: I/O Ports
4.4.
Input Data Direct Register 00 to 29 : PDDR00 to 29 (Port
Data Direct Register 00 to 29)
The bit configuration of input data direct register 00 to 29 is shown below.
These registers can always show the voltage levels of individual external pins. These registers can always be read
unconditionally.
PDDR00 to PDDR29 : Address 0E40H, 0E41H, (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
X
X
X
X
X
X
X
X
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit7 to bit0] P (Port) : Read bits
The value of the external pins can be read.
PDDR00.P[7:0] is for external pins P007 to P000
PDDR01.P[7:0] is for external pins P017 to P010
PDDR02.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
"L" level
1
"H" level
PDDR13.P[7,2:1], PDDR14.P[7:0], PDDR15.P[7:6], PDDR22.P[4:3], PDDR24.P[7:6], PDDR25.P[7],
PDDR26.P[1:0], PDDR27.P[4] are reserved bits. Both writing to and reading from these bits have no effect.
PDDR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have no
effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "Pins of Port
Function (General-Purpose I/O)" in "CHAPTER:OVERVIEW". As for those bits allocated in the missing ports, both
writing and reading have no effect.
396
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Chapter 12: I/O Ports
4.5.
Port Pull-up/down Enable Register 00 to 29 : PPER00 to 29
(Port Pull-up/down Enable Register 00 to 29)
The bit configuration of port pull-up/down enable register 00 to 29 is shown below.
These registers enable pull-up or pull-down of each port. These registers are functioned for input condition pins only.
PPER00 to PPER29 are key code target registers.
PPER00 to PPER29 : Address 0EC0H, 0EC1H, (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] P (Port) : Pull-up/down enable selection bits
PPER00.P[7:0] is for external pins P007 to P000
PPER01.P[7:0] is for external pins P017 to P010
PPER02.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Pull-up/down disabled (Initial value)
1
Pull-up/down enabled
This series does not have pull-down function.
See "List of Pin Functions" and "I/O Circuit Types" of "CHAPTER: OVERVIEW" for the existence of pull-up
function.
PPER13.P[7,2:1], PPER14.P[7:0], PPER15.P[7:6], PPER22.P[4:3], PPER24.P[7:6], PPER25.P[7], PPER26.P[1:0],
PPER27.P[4] are reserved bits. Both writing to and reading from these bits have no effect.
PPER13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "Pins of Port
Function (General-Purpose I/O)" in "CHAPTER:OVERVIEW". As for those bits allocated in the missing ports, both
writing and reading have no effect.
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Chapter 12: I/O Ports
4.6.
Port Input Level Selection Register 00 to 15: PILR00 to 15
(Port Input Level Register 00 to 15)
The bit configuration of port input level selection register 00 to 15 is shown below.
These registers set the input level for each port. Glitch input may occur. Therefore, if, for example, the relevant pin is
used as an external input clock or trigger for a peripheral, disable the peripheral.
PILR00 to PILR15 are key code target registers.
PILR00 to PILR15 : Address 0EE0H, 0EE1H, (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] P (Port) : Port input level selection bits
PILR00.P[7:0] is for external pins P007 to P000
PILR01.P[7:0] is for external pins P017 to P010
(A similar process continues)
The assignment is as shown above.
Controlled ports: P001, P004, P006, P007, P010 to P017, P052, P114, P120, P123, and P155
P[n]
Operation
0
CMOS hysteresis input
1
Automotive input (Initial value)
For the standard values of input levels, see the data sheet.
PILR00.P[5,3:2,0], PILR05.P[7:3,1:0], PILR11.P[7:5,3:0], PILR12.P[7:4,2:1], and PILR15.P[7:6,4:0] are reserved
bits. Both writing to and reading from these bits have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "Pins of Port
Function (General-Purpose I/O)" in "CHAPTER:OVERVIEW". As for those bits allocated in the missing ports, both
writing and reading have no effect.
398
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Chapter 12: I/O Ports
4.7.
Extended Port Function Register 00 to 111 : EPFR00 to 111
(Extended Port Function Register 00 to 111)
The bit configuration of extended port function register 00 to 111 is show below.
These registers control switching between the peripheral and the external bus, I/O relocation and I/O multiplexing.
Unlike other port registers, these registers have an enable bit for each peripheral, rather than for each pin.
When I/O relocation is executed, glitch occurs by switching and operation may happen by recognition as a signal
change. Therefore, execute I/O relocation for input neglecting inputs from peripheral resource. The external interrupt
flag must be cleared before the interrupt is enabled.
Pin assignment to peripheral resources is made by the registers of PFR and EPFR. However, since all registers cannot
be changed at one time, I/O relocation for outputs must be executed in the port setting state (PFRxx.P[n]=0).
EPFR00 to EPFR111 are key code target registers.
4.7.1.
Extended Port Function Register 00, 01, 56 : EPFR00,
EPFR01, EPFR56
The bit configuration of extended port function register 00, 01, 56 is shown.
These registers select input pins for input capture. (I/O relocation)
EPFR00 : Address 0E60H (Access : Byte, Half-word, Word)
bit7
bit6
ICU3E[1:0]
Initial value
Attribute
ICU3E[1:0] :
ICU2E[1:0] :
ICU1E[1:0] :
ICU0E[1:0] :
0
R/W
0
bit5
bit4
ICU2E[1:0]
0
0
R/W
R/W
R/W
Input capture ch.3 input pin selection.
Input capture ch.2 input pin selection.
Input capture ch.1 input pin selection.
Input capture ch.0 input pin selection.
bit3
bit2
ICU1E[1:0]
bit1
bit0
ICU0E[1:0]
0
0
0
0
R/W
R/W
R/W
R/W
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Chapter 12: I/O Ports
EPFR01 : Address 0E61H (Access : Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
ICU7E
Reserved
ICU6E
Reserved
ICU5E
1
0
1
0
1
0
0
0
R1,WX
R/W
R/W
R/W
bit2
bit1
bit0
ICU9E
Reserved
ICU8E
Attribute R1,WX
R/W
R1,WX
R/W
ICU7E :
Input capture ch.7 input pin selection.
ICU6E :
Input capture ch.6 input pin selection.
ICU5E :
Input capture ch.5 input pin selection.
ICU4E[1:0] :
Input capture ch.4 input pin selection.
bit1
bit0
ICU4E[1:0]
EPFR56 : Address 0E98H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
Attribute R1,WX
R1,WX
R1,WX
ICU9E : Input capture ch.9 input pin selection.
ICU8E : Input capture ch.8 input pin selection.
1
1
0
1
0
R1,WX
R1,WX
R/W
R1,WX
R/W
ICUnE[1:0]
(n=0 to 3)
Operation
00
Input from the ICUn_0 pin
01
Input from the ICUn_1pin
10
Input from the ICUn_2 pin
11
Input from the ICUn_3 pin
ICUnE[1:0]
(n=4)
400
Operation
00
Input from the ICUn_0 pin
01
Input from the ICUn_1pin
10
Input from the ICUn_2 pin
11
Reserved (Input from the ICUn_2 pin)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 12: I/O Ports
ICUnE
(n=5 to 9)
Operation
0
Input from the ICUn_0 pin
1
Input from the ICUn_1pin
EPFR01 [bit7, bit5, bit3] Reserved
EPFR56 [bit7 to bit3, bit1] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.2.
Extended Port Function Register 02 to 05, 57 to 60 :
EPFR02 to 05, 57 to 60
The bit configuration of extended port function register 02 to 05, 57 to 60 is shown.
These registers enable reload timer output and select output/input pins. (I/O relocation and I/O multiplexing)
EPFR02 : Address 0E62H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
bit4
Reserved
1
1
bit3
bit2
TOT0E[1:0]
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
TOT0E[1:0] :
Reload timer ch.0 TOT output pin selection
TIN0E[1:0] :
Reload timer ch.0 TIN input pin selection
bit1
bit0
TIN0E[1:0]
0
0
0
R/W
R/W
R/W
bit1
bit0
Reserved
TIN1E
0
1
0
R/W
R1,WX
R/W
bit1
bit0
Reserved
TIN2E
0
1
0
R/W
R1,WX
R/W
EPFR03 : Address 0E63H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
1
1
bit3
bit2
TOT1E[2:0]
1
0
0
Attribute R1,WX
R1,WX
R1,WX
R/W
R/W
TOT1E[2:0] :
Reload timer ch.1 TOT output pin selection
TIN1E :
Reload timer ch.1 TIN input pin selection
EPFR04 : Address 0E64H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
bit4
Reserved
1
1
bit3
bit2
TOT2E[1:0]
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
TOT2E[1:0] :
Reload timer ch.2 TOT output pin selection
TIN2E :
Reload timer ch.2 TIN input pin selection
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Chapter 12: I/O Ports
EPFR05 : Address 0E65H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
bit4
Reserved
1
1
bit3
bit2
TOT3E[1:0]
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
TOT3E[1:0] :
Reload timer ch.3 TOT output pin selection
TIN3E[1:0] :
Reload timer ch.3 TIN input pin selection
bit1
bit0
TIN3E[1:0]
0
0
0
R/W
R/W
R/W
bit2
bit1
bit0
TOT4E
Reserved
TIN4E
0
1
0
R/W
R1,WX
R/W
bit1
bit0
Reserved
TIN5E
0
1
0
R/W
R1,WX
R/W
bit1
bit0
Reserved
TIN6E
0
1
0
R/W
R1,WX
R/W
bit1
bit0
EPFR57 : Address 0E99H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
TOT4E :
TIN4E :
1
1
bit4
bit3
Reserved Reserved
1
1
1
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
Reload timer ch.4 TOT output pin selection
Reload timer ch.4 TIN input pin selection
EPFR58 : Address 0E9AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
bit4
Reserved
1
1
bit3
bit2
TOT5E[1:0]
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
TOT5E[1:0] :
Reload timer ch.5 TOT output pin selection
TIN5E :
Reload timer ch.5 TIN input pin selection
EPFR59 : Address 0E9BH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
bit4
Reserved
1
1
bit3
bit2
TOT6E[1:0]
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
TOT6E[1:0] :
Reload timer ch.6 TOT output pin selection
TIN6E :
Reload timer ch.6 TIN input pin selection
EPFR60 : Address 0E9CH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
bit4
Reserved
1
1
bit3
TOT7E[1:0]
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
TOT7E[1:0] :
Reload timer ch.7 TOT output pin selection
402
bit2
Reserved Reserved
0
1
1
R/W
R1,WX
R1,WX
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Chapter 12: I/O Ports
TOTnE[2:0]
(n=1)
Operation
000
No output
xx1
Output from the TOTn_0 pin
x1x
Output from the TOTn_1 pin
1xx
Output from the TOTn_2 pin
TOTnE[1:0]
(n=0, 2, 3, 5 to 7)
Operation
00
No output
01
Output from the TOTn_0 pin
10
Output from the TOTn_1 pin
11
Reserved (Output from the TOTn_1 pin)
TOTnE[1:0]
(n=4)
Operation
0
No output
1
Output from the TOTn_0 pin
TINnE[1:0]
(n=0, 3)
Operation
00
Input from the TINn_0 pin
01
Input from the TINn_1 pin
10
Input from the TINn_2 pin
11
Reserved (Input from the TINn_2 pin)
TINnE
(n=1, 2, 4 to 6)
Operation
0
Input from the TINn_0 pin
1
Input from the TINn_1 pin
EPFR02 [bit7 to bit4] Reserved
EPFR03 [bit7 to bit5, bit1] Reserved
EPFR04 [bit7 to bit4, bit1] Reserved
EPFR05 [bit7 to bit4] Reserved
EPFR57 [bit7 to bit3, bit1] Reserved
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EPFR58 [bit7 to bit4, bit1] Reserved
EPFR59 [bit7 to bit4, bit1] Reserved
EPFR60 [bit7 to bit4, bit1, bit0] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.3.
Extended Port Function Register 06 to 09, 33 to 36, 61 to
64, 100 to 107 : EPFR06 to 09, 33 to 36, 61 to 64, 100 to
107
The bit configuration of extended port function register 06 to 09, 33 to 36, 61 to 64, 100 to 107 is
shown.
These registers enable multi-function serial interface output. (I/O relocation and I/O multiplexing)
The relocation of I2C of ch.3 to ch.8 and ch.11 to ch.19 doesn't correspond. Please set the register so that the
relocation of _0 is selected when you select I2C with ch.3 to ch.8 and ch.11 to ch.19.
EPFR35 : Address 0E83H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
1
bit4
bit3
bit2
bit1
SOT0E[1:0]
SCK0E[1:0]
0
0
0
Attribute R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
SOT0E[1:0] :
Multi-function serial interface ch.0 SOT output pin selection
SCK0E[1:0] :
Multi-function serial interface ch.0 SCK output/input pin selection
SIN0E :
Multi-function serial interface ch.0 SIN input pin selection
bit0
SIN0E
0
0
R/W
R/W
EPFR36 : Address 0E84H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
1
1
1
1
bit3
bit2
bit1
bit0
SOT1E
Reserved
SCK1E
Reserved
0
1
0
1
R/W
R1,WX
bit1
bit0
SCK2E
Reserved
0
1
R/W
R1,WX
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
R1,WX
SOT1E : Multi-function serial interface ch.1 SOT output pin selection
SCK1E : Multi-function serial interface ch.1 SCK output/input pin selection
EPFR06 : Address 0E66H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
1
1
bit3
bit2
SOT2E[1:0]
1
1
0
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
SOT2E[1:0] :
Multi-function serial interface ch.2 SOT output pin selection
SCK2E :
Multi-function serial interface ch.2 SCK output/input pin selection
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EPFR07 : Address 0E67H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
1
bit4
bit3
bit2
bit1
SOT3E[1:0]
SCK3E[1:0]
0
0
0
Attribute R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
SOT3E[1:0] :
Multi-function serial interface ch.3 SOT output pin selection
SCK3E[1:0] :
Multi-function serial interface ch.3 SCK output/input pin selection
SIN3E :
Multi-function serial interface ch.3 SIN input pin selection
bit0
SIN3E
0
0
R/W
R/W
bit1
bit0
EPFR08 : Address 0E68H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
1
bit4
bit3
bit2
SOT4E[1:0]
SCK4E[1:0]
0
0
0
SIN4E
0
0
R/W
R/W
bit2
bit1
bit0
SOT5E
SCK5E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT6E
SCK6E
Reserved
0
0
1
R/W
R1,WX
Attribute R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
SOT4E[1:0] :
Multi-function serial interface ch.4 SOT output pin selection
SCK4E[1:0] :
Multi-function serial interface ch.4 SCK output/input pin selection
SIN4E :
Multi-function serial interface ch.4 SIN input pin selection
EPFR09 : Address 0E69H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT5E : Multi-function serial interface ch.5 SOT output pin selection
SCK5E : Multi-function serial interface ch.5 SCK output/input pin selection
EPFR33 : Address 0E81H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT6E : Multi-function serial interface ch.6 SOT output pin selection
SCK6E : Multi-function serial interface ch.6 SCK output/input pin selection
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EPFR34 : Address 0E82H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
bit2
bit1
bit0
SOT7E
SCK7E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT8E
SCK8E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT9E
SCK9E
Reserved
0
0
1
R/W
R1,WX
bit1
bit0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT7E : Multi-function serial interface ch.7 SOT output pin selection
SCK7E : Multi-function serial interface ch.7 SCK output/input pin selection
EPFR61 : Address 0E9DH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT8E : Multi-function serial interface ch.8 SOT output pin selection
SCK8E : Multi-function serial interface ch.8 SCK output/input pin selection
EPFR62 : Address 0E9EH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT9E : Multi-function serial interface ch.9 SOT output pin selection
SCK9E : Multi-function serial interface ch.9 SCK output/input pin selection
EPFR63 : Address 0E9FH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
1
1
1
bit4
bit3
SOT10E
Reserved
0
1
bit2
SCK10E Reserved Reserved
0
Attribute R1,WX
R1,WX
R1,WX
R/W
R1,WX
R/W
SOT10E : Multi-function serial interface ch.10 SOT output pin selection
SCK10E : Multi-function serial interface ch.10 SCK output/input pin selection
406
1
1
R1,WX
R1,WX
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Chapter 12: I/O Ports
EPFR64 : Address 01B8H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
bit2
bit1
bit0
SOT11E
SCK11E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT12E
SCK12E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT13E
SCK13E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT14E
SCK14E
Reserved
0
0
1
R/W
R1,WX
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT11E : Multi-function serial interface ch.11 SOT output pin selection
SCK11E : Multi-function serial interface ch.11 SCK output/input pin selection
EPFR100 : Address 01E4H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT12E : Multi-function serial interface ch.12 SOT output pin selection
SCK12E : Multi-function serial interface ch.12 SCK output/input pin selection
EPFR101 : Address 01E5H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT13E : Multi-function serial interface ch.13 SOT output pin selection
SCK13E : Multi-function serial interface ch.13 SCK output/input pin selection
EPFR102 : Address 01E6H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT14E : Multi-function serial interface ch.14 SOT output pin selection
SCK14E : Multi-function serial interface ch.14 SCK output/input pin selection
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EPFR103 : Address 01E7H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
bit2
bit1
bit0
SOT15E
SCK15E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT16E
SCK16E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT17E
SCK17E
Reserved
0
0
1
R/W
R1,WX
bit2
bit1
bit0
SOT18E
SCK18E
Reserved
0
0
1
R/W
R1,WX
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT15E : Multi-function serial interface ch.15 SOT output pin selection
SCK15E : Multi-function serial interface ch.15 SCK output/input pin selection
EPFR104 : Address 01E8H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT16E : Multi-function serial interface ch.16 SOT output pin selection
SCK16E : Multi-function serial interface ch.16 SCK output/input pin selection
EPFR105 : Address 01E9H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT17E : Multi-function serial interface ch.17 SOT output pin selection
SCK17E : Multi-function serial interface ch.17 SCK output/input pin selection
EPFR106 : Address 01EAH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT18E : Multi-function serial interface ch.18 SOT output pin selection
SCK18E : Multi-function serial interface ch.18 SCK output/input pin selection
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EPFR107 : Address 01EBH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
1
1
bit2
bit1
bit0
SOT19E
SCK19E
Reserved
0
0
1
R/W
R1,WX
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
SOT19E : Multi-function serial interface ch.19 SOT output pin selection
SCK19E : Multi-function serial interface ch.19 SCK output/input pin selection
SOT0, 2 pin selection
SOTnE[1:0] (n=0, 2)
Operation
00
No output
01
Output from the SOTn_0 pin
1x
Output from the SOTn_1 pin
SOT1, 5 to 9, 11 to 19 pin selection
SOTnE (n=1, 5 to 9,
11 to 19)
Operation
0
No output
1
Output from the SOTn_0 pin
SOT10 pin selection
SOTnE (n=10)
Operation
0
No output
1
Output from the SOTn_1 pin
SOT3, 4 pin selection
SOTnE[1:0] (n=3, 4)
Operation
00
No output
01
Output from the SOTn_0 pin
10
Output from the SOTn_1 pin
11
Output from the SOTn_2 pin
SCK0 pin selection
SCKnE[1:0] (n=0)
Operation
00
Non input/output from the SCKn_0
01
Input from the SCKn_0 / output from the SCKn
10
Input from the SCKn_1 / output from the SCKn_1
11
Reserved (Input from the SCKn_1 / output from the SCKn_1)
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SCK 1, 2, 5 to 9, 11 to 19 pin selection
SCKnE (n= 1, 2, 5 to 9,
11 to 19)
Operation
0
Non input/output from the SCKn_0
1
Input from the SCKn_0 / output from the SCKn
SCK 10 pin selection
SCKnE (n= 10)
Operation
0
Non input/output from the SCKn_1
1
Input from the SCKn_1 / output from the SCKn_1
SCK3, 4 pin selection
SCKnE[1:0] (n=3, 4)
Operation
00
Non input/output from the SCKn_0
01
Input from the SCKn_0 / output from the SCKn
10
Input from the SCKn_1 / output from the SCKn_1
11
Input from the SCKn_2 / output from the SCKn_2
SIN0, 3, 4 pin selection
SINnE (n=0, 3, 4)
Operation
0
Input from the SINn_0 pin
1
Input from the SINn_1 pin
EPFR35 [bit7 to bit5] Reserved
EPFR36 [bit7 to bit4, bit2, bit0] Reserved
EPFR06 [bit7 to bit4, bit0] Reserved
EPFR07 [bit7 to bit5] Reserved
EPFR08 [bit7 to bit5] Reserved
EPFR09 [bit7 to bit3, bit0] Reserved
EPFR33 [bit7 to bit3, bit0] Reserved
EPFR34 [bit7 to bit3, bit0] Reserved
EPFR61 [bit7 to bit3, bit0] Reserved
EPFR62 [bit7 to bit3, bit0] Reserved
EPFR63 [bit7 to bit5, bit3, bit1, bit0] Reserved
EPFR64 [bit7 to bit3, bit0] Reserved
EPFR100 [bit7 to bit3, bit0] Reserved
EPFR101 [bit7 to bit3, bit0] Reserved
EPFR102 [bit7 to bit3, bit0] Reserved
EPFR103 [bit7 to bit3, bit0] Reserved
EPFR104 [bit7 to bit3, bit0] Reserved
EPFR105 [bit7 to bit3, bit0] Reserved
EPFR106 [bit7 to bit3, bit0] Reserved
EPFR107 [bit7 to bit3, bit0] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.4.
Extended Port Function Register 10 to 15, 45, 71 to
89 to 98 : EPFR10 to 15, 45, 71 to 78, 89 to 98
78,
The bit configuration of extended port function register 10 to 15, 45, 71 to 78, 89 to 98 is shown.
These registers enable PPG output and select output pins. (I/O relocation and I/O multiplexing)
EPFR10 : Address 0E6AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
PPG1E[1:0] :
PPG ch.1 output pin selection
PPG0E[1:0] :
PPG ch.0 output pin selection
bit3
bit2
bit1
bit0
PPG1E[1:0]
PPG0E[1:0]
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
EPFR11 : Address 0E6BH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
PPG3E[1:0] :
PPG ch.3 output pin selection
PPG2E[1:0] :
PPG ch.2 output pin selection
bit3
bit2
PPG3E[1:0]
PPG2E[1:0]
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
EPFR12 : Address 0E6CH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
1
1
1
1
Attribute R1,WX
R1,WX
R1,WX
R1,WX
PPG5E[1:0] :
PPG ch.5 output pin selection
PPG4E[1:0] :
PPG ch.4 output pin selection
bit3
bit2
PPG5E[1:0]
PPG4E[1:0]
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
PPG7E
PPG6E
EPFR13 : Address 0E6DH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
1
1
1
Attribute R1,WX
R1,WX
R1,WX
PPG7E : PPG ch.7 output pin selection
PPG6E : PPG ch.6 output pin selection
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
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EPFR14 : Address 0E6EH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
1
1
1
Attribute R1,WX
R1,WX
R1,WX
PPG9E : PPG ch.9 output pin selection
PPG8E : PPG ch.8 output pin selection
bit1
bit0
PPG9E
PPG8E
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
bit2
bit1
bit0
PPG12E
PPG11E
PPG10E
EPFR15 : Address 0E6FH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
1
1
Attribute R1,WX
R1,WX
R1,WX
PPG12E : PPG ch.12 output pin selection
PPG11E : PPG ch.11 output pin selection
PPG10E : PPG ch.10 output pin selection
1
1
0
0
0
R1,WX
R1,WX
R/W
R/W
R/W
bit2
bit1
bit0
PPG15E
PPG14E
PPG13E
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
EPFR45 : Address 0E8DH (Access : Byte, Half-word, Word)
bit7
Reserved
Initial value
1
bit6
bit5
bit4
bit3
PPG17E[1:0]
PPG16E[1:0]
0
0
0
Attribute R1,WX
R/W
R/W
R/W
PPG17E[1:0] :
PPG ch.17 output pin selection
PPG16E[1:0] :
PPG ch.16 output pin selection
PPG15E :
PPG ch.15 output pin selection
PPG14E :
PPG ch.14 output pin selection
PPG13E :
PPG ch.13 output pin selection
EPFR71 : Address 01BFH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG21E Reserved PPG20E
Initial value
1
0
1
bit3
Reserved
bit2
PPG19E Reserved PPG18E
0
1
0
1
0
Attribute R1,WX
R/W
R1,WX
PPG21E : PPG ch.21 output pin selection
PPG20E : PPG ch.20 output pin selection
PPG19E : PPG ch.19 output pin selection
PPG18E : PPG ch.18 output pin selection
R/W
R1,WX
R/W
R1,WX
R/W
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EPFR72 : Address 01C0H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PPG25E[1:0]
PPG24E[1:0]
PPG23E[1:0]
0
0
0
0
1
0
R/W
R/W
R1,WX
R/W
bit1
bit0
0
0
Attribute
R/W
R/W
R/W
R/W
PPG25E[1:0] :
PPG ch.25 output pin selection
PPG24E[1:0] :
PPG ch.24 output pin selection
PPG23E[1:0] :
PPG ch.23 output pin selection
PPG22E :
PPG ch.22 output pin selection
Reserved PPG22E
EPFR73 : Address 01C1H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
bit3
bit2
PPG29E[1:0]
PPG28E[1:0]
PPG27E[1:0]
PPG26E[1:0]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
0
0
Attribute
R/W
R/W
R/W
R/W
PPG29E[1:0] :
PPG ch.29 output pin selection
PPG28E[1:0] :
PPG ch.28 output pin selection
PPG27E[1:0] :
PPG ch.27 output pin selection
PPG26E[1:0] :
PPG ch.26 output pin selection
EPFR74 : Address 01C2H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
bit3
bit2
PPG33E[1:0]
PPG32E[1:0]
PPG31E[1:0]
PPG30E[1:0]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
0
0
Attribute
R/W
R/W
R/W
R/W
PPG33E[1:0] :
PPG ch.33 output pin selection
PPG32E[1:0] :
PPG ch.32 output pin selection
PPG31E[1:0] :
PPG ch.31 output pin selection
PPG30E[1:0] :
PPG ch.30 output pin selection
EPFR75 : Address 01C3H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
bit3
bit2
PPG37E[1:0]
PPG36E[1:0]
PPG35E[1:0]
PPG34E[1:0]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
0
0
Attribute
R/W
R/W
R/W
R/W
PPG37E[1:0] :
PPG ch.37 output pin selection
PPG36E[1:0] :
PPG ch.36 output pin selection
PPG35E[1:0] :
PPG ch.35 output pin selection
PPG34E[1:0] :
PPG ch.34 output pin selection
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EPFR76 : Address 01C4H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
PPG41E[1:0]
PPG40E[1:0]
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
PPG41E[1:0] :
PPG ch.41 output pin selection
PPG40E[1:0] :
PPG ch.40 output pin selection
PPG39E :
PPG ch.39 output pin selection
PPG38E :
PPG ch.38 output pin selection
bit3
PPG39E
bit2
bit1
bit0
Reserved PPG38E Reserved
0
1
0
1
R/W
R1,WX
R/W
R1,WX
bit1
bit0
EPFR77 : Address 01C5H (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
1
bit5
PPG45E
1
0
bit4
bit3
bit2
PPG44E[1:0]
PPG43E[1:0]
0
0
0
0
0
R/W
R/W
R/W
R/W
bit1
bit0
PPG47E
PPG46E
Attribute R1,WX
R1,WX
R/W
R/W
PPG45E :
PPG ch.45 output pin selection
PPG44E[1:0] :
PPG ch.44 output pin selection
PPG43E[1:0] :
PPG ch.43 output pin selection
PPG42E :
PPG ch.42 output pin selection
PPG42E
EPFR78 : Address 01C6H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
1
1
1
Attribute R1,WX
R1,WX
R1,WX
PPG47E : PPG ch.47 output pin selection
PPG46E : PPG ch.46 output pin selection
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
bit1
bit0
EPFR89 : Address 01D1H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG51E Reserved PPG50E
Initial value
1
0
1
0
Attribute R1,WX
R/W
R1,WX
R/W
PPG51E :
PPG ch.51 output pin selection
PPG50E :
PPG ch.50 output pin selection
PPG49E[1:0] :
PPG ch.49 output pin selection
PPG48E[1:0] :
PPG ch.48 output pin selection
414
bit3
bit2
PPG49E[1:0]
PPG48E[1:0]
0
0
0
0
R/W
R/W
R/W
R/W
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EPFR90 : Address 01D2H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG55E Reserved PPG54E
Initial value
1
0
1
Attribute R1,WX
R/W
R1,WX
PPG55E : PPG ch.55 output pin selection
PPG54E : PPG ch.54 output pin selection
PPG53E : PPG ch.53 output pin selection
PPG52E : PPG ch.52 output pin selection
bit3
Reserved
bit2
bit1
bit0
PPG53E Reserved PPG52E
0
1
0
1
0
R/W
R1,WX
R/W
R1,WX
R/W
bit1
bit0
EPFR91 : Address 01D3H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG59E Reserved PPG58E
Initial value
1
0
1
Attribute R1,WX
R/W
R1,WX
PPG59E : PPG ch.59 output pin selection
PPG58E : PPG ch.58 output pin selection
PPG57E : PPG ch.57 output pin selection
PPG56E : PPG ch.56 output pin selection
bit3
Reserved
bit2
PPG57E Reserved PPG56E
0
1
0
1
0
R/W
R1,WX
R/W
R1,WX
R/W
bit1
bit0
EPFR92 : Address 01D4H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG63E Reserved PPG62E
Initial value
1
0
1
Attribute R1,WX
R/W
R1,WX
PPG63E : PPG ch.63 output pin selection
PPG62E : PPG ch.62 output pin selection
PPG61E : PPG ch.61 output pin selection
PPG60E : PPG ch.60 output pin selection
bit3
Reserved
bit2
PPG61E Reserved PPG60E
0
1
0
1
0
R/W
R1,WX
R/W
R1,WX
R/W
bit1
bit0
EPFR93 : Address 01D5H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
bit3
bit2
PPG67E[1:0]
PPG66E[1:0]
PPG65E[1:0]
PPG64E[1:0]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
0
0
Attribute
R/W
R/W
R/W
R/W
PPG67E[1:0] :
PPG ch.67 output pin selection
PPG66E[1:0] :
PPG ch.66 output pin selection
PPG65E[1:0] :
PPG ch.65 output pin selection
PPG64E[1:0] :
PPG ch.64 output pin selection
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EPFR94 : Address 01D6H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG71E Reserved PPG70E
Initial value
1
0
1
Attribute R1,WX
R/W
R1,WX
PPG71E : PPG ch.71 output pin selection
PPG70E : PPG ch.70 output pin selection
PPG69E : PPG ch.69 output pin selection
PPG68E : PPG ch.68 output pin selection
bit3
Reserved
bit2
bit1
bit0
PPG69E Reserved PPG68E
0
1
0
1
0
R/W
R1,WX
R/W
R1,WX
R/W
bit1
bit0
EPFR95 : Address 01D7H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG75E Reserved PPG74E
Initial value
1
0
1
Attribute R1,WX
R/W
R1,WX
PPG75E : PPG ch.75 output pin selection
PPG74E : PPG ch.74 output pin selection
PPG73E : PPG ch.73 output pin selection
PPG72E : PPG ch.72 output pin selection
bit3
Reserved
bit2
PPG73E Reserved PPG72E
0
1
0
1
0
R/W
R1,WX
R/W
R1,WX
R/W
bit1
bit0
EPFR96 : Address 01E0H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG79E Reserved PPG78E
Initial value
1
0
1
Attribute R1,WX
R/W
R1,WX
PPG79E : PPG ch.79 output pin selection
PPG78E : PPG ch.78 output pin selection
PPG77E : PPG ch.77 output pin selection
PPG76E : PPG ch.76 output pin selection
bit3
Reserved
bit2
PPG77E Reserved PPG76E
0
1
0
1
0
R/W
R1,WX
R/W
R1,WX
R/W
bit1
bit0
EPFR97 : Address 01E1H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved PPG83E Reserved PPG82E
Initial value
1
0
1
bit3
Reserved
bit2
PPG81E Reserved PPG80E
0
1
0
1
0
Attribute R1,WX
R/W
R1,WX
PPG83E : PPG ch.83 output pin selection
PPG82E : PPG ch.82 output pin selection
PPG81E : PPG ch.81 output pin selection
PPG80E : PPG ch.80 output pin selection
R/W
R1,WX
R/W
R1,WX
R/W
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EPFR98 : Address 01E2H (Access : Byte, Half-word, Word)
bit7
Initial value
bit6
bit5
bit4
PPG87E[1:0]
PPG86E[1:0]
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
PPG87E[1:0] :
PPG ch.87 output pin selection
PPG86E[1:0] :
PPG ch.86 output pin selection
PPG85E :
PPG ch.85 output pin selection
PPG84E :
PPG ch.84 output pin selection
bit3
Reserved
bit2
bit1
bit0
PPG85E Reserved PPG84E
1
0
1
0
R1,WX
R/W
R1,WX
R/W
PPGnE[1:0] (n= 0 to 5, 16,
17, 23 to 37, 40, 41, 43, 44,
48, 49, 64 to 67, 86, 87)
Operation
00
No output
01
Output from the PPGn_0 pin
1x
Output from the PPGn_1 pin
PPGnE (n= 6 to 15, 18 to 22,
42, 45 to 47, 50 to 63,
68 to 85)
Operation
0
No output
1
Output from the PPGn_0 pin
PPGnE (n= 38, 39)
Operation
0
No output
1
Output from the PPGn_1 pin
EPFR10 [bit7 to bit4] Reserved
EPFR11 [bit7 to bit4] Reserved
EPFR12 [bit7 to bit4] Reserved
EPFR13 [bit7 to bit2] Reserved
EPFR14 [bit7 to bit2] Reserved
EPFR15 [bit7 to bit3] Reserved
EPFR45 [bit7] Reserved
EPFR71 [bit7, bit5, bit3, bit1] Reserved
EPFR72 [bit1] Reserved
EPFR76 [bit2, bit0] Reserved
EPFR77 [bit7, bit6] Reserved
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EPFR78 [bit7 to bit2] Reserved
EPFR89 [bit7, bit5] Reserved
EPFR90 [bit7, bit5, bit3, bit1] Reserved
EPFR91 [bit7, bit5, bit3, bit1] Reserved
EPFR92 [bit7, bit5, bit3, bit1] Reserved
EPFR94 [bit7, bit5, bit3, bit1] Reserved
EPFR95 [bit7, bit5, bit3, bit1] Reserved
EPFR96 [bit7, bit5, bit3, bit1] Reserved
EPFR97 [bit7, bit5, bit3, bit1] Reserved
EPFR98 [bit3, bit1] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.5.
Extended Port Function Register 79, 80, 99 : EPFR79, 80,
99
The bit configuration of extended port function register 79, 80, 99 is shown.
These registers select PPG trigger input pins. (I/O relocation)
EPFR79 : Address 01C7H (Access : Byte, Half-word, Word)
bit7
bit6
TRG5E[1:0]
Initial value
Attribute
bit5
bit4
bit3
bit2
TRG4E
TRG3E
TRG2E
TRG1E
bit1
bit0
TRG0E[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
TRG5E[1:0] :
TRG4E :
TRG3E :
TRG2E :
TRG1E :
TRG0E[1:0] :
PPG trigger ch.5 input pin selection
PPG trigger ch.4 input pin selection
PPG trigger ch.3 input pin selection
PPG trigger ch.2 input pin selection
PPG trigger ch.1 input pin selection
PPG trigger ch.0 input pin selection
EPFR80 : Address 01C8H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
TRG9E :
TRG8E :
TRG7E :
TRG6E[1:0] :
418
bit4
bit3
bit2
TRG9E
TRG8E
TRG7E
TRG6E[1:0]
1
1
1
0
0
0
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
PPG trigger ch.9 input pin select
PPG trigger ch.8 input pin select
PPG trigger ch.7 input pin select
PPG trigger ch.6 input pin select
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EPFR99 : Address 01E3H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
TRG17E :
TRG16E :
TRG13E :
TRG12E :
bit3
bit2
bit1
bit0
TRG17E
TRG16E
TRG13E
TRG12E
1
1
1
1
0
0
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
PPG trigger ch.17 input pin select
PPG trigger ch.16 input pin select
PPG trigger ch.13 input pin select
PPG trigger ch.12 input pin select
TRGnE[1:0] (n=0, 5, 6)
Operation
00
Input from the TRGn_0 pin (Initial value)
01
Input from the TRGn_1 pin
1x
Input from the TRGn_2 pin
TRGnE (n= 1 to 4, 7 to 9,
12, 13, 16, 17)
Operation
0
Input from the TRGn_0 pin (Initial value)
1
Input from the TRGn_1 pin
EPFR80 [bit7 to bit5] Reserved
EPFR99 [bit7 to bit4] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.6.
Extended Port Function Register 51, 86 : EPFR51, 86
The bit configuration of extended port function register 51, 86 is shown.
This register enables CAN output and selects input pins. (I/O relocation and I/O multiplexing)
EPFR86 : Address 01CEH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
bit4
bit3
bit2
RX1E
TX2E
TX1E
bit1
bit0
TX0E[1:0]
1
1
1
0
0
0
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
bit1
bit0
TX4E
TX3E
EPFR51 : Address 0E93H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
bit4
bit3
RX5E
bit2
TX5E[1:0]
1
1
1
0
0
0
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
TXnE (n=0 to 5) : CAN channel n transmission data output enabled
TXnE (n=1 to 4)
Operation
0
CAN channel n output disabled (Initial value)
1
CAN channel n output enabled
TXnE[1:0] (n=0, 5)
Operation
00
CAN channel n output disabled (Initial value)
01
CAN channel TXn(128)_0 output enabled
1x
CAN channel TXn(128)_1 output enabled
RXnE (n=1, 5) : CAN channel n reception data input pin select
RXnE (n=1, 5)
420
Operation
0
CAN channel RXn(128)_0 input enabled (Initial value)
1
CAN channel RXn(128)_1 input enabled
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EPFR86 [bit7 to bit5] Reserved
EPFR51 [bit7 to bit5] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.7.
Extended Port Function Register 26 : EPFR26
The bit configuration of extended port function register 26 is shown.
This register enables Base Timer output and selects output and input pins. (I/O relocation and I/O multiplexing)
EPFR26 : Address 0E7AH (Access : Byte, Half-word, Word)
bit7
bit6
TIB1E[1:0]
Initial value
bit5
bit4
TIB0E[1:0]
bit3
bit2
TIA1E[1:0]
bit1
bit0
TIA0E[1:0]
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIBnE[1:0]
(n=0, 1) : Base Timer TIOBn input pin select
TIBnE[1:0] (n=0, 1)
Operation
x0
Input from the base timer TIOBn_0 (Initial value)
x1
Input from the base timer TIOBn_1
TIA0E[1:0]: Base Timer TIOA0 output pin select
TIA0E[1:0]
Operation
00
Base timer TIOA0_0, TIOA0_1 output disabled (Initial value)
01
Base timer TIOA0_0 output enabled
1x
Base timer TIOA0_1 output enabled
TIA1E[1:0]: Base Timer TIOA1 output/input pin select
TIA1E[1:0]
Operation
00
Base timers TIOA1_0, TIOA1_1 output disabled, Input from the base
timer TIOA1_0 (Initial value)
01
Base timer TIOA1_0 output enabled, Input from the base timer
TIOA1_0
1x
Base timer TIOA1_1 output enabled, Input from the base timer
TIOA1_1
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4.7.8.
Extended Port Function Register 27 : EPFR27
The bit configuration of extended port function register 27 is shown.
This register enables real time clock output.
EPFR27 : Address 0E7BH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
bit4
bit3
bit2
WOTE
bit1
bit0
Reserved
1
1
1
0
1
1
1
1
R1,WX
R1,WX
R1,WX
R/W
R1,WX
R1,WX
R1,WX
R1,WX
WOTE : Real time clock over flow output enable
WOTE
Operation
0
Real time clock over flow output disabled (Initial value)
1
Real time clock over flow output enabled
EPFR27 [bit7 to bit5, bit3 to bit0] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.9.
Extended Port Function Register 28 : EPFR28
The bit configuration of extended port function register 28 is shown.
This register enables free-run timer clock input. (I/O multiplexing)
EPFR28 : Address 0E7CH (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
FRCK5E
FRCK4E
bit3
bit2
bit1
bit0
FRCK3E Reserved FRCK1E Reserved
1
1
0
0
0
1
0
1
R1,WX
R1,WX
R/W
R/W
R/W
R1,WX
R/W
R1,WX
FRCK5E : Free-run timer ch.5 clock input selection
FRCK4E : Free-run timer ch.4 clock input selection
FRCK3E : Free-run timer ch.3 clock input selection
FRCK1E : Free-run timer ch.1 clock input selection
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FRCKnE (n=1, 3 to 5)
Operation
0
Input from the FRCKn_0 (Initial value)
1
Input from the FRCKn_1
EPFR28 [bit7, bit6, bit2, bit0] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.10. Extended Port Function Register 29, 48, 81, 82 : EPFR29,
48, 81, 82
The bit configuration of extended port function register 29, 48, 81, 82 is shown.
These registers enable output compare output. (I/O multiplexing and I/O relocation)
EPFR29 : Address 0E7DH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
EPFR81 : Address 01C9H (Access : Byte, Half-word, Word)
bit7
Initial value
Attribute
bit6
bit5
bit4
bit3
bit2
OCU7E[1:0]
OCU6E[1:0]
Reserved
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
EPFR82 : Address 01CAH (Access : Byte, Half-word, Word)
bit7
Initial value
Attribute
bit6
bit5
bit4
bit3
bit2
OCU11E[1:0]
OCU10E[1:0]
OCU9E[1:0]
OCU8E[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
EPFR48 : Address 0E90H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
Reserved
bit2
OCU13E Reserved OCU12E
1
1
1
1
1
0
1
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R1,WX
R/W
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OCUnE[1:0] (n=6 to 11) : Output compare channel n output enable
OCUnE[1:0] (n=6 to 11)
Operation
00
No output
01
Output from the OCUn_0
10
Output from the OCUn_1
11
Setting is prohibited
OCUnE (n=12, 13) : Output compare channel n output enable
OCUnE (n=12, 13)
Operation
0
No output
1
Output from the OCUn_0
EPFR29 [bit7 to bit0] Reserved
EPFR81 [bit3 to bit0] Reserved
The read value is the written value.
EPFR48 [bit7 to bit3, bit1] Reserved
These bits always read "1". Writing has no effect on operation.
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Chapter 12: I/O Ports
4.7.11. Extended Port Function Register 49, 83 : EPFR49, 83
The bit configuration of extended port function register 49, 83 is shown.
This register selects up/down counter pins. (I/O relocation)
EPFR83 : Address 01CBH (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
ZIN1E
BIN1E
AIN1E
1
0
0
0
0
R1,WX
R/W
R/W
R/W
R/W
bit1
bit0
BIN0E
AIN0E
0
0
0
R/W
R/W
R/W
bit2
bit1
bit0
ZIN2E
BIN2E
AIN2E
ZIN0E[1:0]
EPFR49 : Address 0E91H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
1
1
1
1
1
0
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
AINnE (n=0 to 2)
Operation
0
Input from the AINn_0 pin (Initial value)
1
Input from the AINn_1 pin
Same BIN0E, BIN1E, BIN2E, ZIN1E, ZIN2E
ZINnE[1:0] (n=0)
Operation
00
Input from the ZINn_0 pin (Initial value)
01
Input from the ZINn_1 pin
1x
Input from the ZINn_2 pin
EPFR83 [bit7] Reserved
EPFR49 [bit7 to bit3] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.12. Extended Port Function Register 42 : EPFR42
The bit configuration of extended port function register 42 is shown.
This register selects D/A converter output signal. (I/O multiplexing)
EPFR42 : Address 0E8AH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
DAS1
DAS0
1
1
1
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
DAS1 : D/A converter 1 output data selection enable
DAS0 : D/A converter 0 output data selection enable
DASn (n=0, 1)
Operation
0
DAOn output disabled (Initial value)
1
DAOn output enabled
EPFR42 [bit7 to bit2] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.13. Extended Port Function Register 43, 44, 50 : EPFR43, 44,
50
The bit configuration of extended port function register 43, 44, 50 is shown.
These registers select external interrupt pins. (I/O relocation)
EPFR43 : Address 0E8BH (Access : Byte, Half-word, Word)
bit7
bit6
INT7E
Initial value
Attribute
bit5
Reserved
bit4
bit3
bit2
bit1
bit0
INT4E
INT3E
INT2E
INT1E
Reserved
0
1
1
0
0
0
0
1
R/W
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R1,WX
bit1
bit0
INT9E
Reserved
EPFR44 : Address 0E8CH (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
INT14E
INT13E
1
0
0
1
1
1
0
1
R1,WX
R/W
R/W
R1,WX
R1,WX
R1,WX
R/W
R1,WX
bit1
bit0
INT17E
INT16E
Reserved
EPFR50 : Address 0E92H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
1
1
1
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
INTnE (n=1 to 4, 7, 9,
13, 14, 16, 17)
Operation
0
Input from the INTn_0 pin (Initial value)
1
Input from the INTn_1 pin
EPFR43 [bit6, bit5, bit0] Reserved
EPFR44 [bit7, bit4 to bit2, bit0] Reserved
EPFR50 [bit7 to bit2] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.14. Extended Port Function Register 65 to 70, 110 : EPFR65
to 70, 110
The bit configuration of extended port function register 65 to 70, 110 is shown.
These registers enable serial chip select output.
EPFR65 : Address 01B9H (Access: Byte, Half-word, Word)
bit7
bit6
SCSO40E[1:0]
Initial value
Attribute
bit5
bit4
SCSO3E[1:0]
bit3
bit2
bit1
bit0
Reserved SCSO2E SCSO1E Reserved
0
0
0
0
1
0
0
1
R/W
R/W
R/W
R/W
R1,WX
R/W
R/W
R1,WX
bit1
bit0
SCSO40E[1:0] : Serial chip select 40 input/output pin select
SCSO3E[1:0] : Serial chip select 3 input/output pin select
SCSO2E :
Serial chip select 2 output pin select
SCSO1E :
Serial chip select 1 input/output pin select
EPFR66 : Address 01BAH (Access: Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
SCSO43E[1:0]
bit3
bit2
SCSO42E[1:0]
SCSO41E[1:0]
1
1
0
0
0
0
0
0
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
R/W
SCSO43E[1:0] : Serial chip select 43 output pin select
SCSO42E[1:0] : Serial chip select 42 output pin select
SCSO41E[1:0] : Serial chip select 41 output pin select
EPFR67 : Address 01BBH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit2
bit1
bit0
SCSO53
E
SCSO52
E
SCSO51
E
SCSO50
E
1
1
1
1
0
0
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
SCSO53E :
Serial chip select 53 output pin select
SCSO52E :
Serial chip select 52 output pin select
SCSO51E :
Serial chip select 51 output pin select
SCSO50E :
Serial chip select 50 output pin select
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EPFR68 : Address 01BCH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
bit2
bit1
bit0
SCSO63
E
SCSO62
E
SCSO61
E
SCSO60
E
1
1
1
1
0
0
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
SCSO63E :
Serial chip select 63 output pin select
SCSO62E :
Serial chip select 62 output pin select
SCSO61E :
Serial chip select 61 output pin select
SCSO60E :
Serial chip select 60 output pin select
EPFR69 : Address 01BDH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
bit2
bit1
bit0
SCSO73
E
SCSO72
E
SCSO71
E
SCSO70
E
1
1
1
1
0
0
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
bit1
bit0
SCSO9E
SCSO8E
SCSO73E :
Serial chip select 73 output pin select
SCSO72E :
Serial chip select 72 output pin select
SCSO71E :
Serial chip select 71 output pin select
SCSO70E :
Serial chip select 70 output pin select
EPFR70 : Address 01BEH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
SCSO11
E
Reserved
Initial value
Attribute
bit4
bit3
bit2
SCSO10E[1:0]
1
1
1
0
0
0
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
SCSO11E :
Serial chip select 11 output pin select
SCSO10E[1:0] : Serial chip select 10 input/output pin select
SCSO9E :
Serial chip select 9 output pin select
SCSO8E : Serial chip select 8 output pin selectEPFR110 : Address 01EEH (Access:
Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
bit3
bit2
bit1
bit0
SCSO19
E
SCSO18
E
SCSO15
E
SCSO14
E
SCSO13
E
SCSO12
E
1
1
0
0
0
0
0
0
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
R/W
SCSO19E :
Serial chip select 19 output pin select
SCSO18E :
Serial chip select 18 output pin select
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SCSO15E :
Serial chip select 15 output pin select
SCSO14E :
Serial chip select 14 output pin select
SCSO13E :
Serial chip select 13 output pin select
SCSO12E :
Serial chip select 12 output pin select
SCSOnE[1:0] (n=3, 40
to 43, 10)
Operation
00
Input from the SCSn_0 pin, output disabled (Initial value) *
01
Input from the SCSn_0 pin / Output from the SCSn_0 pin *
1x
Input from the SCSn_1 pin / Output from the SCSn_1 pin *
*:SCSOnE(n=41, 42, 43) is output only.
SCSOnE (n=2, 50 to
53, 60 to 63, 70 to 73, 8,
9, 11, 12 to 15, 18, 19)
Operation
0
Input from the SCSn_0 pin, output disabled (Initial value) *
1
Input from the SCSn_0 pin / Output from the SCSn_0 pin *
*:SCSOnE(n=51, 52, 53, 61, 62, 63, 71, 72, 73) is output only.
SCSOnE (n=1)
Operation
0
Input from the SCSn_1 pin, output disabled (Initial value)
1
Input from the SCSn_1 pin / Output from the SCSn_1 pin
EPFR65 [bit3, bit0] Reserved
EPFR66 [bit7, bit6] Reserved
EPFR67 [bit7 to bit4] Reserved
EPFR68 [bit7 to bit4] Reserved
EPFR69 [bit7 to bit4] Reserved
EPFR70 [bit7 to bit5] Reserved
EPFR110 [bit7, bit6] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.15. Extended Port Function Register 84, 85 : EPFR84,
85
The bit configuration of extended port function register 84, 85 is shown.
These registers enable wave generator output and select I/O pins. (I/O multiplexing and I/O relocation)
EPFR84 : Address 01CCH (Access: Byte, Half-word, Word)
bit7
bit5
bit4
bit3
bit2
bit1
bit0
RTO3E[1:0]
RTO2E[1:0]
RTO1E[1:0]
RTO0E[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
Initial value
Attribute
bit6
RTO3E[1:0] :
Wave generator real time output ch.3 output pin select
RTO2E[1:0] :
Wave generator real time output ch.2 output pin select
RTO1E[1:0] :
Wave generator real time output ch.1 output pin select
RTO0E[1:0] :
Wave generator real time output ch.0 output pin select
EPFR85 : Address 01CDH (Access: Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
bit3
bit2
DTTI0E[1:0]
RTO5E[1:0]
RTO4E[1:0]
1
1
0
0
0
0
0
0
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
R/W
DTTI0E[1:0] :
Wave generator ch.0 to ch.5 input pin select
RTO5E[1:0] :
Wave generator real time output ch.5 output pin select
RTO4E[1:0] :
Wave generator real time output ch.4 output pin select
RTOnE[1:0] (n=0 to 5)
Operation
00
RTOn output disabled (Initial value)
01
RTOn_0 output enabled
1x
RTOn_1 output enabled
DTTI0E[1:0]
Operation
00
Input from the DTTI_0 pin (Initial value)
01
Input from the DTTI_1 pin
1x
Input from the DTTI_2 pin
EPFR85 [bit7, bit6] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.16. Extended Port Function Register 87 : EPFR87
The bit configuration of extended port function register 87 is shown.
These registers are reserved.
EPFR87 : Address 01CFH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Initial value
Attribute
1
1
1
1
1
1
1
1
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
EPFR87 [bit7 to bit0] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.17. Extended Port Function Register 88 : EPFR88
The bit configuration of extended port function register 88 is shown.
This register enables clock monitor output.
EPFR88 : Address 01D0H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
MONKCL
KE
Reserved
Initial value
Attribute
bit0
1
1
1
1
1
1
1
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
MONKCLKE : Clock monitor output pin select
MONKCLKE
Operation
0
MONCLK output disabled (Initial value)
1
MONCLK output enabled
EPFR88 [bit7 to bit1] Reserved
These bits always read "1". Writing has no effect on operation.
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4.7.18. Extended Port Function Register 108, 109 : EPFR108,
109
The bit configuration of extended port function register 108 and 109 is shown.
These registers enable FlexRay output and select input pins. (I/O multiplexing and I/O relocation)
EPFR108 : Address 01ECH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
bit4
bit3
bit2
bit1
TXENAE[1:0]
TXDAE[1:0]
bit0
RXDAE
1
1
1
0
0
0
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
bit1
bit0
EPFR109 : Address 01EDH (Access: Byte, Half-word, Word)
bit7
bit6
STOP
WTE
Reserved
Initial value
1
bit5
1
Attribute R1,WX
R1,WX
RXDxE (x=A, B)
bit4
bit3
bit2
TXENBE[1:0]
TXDBE[1:0]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
RXDxE (x=A, B)
RXDBE
Operation
0
Input from RXDx_0 (Initial value)
1
Input from RXDx_1
TXDxE[1:0] (x=A, B)
TXDxE[1:0] (x=A, B)
Operation
00
TXDx output disabled (Initial value)
01
TXDx_0 output enabled
1x
TXDx_1 output enabled
TXENxE[1:0] (x=A, B)
TXENxE[1:0] (x=A, B)
Operation
00
TXENx output disabled (Initial value)
01
TXENx_0 output enabled
1x
TXENx_1 output enabled
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STOPWTE
STOPWTE
Operation
0
Input from STOPWT_0 (Initial value)
1
Input from STOPWT_1
EPFR108 [bit7 to bit5] Reserved
EPFR109 [bit7 to bit6] Reserved
These bits always read "1". Writing has no effect on operation.
4.7.19. Extended Port Function Register 111 : EPFR111
The bit configuration of extended port function register 111 is shown.
This register selects an external bus interface pin. (I/O relocation)
EPFR111 : Address 01EFH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
Attribute
bit0
RDYE
1
1
1
1
1
1
1
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
RDYE: External bus ready input select
RDYE
Operation
0
Input from RDY_0 (Initial value)
1
Input from RDY_1
EPFR111 [bit7 to bit1] Reserved
These bits always read "1". Writing has no effect on operation.
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4.8.
Port Input Enable Register: PORTEN (PORT ENable
register)
The bit configuration of the port input enable register is shown below.
This register releases the port input block. At a power-on reset, inputs to most pins are blocked in order to avoid
pass-through current fluctuations before the ports are configured by software. For information on pins whose inputs
are blocked, see "Pin Status in CPU Status" in "APPENDIX". After each port pin is configured for its function by
software, Global PORT Enable (PORTEN.GPORTEN) bit must be set to "1" to enable input. The PORTEN is the
target key code register.
PORTEN : Address 0F40H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial
value
Attribute
bit0
GPORTEN
1
1
1
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
[bit0] GPORTEN (Global PORT ENable) : Global input enable
GPORTEN
Operation
0
Most pins are set to block input. See the "Pin Status" table in the
"APPENDIX" for the pins that are input-blocked.
1
Input block by this bit is released.
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4.9.
KEY CoDe Register : KEYCDR
The bit configuration of key code register is shown.
This register sets register writing that includes the error writing protection function. If writing to this register is not
executed according to the specified method, writing to the target register will become invalid. This register is only
enabled for half-word access.
KEYCDR : Address 0F44H (Access: Half-word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
KEY1
KEY0
SIZE
RADR12
RADR11
RADR10
RADR9
RADR8
0
0
0
0
0
0
0
0
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RADR7
RADR6
RADR5
RADR4
RADR3
RADR2
RADR1
RADR0
0
0
0
0
0
0
0
0
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
[bit15, bit14] KEY1, KEY0: Key code
Key code setting bits. It is necessary to write continuously to this bit according to the order "00", "01", "10", and
"11".
Note:
When the writing order becomes different, the key code setting will become invalid and it will be necessary to reset
them from the beginning.
[bit13] SIZE: Access size
This bit sets the access size for writing to the key code target register. Write the same data to the bit when writing the
key code according to the order "00", "01", "10", and "11".
SIZE
0
1
Description
Set byte access
Set half-word access
Notes:
When different data is written while writing the key code "00", "01", "10", and "11", the key code setting will
become invalid and it will be necessary to reset it from the beginning.
Word access for the key code target register is prohibited.
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[bit12 to bit0] RADR[12:0]: Port address
These bits set the lower 13 bits of the address for the key code target register. Write the same data to the bit when
writing the key code according to the order "00", "01", "10", and "11".
Notes:
When different data is written while writing the key code "00", "01", "10", and "11", the key code setting will
become invalid and it will be necessary to reset them from the beginning.
Key code setting might be canceled because of the DMA transfer. Read the value of the target register, and check if
the value is updated.
5. Operation
This section explains operations of I/O ports.
5.1. Pin I/O Assignment
5.2. EPFR setting priority
5.3. Notes on Input I/O Relocation Setting
5.4. Noise Filter
5.5. Input blocked by GPORTEN
5.6. Notes on Pins with the A/D Converter Function
5.7. Setting when Using the Base Timer TIOA1 Pin
5.8. Key Code Register Function Settings
5.9. Operation at Wake Up from Power Shutdown
5.10. Notes on switching the I/O port function
5.11. Input blocked when specific peripheral functions are used
5.1.
Pin I/O Assignment
The pin I/O assignment is shown below.
Pin I/O assignment is explained here. The I/O direction of each pin is controlled based on the configuration shown
below.
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Figure 5-1 Configuration of Pin I/O Directions, Output Value Selection, and Input Value Retrieval
See "4.1 Port Data Register 00 to 29 : PDR00 to 29 (Port Data Register 00 to 29)" for the
PDR read value.
EPFR
PFR
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
DDR
Input I/O relocation selection circuit
To peripheral
input value
To input I/O relocation selection circuit
Input value from each pins
EPFR
To external bus input value
PDDR
To peripheral input value
As explained in the pertinent section concerning pin assignment, first change the PFR setting to enable the port
function. Since the pin functions as a port, also set the DDR and PDR values in advance if necessary. Note that the
I/O direction of the pin is once set as specified by the DDR. For a pin with the A/D converter function, set the
applicable bit in the analog input enable register (ADER) of the A/D converter to "Port I/O mode". For information
on the setting method, see "CHAPTER: 12-BIT A/D CONVERTER".
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5.1.1.
Peripheral I/O (Bidirectional) Pin Assignment
The peripheral I/O (bidirectional) pin assignment is shown below.
Preparation
Since the pin once functions as a port as the result of step (1), set the DDR and PDR values in advance if
necessary.
For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the
A/D converter to "Port I/O mode". For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER".
(1)Set the PFR for the applicable pin to enable the port function.
(2)Disable the EPFRs for all other peripherals to be used by the relevant pin.
(3)If the relevant pin is also used for the external bus or the relevant peripheral is one of the targets of I/O
multiplexing, set the EPFR of the relevant peripheral. In addition, if the relevant peripheral has the I/O relocation
function, set the terminal to be used with the EPFR of the relevant peripheral.
(4)Set the PFR for the peripheral.
Figure 5-2 Peripheral I/O Assignment Procedure
(2) EPFR
(3)
(1) PFR
(4)
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
DDR
Input I/O relocation selection circuit
Input value from each pins
To peripheral
input value
To input I/O relocation selection circuit
To external bus input value
EPFR
(3)
PDDR
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5.1.2.
Peripheral Input Assignment
The peripheral input assignment is shown below.
Preparation
Since the pin will once function as a port as the result of step (1), set the DDR and PDR values in advance if
necessary.
For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the
A/D converter to "Port I/O mode". For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER".
(1)Set the PFR of the applicable pin to enable the port function.
(2)Disable the EPFRs for all other peripherals that use the relevant pin.
(3)If the relevant peripheral has the I/O relocation function, set the EPFR of the relevant peripheral.
(4)Set the DDR for input.
Figure 5-3 Peripheral Input Assignment Procedure
(2)
EPFR
(1)
PFR
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
(4)
DDR
Input I/O relocation selection circuit
Input value from each pins
To peripheral
input value
To input I/O relocation selection circuit
EPFR
(3)
To external bus input value
PDDR
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Chapter 12: I/O Ports
Note:
As shown in the figure above, if the pin is set for peripheral output etc., its output value is supplied to other peripheral
inputs sharing the same pin.
Example: Since INT10_0 and PPG10_0 are assigned to the same pin (pin number 125, P102), external interrupt 10(0)
can be generated at the PPG10(0) output by setting the pin to peripheral output of PPG10_0.
5.1.3.
Peripheral Output Assignment
The peripheral output assignment is shown below.
The setting method is the same as that described in "5.1.1 Peripheral I/O (Bidirectional) Pin Assignment".
Preparation
Since the pin will once function as a port as the result of step (1), set the DDR and PDR values in advance if
necessary.
For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the
A/D converter to "Port I/O mode". For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER".
(1)Set the PFR of the applicable pin to enable the port function.
(2)Disable the EPFRs for all other peripherals to use the relevant pin.
(3)If the relevant pin is also used for the external bus or the relevant peripheral is one of the targets of I/O
multiplexing, set the EPFR of the relevant peripheral. In addition, if the relevant peripheral has the I/O relocation
function, set the pin to be used with the EPFR of the relevant peripheral.
(4)Set the PFR for the peripheral.
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Figure 5-4 Peripheral Output Assignment Procedure
(2)
EPFR
(3)
(1) PFR
(4)
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
DDR
Input I/O relocation selection circuit
Input value from each pins
To peripheral
input value
To input I/O relocation selection circuit
EPFR
To external bus input value
PDDR
5.1.4.
To peripheral input value
External Bus Assignment
The external bus assignment is shown below.
Preparation
Since the pin will once function as a port as the result of step (1), set the DDR and PDR values in advance if
necessary.
For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the
A/D converter to "Port I/O mode". For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER".
(1)Set the PFR for the applicable pin to enable the port function.
(2)Disable the EPFRs for all other peripherals that use the same pin as the external bus.
(3)Set the PFR for the peripheral.
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Figure 5-5 External Bus Assignment Procedure
(2)
EPFR
PFR
(1)
(3)
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
DDR
Input I/O relocation selection circuit
To peripheral
input value
To input I/O relocation selection circuit
Input value from each pins
EPFR
To external bus input value
PDDR
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5.1.5.
Port Function (Input) Assignment
The port function (input) assignment is shown below.
Preparation
For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the
A/D converter to "Port I/O mode". For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER".
(1)Set the PFR to enable the port function.
(2)Set the DDR for input.
Figure 5-6 Port Function (Input) Assignment Procedure
EPFR
(1)
PFR
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
DDR
Input I/O relocation selection circuit
(2)
Input value from each pins
To peripheral
input value
To input I/O relocation selection circuit
EPFR
To external bus input value
PDDR
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5.1.6.
Port Function (Output) Assignment
The port function (Output) assignment is shown below.
Preparation
For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the
A/D converter to "Port I/O mode". For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER".
(1)Set the PFR to enable the port function.
(2)Set the DDR for output.
Figure 5-7 Port Function (Output) Assignment Procedure
EPFR
PFR
(1)
Peripheral
output value
External bus
Output value
Pin
PDR
Peripheral I/O
direction control
External bus I/O
direction control
(2)
DDR
Input I/O relocation selection circuit
Input value from each pins
To peripheral
input value
To input I/O relocation selection circuit
EPFR
To external bus input value
PDDR
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5.1.7.
A/D Converter Input Assignment
The A/D converter input assignment is shown below.
(1) Set the analog input enable register (ADER) of the A/D converter to analog input mode. See "CHAPTER: 12-bit
A/D CONVERTER".
Since the A/D converter assignment is given the highest priority, no other configuration is required.
5.1.8.
D/A converter output assignment
The D/A converter output assignment is shown below.
Same as "5.1.3. Peripheral Output Assignment"
5.2.
EPFR setting priority
The EPFR setting priority is explained below.
If the PFR is set for the peripheral and multiple EPFR settings are overlapping for a single pin, the valid peripheral is
determined based on the following priorities:
1. D/A converter output
2. CAN
3. Multi-function serial interface
4. PPG
5. Real time clock
6. Base timer
7. Reload timer
8. Output compare
9. FlexRay
10. Clock monitor
11. Waveform generator
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Chapter 12: I/O Ports
5.3.
Notes on Input I/O Relocation Setting
Notes on input I/O relocation setting are shown below.
When switching an input pin to another pin, if there is a difference between pin levels before and after the switch, the
I/O relocation change may become a trigger input to the peripheral that uses the relevant pin as a trigger.
5.4.
Noise Filter
The noise filter is shown.
If an external pin is used to receive input for the following functions, the value that is entered through the noise filter
is treated as the input level:
Port function
External interrupt request
Free-run Timer
Reload timer
PPG
Input capture
A/D converter trigger input
Base timer
UP/DOWN COUNTER
Dead timer interrupt request
FlexRay STOPWT input
Note:
For details, see "Pins of Each Function" in "CHAPTER: OVERVIEW".
5.5.
Input blocked by GPORTEN
The input blocked function by GPORTEN is explained below.
The majority of pins become the input blocked to avoid the change of the penetration current before the port is set
with software at power-on reset. See "Pin Status in CPU Status" in " APPENDIX " for the pin that becomes input
blocked. See "4.8 Port Input Enable Register: PORTEN (PORT ENable register)"for the method of releasing the input
blocked state.
When the state of a pin to be the input blocked state is read during the input blocked by GPORTEN, "0" is always
read out.
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5.6.
Notes on Pins with the A/D Converter Function
Notes on pins with the A/D converter function are shown below.
When using a pin with the A/D converter function to perform a different function (digital port, peripheral function),
set the relevant bit of the A/D converter analog input enable register (ADER) to "Analog input disable" in advance. In
this case an A/D conversion should not be done on this analog input, because the digital inputs of this port pin are
fixed at "0" during A/D conversion. For information on the setting method, see "CHAPTER: 12-bit A/D
CONVERTER". If analog input is enabled, inputs from ports and from peripheral functions are fixed at "0" and
outputs are fixed at Hi-Z regardless of the port function register (PFR00 to PFR29) and extended port function
register (EPFR00 to EPFR111) settings.
5.7.
Setting when Using the Base Timer TIOA1 Pin
Setting when using the base timer TIOA1 pin is shown below.
If the base timer TIOA1 pin is to be used, it must be set for input for base timer I/O mode 1 and set for output for all
cases other than base timer I/O mode 1. If the base timer TIOA1 pin is to be used, it must be set for peripheral input
for base timer I/O mode 1 (see "5.1.2 Peripheral Input Assignment") and set for peripheral output for all cases other
than base timer I/O mode 1 (see "5.1.3 Peripheral Output Assignment").
5.8.
Key Code Register Function Settings
Setting when using the Key Code Register is shown.
The following settings are necessary for the key code register (KEYCDR) in order to write to the key code target
register.
Set KEY1+KEY0+Access Size (SIZE)+Access address (RADR[12:0]) to the key code register using
half-word.
Write (KEY1, KEY0) continuously according to the order (0, 0), (0, 1), (1, 0), and (1, 1). Set the address and
access size to the same value four times when (KEY1, KEY0) is written four times.
The following is a flow chart.
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Figure 5-8 Key Code Flow Chart
Start
KEYCDR
Written value
KEY[1:0]
00
SIZE
Access size
RADR[12:0]
Access address lower 13 bits
KEYCDR
Written value
KEY[1:0]
01
SIZE
Access size
RADR[12:0]
Access address lower 13 bits
KEYCDR
Written value
KEY[1:0]
10
SIZE
Access size
RADR[12:0]
Access address lower 13 bits
KEYCDR
Written value
KEY[1:0]
11
SIZE
Access size
RADR[12:0]
Access address lower 13 bits
Write to address set by RADR (lower 13 bits match) with the access size set by SIZE
End
If the following conditions apply, the key code will not be released and writing will not be executed to the target
register. In this case, it is necessary to set the key code register again from the beginning.
When writing order for (KEY1, KEY0) is different
When the data written to the SIZE bit is changed in the middle
When the data written to the RADR bit is changed in the middle
When the access size written to the SIZE bit is different from the size when accessing the actual target register
When the address (lower 13 bits) written to the RADR bit is different from the address (lower 13 bits) when
accessing the actual target register
When the key code register and register related to the port are read while writing to the key code register
Notes:
The key code setting might be canceled by DMA transfer. Read the value written in the object register, and confirm
whether the value has been changed.
While debugging by the on-chip debugger (OCD), the key code setting is canceled when the break function is
executed during the key code setting.
The DDR, PFR, EPFR, PPER, PILR, PORTEN, ADER, and DACR are the target key code registers. It is necessary
to set the key code in order to execute writing.
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Chapter 12: I/O Ports
5.9.
Operation at Wake Up from Power Shutdown
The operation at wake up from the power shutdown is shown below.
When PMUCTLR:IOCTMD bit is set, the I/O state is kept during the wake up sequence from the power shutdown.
The maintenance of the I/O state continues until PMUCTLR:IOCT is set.
When PMUCTLR:IOCTMD bit is cleared, maintenance of the I/O state is kept during the wake-up from power
shutdown. After completion of wake-up, this state shall be canceled and the register setting of the I/O port shall be
effective.
On waking up from power shutdown, there is a case that the maintenance of the I/O latch is not released.
After waking up from power shutdown, PMUCTLR.IOCT bit must be written "1" for releasing the maintenance of
I/O.
5.10. Notes on switching the I/O port function
Notes on switching the I/O port function are shown below.
When I/O port is switched from port function to resource or from resource to port function, the value of PDR may be
output momentarily.
It happens if port function is changed from "input to output" or "output to input" at the time of switching.
If this output may cause a problem for the system, please write a value to PDR in advance at a level that will not
cause a problem.
5.11. Input blocked when specific peripheral functions are used
A note regarding blocked input when specific peripheral functions are used is shown below.
When a pin is used as the A/D function and the state of the pin is read, "0" is always read.
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Chapter 13: Interrupt Control (Interrupt Controller)
This chapter explains the interrupt control (interrupt controller).
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
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Chapter 13: Interrupt Control (Interrupt Controller)
1. Overview
This section explains overview the of the interrupt control (interrupt controller).
The interrupt controller performs arbitration of interrupt requests.
2. Features
This section explains features of the interrupt control (interrupt controller).
This module is composed of the following parts.
ICR register
Interrupt priority determination circuit
Interrupt level and interrupt vector generation circuit
This module has the following functions.
Detecting NMI requests and peripheral interrupt requests
Priority determination (by level and interrupt vector)
Transmitting the interrupt level of the factor with the highest priority to the CPU
Transmitting the interrupt vector number of the factor with the highest priority to the CPU
Generating wakeup requests by NMI / interrupts that occur with a level other than "11111"
3. Configuration
This section explains the configuration of the interrupt control (interrupt controller).
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Chapter 13: Interrupt Control (Interrupt Controller)
Figure 3-1 Block Diagram
ICR00
Bus access
5
5
ICR01
5
Interrupt level
Interrupt level
and interrupt vector
determination and
generation circuit
5
Interrupt
vector number
ICR47
5
Wakeup
5
48
Peripheral interrupt
*
* : NMI or (XBS RAM double bit error generation) or (Backup RAM double bit error generation)
or (AHB RAM double bit error generation) or TPU violation or Error generation at internal bus diagnosis.
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Chapter 13: Interrupt Control (Interrupt Controller)
4. Registers
This section explains the registers of the interrupt control (interrupt controller).
Table 4-1 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
0x0440
ICR00
ICR01
ICR02
ICR03
0x0444
ICR04
ICR05
ICR06
ICR07
0x0448
ICR08
ICR09
ICR10
ICR11
0x044C
ICR12
ICR13
ICR14
ICR15
0x0450
ICR16
ICR17
ICR18
ICR19
0x0454
ICR20
ICR21
ICR22
ICR23
0x0458
ICR24
ICR25
ICR26
ICR27
0x045C
ICR28
ICR29
ICR30
ICR31
0x0460
ICR32
ICR33
ICR34
ICR35
0x0464
ICR36
ICR37
ICR38
ICR39
0x0468
ICR40
ICR41
ICR42
ICR43
0x046C
ICR44
ICR45
ICR46
ICR47
Interrupt control registers 00 to 47
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Chapter 13: Interrupt Control (Interrupt Controller)
4.1.
Interrupt Control Registers 00 to 47 : ICR00 to ICR47
(Interrupt Control Register 00 to 47)
The bit configuration of the interrupt control registers 00 to 47 is shown below.
One register is provided for each interrupt input to set the level for the corresponding interrupt request.
ICR00 to ICR47 : Address 0440H to 046FH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
1
Attribute R1,WX
bit1
bit0
IL[4:0]
1
1
1
1
1
1
1
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
[bit4 to bit0] IL[4:0] (Interrupt Level control)
The interrupt level setting bits specify the interrupt level for the corresponding interrupt request. An interrupt request
is masked in the CPU if the interrupt level set in these registers is greater than or equal to the level mask value in the
ILM register of the CPU. These bits are initialized to "5’b11111" on reset.
The correspondence between the configurable interrupt level settings bits and the interrupt levels is shown below.
IL[4:0]
Interrupt level
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
16
17
18
19
20
21
22
23
24
25
26
27
28
29
11110
30
11111
31
IL4 is fixed at 1 Writing has no effect.
↑
|
|
|
|
|
|
|
|
|
|
|
|
↓
Configurable highest level
(High)
(Low)
Interrupts disabled
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Chapter 13: Interrupt Control (Interrupt Controller)
5. Operation
This section explains the operation of the interrupt control (interrupt controller).
5.1. Setting
5.2. Starting
5.3. Determining Priorities
5.4. Recovering From Stop Mode
5.5. Recovering From Standby Mode (Power shutdown)
5.1.
Setting
This section explains the setting of the interrupt control (interrupt controller).
1. Configure the ICR register of the interrupt vector number corresponding to the peripheral for which you want to
generate the interrupt.
2. Configure the peripheral where you want to generate the interrupt. (Configure interrupt output as enabled on the
peripheral.)
5.2.
Starting
This section explains the starting of the interrupt control (interrupt controller).
Start the configured peripheral.
5.3.
Determining Priorities
The determining priorities are shown below.
This module selects the highest priority interrupt among interrupt factors that occur simultaneously and outputs the
interrupt level and interrupt vector number for the interrupt factors to the CPU.
The criteria for determining the priority of interrupt factors are as follows.
1.
2.
NMI
Factors that meet the following conditions
If the value of the interrupt level is not 31 (5’b11111). (31 indicates interrupts disabled)
The factors where the value of the interrupt level is the smallest.
When the interrupt level is the same (except for 31), the factors that has the smallest interrupt vector number
from amongst these.
If no interrupt factors is selected by the above criteria, 31 (5’b11111) is output as the interrupt level. The interrupt
vector number at this time is undefined.
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5.4.
Recovering From Stop Mode
The recovering from stop mode is shown below.
The function for using an interrupt request to recover from stop mode is performed by this module. If an interrupt
request (the interrupt level is anything other than "5’b11111") is generated from a peripheral (including NMI), a
request is generated to the clock control unit to recover from stop mode.
As the interrupt priority judgment unit restarts operation once the clock supply starts after recovery from stop mode,
the CPU is able to execute instructions until the interrupt priority judgment unit produces a result.
For interrupts that are not used as sources for recovering from stop mode, set the interrupt level of the corresponding
interrupt control registers (ICR00 to ICR47) to "5’b11111" (interrupts disabled).
5.5.
Recovering From Standby Mode (Power shutdown)
The recovering from standby mode (Power shutdown) is show below.
When the interrupt level is higher than ICR=0x1F (interrupt disable) and the standby return factor is more effective in
the state that the interrupt factor has been generated, the state cannot change to the power shutdown state. The
instruction execution is continued as it is.
When the interrupt level is at ICR=0x1F (interrupt disable) and there is a state in which an interrupt factor is
generated, this does not result in a standby return factor. Thus, even though the state once changes to the power
shutdown state, it returns immediately after completion of the power shutdown return sequence because the state has
the power shutdown return factor. (It is executed from the reset vector.)
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Chapter 14: External Interrupt Input
This chapter explains the external interrupt input.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Setting
7.
Q&A
8.
Notes
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Chapter 14: External Interrupt Input
1. Overview
This section explains the overview of the external interrupt input.
Interrupt request input from external interrupt input pins (INT0 to INT23).
2. Features
This section explains features of the external interrupt input.
Twenty-four types of external interrupt input pins (INT0 to INT23)
Interrupt detection factors:4 types: ("L" level, "H" level, rising edge, and falling edge)
3. Configuration
This section explains the configuration of the external interrupt input.
Figure 3-1 Block Diagram
Detection circuit
INTx external pin
Set
Interrupt
EIRR
Clear
ELVR
Cleared by
writing zero
ENIR
To I/O port controller
(When external
interrupts are enabled,
the INTx pins prevent
automatic port blocking
in standby mode.)
Bus access
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Chapter 14: External Interrupt Input
4. Registers
This section explains registers of the external interrupt input.
List of External Pins
External pins (INT)
460
Channel
Base_addr
MB91F52xR,
MB91F52xU
MB91F52xM,
MB91F52xY
0
0x0550
INT0_0
INT0_0
1
0x0550
INT1_0/INT1_1
INT1_0/INT1_1
2
0x0550
INT2_0/INT2_1
INT2_0/INT2_1
3
0x0550
INT3_0/INT3_1
INT3_0/INT3_1
4
0x0550
INT4_0/INT4_1
INT4_0/INT4_1
5
0x0550
INT5_0
INT5_0
6
0x0550
INT6_0
INT6_0
7
0x0550
INT7_0/INT7_1
INT7_0/INT7_1
8
0x0554
INT8_0
INT8_0
9
0x0554
INT9_0/INT9_1
INT9_0/ INT9_1
10
0x0554
INT10_0
INT10_0
11
0x0554
INT11_0
INT11_0
12
0x0554
INT12_0
INT12_0
13
0x0554
INT13_0/INT13_1
INT13_0/INT13_1
14
0x0554
INT14_0/INT14_1
INT14_0/INT14_1
15
0x0554
INT15_0
INT15_0
16
0x0540
−
INT16_0/INT16_1
17
0x0540
−
INT17_0/INT17_1
18
0x0540
−
INT18_0
19
0x0540
−
INT19_0
20
0x0540
−
INT20_0
21
0x0540
−
INT21_0
22
0x0540
−
INT22_0
23
0x0540
−
INT23_0
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Table 4-1 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
0x0550
EIRR0
ENIR0
ELVR0
External interrupt factor register 0
External interrupt enable register 0
External interrupt request level register 0
0x0554
EIRR1
ENIR1
ELVR1
External interrupt factor register 1
External interrupt enable register 1
External interrupt request level register 1
0x0540
EIRR2
ENIR2
ELVR2
External interrupt factor register 2
External interrupt enable register 2
External interrupt request level register 2
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Chapter 14: External Interrupt Input
4.1.
External Interrupt Factor Register 0/1/2 :
EIRR0/EIRR1/EIRR2 (External Interrupt Request Register
0/1/2)
The bit configuration of external interrupt factor register 0/1/2 (EIRR0/EIRR1/EIRR2) is shown below.
This register holds information that an external interrupt factor has been generated.
EIRR0 : Address 0550H (Access: Byte, Half-word, Word)
EIRR1 : Address 0554H (Access: Byte, Half-word, Word)
EIRR2 : Address 0540H (Access: Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
X
X
X
X
X
X
X
X
Attribute R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W
[bit7 to bit0] ER7 to ER0 (External interrupt Request7 to 0) : External interrupt request bits
Flags to indicate that there is an interrupt request by INT external pin input. Writing "0" will clear it.
ERn
Meaning
Read
Write
0
No external interrupt request
Clear
1
External interrupt request exists
Does not influence operation
Notes:
EIRR0:ER0 corresponds to INT0 pin, EIRR0:ER1 to INT1 pin, ..., EIRR0:ER7 to INT7 pin, EIRR1:ER0 to INT8
pin, ..., EIRR1:ER7 to INT15 pin, EIRR2:ER0 to INT16 pin, ..., EIRR2:ER7 to INT23 pin.
Writing "1" to these bits is invalid.
The values read with read-modify-write (RMW) instructions will always be "1".
When external interrupt detection condition is at "L" level or "H" level, the corresponding bit will be set again if
the external interrupt pin input is at an active level after clearing each bit in the EIRR register.
The factor bit in the interrupt factor register may be set by changing interrupt request level register. Initialize the
interrupt factor register after changing the interrupt request level register.
The value after resetting this register depends on the pin state after the reset.
This register will be initialized by all reset factors except recovery from standby (power shutdown) when
PMUCTLR:IOCTMD=1.
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Chapter 14: External Interrupt Input
4.2.
External Interrupt Enable Register 0/1/2 :
ENIR0/ENIR1/ENIR2 (ENable Interrupt request Register
0/1/2)
The bit configuration of external interrupt enable register 0/1/2 (ENIR0/ENIR1/ENIR2) is shown below.
This register enables external interrupt inputs.
ENIR0 : Address 0551H (Access: Byte, Half-word, Word)
ENIR1 : Address 0555H (Access: Byte, Half-word, Word)
ENIR2 : Address 0541H (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] EN7 to EN0 (interrupt ENable) : External interrupt enable bits
These bits perform mask controls of interrupt requests from external pin INT inputs.
ENn
Operations at the detection of an external pin
0
Interrupt request mask. Holds interrupt requests but does not output them.
(initial value)
1
Interrupt request enabled. Enables interrupt requests.
Notes:
ENIR0:EN0 corresponds to INT0 pin, ENIR0:EN1 to INT1 pin, ..., ENIR0:EN7 to INT7 pin, ENIR1:EN0 to INT8
pin, ..., ENIR1:EN7 to INT15 pin, ENIR2:ER0 to INT16 pin, ..., ENIR2:ER7 to INT23 pin.
This register will be initialized by all reset factors except recovery from standby (power shutdown) when
PMUCTLR:IOCTMD=1.
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Chapter 14: External Interrupt Input
4.3.
External Interrupt Request Level Register 0/1/2 :
ELVR0/ELVR1/ELVR2 (External interrupt LeVel Register
0/1/2)
The bit configuration of external interrupt request level register 0/1/2 (ELVR0/ELVR1/ELVR2) is shown
below.
This register selects detection conditions for external interrupt requests.
ELVR0 : Address 0552H (Access: Byte, Half-word, Word)
ELVR1 : Address 0556H (Access: Byte, Half-word, Word)
ELVR2 : Address 0542H (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
Attribute
Initial value
Attribute
[bit15 to bit1] LB7 to LB0 (Level select B) : Level select B
[bit14 to bit0] LA7 to LA0 (Level select A) : Level select A
These bits select detection conditions for external interrupt requests. Combination of 2 bits, LA bit and LB bit will be
used.
LBn
LAn
Detection conditions
0
0
"L" level detection(Initial value)
0
1
"H" level detection
1
0
Rising edge detection
1
1
Falling edge detection
When the request input is a level (LAn, LBn ="00" or "01"), the corresponding bit (ERn) will turn back to "1" if INTn
pin input is still in the effective levels after setting the external interrupt request bit (ERn) to "0".
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Chapter 14: External Interrupt Input
Notes:
ELVR0:LA/LB0 corresponds to INT0 pin, ELVR0:LA/LB1 to INT1 pin, ..., ELVR0:LA/LB7 to INT7 pin,
ELVR1:LA/LB0 to INT8 pin, ..., ELVR1:LA/LB7 to INT15 pin, ELVR2:LA/LB0 to INT16 pin, ...,
ELVR2:LA/LB7 to INT23 pin.
The factor bit in the interrupt factor register may be set by changing the interrupt request level register. Initialize
the interrupt factor register after changing the interrupt request level register.
This register will be initialized by all reset factors except recovery from standby (power shutdown) when
PMUCTLR:IOCTMD=1.
5. Operation
This section explains the operation of the external interrupt input.
Figure 5-1 Operation Diagram
Edge/level detection
(2)
(1)
INT ("H")
("L")
(1)
(2)
(2)
INT (rising)
(1)
(falling)
(1)
(2)
Clears with the software
(3)
Interrupt request (ER)
(4)
(1)
(2)
(3)
(4)
External interrupt signal (INT) input
Detects interrupt signals (level/edge).
Generates interrupt requests.
Clears interrupt requests with the software.
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Chapter 14: External Interrupt Input
Figure 5-2 Operation of External Interrupt
External interrupt
Interrupt controller
CPU
Resource request
ELVR
ICRyy
EIRR
ENIR
IL
CMP
ICRxx
CMP
ILM
Factor
1. Operation of external interrupt
This module generates the interrupt request signal to the interrupt controller when a request set in the ELVR
register is input in the corresponding pin after setting a request level and the enable register. The corresponding
interrupt will be generated when the interrupt from this resource was found to have the highest priority in the
result for examining the priority in interrupts concurrently occurred in the interrupt controller.
2. Transition to standby mode
Channels not to be used should be moved to disable state before letting them go into the standby mode. External
pins enter an input blocked state at standby mode, but external pins of external interrupt enabled channels enter an
input enabled state.
3. Setting procedure of external interrupts
When setting registers which reside in the external interrupt unit, follow the steps shown below:
(1)
(2)
(3)
(4)
(5)
Disable the corresponding bit for the enable register.
Set the corresponding bit for the request level setting register.
Read the request level register.
Clear the corresponding bit for the factor register.
Enable the corresponding bit for the enable register.
(Note that concurrent writes of 16-bit data are allowed in step (4) and (5).)
The enable register must be disabled before you can set the registers in this module. The factor register must be
cleared before you can set the enable register to enable state.
This has to be done to avoid generating erroneous interrupt factors at the time of setting register or in interrupt
enable state.
4. External interrupt factor
Requests to the interrupt controller will continue to be active although a request input from outside is canceled,
because there is an internal factor retention circuit.
To cancel requests going toward the interrupt controller, the factor register should be cleared.
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Chapter 14: External Interrupt Input
Figure 5-3 Clearing the Factor Retention Circuit and Interrupt Factor and Interrupt
Request to Interrupt Controller in Interrupt Enable State
Clearing the factor retention circuit
Interrupt
input
Level/edge
detection
Factor F/F
(factor retention circuit)
Enable gate
Interrupt
controller
Factors continue to be maintained unless cleared
Interrupt factors and interrupt requests to the interrupt controller when interrupts permitted
H level
Interrupt input
Interrupt request to
interrupt controller
Made inactive by clearing the factor F/F
6. Setting
This section explains settings of the external interrupt input.
Table 6-1 Necessary Settings for Using External Interrupts
Settings
Setting register
Setting method
Detection level settings
External interrupt request level setting register
(ELVR0, ELVR1, and ELVR2)
See "■ About
Detection Levels and
Their Setting
Procedures"
in "7. Q&A".
Specifying external pins to be
used for input.
See "CHAPTER: I/O PORTS".
See "CHAPTER: I/O
PORTS".
External interrupt
An input from the external pin
→ Input signal to pins INT0 to INT23
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Chapter 14: External Interrupt Input
7. Q&A
This section explains Q&A of the external interrupt input.
About Detection Levels and Their Setting Procedures
Four levels: ("L" level, "H" level, rising edge, falling edge)
Set the detection level bits as follows: (ELVRy:LBn, LAn) (n=0 to 7, y=0 to 2).
Operation modes
Detection level bits (LBn, LAn) n=0 to 7
To perform "L" level detection
Set "00".
To perform "H" level detection
Set "01".
To perform rising edge detection
Set "10".
To perform falling edge detection
Set "11".
How to Make External Pins to Use for Input
See "CHAPTER: I/O PORTS".
About Interrupt Related Registers
See "CHAPTER: INTERRUPT CONTROL (INTERRUPT CONTROLLER)".
About Interrupt Types
Interrupt factors are only for external interrupts. There are no select bits.
How to Enable/Disable/Clear Interrupts
Interrupt request enable flag, interrupt request flag
Interrupt enable setting is done by the interrupt enable bit (ENIR0/ENIR1/ENIR2:EN0 to EN7).
Operation
Interrupt enable bit (ENn)
To disable interrupt requests
Set "0".
To enable interrupt requests
Set "1".
Interrupt request clear is done by the interrupt request bit (EIRR0/EIRR1/EIRR2:ER0 to ER7).
Operation
To clear interrupt requests
468
Interrupt request bit (ERn)
Write "0".
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Chapter 14: External Interrupt Input
8. Notes
This section explains the notes of the external interrupt input.
The external interrupt input register is not initialized when returned from the standby clock mode (power shutdown)
and the standby stop mode (power shutdown) when PMUCTLR:IOCTMD=1. To maintain the status before it returns
and the status under return, set the device in the status of the I/O maintenance by setting PMUCTLR.IOCTMD before
setting standby. And, release the I/O maintenance by setting PMUCTLR.IOCT after the I/O port is set. See
"CHAPTER: POWER CONSUMPTION CONTROL" for the details of the PMUCTLR register.
[MB91F52xxxC/MB91F52xxxE] Moreover, the internal reset is issued at the return from the standby watch mode
(power shutdown) and the standby stop mode (power shutdown) when PMUCTLR:IOCTMD=1. Therefore, only the
reset causes (power-on reset, internal low-voltage detection, and simultaneous assertion of RSTX and NMIX) are
recognized. At this time, the register of the external interrupt input is not initialized. If the flag for RSTX reset or the
flag for the external low-voltage detection reset is set after the start-up, the user needs to initialize the external
interrupt input register before using it.
[MB91F52xxxD] Moreover, the internal reset is issued at the return from the standby watch mode (power shutdown)
and the standby stop mode (power shutdown) when PMUCTLR:IOCTMD=1. Therefore, only the reset causes
(power-on reset, internal low-voltage detection, and assertion of RSTX) are recognized. At this time, the register of
the external interrupt input is not initialized. If the flag for RSTX reset or the flag for the external low-voltage
detection reset is set after the start-up, the user needs to initialize the external interrupt input register before using it.
Note:
■ Note for using the external interrupt as source for recovering from the watch mode with power-shutdown
Set the interrupt levels that are used as sources for recovering from the watch mode with power-shutdown to ‘31’,
before CPU state changes to the watch mode with power-shutdown. And don’t use NMIX pin as source for
recovering from the watch mode with power-shutdown.
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Chapter 15: NMI Input
This chapter explains the NMI input.
1.
Overview
2.
Features
3.
Configuration
4.
Register
5.
Operation
6.
Usage Example
Code : FR81S10_NMI-1v1-91528-3-E
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Chapter 15: NMI Input
1. Overview
This section explains the overview of the NMI input.
NMI (Non Maskable Interrupt) is the non-maskable interrupt signal that is entered from the NMIX pin. The NMI can
be used as a source for recovering from stop mode.
2. Features
This section explains features of the NMI input
Can be used in stop mode (Power-shutdown is included) and watch mode. Don’t use NMI input as source for
recovering from the watch mode (Power-shutdown).
3. Configuration
This section explains the configuration of the NMI input.
Figure 3-1 Block Diagram
NMIX
external pin
Falling edge
detection
Set
NMI flag
NMI interrupt
request
Clear
NMI acceptance
or reset
Watch/Stop mode
4. Register
This section explains the register of the NMI input.
This function has no register.
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Chapter 15: NMI Input
5. Operation
This section explains the operation of the NMI input.
NMI Interrupt Level
The NMI has the highest level among the user interrupts and cannot be masked. As an exception, the NMI is masked
after reset until the ILM is set by the CPU.
NMI External Pin
In stop mode, this pin detects the L level, and at other times it detects the falling edge.
Interrupt Request Output
The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an interrupt for the
NMI itself is accepted or reset occurs. The NMI flag cannot be read or written.
Read IRPR15H register to judge whether the NMI is caused by the NMIX external pin or the other factors. For details
of this register, see "INTERRUPT REQUEST BATCH READ".
Recovering From Stop Mode
When switching to stop mode, if an "L" level is input to the NMIX, an NMI request is output to the interrupt
controller and the CPU recovers from stop mode. If the CPU switches to stop mode without returning the input level
of the NMIX pin to the "H" level after the NMI processing routine has finished in normal mode (not stop mode), the
CPU recovers immediately after switching to stop mode (see [2] in Figure 5-1). Similarly, the power-shutdown will
not be controlled when the status changes to the stop mode (power-shutdown) without setting the NMIX pin to the
"H" level. Return the input level of the NMIX pin to the "H" level before entering stop mode so that the input level of
the NMIX pin is set to the "L" level in stop mode.
An internal reset is issued at the return from standby mode (power-shutdown), and no NMI request is accepted.
Figure 5-1 Recovering from Stop Mode
Operation status
Recovery from stop at
"L" level after falling edge
NMIX input
NMIX input
Operation status
NMI processing
routine
NMIX input
"L" level detected and recover from stop
mode soon after entering stop mode
Note:
The watch mode and the watch mode (power-shutdown) are similarly controlled.
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Chapter 15: NMI Input
6. Usage Example
This section explains a usage example of the NMI input.
This section gives an example of using the NMI function.
Figure 6-1 Usage Example
RSTX
Master chip
MCU
NMIX
UART, etc.
NMI usage example
• The recovery request from sleep or standby
• Urgent communication request
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Chapter 16: Delay Interrupt
This chapter explains the delay interrupt.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Restrictions
Code : FR81S10_DINT-1v1-91528-2-E
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Chapter 16: Delay Interrupt
1. Overview
This section explains the overview of the delay interrupt.
The delay interrupt is a function for generating interrupts for the OS (operating system) to switch between tasks.
This function allows interrupt requests to the CPU to be generated and cancelled by software.
2. Features
This section explains features of the delay interrupt.
The delay interrupt can be generated by writing to a register.
3. Configuration
This section explains the configuration of the delay interrupt.
Figure 3-1 Block Diagram
Bus access
Delay interrupt
Interrupt request
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Chapter 16: Delay Interrupt
4. Registers
This section explains registers of the delay interrupt.
Registers
Address
Register function
0x0044
+0
+1
+2
+3
DICR
Reserved
Reserved
Reserved
Delay Interrupt Control
Register
Delay Interrupt Control Register : DICR (Delay Interrupt Control Register)
This register controls the delay interrupts.
DICR : Address 0044H (Access: Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
bit0
DLYI
Initial value
1
1
1
1
1
1
1
0
Attribute
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
[bit0] DLYI (DeLaY Interrupt enable) : Delay Interrupt Enable Bit
This bit generates and clears the delay interrupt factor.
DLYI
Description
"0" write
Clears the delay interrupt factor
"1" write
Generates the delay interrupt factor
5. Operation
This section explains the operation description of the delay interrupt.
The delay interrupts are used to generate interrupts for task switching. Using this function allows interrupt requests to
the CPU to be generated and cancelled by software.
Interrupt Vector Number
The delay interrupts are allocated to the interrupt sources with the highest interrupt vector number.
In this core, delay interrupts are allocated to interrupt vector number 63 (0x3F).
DLYI Bit of the DICR Register
Writing "1" to this bit generates a delay interrupt factor. Writing "0" to this bit cancels the delay interrupt source.
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Chapter 16: Delay Interrupt
This bit functions like a standard interrupt factor flag and should be cleared in the interrupt routine at the same time as
when switching a task.
6. Restrictions
This section explains restrictions of the delay interrupt.
Do not use delay interrupts for DMA transfer requests.
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Chapter 17: Interrupt Request Batch Read
This chapter explains the overview, features, and configuration of the interrupt request batch read.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
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Chapter 17: Interrupt Request Batch Read
1. Overview
This section explains the overview of the interrupt request batch read.
This module can read multiple interrupt requests assigned to one interrupt vector number in a batch. Interrupt requests
that have been generated can be identified by using the bit search instruction of the FR81-family CPU.
2. Features
This section shows features of the interrupt request batch read.
Using this module, you can easily check whether interrupts have been generated.
3. Configuration
This section shows the configuration of the interrupt request batch read.
Figure 3-1 Block Diagram
From Peripheral
Interrupt request
Bus access
:
:
:
Interrupt
controller
:
Interrupt request
batch read
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Chapter 17: Interrupt Request Batch Read
4. Registers
This section explains the registers of the interrupt request batch read.
Table 4-1 Registers Map
Registers
Address
+0
+1
+2
+3
Register function
0x0418
IRPR0H
IRPR0L
IRPR1H
Interrupt request batch read register 0 upper-order (#18)
Interrupt request batch read register 0 lower-order (#19)
IRPR1L
Interrupt request batch read register 1 upper-order (#20)
Interrupt request batch read register 1 lower-order (#22)
0x041C
Reserved
Reserved
IRPR3H
IRPR3L
IRPR5H
Interrupt request batch read register 4 upper-order (#42)
Interrupt request batch read register 4 lower-order (#43)
IRPR5L
Interrupt request batch read register 5 upper-order (#44)
Interrupt request batch read register 5 lower-order (#36)
IRPR7H
Interrupt request batch read register 6 upper-order (#45)
Interrupt request batch read register 6 lower-order (#46)
IRPR7L
Interrupt request batch read register 7 upper-order (#47)
Interrupt request batch read register 7 lower-order (#49)
IRPR9H
Interrupt request batch read register 8 upper-order (#50)
Interrupt request batch read register 8 lower-order (#51)
IRPR9L
Interrupt request batch read register 9 upper-order (#52)
Interrupt request batch read register 9 lower-order (#53)
0x0420
0x0424
IRPR4H
IRPR6H
IRPR4L
IRPR6L
IRPR8L
Interrupt request batch read register 3 upper-order (#40)
Interrupt request batch read register 3 lower-order (#41)
0x0428
IRPR8H
0x042C
Interrupt request batch read register 10 upper-order (#54)
Interrupt request batch read register 10 lower-order (#55)
IRPR10H IRPR10L IRPR11H IRPR11L
Interrupt request batch read register 11 upper-order (#56)
Interrupt request batch read register 11 lower-order (#57)
0x0430
Interrupt request batch read register 12 upper-order (#58)
Interrupt request batch read register 12 lower-order (#59)
IRPR12H IRPR12L IRPR13H IRPR13L
Interrupt request batch read register 13 upper-order (#60)
Interrupt request batch read register 13 lower-order (#61)
0x0434
Interrupt request batch read register 14 upper-order (#62)
Interrupt request batch read register 14 lower-order (#62)
IRPR14H IRPR14L IRPR15H IRPR15L
Interrupt request batch read register 15 upper-order (#15)
Interrupt request batch read register 15 lower-order (#35)
Interrupt request batch read register 16 upper-order (#31)
Interrupt request batch read register 16 lower-order (#32)
0x043C IRPR16H IRPR16L IRPR17H IRPR17L
Interrupt request batch read register 17 upper-order (#33)
Interrupt request batch read register 17 lower-order (#34)
#nn : Interrupt vector number (decimal)
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4.1.
Interrupt Request Batch Read Register 0 upper-order :
IRPR0H (Interrupt Request Peripheral Read register 0H)
The bit configuration of the interrupt request batch read register 0 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #18)
IRPR0H : Address 0418H (Access : Byte, Half-word, Word)
bit7
bit6
RTIR0
RTIR1
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] RTIR0 (Reload Timer Interrupt Request 0) : Reload timer 0 interrupt request
[bit6] RTIR1 (Reload Timer Interrupt Request 1) : Reload timer 1 interrupt request
Read value of each bit
4.2.
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
Interrupt Request Batch Read Register 0 lower-order :
IRPR0L (Interrupt Request Peripheral Read register 0L)
The bit configuration of the interrupt request batch read register 0 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #19)
IRPR0L : Address 0419H (Access : Byte, Half-word, Word)
bit7
bit6
RTIR2
RTIR3
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] RTIR2 (Reload Timer Interrupt Request 2) : Reload timer 2 interrupt request
[bit6] RTIR3 (Reload Timer Interrupt Request 3) : Reload Timer 3 Interrupt Request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.3.
Interrupt Request Batch Read Register 1 upper-order :
IRPR1H (Interrupt Request Peripheral Read register 1H)
The bit configuration of the interrupt request batch read register 1 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #20)
IRPR1H : Address 041AH (Access : Byte, Half-word, Word)
bit7
bit6
RXIR0
ISIR0
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] RXIR0 (multifunction serial interface RX Interrupt Request 0) : Multi-function serial interface ch.0
reception completion interrupt request
[bit6] ISIR0 (multifunction serial Interface Status Interrupt Request 0) : Multi-function serial
interface ch.0 status interrupt request
Read value of each bit
4.4.
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
Interrupt Request Batch Read Register 1 lower-order :
IRPR1L (Interrupt Request Peripheral Read register 1L)
The bit configuration of the interrupt request batch read register 1 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #22)
IRPR1L : Address 041BH (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
RXIR1
ISIR1
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] RXIR1 (multifunction serial interface RX Interrupt Request 1) : Multi-function serial interface ch.1
reception completion interrupt request
[bit6] ISIR1 (multifunction serial Interface Status Interrupt Request 1) : Multi-function serial interface ch.1
status interrupt request
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Read value of each bit
4.5.
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
Interrupt Request Batch Read Register 3 upper-order :
IRPR3H (Interrupt Request Peripheral Read register 3H)
The bit configuration of the interrupt request batch read register 3 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #40)
IRPR3H : Address 041EH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
PPGIR0
PPGIR1
PPGIR10
PPGIR11
PPGIR20
PPGIR21
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
Initial value
Attribute
bit1
bit0
Reserved
[bit7] PPGIR0 (PPG Interrupt Request 0) : PPG0 interrupt request
[bit6] PPGIR1 (PPG Interrupt Request 1) : PPG1 interrupt request
[bit5] PPGIR10 (PPG Interrupt Request10) : PPG10 interrupt request
[bit4] PPGIR11 (PPG Interrupt Request 11) : PPG11 interrupt request
[bit3] PPGIR20 (PPG Interrupt Request 20) : PPG20 interrupt request
[bit2] PPGIR21 (PPG Interrupt Request 21) : PPG21 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.6.
Interrupt Request Batch Read Register 3 lower-order :
IRPR3L (Interrupt Request Peripheral Read register 3L)
The bit configuration of the interrupt request batch read register 3 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #41)
IRPR3L : Address 041FH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
PPGIR2
PPGIR3
PPGIR12
PPGIR13
PPGIR22
PPGIR23
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
Initial value
Attribute
bit1
bit0
Reserved
[bit7] PPGIR2 (PPG Interrupt Request 2) : PPG2 interrupt request
[bit6] PPGIR3 (PPG Interrupt Request 3) : PPG3 interrupt request
[bit5] PPGIR12 (PPG Interrupt Request 12) : PPG12 interrupt request
[bit4] PPGIR13 (PPG Interrupt Request 13) : PPG13 interrupt request
[bit3] PPGIR22 (PPG Interrupt Request 22) : PPG22 interrupt request
[bit2] PPGIR23 (PPG Interrupt Request 23) : PPG23 interrupt request
Read value of each bit
4.7.
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
Interrupt Request Batch Read Register 4 upper-order :
IRPR4H (Interrupt Request Peripheral Read register 4H)
The bit configuration of the interrupt request batch read register 4 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #42)
IRPR4H : Address 0420H (Access : Byte, Half-word, Word)
Initial value
Attribute
484
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PPGIR4
PPGIR5
PPGIR14
PPGIR15
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
Reserved
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[bit7] PPGIR4 (PPG Interrupt Request 4) : PPG4 interrupt request
[bit6] PPGIR5 (PPG Interrupt Request 5) : PPG5 interrupt request
[bit5] PPGIR14 (PPG Interrupt Request 14) : PPG14 interrupt request
[bit4] PPGIR15 (PPG Interrupt Request 15) : PPG15 interrupt request
Read value of each bit
4.8.
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
Interrupt Request Batch Read Register 4 lower-order :
IRPR4L (Interrupt Request Peripheral Read register 4L)
The bit configuration of the interrupt request batch read register 4 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #43)
IRPR4L : Address 0421H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
PPGIR6
PPGIR7
PPGIR16
PPGIR17
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit3
bit2
bit1
bit0
Reserved
[bit7] PPGIR6 (PPG Interrupt Request 6) : PPG6 interrupt request
[bit6] PPGIR7 (PPG Interrupt Request 7) : PPG7 interrupt request
[bit5] PPGIR16 (PPG Interrupt Request 16) : PPG16 interrupt request
[bit4] PPGIR17 (PPG Interrupt Request 17) : PPG17 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.9.
Interrupt Request Batch Read Register 5 upper-order :
IRPR5H (Interrupt Request Peripheral Read register 5H)
The bit configuration of the interrupt request batch read register 5 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #44)
IRPR5H : Address 0422H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
PPGIR8
PPGIR9
PPGIR18
PPGIR19
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit3
bit2
bit1
bit0
Reserved
[bit7] PPGIR8 (PPG Interrupt Request 8) : PPG8 interrupt request
[bit6] PPGIR9 (PPG Interrupt Request 9) : PPG9 interrupt request
[bit5] PPGIR18 (PPG Interrupt Request 18) : PPG18 interrupt request
[bit4] PPGIR19 (PPG Interrupt Request 19) : PPG19 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.10. Interrupt Request Batch Read Register 5 lower-order :
IRPR5L (Interrupt Request Peripheral Read register 5L)
The bit configuration of the interrupt request batch read register 5 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #36)
IRPR5L : Address 0423H (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CANIR2
UDCIR0
UDCIR1
CANIR5
UDCIR2
UDCIR3
GEAR_IR
Q
OVF_IR
Q
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit7] CANIR2 (CAN Interrupt Request 2) : CAN ch.2 interrupt request
[bit6] UDCIR0 (UpDown Counter Interrupt Request 0) : Up/Down counter ch.0 interrupt request
[bit5] UDCIR1 (UpDown Counter Interrupt Request 1) : Up/Down counter ch.1 interrupt request
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[bit4] CANIR5 (CAN Interrupt Request 5) : CAN ch.5 interrupt request
[bit3] UDCIR2 (UpDown Counter Interrupt Request 2) : Up/Down counter ch.2 interrupt request
[bit2] UDCIR3 (UpDown Counter Interrupt Request 3) : Up/Down counter ch.3 interrupt request
[bit1] GEAR_IRQ (PLL Gear Interrupt Request) : FlexRay PLL Gear Interrupt Request
[bit0] OVF_IRQ (Over Flow Interrupt Request) : FlexRay PLL alarm Interrupt Request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.11. Interrupt Request Batch Read Register 6 upper-order :
IRPR6H (Interrupt Request Peripheral Read register 6H)
The bit configuration of the interrupt request batch read register 6 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #45)
IRPR6H : Address 0424H (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
RXIR8
ISIR8
bit3
bit2
bit1
bit0
Reserved
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
[bit5] RXIR8 (multifunction serial interface RX Interrupt Request 8) : Multi-function serial interface ch.8
reception completion interrupt request
[bit4] ISIR8 (multifunction serial Inform Status Interrupt Request 8) : Multi-function serial interface ch.8 status
interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.12. Interrupt Request Batch Read Register 6 lower-order :
IRPR6L (Interrupt Request Peripheral Read register 6L)
The bit configuration of the interrupt request batch read register 6 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #46)
IRPR6L : Address 0425H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
MTIR
STIR
PTIR
TXIR8
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit3
bit2
bit1
bit0
Reserved
[bit7] MTIR (Main Timer Interrupt Request) : Main timer interrupt request
[bit6] STIR (Sub Timer Interrupt Request) : Sub timer interrupt request
[bit5] PTIR (PLL Timer Interrupt Request) : PLL timer interrupt request
[bit4] TXIR8 (multifunction serial TX Interrupt Request 8) : Multi-function serial interface ch.8 transmission
completion interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.13. Interrupt Request Batch Read Register 7 upper-order :
IRPR7H (Interrupt Request Peripheral Read register 7H)
The bit configuration of the interrupt request batch read register 7 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #47)
IRPR7H : Address 0426H (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
SUBIR
Reserved
RXIR9
ISIR9
0
0
0
0
0
0
0
0
R0,WX
R,WX
R0,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
Reserved
[bit6] SUBIR (SUB Interrupt Request) : Clock calibration (sub) interrupt request
[bit4] RXIR9 (multifunction serial RX Interrupt Request 9) : Multi-function serial interface ch.9 reception
completion interrupt request
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[bit3] ISIR9 (multifunction serial Inform Status Interrupt Request 9) : Multi-function serial interface ch.9 status
interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.14. Interrupt Request Batch Read Register 7 lower-order :
IRPR7L (Interrupt Request Peripheral Read register 7L)
The bit configuration of the interrupt request batch read register 7 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #49)
IRPR7L : Address 0427H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
CRIR
TXIR9
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R,WX
R,WX
[bit1] CRIR (CR clock calibration Interrupt Request) : Clock calibration (CR) interrupt request
[bit0] TXIR9 (multifunction serial TX Interrupt Request 9) : Multi-function serial interface ch.9 transmission
completion interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.15. Interrupt Request Batch Read Register 8 upper-order :
IRPR8H (Interrupt Request Peripheral Read register 8H)
The bit configuration of the interrupt request batch read register 8 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #50)
IRPR8H : Address 0428H (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
bit3
FRTIR4
bit2
bit1
bit0
Reserved
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
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[bit5] FRTIR4 (FRT Interrupt Request 4) : Free-run timer ch.4 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.16. Interrupt Request Batch Read Register 8 lower-order :
IRPR8L (Interrupt Request Peripheral Read register 8L)
The bit configuration of the interrupt request batch read register 8 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #51)
IRPR8L : Address 0429H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
FRTIR3
FRTIR5
0
0
0
0
0
R0,WX
R,WX
R,WX
R0,WX
R0,WX
Initial value
Attribute
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit6] FRTIR3 (FRT Interrupt Request 3) : Free-run timer ch.3 interrupt request
[bit5] FRTIR5 (FRT Interrupt Request 5) : Free-run timer ch.5 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.17. Interrupt Request Batch Read Register 9 upper-order :
IRPR9H (Interrupt Request Peripheral Read register 9H)
The bit configuration of the interrupt request batch read register 9 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #52)
IRPR9H : Address 042AH (Access : Byte, Half-word, Word)
Initial value
Attribute
490
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
ICUIR6
0
0
0
0
0
R0,WX
R,WX
R0,WX
R0,WX
R0,WX
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
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[bit6] ICUIR6 (ICU Interrupt Request 6) : Input capture ch.6 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.18. Interrupt Request Batch Read Register 9 lower-order :
IRPR9L (Interrupt Request Peripheral Read register 9L)
The bit configuration of the interrupt request batch read register 9 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #53)
IRPR9L : Address 042BH (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
ICUIR7
0
0
0
0
0
R0,WX
R,WX
R0,WX
R0,WX
R0,WX
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit6] ICUIR7 (ICU Interrupt Request 7) : Input capture ch.7 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.19. Interrupt Request Batch Read Register 10 upper-order :
IRPR10H (Interrupt Request Peripheral Read register 10H)
The bit configuration of the interrupt request batch read register 10 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #54)
IRPR10H : Address 042CH (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
ICUIR8
0
0
0
0
0
R0,WX
R,WX
R0,WX
R0,WX
R0,WX
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
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[bit6] ICUIR8 (ICU Interrupt Request 8) : Input capture ch.8 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.20. Interrupt Request Batch Read Register 10 lower-order :
IRPR10L (Interrupt Request Peripheral Read register 10L)
The bit configuration of the interrupt request batch read register 10 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #55)
IRPR10L : Address 042DH (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
ICUIR9
0
0
0
0
0
R0,WX
R,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit6] ICUIR9 (ICU Interrupt Request 9) : Input capture ch.9 interrupt request
Read value of each bit
492
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.21. Interrupt Request Batch Read Register 11 upper-order :
IRPR11H (Interrupt Request Peripheral Read register 11H)
The bit configuration of the interrupt request batch read register 11 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #56)
IRPR11H : Address 042EH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
ICUIR4
Initial value
Attribute
bit3
bit2
bit1
bit0
Reserved
0
0
0
0
0
0
0
0
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
[bit7] ICUIR4 (ICU Interrupt Request 4) : Input capture ch.4 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.22. Interrupt Request Batch Read Register 11 lower-order :
IRPR11L (Interrupt Request Peripheral Read register 11L)
The bit configuration of the interrupt request batch read register 11 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #57)
IRPR11L : Address 042FH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
ICUIR5
Initial value
Attribute
bit3
bit2
bit1
bit0
Reserved
0
0
0
0
0
0
0
0
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
[bit7] ICUIR5 (ICU Interrupt Request 5) : Input capture ch.5 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.23. Interrupt Request Batch Read Register 12 upper-order :
IRPR12H (Interrupt Request Peripheral Read register 12H)
The bit configuration of the interrupt request batch read register 12 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #58)
IRPR12H : Address 0430H (Access : Byte, Half-word, Word)
bit7
bit6
Reserved
Initial value
Attribute
bit5
bit4
bit3
bit2
OCUIR6
OCUIR7
OCUIR10
OCUIR11
bit1
bit0
Reserved
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R,WX
R,WX
R,WX
R,WX
R0,WX
R0,WX
[bit5] OCUIR6 (OCU Interrupt Request 6) : Output compare ch.6 interrupt request
[bit4] OCUIR7 (OCU Interrupt Request 7) : Output compare ch.7 interrupt request
[bit3] OCUIR10 (OCU Interrupt Request 10) : Output compare ch.10 interrupt request
[bit2] OCUIR11 (OCU Interrupt Request 11) : Output compare ch.11 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.24. Interrupt Request Batch Read Register 12 lower-order :
IRPR12L (Interrupt Request Peripheral Read register 12L)
The bit configuration of the interrupt request batch read register 12 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #59)
IRPR12L : Address 0431H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Reserved
Reserved
Reserved
OCUIR8
OCUIR9
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R,WX
R,WX
R0,WX
R0,WX
Initial value
Attribute
bit1
bit0
Reserved
[bit3] OCUIR8 (OCU Interrupt Request 8) : Output compare ch.8 interrupt request
[bit2] OCUIR9 (OCU Interrupt Request 9) : Output compare ch.9 interrupt request
Read value of each bit
494
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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4.25. Interrupt Request Batch Read Register 13 upper-order :
IRPR13H (Interrupt Request Peripheral Read register 13H)
The bit configuration of the interrupt request batch read register 13 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #60)
IRPR13H : Address 0432H (Access : Byte, Half-word, Word)
bit7
bit6
BT0IR0
BT0IR1
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] BT0IR0 (BT0 Interrupt Request 0) : Base timer ch.0 interrupt request 0
[bit6] BT0IR1 (BT0 Interrupt Request 1) : Base timer ch.0 interrupt request 1
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.26. Interrupt Request Batch Read Register 13 lower-order :
IRPR13L (Interrupt Request Peripheral Read register 13L)
The bit configuration of the interrupt request batch read register 13 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #61)
IRPR13L : Address 0433H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
BT1IR0
BT1IR1
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
Initial value
Attribute
bit2
bit1
bit0
Reserved
[bit7] BT1IR0 (BT1 Interrupt Request 0) : Base timer ch.1 interrupt request 0
[bit6] BT1IR1 (BT1 Interrupt Request 1) : Base timer ch.1 interrupt request 1
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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Chapter 17: Interrupt Request Batch Read
4.27. Interrupt Request Batch Read Register 14 upper-order :
IRPR14H (Interrupt Request Peripheral Read register 14H)
The bit configuration of the interrupt request batch read register 14 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #62)
IRPR14H : Address 0434H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
DMAC0IR DMAC1IR DMAC2IR DMAC3IR
Initial value
Attribute
bit3
bit2
bit1
bit0
DMAC4IR
DMAC5IR
DMAC6IR
DMAC7IR
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit7] DMAC0IR (DMAC 0 Interrupt Request) : DMAC ch.0 interrupt request
[bit6] DMAC1IR (DMAC 1 Interrupt Request) : DMAC ch.1 interrupt request
[bit5] DMAC2IR (DMAC 2 Interrupt Request) : DMAC ch.2 interrupt request
[bit4] DMAC3IR (DMAC 3 Interrupt Request) : DMAC ch.3 interrupt request
[bit3] DMAC4IR (DMAC 4 Interrupt Request) : DMAC ch.4 interrupt request
[bit2] DMAC5IR (DMAC 5 Interrupt Request) : DMAC ch.5 interrupt request
[bit1] DMAC6IR (DMAC 6 Interrupt Request) : DMAC ch.6 interrupt request
[bit0] DMAC7IR (DMAC 7 Interrupt Request) : DMAC ch.7 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.28. Interrupt Request Batch Read Register 14 lower-order :
IRPR14L (Interrupt Request Peripheral Read register 14L)
The bit configuration of the interrupt request batch read register 14 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #62)
IRPR14L : Address 0435H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DMAC8IR DMAC9IR DMAC10IR DMAC11IR DMAC12IR DMAC13IR DMAC14IR DMAC15IR
Initial value
Attribute
496
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
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Chapter 17: Interrupt Request Batch Read
[bit7] DMAC8IR (DMAC 8 Interrupt Request) : DMAC ch.8 interrupt request
[bit6] DMAC9IR (DMAC 9 Interrupt Request) : DMAC ch.9 interrupt request
[bit5] DMAC10IR (DMAC 10 Interrupt Request) : DMAC ch.10 interrupt request
[bit4] DMAC11IR (DMAC 11 Interrupt Request) : DMAC ch.11 interrupt request
[bit3] DMAC12IR (DMAC 12 Interrupt Request) : DMAC ch.12 interrupt request
[bit2] DMAC13IR (DMAC 13 Interrupt Request) : DMAC ch.13 interrupt request
[bit1] DMAC14IR (DMAC 14 Interrupt Request) : DMAC ch.14 interrupt request
[bit0] DMAC15IR (DMAC 15 Interrupt Request) : DMAC ch.15 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.29. Interrupt Request Batch Read Register 15 upper-order :
IRPR15H (Interrupt Request Peripheral Read register 15H)
The bit configuration of the interrupt request batch read register 15 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #15)
IRPR15H : Address 0436H (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
EXTNMI
XB_ECC_DE
BR_ECC_DE
0
0
0
0
0
R,WX
R,WX
R,WX
R0,WX
R0,WX
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] EXTNMI : External NMI Request
The EXTNMI bit is set by detecting external NMI request, and cleared by reading this register.
External NMI request
detection
Set
EXTNMI bit
IRPR15H
read or reset
Clear
[bit6] XB_ECC_DE : XBS RAM double bit error generation interrupt request
[bit5] BR_ECC_DE : Backup RAM double bit error generation interrupt request
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Chapter 17: Interrupt Request Batch Read
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
An internal reset is issued at the return from standby mode (power-shutdown), no NMI request can be maintained.
4.30. Interrupt Request Batch Read Register 15 lower-order :
IRPR15L (Interrupt Request Peripheral Read register 15L)
The bit configuration of the interrupt request batch read register 15 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #35)
IRPR15L : Address 0437H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CANIR1
XBTC
XBIC
XBTE
BRTC
BRIC
BRTE
CANIR4
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
Initial value
Attribute
[bit7] CANIR1(CAN Interrupt Request 1) : CAN ch.1 interrupt request
[bit6] XBTC(XBs ram Test Completed interrupt request) : XBS RAM test completed interrupt request
[bit5] XBIC(XBs ram Initialization Completed interrupt request) : XBS RAM initialization completed request
interrupt request
[bit4] XBTE(XBs ram Test Error interrupt request) : XBS RAM test error interrupt request
[bit3] BRTC(Backup RAM Test Completed interrupt request) : Backup RAM test completed interrupt request
[bit2] BRIC(Backup RAM Initialization Completed interrupt request) : Backup RAM initialization completed
interrupt request
[bit1] BRTE(Backup RAM Test Error interrupt request) : Backup RAM test error interrupt request
[bit0] CANIR4(CAN Interrupt Request 4) : CAN ch.4 interrupt request
Read value of each bit
498
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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Chapter 17: Interrupt Request Batch Read
4.31. Interrupt Request Batch Read Register 16 upper-order :
IRPR16H (Interrupt Request Peripheral Read register 16H)
The bit configuration of the interrupt request batch read register 16 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #31)
IRPR16H: Address 043CH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
ERAYIR
0
TXIR5
TXIR13
0
0
0
0
0
R,WX
R,WX
R,WX
R0,WX
R0,WX
Initial value
Attribute
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] ERAYIR0 (ERAY Interrupt Request 0) : FlexRay Ch.0 interrupt request
[bit6] TXIR5 (multifunction serial TX Interrupt Request 5) : Multi-function serial interface ch.5 transmission
completion interrupt request
[bit5] TXIR13 (multifunction serial TX Interrupt Request 13) : Multi-function serial interface ch.13 transmission
completion interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.32. Interrupt Request Batch Read Register 16 lower-order :
IRPR16L (Interrupt Request Peripheral Read register 16L)
The bit configuration of the interrupt request batch read register 16 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #32)
IRPR16L: Address 043DH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
ERAYIR1 RXIR6 ISIR6 RXIR14 ISIR14
Initial value
Attribute
0
R,WX
0
0
R,WX R,WX
0
R,WX
0
bit1
bit0
Reserved
0
0
0
R,WX R0,WX R0,WX R0,WX
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Chapter 17: Interrupt Request Batch Read
[bit7] ERAYIR1 (ERAY Interrupt Request 1) : FlexRay Ch.1 interrupt request
[bit6] RXIR6 (multifunction serial RX Interrupt Request 6) : Multi-function serial interface ch.6 reception
completion interrupt request
[bit5] ISIR6 (multifunction serial Inform Status Interrupt Request 6) : Multi-function serial interface ch.6 status
interrupt request
[bit4] RXIR14 (multifunction serial RX Interrupt Request 14) : Multi-function serial interface ch.14 reception
completion interrupt request
[bit3] ISIR14 (multifunction serial Inform Status Interrupt Request 14) : Multi-function serial interface ch.14
status interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
4.33. Interrupt Request Batch Read Register17 upper-order :
IRPR17H (Interrupt Request Peripheral Read register 17H)
The bit configuration of the interrupt request batch read register 17 upper-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #33)
IRPR17H: Address 043EH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
ERAYTI
R0
TXIR6
TXIR14
0
0
0
0
0
R,WX
R,WX
R,WX
R0,WX
R0,WX
Initial value
Attribute
bit4
bit3
bit2
bit1
bit0
0
0
0
R0,WX
R0,WX
R0,WX
Reserved
[bit7] ERAYTIR0 (ERAY Timer Interrupt Request 0) : FlexRay Timer Ch.0 interrupt request
[bit6] TXIR6 (multifunction serial TX Interrupt Request 6) : Multi-function serial interface ch.6 transmission
completion interrupt request
[bit5] TXIR14 (multifunction serial TX Interrupt Request 14) : Multi-function serial interface ch.14 transmission
completion interrupt request
500
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
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Chapter 17: Interrupt Request Batch Read
4.34. Interrupt Request Batch Read Register 17 lower-order :
IRPR17L (Interrupt Request Peripheral Read register 17L)
The bit configuration of the interrupt request batch read register 17 lower-order is shown.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #34)
IRPR17L: Address 043FH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
CANIR0 CANIR3 ERAYTIR1
Initial value
Attribute
0
0
0
R,WX
R,WX
R,WX
bit2
bit1
bit0
0
0
Reserved
0
0
0
R0,WX R0,WX R0,WX R0,WX R0,WX
[bit7] CANIR0 (CAN Interrupt Request 0) : CAN ch.0 interrupt request
[bit6] CANIR3 (CAN Interrupt Request 3) : CAN ch.3 interrupt request
[bit5] ERAYTIR1 (ERAY Timer Interrupt Request 1) : FlexRay Timer Ch.1 interrupt request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
5. Operation
This section explains the operation of the interrupt request batch read.
Within each interrupt handler, the pertinent register is read to determine what bits are set. As a consequence, what
interrupt requests have been generated is found.
Note:
This register does not provide a function that can be used to input external interrupts.
Read registers EIRR0, EIRR1, and EIRR2 which are used to input external interrupts.
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501
Chapter 18: PPG
This chapter explains the PPG.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Notes
Code : FS30-4v3-91528-3-E
502
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Chapter 18: PPG
1. Overview
This section explains the overview of the PPG.
The programmable pulse generator (PPG) is used to obtain one-shot (rectangular wave) or pulse width modulation
(PWM) outputs. The PPG can easily adapt itself to a wide range of applications because the cycle and duty of its
output can be programmed by software.
Cycle value
Count clock
Reload
Borrow
Down counter
Match
Inversion Output value
Latch
Pin
Buffer
Duty value
The numbers of available external output pins are shown below:
MB91F52xR (144pin) : 42
MB91F52xU (176pin) : 48
MB91F52xM (208pin) : 64
MB91F52xY (416pin) : 88
2. Features
This section explains features of the PPG.
Clamp output
Normal polarity: Output clamped to "L"
Inverted polarity: Output clamped to "H"
Count clock
One of the following 4 count clocks is selected:
Outputs obtained by dividing the frequency of the peripheral clock by 1, 4, 16, and 64.
Cycle
Setting range = Duty value to 65535 (specified by a 16-bit register)
Cycle = Count clock (PCSR register value + 1)
(Example) Count clock = 32 MHz (31.25 ns), PCSR value = 63999
Cycle = 31.25ns (63999+1) = 2ms
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Chapter 18: PPG
Cycle Setting (PHCSR/PLCSR) for the High/Low format at the PPG communication mode is also similar.
Duty
Setting range = 0 to cycle value (specified by a 16-bit register)
Duty = Count clock (PDUT register value + 1)
Duty setting (PHDUT/PLDUT) for the High/Low format at the PPG communication mode is also similar.
Output Waveforms
PWM Waveform
Normal Wave Form
Normal
Polarity
Inverted
Polarity
L
H
L
H
L
H
H
L
H
L
H
L
Duty
Cycle
Center Aligned Wave Form
Normal
Polarity
Inverted
Polarity
L
H
L
L
H
L
H
L
H
H
L
H
Duty
Cycle
* Cycle and duty are double as compared to when selecting
normal waveform.
504
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Chapter 18: PPG
One-shot Waveform (rectangular wave)
Normal Wave Form
Normal
Polarity
Inverted
Polarity
L
H
H
L
Duty
Cycle
Center Aligned Wave Form
Normal
Polarity
Inverted
Polarity
L
H
L
H
L
H
Duty
Cycle
* Cycle and duty are double as compared to when selecting
normal waveform.
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Chapter 18: PPG
High/Low format Waveform
The cycle of the High format and the Low format and duty are set respectively, and outputting waveform is
changed according to the data setting.
High format Setting1 Cycle=A Duty=C
High format Output Wave Form
Cycle Value
A
Normal Polarity
L
H
Duty Value
C
Inverted Polarity
H
L
Cycle=A
Duty=C
Low format Setting2 Cycle=B Duty=D
Low format Output Wave Form
Cycle Value
B
Normal Polarity
L
H
Duty Value
D
Inverted Polarity
H
L
Cycle=B
Duty=D
Data
00A5h (0000_0000_1010_0101)
Data Bit Length
Register
Selected Setting
7h
1
0
1
0
0
1
0
1
Setting1
Setting2
Setting1
Setting2
Setting2
Setting1
Setting2
Setting1
Cycle Value
A
B
A
B
B
A
B
A
Duty Value
C
D
C
D
D
C
D
C
1
0
1
0
0
1
0
1
A
B
C
D
Normal Polarity
Inverted Polarity
506
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Chapter 18: PPG
Interrupt factors
One of the following six interrupts is selected:
Software trigger or external trigger (TRG pin)
Borrow occurrence on the counter (match with the specified cycle)
Duty match
Borrow occurrence on the counter (match with the specified cycle) or duty match
Timing Point Capture match
Empty flag of PPG communication data register
Activation triggers
Software trigger
External trigger (TRG pin)
The activation trigger is input from an external.
The activation trigger is selected from one of the following triggers:
Internal trigger (EN0 to EN87)
External trigger (TRG pins 0 to 21)
Reload timer 0/1
GATE function
PPG is activated/stopped by GATE signals from the waveform generator.
Start Delay Mode
Support for PWM, One-shot operation, Normal Wave Form, and Center Aligned Wave Form.
Setting range = 0 to 65535 (specified by a 16-bit register)
Delay range = Count Clock (PSDR Resister value + 1)
(Example) Normal Wave Form: Count Clock = 32MHz (31.25ns), PSDR=63999
Cycle = 31.25ns (63999 + 1) = 2ms
(Example) Center Aligned Wave Form: Count Clock = 32MHz (31.25ns), PSDR=63999
Cycle = 31.25ns {(63999 + 1) 2} = 4ms
Timing Point Capture Mode
The AD activation trigger is generated according to the timing of the Timing Point Capture setting value.
PPG communication Mode
Cycle of High format and Low format, and setting of duty.
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Chapter 18: PPG
3. Configuration
This section explains the configuration of the PPG.
Figure 3-1 Configuration Diagram of PPG
MDSE
0
1
High/Low format
Cycle Value
Cycle Value
PHCSR/PLCSR
PCSR
PDUT
Reload
Reload
Buffer
Buffer
PCN: bit13
PWM operation
One-shot operation
OWFS
0
1
PCN: bit8
Normal Wave Form
Center Aligned Wave Form
CKS1, CKS0
0
0
0
1
1
0
1
1
PCN: bit11. bit10
EXT_CNTEN
EXT_CNTEN/4
EXT_CNTEN/16
EXT_CNTEN/64
Duty Value
High/Low format Duty
Value
Timing Point Capture
PHDUT/PLDUT
Setting Value (PTPC)
Buffer
PGMS
0
0
1
1
OSEL
0
1
0
1
PCN: bit9. bit0
Normal output
Inverted output
Clamp “L”output
Clamp “H”output
Buffer
Reload
A/D activation trigger
ADTRG
Compa
rison
Clock
EXT_CNTEN
PTMR
Prescaler
PPG output
PPG
Output
level(latch)
Compa
rison
Pulse Select
HFPR/LFPR
PCN: bit13,12
0
Low Pulse output
1
High Pulse output
Start Delay Setting Value
(PSDR)
CNTE
0
1
PPG communication mode data setting value
(PCMDDT)
PTRG: bit15
Stop
Enable operation
PPG communication mode data bit length setting value
(PCMDWD)
STRD
0
1
PCN2: bit8
Start Delay disable
Start Delay enable
Control
Circuit
TPC
0
1
PCN2: bit9
Timing Point Capture disable
Timing Point Capture enable
CMD
0
1
PCN2: bit10
PPG communication mode disable
PPG communication mode enable
CMDSEL
0
1
IRQ
RTRG
0
1
GATEC: bit0
Rising activation → falling stop
Falling activation → rising stop
0
0
508
0
signal
PSTR
IRQF
PCN: bit14
0
No interrupt request
1
Interrupu
Interruptrequest
request
0 write: Clearing IRQF
PTRG: bit12
Disable restart
Enable restart
STGR
GATE
GATE
PCN: bit5
Disable interrupt
Enable interrupt
PPG interrupt
PCN2: bit11
Data LSB output
data MSB output
EDGE
0
1
IREN
0
1
Level
detection
EN0
EN1
GTREN0:bit0
GTREN0:bit1
EN47
RLT0 Output
RLT1 Output
External trigger 0
External trigger 1
GTREN2:bit15
External trigger 11
Pin TRG11
TSEL0[6:0]/TSEL1[6:0]
0 0 0 0 0 0
0 0 0 0 0 1
GTRS0-GTRS23:bit14-8/bit6-bit0
EN0 bit (GTREN0:bit0)
EN1 bit (GTREN0:bit1)
1
Activation
trigger
TRG
Edge
selection
Pin TRG0
Pin TRG1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
EN47 bit (GTREN2:bit15)
16bit Reload Timer 0
16bit Reload Timer 1
External trigger 0
External trigger 1
1
0
0
1
0
1
1
External trigger 11
GATEC: bit1
Activation by activation
trigger
Activation by activation
signal from waveform
generator
STRG
0
1
PTRG: bit14
No effect on operation
Software trigger
IRS2
IRS1
IRS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
SREMP
EGS1, EGS0
0
0
0
1
1
0
1
1
PCN: bit7. bit6
No effect on operation
Rising edge
Falling edge
Both edge
0
1
REMP
0
1
PCN: bit3. bit2
STGR=0
Input of software trigger or external trigger
STGR=1
Input of GATE signal trigger
Counter borrow occurrence
Duty value match
Counter borrow ocurrence
occurrenceororduty
dutyvalue
valuematch
match
Timing Point Capture value match
PPG communication data register Empty factor
PCN2: bit1
PPG communication data shift register Empty flag
(NotEmpty state)
PPG communication data shift register Empty flag
(Empty state)
PCN2: bit2
PPG communication data register Empty flag
(NotEmpty state)
PPG communication data register Empty flag
(Empty state)
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Chapter 18: PPG
4. Registers
This section explains registers of the PPG.
List of External Pins
Channel
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
External Pins (PPG Output)
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
PPG0_0/PPG0_1
PPG1_0/PPG1_1
PPG2_0/PPG2_1
PPG3_0/PPG3_1
PPG4_0/PPG4_1
PPG5_0/PPG5_1
PPG6_0
PPG7_0
PPG8_0
PPG9_0
PPG10_0
PPG11_0
PPG12_0
PPG13_0
PPG14_0
PPG15_0
PPG16_0/PPG16_1
PPG17_0/PPG17_1
PPG18_0
PPG19_0
PPG20_0
PPG21_0
PPG22_0
PPG23_0/PPG23_1
PPG24_0
PPG25_0
PPG26_0
PPG27_0
PPG28_0
PPG29_0
PPG30_0
PPG31_0
PPG32_0
PPG33_0
PPG34_0
PPG35_0
PPG36_0
PPG37_0
−
PPG0_0/PPG0_1
PPG1_0/PPG1_1
PPG2_0/PPG2_1
PPG3_0/PPG3_1
PPG4_0/PPG4_1
PPG5_0/PPG5_1
PPG6_0
PPG7_0
PPG8_0
PPG9_0
PPG10_0
PPG11_0
PPG12_0
PPG13_0
PPG14_0
PPG15_0
PPG16_0/PPG16_1
PPG17_0/PPG17_1
PPG18_0
PPG19_0
PPG20_0
PPG21_0
PPG22_0
PPG23_0/PPG23_1
PPG24_0/PPG24_1
PPG25_0/PPG25_1
PPG26_0/PPG26_1
PPG27_0/PPG27_1
PPG28_0/PPG28_1
PPG29_0/PPG29_1
PPG30_0/PPG30_1
PPG31_0/PPG31_1
PPG32_0/PPG32_1
PPG33_0/PPG33_1
PPG34_0/PPG34_1
PPG35_0/PPG35_1
PPG36_0/PPG36_1
PPG37_0/PPG37_1
PPG38_1
PPG0_0/PPG0_1
PPG1_0/PPG1_1
PPG2_0/PPG2_1
PPG3_0/PPG3_1
PPG4_0/PPG4_1
PPG5_0/PPG5_1
PPG6_0
PPG7_0
PPG8_0
PPG9_0
PPG10_0
PPG11_0
PPG12_0
PPG13_0
PPG14_0
PPG15_0
PPG16_0/PPG16_1
PPG17_0/PPG17_1
PPG18_0
PPG19_0
PPG20_0
PPG21_0
PPG22_0
PPG23_0/PPG23_1
PPG24_0/PPG24_1
PPG25_0/PPG25_1
PPG26_0/PPG26_1
PPG27_0/PPG27_1
PPG28_0/PPG28_1
PPG29_0/PPG29_1
PPG30_0/PPG30_1
PPG31_0/PPG31_1
PPG32_0/PPG32_1
PPG33_0/PPG33_1
PPG34_0/PPG34_1
PPG35_0/PPG35_1
PPG36_0/PPG36_1
PPG37_0/PPG37_1
PPG38_1
PPG0_0/PPG0_1
PPG1_0/PPG1_1
PPG2_0/PPG2_1
PPG3_0/PPG3_1
PPG4_0/PPG4_1
PPG5_0/PPG5_1
PPG6_0
PPG7_0
PPG8_0
PPG9_0
PPG10_0
PPG11_0
PPG12_0
PPG13_0
PPG14_0
PPG15_0
PPG16_0/PPG16_1
PPG17_0/PPG17_1
PPG18_0
PPG19_0
PPG20_0
PPG21_0
PPG22_0
PPG23_0/PPG23_1
PPG24_0/PPG24_1
PPG25_0/PPG25_1
PPG26_0/PPG26_1
PPG27_0/PPG27_1
PPG28_0/PPG28_1
PPG29_0/PPG29_1
PPG30_0/PPG30_1
PPG31_0/PPG31_1
PPG32_0/PPG32_1
PPG33_0/PPG33_1
PPG34_0/PPG34_1
PPG35_0/PPG35_1
PPG36_0/PPG36_1
PPG37_0/PPG37_1
PPG38_1
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Chapter 18: PPG
Channel
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
510
External Pins (PPG Output)
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
−
PPG40_1
PPG41_1
−
PPG43_1
PPG44_1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PPG39_1
PPG40_0/PPG40_1
PPG41_0/PPG41_1
PPG42_0
PPG43_0/PPG43_1
PPG44_0/PPG44_1
PPG45_0
PPG46_0
PPG47_0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PPG39_1
PPG40_0/PPG40_1
PPG41_0/PPG41_1
PPG42_0
PPG43_0/PPG43_1
PPG44_0/PPG44_1
PPG45_0
PPG46_0
PPG47_0
PPG48_0/PPG48_1
PPG49_0/PPG49_1
PPG50_0
PPG51_0
PPG52_0
PPG53_0
PPG54_0
PPG55_0
PPG56_0
PPG57_0
PPG58_0
PPG59_0
PPG60_0
PPG61_0
PPG62_0
PPG63_0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PPG39_1
PPG40_0/PPG40_1
PPG41_0/PPG41_1
PPG42_0
PPG43_0/PPG43_1
PPG44_0/PPG44_1
PPG45_0
PPG46_0
PPG47_0
PPG48_0/PPG48_1
PPG49_0/PPG49_1
PPG50_0
PPG51_0
PPG52_0
PPG53_0
PPG54_0
PPG55_0
PPG56_0
PPG57_0
PPG58_0
PPG59_0
PPG60_0
PPG61_0
PPG62_0
PPG63_0
PPG64_0/PPG64_1
PPG65_0/PPG65_1
PPG66_0/PPG66_1
PPG67_0/PPG67_1
PPG68_0
PPG69_0
PPG70_0
PPG71_0
PPG72_0
PPG73_0
PPG74_0
PPG75_0
PPG76_0
PPG77_0
PPG78_0
PPG79_0
PPG80_0
PPG81_0
PPG82_0
PPG83_0
PPG84_0
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Chapter 18: PPG
Channel
85
86
87
External Pins (PPG Output)
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
−
−
−
−
−
−
−
−
−
PPG85_0
PPG86_0/PPG86_1
PPG87_0/PPG87_1
External Pins (PPG Trigger Input)
Channel
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
1
2
3
4
5
TRG0_0/TRG0_1/
TRG0_2
TRG1_0/TRG1_1
TRG2_0/TRG2_1
TRG3_0/TRG3_1
TRG4_0/TRG4_1
TRG5_0/TRG5_1
6
TRG6_0/TRG6_1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TRG7_0/TRG7_1
TRG8_0
TRG9_0
−
−
−
−
−
−
−
−
−
−
−
−
TRG0_0/TRG0_1/
TRG0_2
TRG1_0/TRG1_1
TRG2_0/TRG2_1
TRG3_0/TRG3_1
TRG4_0/TRG4_1
TRG5_0/TRG5_1/
TRG5_2
TRG6_0/TRG6_1/
TRG6_2
TRG7_0/TRG7_1
TRG8_0/TRG8_1
TRG9_0/TRG9_1
TRG10_0
TRG11_0
−
−
−
−
−
−
−
−
−
−
TRG0_0/TRG0_1/
TRG0_2
TRG1_0/TRG1_1
TRG2_0/TRG2_1
TRG3_0/TRG3_1
TRG4_0/TRG4_1
TRG5_0/TRG5_1/
TRG5_2
TRG6_0/TRG6_1/
TRG6_2
TRG7_0/TRG7_1
TRG8_0/TRG8_1
TRG9_0/TRG9_1
TRG10_0
TRG11_0
TRG12_0/TRG12_1
TRG13_0/TRG13_1
TRG14_0
TRG15_0
−
−
−
−
−
−
TRG0_0/TRG0_1/
TRG0_2
TRG1_0/TRG1_1
TRG2_0/TRG2_1
TRG3_0/TRG3_1
TRG4_0/TRG4_1
TRG5_0/TRG5_1/
TRG5_2
TRG6_0/TRG6_1/
TRG6_2
TRG7_0/TRG7_1
TRG8_0/TRG8_1
TRG9_0/TRG9_1
TRG10_0
TRG11_0
TRG12_0/TRG12_1
TRG13_0/TRG13_1
TRG14_0
TRG15_0
TRG16_0/TRG16_1
TRG17_0/TRG17_1
TRG18_0
TRG19_0
TRG20_0
TRG21_0
0
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Chapter 18: PPG
The registers of PPG are listed below.
List of PPG Registers
Address
+0
+1
+2
0x1A40
0x1A44
PPG (ch.0) control status register (PCN0)
PPG (ch.0) duty setting register (PDUT0)
0x1A48
PPG (ch.0) control status register2 (PCN200)
0x1A5C
0x1A60
PPG (ch.0) Timing Point Capture value setting
register (PTPC0)
PPG (ch.0) communication mode High format
cycle setting register (PHCSR0)
PPG (ch.0) communication mode High format
duty setting register (PHDUT0)
PPG (ch.0) communication mode data setting
register (PCMDDT0)
PPG (ch.1) control status register (PCN1)
PPG (ch.1) duty setting register (PDUT1)
0x1A64
PPG (ch.1) control status register2 (PCN201)
0x1A4C
0x1A50
0x1A54
0x1A58
0x1A78
0x1A7C
PPG (ch.1) Timing Point Capture value setting
register (PTPC1)
PPG (ch.1) communication mode High format
cycle setting register (PHCSR1)
PPG (ch.1) communication mode High format
duty setting register (PHDUT1)
PPG (ch.1) communication mode data setting
register (PCMDDT1)
PPG (ch.2) control status register (PCN2)
PPG (ch.2) duty setting register (PDUT2)
0x1A80
PPG (ch.2) control status register2 (PCN202)
0x1A68
0x1A6C
0x1A70
0x1A74
0x1A94
0x1A98
PPG (ch.2) Timing Point Capture value setting
register (PTPC2)
PPG (ch.2) communication mode High format
cycle setting register (PHCSR2)
PPG (ch.2) communication mode High format
duty setting register (PHDUT2)
PPG (ch.2) communication mode data setting
register (PCMDDT2)
PPG (ch.3) control status register (PCN3)
PPG (ch.3) duty setting register (PDUT3)
0x1A9C
PPG (ch.3) control status register2 (PCN203)
0x1A84
0x1A88
0x1A8C
0x1A90
0x1AA0
0x1AA4
0x1AA8
512
PPG (ch.3) Timing Point Capture value setting
register (PTPC3)
PPG (ch.3) communication mode High format
cycle setting register (PHCSR3)
PPG (ch.3) communication mode High format
duty setting register (PHDUT3)
+3
PPG (ch.0) cycle setting register (PCSR0)
PPG (ch.0) timer register (PTMR0)
PPG (ch.0) Start Delay value setting register
(PSDR0)
PPG (ch.0) communication mode data bit
length setting register (PCMDWD0)
PPG (ch.0) communication mode Low format
cycle setting register (PLCSR0)
PPG (ch.0) communication mode Low format
duty setting register (PLDUT0)
Reserved
PPG (ch.1) cycle setting register (PCSR1)
PPG (ch.1) timer register (PTMR1)
PPG (ch.1) Start Delay value setting register
(PSDR1)
PPG (ch.1) communication mode data bit
length setting register (PCMDWD1)
PPG (ch.1) communication mode Low format
cycle setting register (PLCSR1)
PPG (ch.1) communication mode Low format
duty setting register (PLDUT1)
Reserved
PPG (ch.2) cycle setting register (PCSR2)
PPG (ch.2) timer register (PTMR2)
PPG (ch.2) Start Delay value setting register
(PSDR2)
PPG (ch.2) communication mode data bit
length setting register (PCMDWD2)
PPG (ch.2) communication mode Low format
cycle setting register (PLCSR2)
PPG (ch.2) communication mode Low format
duty setting register (PLDUT2)
Reserved
PPG (ch.3) cycle setting register (PCSR3)
PPG (ch.3) timer register (PTMR3)
PPG (ch.3) Start Delay value setting register
(PSDR3)
PPG (ch.3) communication mode data bit
length setting register (PCMDWD3)
PPG (ch.3) communication mode Low format
cycle setting register (PLCSR3)
PPG (ch.3) communication mode Low format
duty setting register (PLDUT3)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Address
+0
+1
0x1AB0
0x1AB4
PPG (ch.3) communication mode data setting
register (PCMDDT3)
PPG (ch.4) control status register (PCN4)
PPG (ch.4) duty setting register (PDUT4)
0x1AB8
PPG (ch.4) control status register2 (PCN204)
0x1AAC
0x1AC0
0x1AC4
PPG (ch.4) Timing Point Capture value setting
register (PTPC4)
PPG (ch.5) control status register (PCN5)
PPG (ch.5) duty setting register (PDUT5)
0x1AC8
PPG (ch.5) control status register2 (PCN205)
0x1ABC
0x1AD0
0x1AD4
PPG (ch.5) Timing Point Capture value setting
register (PTPC5)
PPG (ch.6) control status register (PCN6)
PPG (ch.6) duty setting register (PDUT6)
0x1AD8
PPG (ch.6) control status register2 (PCN206)
0x1ACC
0x1AE0
0x1AE4
PPG (ch.6) Timing Point Capture value setting
register (PTPC6)
PPG (ch.7) control status register (PCN7)
PPG (ch.7) duty setting register (PDUT7)
0x1AE8
PPG (ch.7) control status register2 (PCN207)
0x1ADC
0x1AF0
0x1AF4
PPG (ch.7) Timing Point Capture value setting
register (PTPC7)
PPG (ch.8) control status register (PCN8)
PPG (ch.8) duty setting register (PDUT8)
0x1AF8
PPG (ch.8) control status register2 (PCN208)
0x1AEC
0x1B00
0x1B04
PPG (ch.8) Timing Point Capture value setting
register (PTPC8)
PPG (ch.9) control status register (PCN9)
PPG (ch.9) duty setting register (PDUT9)
0x1B08
PPG (ch.9) control status register2 (PCN209)
0x1AFC
0x1B10
0x1B14
PPG (ch.9) Timing Point Capture value setting
register (PTPC9)
PPG (ch.10) control status register (PCN10)
PPG (ch.10) duty setting register (PDUT10)
0x1B18
PPG (ch.10) control status register2 (PCN210)
0x1B0C
0x1B20
0x1B24
PPG (ch.10) Timing Point Capture value setting
register (PTPC10)
PPG (ch.11) control status register (PCN11)
PPG (ch.11) duty setting register (PDUT11)
0x1B28
PPG (ch.11) control status register2 (PCN211)
0x1B1C
+2
+3
Reserved
PPG (ch.4) cycle setting register (PCSR4)
PPG (ch.4) timer register (PTMR4)
PPG (ch.4) Start Delay value setting register
(PSDR4)
Reserved
PPG (ch.5) cycle setting register (PCSR5)
PPG (ch.5) timer register (PTMR5)
PPG (ch.5) Start Delay value setting register
(PSDR5)
Reserved
PPG (ch.6) cycle setting register (PCSR6)
PPG (ch.6) timer register (PTMR6)
PPG (ch.6) Start Delay value setting register
(PSDR6)
Reserved
PPG (ch.7) cycle setting register (PCSR7)
PPG (ch.7) timer register (PTMR7)
PPG (ch.7) Start Delay value setting register
(PSDR7)
Reserved
PPG (ch.8) cycle setting register (PCSR8)
PPG (ch.8) timer register (PTMR8)
PPG (ch.8) Start Delay value setting register
(PSDR8)
Reserved
PPG (ch.9) cycle setting register (PCSR9)
PPG (ch.9) timer register (PTMR9)
PPG (ch.9) Start Delay value setting register
(PSDR9)
Reserved
PPG (ch.10) cycle setting register (PCSR10)
PPG (ch.10) timer register (PTMR10)
PPG (ch.10) Start Delay value setting register
(PSDR10)
Reserved
PPG (ch.11) cycle setting register (PCSR11)
PPG (ch.11) timer register (PTMR11)
PPG (ch.11) Start Delay value setting register
(PSDR11)
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Chapter 18: PPG
Address
+0
+1
+2
0x1B30
0x1B34
PPG (ch.11) Timing Point Capture value setting
register (PTPC11)
PPG (ch.12) control status register (PCN12)
PPG (ch.12) duty setting register (PDUT12)
0x1B38
PPG (ch.12) control status register2 (PCN212)
0x1B2C
0x1B40
0x1B44
PPG (ch.12) Timing Point Capture value setting
register (PTPC12)
PPG (ch.13) control status register (PCN13)
PPG (ch.13) duty setting register (PDUT13)
0x1B48
PPG (ch.13) control status register2 (PCN213)
0x1B3C
0x1B50
0x1B54
PPG (ch.13) Timing Point Capture value setting
register (PTPC13)
PPG (ch.14) control status register (PCN14)
PPG (ch.14) duty setting register (PDUT14)
0x1B58
PPG (ch.14) control status register2 (PCN214)
0x1B4C
0x1B60
0x1B64
PPG (ch.14) Timing Point Capture value setting
register (PTPC14)
PPG (ch.15) control status register (PCN15)
PPG (ch.15) duty setting register (PDUT15)
0x1B68
PPG (ch.15) control status register2 (PCN215)
0x1B5C
0x1B70
0x1B74
PPG (ch.15) Timing Point Capture value setting
register (PTPC15)
PPG (ch.16) control status register (PCN16)
PPG (ch.16) duty setting register (PDUT16)
0x1B78
PPG (ch.16) control status register2 (PCN216)
0x1B6C
0x1B80
0x1B84
PPG (ch.16) Timing Point Capture value setting
register (PTPC16)
PPG (ch.17) control status register (PCN17)
PPG (ch.17) duty setting register (PDUT17)
0x1B88
PPG (ch.17) control status register2 (PCN217)
0x1B7C
0x1B90
0x1B94
PPG (ch.17) Timing Point Capture value setting
register (PTPC17)
PPG (ch.18) control status register (PCN18)
PPG (ch.18) duty setting register (PDUT18)
0x1B98
PPG (ch.18) control status register2 (PCN218)
0x1B8C
0x1BA0
0x1BA4
PPG (ch.18) Timing Point Capture value setting
register (PTPC18)
PPG (ch.19) control status register (PCN19)
PPG (ch.19) duty setting register (PDUT19)
0x1BA8
PPG (ch.19) control status register2 (PCN219)
0x1B9C
514
+3
Reserved
PPG (ch.12) cycle setting register (PCSR12)
PPG (ch.12) timer register (PTMR12)
PPG (ch.12) Start Delay value setting register
(PSDR12)
Reserved
PPG (ch.13) cycle setting register (PCSR13)
PPG (ch.13) timer register (PTMR13)
PPG (ch.13) Start Delay value setting register
(PSDR13)
Reserved
PPG (ch.14) cycle setting register (PCSR14)
PPG (ch.14) timer register (PTMR14)
PPG (ch.14) Start Delay value setting register
(PSDR14)
Reserved
PPG (ch.15) cycle setting register (PCSR15)
PPG (ch.15) timer register (PTMR15)
PPG (ch.15) Start Delay value setting register
(PSDR15)
Reserved
PPG (ch.16) cycle setting register (PCSR16)
PPG (ch.16) timer register (PTMR16)
PPG (ch.16) Start Delay value setting register
(PSDR16)
Reserved
PPG (ch.17) cycle setting register (PCSR17)
PPG (ch.17) timer register (PTMR17)
PPG (ch.17) Start Delay value setting register
(PSDR17)
Reserved
PPG (ch.18) cycle setting register (PCSR18)
PPG (ch.18) timer register (PTMR18)
PPG (ch.18) Start Delay value setting register
(PSDR18)
Reserved
PPG (ch.19) cycle setting register (PCSR19)
PPG (ch.19) timer register (PTMR19)
PPG (ch.19) Start Delay value setting register
(PSDR19)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Address
+0
+1
0x1BB0
0x1BB4
PPG (ch.19) Timing Point Capture value setting
register (PTPC19)
PPG (ch.20) control status register (PCN20)
PPG (ch.20) duty setting register (PDUT20)
0x1BB8
PPG (ch.20) control status register2 (PCN220)
0x1BAC
0x1BC0
0x1BC4
PPG (ch.20) Timing Point Capture value setting
register (PTPC20)
PPG (ch.21) control status register (PCN21)
PPG (ch.21) duty setting register (PDUT21)
0x1BC8
PPG (ch.21) control status register2 (PCN221)
0x1BBC
0x1BD0
0x1BD4
PPG (ch.21) Timing Point Capture value setting
register (PTPC21)
PPG (ch.22) control status register (PCN22)
PPG (ch.22) duty setting register (PDUT22)
0x1BD8
PPG (ch.22) control status register2 (PCN222)
0x1BCC
0x1BE0
0x1BE4
PPG (ch.22) Timing Point Capture value setting
register (PTPC22)
PPG (ch.23) control status register (PCN23)
PPG (ch.23) duty setting register (PDUT23)
0x1BE8
PPG (ch.23) control status register2 (PCN223)
0x1BDC
0x1BF0
0x1BF4
PPG (ch.23) Timing Point Capture value setting
register (PTPC23)
PPG (ch.24) control status register (PCN24)
PPG (ch.24) duty setting register (PDUT24)
0x1BF8
PPG (ch.24) control status register2 (PCN224)
0x1BEC
0x1C00
0x1C04
PPG (ch.24) Timing Point Capture value setting
register (PTPC24)
PPG (ch.25) control status register (PCN25)
PPG (ch.25) duty setting register (PDUT25)
0x1C08
PPG (ch.25) control status register2 (PCN225)
0x1BFC
0x1C10
0x1C14
PPG (ch.25) Timing Point Capture value setting
register (PTPC25)
PPG (ch.26) control status register (PCN26)
PPG (ch.26) duty setting register (PDUT26)
0x1C18
PPG (ch.26) control status register2 (PCN226)
0x1C0C
0x1C20
0x1C24
PPG (ch.26) Timing Point Capture value setting
register (PTPC26)
PPG (ch.27) control status register (PCN27)
PPG (ch.27) duty setting register (PDUT27)
0x1C28
PPG (ch.27) control status register2 (PCN227)
0x1C1C
+2
+3
Reserved
PPG (ch.20) cycle setting register (PCSR20)
PPG (ch.20) timer register (PTMR20)
PPG (ch.20) Start Delay value setting register
(PSDR20)
Reserved
PPG (ch.21) cycle setting register (PCSR21)
PPG (ch.21) timer register (PTMR21)
PPG (ch.21) Start Delay value setting register
(PSDR21)
Reserved
PPG (ch.22) cycle setting register (PCSR22)
PPG (ch.22) timer register (PTMR22)
PPG (ch.22) Start Delay value setting register
(PSDR22)
Reserved
PPG (ch.23) cycle setting register (PCSR23)
PPG (ch.23) timer register (PTMR23)
PPG (ch.23) Start Delay value setting register
(PSDR23)
Reserved
PPG (ch.24) cycle setting register (PCSR24)
PPG (ch.24) timer register (PTMR24)
PPG (ch.24) Start Delay value setting register
(PSDR24)
Reserved
PPG (ch.25) cycle setting register (PCSR25)
PPG (ch.25) timer register (PTMR25)
PPG (ch.25) Start Delay value setting register
(PSDR25)
Reserved
PPG (ch.26) cycle setting register (PCSR26)
PPG (ch.26) timer register (PTMR26)
PPG (ch.26) Start Delay value setting register
(PSDR26)
Reserved
PPG (ch.27) cycle setting register (PCSR27)
PPG (ch.27) timer register (PTMR27)
PPG (ch.27) Start Delay value setting register
(PSDR27)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
515
Chapter 18: PPG
Address
+0
+1
+2
0x1C30
0x1C34
PPG (ch.27) Timing Point Capture value setting
register (PTPC27)
PPG (ch.28) control status register (PCN28)
PPG (ch.28) duty setting register (PDUT28)
0x1C38
PPG (ch.28) control status register2 (PCN228)
0x1C2C
0x1C40
0x1C44
PPG (ch.28) Timing Point Capture value setting
register (PTPC28)
PPG (ch.29) control status register (PCN29)
PPG (ch.29) duty setting register (PDUT29)
0x1C48
PPG (ch.29) control status register2 (PCN229)
0x1C3C
0x1C50
0x1C54
PPG (ch.29) Timing Point Capture value setting
register (PTPC29)
PPG (ch.30) control status register (PCN30)
PPG (ch.30) duty setting register (PDUT30)
0x1C58
PPG (ch.30) control status register2 (PCN230)
0x1C4C
0x1C60
0x1C64
PPG (ch.30) Timing Point Capture value setting
register (PTPC30)
PPG (ch.31) control status register (PCN31)
PPG (ch.31) duty setting register (PDUT31)
0x1C68
PPG (ch.31) control status register2 (PCN231)
0x1C5C
0x1C70
0x1C74
PPG (ch.31) Timing Point Capture value setting
register (PTPC31)
PPG (ch.32) control status register (PCN32)
PPG (ch.32) duty setting register (PDUT32)
0x1C78
PPG (ch.32) control status register2 (PCN232)
0x1C6C
0x1C80
0x1C84
PPG (ch.32) Timing Point Capture value setting
register (PTPC32)
PPG (ch.33) control status register (PCN33)
PPG (ch.33) duty setting register (PDUT33)
0x1C88
PPG (ch.33) control status register2 (PCN233)
0x1C7C
0x1C90
0x1C94
PPG (ch.33) Timing Point Capture value setting
register (PTPC33)
PPG (ch.34) control status register (PCN34)
PPG (ch.34) duty setting register (PDUT34)
0x1C98
PPG (ch.34) control status register2 (PCN234)
0x1C8C
0x1CA0
0x1CA4
PPG (ch.34) Timing Point Capture value setting
register (PTPC34)
PPG (ch.35) control status register (PCN35)
PPG (ch.35) duty setting register (PDUT35)
0x1CA8
PPG (ch.35) control status register2 (PCN235)
0x1C9C
516
+3
Reserved
PPG (ch.28) cycle setting register (PCSR28)
PPG (ch.28) timer register (PTMR28)
PPG (ch.28) Start Delay value setting register
(PSDR28)
Reserved
PPG (ch.29) cycle setting register (PCSR29)
PPG (ch.29) timer register (PTMR29)
PPG (ch.29) Start Delay value setting register
(PSDR29)
Reserved
PPG (ch.30) cycle setting register (PCSR30)
PPG (ch.30) timer register (PTMR30)
PPG (ch.30) Start Delay value setting register
(PSDR30)
Reserved
PPG (ch.31) cycle setting register (PCSR31)
PPG (ch.31) timer register (PTMR31)
PPG (ch.31) Start Delay value setting register
(PSDR31)
Reserved
PPG (ch.32) cycle setting register (PCSR32)
PPG (ch.32) timer register (PTMR32)
PPG (ch.32) Start Delay value setting register
(PSDR32)
Reserved
PPG (ch.33) cycle setting register (PCSR33)
PPG (ch.33) timer register (PTMR33)
PPG (ch.33) Start Delay value setting register
(PSDR33)
Reserved
PPG (ch.34) cycle setting register (PCSR34)
PPG (ch.34) timer register (PTMR34)
PPG (ch.34) Start Delay value setting register
(PSDR34)
Reserved
PPG (ch.35) cycle setting register (PCSR35)
PPG (ch.35) timer register (PTMR35)
PPG (ch.35) Start Delay value setting register
(PSDR35)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Address
+0
+1
0x1CB0
0x1CB4
PPG (ch.35) Timing Point Capture value setting
register (PTPC35)
PPG (ch.36) control status register (PCN36)
PPG (ch.36) duty setting register (PDUT36)
0x1CB8
PPG (ch.36) control status register2 (PCN236)
0x1CAC
0x1CC0
0x1CC4
PPG (ch.36) Timing Point Capture value setting
register (PTPC36)
PPG (ch.37) control status register (PCN37)
PPG (ch.37) duty setting register (PDUT37)
0x1CC8
PPG (ch.37) control status register2 (PCN237)
0x1CBC
0x1CD0
0x1CD4
PPG (ch.37) Timing Point Capture value setting
register (PTPC37)
PPG (ch.38) control status register (PCN38)
PPG (ch.38) duty setting register (PDUT38)
0x1CD8
PPG (ch.38) control status register2 (PCN238)
0x1CCC
0x1CE0
0x1CE4
PPG (ch.38) Timing Point Capture value setting
register (PTPC38)
PPG (ch.39) control status register (PCN39)
PPG (ch.39) duty setting register (PDUT39)
0x1CE8
PPG (ch.39) control status register2 (PCN239)
0x1CDC
0x1CF0
0x1CF4
PPG (ch.39) Timing Point Capture value setting
register (PTPC39)
PPG (ch.40) control status register (PCN40)
PPG (ch.40) duty setting register (PDUT40)
0x1CF8
PPG (ch.40) control status register2 (PCN240)
0x1CEC
0x1D00
0x1D04
PPG (ch.40) Timing Point Capture value setting
register (PTPC40)
PPG (ch.41) control status register (PCN41)
PPG (ch.41) duty setting register (PDUT41)
0x1D08
PPG (ch.41) control status register2 (PCN241)
0x1CFC
0x1D10
0x1D14
PPG (ch.41) Timing Point Capture value setting
register (PTPC41)
PPG (ch.42) control status register (PCN42)
PPG (ch.42) duty setting register (PDUT42)
0x1D18
PPG (ch.42) control status register2 (PCN242)
0x1D0C
0x1D20
0x1D24
PPG (ch.42) Timing Point Capture value setting
register (PTPC42)
PPG (ch.43) control status register (PCN43)
PPG (ch.43) duty setting register (PDUT43)
0x1D28
PPG (ch.43) control status register2 (PCN243)
0x1D1C
+2
+3
Reserved
PPG (ch.36) cycle setting register (PCSR36)
PPG (ch.36) timer register (PTMR36)
PPG (ch.36) Start Delay value setting register
(PSDR36)
Reserved
PPG (ch.37) cycle setting register (PCSR37)
PPG (ch.37) timer register (PTMR37)
PPG (ch.37) Start Delay value setting register
(PSDR37)
Reserved
PPG (ch.38) cycle setting register (PCSR38)
PPG (ch.38) timer register (PTMR38)
PPG (ch.38) Start Delay value setting register
(PSDR38)
Reserved
PPG (ch.39) cycle setting register (PCSR39)
PPG (ch.39) timer register (PTMR39)
PPG (ch.39) Start Delay value setting register
(PSDR39)
Reserved
PPG (ch.40) cycle setting register (PCSR40)
PPG (ch.40) timer register (PTMR40)
PPG (ch.40) Start Delay value setting register
(PSDR40)
Reserved
PPG (ch.41) cycle setting register (PCSR41)
PPG (ch.41) timer register (PTMR41)
PPG (ch.41) Start Delay value setting register
(PSDR41)
Reserved
PPG (ch.42) cycle setting register (PCSR42)
PPG (ch.42) timer register (PTMR42)
PPG (ch.42) Start Delay value setting register
(PSDR42)
Reserved
PPG (ch.43) cycle setting register (PCSR43)
PPG (ch.43) timer register (PTMR43)
PPG (ch.43) Start Delay value setting register
(PSDR43)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
517
Chapter 18: PPG
Address
+0
+1
+2
0x1D30
0x1D34
PPG (ch.43) Timing Point Capture value setting
register (PTPC43)
PPG (ch.44) control status register (PCN44)
PPG (ch.44) duty setting register (PDUT44)
0x1D38
PPG (ch.44) control status register2 (PCN244)
0x1D2C
0x1D40
0x1D44
PPG (ch.44) Timing Point Capture value setting
register (PTPC44)
PPG (ch.45) control status register (PCN45)
PPG (ch.45) duty setting register (PDUT45)
0x1D48
PPG (ch.45) control status register2 (PCN245)
0x1D3C
0x1D50
0x1D54
PPG (ch.45) Timing Point Capture value setting
register (PTPC45)
PPG (ch.46) control status register (PCN46)
PPG (ch.46) duty setting register (PDUT46)
0x1D58
PPG (ch.46) control status register2 (PCN246)
0x1D4C
0x1D60
0x1D64
PPG (ch.46) Timing Point Capture value setting
register (PTPC46)
PPG (ch.47) control status register (PCN47)
PPG (ch.47) duty setting register (PDUT47)
0x1D68
PPG (ch.47) control status register2 (PCN247)
0x1D5C
0x1D70
0x1D74
PPG (ch.47) Timing Point Capture value setting
register (PTPC47)
PPG(ch.48) control status register (PCN48)
PPG(ch.48) duty setting register (PDUT48)
0x1D78
PPG(ch.48) control status register 2(PCN248)
0x1D6C
0x1D80
0x1D84
PPG(ch.48)Timing Point Capture value setting
register (PTPC48)
PPG(ch.49) control status register (PCN49)
PPG(ch.49) duty setting register (PDUT49)
0x1D88
PPG(ch.49) control status register 2(PCN249)
0x1D7C
0x1D90
0x1D94
PPG(ch.49)Timing Point Capture value setting
register (PTPC49)
PPG(ch.50) control status register (PCN50)
PPG(ch.50) duty setting register (PDUT50)
0x1D98
PPG(ch.50) control status register 2(PCN250)
0x1D8C
0x1DA0
0x1DA4
PPG(ch.50)Timing Point Capture value setting
register (PTPC50)
PPG(ch.51) control status register (PCN51)
PPG(ch.51) duty setting register (PDUT51)
0x1DA8
PPG(ch.51) control status register 2(PCN251)
0x1D9C
518
+3
Reserved
PPG (ch.44) cycle setting register (PCSR44)
PPG (ch.44) timer register (PTMR44)
PPG (ch.44) Start Delay value setting register
(PSDR44)
Reserved
PPG (ch.45) cycle setting register (PCSR45)
PPG (ch.45) timer register (PTMR45)
PPG (ch.45) Start Delay value setting register
(PSDR45)
Reserved
PPG (ch.46) cycle setting register (PCSR46)
PPG (ch.46) timer register (PTMR46)
PPG (ch.46) Start Delay value setting register
(PSDR46)
Reserved
PPG (ch.47) cycle setting register (PCSR47)
PPG (ch.47) timer register (PTMR47)
PPG (ch.47) Start Delay value setting register
(PSDR47)
Reserved
PPG(ch.48) cycle setting register (PCSR48)
PPG(ch.48) timer register (PTMR48)
PPG(ch.48)Start Delay value setting register
(PSDR48)
Reserved
PPG(ch.49) cycle setting register (PCSR49)
PPG(ch.49) timer register (PTMR49)
PPG(ch.49)Start Delay value setting register
(PSDR49)
Reserved
PPG(ch.50) cycle setting register (PCSR50)
PPG(ch.50) timer register (PTMR50)
PPG(ch.50)Start Delay value setting register
(PSDR50)
Reserved
PPG(ch.51) cycle setting register (PCSR51)
PPG(ch.51) timer register (PTMR51)
PPG(ch.51)Start Delay value setting register
(PSDR51)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Address
+0
+1
0x1DB0
0x1DB4
PPG(ch.51)Timing Point Capture value setting
register (PTPC51)
PPG(ch.52) control status register (PCN52)
PPG(ch.52) duty setting register (PDUT52)
0x1DB8
PPG(ch.52) control status register 2(PCN252)
0x1DAC
0x1DC0
0x1DC4
PPG(ch.52)Timing Point Capture value setting
register (PTPC52)
PPG(ch.53) control status register (PCN53)
PPG(ch.53) duty setting register (PDUT53)
0x1DC8
PPG(ch.53) control status register 2(PCN253)
0x1DBC
0x1DD0
0x1DD4
PPG(ch.53)Timing Point Capture value setting
register (PTPC53)
PPG(ch.54) control status register (PCN54)
PPG(ch.54) duty setting register (PDUT54)
0x1DD8
PPG(ch.54) control status register 2(PCN254)
0x1DCC
0x1DE0
0x1DE4
PPG(ch.54)Timing Point Capture value setting
register (PTPC54)
PPG(ch.55) control status register (PCN55)
PPG(ch.55) duty setting register (PDUT55)
0x1DE8
PPG(ch.55) control status register 2(PCN255)
0x1DDC
0x1DF0
0x1DF4
PPG(ch.55)Timing Point Capture value setting
register (PTPC55)
PPG(ch.56) control status register (PCN56)
PPG(ch.56) duty setting register (PDUT56)
0x1DF8
PPG(ch.56) control status register 2(PCN256)
0x1DEC
0x1E00
0x1E04
PPG(ch.56)Timing Point Capture value setting
register (PTPC56)
PPG(ch.57) control status register (PCN57)
PPG(ch.57) duty setting register (PDUT57)
0x1E08
PPG(ch.57) control status register 2(PCN257)
0x1DFC
0x1E10
0x1E14
PPG(ch.57)Timing Point Capture value setting
register (PTPC57)
PPG(ch.58) control status register (PCN58)
PPG(ch.58) duty setting register (PDUT58)
0x1E18
PPG(ch.58) control status register 2(PCN258)
0x1E0C
0x1E20
0x1E24
PPG(ch.58)Timing Point Capture value setting
register (PTPC58)
PPG(ch.59) control status register (PCN59)
PPG(ch.59) duty setting register (PDUT59)
0x1E28
PPG(ch.59) control status register 2(PCN259)
0x1E1C
+2
+3
Reserved
PPG(ch.52) cycle setting register (PCSR52)
PPG(ch.52) timer register (PTMR52)
PPG(ch.52)Start Delay value setting register
(PSDR52)
Reserved
PPG(ch.53) cycle setting register (PCSR53)
PPG(ch.53) timer register (PTMR53)
PPG(ch.53)Start Delay value setting register
(PSDR53)
Reserved
PPG(ch.54) cycle setting register (PCSR54)
PPG(ch.54) timer register (PTMR54)
PPG(ch.54)Start Delay value setting register
(PSDR54)
Reserved
PPG(ch.55) cycle setting register (PCSR55)
PPG(ch.55) timer register (PTMR55)
PPG(ch.55)Start Delay value setting register
(PSDR55)
Reserved
PPG(ch.56) cycle setting register (PCSR56)
PPG(ch.56) timer register (PTMR56)
PPG(ch.56)Start Delay value setting register
(PSDR56)
Reserved
PPG(ch.57) cycle setting register (PCSR57)
PPG(ch.57) timer register (PTMR57)
PPG(ch.57)Start Delay value setting register
(PSDR57)
Reserved
PPG(ch.58) cycle setting register (PCSR58)
PPG(ch.58) timer register (PTMR58)
PPG(ch.58)Start Delay value setting register
(PSDR58)
Reserved
PPG(ch.59) cycle setting register (PCSR59)
PPG(ch.59) timer register (PTMR59)
PPG(ch.59)Start Delay value setting register
(PSDR59)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
519
Chapter 18: PPG
Address
+0
+1
+2
0x1E30
0x1E34
PPG(ch.59)Timing Point Capture value setting
register (PTPC59)
PPG(ch.60) control status register (PCN60)
PPG(ch.60) duty setting register (PDUT60)
0x1E38
PPG(ch.60) control status register 2(PCN260)
0x1E2C
0x1E40
0x1E44
PPG(ch.60)Timing Point Capture value setting
register (PTPC60)
PPG(ch.61) control status register (PCN61)
PPG(ch.61) duty setting register (PDUT61)
0x1E48
PPG(ch.61) control status register 2(PCN261)
0x1E3C
0x1E50
0x1E54
PPG(ch.61)Timing Point Capture value setting
register (PTPC61)
PPG(ch.62) control status register (PCN62)
PPG(ch.62) duty setting register (PDUT62)
0x1E58
PPG(ch.62) control status register 2(PCN262)
0x1E4C
0x1E60
0x1E64
PPG(ch.62)Timing Point Capture value setting
register (PTPC62)
PPG(ch.63) control status register (PCN63)
PPG(ch.63) duty setting register (PDUT63)
0x1E68
PPG(ch.63) control status register 2(PCN263)
0x1E5C
0x1E70
0x1E74
PPG(ch.63)Timing Point Capture value setting
register (PTPC63)
PPG(ch.64) control status register (PCN64)
PPG(ch.64) duty setting register (PDUT64)
0x1E78
PPG(ch.64) control status register 2(PCN264)
0x1E6C
0x1E80
0x1E84
PPG(ch.64)Timing Point Capture value setting
register (PTPC64)
PPG(ch.65) control status register (PCN65)
PPG(ch.65) duty setting register (PDUT65)
0x1E88
PPG(ch.65) control status register 2(PCN265)
0x1E7C
0x1E90
0x1E94
PPG(ch.65)Timing Point Capture value setting
register (PTPC65)
PPG(ch.66) control status register (PCN66)
PPG(ch.66) duty setting register (PDUT66)
0x1E98
PPG(ch.66) control status register 2(PCN266)
0x1E8C
0x1EA0
0x1EA4
PPG(ch.66)Timing Point Capture value setting
register (PTPC66)
PPG(ch.67) control status register (PCN67)
PPG(ch.67) duty setting register (PDUT67)
0x1EA8
PPG(ch.67) control status register 2(PCN267)
0x1E9C
520
+3
Reserved
PPG(ch.60) cycle setting register (PCSR60)
PPG(ch.60) timer register (PTMR60)
PPG(ch.60)Start Delay value setting register
(PSDR60)
Reserved
PPG(ch.61) cycle setting register (PCSR61)
PPG(ch.61) timer register (PTMR61)
PPG(ch.61)Start Delay value setting register
(PSDR61)
Reserved
PPG(ch.62) cycle setting register (PCSR62)
PPG(ch.62) timer register (PTMR62)
PPG(ch.62)Start Delay value setting register
(PSDR62)
Reserved
PPG(ch.63) cycle setting register (PCSR63)
PPG(ch.63) timer register (PTMR63)
PPG(ch.63)Start Delay value setting register
(PSDR63)
Reserved
PPG(ch.64) cycle setting register (PCSR64)
PPG(ch.64) timer register (PTMR64)
PPG(ch.64)Start Delay value setting register
(PSDR64)
Reserved
PPG(ch.65) cycle setting register (PCSR65)
PPG(ch.65) timer register (PTMR65)
PPG(ch.65)Start Delay value setting register
(PSDR65)
Reserved
PPG(ch.66) cycle setting register (PCSR66)
PPG(ch.66) timer register (PTMR66)
PPG(ch.66)Start Delay value setting register
(PSDR66)
Reserved
PPG(ch.67) cycle setting register (PCSR67)
PPG(ch.67) timer register (PTMR67)
PPG(ch.67)Start Delay value setting register
(PSDR67)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Address
+0
+1
0x1EB0
0x1EB4
PPG(ch.67)Timing Point Capture value setting
register (PTPC67)
PPG(ch.68) control status register (PCN68)
PPG(ch.68) duty setting register (PDUT68)
0x1EB8
PPG(ch.68) control status register 2(PCN268)
0x1EAC
0x1EC0
0x1EC4
PPG(ch.68)Timing Point Capture value setting
register (PTPC68)
PPG(ch.69) control status register (PCN69)
PPG(ch.69) duty setting register (PDUT69)
0x1EC8
PPG(ch.69) control status register 2(PCN269)
0x1EBC
0x1ED0
0x1ED4
PPG(ch.69)Timing Point Capture value setting
register (PTPC69)
PPG(ch.70) control status register (PCN70)
PPG(ch.70) duty setting register (PDUT70)
0x1ED8
PPG(ch.70) control status register 2(PCN270)
0x1ECC
0x1EE0
0x1EE4
PPG(ch.70)Timing Point Capture value setting
register (PTPC70)
PPG(ch.71) control status register (PCN71)
PPG(ch.71) duty setting register (PDUT71)
0x1EE8
PPG(ch.71) control status register 2(PCN271)
0x1EDC
0x1EF0
0x1EF4
PPG(ch.71)Timing Point Capture value setting
register (PTPC71)
PPG(ch.72) control status register (PCN72)
PPG(ch.72) duty setting register (PDUT72)
0x1EF8
PPG(ch.72) control status register 2(PCN272)
0x1EEC
0x1F00
0x1F04
PPG(ch.72)Timing Point Capture value setting
register (PTPC72)
PPG(ch.73) control status register (PCN73)
PPG(ch.73) duty setting register (PDUT73)
0x1F08
PPG(ch.73) control status register 2(PCN273)
0x1EFC
0x1F10
0x1F14
PPG(ch.73)Timing Point Capture value setting
register (PTPC73)
PPG(ch.74) control status register (PCN74)
PPG(ch.74) duty setting register (PDUT74)
0x1F18
PPG(ch.74) control status register 2(PCN274)
0x1F0C
0x1F20
0x1F24
PPG(ch.74)Timing Point Capture value setting
register (PTPC74)
PPG(ch.75) control status register (PCN75)
PPG(ch.75) duty setting register (PDUT75)
0x1F28
PPG(ch.75) control status register 2(PCN275)
0x1F1C
+2
+3
Reserved
PPG(ch.68) cycle setting register (PCSR68)
PPG(ch.68) timer register (PTMR68)
PPG(ch.68)Start Delay value setting register
(PSDR68)
Reserved
PPG(ch.69) cycle setting register (PCSR69)
PPG(ch.69) timer register (PTMR69)
PPG(ch.69)Start Delay value setting register
(PSDR69)
Reserved
PPG(ch.70) cycle setting register (PCSR70)
PPG(ch.70) timer register (PTMR70)
PPG(ch.70)Start Delay value setting register
(PSDR70)
Reserved
PPG(ch.71) cycle setting register (PCSR71)
PPG(ch.71) timer register (PTMR71)
PPG(ch.71)Start Delay value setting register
(PSDR71)
Reserved
PPG(ch.72) cycle setting register (PCSR72)
PPG(ch.72) timer register (PTMR72)
PPG(ch.72)Start Delay value setting register
(PSDR72)
Reserved
PPG(ch.73) cycle setting register (PCSR73)
PPG(ch.73) timer register (PTMR73)
PPG(ch.73)Start Delay value setting register
(PSDR73)
Reserved
PPG(ch.74) cycle setting register (PCSR74)
PPG(ch.74) timer register (PTMR74)
PPG(ch.74)Start Delay value setting register
(PSDR74)
Reserved
PPG(ch.75) cycle setting register (PCSR75)
PPG(ch.75) timer register (PTMR75)
PPG(ch.75)Start Delay value setting register
(PSDR75)
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Chapter 18: PPG
Address
+0
+1
+2
0x1F30
0x1F34
PPG(ch.75)Timing Point Capture value setting
register (PTPC75)
PPG(ch.76) control status register (PCN76)
PPG(ch.76) duty setting register (PDUT76)
0x1F38
PPG(ch.76) control status register 2(PCN276)
0x1F2C
0x1F40
0x1F44
PPG(ch.76)Timing Point Capture value setting
register (PTPC76)
PPG(ch.77) control status register (PCN77)
PPG(ch.77) duty setting register (PDUT77)
0x1F48
PPG(ch.77) control status register 2(PCN277)
0x1F3C
0x1F50
0x1F54
PPG(ch.77)Timing Point Capture value setting
register (PTPC77)
PPG(ch.78) control status register (PCN78)
PPG(ch.78) duty setting register (PDUT78)
0x1F58
PPG(ch.78) control status register 2(PCN278)
0x1F4C
0x1F60
0x1F64
PPG(ch.78)Timing Point Capture value setting
register (PTPC78)
PPG(ch.79) control status register (PCN79)
PPG(ch.79) duty setting register (PDUT79)
0x1F68
PPG(ch.79) control status register 2(PCN279)
0x1F5C
0x1F70
0x1F74
PPG(ch.79)Timing Point Capture value setting
register (PTPC79)
PPG(ch.80) control status register (PCN80)
PPG(ch.80) duty setting register (PDUT80)
0x1F78
PPG(ch.80) control status register 2(PCN280)
0x1F6C
0x1F80
0x1F84
PPG(ch.80)Timing Point Capture value setting
register (PTPC80)
PPG(ch.81) control status register (PCN81)
PPG(ch.81) duty setting register (PDUT81)
0x1F88
PPG(ch.81) control status register 2(PCN281)
0x1F7C
0x1F90
0x1F94
PPG(ch.81)Timing Point Capture value setting
register (PTPC81)
PPG(ch.82) control status register (PCN82)
PPG(ch.82) duty setting register (PDUT82)
0x1F98
PPG(ch.82) control status register 2(PCN282)
0x1F8C
0x1FA0
0x1FA4
PPG(ch.82)Timing Point Capture value setting
register (PTPC82)
PPG(ch.83) control status register (PCN83)
PPG(ch.83) duty setting register (PDUT83)
0x1FA8
PPG(ch.83) control status register 2(PCN283)
0x1F9C
522
+3
Reserved
PPG(ch.76) cycle setting register (PCSR76)
PPG(ch.76) timer register (PTMR76)
PPG(ch.76)Start Delay value setting register
(PSDR76)
Reserved
PPG(ch.77) cycle setting register (PCSR77)
PPG(ch.77) timer register (PTMR77)
PPG(ch.77)Start Delay value setting register
(PSDR77)
Reserved
PPG(ch.78) cycle setting register (PCSR78)
PPG(ch.78) timer register (PTMR78)
PPG(ch.78)Start Delay value setting register
(PSDR78)
Reserved
PPG(ch.79) cycle setting register (PCSR79)
PPG(ch.79) timer register (PTMR79)
PPG(ch.79)Start Delay value setting register
(PSDR79)
Reserved
PPG(ch.80) cycle setting register (PCSR80)
PPG(ch.80) timer register (PTMR80)
PPG(ch.80)Start Delay value setting register
(PSDR80)
Reserved
PPG(ch.81) cycle setting register (PCSR81)
PPG(ch.81) timer register (PTMR81)
PPG(ch.81)Start Delay value setting register
(PSDR81)
Reserved
PPG(ch.82) cycle setting register (PCSR82)
PPG(ch.82) timer register (PTMR82)
PPG(ch.82)Start Delay value setting register
(PSDR82)
Reserved
PPG(ch.83) cycle setting register (PCSR83)
PPG(ch.83) timer register (PTMR83)
PPG(ch.83)Start Delay value setting register
(PSDR83)
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Chapter 18: PPG
Address
+0
+1
0x1FB0
0x1FB4
PPG(ch.83)Timing Point Capture value setting
register (PTPC83)
PPG(ch.84) control status register (PCN84)
PPG(ch.84) duty setting register (PDUT84)
0x1FB8
PPG(ch.84) control status register 2(PCN284)
0x1FAC
0x1FC0
0x1FC4
PPG(ch.84)Timing Point Capture value setting
register (PTPC84)
PPG(ch.85) control status register (PCN85)
PPG(ch.85) duty setting register (PDUT85)
0x1FC8
PPG(ch.85) control status register 2(PCN285)
0x1FBC
0x1FD0
0x1FD4
PPG(ch.85)Timing Point Capture value setting
register (PTPC85)
PPG(ch.86) control status register (PCN86)
PPG(ch.86) duty setting register (PDUT86)
0x1FD8
PPG(ch.86) control status register 2(PCN286)
0x1FCC
0x1FE0
0x1FE4
PPG(ch.86)Timing Point Capture value setting
register (PTPC86)
PPG(ch.87) control status register (PCN87)
PPG(ch.87) duty setting register (PDUT87)
0x1FE8
PPG(ch.87) control status register 2(PCN287)
0x1FEC
PPG(ch.87)Timing Point Capture value setting
register (PTPC87)
0x1FDC
+2
+3
Reserved
PPG(ch.84) cycle setting register (PCSR84)
PPG(ch.84) timer register (PTMR84)
PPG(ch.84)Start Delay value setting register
(PSDR84)
Reserved
PPG(ch.85) cycle setting register (PCSR85)
PPG(ch.85) timer register (PTMR85)
PPG(ch.85)Start Delay value setting register
(PSDR85)
Reserved
PPG(ch.86) cycle setting register (PCSR86)
PPG(ch.86) timer register (PTMR86)
PPG(ch.86)Start Delay value setting register
(PSDR86)
Reserved
PPG(ch.87) cycle setting register (PCSR87)
PPG(ch.87) timer register (PTMR87)
PPG(ch.87)Start Delay value setting register
(PSDR87)
Reserved
List of GATE Function Control Registers Map
Address
+0
+1
+2
+3
0x19DC
Reserved
GATE function control
register 0 (GATEC0)
Reserved
GATE function control
register 2 (GATEG2)
0x19E0
Reserved
GATE function control
register 4 (GATEC4)
Reserved
Reserved
+2
+3
List of PPG Control Registers Map
Address
+0
+1
0x19E8
General-purpose trigger selection register 0
(GTRS0)
General-purpose trigger selection register 1
(GTRS1)
0x19EC
General-purpose trigger selection register 2
(GTRS2)
General-purpose trigger selection register 3
(GTRS3)
0x19F0
General-purpose trigger selection register 4
(GTRS4)
General-purpose trigger selection register 5
(GTRS5)
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Chapter 18: PPG
Address
+0
+1
+2
+3
0x19F4
General-purpose trigger selection register 6
(GTRS6)
General-purpose trigger selection register 7
(GTRS7)
0x19F8
General-purpose trigger selection register 8
(GTRS8)
General-purpose trigger selection register 9
(GTRS9)
0x19FC
General-purpose trigger selection register 10
(GTRS10)
General-purpose trigger selection register 11
(GTRS11)
0x1A00
General-purpose trigger selection register 12
(GTRS12)
General-purpose trigger selection register 13
(GTRS13)
0x1A04
General-purpose trigger selection register 14
(GTRS14)
General-purpose trigger selection register 15
(GTRS15)
0x1A08
General-purpose trigger selection register 16
(GTRS16)
General-purpose trigger selection register 17
(GTRS17)
0x1A0C
General-purpose trigger selection register 18
(GTRS18)
General-purpose trigger selection register 19
(GTRS19)
0x1A10
General-purpose trigger selection register 20
(GTRS20)
General-purpose trigger selection register 21
(GTRS21)
0x1A14
General-purpose trigger selection register 22
(GTRS22)
General-purpose trigger selection register 23
(GTRS23)
0x1A18
General-purpose trigger selection register
(GTRS24)
General-purpose trigger selection register
(GTRS25)
0x1A1C
General-purpose trigger selection register
(GTRS26)
General-purpose trigger selection register
(GTRS27)
0x1A20
General-purpose trigger selection register
(GTRS28)
General-purpose trigger selection register
(GTRS29)
0x1A24
General-purpose trigger selection register
(GTRS30)
General-purpose trigger selection register
(GTRS31)
0x1A28
General-purpose trigger selection register
(GTRS32)
General-purpose trigger selection register
(GTRS33)
0x1A2C
General-purpose trigger selection register
(GTRS34)
General-purpose trigger selection register
(GTRS35)
0x1A30
General-purpose trigger selection register
(GTRS36)
General-purpose trigger selection register
(GTRS37)
0x1A34
General-purpose trigger selection register
(GTRS38)
General-purpose trigger selection register
(GTRS39)
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Chapter 18: PPG
Address
+0
+1
+2
+3
0x19D0
General-purpose trigger selection register
(GTRS40)
General-purpose trigger selection register
(GTRS41)
0x19D4
General-purpose trigger selection register
(GTRS42)
General-purpose trigger selection register
(GTRS43)
0x1A38
General-purpose trigger setting register 0
(GTREN0)
General-purpose trigger setting register 1
(GTREN1)
0x1A3C
General-purpose trigger setting register 2
(GTREN2)
General-purpose trigger setting register 3
(GTREN3)
0x19D8
General-purpose trigger setting register 4
(GTREN4)
General-purpose trigger setting register 5
(GTREN5)
4.1.
PPG Control Status Register : PCN0 to PCN 87
The bit configuration of PPG control status register is shown.
The PPG control status register (PCN) controls the operation and status of the PPG.
PPG CoNtrol status register (PCN): Address Base_addr + 00H (Access: Byte,
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CNTE
STRG
MDSE
RTRG
CKS1
CKS0
PGMS
OWFS
0
0
0
0
0
0
0
0
R/W
R0/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EGS1
EGS0
IREN
IRQF
IRS1
IRS0
Reserved
OSEL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R(RM1)/W
R/W
R/W
R/W0
R/W
Note:
The each bits of the PPG control status register (PCN), except for Bit13 MDSE: mode selection bit and Bit8 OWFS:
PPG output waveform selection bit, will become effective immediately by writing in the register.
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Chapter 18: PPG
[bit15] CNTE : Timer operation enable bit
CNTE
0
Explanation
The timer operation is stopped.
1
The timer operation is enabled.
This bit is the timer operation enable bit.
If this bit is set to "0", the PPG operation is stopped.
If this bit is set to "1", the PPG operation is enabled.
[bit14] STRG : Software trigger bit
STRG
0
Explanation
The operation is not influenced by the value written to this bit
(The read value is always "0").
The PPG is activated by a software trigger that is generated independent of the
external trigger (at the TRG pin). This trigger is not influenced by the trigger input
edge selection bits (EGS1, EGS0).
This bit is the software trigger bit.
If this bit is set to "0", the operation is not influenced by the value written to this bit.
If this bit is set to "1", The PPG is activated by a software trigger that is generated independent of the external trigger
(at the TRG pin). This trigger is not influenced by the trigger input edge selection bits (EGS1, EGS0).
1
[bit13] MDSE : Mode selection bit
MDSE
0
Explanation
PWM operation
1
One-shot operation
This bit selects type of output waveform.
If this bit is set to "0", the PWM operation is enabled and the consecutive pulse is generated.
If this bit is set to "1", the pulse is output only once.
Note:
This bit is effective for each cycle (trigger generation or counter borrow generation).
[bit12] RTRG : Restart enable bit
RTRG
0
Explanation
Restart disabled
1
Restart enabled
This bit enables/disables to restart PPG operation.
If this bit is set to "0", the PPG is disabled from restarting.
If this bit is set to "1", the PPG is enabled to restart. When the restart enable bit is set to "1", the PPG is enabled to
restart as triggered (by software/internal/external).
[bit11, bit10] CKS1, CKS0 : Count clock selection bits
CKS1, CKS0
0
526
0
Explanation
Peripheral clock (PCLK)
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Chapter 18: PPG
CKS1, CKS0
Explanation
0
1
Division of the peripheral clock frequency by 4
1
0
Division of the peripheral clock frequency by 16
1
1
Division of the peripheral clock frequency by 64
This bit is the count clock selection bits of down counter.
[bit9] PGMS : PPG output mask selection bit
PGMS
0
Explanation
No output mask
1
Output mask
This bit specifies whether to mask the PPG output.
If this bit is set to "0", the PPG output is not masked.
If this bit is set to "1", the PPG output is masked.
Note:
When this bit is set to "1", the PPG output can be clamped to "L" or "H" regardless of the mode selection, cycle, and
duty settings.
The output level can be specified by the PPG output polarity selection bit (PCN:OSEL).
(If OSEL = 0, the output is maintained at the "L" level.)
When this bit is set from "1" to "0" to cancel the PPG output mask, perform the setting within the period between the
beginning of cycle and the duty match.
[bit8] OWFS : PPG output waveform selection bit
OWFS
0
Explanation
Normal Wave Form is output.
1
Center Aligned Wave Form is output.
This bit selects the PPG output waveform.
If this bit is set to "0", the PPG outputs the Normal Wave Form.
If this bit is set to "1", the PPG outputs the Center Aligned Wave Form.
Note:
This bit is effective for each cycle (trigger generation or counter borrow generation).
[bit7, bit6] EGS1, EGS0 : Trigger input edge selection bits
EGS1, EGS0
Explanation
0
0
No edge selection (only software triggers are possible.)
0
1
Rising edge
1
0
Falling edge
1
1
Both edges (rising or falling)
These bits select the trigger input edge.
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Chapter 18: PPG
Note:
If EGS1=0 and EGS0=0, only the trigger with software trigger (PCN:STRG) is possible. The input from an external
trigger (TRG pin) to PPG is disabled.
Other settings of EGS1 and EGS0 influence only the input of an external trigger (TRG pin).
The trigger of PPG to start by writing "1" to the software trigger (PCN:STRG) is not influenced by the setting of
PCN:EGS1 and EGS0.
[bit5] IREN : Interrupt request enable bit
IREN
Explanation
0
Interrupt request disabled
1
Interrupt request enabled
This bit enables/disables interrupt requests.
If this bit is set to "0", interrupt requests are disabled.
If this bit is set to "1", interrupt requests are enabled.
[bit4] IRQF : Interrupt request flag bit
IRQF
Explanation
Read
Write
Read
Write
0
1
No interrupt request
Clears the interrupt request flag.
No interrupt request
Writing of "1" does not influence operation.
Note:
If this bit is set to "0" when the interrupt request flag (IRQF) = "1", the interrupt request flag (IRQF = 1) that is set by
hardware takes precedence.
[bit3, bit2] IRS1, IRS0 : Interrupt factor selection bits
IRS1, IRS0
Explanation
0
0
STGR=0: Software trigger or external trigger (TRG pin) input
STGR=1: GATE signal trigger input
0
1
Counter borrow occurrence
1
0
Counter and duty value match
1
1
Counter borrow occurrence or counter and duty value match
Note:
See the following figures for the relationship between output waveforms and interrupt generation locations:
In the case of the PPG output waveform selection bit (OWFS="0"):
Figure 5-1 Example of PWM Operation (Normal Wave Form Selected)
Figure 5-3 Example of One-shot Operation (Normal Wave Form Selected)
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Chapter 18: PPG
In the case of the PPG output waveform selection bit (OWFS="1"):
Figure 5-2 Example of PWM Operation (Center Aligned Wave Form Selected)
Figure 5-4 Example of One-shot Operation (Center Aligned Wave Form Selected)
[bit1] Reserved
This bit must be set to "0".
[bit0] OSEL : PPG output polarity selection bit
OSEL
0
Explanation
Normal polarity
1
Inverted polarity
This bit selects the PPG output polarity.
If this bit is set to "0", the normal polarity is selected.
If this bit is set to "1", the inverted polarity is selected.
Note:
If the PPG output mask selection bit (PCN:PGMS) is set to "1", setting the PPG output polarity selection bit (OSEL)
to "0" or "1" causes the output to be clamped to "L" or "H", respectively.
4.2.
PPG Cycle Setting Register : PCSR0 to PCSR87
The bit configuration of the PPG cycle setting register is shown.
The PPG cycle setting register (PCSR) specifies the cycle of the PPG output waveform.
PPG cycle setting register (PCSR): Address Base_addr + 02H (Access: Half-word,
Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
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Chapter 18: PPG
[bit15 to bit0] D15 to D0 : PPG cycle setting bits
D15 to D0
Function
Cycle of the PPG output waveform
These bits are write-only.
The PPG cycle setting register has a buffer.
Data transfer from the buffer to the counter occurs automatically when a borrow occurs on the counter.
Be sure to set the PPG duty setting register (PDUT) after the PPG cycle setting register is rewritten.
Notes:
If the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected, the waveform is
output at the cycle of a set value of PPG cycle setting register.
If the PPG output waveform selection bit (PCN.OWFS)="1" (Center Aligned Wave Form) is selected, the
waveform is output at twice the cycle of a set value of PPG cycle setting register.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
4.3.
PPG Duty Setting Register : PDUT0 to PDUT87
The bit configuration of the PPG duty setting register is shown.
The PPG duty setting register (PDUT) specifies the duty of the PPG output waveform.
PPG duty setting register (PDUT): Address Base_addr + 04H (Access: Half-word,
Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
[bit15 to bit0] D15 to D0 : PPG duty setting bits
D15 to D0
Function
Duty of the PPG output waveform
These bits are write-only.
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Chapter 18: PPG
The PPG duty setting register has a buffer.
Data transfer from the buffer to the counter occurs automatically when a borrow occurs on the counter.
Be sure to set a value that is smaller than the value set to the PPG cycle setting register (PCSR) to the PPG duty
setting register.
Notes:
If the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected, the waveform is
output at the duty of a set value of PPG duty setting register.
If the PPG output waveform selection bit (PCN.OWFS)="1" (Center Aligned Wave Form) is selected, the
waveform is output at twice the duty of a set value of PPG duty setting register.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed the value is not written at
an upper and lower bit position.
4.4.
PPG Timer Register : PTMR0 to PTMR87
The bit configuration of the PPG timer register is shown.
The PPG timer register (PTMR) allows the PPG timer countdown value to be read.
PPG timer register (PTMR): Address Base_addr + 06H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
1
1
1
1
1
1
1
1
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15 to bit0] D15 to D0 : PPG timer value bits
D15 to D0
Function
Timer down count value
These bits are read-only.
The count value of the 17-bit down counter can be read from these bits.
If the Normal Wave Form (OWFS="0") is selected, the lower 16 bits are read.
If the Center Aligned Wave Form (OWFS="1") is selected, the upper 16 bits are read.
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Chapter 18: PPG
4.5.
PPG Control Status Register2 : PCN200 to PCN287
The bit configuration of the PPG control status register2 is shown.
The PPG control status register2 (PCN2) controls the operation and status of the PPG.
PPG control status register2 (PCN2): Address Base_addr + 08H (Access: Byte,
Half-word, Word)
bit15
bit14
Reserved Reserved
Initial value
Attribute
bit13
bit12
bit11
bit10
bit9
bit8
LFPR
HFPR
CMDSEL
CMD
TPC
STRD
0
0
0
0
0
0
0
0
R0/W0
R0/W0
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
REMP
SREMP
IRS2
Reserved Reserved Reserved Reserved Reserved
Initial value
Attribute
0
0
0
0
0
1
1
0
R0/W0
R0/W0
R0/W0
R0/W0
R0/W0
R,W0
R,W0
R/W
[bit15, bit14] Reserved bits
The read value of these bits is always "0".
These bits must always be written to "0".
[bit13] LFPR : Low format pulse polarity selection bit
LFPR
Explanation
0
Output from Low pulse
(When PCN.OSEL=1: the High pulse output)
1
Output from High pulse
(When PCN.OSEL=1: the Low pulse output)
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "0". This bit
must always be written to "0".
[bit12] HFPR : High format pulse polarity selection bit
HFPR
532
Explanation
0
Output from Low pulse
(When PCN.OSEL=1: the High pulse output)
1
Output from High pulse
(When PCN.OSEL=1: the Low pulse output)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "0". This bit
must always be written to "0".
[bit11] CMDSEL : PPG communication mode data read selection bit
CMDSEL
Explanation
0
Output from LSB bit position of PCMDDT set in PCMDWD
1
Output from MSB bit position of PCMDDT set in PCMDWD
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "0". This bit
must always be written to "0".
[bit10] CMD : PPG communication mode enable bit
CMD
Explanation
0
PPG communication mode disable
1
PPG communication mode enable
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "0". This bit
must always be written to "0".
[bit9] TPC : Timing Point Capture enable bit
TPC
Explanation
0
Timing Point Capture mode disable
1
Timing Point Capture mode enable
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "0". This bit
must always be written to "0".
[bit8] STRD : Start Delay mode enable bit
STRD
Explanation
0
Start Delay mode disable
1
Start Delay mode enable
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533
Chapter 18: PPG
[bit7 to bit3] Reserved bits
The read value of these bits is always "0".
These bits must always be written to "0".
[bit2] REMP : PPG communication data register Empty flag bit
REMP
Explanation
0
No interrupt (state of Not Empty)
1
Interrupt (state of Empty)
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "1".
[bit1] SREMP : PPG communication data shift register Empty flag bit
SREMP
Explanation
0
No interrupt (state of Not Empty)
1
Interrupt (state of Empty)
Note:
In PPG4 to PPG87, the communication function is not built into. The read value of this bit is always "1".
[bit0] IRS2 : Interrupt factor selection2 bit
IRS2 IRS1 IRS0
0
0
0
STGR=0 : Software trigger or external trigger (TRG pin) input
STGR=1 : GATE signal trigger input
0
0
1
Borrow occurrence on the counter
0
1
0
Counter matched with the specified duty value
0
1
1
Borrow occurrence on the counter or counter matched with the specified
duty value
1
0
0
Timing Point Capture value match
Other value
534
Explanation
PPG communication data register Empty factor
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
4.6.
Start Delay Value Setting Register : PSDR0 to PSDR87
The bit configuration of the Start Delay value setting register is shown.
The Start Delay value setting register (PSDR) sets the delay value to shift the phase of PPG output waveform.
Start Delay value setting register (PSDR): Address Base_addr + 0AH (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] D15 to D0 : Start Delay value setting bits
The phase from the activation trigger generation to PPG waveform output is adjusted according to the following
calculations.
(Start Delay value setting register + 1) Count clock
Notes:
If the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected, the delay value is
the set value of the Start Delay value setting register.
If the PPG output waveform selection bit (PCN.OWFS)="1" (Center Aligned Wave Form) is selected, the delay
value is doubling the set value of the Start Delay value setting register.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
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535
Chapter 18: PPG
4.7.
Timing Point Capture Value Setting Register : PTPC0 to
PTPC87
The bit configuration of the Timing Point Capture value setting register is shown.
Timing Point Capture sets the timing that generates an interrupt and the A/D activation trigger.
Timing Point Capture value setting register (PTPC): Address Base_addr + 0CH
(Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] D15 to D0 : Timing Point Capture value setting bits
These bits set the timing that generates an interrupt and the A/D activation trigger.
Interrupt and A/D activation trigger is generated according to the timing after (Timing Point Capture setting value + 1
(*)) from the activation trigger. (*: When OWFS=0 is set)
Notes:
Be sure to set the register to become "Timing Point Capture setting value < PPG cycle setting value".
The value when the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected is set
to the Timing Point Capture value.
If the PPG output waveform selection bit (PCN.OWFS)="1" (Center Aligned Wave Form) is selected, a set value
of the Timing Point Capture value setting register is doubling (PCN.OWFS)="0".
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
536
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Chapter 18: PPG
4.8.
PPG Communication Mode High Format Cycle Setting
Register : PHCSR0 to PHCSR3
The bit configuration of the PPG communication mode High format cycle setting register is shown.
The PPG communication mode High format cycle setting register (PHCSR) sets the cycle for the High format.
PPG communication mode High format cycle setting register (PHCSR): Address
Base_addr + 10H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
[bit15 to bit0] D15 to D0 : PPG communication mode High format cycle setting bits
When borrow of the counter is generated, the value is automatically transferred from the PPG communication mode
High format cycle setting register to the counter.
Notes:
In the PPG communication mode, the setting of PPG output waveform selection bit (PCN.OWFS) and mode
selection bit (PCN.MDSE) does not influence operation.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
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537
Chapter 18: PPG
4.9.
PPG Communication Mode Low Format Cycle Setting
Register : PLCSR0 to PLCSR3
The bit configuration of the PPG communication mode Low format cycle setting register is shown.
The PPG communication mode Low format cycle setting register (PLCSR) sets the cycle for the Low format.
PPG communication mode Low format cycle setting register (PLCSR): Address
Base_addr + 12H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
[bit15 to bit0] D15 to D0 : PPG communication mode Low format cycle setting bits
When borrow of the counter is generated, the value is automatically transferred from the PPG communication mode
Low format cycle setting register to the counter.
Notes:
In the PPG communication mode, the setting of PPG output waveform selection bit (PCN.OWFS) and mode
selection bit (PCN.MDSE) does not influence operation.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
538
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Chapter 18: PPG
4.10. PPG Communication Mode High Format Duty Setting
Register : PHDUT0 to PHDUT3
The bit configuration of the PPG communication mode High format duty setting register is shown.
The PPG communication mode High format duty setting register (PHDUT) sets the duty for the High format.
PPG communication mode High format duty setting register (PHDUT): Address
Base_addr + 14H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
[bit15 to bit0] D15 to D0 : PPG communication mode High format duty setting bits
When borrow of the counter is generated, the value is automatically transferred from the PPG communication mode
High format duty setting register to the counter.
Notes:
Be sure to set a value that is smaller than the value set to the PPG communication mode High format cycle setting
register (PHCSR) to the PPG communication mode High format duty setting register.
In the PPG communication mode, the setting of PPG output waveform selection bit (PCN.OWFS) and mode
selection bit (PCN.MDSE) does not influence operation.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
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539
Chapter 18: PPG
4.11. PPG Communication Mode Low Format Duty Setting
Register : PLDUT0 to PLDUT3
The bit configuration of the PPG communication mode Low format duty setting register is shown.
The PPG communication mode Low format duty setting register (PLDUT) sets the duty for the Low
format.
PPG communication mode Low format duty setting register (PLDUT): Address
Base_addr + 16H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
[bit15 to bit0] D15 to D0 : PPG communication mode Low format duty setting bits
When borrow of the counter is generated, the value is automatically transferred from the PPG communication mode
Low format duty setting register to the counter.
Notes:
Be sure to set a value that is smaller than the value set to the PPG communication mode Low format cycle setting
register (PLCSR) to the PPG communication mode Low format duty setting register.
In the PPG communication mode, the setting of PPG output waveform selection bit (PCN.OWFS) and mode
selection bit (PCN.MDSE) does not influence operation.
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written
at an upper and lower bit position.
540
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
4.12. PPG Communication Mode Data Setting Register :
PCMDDT0 to PCMDDT3
The bit configuration of the PPG communication mode data setting register is shown.
The PPG communication mode data setting register (PCMDDT) sets the control of the High/Low format waveform
output.
PPG communication mode data setting register (PCMDDT): Address Base_addr +
18H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] D15 to D0 : PPG communication mode data setting bits
These bits control the PPG High/Low format waveform output.
When the register setting value is "1", the High format waveform is output. When the register setting value is "0", the
Low format waveform is output.
Note:
Be sure to access this register by the word (16-bit) format. If this register is byte accessed, the value is not written at
an upper and lower bit position.
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541
Chapter 18: PPG
4.13. PPG Communication Mode Data Bit Length Setting
Register : PCMDWD0 to PCMDWD3
The bit configuration of the PPG communication mode data bit length setting register is shown.
The PPG communication mode data bit length setting register (PCMDWD) sets the bit length of the High/Low format
waveform output.
PPG communication mode data bit length setting register (PCMDWD): Address
Base_addr + 0EH (Byte, Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
R1/W1
R1/W1
R1/W1
R1/W1
R1/W1
R1/W1
R1/W1
R1/W1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Reserved
Reserved
Reserved
D3
D2
D1
D0
0
0
0
0
0
0
0
0
R0/W0
R0/W0
R0/W0
R0/W0
R/W
R/W
R/W
R/W
[bit15 to bit8] Reserved bits
The read value of these bits is always "1".
These bits must always be written to "1".
[bit7 to bit4] Reserved bits
The read value of these bits is always "0".
These bits must always be written to "0".
[bit3 to bit0] D3 to D0 : PPG communication mode data bit length setting bits
These bits control the bit length of the PPG High/Low format waveform output.
"0000b"
"0001b"
"0010b"
"0011b"
"0100b"
"0101b"
"0110b"
"0111b"
"1000b"
"1001b"
"1010b"
"1011b"
"1100b"
"1101b"
542
; PPG communication 1 bit
: PPG communication 2 bits
: PPG communication 3 bits
: PPG communication 4 bits
: PPG communication 5 bits
: PPG communication 6 bits
: PPG communication 7 bits
: PPG communication 8 bits
: PPG communication 9 bits
: PPG communication 10 bits
: PPG communication 11 bits
: PPG communication 12 bits
: PPG communication 13 bits
: PPG communication 14 bits
(PCMDDT bit0)
(PCMDDT bit1 to bit0)
(PCMDDT bit2 to bit0)
(PCMDDT bit3 to bit0)
(PCMDDT bit4 to bit0)
(PCMDDT bit5 to bit0)
(PCMDDT bit6 to bit0)
(PCMDDT bit7 to bit0)
(PCMDDT bit8 to bit0)
(PCMDDT bit9 to bit0)
(PCMDDT bit10 to bit0)
(PCMDDT bit11 to bit0)
(PCMDDT bit12 to bit0)
(PCMDDT bit13 to bit0)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
"1110b"
"1111b"
: PPG communication 15 bits (PCMDDT bit14 to bit0)
: PPG communication 16 bits (PCMDDT bit15 to bit0)
4.14. GATE Function Control Register : GATEC0, GATEC2,
GATEC4
The bit configuration of the GATE function control register is shown.
The GATE function control register (GATEC) controls the operation of the GATE function.
GATE function control register (GATEC): Address 19DDH, 19DFH, 19E1H (Access:
Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
STGR
EDGE
0
0
0
0
0
0
0
0
R0/W0
R0/W0
R0/W0
R0/W0
R0/W0
R0/W0
R/W
R/W
Initial value
Attribute
[bit7 to bit2] Reserved bits
The read value of these bits is always "0".
These bits must always be written to "0".
[bit1] STGR : GATE function selection bit
STGR
Explanation
0
PPG is activated by the activation trigger.
1
PPG is activated and stopped according to the GATE signal from a waveform generator.
[bit0] EDGE : GATE function activation effective edge selection bit
EDGE
Explanation
0
PPG is activated by the rising of the GATE signals, and stopped by the falling.
PPG activates during "H".
1
PPG is activated by the falling of the GATE signals, and stopped by the rising.
PPG activates during "L".
Note:
Be sure to set GATE function control register (GATEC) before activating PPG. Please change neither the GATE
selection bit (STGR) nor polarity selection bit (EDGE) of the GATE function control register (GATEC) during the
PPG operation.
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543
Chapter 18: PPG
4.15. General-purpose Trigger Selection Register : GTRS0 to
GTRS43
The bit configuration of the general-purpose trigger selection register is shown.
The General-purpose trigger selection register (GTRS) is used to select the trigger input to PPG.
General-purpose trigger selection register (GTRS): Address 19E8H to 1A36 H, 19D0H
to 19D6H (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
TSELii_6
TSELii_5
TSELii_4
TSELii_3
TSELii_2
TSELii_1
TSELii_0
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
TSELii_6
TSELii_5
TSELii_4
TSELii_3
TSELii_2
TSELii_1
TSELii_0
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
Attribute
Initial value
Attribute
"ii" of "TSELii_" is an index that shows the number of PPG0 to PPG87.
[bit15] / [bit7] Reserved bits
The read value of these bits is always "0".
Writing has no effect on operation.
[bit14 to bit8] / [bit6 to bit0] TSELii [6:0]: Activation trigger selection bits
bit14 to bit8 : selection bit of the activation trigger of PPG2n+1(n=0 to 43).
bit6 to bit0 : selection bit of the activation trigger of PPG2n(n=0 to 43).
TSELii [6:0]
544
Activation trigger selection
0
0
0
0
0
0
0
Internal trigger (EN0) selected
0
0
0
0
0
0
1
Internal trigger (EN1) selected
0
0
0
0
0
1
0
Internal trigger (EN2) selected
0
0
0
0
0
1
1
Internal trigger (EN3) selected
0
0
0
0
1
0
0
Internal trigger (EN4) selected
0
0
0
0
1
0
1
Internal trigger (EN5) selected
0
0
0
0
1
1
0
Internal trigger (EN6) selected
0
0
0
0
1
1
1
Internal trigger (EN7) selected
0
0
0
1
0
0
0
Internal trigger (EN8) selected
0
0
0
1
0
0
1
Internal trigger (EN9) selected
0
0
0
1
0
1
0
Internal trigger (EN10) selected
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
TSELii [6:0]
Activation trigger selection
0
0
0
1
0
1
1
Internal trigger (EN11) selected
0
0
0
1
1
0
0
Internal trigger (EN12) selected
0
0
0
1
1
0
1
Internal trigger (EN13) selected
0
0
0
1
1
1
0
Internal trigger (EN14) selected
0
0
0
1
1
1
1
Internal trigger (EN15) selected
0
0
1
0
0
0
0
Internal trigger (EN16) selected
0
0
1
0
0
0
1
Internal trigger (EN17) selected
0
0
1
0
0
1
0
Internal trigger (EN18) selected
0
0
1
0
0
1
1
Internal trigger (EN19) selected
0
0
1
0
1
0
0
Internal trigger (EN20) selected
0
0
1
0
1
0
1
Internal trigger (EN21) selected
0
0
1
0
1
1
0
Internal trigger (EN22) selected
0
0
1
0
1
1
1
Internal trigger (EN23) selected
0
0
1
1
0
0
0
Internal trigger (EN24) selected
0
0
1
1
0
0
1
Internal trigger (EN25) selected
0
0
1
1
0
1
0
Internal trigger (EN26) selected
0
0
1
1
0
1
1
Internal trigger (EN27) selected
0
0
1
1
1
0
0
Internal trigger (EN28) selected
0
0
1
1
1
0
1
Internal trigger (EN29) selected
0
0
1
1
1
1
0
Internal trigger (EN30) selected
0
0
1
1
1
1
1
Internal trigger (EN31) selected
0
1
0
0
0
0
0
Internal trigger (EN32) selected
0
1
0
0
0
0
1
Internal trigger (EN33) selected
0
1
0
0
0
1
0
Internal trigger (EN34) selected
0
1
0
0
0
1
1
Internal trigger (EN35) selected
0
1
0
0
1
0
0
Internal trigger (EN36) selected
0
1
0
0
1
0
1
Internal trigger (EN37) selected
0
1
0
0
1
1
0
Internal trigger (EN38) selected
0
1
0
0
1
1
1
Internal trigger (EN39) selected
0
1
0
1
0
0
0
Internal trigger (EN40) selected
0
1
0
1
0
0
1
Internal trigger (EN41) selected
0
1
0
1
0
1
0
Internal trigger (EN42) selected
0
1
0
1
0
1
1
Internal trigger (EN43) selected
0
1
0
1
1
0
0
Internal trigger (EN44) selected
0
1
0
1
1
0
1
Internal trigger (EN45) selected
0
1
0
1
1
1
0
Internal trigger (EN46) selected
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Chapter 18: PPG
TSELii [6:0]
546
Activation trigger selection
0
1
0
1
1
1
1
Internal trigger (EN47) selected
0
1
1
1
1
1
0
16-bit reload timer 0 selected
0
1
1
1
1
1
1
16-bit reload timer 1 selected
1
0
0
0
0
0
0
External trigger 0 selected
1
0
0
0
0
0
1
External trigger 1 selected
1
0
0
0
0
1
0
External trigger 2 selected
1
0
0
0
0
1
1
External trigger 3 selected
1
0
0
0
1
0
0
External trigger 4 selected
1
0
0
0
1
0
1
External trigger 5 selected
1
0
0
0
1
1
0
External trigger 6 selected
1
0
0
0
1
1
1
External trigger 7 selected
1
0
0
1
0
0
0
External trigger 8 selected
1
0
0
1
0
0
1
External trigger 9 selected
1
0
0
1
0
1
0
External trigger 10 selected
1
0
0
1
0
1
1
External trigger 11 selected
1
0
0
1
1
0
0
External trigger 12 selected
1
0
0
1
1
0
1
External trigger 13 selected
1
0
0
1
1
1
0
External trigger 14 selected
1
0
0
1
1
1
1
External trigger 15 selected
1
0
1
0
0
0
0
External trigger 16 selected
1
0
1
0
0
0
1
External trigger 17 selected
1
0
1
0
0
1
0
External trigger 18 selected
1
0
1
0
0
1
1
External trigger 19 selected
1
0
1
0
1
0
0
External trigger 20 selected
1
0
1
0
1
0
1
External trigger 21 selected
1
0
1
0
1
1
0
Internal trigger (EN48) selected
1
0
1
0
1
1
1
Internal trigger (EN49) selected
1
0
1
1
0
0
0
Internal trigger (EN50) selected
1
0
1
1
0
0
1
Internal trigger (EN51) selected
1
0
1
1
0
1
0
Internal trigger (EN52) selected
1
0
1
1
0
1
1
Internal trigger (EN53) selected
1
0
1
1
1
0
0
Internal trigger (EN54) selected
1
0
1
1
1
0
1
Internal trigger (EN55) selected
1
0
1
1
1
1
0
Internal trigger (EN56) selected
1
0
1
1
1
1
1
Internal trigger (EN57) selected
1
1
0
0
0
0
0
Internal trigger (EN58) selected
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
TSELii [6:0]
Activation trigger selection
1
1
0
0
0
0
1
Internal trigger (EN59) selected
1
1
0
0
0
1
0
Internal trigger (EN60) selected
1
1
0
0
0
1
1
Internal trigger (EN61) selected
1
1
0
0
1
0
0
Internal trigger (EN62) selected
1
1
0
0
1
0
1
Internal trigger (EN63) selected
1
1
0
0
1
1
0
Internal trigger (EN64) selected
1
1
0
0
1
1
1
Internal trigger (EN65) selected
1
1
0
1
0
0
0
Internal trigger (EN66) selected
1
1
0
1
0
0
1
Internal trigger (EN67) selected
1
1
0
1
0
1
0
Internal trigger (EN68) selected
1
1
0
1
0
1
1
Internal trigger (EN69) selected
1
1
0
1
1
0
0
Internal trigger (EN70) selected
1
1
0
1
1
0
1
Internal trigger (EN71) selected
1
1
0
1
1
1
0
Internal trigger (EN72) selected
1
1
0
1
1
1
1
Internal trigger (EN73) selected
1
1
1
0
0
0
0
Internal trigger (EN74) selected
1
1
1
0
0
0
1
Internal trigger (EN75) selected
1
1
1
0
0
1
0
Internal trigger (EN76) selected
1
1
1
0
0
1
1
Internal trigger (EN77) selected
1
1
1
0
1
0
0
Internal trigger (EN78) selected
1
1
1
0
1
0
1
Internal trigger (EN79) selected
1
1
1
0
1
1
0
Internal trigger (EN80) selected
1
1
1
0
1
1
1
Internal trigger (EN81) selected
1
1
1
1
0
0
0
Internal trigger (EN82) selected
1
1
1
1
0
0
1
Internal trigger (EN83) selected
1
1
1
1
0
1
0
Internal trigger (EN84) selected
1
1
1
1
0
1
1
Internal trigger (EN85) selected
1
1
1
1
1
0
0
Internal trigger (EN86) selected
1
1
1
1
1
0
1
Internal trigger (EN87) selected
Other settings
Setting prohibited
Note:
A trigger input to PPG is selected.
On selected PPGn, the PPG will be activated when the edge selected by the trigger input edge selection bits
(PCN:EGS1, RGS0) is detected upon the selected activation trigger.
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547
Chapter 18: PPG
4.16. General-purpose Trigger Setting Register : GTREN0 to
GTREN5
The bit configuration of the general-purpose trigger setting register is shown.
The general-purpose trigger setting register (GTREN) controls the generation of internal trigger to the PPG.
General-purpose trigger setting register 0 (GTREN0): Address 1A38H (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN15
EN14
EN13
EN12
EN11
EN10
EN9
EN8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
General-purpose trigger setting register 1 (GTREN1): Address 1A3AH (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
548
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN31
EN30
EN29
EN28
EN27
EN26
EN25
EN24
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN23
EN22
EN21
EN20
EN19
EN18
EN17
EN16
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
General-purpose trigger setting register 2 (GTREN2): Address 1A3CH (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN47
EN46
EN45
EN44
EN43
EN42
EN41
EN40
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN39
EN38
EN37
EN36
EN35
EN34
EN33
EN32
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
General-purpose trigger setting register 3 (GTREN3): Address 1A3EH (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN63
EN62
EN61
EN60
EN59
EN58
EN57
EN56
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN55
EN54
EN53
EN52
EN51
EN50
EN49
EN48
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
General-purpose trigger setting register 4 (GTREN4): Address 19D8H (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN79
EN78
EN77
EN76
EN75
EN74
EN73
EN72
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN71
EN70
EN69
EN68
EN67
EN66
EN65
EN64
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
549
Chapter 18: PPG
General-purpose trigger setting register 5 (GTREN5): Address 19DAH (Access:
Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
R1/W
R1/W
R1/W
R1/W
R1/W
R1/W
R1/W
R1/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN39
EN38
EN37
EN36
EN35
EN34
EN33
EN32
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit8] Reserved bits
These bits always read "1". Writing has no effect on operation.
GTREN0, GTREN1, GTREN2, GTREN3, GTREN4, and GTREN5 EN87 to EN0 Internal trigger input bits
EN87 to EN0
0
Explanation
Sets the level to "L".
1
Sets the level to "H".
These bits are used to generate a trigger at a specified internal trigger level.
If these bits are set to "0", a level "L" trigger is generated.
If these bits are set to "1", a level "H" trigger is generated.
Notes:
If an internal trigger (one of EN0 to EN87) is selected by the PPG activation trigger selection bits (TSELii_[6:0]),
the selected EN serves as the PPG trigger input bit.
When the state selected by the trigger input edge selection bits (PCN:EGS1, EGS0) is generated by software with
the use of the trigger input bit (selected one of EN0 to EN87), the trigger input bit serves as the PPG activation
trigger.
550
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
5. Operation
This section explains the operation of the PPG.
5.1. PWM Operation (Normal Wave Form)
5.2. PWM Operation (Center Aligned Wave Form Selected)
5.3. One-shot Operation (Normal Wave Form Selected)
5.4. One-shot Operation (Center Aligned Wave Form Selected)
5.5. Restart Operation
5.6. GATE Operation
5.7. Start Delay Mode Operation (PWM Normal Wave Form Selected)
5.8. Timing Point Capture Mode Operation (PWM Normal Wave Form Selected)
5.9. PPG Communication Mode Operation
5.10. PPG Communication Activation
5.11. PPG Communication Operation
5.12. PPG Communication Forced Stop and Restart operation
5.13. PPG Output Pulse Polarity Selection
5.14. Interrupt
5.1.
PWM Operation (Normal Wave Form)
The PWM operation (Normal Wave Form) is explained.
During the PWM operation, variable-duty pulses are output at the PPG pin.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
551
Chapter 18: PPG
Figure 5-1 Example of PWM Operation (Normal Wave Form Selected)
(3)
Enable PPG operation
CNTE
(4)
Activation trigger
(1)
PCSR
PDUT
Buffer
(cycle value)
Buffer
(duty value)
8000
8000
0007
0005
(2) Writing
(6) Rewriting
8000
8000
(5) Load
(13) Load
0007
0005
(5) Load
(13) Load
Down count
value (PTMR)
Reload
Reload
(7) Down count
(8) Match
0007
Match
0005
Match
(10) Down count
(11) Borrow
(9) Inversion
PPG pin output
(12) Clear
Borrow
Inversion
Clear
Inversion
Normal polarity
Duty
Cycle
Inverted polarity
Interrupt factor
Valid edge
552
Duty match
Counter borrow
Duty match
Counter borrow
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Writing of PCSR (cycle value)
Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Enabling of PPG operation
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
Rewriting of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
Repetition of steps (7) to (13)
Calculation formulas:
Cycle = {Cycle value (PCSR) + 1} Count clock
Duty = {Duty value (PDUT) + 1} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
553
Chapter 18: PPG
5.2.
PWM Operation (Center Aligned Wave Form Selected)
The PWM operation (Center Aligned Wave Form selected) is explained.
During the PWM operation, variable-duty pulses are output at the PPG pin. If the PPG output waveform selection bit
(PCN:OWFS)="1" is selected (Center Aligned Wave Form), the output waveform is generated by doubling the value
of the PPG cycle setting register (PCSR) and the value of the PPG duty setting register (PDUT)
Figure 5-2 Example of PWM Operation (Center Aligned Wave Form Selected)
(3)
Enable PPG operation
CNTE
(4)
Activation trigger
(1)
PCSR
8000
PDUT
8000
0007
0005
(2)Writing
Buffer
(cycle value)
(6)Rewriting
8000
8000
(5)Load
(16)Load
Buffer
(Duty value)
8008
8006
Buffer
(Duty value end-point)
7FF8
7FFC
(5)Load
Down count value
(PTMR)
(16)Load
(7)Down count
(8)Match
8008
8006
Match
(10)Down count
(11)Match
7FFC
7FF8
Match
(13)Down count
(14)Borrow
(9)Inversion
(12)Clear
(15)Clear
PPG pin output
Borrow
Inversion
Clear
Clear
Inversion
Normal
plarity
Normal
polarity
Duty X2
Cycle X2
Inverted polarity
Interrupt factor
Valid edge
554
Duty match
Counter borrow
Duty match
Counter borrow
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
Writing of PCSR (cycle value)
Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Enabling of PPG operation
Activation trigger generation
Loading of the [(Cycle value) 2 + 1] to the down count value (PTMR) and the duty value to the
buffer (duty value) and the buffer (duty value end point)
Duty value
(Output level inversion timing) = (Duty value + Cycle value + 1)
Duty value end point (Output level clear timing)
= (Cycle value - Duty value - 1)
Rewriting of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Counter decrement
The down counter matches the duty value (output level inversion timing)
Output level inversion at the PPG pin
Counter decrement
The down counter matches the duty value end point (output level clear timing)
Clearing of PPG pin output level (restoration to normal state)
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the [(Cycle value) 2 + 1] to the down count value (PTMR) and the duty value to the
buffer (duty value) and the buffer (duty value end point)
Repetition of steps (7) to (16)
Calculation formulas:
Cycle = {(Cycle value (PCSR) + 1) 2} Count clock
Duty = {(Duty value (PDUT) + 1) 2} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
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555
Chapter 18: PPG
5.3.
One-shot Operation (Normal Wave Form Selected)
The One-shot operation (Normal Wave Form selected) is explained.
During the one-shot operation, one-shot pulses are output at the PPG pin.
Figure 5-3 Example of One-shot Operation (Normal Wave Form Selected)
(3)
Enable PPG operation
CNTE
(4)
Activation trigger
(1)
PCSR
PDUT
8000
0007
(2) Writing
Buffer
(cycle value)
8000
(5) Load
Buffer
(duty value)
0007
(5) Load
Down count
value (PTMR)
(6) Down count
(7) Match
0007
(9) Down count
(10) Borrow
(8) Inversion
PPG pin output
(11) Clear
Normal polarity
Duty
Cycle
Inverted polarity
Interrupt factor
Valid edge
556
Duty match
Counter borrow
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
Writing of PCSR (cycle value)
Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Enabling of PPG operation
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
(6) Counter decrement
(7) The down counter matches the duty value
(8) Output level inversion at the PPG pin
(9) Counter decrement
(10) Counter borrow occurrence
(11) Clearing of PPG pin output level (restoration to normal state)
(12) End of operation sequence
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
557
Chapter 18: PPG
5.4.
One-shot Operation (Center Aligned Wave Form Selected)
The One-shot operation (Center Aligned Wave Form selected) is explained.
During the one-shot operation, one-shot pulses are output at the PPG pin. If the PPG output waveform selection bit
(PCN.OWFS)="1" is selected (Center Aligned Wave Form), the output waveform is generated by doubling the value
of the PPG cycle setting register (PCSR) and the value of the PPG duty setting register (PDUT).
Figure 5-4 Example of One-shot Operation (Center Aligned Wave Form Selected)
(3)
Enable PPG operation
CNTE
(4)
Activation trigger
(1)
PCSR
PDUT
8000
0007
(2)Writing
Buffer
(cycle value)
8000
(5)Load
Buffer
(duty value)
8008
Buffer
(duty value end-point)
7FF8
(5)Load
Doun count
value
Down
count value
(PTMR)
(6)Down count
(7)match
8008
(9)down count
(10)match
7FF8
(12)down count
(13)borrow
(8)inverison
(8) inversion
PPG pin output
(11)clear
(14)clear
Normal polarity
duty X2
cycle X2
Inverted polarity
Interrupt factor
Valid edge
558
Duty match
Counter borrow
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Writing of PCSR (cycle value)
Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Enabling of PPG operation
Activation trigger generation
Loading of the [(Cycle value) 2 + 1] to the down count value (PTMR) and the duty value to the
buffer (duty value) and the buffer (duty value end point)
Duty value
(Output level inversion timing) = (Duty value + Cycle value + 1)
Duty value end point (Output level clear timing)
= (Cycle value - Duty value - 1)
Counter decrement
The down counter matches the duty value (output level inversion timing)
Output level inversion at the PPG pin
Counter decrement
The down counter matches the duty value end point (output level clear timing)
Clearing of PPG pin output level (restoration to normal state)
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
End of operation sequence
5.5.
Restart Operation
The restart operation is explained.
Restart operation is as follows:
Restart during PWM Operation
Figure 5-5 Restart during PWM Operation (Normal Waveform Selected)
Rising edge detection
Restart with trigger
Trigger
m
n
O
PPG
Duty
Cycle
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Chapter 18: PPG
Restart during One-shot Operation
Figure 5-6 Restart during One-shot Operation (Normal Waveform Selected)
Rising edge detection
Restart with trigger
Trigger
m
n
O
PPG
Duty
Cycle
Regardless of whether PWM operation or one-shot operation is being performed, the second or subsequent trigger
does not influence operation (does not cause restart) if the restart enable bit (PCN:RTRG) is "0" (restart disabled).
However, if, in the case of one-shot operation, the second or subsequent trigger occurs after one-shot operation, it
works as a restart trigger.
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Chapter 18: PPG
5.6.
GATE Operation
The GATE operation is explained.
PPG can be activated/stopped by GATE signals from the waveform generator. PPG activation valid time can be
controlled by the EDGE bit of the GATE control register (GATEC:EDGE) and GATE signals from the waveform
generator.
Figure 5-7 PPG Counter Operation by GATE Function
EDGE=0(rising activation → falling stop)
PCN:MDSE=0(PWM operation)
GATE signals from
the waveform
GATE signal
generator
PPG
Down counter
PPG output
（OSEL=0）
Start
Stop
Start
Stop
Start
EDGE=1(falling activation → rising stop)
PCN:MDSE=0(PWM operation)
GATE signals from
the waveform
GATE signal
generator
PPG
downcounter
PPG output
（OSEL=0）
Start
If the one-shot pulse operation (PCN:MDSE= "1") is set when PPG operation is selected (GATEC:STGR) by GATE
function, continuous pulses are output from the PPG output pin in the same way as the PWM operation.
Notes:
If the GATE signal is changed from "1" to "0" (when EDGE is "0") during the PPG operation, the PPG down
counter value (PTMR) will be maintained and the PPG output will be changed to "L" and will be stopped.
When the GATE function is enabled (STGR is "1") and restart is enabled (RTRG is "1"), inputting another
activation trigger does not start the restart operation.
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Chapter 18: PPG
5.7.
Start Delay Mode Operation (PWM Normal Wave Form
Selected)
The Start Delay mode operation (PWM Normal Wave Form selected) is explained.
In the Start Delay operation, a valid edge of PPG waveform output is delayed for the Start Delay value setting period.
If the PPG output waveform selection bit (PCN.OWFS)="1" (Center Aligned Wave Form) is selected, the delay value
is doubling the set value of the Start Delay value setting register. Moreover, the PWM operation, the one shot
operation, Normal Wave Form, and Center Aligned Wave Form are supported.
Figure 5-8 Example of Start Delay Operation (PWM Normal Wave Form Selected)
mode enable
(4) Start Delay enable
STRD
(5) Enable PPG operation
CNTE
(6)
Activation trigger
(1)
PSDR
0007
(2)
PCSR
8000
PDUT
0005
(3) Writing
Buffer
(cycle value)
8000
Buffer
(duty value)
0005
Down count value
(PTMR)
(9) Load
(16) Reload
8000
(10) down count
(17)
(7) Load
0007
(11) match
(8) down count
0005
(13) downcount
(14) borrow
PPG pin output
(12) invertion
inversion
(12)
Normal polarity
(15) clear
duty
Start Delay
cycle
Inverted polarity
Interrupt factor
Valid edge
562
Duty match
Counter borrow
Duty match
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
Writing of PSDR (Delay value)
Writing of PCSR (cycle value)
Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Enabling Start Delay mode
Enabling of PPG operation
Activation trigger generation
Loading of the Delay values
Counter decrement (Delay value set by (1))
Loading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
Repetition of steps (10) to (16)
Calculation formulas:
Start Delay value = {Start Delay value (PSDR) + 1} Count clock
Cycle = {Cycle value (PCSR) + 1} Count clock
Duty = {Duty value (PDUT) + 1} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
Note:
The calculating formula when Center Aligned Wave Form is selected is as follows.
Calculation formulas:
Start Delay value = {(Register setting value (PSDR) + 1) 2} Count clock
Cycle = {(Cycle value (PCSR) + 1) 2} Count clock
Duty = {(Duty value (PDUT) + 1) 2} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
Notes:
When the Start Delay value (PSDR) is rewritten during the PPG operation in the Start Delay mode, the Start Delay
value becomes effective after prohibiting operating once and generating the activation trigger. (The Start Delay
value becomes effective with the activation trigger.)
The Start Delay setting period (PSDR) is waited again when the restart request is generated during the Start Delay
operation (waiting time period). Moreover, the PPG waveform output is stopped and the Start Delay setting period
is waited again when the restart is requested while outputting PPG waveform by the Start Delay mode enable
(STRD)="1".
Be sure to prohibit operating once when "0" is written in the Start Delay mode enable (STRD) during the Start
Delay period. Moreover, if the activation trigger is not generated, the Start Delay mode disable (STRD=0) does not
become effective.
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Chapter 18: PPG
5.8.
Timing Point Capture Mode Operation (PWM Normal Wave
Form Selected)
The Timing Point Capture mode operation (PWM Normal Wave Form selected) is explained.
In the Timing Point Capture mode operation, the interrupt and the AD activation trigger are generated according to
the timing of the Timing Point Capture setting value. If the PPG output waveform selection bit (PCN.OWFS)="1"
(Center Aligned Wave Form) is selected, the doubling setting value of the Timing Point Capture value setting register
and the down counter value are compared. Moreover, the PWM operation, the one shot operation, Normal Wave Form,
and Center Aligned Wave Form are supported.
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Chapter 18: PPG
Figure 5-9 Timing Point Capture Operation (PWM Normal Wave Form Selected)
(4) Timing Point Capture mode enable
TPC
(5) Enable PPG operation
CNTE
(6)
Activation trigger
(1)
PTPC
7FFA
(2)
PCSR
8000
PDUT
0007
(3) Writing
Buffer
(cycle value)
8000
Buffer
(duty value)
0007
Down count value
(PTMR)
(16) Reload
(7) Load
8000
(8) down count
(17)
(9) match
0007
(11) match
0005
(13) down count
(14) borrow
PPG pin output
(10) inversion
Normal polarity
(15) clear
duty
cycle
Inverted polarity
Interrupt factor
Valid
edge
Counter
borrow
Duty match
Duty match
Timing Point Capture
match
ADTRG
Timing Point Capture
setting value
Timing Point Capture
match
(12) AD start trigger generation
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Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
Writing of PTPC (Timing Point Capture value)
Writing of PCSR (cycle value)
Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
Enabling Timing Point Capture mode
Enabling of PPG operation
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Passage of Timing Point Capture setting period from activation trigger
Interrupt and A/D activation trigger generation
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value to the buffer (duty
value)
Repetition of steps (8) to (16)
Calculation formulas:
Cycle = {Cycle value (PCSR) + 1} Count clock
Duty = {Duty value (PDUT) + 1} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
Timing Point Capture interrupt and A/D activation trigger generation : Passage of {PTPC register setting value +
1} period from the activation trigger
Note:
The calculating formula when Center Aligned Wave Form is selected is as follows.
Calculation formulas:
Cycle = {(Cycle value (PCSR) + 1) 2} Count clock
Duty = {(Duty value (PDUT) + 1) 2} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
Timing Point Capture interrupt and A/D activation trigger generation : Passage of {(PTPC register setting value +
1) 2} period from the activation trigger
Notes:
The Timing Point Capture value setting (PTPC) has to set smaller than the cycle value (PCSR). When the value
that is larger than cycle value (PCSR) is set, the A/D activation trigger or the Timing Point Capture match interrupt
is not generated.
The value becomes effective at the next cycle after rewriting when the Timing Point Capture value (PTPC) is
rewritten during the PPG operation.
When "0" is written in the Timing Point Capture mode enable (TPC) during the PPG operation, neither the
interrupt by the Timing Point Capture value match nor the A/D activation trigger is generated. Be sure to set the
setting according to the procedure when Timing Point Capture mode enable (TPC) is set again.
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Chapter 18: PPG
5.9.
PPG Communication Mode Operation
The PPG communication mode operation is explained.
In the PPG communication mode operation, the waveform according to the setting is output by setting the cycle/duty
of the High/Low format, the data, and the bit length. The operation of the PPG communication function is different
from usual PWM operation and the one-shot operation. (There is no Center Aligned Wave Form, and only Normal
Wave Form corresponds.)
In the PPG communication mode, the following registers are valid or invalid.
There is no influence on the PPG communication operation though writing in an invalid register is possible.
Valid registers:
Software trigger (STRG), Count clock selection (CKS1, CKS0),
PPG output mask selection (PGMS), Trigger input selection (EGS1, EGS0),
Interrupt request enable (IREN), Interrupt factor selection (IRS1, IRS0),
Interrupt request flag (IRQF) *1,
PPG output polarity selection (OSEL),
PPG timer (PTMR), GATE function control (GATEC),
Low format pulse selection (LFPR), High format pulse selection (HFPR),
PPG communication mode data reading selection (CMDSEL),
PPG communication mode enable (CMD),
PPG communication data register Empty flag (REMP) *2,
PPG communication data shift register Empty flag (SREMP) *2,
Interrupt factor selection2 (IRS2),
High format cycle setting (PHCSR), Low format cycle setting (PLCSR),
High format duty setting (PHDUT),
Low format duty setting (PLDUT),
Communication mode data setting (PCMDDT),
Communication mode data bit length setting (PCMDWD)
Invalid registers:
Timer operation enable (CNTE), Mode selection (MDSE), Restart enable (RTRG),
PPG output waveform selection (OWFS),
PPG cycle setting (PCSR), PPG duty setting (PDUT),
Timing Point Capture enable (TPC), Start Delay enable (STRD),
Start Delay value setting (PSDR), Timing Point Capture value setting (PTPC)
*1: IRS[2:0]=000b to 100b of the interrupt selection cannot be set during PPG communication; however, the registers
are enabled.
*2: Cannot be set because this is a read only register.
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Chapter 18: PPG
5.10. PPG Communication Activation
The PPG communication activation is explained.
The PPG communication mode starts by setting the PPG communication enable (CMD), the cycle setting (PHCSR,
PLCSR), the duty setting (PHDUT/PLDUT), the data (PCMDDT), and the data bit length (PCMDWD), and then set
the activation trigger at the end. There is no restriction in the order of setting registers other than the activation trigger.
Figure 5-10 Example of PPG Communication Mode Operation (Activation Operation Case 1)
(6) PPG communication mode enable
CMD
(7) Activation trigger
Activation trigger
(1) cycle setting
PHCSR
PLCSR
A
B
(2) duty setting
PHDUT
C
PLDUT
D
(3) PPG communication mode data width
PCMDWD
1h (0001)
(4) PPG communication mode data
PCMDDT
02h (0000_0010)
(5) transmit for shift register
Shift register
(PCMDDT)
02h (0000_0010)
Register Empty flag
(REMP)
(8) Load
Figure 5-11 Example of PPG Communication Mode Operation (Activation Operation Case 2)
(4) PPG communication mode enable
CMD
(7) Activation trigger
Activation trigger
(1) cycle setting
PHCSR
PLCSR
A
B
(2) duty setting
PHDUT
PLDUT
C
D
(3) PPG communication mode data width
PCMDWD
1h (0001)
(5) PPG communication mode data
PCMDDT
Shift register
(PCMDDT)
02h (0000_0010)
(6) transmit for shift register
02h (0000_0010)
Register Empty flag
(REMP)
(8) Load
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Chapter 18: PPG
5.11. PPG Communication Operation
The PPG communication operation is explained.
After it is initialized, the waveform according to the PPG communication data bit length (PCMDWD) setting is
output. If the PPG communication data setting (PCMDDT) is not rewritten before completion of the waveform output
(Figure 5-12), PPG communication ends. If the PPG communication data setting (PCMDDT) is rewritten, the
waveform output is completed according to the bit length setting. Then, PPG communication starts again with the
rewritten data setting (PCMDDT) (Figure 5-13).
PPG Single-shot Communication Operation
Figure 5-12 Example of PPG Communication Mode Operation (Single-shot Communication)
(5) PPG communication mode enable
CMD
(7) Activation trigger
Acti vation trigger
(1) cycle setting
PHCSR
A
PLCSR
B
(2) duty setting
PHDUT
C
PLDUT
D
(3) PPG communication mode data width
PCMDWD
4h (0100)
(4) PPG communication mode data
PCMDDT
14h (0001_0100)
(6) transmit for shift register
Shift re gister
(PCMDDT)
14h (0001_0100)
Registe r E mp ty flag
(REMP)
Shift re gister Empty flag
(SREMP)
0
PPG ou tpu t counter
Down cou nt value
(PTMR)
1
2
(8) Load
3
4
5
0
(15) Load
A
B
(9) down count
(10) match
(16)
C
D
(12) down count
(18)
(13) borrow
PPG pi n o utp ut
Normal polarity
(11) inversion (14) clear
*1
High format cycle
*2
Low format cycle
Inve rte d p olarity
*1 : High format duty
*2 : Low format duty
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Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
Writing of PHCSR/PLCSR (High/Low format cycle values)
Writing of PHDUT/PLDUT (High/Low format duty value)
Writing of PCMDWD (PPG communication mode data width)
Writing of PCMDDT (PPG communication mode data)
Enabling of PPG communication mode
Transmitting PCMDDT (PPG communication mode data) to the shift register
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value (Which cycle and duty
of the High or Low format is loaded is determined according to the PCMDDT, PCMDWD, and
CMDSEL setting)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value
Repetition of steps (9) to (15) according to the setting of PCMDDT and PCMDWD
Operation sequence completion
Notes:
There is no restriction by the order of setting above-mentioned (1) to (5). However, the PPG communication
operation does not start if the setting is not written all of (1) to (5).
The PPG communication does not start when the activation trigger is generated without completing the setting of
above-mentioned (1) to (5). Moreover, in this case, it is necessary to set (1) to (5) again to clear the setting once.
Note:
Calculation formulas: The calculating formula is common in all modes.
Cycle = {Cycle value (PCSR) + 1} Count clock
Duty = {Duty value (PDUT) + 1} Count clock
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} Count clock
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Chapter 18: PPG
PPG Continuousness Communication Operation
Figure 5-13 Example of PPG Communication Mode Operation (Continuousness
Communication)
(5) PPG communication mode enable
CMD
(7) activation trigger
Acti vation trigger
(1) cycle setting
PHCSR
A
PLCSR
B
(2) duty setting
PHDUT
C
PLDUT
D
(3) PPG communication mode data width
PCMDWD
1h (0001)
(4) PPG communication mode data
PCMDDT
(17) PPG communication mode data
02h (0000_0010)
03h (0000_0011)
(6) transmit for shift register
Shift re gister
(PCMDDT)
(19) transmit for shift register
02h (0000_0010)
03h (0000_0011)
Registe r E mp ty flag
(REMP)
Shift re gister Empty flag
(SREMP)
PPG ou tpu t counter
0
Down cou nt value
(PTMR)
1
2
(8) Load
1
2
0
(20) Load
(15) Load
A
B
(9) down count
(10) match
(21)
(16)
C
D
(12) down count
(23)
(18) borrow
(13) borrow
PPG pi n o utp ut
Normal polarity
(11) inversion (14) clear
*1
High format cycle
*2
Low format cycle
Inve rte d p olarity
*1 : High format duty
*2 : Low format duty
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Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
Writing of PHCSR/PLCSR (High/Low format cycle values)
Writing of PHDUT/PLDUT (High/Low format duty value)
Writing of PCMDWD (PPG communication mode data width)
Writing of PCMDDT (PPG communication mode data)
Enabling of PPG communication mode
Transmitting PCMDDT (PPG communication mode data) to the shift register
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value (Which cycle and duty
of the High or Low format is loaded is determined according to the PCMDDT, PCMDWD, and
CMDSEL setting)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value
Repetition of steps (9) to (15) according to the setting of PCMDDT and PCMDWD
Writing of PCMDDT (PPG communication mode data)
Counter borrow occurrence
Transmitting PCMDDT (PPG communication mode data) to the shift register
Loading of the cycle value to the down count value (PTMR) and the duty value (Which cycle and duty
of the High or Low format is loaded is determined according to the PCMDDT, PCMDWD, and
CMDSEL setting)
Repetition of steps (9) to (15) according to the setting of PCMDDT and PCMDWD
Operation sequence completion
Notes:
There is no restriction by the order of setting above-mentioned (1) to (5). However, the PPG communication
operation does not start if the setting is not written all of (1) to (5).
The PPG communication does not start when the activation trigger is generated without completing the setting of
above-mentioned (1) to (5). Moreover, in this case, it is necessary to set (1) to (5) again to clear the setting once.
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Chapter 18: PPG
5.12. PPG Communication Forced Stop and Restart operation
The PPG communication forced stop and restart operation is explained.
The PPG communication stops and the internal circuit other than the setting register are initialized when "0" is written
in the PPG communication mode setting register (CMD) during the PPG communication mode operation. Moreover,
to restart the PPG communication operation, it is necessary to write the setting in all related registers.
Figure 5-14 Example of PPG Communication Mode Operation (Communication Forced Stop and
Restart)
(17) PPG communication mode disable
(5) PPG communication mode enable
CMD
(7) Activation trigger
Acti vation trigger
(1) cycle setting
PHCSR
PLCSR
A
A
B
B
(2) duty setting
PHDUT
C
C
(18)
PLDUT
D
D
(3) PPG communication mode data width
PCMDWD
1h (0001)
5h (0101)
(4) PPG communication mode data
PCMDDT
03h (0000_0011)
B4h (1011_0100)
(6) transmit for shift register
Shift re gister
(PCMDDT)
00h (0000_0000)
B4h (1011_0100)
03h (0000_0011)
Registe r E mp ty flag
(REMP)
Shift re gister Empty flag
(SREMP)
0
PPG ou tpu t counter
Down cou nt value
(PTMR)
1
0
2
(8) Load
2
1
0
(15) Load
A
B
(9) down count
(10) match
(16)
C
D
(12) down count
(20)
(13) borrow
PPG pi n o utp ut
Normal polarity
(11) inversion (14) clear
*1
High format cycle
*2
Low format cycle
*1
High format cycle
*1
High format cycle
Inve rte d p olarity
*1 : High format duty
*2 : Low format duty
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Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
Writing of PHCSR/PLCSR (High/Low format cycle values)
Writing of PHDUT/PLDUT (High/Low format duty value)
Writing of PCMDWD (PPG communication mode data width)
Writing of PCMDDT (PPG communication mode data)
Enabling of PPG communication mode
Transmitting PCMDDT (PPG communication mode data) to the shift register
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value (Which cycle and duty
of the High or Low format is loaded is determined according to the PCMDDT, PCMDWD, and
CMDSEL setting)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value
Repetition of steps (9) to (15) according to the setting of PCMDDT and PCMDWD
PPG communication mode disable (internal circuit and flag register clear)
Resetting all of (1) to (7), repetition of steps (8) to (15) according to the setting of PCMDDT and
PCMDWD
Operation sequence completion
Notes:
There is no restriction by the order of setting above-mentioned (1) to (5). However, the PPG communication
operation does not start if the setting is not written all of (1) to (5).
The PPG communication does not start when the activation trigger is generated without completing the setting of
above-mentioned (1) to (5).
Moreover, in this case, it is necessary to set (1) to (5) again to clear the setting once.
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Chapter 18: PPG
5.13. PPG Output Pulse Polarity Selection
The PPG output pulse polarity selection is explained.
The PPG waveform can be output from the High pulse by writing "1" in the High/Low format pulse polarity selection
register (HFPR/LFPR). (Output from the Low pulse in "0" setting.)
Figure 5-15 Example of PPG Communication Mode Operation (Output Pulse Selection Mode
"1" Setting)
(6) PPG communication mode enable
CMD
(8) Activation trigger
Acti vation trigger
(1) cycle setting
PHCSR
A
PLCSR
B
(2) duty setting
PHDUT
C
PLDUT
D
(3) pulse polarity select
HFP R
'H'=inversion
LFPR
'H'=inversion
(4) PPG communication mode data width
PCMDWD
4h (0100)
(5) PPG communication mode data
PCMDDT
14h (0001_0100)
(7) transmit for shift register
Shift re gister
(PCMDDT)
14h (0001_0100)
Registe r E mp ty flag
(REMP)
Shift re gister Empty flag
(SREMP)
PPG ou tpu t counter
0
Down cou nt value
(PTMR)
1
2
(9) Load
3
4
5
0
(16) Load
A
B
(10) down count
(11) match
(17)
C
D
(13) down count
(19)
(14) borrow
PPG pi n o utp ut
Normal polarity
(12) inversion (15) clear
*1
High format cycle
*2
Low format cycle
Inve rte d p olarity
*1 : High format duty
*2 : Low format duty
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Chapter 18: PPG
Setting and operation procedure:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
Writing of PHCSR/PLCSR (High/Low format cycle values)
Writing of PHDUT/PLDUT (High/Low format duty value)
Writing of HFPR/LFPR (High/Low format pulse polarity selection)
Writing of PCMDWD (PPG communication mode data width)
Writing of PCMDDT (PPG communication mode data)
Enabling of PPG communication mode
Transmitting PCMDDT (PPG communication mode data) to the shift register
Activation trigger generation
Loading of the cycle value to the down count value (PTMR) and the duty value (Which cycle and duty
of the High or Low format is loaded is determined according to the PCMDDT, PCMDWD, and
CMDSEL setting)
Counter decrement
The down counter matches the duty value
Output level inversion at the PPG pin
Counter decrement
Counter borrow occurrence
Clearing of PPG pin output level (restoration to normal state)
Reloading of the cycle value to the down count value (PTMR) and the duty value
Repetition of steps (10) to (16) according to the setting of PCMDDT and PCMDWD
Operation sequence completion
Notes:
There is no restriction by the order of setting above-mentioned (1) to (6). However, the PPG communication
operation does not start if the setting is not written all of (1), (2), and (4) to (6).
The PPG communication does not start when the activation trigger is generated without completing the setting of
above-mentioned (1) to (5).
Moreover, in this case, it is necessary to set (1) to (5) again to clear the setting once.
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Chapter 18: PPG
5.14. Interrupt
The interrupt is explained.
The interrupt request is generated for the following either.
Software trigger, External trigger, and GATE signal trigger
Counter borrow occurrence (The set cycle is matched)
Match of duty
Match of Timing Point Capture value
PPG communication data register Empty flag
The generated interrupt factor is different depending on the operation mode of PPG.
Table 5-1 Correspondence of Operation Mode and Interrupt Request
Interrupt request
PWM operation and
one-shot operation
Timing Point
Capture mode
PPG
communication
mode
Software trigger, External
trigger, and GATE signal
trigger
Counter borrow occurrence
Match of counter and duty
value
Counter borrow occurrence,
or match of counter and duty
value
Match of Timing Point
Capture value
PPG communication data
register Empty factor
: Supported
: Not supported
Table 5-2 shows the register related to the interrupt of each operation mode.
Table 5-2 Interrupt Setting of Each Operation Mode
Interrupt setting
Setting of
interrupt factor
PWM operation,
One shot operation
Timing point capture
mode
PCNn.IRS[1:0]
=00 to 11
PCN2n.IRS[2:0]
=000 to 100
PPG communication
mode
PCN2n.IRS[2:0]
=101 to 111
Interrupt
request enable
Interrupt flag
PCNn.IRQF=1
PCNn.IREN=1
PCNn.IRQF=1
PCNn.IREN=1
PCN2n.REMP=1
or
PSC2n.SREMP=1
PCNn.IREN=1
Clear of
interrupt
request
"0" is written in
PCN.IRQF.
"0" is written in
PCN.IRQF.
"0" is written in
PCN.IRQF.
(n=0 to 87)
PCN: PPG control register
PCN2: PPG control register2
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Chapter 18: PPG
6. Notes
This section explains notes of the PPG.
Note the following when using the PPG:
PPG Operation Activation
1. The first load delays up to 2.5T after the activation trigger (T: Count clock). If an operation that loads a value to the
down counter and another operation that decrements the counter occur at the same time, the first operation takes
precedence (overwrites the down counter).
trigger
max 2.5T
Load
clock
Count value
X
0003
0002
0001
0000
0003
0002
PPG
interrupt
Varid
edge
Valid edge
Duty match
Counter borrow
2. To activate the PPG, the timer operation enable bit (PCN:CNTE) must be set to "1" before or when PPG operation
is enabled.
3. The PPG activation with the PSTR pin (PPG activation trigger) is the same operation as the PPG activation using a
software trigger or an external trigger (TRG pin).
Beforehand, it is necessary to set the register necessary for the PPG operation.
PPG is Operating
1. During the PPG operation, do not change any of the following: the mode selection bit (PCN:MDSE), the restart
enable bit (PCN:RTRG), the counter clock selection bits (PCN:CKS1, CKS0), the trigger input edge selection bits
(PCN:EGS1, EGS0), the interrupt factor selection bits (PCN:IRS1, IRS0), the activation trigger selection bits
(GTRS:TSEL[6:0]), and the PPG output polarity selection bit (PCN:OSEL).
If any of the above bits is changed during the PPG operation, disable PPG operation before reconfiguring the register.
2. If the timer operation enable bit (PCN:CNTE) is set to "0" to disable the PPG during the PPG operation, the PPG
down counter value will be maintained and the PPG output will be changed to "L" and will be stopped.
Thereafter, to restart the PPG, set the timer operation enable bit (PCN:CNTE) to "1" to enable the PPG and reload the
cycle and the duty values by entering an activation trigger.
3. If the timer operation enable bit (PCN:CNTE) is set to "0" to disable the PPG, it takes 3 clocks in internal clock
until the PPG output is stopped.
4. When the PPG output waveform selection (OWFS) is rewritten during the PPG communication operation, the
setting will be reflected at the next cycle.
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Chapter 18: PPG
5. To change the PPG output mask (PCN.PGMS) from "1" to "0" to cancel mask during the PPG communication
operation, perform the setting within the period between the beginning of cycle and the duty match.
Cycle Value (PCSR) and Duty (PDUT) Settings
1. When writing a cycle value (PCSR) and a duty value (PDUT), be sure to observe the sequence of (1) PCSR and (2)
PDUT. Notes the following when rewriting the cycle value (PCSR) and duty value (PDUT):
(1) The cycle value (PCSR) and the duty value (PDUT) are fetched to the buffer when the duty value (PDUT) is
written and will be transferred from the buffer to the counter when an activation trigger is generated or when a
borrow occurs.
(2) If the cycle value (PCSR) or duty value (PDUT) is rewritten during the PPG operation, the new value will be
effective on the output waveform at the next cycle after the duty value (PDUT) is rewritten.
(3) If only the cycle value (PCSR) needs to be rewritten, after the cycle value is reset, the duty value (PDUT),
which is unchanged, must be reset in the order of (1) PCSR and (2) PDUT.
(4) The duty value (PDUT) may be freely rewritten.
2. When you set the PPG duty setting register (PDUT), use values smaller than that set to the PPG cycle setting
register (PCSR).
3. When accessing the cycle setting register (PCSR) and duty setting register (PDUT) of the PPG, be sure to use word
(16-bit) format. If these registers are accessed in byte format, the values are not written at an upper and lower bit
positions.
GATE Function
1. Set the GATE function control register (GATEC) before PPG activation.
Do not change the GATE selection bit (STGR) and the polarity selection bit (EDGE) of the GATE function control
register (GATEC) during the PPG operation.
2. It takes 4 clocks in internal clock until the PPG output is stopped after GATE signal is negated.
3.When the GATE function is enabled (STGR is "1") and restart (RTRG) is enabled, inputting another activation
trigger does not start the restart operation.
4. If the GATE signal is changed from "1" to "0" (EDG = "0") during the PPG operation, the PPG down counter value
will be maintained and the PPG output will be changed to "L" and will be stopped. Thereafter, the GATE signal is
changed from "0" to "1", the cycle and duty values are reloaded, and operation is started.
Interrupts
1. If the interrupt request flag is set to "0" when interrupt request flag (PCN:IRQF) is "1", the flag clear request is
overwritten, and the interrupt request flag becomes "1".
2. The performance while the PPG output mask is set (PCN.PGMS="1") is shown below. The interrupt flag will not
be set to "1" regardless of interrupt factor caused by duty match. The interrupt flag will be set to "1" because of
interrupt factor caused by counter borrow occurrence. The interrupt flag will be set to "1" because of interrupt factor
caused by triggers (software trigger, external trigger or trigger caused by GATE signal).
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Chapter 18: PPG
Start Delay Function
1. To activate the Start Delay mode, the timer operation enable bit (CNTE) and the Start Delay mode enable (STRD)
must be set to "1" before or when PPG operation is enabled (activated).
2. When the Start Delay value (PSDR) is rewritten during the PPG operation in the Start Delay mode, the Start Delay
value becomes effective after prohibiting operating once and generating the activation trigger. (The Start Delay value
becomes effective with the activation trigger.)
3. The Start Delay setting period (PSDR) is waited again when the restart request is generated during the Start Delay
operation (waiting time period). Moreover, the PPG waveform output is stopped and the Start Delay setting period is
waited again when the restart is requested while outputting PPG waveform by the Start Delay mode enable
(STRD)="1".
4. When the Start Delay mode enable (STRD) is set to "1", the Start Delay value cannot be set to "0". (A minimum
setting of the Start Delay value is "1") Set the Start Delay mode enable (STRD) to "0" if the delay value is set to "0".
5. Be sure to prohibit operating once when "0" is written in the Start Delay mode enable (STRD) during the Start
Delay period. Moreover, if the activation trigger is not generated, the Start Delay mode disable (STRD=0) does not
become effective.
6. If the timer operation enable bit (CNTE) is set to "0" to disable the PPG during the Start Delay mode period, the
PPG stops with its state (count and output level) maintained. (Refer to 5th particular of "6. Notes" for the return
method.)
Timing Point Capture Function
1. The Timing Point Capture value setting (PTPC) has to set smaller than the cycle value (PCSR). When the value
that is larger than cycle value (PCSR) is set, the A/D activation trigger or the Timing Point Capture match interrupt is
not generated.
2. When the Start Delay mode enable (STRD) = "1" and the Timing Point Capture mode enable (TPC) = is set "1",
neither the interrupt nor the A/D activation trigger by the Timing Point Capture value match during the Start Delay
(waiting) are generated.
3. The value becomes effective at the next cycle after rewriting when the Timing Point Capture value (PTPC) is
rewritten during the PPG operation.
4. When "0" is written in the Timing Point Capture mode enable (TPC) during the PPG operation, neither the interrupt
by the Timing Point Capture value match nor the A/D activation trigger is generated. Make the setting according to
the procedure when Timing Point Capture mode enable (TPC) is set again.
PPG Communication Mode Function
1. PPG communication is started by setting PPG communication enable (CMD), the cycle setting (PHCSR/PLCSR),
the duty setting (PHDUT/PLDUT), the PPG communication mode data (PCMDDT), and the PPG communication
data bit length (PCMDWD), and then setting the activation trigger at the end. Thus, PPC communication is started.
Be sure to write the setting in the register when the PPG communication is activated. Also, set the other registers
before the start triggers are set.
However, PPG communication will not be started if the activation triggers are generated before the settings above are
not completed. Perform setting again after disabling the PPG communication (PCN2.CMD="0").
(similar when GATE function is used)
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Chapter 18: PPG
2. In the PPG communication mode, the following registers are valid or invalid.
Valid registers:
Software trigger (STRG)
Count clock selection (CKS1, CKS0)
PPG output mask selection (PGMS)
Trigger input selection (EGS1, EGS0)
Interrupt request enable (IREN)
Interrupt factor selection (IRS1, IRS0)
Interrupt request flag (IRQF)*1
PPG output polarity selection (OSEL)
PPG timer (PTMR)
GATE function control (GATEC)
PPG communication mode data reading selection (CMDSEL)
PPG communication mode enable (CMD)
Timing Point Capture interrupt (IRS2)
PPG communication data register Empty flag (REMP)*2
PPG communication data shift register Empty flag (SREMP) *2
High format cycle setting (PHCSR)
Low format cycle setting (PLCSR)
High format duty setting (PHDUT)
Low format duty setting (PLDUT)
Communication mode data setting (PCMDDT)
Communication mode data bit length setting (PCMDWD)
Low format pulse polarity selection (LFPR)
High format pulse polarity selection (HFPR)
Invalid registers:
Timer operation enable (CNTE)
Mode selection (MDSE)
Restart enable (RTRG)
PPG output waveform selection (OWFS)
Interrupt request flag (IRQF)
PPG cycle setting (PCSR)
PPG duty setting (PDUT)
Timing Point Capture enable (TPC)
Start Delay enable (STRD)
Start Delay value setting (PSDR)
Timing Point Capture value setting (PTPC)
*1: IRS[2:0]=000b to 100b of the interrupt selection cannot be set during the PPG communication; however, the
registers are enabled.
*2: Cannot be set because this is a read only register.
3. During the PPG communication operation, do not change any of the following: the count clock selection (CKS1,
CKS0), the interrupt selection (IRS2 to IRS0), the trigger input edge selection (EGS1, EGS0), the PPG output
polarity selection (OSEL), the GATE function enable (STGR), the activation effective edge selection (EDGE), the
PPG communication mode data reading selection (CMDSEL), the High/Low format pulse selection (HFPR/LFPR)
and the communication mode data bit length setting (PCMDWD). If any of the above bits is changed during the
PPG communication operation, disable PPG communication operation before reconfiguring the register.
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Chapter 18: PPG
4. Notes the following when rewriting the cycle value (PHCSR/PLCSR) and the duty value (PHDUT/PLDUT) in the
PPG communication mode.
(1) The cycle value (PHCSR/PLCSR) and the duty value (PHDUT/PLDUT) will be transferred from the register
to the counter when an activation trigger is generated or when a borrow occurs. Therefore, if the cycle
(PHCSR/PLCSR) or duty value (PHDUT/PLDUT) is rewritten during the PPG communication operation, the new
value will be effective on the output waveform at the next cycle after the borrow occurs
(2) The duty value (PHDUT/PLDUT) must be equal to or smaller than the cycle value (PHCSR/PLCSR).
If the duty value is set larger than the cycle value (PHCSR/PLCSR), disable PPG communication operation before
changing the duty value (PHDUT/PLDUT) to a smaller value. If PPG communication operation is not disabled,
the following will occur:
The output level will be "H" or "L" depending on [the cycle value (PHCSR/PLCSR) < the duty value
(PHDUT/PLDUT)] setting. ("H" or "L" is selected via the PPG output polarity selection setting.)
(3) If the cycle value (PHCSR/PLCSR) and the duty value (PHDUT/PLDUT) are set to the same value, or if the
duty value (PHDUT/PLDUT) set to "0", the following will occur:
When setting as cycle = duty:
If the polarity is normal (OSEL=0), "H" output.
If the polarity is inverted (OSEL=1), "L" output.
When setting as duty = 0:
If the polarity is normal (OSEL=0), "H" is output for 1 count clock cycle.
If the polarity is inverted (OSEL=1), "L" is output for 1 count clock cycle.
5. When accessing the High/Low format cycle setting register (PHCSR/PLCSR) and the duty setting register
(PHDUT/PLDUT) of the PPG communication mode, be sure to use 16-bit format. If these registers are accessed in
byte format, the values are not written at an upper and lower bit positions.
6. When the PPG communication is continuously executed, rewriting PPG communication mode data (PCMDDT) is
needed during the PPG communication operation. (Even if the same value is written, the PPG communication is
executed.)
However, after the bit length according to PCMDWD (PPG communication mode data bit length) setting is output,
the next setting data is output.
7. When the PPG output mask selection (PGMS) is rewritten during the PPG communication operation, the setting
will be reflected at the next cycle.
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Chapter 19: Watchdog Timer
This chapter explains the watchdog timer.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Usage Example
Code : FR81S10_WDT-1v1-91528-3-E
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Chapter 19: Watchdog Timer
1. Overview
This section gives an overview of the watchdog timer.
This device has two watchdog timers that can detect both the states of software and hardware running out of control,
and these watchdog timers can generate reset requests.
Figure 1-1 Block Diagram (schematic)
Bus Access
Peripheral clock
(PCLK)
CR oscillator
Watchdog 0
(Software Watchdog)
Watchdog 1
(Hardware Watchdog)
Watchdog reset 0
Watchdog reset 1
2. Features
This section explains features of the watchdog timer.
2.1 Watchdog Timer 0 (Software Watchdog)
2.2 Watchdog Timer 1 (Hardware Watchdog)
2.1.
Watchdog Timer 0 (Software Watchdog)
This section explains features of the watchdog timer 0.
Stop mode detection function
Able to detect the transition to watch mode or stop mode and generate a reset request
Watchdog timer clear
The timer is cleared by operation initialization reset or by writing the inverse value of the value previously written
to the clear register
Illegal write detection function
If the incorrect value is written to the clear register, a reset request is generated.
Watchdog timer period
The period can be selected from among sixteen choices of the peripheral clock (PCLK) × (2 9 to 224) cycles
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Chapter 19: Watchdog Timer
Count stop conditions
The count stops while the CPU is stopped
To set the lower limit value of the timer count of the watchdog timer.
The value can be selected from among sixteen choices of the peripheral clock (PCLK) × (2 8 to 223) cycles.
Monitoring the watchdog timer window and generating a reset request.
If the clear register is written below the lower limit value of the timer count of the watchdog timer, the watchdog
timer generates a reset request.
2.2.
Watchdog Timer 1 (Hardware Watchdog)
This section explains features of the watchdog timer 1.
This timer is driven by the clock generated by the built-in CR oscillator circuit immediately after the reset is released.
For information on settings (calibration) of the oscillator, see "CHAPTER: RTC/WDT1 (CALIBRATION)".
Watchdog timer clear
The timer is cleared by the operation initialization reset or by writing "0xA5" to the clear register.
Illegal write detection function
If a value other than "0xA5" is written to the clear register, a reset request is generated
Watchdog timer period
The period is fixed by the hardware at CR oscillator × 2 15 cycles
Count stop conditions
The count stops when using ICE, during sleep mode, watch mode, stop mode, and when waiting for the oscillator
to stabilize when recovering from standby mode
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Chapter 19: Watchdog Timer
3. Configuration
This section shows the configuration of the watchdog timer.
Figure 3-1 Block Diagram (Detailed)
WDTCPR0
Register value
maintained
RST
CPAT
PCLK
CMP
Stop/
Watch Mode
WDTCR0
R
Q
PCLK
RSTP
Watchdog
reset 0
S
WDT0 stops
Sleep mode
in sleep mode
and standby mode
EN
WDTCPR1
Overflow
Overflow
Overflow
cyclecompare
select
ion
cycle
period
selection
Watchdog timer 0
(24-bit up counter)
WDTCR0
WT
RST
PCLK
overflow
Select
Register value
maintained
RST
CPAT
PCLK
CMP
"0xA5"
"0xa5"
CR
oscillator
clk_wdg1
CRclk_wdg1
oscillator
clk_wdg1
EN
RST
CR oscillator
Watchdog
reset 1
Overflow
Overflow
Overflow
cyclecompare
select
ion
period
selection
cycle
overflow
Watchdog timer 1
(24-bit up counter)
WDTCR1
586
Q
S
WDT1 stops in sleep mode
wdg1 and
en standby
pin
mode
WT
R
Select
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Chapter 19: Watchdog Timer
4. Registers
This section explains the registers of the watchdog timer.
Table 4-1 Register Map
Registers
Address
Register function
+0
0x0038
WDTECR0
+2
+3
Watchdog timer 0 extended configuration
register
Reserved
Watchdog timer 0 control register
Watchdog timer 0 clear register
WDTCR0 WDTCPR0 WDTCR1 WDTCPR1
Watchdog timer 1 cycle information register
Watchdog timer 1 clear register
0x003C
4.1.
+1
Watchdog Timer 0 Control Register : WDTCR0 (WatchDog
Timer 0 Configuration Register)
The bit configuration of the watchdog control register 0 is shown.
This register configures each of the settings of the watchdog timer 0.
Writing to this register is invalid after the watchdog timer 0 is activated.
WDTCR0 : Address 003CH (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
RSTP
0
0
0
0
0
0
0
0
R0,W0
R/W
R0,W0
R0,W0
R/W
R/W
R/W
R/W
Reserved
bit1
bit0
WT[3:0]
[bit7] Reserved: (Reserved bit)
Be sure to write "0" to this bit. The read value is "0".
[bit6] RSTP (Reset by SToP) : Stop mode detection reset enable
This bit configures whether a reset signal is generated or not when a transition to watch mode or stop mode is
detected while the watchdog timer 0 is operating. When this bit is enabled, the watchdog timer reset 0 occurs when
the CPU switches to watch mode or stop mode. When this bit is not enabled, the watchdog timer 0 is paused when the
CPU switches to watch mode or stop mode, and the count stops until the CPU recovers from watch mode or stop
mode.
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Chapter 19: Watchdog Timer
RSTP
0
Stop mode detection
Not detected (initial value)
1
Generates a reset signal when detected
Writing to this bit after the watchdog timer 0 is activated is invalid.
[bit5, bit4] Reserved: (Reserved bits)
Be sure to write "0" to these bits. The read value is "0".
[bit3 to bit0] WT[3:0] (Watchdog Timer interval) : Watchdog timer cycle selection
These bits configure the number of cycles of timer interval starting from when the watchdog timer 0 was last cleared
to when a watchdog reset 0 is issued. Details are shown as follows.
WT[3:0]
The Watchdog Timer 0 cycle
0000
PCLK (Peripheral Clock) × 29 cycles
0001
PCLK × 210 cycles
0010
PCLK × 211 cycles
0011
PCLK × 212 cycles
0100
PCLK × 213 cycles
0101
PCLK × 214 cycles
0110
PCLK × 215 cycles
0111
PCLK × 216 cycles
1000
PCLK × 217 cycles
1001
PCLK × 218 cycles
1010
PCLK × 219 cycles
1011
PCLK × 220 cycles
1100
PCLK × 221 cycles
1101
PCLK × 222 cycles
1110
PCLK × 223 cycles
1111
PCLK × 224 cycles
After the watchdog timer 0 is activated writing to this bit is invalid.
The watchdog timer 0 does not count while the CPU is not operating.
Counting is performed while the CPU is operating even if DMA transfer is being performed.
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Chapter 19: Watchdog Timer
4.2.
Watchdog Timer 0 Clear Register : WDTCPR0 (WatchDog
Timer Clear Pattern Register 0)
The bit configuration of the watchdog timer 0 clear register is shown.
This register activates or clears (delays issue of a reset signal) the watchdog timer 0.
WDTCPR0 : Address 003DH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPAT[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
[bit7 to bit0] CPAT[7:0] (Clear PATtern) : Watchdog Timer 0 clear
The watchdog timer 0 is activated by the first write to this register after the reset is released. The watchdog timer is
cleared after being activated by writing a value with all of the bits inverted from the previously written value. If a
value other than the inverse value of the previously written value is written, the watchdog reset 0 is issued at that
time.
The value read out from this register is always "0x00" regardless of the value written.
4.3.
Watchdog Timer 0 Extended Configuration Register :
WDTECR0 (Watchdog Timer Extended Configuration
Register 0)
The bit configuration of the watchdog timer 0 Extended Configuration Register is shown.
This register configures the settings for window watching function of the watchdog timer 0.
Writing to this register is invalid after the watchdog timer 0 is activated.
WDTECR0 : Address 0038H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
Reserved
Initial value
0
Attribute R0,W0
bit4
bit3
WTWE
bit2
bit1
bit0
WTLI[3:0]
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] Reserved: (Reserved bits)
Be sure to write "0" to this bit. The read value is "0".
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Chapter 19: Watchdog Timer
[bit4] WTWE (Watchdog Timer Window Enable) : Watchdog Timer Window Function Enable
This bit controls the window function of the watchdog timer 0. When the bit WTWE is set to "1" the window function
becomes enabled.
The initial value of this bit is "0". (The window function is invalid.)
WTWE
Window function enabled
0
Window function is invalid (initial value)
1
Window function is valid
[bit3 to bit0] WTLI[3:0] (Watchdog Timer Lower Interval) : Selection of the lower limit of watchdog timer
These bits configure the lower limit of the interval starting from when the watchdog timer 0 is cleared to when it is
cleared next time. When the window function is valid, if a request for clearing the watchdog timer 0 comes before a
lower limit of timer shown below, a watchdog reset signal is issued.
WTLI[3:0]
The Lower Limit of the Watchdog Timer
0000
PCLK (Peripheral Clock) × 28 cycles
0001
PCLK × 29 cycles
0010
PCLK × 210 cycles
0011
PCLK × 211 cycles
0100
PCLK × 212 cycles
0101
PCLK × 213 cycles
0110
PCLK × 214 cycles
0111
PCLK × 215 cycles
1000
PCLK × 216 cycles
1001
PCLK × 217 cycles
1010
PCLK × 218 cycles
1011
PCLK × 219 cycles
1100
PCLK × 220 cycles
1101
PCLK × 221 cycles
1110
PCLK × 222 cycles
1111
PCLK × 223 cycles
Set the watchdog timer below the period specified with WTCR0.WT[3:0]. If a period larger than that specified with
WTCR0.WT[3:0] is set, a reset signal is generated. This is because the watchdog timer is satisfied with the condition
to be cleared below the lower limit of the window even though the timer is cleared before overflow.
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Chapter 19: Watchdog Timer
4.4.
Watchdog Timer 1 Cycle information Register : WDTCR1
(WatchDog Timer Cycle information Register 1)
The bit configuration of the watchdog timer 1 cycle information register is shown.
This register configures each of the settings of watchdog timer 1.
WDTCR1 : Address 003EH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
0
Attribute R0,WX
bit1
bit0
WT[3:0]
0
0
0
0
1
1
0
R0,WX
R0,WX
R0,WX
R0,WX
R1,WX
R1,WX
R0,WX
This register cannot be written again.
[bit7 to bit4] Reserved: (Reserved bits)
The value "0" is always read. Writing to these bits has no influence on operation.
[bit3 to bit0] WT[3:0] (Watchdog Timer interval) : Watchdog timer cycle selection
These bits configure the number of cycles of timer interval starting from when the watchdog timer 1 was last cleared
to when a watchdog reset 1 is issued. The cycle is fixed to 215 cycles. Writing to these bits are invalid
WT[3:0]
0110
4.5.
Watchdog timer 1 cycle
CR oscillator × 215 cycles (initial value, fixed)
Watchdog Timer 1 Clear Register : WDTCPR1 (WatchDog
Timer Clear Pattern Register 1)
The bit configuration of the watchdog timer 1 clear register is shown.
This register clears watchdog timer 1 (delays issue of a reset signal).
WDTCPR1 : Address 003FH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPAT[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
[bit7 to bit0] CPAT[7:0] (Clear PATtern) : Watchdog timer 1 clear
Watchdog timer 1 activates after the reset is released. The watchdog timer is cleared after being activated by writing
"0xA5". When a value other than "0xA5" is written, the watchdog reset 1 is issued at that time. The value read out
from this register is always "0x00"regardless of the value written.
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Chapter 19: Watchdog Timer
5. Operation
This section explains operation of the watchdog timer.
5.1 Software Watchdog Function
5.2 Hardware Watchdog Function
5.1.
Software Watchdog Function
This section explains the software watchdog function
5.1.1 Settings
5.1.2 Activation
5.1.3 Operation
5.1.1.
Settings
This section explains settings of the software watchdog function.
Before activating the watchdog timer 0, set bits 3 to 0: WT[3:0] of the register WDTCR0 in order to select the period
starting from clearing the watchdog timer to issuing the reset request.
Since the watchdog timer 0 counts only when the CPU is operating, set the period on the basis of the number of
program steps and the clock division setting.
Before activating the watchdog timer 0, set bit6: RSTP of the register WDTCR0 in order to select whether or not to
generate a reset signal when a transition to watch mode or stop mode is detected.
When RSTP="0", the timer stops in watch mode or stop mode.
When RSTP="1", a reset signal is generated as soon as the CPU enters watch mode or stop mode.
If the device is used in watch mode or stop mode, set RSTP="0". Writing to the RSTP bit is invalid after the
watchdog timer 0 is activated.
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Chapter 19: Watchdog Timer
5.1.2.
Activation
This section explains activation of the software watchdog function.
The watchdog timer 0 is activated by the first write of any data to the register WDTCPR0 after reset.
There is no restriction on the data written.
The value "0x00" is always read out from the register WDTCPR0 regardless of any data written.
5.1.3.
Operation
This section explains operation of the software watchdog function.
The operation of the watchdog timer 0 after activation is explained.
Counting Conditions
The watchdog timer 0 counts the rising edges of the peripheral clock (PCLK) while the CPU is operating.
DMA transfer does not influence the watchdog timer 0 to count.
As in sleep mode, the watchdog timer 0 stops counting only while the CPU is being stopped. Since sampling of
operating state of the CPU is done by the peripheral clock, a change in the operating state of the CPU occurring
within the period of the peripheral clock is ignored.
When the watchdog timer 0 is connected with ICE, the timer stops counting under the following conditions:
In emulator mode
In the debug interface functions, if the watchdog reset suppression function is enabled.
Under any conditions mentioned above, when the watchdog timer 0 stops counting it pauses without clearing the
counter. Hence, when the watchdog timer 0 resumes counting the timer will continue counting from the previous
count.
Because the peripheral clock stops during the oscillation stabilization wait time of the source clock, the watchdog
timer 0 also stops counting.
Clearing the Timer
Once the watchdog timer 0 is activated, the timer must be cleared before the timer period has elapses.
Clearing the watchdog timer 0 is performed by writing data to the register WDTCPR0. These data written must be the
inverted values of all bits of the WDTCPR0 that was written previously.
When the watchdog timer 0 is activated with the set value "0x55", for example, written to the register WDTCPR0, the
timer is cleared in the following way:
After activation of the watchdog timer 0, the set value should be written alternately like "0xAA" then "0x55" then
"0xAA" then "0x55".
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Chapter 19: Watchdog Timer
Since the read value of the register WDTCPR0 is always "0x00", the previously written value cannot be determined
by reading WDTCPR0. For this reason, if the previously written value cannot be stored in other location, write to the
register two times consecutively in a single clear.
When the window function is effective during the watching period, clear the timer within a period of time while the
counter can be cleared effectively.
Reset Request Generation
The watchdog timer 0 generates a watchdog reset request under the following conditions:
An overflow of the configured watchdog timer cycle occurs.
There is a transition to watch mode or to stop mode while stop mode detection reset is enabled.
A value, other than the inverted value of the value which is previously written, is written to the clear register.
Writing to the clear register within the lower limit of the watching period of the window function.
5.2.
Hardware Watchdog Function
This section explains operation of the hardware watchdog function.
5.2.1 Settings
5.2.2 Activation
5.2.3 Operation
5.2.1.
Settings
This section explains settings of the hardware watchdog function.
The values set to those bits from bit3 to bit0:WT[3:0] of the register WDTCR1 of the watchdog timer 1 are fixed with
hardware.
5.2.2.
Activation
This section explains activation of the hardware watchdog function.
The watchdog timer 1 is activated immediately after the reset is released.
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Chapter 19: Watchdog Timer
5.2.3.
Operation
This section explains operation of the hardware watchdog function.
The operation of the watchdog timer 1 after activation is explained.
Counting conditions
The watchdog timer 1 counts the rising edges of the CR oscillation.
When the watchdog timer 1 is connected with ICE, the timer stops counting under the following conditions:
In emulator mode
In the debug interface functions, if the watchdog reset suppression function is enabled.
The watchdog timer 1 stops counting in sleep mode, watch mode, stop mode, and during the oscillation stabilization
wait time recovering from standby mode.
Clearing the timer
Once the watchdog timer 1 is activated, the timer must be cleared before the timer period has elapses.
The watchdog timer 1 is cleared when the value "0xA5" is written to the register WDTCPR1.
Reset Request Generation
The watchdog timer 1 generates a watchdog reset request under the following conditions:
An overflow of the watchdog timer cycle occurs.
A value other than "0xA5" is written to the register WDTCPR1.
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Chapter 19: Watchdog Timer
6. Usage Example
This section gives an example of how the watchdog timer is used.
This example shows how to clear the watchdog timer.
Figure 6-1 Example of Clearing the Watchdog Timers
Boot
Clock settings
Watchdog timer
settings
Create periodic
interrupt service
Within periodic
interrupt service
by timer
596
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if notif configured.
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• Perform other processing as necessary. (Various calibrations, etc.)
• Perform other processing as necessary. (Various calibrations, etc.)
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Chapter 20: Base Timer
This chapter explains the base timer.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FM10-3v1-91528-3-E
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Chapter 20: Base Timer
1. Overview
This section explains the overview of the base timer.
This series includes the base timer for max 2 channels. These base timers provide the following functions:
16/32-bit reload timer
16-bit PWM timer
16-bit PPG timer
16/32-bit PWC timer
2. Features
This section explains features of the base timer.
This series includes the base timer for 2 channels. Each channel selects and uses appropriate ones of the following
functions:
2.1 16/32-bit Reload Timer
2.2 16-bit PWM Timer
2.3 16/32-bit PWC Timer
2.4 16-bit PPG Timer
2.1.
16/32-bit Reload Timer
This section explains the 16/32-bit reload timer of the base timer.
A base timer can be used as a 16/32-bit reload timer. The 16/32-bit reload timer is a timer that decreases from a preset
value.
I/O mode
You can select a signal (external clock, external activation trigger, waveform) I/O operation using the base timer I/O
selection function.
Timer mode
You can run multiple timers for individual channels and can combine 16-bit reload timers for two channels into one
32-bit reload timer.
Operation mode
You can select one of the following two:
Reload mode: In this mode, when the down counter underflows, the preset value (cycle) is reloaded to allow the
timer to restart counting.
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Chapter 20: Base Timer
One-shot mode: Once the down counter underflows, the counter will no longer count.
Count clock
You can select one of eight internal (peripheral) clocks and three external clocks (ECK signals).
Internal clock (peripheral clock): Clock obtained by dividing the frequency of the peripheral clock (PCLK) by 1, 4,
16, 128, 256, 512, 1024, or 2048.
External clock (ECK signal): Rising edges, falling edges, or both edges are detected.
Activation trigger
One of the following can be selected:
Software trigger
External event: Rising edge, falling edge, or both edges
16/32-bit reload timer reactivation: The 16/32-bit reload timer can be reactivated when an activation trigger is
detected during counting.
Interrupt request
An interrupt request can be generated in one of the following events:
IRQ0: When an underflow occurs
IRQ1: When a 16/32-bit reload timer activation trigger is detected
2.2.
16-bit PWM Timer
This section explains the 16-bit PWM timer of the base timer.
The 16-bit PWM timer, PWM standing for Pulse Width Modulator, produces a desired waveform at an external pin
when a duty ratio of the pulse width is specified.
I/O mode
You can select a signal (external clock, external activation trigger, waveform) I/O operation using the base timer I/O
selection function.
Operation mode
You can select one of the following two:
Reload mode: In this mode, when the 16-bit down counter underflows, the preset cycle is reloaded to allow the
timer to restart counting.
One-shot mode: Once the 16-bit down counter underflows, the counter will no longer count.
Count clock
You can select one of eight internal (peripheral) clocks and three external clocks (ECK signals).
Internal clock (peripheral clock): Clock obtained by dividing the frequency of the peripheral clock (PCLK) by 1, 4,
16, 128, 256, 512, 1024, or 2048.
External clock (ECK signal): Rising edges, falling edges, or both edges are detected.
Activation trigger
One of the following can be selected:
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Chapter 20: Base Timer
Software trigger
Three external events: (Rising edge, falling edge, or both edges detection)
16-bit PWM timer reactivation
The 16-bit PWM timer can be reactivated when an activation trigger is detected during counting.
Output waveform
The output signal from the external pin can be fixed at the "L" or "H" level.
Interrupt request
An interrupt request can be generated in one of the following events:
IRQ0 : When an underflow occurs or counting is performed up to a preset value (duty)
IRQ1 : When a 16-bit PWM timer activation trigger is detected
2.3.
16/32-bit PWC Timer
This section explains the 16/32-bit PWC timer of the base timer.
The 16/32-bit PWC timer, PWC standing for Pulse Width Counter, is used to measure pulse widths or cycles.
I/O mode
You can select a signal (waveform) I/O operation using the base timer I/O selection function.
Timer mode
You can run multiple timers for individual channels and can combine 16-bit PWC timers for two channels into one
32-bit PWC timer.
Operation mode
You can select one of the following two:
Single measurement mode: In this mode, measurement is conducted only once.
Continuous measurement mode: In this mode, after one sequence of measurement is conducted, the input of the
next measurement start edge is awaited and the detection of the next measurement start edge triggers another
sequence of measurement.
Count clock
You can select one of the internal (peripheral) clocks obtained by dividing the frequency of the peripheral clock
(PCLK) by eight types.
Clocks obtained by dividing the frequency of the peripheral clock (PCLK) by 1, 4, 16, 128, 256, 512, 1024, and
2048.
Measurement mode
You can select one of the following five options relating to the pulse width and cycle to be measured:
600
"H" pulse width: Duration in which the input signal is maintained at the "H" level
"L" pulse width: Duration in which the input signal is maintained at the "L" level
Rising edge interval: Period from the detection of a rising edge to the detection of the next rising edge
Falling edge interval: Period from the detection of a falling edge to the detection of the next falling edge
Edge-to-edge pulse width: The width between consecutive input edges is one of the following:
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Chapter 20: Base Timer
Period from the detection of a rising edge to the detection of the falling edge
Period from the detection of a falling edge to the detection of the rising edge
16/32-bit PWC timer reactivation
The 16/32-bit PWC timer can be reactivated when an activation trigger is detected during counting.
Interrupt request
An interrupt request can be generated in one of the following events:
IRQ0 : When an overflow occurs
IRQ1 : When measurement ends
2.4.
16-bit PPG Timer
This section explains the 16-bit PPG timer of the base timer.
The 16-bit PPG timer, PPG standing for Programmable Pulse Generator, is a timer that generates a waveform with a
desired pulse width.
I/O mode
You can select a signal (external clock, external activation trigger, waveform) I/O operation using the base timer I/O
selection function.
Operation mode
You can select one of the following two:
Reload mode: A sequence of "L"-level and "H"-level signals (consecutive pulses) is output.
One-shot mode: A string of one "L"-level signal and one "H"-level signal (single pulses) is output.
Count clock
You can select one of eight internal (peripheral) clocks and three external clocks (ECK signals).
Internal clock (peripheral clock): Clock obtained by dividing the frequency of the peripheral clock (PCLK) by 1, 4,
16, 128, 256, 512, 1024, or 2048.
External clock (ECK signal): Rising edges, falling edges, or both edges are detected.
Activation trigger
One of the following can be selected:
Software trigger
Three external events: (Rising edge, falling edge, or both edges detection)
16-bit PPG timer reactivation
The 16-bit PPG timer can be reactivated when an activation trigger is detected during counting.
Interrupt request
An interrupt request can be generated in one of the following events:
IRQ0 : When an underflow occurs based on the value of the base timer x H width setting reload register
(BTxPRLH).
IRQ1 : When a 16-bit PPG timer activation trigger is detected.
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Chapter 20: Base Timer
3. Configuration
This section explains the configuration of the base timer.
Figure 3-1 Block Diagram (Overview)
Interrupt
IRQ0 : Underflow/overflow/duty match
IRQ1 : Trigger/measurement completion interrupt
Interrupt
IRQ0, IRQ1
Bus access
Interrupt
IRQ0, IRQ1
Channel 0
Channel 1
Registers
Registers
I/O selection
register
(BTSEL01)
Counter
Counter
Simultaneous
software activation
register (BTSSSR)
Trigger logic
Interrupt logic
Trigger logic
I/O selection logic
TIOA0
Base Timer
TIOB0
TIOA1
Interrupt logic
TIOB1
(Input for I/O mode1 and output or
unused for other than I/O mode 1)
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Chapter 20: Base Timer
4. Registers
This section explains registers of the base timer.
List of Base Addresses (Base_addr) and External Pins
Table 4-1 Table of Base Addresses (Base_addr) and External Pins
External pin *
Channel number
Base address
MB91F52xR, MB91F52xU, MB91F52xM, MB91F52xY
0
0x0080
TIOA0_0/TIOA0_1,TIOB0_0/TIOB0_1
1
0x0090
TIOA1_0/TIOA1_1,TIOB1_0/TIOB1_1
*: TIOA0, TIOA1, TIOB0 and TIOB1 are assigned according to the BTSEL01 register setting, but the setting without
external pins is disabled.
Registers Map
Table 4-2 Registers Map
Registers
Address
Register function
+0
+1
+2
0x0080
[Common] BT0TMR
0x0084
[Reload
timer]
BT0STC
[PWM]
BT0STC
[PPG]
BT0STC
[PWC]
BT0STC
0x0088
0x008C
[Common]
BT0TMCR
2
+3
[Common] BT0TMCR
[Reload timer]
BT0PCSR
[PWM]
BT0PCSR
[PPG]
BT0PRLL
[PWC]
Reserved
[Common] Timer register 0
[Common] Control register 0
Reserved
[Common] Control register 20
[Reload timer] Status control register 0
[PWM] Status control register 0
[PPG] Status control register 0
[PWC] Status control register 0
[Reload timer]
Reserved
[PWM]
BT0PDUT
[PPG]
BT0PRLH
[PWC]
BT0DTBF
[Reload timer] Cycle setting register 0
[PWM] Cycle setting register 0
[PPG] L width setting reload register 0
[PWM] Duty setting register 0
[PPG] H width setting reload register 0
[PWC] Data buffer register 0
Reserved
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Chapter 20: Base Timer
Registers
Address
Register function
+0
+1
0x0090
[Common] BT1TMR
0x0094
[Reload
timer]
BT1STC
[PWM]
BT1STC
[PPG]
BT1STC
[PWC]
BT1STC
0x0098
0x009C
604
[Common]
BT1TMCR
2
[Reload timer]
BT1PCSR
[PWM]
BT1PCSR
[PPG]
BT1PRLL
[PWC]
Reserved
BTSEL01
Reserved
+2
+3
[Common] BT1TMCR
[Common] Timer register 1
[Common] Control register 1
Reserved
[Common] Control register 21
[Reload timer] Status control register 1
[PWM] Status control register 1
[PPG] Status control register 1
[PWC] Status control register 1
[Reload timer]
Reserved
[PWM]
BT1PDUT
[PPG]
BT1PRLH
[PWC]
BT1DTBF
[Reload timer] Cycle setting register 1
[PWM] Cycle setting register 1
[PPG] L width setting reload register 1
[PWM] Duty setting register 1
[PPG] H width setting reload register 1
[PWC] Data buffer register 1
BTSSSR
I/O selection register
Simultaneous software activation register
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Chapter 20: Base Timer
4.1.
Common Registers
This section explains the common registers of the base timer.
The registers described here are common to various operations.
4.1.1.
Timer Registers 0, 1 : BTxTMR (Base Timer 0/1 TiMer
Register)
The bit configuration of timer registers 0, 1 (BTxTMR) is shown below.
These registers read the counter value on the timer. The registers are only valid when its content represents a reload,
PWM, or PPG timer. The value read from the registers is undefined if a PWC timer is read. For information on the
values that will be read, see the section of Operation Description.
BTxTMR : Address Base_addr + 00H (Access: Half-word)
bit15
bit14
---
bit2
bit1
bit0
D[15:0]
Initial value
Attribute
0
0
---
0
0
0
R,WX
R,WX
---
R,WX
R,WX
R,WX
Note:
These registers must be accessed in 16-bit mode.
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Chapter 20: Base Timer
4.1.2.
Timer Control Registers 0, 1 : BTxTMCR (Base Timer 0/1
TiMer Control Register)
The bit configuration of timer control registers 0, 1 (BTxTMCR) is shown below.
These registers variously configure and stop the base timer and issue software triggers.
BTxTMCR : Address Base_addr + 02H (Access: Half-word)
bit15
bit14
Reserved
Initial value
Attribute
Attribute
bit12
CKS[2:0]
bit11
bit10
[PWM PPG]
RTGEN
[Others]
Reserved
[PWM PPG]
PMSK
[PWC]
EGS[2]
[Others]
Reserved
bit9
bit8
EGS[1:0]
0
0
0
0
0
0
0
0
R/W0
3
R0,W0 *
R/W
R/W
R/W
R/W
1
R0,WX *
R/W
1
R0,WX *
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
[Reload
timer - PWM
- PPG]
OSEL
[Others]
Reserved
MDSE
CTEN
STRG
[Reload
timer PWC]
T32
[Others]
Reserved
Initial value
bit13
FMD[2:0]
0
0
0
0
0
0
0
0
R/W
1
R0,W0 *
2
R0,W0 *
R/W
R/W
R/W
R/W
1
R/W0 *
R/W
R,W
R0,W
1
R0,W0 *
*1: Attribute assumed for "Reserved"
*2: Attribute assumed for a 32-bit timer serving an odd-number channel
*3: Attribute assumed for a 32-bit timer serving an odd-number channel or for a 16/32-bit PWC timer
BTxTMCR2 : Address Base_addr + 04H (Access: Byte)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
Reserved
Initial value
Attribute
606
bit8
CKS3
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
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Notes:
If you need to change the FMD[2:0] setting, once reset it to FMD[2:0] = 000, and then set FMD[2:0] to the desired
value.
Reserved bits must be set to "0".
If you want to set bits of these registers except for the software trigger (STRG) bit, proceed as follows:
1. Once stop operation by writing FMD[2:0] = 000 or CTEN = 0.
2. Write desired values to the timer function selection bits (FMD[2:0]) and other bits.
When writing to the software trigger bit (STRG), be careful not to clear other bits.
Since FMD[2:0] = 000 specifies reset mode, you cannot set other bits when setting FMD[2:0] = 000.
These registers must be accessed in 16-bit mode.
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit15] Reserved
Write 0 to this bit.
[BTxTMCR2:bit8, BTxTMCR:bit14 to bit12] CKS[3:0] (ClocK Select) : Count clock selection bits
This bit selects a count clock.
Description
CKS[3:0]
Clock source
Description
0000
1 division
0001
4 division
0010
Internal clock
(Peripheral clock (PCLK))
16 division
0011
128 division
0100
256 division
0101
Rising edge
0110
[Reload timer/PWM/PPG] external clock (ECK signal)
[PWC] Setting is prohibited
Falling edge
0111
Both edges
1000
512 division
1001
Internal clock
(Peripheral clock (PCLK))
1010
Other
1024 division
2048 division
Setting is prohibited.
In the PWC mode, settings of 0101, 0110, and 0111 are prohibited.
[PWM/PPG] [bit11] RTGEN (Restart by TriGger ENable) : Restart enable bit
If "1" is written to the STRG bit or an external activation trigger (TGIN signal) is detected, this bit sets whether or not
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to recount the value of cycle setting register (BTxPCSR)/L width setting reload register (BTxPRLL) by reloading it to
the 16-bit down counter.
RTGEN
Description of operation
0
Does not reactivate
1
Reactivates
[PWM/PPG] [bit10] PMSK (Pulse MaSK) : Pulse output mask bit
This bit selects a level of waveform to output (TOUT signal) from the followings:
Normal output : Output the waveform output from the 16-bit PWM/PPG timer without modification.
Fixed output : Output a sequence of "L" level or "H" level signals regardless of the settings of cycle or
duty.
PMSK
Description
0
Normal output
1
Fixed output
If the fixed output is selected by writing "1" to this bit, the level being output will vary depending on the settings of
the OSEL bit.
If OSEL=0 : "L" level will be output.
If OSEL=1 : "H" level will be output.
[Reload timer/PWM/PPG] [bit9, bit8] EGS[1:0] (EdGe Select) : Trigger input selection bits
These bits select an effective edge for the external activation trigger (TGIN) signal.
EGS[1:0]
Description
00
Trigger input has no effect on the operation
01
Rising edge
10
Falling edge
11
Both edges
[PWC] [bit10 to bit8] EGS[2:0] (EdGe Select) : Measurement mode selection bits
These bits select a measurement mode.
EGS[2:0]
000
608
Description
"H" pulse width measurement: Duration in which the input signal is maintained at
the "H" level
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Chapter 20: Base Timer
EGS[2:0]
Description
001
Rising edge interval measurement: Time from the detection of a rising edge to the
detection of the next rising edge
010
Falling edge interval measurement: Time from the detection of a falling edge to the
detection of the next falling edge
011
Edge-to-edge pulse width measurement: The width between consecutive input
edges is either:(1) or (2).
(1) Time from the detection of a rising edge to the detection of the falling edge
(2) Time from the detection of a falling edge to the detection of the rising edge
100
"L" pulse width measurement: Duration in which the input signal is maintained at
the "L" level(Time from the detection of a falling edge to the detection of the rising
edge)
101
110
111
Setting is prohibited
[Reload timer/PWC] [bit7] T32 (Timer 32bit) : 32-bit timer selection bit
This bit selects whether to run the 16/32-bit timer individually by each channel or use the two channels as 32-bit timer
through a cascade connection. Set this bit for both channel 0 and channel 1.
T32 (channel 0)
T32 (channel 1)
Description
0
0
16-bit timer independent operation
respectively
0
1
Setting is prohibited
1
0
32-bit timer
1
1
Setting is prohibited
Note:
Change this bit after changing the FMD[2:0] to 000.(Once you have changed the FMD[2:0] to 000, set the T32 bit
and FMD[2:0] to a required value at the same time.)
[bit6 to bit4] FMD[2:0] (Function MoDe) : Timer function selection bits
These bits select a function of base timer. To change these bits, go to 000 (reset mode) first, and set it to another
mode.
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Chapter 20: Base Timer
FMD[2:0]
Description
000
Reset mode
(Writing FMD = 000 will reverse the state of the base timer after the reset.
Each register will be reset to the initial value.)
001
16-bit PWM timer
010
16-bit PPG timer
011
16/32-bit reload timer
100
16/32-bit PWC timer
101
110
111
Setting is prohibited
[bit3] OSEL (Output SELect) : Output polarity selection bit
When this bit is set, the signal level (H/L) output from TOUT will be inverted.
OSEL
Description
0
Normal output
1
Inverted output
[bit2] MDSE (MoDe Select) : Mode selection bit
[Reload timer-PWM]
MDSE
Description
0
Reload mode: When the down counter underflows, the value of the base timer x
cycle setting register (BTxPCSR) is reloaded to continue counting.
1
One-shot mode: Once the down counter underflows, the counter will no longer
count.
[PPG]
MDSE
610
Description
0
Reload mode: A sequence of "L"-level and "H"-level signals (consecutive pulses)
is output.
1
One-shot mode: A string of one "L"-level signal and one "H"-level signal (single
pulses) is output.
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Chapter 20: Base Timer
[PWC]
MDSE
Description
0
Continuous measurement mode: In this mode, after one sequence of measurement
is conducted, the input of the next measurement start edge is awaited and the
detection of the next measurement start edge triggers another sequence of
measurement.
1
Single measurement mode: In this mode, measurement is conducted only once.
[bit1] CTEN (CounT ENable) : Counter operation enable bit
This bit enables/disables the counter operation.
Description
CTEN
Read
Write
0
Stopped
This bit becomes "0".
1
Operation enabled
This bit becomes "1".
Note:
When a falling edge is output from the even-number channel during timer operation in I/O mode 4 and I/O mode 6,
this bit, which is an odd-number channel bit, is cleared to 0.
[bit0] STRG (Software TRiGger) : Software trigger bit
Functions as a trigger for timer activation, etc.
The read value at PWC is "0". Write "0" in this bit at PWC.
STRG
Description
0
No effect on the operation
1
Issues a trigger.
Notes:
When writing to this bit, be careful not to clear other bits.
When writing to CTEN and FMD[2:0] simultaneously, a trigger is issued as soon as operation is enabled.
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Chapter 20: Base Timer
4.1.3.
I/O Selection Register : BTSEL01 (Base Timer SELect
register ch.0 and ch.1)
The bit configuration of the I/O selection register (BTSEL01) is shown below.
These bits set the I/O mode of ch.0 and ch.1 for the base timer.
BTSEL01 : Address 009CH (Access: Byte)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
1
Attribute R1,WX
bit2
bit1
bit0
SEL01[3:0]
1
1
1
0
0
0
0
R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
Notes:
These registers must be accessed in 8-bit mode.
Rewrite this register after setting the FMD2 to FMD0 bits of the base timer x the timer control register
(BTxTMCR) to the base timer reset mode (FMD2 to FMD0 = 000).
[bit3 to bit0] SEL01[3:0] (SELect) : ch.0/ch.1 I/O selection bits
These bits set the I/O mode of ch.0 and ch.1 for the base timer.
SEL01[3:0]
612
Description
0000
I/O mode 0
(16-bit timer standard mode)
0001
I/O mode 1
(32-bit timer full mode)
0010
I/O mode 2
(External trigger sharing mode)
0011
Setting is prohibited
0100
I/O mode 4
(Timer activation/stop mode)
0101
I/O mode 5
(Simultaneous software activation mode)
0110
I/O mode 6
(Software activation timer activation/stop mode)
0111
I/O mode 7
(Timer activation mode)
1xxx
Setting is prohibited
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Chapter 20: Base Timer
4.1.4.
Simultaneous Software Activation Register : BTSSSR
(Base Timer Software Synchronous Start Register)
The bit configuration of the simultaneous software activation register (BTSSSR) is shown below.
This register is the input signal in the I/O modes 5 and 6. Trigger can be generated simultaneously for all channels
with this register.
BTSSSR : Address 009EH (Access: Byte, Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
1
Attribute R1,WX
bit7
1
1
1
1
1
1
1
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SSSR1
SSSR0
Reserved
Initial value
1
Attribute R1,WX
1
1
1
1
1
1
1
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,W
R1,W
[bit1] SSSR1 (Software Synchronous Start Register ch.1) : Simultaneous software activation bit ch.1
[bit0] SSSR0 (Software Synchronous Start Register ch.0) : Simultaneous software activation bit ch.0
These bits are the input signal in the I/O modes 5 and 6. For the connections, see "Figure 5-2 Wiring Diagram of Each
I/O Mode (2) ".
SSSR0/1
Description
0
No effect on the operation.
1
"1" pulse is applied to the timer input, and then the corresponding channel is
activated.
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4.2.
Registers for 16/32-bit Reload Timer
This section explains registers for 16/32-bit reload timer.
4.2.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1
STatus Control)
The bit configuration of status control registers 0, 1 (BTxSTC) is shown below.
These registers control interrupt requests.
BTxSTC : Address Base_addr + 05H (Access: Byte)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
TGIE
Reserved
UDIE
Reserved
TGIR
Reserved
UDIR
0
0
0
0
0
0
0
0
R0,W0
R/W
R0,W0
R/W
R0,W0
R(RM1),W
R0,W0
R(RM1),W
Notes:
Reserved bits must be set to "0".
For the read-modify-write instruction to TGIR and UDIR, "1" is read out.
These registers must be accessed in 8-bit mode.
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit6] TGIE (TriGger Interrupt Enable) : Trigger interrupt request enable bit
This bit sets whether or not to generate a trigger interrupt request when an activation trigger for 16/32-bit reload timer
has been detected (TGIR = 1).
[bit4] UDIE (UnDerflow Interrupt Enable) : Underflow interrupt request enable bit
This bit sets whether or not to generate an underflow interrupt request when the down counter underflows (UDIR =
1).
TGIE/UDIE
Description
0
Disables
1
Enables
[bit2] TGIR (TriGger Interrupt Register) : Trigger interrupt request flag bit
This bit indicates that an activation trigger for the 16/32-bit reload timer has been detected. When the TGIE bit is set
to "1" while this bit is "1", a trigger interrupt request will be generated.
[bit0] UDIR (UnDerflow Interrupt Register) : Underflow interrupt request flag bit
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This bit indicates that the down counter value has changed from "0000 H" to "FFFFH" and an underflow occurred.
When this bit is "1" and the UDIE bit is set to "1", an underflow interrupt request is generated.
TGIR/UDIR
4.2.2.
Read
Write
0
No trigger detection/underflow occurred.
This bit is cleared.
1
Trigger detection/underflow occurred.
No effect on the operation
Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1
Pulse Counter Start Register)
The bit configuration of cycle setting registers 0, 1 (BTxPCSR) is shown below.
These registers with a buffer set the cycle for 16/32-bit reload timer. The down counter counts down from the value
set to these registers.
BTxPCSR : Address Base_addr + 08H (Access: Half-word)
bit15
bit14
---
bit2
bit1
bit0
D[15:0]
Initial value
Attribute
X
X
---
X
X
X
R/W
R/W
---
R/W
R/W
R/W
Notes:
These registers must be accessed in 16-bit mode.
Set these registers after selecting a base timer function to the 16/32-bit reload timer (FMD2 to FMD0 = 011) using
the FMD2 to FMD0 bits of the timer control register (BTxTMCR).
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers with a buffer set the cycle for the 16/32-bit reload timer. The down counter counts down from the
value set to these registers.
The value set to these registers is loaded to the 16-bit down counter in the following cases:
When the 16/32-bit reload timer is started
When the down counter underflows
The following values are set to these registers when two channels of a 16-bit reload timer are cascaded and used as
the 32-bit reload timer.
Value of even-number channel cycle setting register (BTxPCSR) : Value of lower 16-bit
Value of odd-number channel cycle setting register (BTxPCSR) : Value of upper 16-bit
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For this reason, in the 32-bit timer mode, write values into these registers in the following order.
1.
2.
4.3.
Odd-number channel base timer x cycle setting register (BTxPCSR)
Even-number channel base timer x cycle setting register (BTxPCSR)
Registers for 16-bit PWM Timer
This section explains registers for 16-bit PWM timer.
4.3.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1
STatus Control)
The bit configuration of status control registers 0, 1 (BTxSTC) is shown below.
These registers control interrupt requests.
BTxSTC : Address Base_addr + 05H (Access: Byte)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
TGIE
DTIE
UDIE
Reserved
TGIR
DTIR
UDIR
0
0
0
0
0
0
0
0
R0,W0
R/W
R/W
R/W
R0,W0
R(RM1),W R(RM1),W R(RM1),W
Notes:
Reserved bits must be set to "0".
For the read-modify-write instruction to TGIR, DTIR, and UDIR, "1" is read out.
These registers must be accessed in 8-bit mode.
These registers will also be initialized when reset mode is set
(writing of BTxTMCR.FMD = 000).
[bit6] TGIE (TriGger Interrupt Enable) : Trigger interrupt request enable bit
This bit sets whether or not to generate a trigger interrupt request when a 16-bit PWM timer activation trigger is
detected (TGIR = 1).
[bit5] DTIE (DuTy Interrupt Enable) : Duty match interrupt request enable bit
This bit sets whether or not to generate a duty match interrupt request when the value of the 16-bit down counter
matches the value of the base timer x duty setting register (BTxPDUT) (DTIR = 1).
[bit4] UDIE (UnDerflow Interrupt Enable) : Underflow interrupt request enable bit
This bit sets whether or not to generate an underflow interrupt request when the down counter underflows (UDIR =
1).
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TGIE/DTIE/UDIE
Description
0
Disables.
1
Enables.
[bit2] TGIR (TriGger Interrupt Register) : Trigger interrupt request flag bit
This bit indicates that a 16-bit PWM timer activation trigger is detected. When this bit is "1" and the TGIE bit is set to
"1", a trigger interrupt request is generated.
[bit1] DTIR (DuTy Interrupt Register) : Duty match interrupt request flag bit
This bit indicates that the value of the 16-bit down counter matches the value of the duty setting register (BTxPDUT)
(a duty matches). When this bit is "1" and the DTIE bit is set to "1", a duty match interrupt request is generated.
[bit0] UDIR (UnDerflow Interrupt Register) : Underflow interrupt request flag bit
This bit indicates that the 16-bit down counter value changed from "0000H" to "FFFFH" and an underflow occurred.
When this bit is "1" and the UDIE bit is set to "1", an underflow interrupt request is generated.
TGIR/DTIR/UDIR
Read
Write
0
A trigger detection, duty match
and underflow did not occur.
1
A trigger detection, duty match or
No effect on the operation.
underflow occurred.
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4.3.2.
Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1
Pulse Counter Start Register)
The bit configuration of cycle setting registers 0, 1 (BTxPCSR) is shown below.
These registers with a buffer set the cycle for the 16-bit PWM timer. The 16-bit down counter counts down from the
value set to these registers. When the counter value matches the value set to these registers, the level of the output
signal (TOUT) is inverted.
BTxPCSR : Address Base_addr + 08H (Access: Half-word)
bit15
bit14
---
bit2
bit1
bit0
D[15:0]
Initial value
Attribute
0
0
---
0
0
0
R/W
R/W
---
R/W
R/W
R/W
Notes:
These registers must be accessed in 16-bit mode.
Set these registers after selecting a base timer function to the 16-bit PWM timer using the FMD2 to FMD0 bits of
the timer control register (BTxTMCR).
Be sure to rewrite the duty setting register (BTxPDUT) when these registers are rewritten.
Do not set a value smaller than the value set to the duty setting register (BTxPDUT).
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers with a buffer set the cycle for the 16-bit PWM timer. The 16-bit down counter counts down from the
value set to these registers. When the counter value matches the value set to these registers, the level of the output
signal (TOUT) is inverted.
These registers have a buffer and thus can be rewritten during counting. The value set to these registers is loaded to
the 16-bit down counter in the following cases:
When the 16-bit PWM timer is activated
When the down counter underflows
When the same value is set to these registers and the base timer x duty setting register (BTxPDUT), the level of the
output signal (TOUT) can be fixed. The output signal level is as follows according to the setting of the OSEL bit of
the base timer x timer control register (BTxTMCR):
OSEL=0: "H" level
OSEL=1: "L" level
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4.3.3.
Duty Setting Registers 0, 1 : BTxPDUT (Base Timer 0/1
Pulse DuTy register)
The bit configuration of duty setting registers 0, 1 (BTxPDUT) is shown below.
These registers with a buffer set the duty for the 16-bit PWM timer. When the 16-bit down counter value matches the
value set to these registers, the level of the output signal (TOUT) is inverted.
BTxPDUT : Address Base_addr + 0AH (Access: Half-word)
bit15
bit14
---
bit2
bt1
bit0
D[15:0]
Initial value
Attribute
0
0
---
0
0
0
R/W
R/W
---
R/W
R/W
R/W
Notes:
These registers must be accessed in 16-bit mode.
Set these registers after selecting a base timer function to the 16-bit PWM timer using the FMD2 to FMD0 bits of
the timer control register (BTxTMCR).
Do not set the value higher than the value set to the cycle setting register (BTxPCSR) when these registers are
rewritten.
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers with a buffer set the duty for the 16-bit PWM timer. When the 16-bit down counter value matches the
value set to these registers, the level of the output signal (TOUT) is inverted.
These registers have a buffer and thus can be rewritten during counting.
If the 16-bit down counter underflows, the buffer value will be transferred.
When the same value is set to these registers and the base timer x cycle setting register (BTxPCSR), the level of the
output signal (TOUT) can be fixed. The output signal level is as follows according to the setting of the OSEL bit of
the base timer x timer control register (BTxTMCR):
OSEL=0: All "H" level
OSEL=1: All "L" level
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4.4.
Registers for 16-bit PPG Timer
This section explains registers for 16-bit PPG timer.
4.4.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1
STatus Control)
The bit configuration of status control registers 0, 1 (BTxSTC) is shown below.
These registers control interrupt requests.
BTxSTC : Address Base_addr + 05H (Access: Byte)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
TGIE
Reserved
UDIE
Reserved
TGIR
Reserved
UDIR
0
0
0
0
0
0
0
0
R0,W0
R/W
R0,W0
R/W
R0,W0
R(RM1),W
R0,W0
R(RM1),W
Notes:
Reserved bits must be set to "0".
For the read-modify-write instruction to TGIR and UDIR, "1" is read out.
These registers must be accessed in 8-bit mode.
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit6] TGIE (TriGger Interrupt Enable) : Trigger interrupt request enable bit
This bit sets whether or not to generate a trigger interrupt request when a 16-bit PPG timer activation trigger is
detected (TGIR = 1).
[bit4] UDIE (UnDerflow Interrupt Enable) : Underflow interrupt request enable bit
This bit sets whether or not to generate an underflow interrupt request when the base timer x H width setting reload
register (BTxPRLH) completed counting down and the counter underflows (UDIR = 1).
TGIE/UDIE
Description
0
Disabled.
1
Enabled.
[bit2] TGIR (TriGger Interrupt Register) : Trigger interrupt request flag bit
This bit indicates that a 16-bit PPG timer activation trigger is detected. When this bit is "1" and the TGIE bit is set to
"1", a trigger interrupt request is generated.
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[bit0] UDIR (UnDerflow Interrupt Register) : Underflow interrupt request flag bit
This bit indicates that the base timer x H width setting reload register (BTxPRLH) completed counting down and an
underflow occurred. An underflow will occur if the register attempts counting down when the 16-bit down counter
value is "0000H". When this bit is "1" and the UDIE bit is set to "1", an underflow interrupt request is generated.
TGIR/UDIR
4.4.2.
Read
Write
0
No trigger detection/underflow occurred.
This bit is cleared.
1
Trigger detection/underflow occurred.
No effect on the operation.
L Width Setting Registers 0, 1 : BTxPRLL (Base Timer 0/1
Pulse Length of "L" register)
The bit configuration of L width setting registers 0, 1 (BTxPRLL) is shown below.
These registers set the default level for the signal output from the 16-bit PPG timer.
BTxPRLL : Address Base_addr + 08H (Access: Half-word)
bit15
bit14
---
bit2
bit1
bit0
D[15:0]
Initial value
Attribute
X
X
---
X
X
X
R/W
R/W
---
R/W
R/W
R/W
Notes:
These registers must be accessed in 16-bit mode.
Set these registers after selecting a base timer function to the PPG timer using the FMD2 to FMD0 bits of the timer
control register (BTxTMCR).
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers set the default level for the signal output from the 16-bit PPG timer. When the 16-bit down counter
completes counting down the value set to these registers, the level of the output waveform (TOUT) will be inverted.
Setting these registers and the base timer x H width setting reload register (BTxPRLH) determines the widths of "L"
level and "H" level for the output signal. The signal level width set to these registers depends on the setting of the
OSEL bit of the timer control register (BTxTMCR) as follows:
OSEL=0: "L" level width
OSEL=1: "H" level width
The value set to these registers is loaded to the 16-bit down counter when a 16-bit PPG timer activation trigger is
detected or when the base timer x H width setting reload register (BTxPRLH) completed counting values and
underflows.
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4.4.3.
H Width Setting Registers 0, 1 : BTxPRLH (Base Timer
0/1 Pulse Length of "H" register)
The bit configuration of H width setting registers 0, 1 (BTxPRLH) is shown below.
These registers with a buffer set the width of signal level output when the base timer x L width setting reload register
(BTxPRLL) completes counting values.
BTxPRLH : Address Base_addr + 0AH (Access: Half-word)
bit15
bit14
---
bit2
bit1
bit0
D[15:0]
Initial value
Attribute
X
X
---
X
X
X
R/W
R/W
---
R/W
R/W
R/W
Notes:
These registers must be accessed in 16-bit mode.
Set these registers after selecting a base timer function to the PPG timer using the FMD2 to FMD0 bits of the timer
control register (BTxTMCR).
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers with a buffer set the width of signal level output when the L width setting reload register (BTxPRLL)
completes counting values. When the 16-bit down counter completes counting down the value set to these registers,
the signal level of the output waveform (TOUT) will be inverted.
Setting these registers and the base timer x L width setting reload register (BTxPRLL) determines the widths of "L"
level and "H" level for the output signal. The signal level width set to these registers depends on the setting of the
OSEL bit of the base timer x timer control register (BTxTMCR) as follows:
OSEL = 0: "H" level width
OSEL = 1: "L" level width
These registers have a buffer and thus can be rewritten during counting. These registers transfer values at the
following timing.
Transfer to the buffer
When a 16-bit PPG timer activation trigger is detected
When the base timer x H width setting reload register (BTxPRLH) completes counting down values and
underflows
Transfer to the 16-bit down counter
When counting down from the value of the base timer x L width setting reload register (BTxPRLL) is
completed.
For rewriting timing, see "Write Timing " in "5.6.3 Operation in Reload Mode".
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Chapter 20: Base Timer
4.5.
16/32-bit PWC Timer Register
This section explains registers for 16/32-bit PWC timer.
4.5.1.
Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1
STatus Control)
The bit configuration of status control registers 0, 1 (BTxSTC) is shown below.
These registers control interrupt requests.
BTxSTC : Address Base_addr + 05H (Access: Byte)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ERR
EDIE
Reserved
OVIE
Reserved
EDIR
Reserved
OVIR
0
0
0
0
0
0
0
0
R,W0
R/W
R0,W0
R/W
R0,W0
R,WX
R0,W0
R(RM1),
W
Notes:
Reserved bits must be set to "0".
For the read-modify-write instruction to OVIR, "1" is read out.
These registers must be accessed in 8-bit mode.
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD= 000).
[bit7] ERR (ERRor) : Error flag bit
This bit indicates that the next measurement is completed before the measurement result is read from the data buffer
register (BTxDTBF) in the continuous measurement mode and the measurement result has been overwritten by the
new value. The old value is discarded. This bit is cleared to "0" when a value is read from the data buffer register
(BTxDTBF).
ERR
Description
0
The measurement result has not been overwritten.
1
The measurement result has been overwritten.
[bit6] EDIE (EnD Interrupt Enable) : Measurement completion interrupt request enable bit
This bit sets whether or not to generate a measurement completion interrupt request when the measurement of the
16/32-bit PWC timer is completed (EDIR = 1).
[bit4] OVIE (OVerflow Interrupt Enable) : Overflow interrupt request enable bit
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This bit sets whether or not to generate an overflow interrupt request when the up counter overflows
(OVIR = 1).
EDIE/OVIE
Description
0
Disabled
1
Enabled
[bit2] EDIR (EnD Interrupt Register) : Measurement completion interrupt request flag bit
This bit indicates that the measurement of the 16/32-bit PWC timer is completed. When this bit is "1" and the EDIE
bit is set to "1", a measurement completion interrupt request is generated. This bit is cleared when the measurement
result (BTxDTBF) is read out.
[bit0] OVIR (OVerflow Interrupt Register) : Overflow interrupt request flag bit
This bit indicates that the up counter value has changed from "FFFFH" to "0000H" and an overflow occurred. When
this bit is "1" and the OVIE bit is set to "1", an overflow interrupt request is generated. This bit is cleared when "0" is
written.
EDIR/OVIR
624
Read
Write
0
No measurement completion/overflow
occurred.
(EDIR) No effect on the operation.
(OVIR) This bit is cleared.
1
Measurement completion/overflow
occurred.
No effect on the operation.
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Chapter 20: Base Timer
4.5.2.
Data Buffer Registers 0, 1 : BTxDTBF (Base Timer 0/1
DaTa BuFfer register)
The bit configuration of data buffer registers 0, 1 (BTxDTBF) is shown below.
These registers are used to read out the measurement value of the 16/32-bit PWC timer and the up counter value.
Notes:
These registers must be accessed in 16-bit mode.
These registers will also be initialized when reset mode is set (writing of BTxTMCR.FMD = 000).
BTxDTBF : Address Base_addr + 0AH (Access: Half-word)
bit15
bit14
---
bit2
bit1
bit0
D[15:0]
Initial value
Attribute
0
0
---
0
0
0
R,WX
R,WX
---
R,WX
R,WX
R,WX
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers are used to read out the measurement value of the 16/32-bit PWC timer and the up counter value. The
value read from these registers is different in the single measurement mode and continuous measurement mode.
Single measurement mode: The up counter value is read during counting and the measurement result is read after
the measurement completion.
Continuous measurement mode: The value measured previously is read both during counting and after the
measurement completion. The up counter value cannot be read.
The following values are set to these registers when two channels of a 16-bit PWC timer are cascaded and used as the
32-bit PWC timer.
Value of even-number channel data buffer register (BTxDTBF): Value of lower 16-bit
Value of odd-number channel data buffer register (BTxDTBF): Value of upper 16-bit
In the 32-bit timer mode, read values from these registers in the following order.
1. Even-channel data buffer register (BTxDTBF)
2. Odd-channel data buffer register (BTxDTBF)
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Chapter 20: Base Timer
5. Operation
This section explains the operation of the base timer.
5.1 Selection of Timer Function
5.2 I/O Allocation
5.3 32-bit Mode Operation
5.4 16/32-bit Reload Timer Operation
5.5 16-bit PWM Timer Operation
5.6 16-bit PPG Timer Operation
5.7 16/32-bit PWC Timer Operation
5.1.
Selection of Timer Function
This section explains selection of the timer function.
Select the timer function for BTxTMCR.FMD[2:0].
5.2.
I/O Allocation
This section explains I/O allocation.
Set I/O of the base timer for the BTSEL01 register before using the timer. You can select one of the following seven:
I/O mode 0
16-bit timer standard mode
The base timer operates separately for each channel in this mode.
I/O mode 1
32-bit timer full mode
The even-number channel signals of the base timer are allocated to the external pin in this mode.
I/O mode 2
External trigger sharing mode
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Chapter 20: Base Timer
The external activation trigger can be input to two channels of base timer at the same time in this mode. Using this
mode allows simultaneous activation of two channels of base timer.
I/O mode 4
Timer activation/stop mode
Activation/stop of the odd-number channel is controlled by the even-number channel in this mode. The odd-number
channel is started with the rising edge(*) of the output signal from the even-number channel and stops with the falling
edge(*).
I/O mode 5
Simultaneous software activation mode
More than one channels are started by the software at the same time in this mode.
I/O mode 6
Software activation timer activation/stop mode
Activation/stop of the odd-number channel is controlled by the even-number channel in this mode. The even-number
channel is started by the software. The odd-number channel is started with the rising edge(*) of the output signal from
the even-number channel and stops with the falling edge(*).
I/O mode 7
Timer activation mode
Activation of the odd-number channel is controlled by the even-number channel in this mode. The odd-number
channel is started with the rising edge(*) of the output signal from the even-number channel.
(*): Make a setting using the trigger input selection bit (BTxTMCR.EGS).
Figure 5-1 Wiring Diagram of Each I/O Mode (1)
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Chapter 20: Base Timer
Block diagram for I/O mode 0 (16-bit timer standard mode)
Base timer
ch.n
Base timer
ch.m
ECK
TGIN
TIN
TOUT
TIOBn
ECK
TGIN
TIN
TOUT
TIOBm
TIOAn
TIOAm
Block diagram for I/O mode 1 (32-bit timer full mode)
TIOBn
Base timer
ch.n
TIOAn
TIOBm
TIOAm
Block diagram for I/O mode 2 (External trigger sharing mode)
Base timer
ch.n
Base timer
ch.m
ECK
TGIN
TIN
TOUT
n:ch.1
ch.m
ECK
TGIN
TIN
TOUT
m:ch.0
Base timer
COU T
TIOB n
TIOAn
ECK
TGIN
TIN
TOUT
TIOB m
TIOAm
Block diagram for I/O mode 4 (Timer activation/stop mode)
COU T
Base timer
ch.n
Base timer
ch.m
628
DTRG
ECK
TGIN
TIN
TOUT
ECK
TGIN
TIN
TOUT
TIOB n
TIOAn
TIOB m
TIOAm
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Chapter 20: Base Timer
m: Channel 0
n: Channel 1
Figure 5-2 Wiring Diagram of Each I/O Mode (2)
Block diagram for I/O mode 5 (simultaneous software activation mode)
Software activation
bit)
signal (SSRn
(SSSRn
bit)
Base timer
ch. n
ECK
TGIN
TIN
TOUT
TIOB n
ECK
TGIN
TIN
TOUT
TIOB m
TIOAn
Software activation
bit)
signal (SSRm
(SSSRm
bit)
Base timer
ch. m
TIOAm
COUT
ch. n
TIOB n
TIOAn
Software activation
bit)bit)
signal (SSRm
(SSSRm
Base timer
ch. m
ECK
TGIN
TIN
TOUT
TIOB m
TIOAm
m:ch.0
Base timer
DTRG
ECK
TGIN
TIN
TOUT
n:ch.1
Block diagram for I/O mode 6 (software activation timer activation/stop mode)
Block diagram for I/O mode 7 (timer activation mode)
COUT
Base timer
ch. n
Base timer
ch. m
m: Channel 0
EC K
TGIN
TIN
TOUT
TIOB n
EC K
TGIN
TIN
TOUT
TIOB m
TIOAn
TIOAm
n: Channel 1
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5.3.
32-bit Mode Operation
This section explains the 32-bit mode operation.
The reload timer and PWC timer can be operated in the 32-bit mode using two channels. The basic function/operation
in the 32-bit mode is shown below.
5.3.1.
32-bit Mode Function
This section explains the 32-bit mode function.
This function realizes the operation of the 32-bit data reload timer or 32-bit data PWC timer by combining two
channels of base timer. The upper 16-bit timer counter value of the odd-number channel is also loaded when the lower
16-bit timer counter value of the even-number channel is read. Thus, the timer counter value in operation can also be
read.
5.3.2.
32-bit Mode Setting
This section explains the 32-bit mode setting.
First, set "000" to the FMD bits of the BTxTMCR register of the even-number channel to reset to the reset mode, then
select the reload timer or PWC timer and set the operation as in the 16-bit mode. While doing so, set to the 32-bit
mode by writing "1" to the T32 bit of the BTxTMCR register. Leave the T32 bit of the odd-number channel "0". You
do not have to set the reset mode. For the reload timer, set the upper 16-bit reload values of the 32-bit to the cycle
setting register of the odd-number channel, then set the lower 16-bit reload values to the cycle setting register of the
even-number channel.
The transition to the 32-bit mode is reflected immediately after the writing to the T32 bit. Thus, setting change for
both channels must be done when the counting is stopped.
To transit from the 32-bit mode to the 16-bit mode, set "000" to the FMD bits of the BTxTMCR register of the
even-number channel to reset both the even-number and odd-number channels, and make a setting in the 16-bit
mode for each channel.
5.3.3.
32-bit Mode Operation
This section explains 32-bit mode operation.
After setting the 32-bit mode when the reload timer or PWC timer is started with the control of the even-number
channel, the timer/counter of the even-number channel operates with lower 16-bit and the timer/counter of the
odd-number channel operates with upper 16-bit.
The 32-bit mode operation depends on the setting of the even-number channel. Thus, the setting of the odd-number
channel (excepting the cycle setting register for the reload timer) is ignored. Timer activation, waveform output and
interrupt signal also apply the setting of the even-number channel. (The odd-number channel is masked with the value
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Chapter 20: Base Timer
fixed to L.)
For the configuration, see "Figure 5-11 Configuration in 32-bit Timer Mode" and "Figure 5-29 Configuration in 32-bit
Timer Mode"
5.4.
16/32-bit Reload Timer Operation
This section explains the 16/32-bit reload timer operation.
This section explains the operation performed when the base timer included in this series is used as the 16/32-bit
reload timer. An example is also given to set various operation conditions.
Figure 5-3 Block Diagram (16-bit Reload Timer Operation)
16-bit mode
T32=0
OSEL
BTxPCSR
Invert control
CKS
3
Output waveform
(TOUT signal)
Toggle
generation
16
20
Peripheral clock
Division
(PCLK)
circuit
External clock
(ECK signal)
Count clock
27
Load
28
Down counter
BTxTMR
Edge
detection
Count
enabled
EGS
2
Underflow
MDSE
Count
enabled
External activation
edge (TGIN signal)
T32
UDIE
STRG
IRQ0
Trigger
CTEN
Edge
detection
CTEN
Underflow
interrupt request
Interrupt
source
factor
generation
Timer enabled
Trigger
interrupt request
IRQ1
TGIE
BTxTMR :: Base
BaseTimer
timer xx timer
BTxTMR
timer register
register (BTxTMR)
(BTxTMR)
BTxPCSR : Base timer x cycle setting register (BTxPCSR)
BTxPCSR : Base Timer x cycle setting register (BTxPCSR)
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Chapter 20: Base Timer
Figure 5-4 Block Diagram (32-bit Reload Timer Operation)
ch.1
BT1PCSR
16
Load
Count clock
Down counter
BT1TMR )
Count
enabled
Underflow
T3 2= 0
32-bit mode
T3 2=1
ch.0
OSE L
BT0PCSR
Invert control
CK S
3
Output waveform
(TOUT signal)
Toggle
generation
16
20
Peripheral clock
PCL K
External clock
(ECK signal)
Division
circuit
Load
27
Count clock
28
Down counter
BT0T MR
Edge
detection
Count
enabled
Underflow
T3 2
EG S
2
MDS E
Count
enabled
External activation
trigger (TGIN signal)
UDIE
STR G
IRQ0
Trigger
CTE N
Edge
detection
CTE N
Underflow
interrupt request
Interrupt
factor
source
generation
Timer enabled
Trigger
interrupt request
IRQ1
TG IE
BT1PCSR : Base timer 1 cycle setting register (BT1PCSR)
BT1TMR : Base timer 1 timer register (BT1TMR)
BT0PCSR : Base timer 0 cycle setting register (BT0PCSR)
BT0TMR : Base timer 0 timer register (BT0TMR)
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5.4.1.
Overview
This section explains the overview of the 16/32-bit reload timer operation.
The 16/32-bit reload timer is a timer that decreases from the value set in the base timer x cycle setting register
(BTxPCSR). This timer has a function of generating an underflow interrupt request when the down counter
underflows.
The 16/32-bit reload timer has two modes: Timer mode and operation mode. The operation of the timer varies in
accordance with combinations of these modes.
Timer mode: One of the following two modes can be selected using the T32 bit of the base timer x timer control
register (BTxTMCR).
16-bit timer mode (T32 = 0): 16-bit reload timer can operate individually for each of the channels.
32-bit timer mode (T32 = 1): 2 channels can be cascaded and used as a 32-bit reload timer.
Operation mode: One of the following two modes can be selected using the MDSE bit of the base timer x timer
control register (BTxTMCR).
Reload mode (MDSE = 0): In this mode, when the down counter underflows, the preset value (cycle) is
reloaded to allow the timer to restart counting.
One-shot mode (MDSE = 1): Once the down counter underflows, the counter will no longer count.
5.4.2.
Operation in Reload Mode
This section explains the operation in reload mode.
This section explains the operation in reload mode.
Overview
In this mode, the value set in the base timer x cycle setting register (BTxPCSR) is reloaded every time an underflow
occurs to ensure that countdown is continued. To use this mode, set reload mode by resetting the MDSE bit of the
base timer x timer control register (BTxTMCR) to "0"(MDSE=0).
Operation
Activation
Activate the 16/32-bit reload timer with the following procedure:
1.
2.
Permit 16/32-bit reload timer operation by setting the CTEN bit of the base timer x timer control register
(BTxTMCR) to "1"(CTEN=1).
The 16/32-bit reload timer begins to wait for an activation trigger.
Enter an activation trigger by one of the following methods:
Set the STRG bit of the base timer x timer control register (BTxTMCR) to "1" (software trigger).
Enter an effective edge (an edge set in the EGS1 and EGS0 bits) for an external activation trigger (TGIN
signal).
Notes:
The external activation trigger (TGIN signal) entry method varies depending on the I/O mode specified by the I/O
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selection register (BTSEL01). See "5.2 I/O Allocation".
To start counting as soon as the operation is permitted, set both CTEN and STRG bits of the base timer x timer
control register (BTxTMCR) to "1".
Counting Operation
When an activation trigger is input, the value (cycle) set in the base timer x cycle setting register (BTxPCSR) is
loaded to the down counter, which begins counting down, after one of the following lengths of time elapses:
If a software trigger is input: 1T (T: Count clock cycle)
If an external activation trigger (TGIN signal) is input: 2T to 3T (T: Count clock cycle)
Figure 5-5 and Figure 5-6 show the count start timing.
Figure 5-5 Count Start Timing (Software Trigger)
Load
Count clock
XXXX H
Counter value
Reload value
-1
-1
CTEN bit
1T
STRG bit
Figure 5-6 Count Start Timing (External Activation Trigger (TGIN Signal), Effective Edge = Rising
Edge)
External activation
trigger
2T to 3T (external trigger)
Load
Count clock
Counter value
0000H
Reload value
-1
-1
Note:
The external activation trigger (TGIN signal) entry method varies depending on the I/O mode specified by the I/O
selection register (BTSEL01). See "5.2 I/O Allocation".
When the down counter underflows after attempting to count down further from the value of "0000 H", the value
(cycle) set in the base timer x cycle setting register (BTxPCSR) is reloaded to the down counter, which continues to
count down. If an underflow occurs, theUDIR bit of the base timer x status control register (BTxSTC) changes to "1".
At this time, an underflow interrupt request occurs if the UDIE bit is set to "1". Figure 5-7 shows the operation in case
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of an underflow.
Figure 5-7 Operation in Case of an Underflow
Load
Count clock
Counter value
0000
000H
0
H
-1
Reload value
-1
1
Underflow
UDIR
Output Waveform
The waveform (TOUT signal) of the 16/32-bit reload timer can be output. The waveform (TOUT signal) to be output
varies according to the setting of the OSEL bit of the base timer x timer control register (BTxTMCR).
Table 5-1 Correspondence between Output Polarities and Output Waveforms
Output polarity
Output waveform
Normal polarity
(OSEL = 0)
"L" level pulse is output when counting starts.
Thereafter, the output level is inverted every time an underflow occurs.
Inverted polarity
(OSEL = 1)
"H" level pulse is output when counting starts.
Thereafter, the output level is inverted every time an underflow occurs.
Figure 5-8 shows the output waveform in reload mode.
Figure 5-8 Output Waveform in Reload Mode (Normal Polarity)
CTEN bit
Opposite (Inversion) level when OSEL=1
TI O A0, TIOA1 pins
Activation trigger
Underflow
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Chapter 20: Base Timer
5.4.3.
Operation in One-Shot Mode
This section explains the operation in one-shot mode.
This section explains the operation in one-shot mode.
Overview
In this mode, the counter will no longer count down once an underflow occurs.
To use this mode, set one-shot mode by setting the MDSE bit of the base timer x timer control register (BTxTMCR)
to "1"(MDSE=1).
Operation
Activation
The same operation as in reload mode. See " Operation" in "5.4.2 Operation in Reload Mode".
Counting Operation
The operation is the same as in reload mode until an underflow occurs. See " Operation". When the down counter
underflows, the value (cycle) set in the base timer x cycle setting register (BTxPCSR) is reloaded to the down counter.
However, the down counter stops counting. If an underflow occurs, the UDIR bit of the base timer x status control
register (BTxSTC) changes to "1". At this time, an underflow interrupt request occurs if the UDIE bit of the base
timer x status control register (BTxSTC) is set to "1".
Figure 5-9 shows the operation in case of an underflow.
Figure 5-9 Operation in Case of an Underflow
Load
Count clock
Counter value
0000H
Reload value
-1
-1
Underflow
UDIR
Output Waveform
The waveform (TOUT signal) of the 16/32-bit reload timer can be output. The waveform (TOUT signal) to be output
varies according to the setting of the OSEL bit of the base timer x timer control register (BTxTMCR).
Table 5-2 shows the correspondence between output polarities and output waveforms.
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Table 5-2 Correspondence between Output Polarities and Output Waveforms
Output polarity
Output waveform
Normal polarity
(OSEL = 0)
When an activation trigger is input (counting in progress), "H" level pulse is
output.
"L" level pulse is output while the timer waits for an activation trigger.
Inverted polarity
(OSEL = 1)
When an activation trigger is input (counting in progress), "L" level pulse is
output.
"H" level pulse is output while the timer waits for an activation trigger.
Figure 5-10 shows the output waveform in one-shot mode.
Figure 5-10 Output Waveform in One-shot Mode (Normal Polarity)
CTEN bit
Opposite (Inversion) level when OSEL=1
TI O A0 , TIOA1 pins
Activation trigger
Underflow
Waiting for activation trigger
5.4.4.
32-bit Timer Mode Operation
This section explains the 32-bit timer mode operation.
This section explains the setting and operation for cascading 2 channels of a 16-bit reload timer and using them as a
32-bit reload timer.
Overview
Using the T32 bit of the base timer x timer control register (BTxTMCR), 2 channels of a 16-bit reload timer can be
cascaded and used as a 32-bit reload timer. In this mode, the even-number channel corresponds to the lower 16-bit
operation, and the odd-number channel corresponds to the upper 16-bit operation. Therefore, set the reload values in
the order of the upper 16 bits (odd-number channels) → the lower 16 bits (even-number channels) and read the down
counter values in the order of the lower 16 bits (even-number channels) → the upper 16 bits (odd-number channels).
Setting Procedure (Example)
To set 32-bit timer mode, set the T32 bit of the base timer x timer control register (BTxTMCR) of even-number
channels to "1" and the T32 bit of the base timer x timer control register (BTxTMCR) of the odd-number channels to
"0". When setting 32-bit timer mode, set the registers using the procedure shown below. Different register settings
should be used between even-number and odd-number channels. The following shows an example of using a cascade
connection.
1.
Specify ch.0 to reset mode by setting FMD2 to FMD0 bits of base timer 0 timer control register (BT0TMCR).
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2.
3.
4.
(FMD2 to FMD0 = 000)
Select 16/32-bit reload timer for ch.0 and ch.1 by setting the FMD2 to FMD0 bits of the base timer x timer
control register (BT0TMCR, BT1TMCR) of ch.0 and ch.1. (FMD2 to FMD0 = 011)
At the same time, select 32-bit timer mode by setting the T32 bit of the base timer 0 timer control register
(BT0TMCR). (T32=1)
Set a reload value in the upper 16 bits in the base timer 1 cycle setting register (BT1PCSR).
Set a reload value in the lower 16 bits in the base timer 0 cycle setting register (BT0PCSR).
Notes:
Rewrite the T32 bit while the operation of both of the even-number and odd-number channels is stopped. Whether
the counting operation is stopped can be checked by setting the CTEN bit of the base timer x timer control register
(BTxTMCR) to "0"(CTEN=0).
A reload value in the base timer x cycle setting register (BTxPCSR) must be set in the order of the odd-number →
even-number channels.
Operation
In 32-bit timer mode, the counting operation is basically the same as in 16-bit timer mode.
However, the counting operation conforms to the settings of the even-number channels, ignoring the settings of the
following registers for the odd-number channels.
Base timer x timer control register (BTxTMCR)
Base timer x status control register (BTxSTC)
This section explains the counting in the 32-bit timer mode.
1.
2.
3.
When the 32-bit reload timer activates, the values in the odd-number channel base timer x cycle setting
register (BTxPCSR) and the even-number channel base timer x cycle setting register (BTxPCSR) (lower
16-bit) are loaded to the down counter.
The down counter starts counting as a 32-bit counter with the even-number channels serving as the lower
16-bit and the odd-number channels as the upper 16-bit.
When the down counter underflows, the UDIR bit of the base timer x timer control register (BTxTMCR) of
the even-number channels changes to "1".
Figure 5-11 shows the channel configuration in 32-bit timer mode.
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Chapter 20: Base Timer
Figure 5-11 Configuration in 32-bit Timer Mode
Underflow
Overflow
Underflow
ch.1
Upper 16-bit
Upper
timer/counter
down
counter
Upper 16-bit
reload value
ch.0
Interrupt request
Underflow
Underflow
Overflow
Read/write signal
Lower 16-bit
16-bit
Lower
timer/counter
down
counter
Waveform output
Lower 16-bit
reload value
T32=0
T32=1
PWC measurement waveform /
External activation trigger
Notes:
The value of the down counter can be checked by reading the base timer x timer register (BTxTMR). In the 32-bit
timer mode, it must be read in the order of the lower 16-bit (even-number channel) → upper 16-bit (odd-number
channel).
In 32-bit timer mode, the operation of the 32-bit reload timer conforms to the settings of the even-number channels.
Therefore, activation triggers and interrupt requests from even-number channels are valid. The output signal
(TOUT) from an odd-number channel pin is fixed to "L" level.
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5.4.5.
Interrupts
This section explains interrupts of the base timer.
An interrupt request is generated in one of the following events:
An activation trigger is detected. (trigger interrupt request)
An underflow occurs (underflow interrupt request).
Table 5-3 Interrupt Occurrence Conditions
Interrupt request
Interrupt request
flag
Permission of
interrupt request
Interrupt request clear
BTxSTC:TGIR=1
BTxSTC:TGIE=1
Set the TGIR bit of BTxSTC
to "0".
Underflow interrupt request BTxSTC:UDIR=1
BTxSTC:UDIE=1
Set the UDIR bit of BTxSTC
to "0".
Trigger interrupt request
Notes:
Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request
will be issued when the interrupt is enabled. To enable the generation of an interrupt request, perform one of the
following operations:
Clear the current interrupt request before enabling the generation of an interrupt request.
Clear the current interrupt request when enabling the interrupt.
Either clear the current interrupt request after disabling the generation of an interrupt request or clear the current
interrupt request within the interrupt processing routine.
For interrupt vector numbers used when issuing an interrupt request, see "List of Interrupts Vector" in entitled
"APPENDIX".
Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00
to ICR47). For information on interrupt level setting, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
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5.4.6.
Precautions for Using this Device
This section explains precautions for using this device.
Note the following when using the 16/32-bit reload timer:
Notes on Program Setting
Change the following bits of the base timer x timer control register (BTxTMCR) after stopping the 16-bit down
counter by resetting CTEN bit to "0"(CTEN=0).
CKS2 to CKS0 bits
EGS1 and EGS0 bits
T32 bit
FMD2 to FMD0 bits
MDSE bit
All registers are initialized when the FMD2 to FMD0 bits of the timer control register (BTxTMCR) are set to
"000" to select reset mode.
Before the base timer function or T32 bit can be changed, the base timer must be reset once. Except when rewriting
the status of FMD2 to FMD0 bits or T32 bit of the timer control register (BTxTMCR) after a reset, be sure to set
the FMD2 to FMD0 bits to "000" to select the reset mode. Then, rewrite the status of these bits.
Notes on Operations
If the count timing of the down counter and the load timing occur at the same time, the load operation is given
precedence.
If a 16/32-bit reload timer activation trigger is detected when counting ends in one-shot mode, the value (cycle) set
in the base timer x cycle setting register (BTxPCSR) is loaded to the 16-bit down counter, which begins counting.
A different signal (external clock, external activation trigger, waveform) I/O operation can be selected using the
base timer I/O selection function.
Note on Interrupts
If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur
at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1".
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5.5.
16-bit PWM Timer Operation
This section explains the 16-bit PWM timer operation.
This section explains the operation performed when the base timer included in this series is used as the 16-bit PWM
timer. An example is also given to set various operation conditions.
Figure 5-12 Block Diagram (16-bit PWM Timer Operation)
BTxPDU T
BTxPCSR
Load
BTxPDU T
Writing
Buffer
CKS
Peripheral clock
PCLK
External clock
(ECK signal)
2
0
2
7
Buffer
OSEL
3
16
16
Invert control
Match detection
Division
circuit
Count clock
28
Load
16
16-bit
Down counter
Edge
detection
Count
enabled
EGS
Toggle
generation
Underflow
2
DTIE
UDIE
STR G CTEN
Count
enabled
MDSE
External activation trigger
(TGIN signal)
Edge
detection
Waveform output
(TOUT signal)
PMSK
Trigger
Timer enabled
Underflow/duty
match interrupt
request
IRQ0
Interrupt
factor
source
generation
IRQ1
CTEN
Trigger interrupt request
TGIE
BTxPCSR: Base timer x cycle setting register (BTxPCSR)
BTxPDUT: Base timer x duty setting register (BTxPDUT)
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5.5.1.
Overview
This section explains the overview of the 16-bit PWM timer operation.
The 16-bit PWM timer sets the cycle in the cycle setting register (BTxPCSR) and the duty in the duty setting register
(BTxPDUT). A desired waveform (TOUT signal) can be output by setting values in these registers. The 16-bit PWM
timer starts decreasing from the value set in the base timer x cycle setting register (BTxPCSR). When the value of the
down counter matches the value of the duty setting register (BTxPDUT), the output signal (TOUT) level is inverted.
When the down counter underflows, the output level is inverted again. This method enables output of a desired
waveform (TOUT signal) with a cycle and duty.
One of two 16-bit PWM timer operation modes can be selected using the MDSE bit of the timer control register
(BTxTMCR) as follows:
Reload mode (MDSE = 0): In this mode, when the 16-bit down counter underflows, the preset cycle is reloaded to
allow the timer to restart counting.
One-shot mode (MDSE = 1): Once the 16-bit down counter underflows, the counter will no longer count.
5.5.2.
Operation in Reload Mode
This section explains the operation in reload mode.
This section explains the operation in reload mode.
Overview
In this mode, the value set in the base timer x cycle setting register (BTxPCSR) is reloaded every time an underflow
occurs to ensure that countdown is continued. To use this mode, set reload mode by resetting the MDSE bit of the
base timer x timer control register (BTxTMCR) to "0"(MDSE=0).
Operation
Activation
Activate the 16-bit PWM timer with the following procedure:
1.
2.
Permit the 16-bit PWM timer operation by setting the CTEN bit of the base timer x timer control register
(BTxTMCR) to "1"(CTEN=1).
The 16-bit PWM timer begins to wait for an activation trigger.
Enter an activation trigger by one of the following methods:
Set the STRG bit of the base timer x timer control register (BTxTMCR) to "1" (software trigger).
Enter an effective edge (an edge set in the EGS1 and EGS0 bits) for an external activation trigger (TGIN
signal).
The 16-bit down counter starts decreasing from the value set in the base timer x cycle setting register (BTxPCSR).
Notes:
The external activation trigger (TGIN signal) entry method varies depending on the I/O mode specified by the I/O
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selection register (BTSEL01).
After a 16-bit PWM timer activation trigger is detected, the following time is required before the value set in the
base timer x cycle setting register (BTxPCSR) can be loaded to the 16-bit down counter:
If a software trigger is input: 1T (T: Count clock cycle)
If an external event trigger is used: 2T to 3T (T:Count clock cycle)
Counting Operation
When an activation trigger is input, the 16-bit down counter, in synchronization with the count clock, starts
decreasing from the value set in the cycle setting register (BTxPCSR).
When the value of the 16-bit down counter matches the value of the duty setting register (BTxPDUT), the operation is
performed as follows:
The DTIR bit of the status control register (BTxSTC) changes to "1".
The level of the output signal (TOUT) is inverted.
Countdown is continued. Later, when the 16-bit down counter underflows, the operation is performed as follows:
The UDIR bit of the status control register (BTxSTC) changes to "1" and the level of the output signal (TOUT) is
inverted.
The value of the cycle setting register (BTxPCSR) is reloaded to continue countdown.
Every time an underflow occurs, the value of the cycle setting register (BTxPCSR) is reloaded to continue counting.
Operation to be performed when an activation trigger is input during counting depends on whether reactivation is
permitted based on the RTGEN bit of the timer control register (BTxTMCR).
If reactivation is not permitted (RTGEN = 0): Any activation trigger is ignored when it is entered during counting.
If reactivation is permitted (RTGEN = 1): The TGIR bit of the base timer x status control register (BTxSTC)
changes to "1". In addition, the value set in the base timer x cycle setting register (BTxPCSR) is reloaded to the
16-bit down counter, which begins counting.
These operations are shown below.
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Figure 5-13 Counting Operation
Counting operation when reactivation is not enabled
Rising edge detection
Activation trigger is ignored
Activation trigger
m
n
0
PWM output waveform
(1)
(2)
(1) = T(n +1) ms
(2) = T(m +1)ms
m : Value of base timer x cycle setting register (BTxPCSR)
n : Value of base timer x duty setting register (BTxPDUT)
T : Cycle of count clock
Counting operation when reactivation is enabled
Rising edge detection Reactivate with trigger
Activation trigger
m
n
0
PWM output waveform
(1)
(2)
(1) = T( n+1 )ms
(2) = T( m+ 1)ms
m : Value of base timer x cycle setting register (BTxPCSR)
n : Value of base timer x duty setting register (BTxPDUT)
T : Cycle of count clock
Note:
If the count timing of the 16-bit down counter and the load timing occur at the same time, the load operation is given
precedence.
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Output Waveform
The waveform (TOUT signal) of the 16-bit PWM timer can be output. The waveform (TOUT signal) to be output
varies according to the setting of the OSEL bit of the base timer x timer control register (BTxTMCR).
Normal polarity (OSEL = 0)
When the 16-bit PWM timer is activated: "L" level
When a duty match occurs: "H" level
When an underflow occurs: "L" level
Inverted polarity (OSEL = 1)
When the 16-bit PWM timer is activated: "H" level
When a duty match occurs: "L" level
When an underflow occurs: "H" level
The output (TOUT signal) can be fixed at the "L" or "H" level.
The output level varies depending on the setting of the OSEL bit of the base timer x timer control register
(BTxTMCR). Examples of procedures are shown below.
Figure 5-14 Examples of Procedures for Fixing to "L" and "H" Levels
Example of procedure for fixing to " L" level (OSEL = 0)
Underflow interrupt request
Duty value
0002 H
0001 H
0000 H
XXXXH
PWM output
waveform
Decrement duty value
"1" is set to the PMSK bit with an underflow interrupt.
The output signal will be fixed to the " L" level from the set cycle.
PMSK bit : PMSK bit of base timer x timer control register (BTxTMCR)
Example of procedure for fixing to "H" level (OSEL = 0)
Duty match interrupt request
PWM output
waveform
Increment duty value
If the duty value is set to the cycle setting value when a duty match
interrupt request is generated, the output signal will be fixed to the
" H" level in the next cycle.
Note:
The output method and output destination of the waveform (TOUT signal) from the 16-bit PWM timer depend on the
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Chapter 20: Base Timer
following settings:
Base timer I/O mode
TIOA0, TIOA1 pin functions
Interrupt Generation Timing
The 16-bit PPG timer can generate an interrupt request in one of the following events:
An activation trigger is detected.
The value of the 16-bit down counter matches the value of the base timer x duty setting register (BTxPDUT)
When an underflow occurs:
An example of interrupt request generation timing using the following settings is shown below.
Value of the cycle setting register (BTxPCSR) = 0003 H
Value of the duty setting register (BTxPDUT) = 0001 H
Figure 5-15 Interrupt Request Generation Timing Chart
Activation trigger
2T to 3T (external activation trigger)
Load
Count clock
Counter value
XXXXH
0003 H
0002 H
0001 H
0000 H
0003 H
0002 H
PWM output
waveform
Interrupt request
Activation edge
trigger interrupt
request (TGIR bit)
Duty match
interrupt request
(DTIR bit)
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Underflow
interrupt request
(UDIR bit)
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5.5.3.
Operation in One-Shot Mode
This section explains the operation in one-shot mode.
This section explains the operation in one-shot mode.
Counting Operation
In this mode, counting stops if an underflow occurs when the value of the 16-bit down counter changes from the
value set in the cycle setting register (BTxPCSR) to "FFFFH".
To use this mode, set one-shot mode by setting the MDSE bit of the timer control register (BTxTMCR) to
"1"(MDSE=1).
Activation
It is the same operation as in reload mode. See "Operation" in the section entitled "5.5.2 Operation in Reload
Mode".
Counting Operation
When an activation trigger is input, the 16-bit down counter, in synchronization with the count clock, starts
decreasing from the value set in the cycle setting register (BTxPCSR). When the value of the 16-bit down counter
matches the value of the duty setting register (BTxPDUT), the operation is performed as follows:
The DTIR bit of the base timer x status control register (BTxSTC) changes to "1".
The level of the output signal (TOUT signal) is inverted.
Countdown is continued. Later, when the 16-bit down counter underflows, the operation is performed as follows:
The UDIR bit of the base timer x status control register (BTxSTC) changes to "1".
The level of the output signal (TOUT signal) is inverted.
Counting stops (The 16-bit down counter stops at the value "FFFFH").
Operation to be performed when an activation trigger is input during counting depends on whether reactivation is
permitted based on the RTGEN bit of the timer control register (BTxTMCR).
If reactivation is not permitted (RTGEN = 0): Any activation trigger is ignored when it is entered during counting.
If reactivation is permitted (RTGEN = 1): The TGIR bit of the base timer x status control register (BTxSTC)
changes to "1". In addition, the value set in the base timer x cycle setting register (BTxPCSR) is reloaded to the
16-bit down counter, which begins counting.
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Figure 5-16 Counting Operation
Counting operation when reactivation is disabled
Rising edge detection
Activation trigger is ignored
Activation trigger
m
n
0
PWM output waveform
= T(n+1) ms
= T(m+1) ms
m : Value of base timer x cycle setting register (BTxPCSR)
n : Value of base timer x duty setting register (BTxPDUT)
T : Count clock cycle
Counting operation when reactivation is enabled
Rising edge detection
Reactivate with activation trigger
Activation trigger
m
n
0
PWM output waveform
= T(n+1) ms
= T(m+1) ms
m : Value of base timer x cycle setting register (BTxPCSR)
n : Value of base timer x duty setting register (BTxPDUT)
T : Count clock cycle
Note:
If a 16-bit PWM timer activation trigger is detected when counting ends, the value set in the cycle setting register
(BTxPCSR) is loaded to the 16-bit down counter, which begins counting.
Output Waveform
It is the same operation as in reload mode. See "Output Waveform" in "5.5.2 Operation in Reload Mode".
Interrupt Generation Timing
It is the same operation as in reload mode. See "Interrupt Generation Timing" in "5.5.2 Operation in Reload Mode".
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5.5.4.
Interrupt
This section explains interrupts.
An interrupt request is generated in one of the following events:
An activation trigger is detected. (trigger interrupt request)
The value of the 16-bit down counter matches the value of (the base timer x duty setting register (BTxPDUT))
(duty match interrupt request).
An underflow occurs (underflow interrupt request).
Table 5-4 Conditions for Interrupt Generation
Interrupt request
Interrupt request
flag
Permission of
interrupt request
Interrupt request clear
Trigger interrupt request
BTxSTC:TGIR = 1
BTxSTC:TGIE = 1
Set the TGIR bit of BTxSTC
to "0".
Duty match interrupt request
BTxSTC:DTIR=1
BTxSTC:DTIE=1
Set the DTIR bit of BTxSTC
to "0".
Underflow interrupt request
BTxSTC:UDIR = 1
BTxSTC:UDIE = 1
Set the UDIR bit of BTxSTC
to "0".
Notes:
Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request
will be issued when the interrupt is enabled. To enable the generation of an interrupt request, perform one of the
following operations:
Clear the current interrupt request before enabling the generation of an interrupt request.
Clear the current interrupt request when enabling the interrupt.
Either clear the current interrupt request after disabling the generation of an interrupt request or clear the current
interrupt request within the interrupt processing routine.
For interrupt vector numbers used when issuing an interrupt request, see "List of Interrupts Vector" in entitled
"APPENDIX".
Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00
to ICR47). For information on interrupt level setting, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
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5.5.5.
Precautions for Using this Device
This section explains precautions for using this device.
Note the following when using the 16-bit PWM timer:
Notes on Program Setting
Change the following bits of the timer control register (BTxTMCR) only after stopping the 16-bit down counter by
resetting the CTEN bit to "0"(CTEN=0).
CKS2 to CKS0 bits
EGS1 and EGS0 bits
FMD2 to FMD0 bits
MDSE bit
All registers are initialized when the FMD2 to FMD0 bits of the base timer x timer control register (BTxTMCR)
are set to "000" to select reset mode.
Before the base timer function can be changed, the base timer must be reset once. Except when rewriting the
FMD2 to FMD0 bits of the base timer x timer control register (BTxTMCR) after reset, be sure to clear FMD2 to
FMD0 bits to "000" to select the reset mode, and then select a base timer function using the FMD2 to FMD0 bits
again.
To set 16-bit PWM timer cycles or duties, proceed as follows:
1. Select the 16-bit PWM timer as the base timer function by setting the FMD2 to FMD0 bits of the base timer x
timer control register (BTxTMCR) to "001"(FMD2 to FMD0=001).
2. Set the cycle in the base timer x cycle setting register (BTxPCSR).
3. Set the duty in the base timer x duty setting register (BTxPDUT).
Notes on Operation
If the count timing of the 16-bit down counter and the load timing occur at the same time, the load operation is
given precedence.
When a 16-bit PWM timer reactivation trigger is detected when counting ends in one-shot mode, the value in the
base timer x cycle setting register (BTxPCSR) is loaded to the 16-bit down counter, which then starts counting.
A different signal (external clock, external activation trigger, waveform) I/O operation can be selected using the
base timer I/O selection function.
Note on Interrupts
If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur
at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1".
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5.6.
16-bit PPG Timer Operation
This section explains the 16-bit PPG timer operation.
This section explains the operation performed when the base timer included in this series is used as the 16-bit PPG
timer. Examples of procedures for setting various operating conditions are also provided.
Figure 5-17 Block Diagram (16-bit PPG Timer Operation)
CK S
Reload data setting
BTxPRLL
16
3
BTxPRLH
Buffer
20
Peripheral clock
PCLK
Division
circuit
27
External clock
(ECK signal)
Load
Count clock
28
OS EL Invert control
PP G output
Down counter
BTC T
Edge
detection
(TOUT signal)
Count
enabled
EGS
Underflow
Toggle
generation
2
PMS K
UDIE
STR G
CTE N
Count
enabled
MDS E
External activation trigger
(TGIN signal)
Edge
detection
CTE N
Underflow
interrupt request
IRQ0
Interrupt
factor
source
generation
Trigger interrupt request
IRQ1
Trigger
Timer enabled
TGIE
BTxPRLL : Base timer x L width setting reload (BTxPRLL)
BTxPRLH : Base timer x H width setting reload (BTxPRLH)
BTxTMR : Base timer x timer register (BTxTMR)
5.6.1.
Overview
This section explains the overview of the 16-bit PPG timer operation.
The 16-bit PPG timer, once activated, decreases from the value initially specified by the base timer x L width setting
reload register (BTxPRLL). When counting down from the value set in the L width setting reload register (BTxPRLL)
is completed, the timer begins counting down from the value set in the H width setting reload register (BTxPRLH).
When counting down from the value set in each register is completed, the output signal (TOUT) inverts its level.
Therefore, by configuring the L width setting reload register (BTxPRLL) and H width setting reload register
(BTxPRLH), you can arbitrarily set the widths of the "L" and "H" levels.
One of two 16-bit PPG timer operation modes can be selected using the MDSE bit of the timer control register
(BTxTMCR) as follows:
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Reload mode (MDSE = 0): A sequence of "L"-level and "H"-level signals (consecutive pulses) is output.
One-shot mode (MDSE = 1): A string of one "L"-level signal and one "H"-level signal (single pulses) is output.
5.6.2.
Pulse Width Calculation Method
This section explains the pulse width calculation method.
When the 16-bit PPG timer has counted down by the value set in the L width setting reload register (BTxPRLL) or
base timer x H width setting reload register (BTxPRLH) plus 1, the output signal (TOUT) inverts its level. Therefore,
the pulse width of the signal to be output is obtained by the following formula:
Example: If the output polarity is normal:
"L" level pulse width = T × (L + 1)
"H" level pulse width = T × (H + 1)
T: Count clock cycle
L: Value set in the base timer x L width setting reload register (BTxPRLL)
H: Value set in the base timer x H width setting reload register (BTxPRLH)
This means that when the L width setting reload register (BTxPRLL) and H width setting reload register (BTxPRLH)
are set to "0000H", the pulse width will be equal to one cycle of the count clock. When they are set to "FFFFH", the
pulse width will be equal to 65536 cycles of the count clock.
5.6.3.
Operation in Reload Mode
This section explains the operation in reload mode.
This section explains the operation in reload mode.
Overview
In this mode, the values set in the base timer x L width setting reload register (BTxPRLL) and base timer x H width
setting reload register (BTxPRLH) are alternately reloaded to the down counter to ensure that the down counter
continues to count down. A desired pulse width can be output continuously by rewriting the base timer x L width
setting reload register (BTxPRLL) and base timer x H width setting reload register (BTxPRLH) each time an
underflow interrupt request is issued.
To use this mode, set reload mode by resetting the MDSE bit of the base timer x timer control register (BTxTMCR) to
"0"(MDSE=0).
Operation
Activation
Activate the 16-bit PPG timer with the following procedure:
1.
Permit the 16-bit PPG timer operation by setting the CTEN bit of the timer control register (BTxTMCR) to
"1"(CTEN=1). The 16-bit PPG timer begins to wait for an activation trigger.
2. Enter an activation trigger by one of the following methods:
Set the STRG bit of the base timer x timer control register (BTxTMCR) to "1" (software trigger).
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Enter an effective edge (an edge set in the EGS1 and EGS0 bits) for an external activation trigger (TGIN
signal).
Notes:
The external activation trigger (TGIN signal) entry method varies depending on the I/O mode specified by the I/O
selection register (BTSEL01).
After a 16-bit PPG timer activation trigger is detected, the following time is required before the value (cycle) set in
the L width setting reload register (BTxPRLL) can be loaded to the 16-bit down counter:
If a software trigger is input: 1T (T: Count clock cycle)
If an external event trigger is used: 2T to 3T (T:Count clock cycle)
Counting Operation
Counting operation initiated by the entry of an activation trigger is explained below, using an example where the
OSEL bit of the timer control register (BTxTMCR) is set for normal polarity (OSEL = 0).
1.
2.
3.
4.
5.
6.
The value set in the L width setting reload register (BTxPRLL) is transferred to the 16-bit down counter and
the value set in the base timer x H width setting reload register (BTxPRLH) is transferred to the buffer. The
16-bit down counter begins to count down from the value of the L width setting reload register (BTxPRLL).
The output signal (TOUT) is at the "L" level.
The 16-bit down counter completes counting down from the value of L width setting reload register
(BTxPRLL).
The buffered value of H width setting reload register (BTxPRLH) is reloaded to the 16-bit down counter,
which continues counting down. The output signal (TOUT) is at the "H" level.
The 16-bit down counter completes counting down from the value of H width setting reload register
(BTxPRLH), thus causing an underflow.
The value of L width setting reload register (BTxPRLL) is reloaded to the 16-bit down counter, which
continues count down. The output signal (TOUT) is at the "L" level. In addition, the value of the H width
setting reload register (BTxPRLH) is transferred to the buffer.
Steps 2 to 5 are repeated to continue counting.
Operation that is performed if reactivation is permitted or not during counting depends on whether reactivation is
permitted based on the RTGEN bit of the timer control register (BTxTMCR).
If reactivation is not permitted (RTGEN = 0): Any activation trigger is ignored when it is entered during counting.
If reactivation is permitted (RTGEN = 1): The TGIR bit of the base timer x status control register (BTxSTC)
changes to "1". In addition, the value of L width setting reload register (BTxPRLL) is reloaded to the 16-bit down
counter, which starts counting.
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Figure 5-18 Example of Counting Operation in Reload Mode
Counting operation when reactivation is disabled
Rising edge detection
Activation trigger is ignored.
Activation trigger
m
n
0
PPG output waveform
(1)
Trigger interrupt
request
(TGIR bit)
Interrupt request
(2)
Underflow
interrupt request
(UDIR bit)
Underflow
interrupt request
(UDIR bit)
(1) = T( m + 1 ) ms
(2) = T( n + 1 ) ms
m : Value of base timer x L width setting reload register (BTxPRLL)
n : Value of base timer x H width setting reload register (BTxPRLH)
T : Count clock cycle
Counting operation when reactivation is enabled
Rising edge detection
Reactivate with activation trigger
Activation trigger
m
n
0
PPG output waveform
(1)
Trigger interrupt
request
(TGIR bit)
Trigger interrupt
request
(TGIR bit)
(2)
Underflow
interrupt request
(UDIR bit)
(1) = T( m + 1 ) ms
(2) = T( n + 1 ) ms
m : Value of base timer x L width setting reload register (BTxPRLL)
n : Value of base timer x H width setting reload register (BTxPRLH)
T : Count clock cycle
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Note:
The output method and output destination of the output signal (TOUT) from the 16-bit PPG timer depend on the
following settings:
Base timer I/O mode
TIOA0, TIOA1 pin functions
If the count timing of the 16-bit down counter and the load timing occur at the same time, the load operation is
given precedence.
Write Timing
The values of the base timer x L width setting reload register (BTxPRLL) and base timer x H width setting reload
register (BTxPRLH) are reloaded at the following timing:
The value set in the base timer x L width setting reload register (BTxPRLL)
It is loaded to the 16-bit down counter in one of the following events:
An activation trigger is detected.
An underflow occurs after counting down from the value of the base timer x H width setting reload register
(BTxPRLH) is completed.
The value set in the base timer x H width setting reload register (BTxPRLH)
It is transferred to the buffer in one of the following events:
An activation trigger is detected.
An underflow occurs after counting down from the value of the base timer x H width setting reload register
(BTxPRLH) is completed.
The content of the buffer is loaded to the 16-bit down counter in the following event:
Counting down from the value of the base timer x L width setting reload register (BTxPRLL) is completed.
Therefore, rewrite the base timer x L width setting reload register (BTxPRLL) and base timer x H width setting reload
register (BTxPRLH) during the period from the time an underflow occurs (the UDIR bit of the status control register
(BTxSTC) changes to "1") to the time counting based on the next cycle begins. The new data will be effective as the
next cycle.
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Figure 5-19 Write Timing
Rising edge detection
Activationtrigger
t rigger
interrupt
Trigger inter rupt
request
Underflow
Underfl ow
interrupt
inter ruptrequest
request
The
cycle
areare
setset
to the
register
The"L"
"L"width
widthand
and"H"
"H"width
widthofofthe
thenext
n ext
cycle
to the
register
BTxPRLL
L0
L1
L2
L3
BTxPRLH
H0
H1
H2
H3
Buffer for
BTxPRLH
xxxx
H0
BTxTMR
xxxx
L0 ~ 0000
H0 ~
0000
L1 ~ 0000
H1 ~
0000
L2 ~ 0000
H2 ~
0000
L0
H0
L1
H1
L2
H2
PPG output
waveform
H1
H2
BTxPRLL : Base timer x L width setting reload (BTxPRLL)
BTxPRLH : Base timer x H width setting reload (BTxPRLH)
BTxTMR : Base timer x timer register (BTxTMR)
Interrupt Generation Timing
The 16-bit PPG timer can generate an interrupt request in one of the following events:
An activation trigger is detected.
An underflow occurs based on the value of H width setting reload register (BTxPRLH).
An example of interrupt request generation timing using the following settings is shown below.
Value of L width setting reload register (BTxPRLL) = 0001H
Value of H width setting reload register (BTxPRLH) = 0001H
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Chapter 20: Base Timer
Figure 5-20 Interrupt Request Generation Timing Chart
Activation trigger
2T to 3T (external trigger)
Load
Count clock
Counter value
XXXXH
0001H
0000H
0001H
0000H
0001H
0000H
PPG output waveform
Interrupt request
Activation edge
trigger interrupt
request (TGIR bit)
5.6.4.
Underflow interrupt
request (UDIR bit)
Operation in One-Shot Mode
This section explains the operation in one-shot mode.
This section explains the operation in one-shot mode.
Counting Operation
Activation
It is the same operation as in reload mode. See "Operation" in "5.6.3 Operation in Reload Mode".
Counting Operation
Counting operation initiated by the entry of an activation trigger is explained below, using an example where the
OSEL bit of the timer control register (BTxTMCR) is set for normal polarity (OSEL = 0).
1.
The value set in the base timer x L width setting reload register (BTxPRLL) is transferred to the 16-bit down
counter and the value set in the base timer x H width setting reload register (BTxPRLH) is transferred to the
buffer. The 16-bit down counter begins to count down from the value of the L width setting reload register
(BTxPRLL). The output signal (TOUT) is at the "L" level.
2. The 16-bit down counter completes counting down from the value of L width setting reload register
(BTxPRLL).
3. The buffered value of H width setting reload register (BTxPRLH) is reloaded to the 16-bit down counter,
which continues counting down. The output signal (TOUT) is at the "H" level.
4. The 16-bit down counter completes counting down from the value of H width setting reload register
(BTxPRLH), thus causing an underflow.
5. The counting stops.
Operation that is performed if reactivation is permitted or not during counting depends on whether reactivation is
permitted based on the RTGEN bit of the timer control register (BTxTMCR).
If reactivation is not permitted (RTGEN = 0): Any activation trigger is ignored when it is entered during counting.
If reactivation is permitted (RTGEN =1): The TGIR bit of the status control register (BTxSTC) changes to "1". In
addition, the value of L width setting reload register (BTxPRLL) is reloaded to the 16-bit down counter, which
starts counting.
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Chapter 20: Base Timer
Figure 5-21 Example of Counting Operation If Reactivation Is Not Enabled
Rising edge detection
Acti vation trigger
t r iggerisisignored
ignored
Activation
Trigger
m
n
0
PPG output
waveform
Interrupt request
(1)
Trigger interrupt
request (TGIR bit)
(2)
Underflow interrupt
request (UDIR bit)
(1) = T(m+1) ms
(2) = T(n+1) ms
m : Value of base timer x L width setting reload register (BTxPRLL)
n : Value of base timer x H width setting reload register (BTxPRLH)
0T : Count clock cycle
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Chapter 20: Base Timer
Figure 5-22 Example of Counting Operation If Reactivation Is Enabled
Rising edge detection
Reactivate with activation trigger
Trigger
m
n
0
(2)
PPG output
waveform
(1)
Interrupt request
Trigger interrupt
request (TGIR bit)
Trigger interrupt
request (TGIR bit)
Underflow interrupt request
(UDIR bit)
(1) = T(m+1) ms
(2) = T(n+1) ms
m : Value of base timer x L width setting reload register (BTxPRLL)
n : Value of base timer x H width setting reload register (BTxPRLH)
0 : Count clock cycle
T
Notes:
The output method and output destination of the output signal (TOUT) from the 16-bit PPG timer depend on
the following settings:
Base timer I/O mode
TIOA0, TIOA1 pin functions
If a 16-bit PPG timer activation trigger is detected when counting ends, the value (cycle) of L width setting
reload register (BTxPRLL) is loaded to the 16-bit down counter, which starts counting.
Interrupt Generation Timing
It is the same operation as in reload mode. See "Interrupt Generation Timing" in "5.6.3 Operation in Reload Mode".
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Chapter 20: Base Timer
5.6.5.
Interrupts
This section explains interrupts of the 16-bit PPG timer operation.
An interrupt request is generated in one of the following events:
An activation trigger is detected. (trigger interrupt request)
An underflow occurs based on the value of H width setting reload register (BTxPRLH). (underflow interrupt
request)
Table 5-5 Interrupt Occurrence Conditions
Interrupt request
Interrupt request flag
Permission of
interrupt request
Interrupt request clear
BTxSTC:TGIR = 1
BTxSTC:TGIE = 1
Set the TGIR bit of
BTxSTC to "0".
Underflow interrupt request BTxSTC:UDIR = 1
BTxSTC:UDIE = 1
Set the UDIR bit of
BTxSTC to "0".
Trigger interrupt request
Notes:
Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request
will be issued when the interrupt is enabled.
To enable the generation of an interrupt request, perform one of the following operations:
Clear the current interrupt request before enabling the generation of an interrupt request.
Clear the current interrupt request when enabling the interrupt.
Either clear the current interrupt request after disabling the generation of an interrupt request or clear the current
interrupt request within the interrupt processing routine.
Set an interrupt level corresponding to the interrupt vector number, using interrupt control registers (ICR00 to
ICR47). For information on interrupt level setting, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
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Chapter 20: Base Timer
5.6.6.
Application Notes
This section explains notes when using the 16-bit PPG timer.
Note the following when using the 16-bit PPG timer:
Notes on Program Setting
Change the following bits of the timer control register (BTxTMCR) only after stopping the 16-bit down counter by
resetting the CTEN bit to "0"(CTEN=0).
CKS2 to CKS0 bits
EGS1 and EGS0 bits
FMD2 to FMD0 bits
MDSE bit
All registers are initialized if the FMD2 to FMD0 bits of timer control register (BTxTMCR) are set to "000" to
select reset mode.
Before the base timer function can be changed, the base timer must be reset once. Except when rewriting the
FMD2 to FMD0 bits of timer control register (BTxTMCR) after reset, be sure to clear FMD2 to FMD0 bits to
"000" to select the reset mode, and then select a base timer function using the FMD2 to FMD0 bits again.
Set the 16-bit PPG timer in the following steps.
1. Set the 16-bit PPG timer as the base timer function by setting the FMD2 to FMD0 bits of timer control register
(BTxTMCR) to "010"(FMD2 to FMD0=010).
2. Set the L width setting reload register (BTxPRLL).
3. Set the H width setting reload register (BTxPRLH).
Notes on Operations
The value loading precedes if the count timing of the 16-bit down counter and the load timing occur at the same
time.
If a 16-bit PPG timer reactivation trigger is detected when counting ends in the one-shot mode, the value (cycle) of
L width setting reload register (BTxPRLL) is loaded to the 16-bit down counter, which starts counting.
A different signal (external clock, external activation trigger, waveform) I/O operation can be selected using the
base timer I/O selection function.
Note on Interrupts
If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur
at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1".
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Chapter 20: Base Timer
5.7.
16/32-bit PWC Timer Operation
This section explains the 16/32-bit PWC timer operation.
This section explains the operation performed when the base timer included in this series is used as the 16/32-bit
PWC timer. Examples of procedures for setting various operating conditions are also provided.
Figure 5-23 Block Diagram (16-bit PWC Timer Operation)
BTxDTBF
16-bit mode
T32=0
CKS
3
Peripheral
clock
(PCLK)
16
20
Division
circuit
Clear
Count
clock
27
28
Up counter
Count
enable
Overflow
MDSE
MDSE
T32
EGS
3
OVIE
Count
enable
Overflow
interrupt request
IRQ 0
CTEN
Waveform to
be measured
(TIN signal)
Interrupt
factor
generation
Edge
detection
CTEN
Edge
detection
IRQ0
Measurement
completion
interrupt request
Activation
detection
IRQ 1
IRQ1
EDIE
Stop detection
BTxDTBF : Base timer x data buffer register (BTxDTBF)
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Chapter 20: Base Timer
Figure 5-24 Block Diagram (32-bit PWC Timer Operation)
ch.1
BT1DTBF
16
Clear
Count
clock
Up counter
Count
enable
Overflow
32-bit mode
T32=0
T32=1
BT0DTBF
ch.0
CKS
3
Peripheral
clock
(PCLK)
16
20
Division
circuit
Clear
Count
clock
27
28
Up counter
Count
enable
Overflow
MDSE
MDSE
T32
EGS
3
OVIE
Count
enable
Overflow
interrupt request
IRQ0
CTEN
Waveform to
be measured
(TIN signal)
Interrupt
factor
generation
Edge
detection
CTEN
Edge
detection
Measurement
completion
interrupt request
Activation
detection
IRQ1
EDIE
Stop detection
BT0DTBF : Base timer 0 x data buffer register(BT0DTBF)
BT1DTBF : Base timer 1 x data buffer register(BT1DTBF)
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Chapter 20: Base Timer
5.7.1.
Overview
This section explains the overview of the 16/32-bit PWC timer operation.
The 16/32-bit PWC timer is used to measure the pulse width and cycle of input signals. When a measurement start
edge is detected in an input signal (TIN), the counting up starts. This counting stops when a measurement end edge is
detected. The counted value (that is, the measured result) is stored as the pulse width or cycles in the data buffer
register (BTxDTBF).
The 16/32-bit PWC timer supports three modes: the timer mode, the operation mode, and measurement mode. The
operation of the timer varies in accordance with a combination of these modes.
Note:
The input method of the TIN signal varies depending on the I/O mode that has been set by the I/O selection register
(BTSEL01). See "5.2 I/O Allocation".
Timer Mode
Either of the following timer modes can be selected using the T32 bit of the timer control register (BTxTMCR).
16-bit timer mode (T32 = 0): A 16-bit PWC timer can operate individually for each of the channels.
32-bit timer mode (T32 = 1): Two channels can be cascaded and used as a 32-bit PWC timer.
See "5.7.3 32-bit Timer Mode Operation" for details on the operation in 32-bit timer mode.
Note:
The T32 bit setting differs between odd-number and even-number channels when the 32-bit timer mode is selected.
For details, see "5.7.3 32-bit Timer Mode Operation".
Operation Mode
Either of the following two modes can be selected using the MDSE bit of the timer control register (BTxTMCR).
Continuous measurement mode (MDSE = 0): In this mode, after one sequence of measurement is conducted, the
input of the next measurement start edge is awaited and the detection of the next measurement start edge triggers
another sequence of measurement.
Single measurement mode (MDSE = 1): In this mode, measurement is conducted only once. Differences between
the single and continuous measurement modes are listed on the table below.
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Table 5-6 Differences between Single and Continuous Measurement Modes
Single measurement mode
Continuous measurement mode
Measurement
When a measurement end edge is
detected, the measurement stops and the
Measurement stops when a measurement
next measurement start edge is waited.
end edge is detected.
When the next measurement start edge
is detected, the measurement restarts.
BTxDTBF function
During measurement: The measured
value is held.
After measurement: The measurement
result is held.
During measurement: The previous
measurement result is held.
After measurement: The measurement
result is held.
During overflow
The measurement stops.
The measurement restarts from 0x0000
Figure 5-25 shows the standard operation flow.
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Chapter 20: Base Timer
Figure 5-25 Operation Flow
BTxTMCR: Base timer x timer control register (BTxTMCR)
BTxSTC: Base timer x status control register (BTxSTC)
BTxDTBF: Base timer x data buffer register (BTxDTBF)
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Note:
In the continuous measurement mode, if the next measurement is completed before the measurement result has been
read from the data buffer register (BTxDTBF), the value being held by the data buffer register (BTxDTBF) is
overwritten by the new value. The old value is discarded. If it has occurred, the ERR bit of the status control register
(BTxSTC) changes to "1". This ERR bit is cleared to "0" when a value is read from the base timer x data buffer
register (BTxDTBF).
Measurement Mode
Either of the following five modes can be selected using EGS2 to EGS0 bits of the timer control register
(BTxTMCR).
Figure 5-26 Measurement Modes and their Explanation 1
Measurement mode
(EGS2 to EGS0)
Measurement description
The width of the period which the "H" level signal is being input is measured.
.
Measurement of H pulse
width
(EGS2 to EGS0=000)
Width
Width
Count stop
Count start
Start
Stop
Count (measurement) start: at rising edge detection
Count (measurement) stop: at falling edge detection
The cycle from the rising edge detection to the next rising edge detection is measured.
Measurement of the cycle
between rising edges
(EGS2 to EGS0=001)
Period
Period
Count stop
start
Count start
Period
Count stop
start
Count (measurement) start: at rising edge detection
Count (measurement) stop: at rising edge detection
The cycle from the falling edge detection to the next falling edge detection is measured.
Measurement of the cycle
between falling edges
(EGS2 to EGS0=010)
Period
Count start
Period
Count stop
start
Period
Count stop
start
Count (measurement) start: at falling edge detection
Count (measurement) stop: at falling edge detection
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Figure 5-27 Measurement Modes and their Explanation 2
Measurement mode
(EGS2 to EGS0)
Measurement description
The width between the edges input continuously is measured.
•From rising edge detection to falling edge detection
•From falling edge detection to rising edge detection Count
Measurement of the pulse
width between all edges
(EGS2 to EGS0=011)
Width
Count start
Width
Width
Count stop
Count start
Count (measurement) start: at edge detection
Count (measurement) stop: at edge detection
The width of the period during which the "L" level signal being input is measured.
Measurement of L pulse
width
(EGS2 to EGS0=100)
Width
Count start
Width
Count stop
Count start
Count stop
.
Count (measurement) start: at falling edge detection
Count (measurement) stop: at rising edge detection
5.7.2.
Operation during PWC Measurement
This section explains the operation during PWC measurement.
This section explains the operations during measurement. For explanation of "sensitive edges" (1) and (2) described
below, see "Figure 5-26 Measurement Modes and their Explanation 1" and "Figure 5-27 Measurement Modes and
their Explanation 2".
Activation
Activate the 16/32-bit PWC timer with the following procedure:
Enable the 16/32-bit PWC timer operation by setting the CTEN bit of the timer control register (BTxTMCR) to
"1"(CTEN=1). The counter value is cleared to "0000H" and the 16/32-bit PWC timer waits for an input of
measurement start edge. (No counting occurs until an input of measurement start edge.)
Counting Operation
Operation in single measurement mode
If sensitive edge (1) is detected in the input signal (TIN) when a measurement start edge is waited, the up counter
starts counting up from "0001H" in synchronous with the count clock. If sensitive edge (2) is detected in the input
signal (TIN), the up counter stops from operating. During this time, the up counter value is stored in the data buffer
register (BTxDTBF). An interrupt request can be generated at the end of measurement or at an occurrence of
overflow.
Notes:
In the single measurement mode, the counting stops if an overflow occurs.
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The input method of waveforms to be measured (TIN signal) varies depending on the I/O mode that has been set
by the I/O selection register (BTSEL01).
Operation in continuous measurement mode
If sensitive edge (1) is detected in the input signal (TIN) when a measurement start edge is waited, the up counter
starts counting up from "0001H" in synchronous with the count clock. If sensitive edge (2) is detected in the input
signal (TIN), the up counter stops from operating and waits for an input of measurement start edge. During this time,
the up counter value is stored in the data buffer register (BTxDTBF). If a rising edge of the input signal (TIN) is
detected when a measurement start edge is waited, the up counter starts counting up from "0001 H" again. An interrupt
request can be generated at the end of measurement or at an occurrence of overflow.
Note:
The input method of waveforms to be measured (TIN signal) varies depending on the I/O mode that has been set by
the I/O selection register (BTSEL01).
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Figure 5-28 Operation Example
Operation of "L" pulse width measurement in single measurement mode
PWC input measured pulse
CTEN bit
Count value
FFFFH
0001H
0000H
Counting
stopped
Counter
cleared
Start
triggered
(Solid line indicates count values.)
Counting 0001H
stared
Time
EDIR bit=1
(Measurement completed)
Operation of "L" pulse width measurement in continuous measurement mode
PWC input measured pulse
CTEN bit
(Solid line indicates count values.)
Data transfer to BTxDTBF
Overflow
Count value
FFFFH
Data transfer to BTxDTBF
0001H
0000H
Start
triggered
Counting
stopped
Counting
stopped
Counter
cleared
Counting 0001H
stared
Counting
continued
Counting 0001H
restared
EDIR bit=1
(Measurement completed)
Time
OVIR bit=1 EDIR bit=1
(Overflow) (Measurement completed)
BTxDTBF: Base timer x data buffer register (BTxDTBF)
Reactivation
If the CTEN bit of the base timer x timer control register (BTxTMCR) is set to "1" during counting, the up counter
reactivates and operates as follows.
If the counter is reactivated when a measurement start edge is waited:
The current status waiting for a measurement start edge is continued.
If the timer is reactivated during measurement:
The up counter value is cleared to "0000H" and set to the measurement start edge waiting status.
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Notes:
If a detection of measurement end edge and a timer reactivation occur simultaneously, the following may result. In
such case, set the interrupt control correctly by considering the operation of interrupt request flag.
Single measurement mode: The timer reactivates and waits for a measurement start edge. Also, the EDIR bit
(the measurement end interrupt request flag) of the status control register (BTxSTC) is set to "1".
Continuous measurement mode: The timer reactivates and waits for a measurement start edge. Also, the EDIR
bit (the measurement end interrupt request flag) of the status control register (BTxSTC) is set to "1". Also, the
current measurement result is transferred to the data buffer register (BTxDTBF).
If the 16/32-bit PWC timer is reactivated in the continuous measurement mode and if a measurement start edge is
detected in the input signal (TIN) simultaneously, the timer immediately starts counting from the value "0001H".
Calculating the Pulse Width
After the measurement, the measurement result can be read from the base timer x data buffer register (BTxDTBF) and
the measured pulse width can be calculated using the following formula.
Pulse width = n × T
n: Data buffer register (BTxDTBF) value
T: Count clock cycle
5.7.3.
32-bit Timer Mode Operation
This section explains the 32-bit timer mode operation.
This section explains the setting and operation for cascading 2 channels of a 16-bit PWC timer and using them as a
32-bit PWC timer.
Overview
Using the T32 bit of the timer control register (BTxTMCR), 2 channels of a 16-bit PWC timer can be cascaded and
used as a 32-bit PWC timer.
In this mode, the even-number channel corresponds to the lower 16-bit operation, and the odd-number channel
corresponds to the upper 16-bit operation. Therefore, the up counter must be read in the order of the lower 16 bits
(even-number channel) → the upper 16 bits (odd-number channel).
Setting Procedure (Example)
To select the 32-bit timer mode, set the T32 bit of the base timer x timer control register (BTxTMCR) of the
even-number channel to "1". Also, set the T32 bit of the odd-number channel to "0". When setting 32-bit timer mode,
set the registers using the procedure shown below.
The register setting differs between even-number and odd-number channels. In this example, channel 0 and channel 1
are connected by cascading.
1.
2.
672
Specify ch.0 to reset mode by setting FMD2 to FMD0 bits of the base timer 0 timer control register
(BT0TMCR). (FMD2 to FMD0 = 000)
Set FMD2 to FMD0 of the timer control registers (BT0TMCR, BT1TMCR) of both base timer ch.0 and ch.1
to "100" (16/32 bit PWC timer) and, at the same time, set the T32 bits of the timer control registers
(BT0TMCR, BI1TMCR) to "1" and "0", respectively, to set 32-bit timer mode. (FMD2 to FMD0 = 100) At the
same time, select the 32-bit timer mode by setting the T32 bit of the base timer 0 timer control register
(BT0TMCR). (T32 = 1)
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Chapter 20: Base Timer
Note:
Rewrite the T32 bit while the operation of both of the even-number and odd-number channels are stopped. Whether
the counting operation is stopped can be checked by setting the CTEN bit of the timer control register (BTxTMCR) to
"0"(CTEN=0).
Operations
In the 32-bit timer mode, the counting operation is basically the same as in the 16-bit timer mode. However, the
counting operation conforms to the settings of the even-number channels, ignoring the settings of the following
registers for the odd-number channels.
Base timer x timer control register (BTxTMCR)
Base timer x status control register (BTxSTC)
This section explains the counting in the 32-bit timer mode.
1.
2.
3.
4.
If the 16/32-bit PWC timer operation is enabled using the CTEN bit of the timer control register (BTxTMCR)
(by setting CTEN = 1) of the even-number channel, the 32-bit PWC timer starts.
When a measurement start edge is detected in the input signal (TIN), the counting starts.
The up counter starts counting as a 32-bit counter with the even-number channel serving as the lower 16 bits
and the odd-number channel as the upper 16 bits.
When a measurement end edge is detected in the input signal (TIN signal), the lower 16-bit data of the up
counter value is stored in the data buffer register (BTxDTBF) of the even-number channel, and the upper
16-bit data of the up counter value is stored in the data buffer register (DTxDTBF) of the odd-number channel.
The channel configuration in 32-bit timer mode is shown below.
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Chapter 20: Base Timer
Figure 5-29 Configuration in 32-bit Timer Mode
ch.1
Overflow
ch.0
Interrupt
Upper 16-bit
up counter
Upper 16-bit
counter value
T32=0
Overlow
Overflow
Lower 16-bit
up counter
Read/write signal
Lower 16-bit
counter value
T32=1
PWC Measurement Waveform
Notes:
The down counter value can be checked by reading the data buffer register (BTxDTBF). In the 32-bit timer mode,
it must be read in the order of the lower 16 bits (even-number channel) → upper 16 bits (odd-number channel).
In 32-bit timer mode, the operation of the 32-bit PWC timer conforms to the settings of the even-number channel.
Therefore, an interrupt request of the even-number channel is effective.
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Chapter 20: Base Timer
5.7.4.
Interrupt
This section explains interrupt of the base timer.
An interrupt request is generated in one of the following events:
An overflow occurs. (Overflow interrupt request)
The measurement ends. (Measurement end interrupt request)
Table 5-7 Interrupt Occurrence Conditions
Interrupt request
Interrupt request flag
Permission of
interrupt request
Interrupt request clear
Overflow interrupt request
BTxSTC:OVIR=1
BTxSTC:OVIE=1
Set the OVIR bit of
BTxSTC to "0".
Measurement end
interrupt request
BTxSTC:EDIR=1
BTxSTC:EDIE=1
Read BTxDTBF
Notes:
Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request
will be issued when the interrupt is enabled.
To enable the generation of an interrupt request, perform one of the following operations:
Clear the current interrupt request before enabling the generation of an interrupt request.
Clear the current interrupt request when enabling the interrupt.
Either clear the current interrupt request after disabling the generation of an interrupt request or clear the current
interrupt request within the interrupt processing routine.
For interrupt vector numbers used for issuing an interrupt request, see "List of Interrupts Vector" in entitled
"APPENDIX".
Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00
to ICR47). For information on interrupt level setting, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
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Chapter 20: Base Timer
5.7.5.
Application Notes
This section explains application notes of the base timer.
Note the following when using the 16/32-bit PWC timer:
Notes on Program Setting
Change the following bits of the base timer x timer control register (BTxTMCR) after stopping the up counter by
resetting the CTEN bit to "0"(CTEN=0).
CKS2 to CKS0 bits
EGS2 to EGS0 bits
T32 bit
FMD2 to FMD0 bits
MDSE bit
All registers are initialized when the FMD2 to FMD0 bits of the timer control register (BTxTMCR) are set to
"000" to select reset mode.
Before the base timer function or T32 bit can be changed, the base timer must be reset once. Except when
rewriting the status of FMD2 to FMD0 bits or T32 bit of the timer control register (BTxTMCR) after a reset, be
sure to reset the FMD2 to FMD0 bits to "000" to select the reset mode. Then, rewrite the status of these bits.
The timer may operate due to the status of previously measured signals if the followings are set simultaneously
during system reset or during reset mode.
The base timer function is set for the 16/32-bit PWC timer by setting the FMD2 to FMD0 bits of the base timer
x timer control register (BTxTMCR) to "100"(FMD2 to FMD0=100).
Enable 16/32-bit PWC timer operation by setting the CTEN bit of the base timer x timer control register
(BTxTMCR) to "1"(CTEN=1).
Notes on Operations
The value loading precedes if the count timing of the up counter and the load timing occur at the same time.
If the 16/32-bit PWC timer operation is enabled by setting the CTEN bit of the base timer x timer control register
(BTxTMCR) to "1"(CTEN=1), the up counter value is cleared. Also, the up counter value is made invalid if it has
been set before the operation is enabled.
If the 16/32-bit PWC timer is reactivated in the continuous measurement mode and if a measurement start edge is
detected in the input signal (TIN) simultaneously, the timer immediately starts counting from the value "0001H".
If two channels of PWC timers are used as a single 32-bit PWC timer, the 16-bit PWC timer setting of the
even-number channel is made valid. The timer setting of odd-number channel is ignored.
The input operation of measurement waveforms varies depending on the base timer I/O selection function.
Notes on Interrupts
If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1"
occur at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1".
If a detection of measurement end edge and a reactivation of 16/32-bit PWC timer occur simultaneously, the
following may result. In such case, set the interrupt control correctly by considering the operation of the interrupt
request flag.
Pulse width single measurement mode: The timer reactivates and waits for a measurement start edge. Also, the
measurement end interrupt request flag (EDIR) is set to "1".
Pulse width continuous measurement mode: The timer reactivates and waits for a measurement start edge. The
measurement end interrupt request flag (EDIR) is set to "1", and the currently measured result is transferred to
the data buffer register (BTxDTBF).
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Chapter 21: Reload Timer
This chapter explains the reload timer.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Application Note
Code : FR81S10_RLT-1v1-91528-3-E
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Chapter 21: Reload Timer
1. Overview
This section explains the overview of the reload timer.
This module is a 16-bit reload down count timer with the interval timer mode, which counts the internal clock, and
the event counter mode, which counts external events.
Figure 1-1 Block Diagram of Reload Timer (1 Channel, Overview)
Cascading to next
reload timer
Peripheral clock
(PCLK)
TIN external
pin pin
TTRG
external
Prescaler
Counter
&
Control unit
Cascading from previous
reload timer
TOUT external pin
Interrupt
The numbers of available channels are shown below.
MB91F52xR (144pin) : 8
MB91F52xU (176pin) : 8
MB91F52xM (208pin) : 8
MB91F52xY (416pin) : 8
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Chapter 21: Reload Timer
2. Features
This section explains features of the reload timer.
An 8-channel reload timer is installed in this series.
Each channel is configured as follows.
16-bit down counter
16-bit reload register
16-bit reload / compare/ capture register
Buffers described above
6-bit prescaler for internal count clock creation
External trigger/event input (TIN)
External toggle output (TOUT)
Control register
Count comparator
×1
×1
×1
×1
×1
×1
×1
×1
×1
This timer, equipped with the interval timer mode/event counter mode described below, can be used for the following
purposes and functions by setting the registers:
Interval timer mode
Single one-shot operation
=> Single-shot Timer
Dual one-shot operation
Single reload operation
=> Reload Timer
Dual reload operation
=> PPG(Programmable Pulse Generator)
Compare mode
=> Output compare, PWM(Pulse Width Modulator)
Capture mode (external trigger input/software trigger use)
=> PWC(Pulse Width Counter)
Underflow interrupt/capture interrupt
6 types of internal clocks (peripheral clock (PCLK) divided by 2/4/8/16/32/64)
External trigger input (rising edge/falling edge/both edges)
External gate input
Event counter mode
Single one-shot operation
Dual one-shot operation
Single reload operation
Dual reload operation
Compare mode
Capture mode (only software trigger)
Underflow interrupt/capture interrupt/compare interrupt
External event input edge detection (rising edge detection/falling edge detection/both edge detection)
Cascade mode
Use ch.0 output for ch.1 input. Use ch.1 output for ch.2 input. Use ch.2 output for ch.3 input.
Use ch.4 output for ch.5 input. Use ch.5 output for ch.6 input. Use ch.6 output for ch.7 input.
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Chapter 21: Reload Timer
3. Configuration
This section explains the configuration of the reload timer.
Figure 3-1 Block Diagram of Reload Timer (1 Channel, Details)
Read/Write
Read/Write
Reload selector
Peripheral bus
Mode control
TMRLRA
Buffer
TMRLRB
MOD1
Reload
RELD
Capture mode
Read/Write
MOD0
INTE
Read only
TMR
Underflow
INT
UF
Compare mode
Count
comparator
Compare
result
EF
Unused
End One-shot
Capture
OUTL
Peripheral
clock
Count control
Enable a count
Trigger
Trigger
Output
FF
TOUT
CNTE
TRG
Gate
CSL2
CSL1
Clock selector
Select
GATE
Prescaler
Edge
control
Peripheral
clock
TTRG
TIN
Peripheral
clock
Input
+
Synchronization
FF
CSL0
Gate
control
TRGM1
Select
TRGM0
TMCSR
bit in any sequence
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Chapter 21: Reload Timer
4. Registers
This section explains registers of the reload timer.
Table of Base Address (Base_addr), External Pins
Table 4-1 Table of Base Address (Base_addr), External Pins
External pin (TOUT output, TIN input)
Channel
0
1
2
3
4
5
6
Base_addr
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
TOT0_0/
TOT0_1
TOT0_0/
TOT0_1
TIN0_0/
TIN0_1/
TOT0_0/
TOT0_1
TIN0_0/
TIN0_2
TIN0_0/
TIN0_1/
TIN0_2
TIN0_0/
TIN0_1/
TIN0_2
TIN0_0/
TIN0_1/
TIN0_2
TOT1_0/
TOT1_2
TOT1_0/
TOT1_1/
TOT1_2
TOT1_0/
TOT1_1/
TOT1_2
TOT1_0/
TOT1_1/
TOT1_2
TIN1_0
TIN1_0/
TIN1_1
TIN1_0/
TIN1_1
TIN1_0/
TIN1_1
TOT2_0/
TOT2_1
TOT2_0/
TOT2_1
TOT2_0/
TOT2_1
TOT2_0/
TOT2_1
TIN2_0/
TIN2_1
TIN2_0/
TIN2_1
TIN2_0/
TIN2_1
TIN2_0/
TIN2_1
TOT3_0/
TOT3_1
TOT3_0/
TOT3_1
TOT3_0/
TOT3_1
TOT3_0/
TOT3_1
TIN3_0/
TIN3_1/
TIN3_2
TIN3_0/
TIN3_1/
TIN3_2
TIN3_0/
TIN3_1/
TIN3_2
TIN3_0/
TIN3_1/
TIN3_2
TOT4_0
TOT4_0
TOT4_0
TOT4_0
TIN4_0/
TIN4_1
TIN4_0/
TIN4_1
TIN4_0/
TIN4_1
TIN4_0/
TIN4_1
TOT5_0/
TOT5_1
TOT5_0/
TOT5_1
TOT5_0/
TOT5_1
TOT5_0/
TOT5_1
TIN5_0/
TIN5_1
TIN5_0/
TIN5_1
TIN5_0/
TIN5_1
TIN5_0/
TIN5_1
TOT6_0/
TOT6_1
TOT6_0/
TOT6_1
TOT6_0/
TOT6_1
TOT6_0/
TOT6_1
TIN6_0/
TIN6_1
TIN6_0/
TIN6_1
TIN6_0/
TIN6_1
TIN6_0/
TIN6_1
0x0060
0x0100
0x0108
0x0110
0x01D8
0x01F0
0x01F8
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Chapter 21: Reload Timer
External pin (TOUT output, TIN input)
Channel
7
Base_addr
0x0068
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
TOT7_0/
TOT7_1
TOT7_0/
TOT7_1
TOT7_0/
TOT7_1
TOT7_0/
TOT7_1
TIN7_0
TIN7_0
TIN7_0
TIN7_0
Registers Map
Table 4-2 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
0x01D8
TMRLRA4
TMR4
16-bit timer reload register A4
16-bit timer register 4
0x01DC
TMRLRB4
TMCSR4
16-bit timer reload register B4
Control status register 4
0x01F0
TMRLRA5
TMR5
16-bit timer reload register A5
16-bit timer register 5
0x01F4
TMRLRB5
TMCSR5
16-bit timer reload register B5
Control status register 5
0x01F8
TMRLRA6
TMR6
16-bit timer reload register A6
16-bit timer register 6
0x01FC
TMRLRB6
TMCSR6
16-bit timer reload register B6
Control status register 6
0x0060
TMRLRA0
TMR0
16-bit timer reload register A0
16-bit timer register 0
0x0064
TMRLRB0
TMCSR0
16-bit timer reload register B0
Control status register 0
0x0100
TMRLRA1
TMR1
16-bit timer reload register A1
16-bit timer register 1
0x0104
TMRLRB1
TMCSR1
16-bit timer reload register B1
Control status register 1
0x0108
TMRLRA2
TMR2
16-bit timer reload register A2
16-bit timer register 2
0x010C
TMRLRB2
TMCSR2
16-bit timer reload register B2
Control status register 2
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Chapter 21: Reload Timer
Registers
Address
Register function
+0
+1
+2
+3
0x0110
TMRLRA3
TMR3
16-bit timer reload register A3
16-bit timer register 3
0x0114
TMRLRB3
TMCSR3
16-bit timer reload register B3
Control status register 3
0x0068
TMRLRA7
TMR7
16-bit timer reload register A7
16-bit timer register 7
0x006C
TMRLRB7
TMCSR7
16-bit timer reload register B7
Control status register 7
4.1.
Control Status Register : TMCSR (TiMer Control and
Status Register)
The bit configuration of the control status register is shown below.
These registers control the operating mode and interrupt.
It is not possible to rewrite any data other than bit7 and bit3 to bit0 when bit1:CNTE= "1".
It is possible to rewrite bit15 to bit8 and bit6 to bit4 and write counter operation enabling by writing CNTE= "1"
simultaneously. It is also possible to rewrite bit15 to bit8, bit6 to bit4 and write operation disabling by writing CNTE=
"0" simultaneously.
TMCSR : Address Base_addr + 06H (Access : Byte, Half-word, Word)
bit15
bit14
MOD[1:0]
Initial value
Attribute
Initial value
bit13
bit12
bit11
TRGM[1:0]
bit10
bit9
CSL[2:0]
bit8
GATE
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EF
Reserved
OUTL
RELD
INTE
UF
CNTE
TRG
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R/W
R(RM1),W
R/W
R0,W
Attribute R(RM1),W
[bit15, bit14] MOD [1:0] (MODe) : Mode selection bits
MOD[1:0]
00
Operation mode
Single mode (initial value)
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MOD[1:0]
Operation mode
01
Dual mode
10
Compare mode
11
Capture mode
[bit13, bit12] TRGM[1:0] (TRiGger input Mode select) : TIN Input mode selection bits
These bits control input pin functions. The functions of the interval timer mode differ from those of the event counter
mode.
[Interval timer mode, trigger input (bit8:GATE = "0")]
Select an effective external edge which can be a reload trigger through TIN input in the following manner:
TRGM[1:0]
TIN effective external edge
00
No external trigger detection (initial value)
01
Rising edge
10
Falling edge
11
Both edges
[Interval timer mode, gate input (bit8:GATE = "1")]
Select the pin level which enables the counter during TIN input in the following manner:
TRGM[1:0]
TIN effective level
x0
Counted only during the input period for TIN pin "L" (initial value)
x1
Counted only during the input period for TIN pin "H"
[Effective edge setting at the event counter mode]
In the event counter mode, select an edge for external event detection in the following manner:
Every time an external event is detected, the counter value is decreased. When an external event is selected, the
setting of the bit8:GATE bit becomes invalid.
TRGM[1:0]
Count target edge
00
Reserved
01
Rising edge
10
Falling edge
11
Both edges
[bit11 to bit9] CSL[2:0] (Count source SeLect) : Count source selection bits
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Chapter 21: Reload Timer
These bits specify the count source. Select a count source from the internal clock (peripheral clock (PCLK)) and the
external event (TIN input) specified following: When the event counter mode is set, set the count effective edge using
bit13, bit12:TRGM[1:0].
CSL[2:0]
Count source
000
Division of the peripheral clock frequency by 2
(initial value)
001
Division of the peripheral clock frequency by 4
010
Division of the peripheral clock frequency by 8
011
Division of the peripheral clock frequency by 16
100
Division of the peripheral clock frequency by 32
101
Division of the peripheral clock frequency by 64
110
Cascade mode
(ch.0: TIN0, ch.1:TOUT0, ch.2:TOUT1, ch.3:TOUT2,
ch.4: TIN4, ch.5:TOUT4, ch.6:TOUT5, ch.7:TOUT6)
111
Operation mode
Interval timer mode
Event counter mode
External event (TIN input)
[bit8] GATE (GATE input enable) : Gate input enabling bit
This bit controls the functions of the input pin (TIN) of (bit11 to bit9:CSL[2:0]=000 to 101) at the interval timer
mode specified following.
GATE
TIN input pin functions
0
Use as trigger input (initial value)
1
Use as gate input
This bit does not influence any operation at the event counter mode.
[bit7] EF (Extended Flag) : Extended interrupt flag
This flag indicates that a compare match interrupt has occurred at the compare mode or a capture input interrupt has
occurred at the capture mode.
Set factor
Clear factor
[Compare mode of the event counter mode]
Count down occurs from compare match (TMR = TMRLRB)
[Capture mode]
Capture input (retrigger)
Writing "0" to this bit or reset.
Writing "1" to this bit will not be effective. In synchronization with the count clock, set operation or clear operation
are performed in the compare mode. The values read with read-modify-write instructions will always be "1".
[bit6] Reserved
Reserved bit. Data writing is ineffective.
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[bit5] OUTL (OUTput Level) : Output polarity setting bit
This bit controls output polarity of the timer output pin (TOUT).
OUTL
TOUT initial value
TOUT initial output level
0
Positive polarity (Initial value)
L level
1
Negative polarity
H level
[bit4] RELD (RELoaD enable) : Reload operation enabling bit
This bit sets reload operation in case of underflow specified following:
RELD
Operation mode
Description of operation
0
One-shot mode
No sooner does a counter underflow occur, than the count
operation stops. Reload is not performed until the next
trigger is inputted. * (initial value)
1
Reload mode
Counter underflow occurs. At the same time, the contents
of the reload register are loaded to the counter to continue
count operation.
* : However, the dual one-shot function reloads TMRLRB at the same time as TMRLRA underflow and continues
counting. After that, count operation stops at the same time as TMRLRB underflow.
[bit3] INTE (INTerrupt Enable) : Interrupt request enabling bit
This bit controls an interrupt request in case of underflow/compare match (event counter mode)/capture specified
following:
INTE
Description of operation
0
Interrupt disabled (no interrupt is generated even if the UF/EF bit is
set.) (initial value)
1
Interrupt enabled (an interrupt request is generated if the UF/EF bit is
set.)
[bit2] UF (Under flow Flag) : Underflow flag
This flag indicates that underflow has occurred when the counter value is decreased from 0x0000.
Set factor
Counter underflow occurrence
Clear factor
Writing "0" to this bit or reset.
[bit1] CNTE (timer CouNTer Enable) : Timer count enabling bit
This bit controls the operation of the timer as follows:
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Chapter 21: Reload Timer
CNTE
Description of operation
0
Operation disabled (initial value)
1
Operation enabled (waiting for activation trigger)
[bit0] TRG (software TRiGger) : Software trigger bit
This bit generates a timer software trigger. If a software trigger is generated, the contents of the reload register are
loaded to the counter to initiate count operation.
TRG
Description of operation
Write "0"
No influence on the operation
Write "1"
A software trigger is generated.
When "0" is written into this bit, no influence on the operation. The read value is always "0".
Trigger input through this register is effective only when bit1:CNTE = "1".
Writing "1" into the TRG bit always generates an effective trigger if the timer is activated (bit1:CNTE= "1") in any
operation mode.
4.2. 16-bit Timer Register : TMR (16bit TiMer Register)
The bit configuration of the 16-bit timer register is shown below.
This register can read the timer count value.
Always perform 16-bit access to this register.
TMR : Address Base_addr + 02H (Access : Half-word)
bit15
bit14
....
bit2
bit1
bit0
TMR[15:0]
Initial value
Attribute
X
X
....
X
X
X
R,WX
R,WX
....
R,WX
R,WX
R,WX
[bit15 to bit0] TMR (TiMeR) : 16-bit timer
This register can read the counter value of the 16-bit timer. The initial value is undefined.
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4.3.
16-bit Timer Reload Register A, 16-bit Timer Reload
Register B : TMRLRA, TMRLRB(16bit TiMer ReLoad
Register A/B)
The bit configuration of 16-bit timer reload register A and 16-bit timer reload register B is shown below.
TMRLRA sets the count initial value.
TMRLRB applies different functions according to the operation mode.
Always perform 16-bit access to this register.
TMRLRA : Address Base_addr + 00H (Access : Half-word)
bit15
bit14
....
bit2
bit1
bit0
TMRLRA[15:0]
Initial value
Attribute
X
X
....
X
X
X
R/W
R/W
....
R/W
R/W
R/W
bit2
bit1
bit0
TMRLRB : Address Base_addr + 04H (Access : Half-word)
bit15
bit14
....
TMRLRB[15:0]
Initial value
Attribute
X
X
....
X
X
X
R,W
R,W
....
R,W
R,W
R,W
[bit15 to bit0] TMRLRA (TiMer ReLoad Register A) : 16-bit reload setting register A
[bit15 to bit0] TMRLRB (TiMer ReLoad Register B) : 16-bit reload setting register B
The TMRLRA register holds the count initial value. The TMRLRA can be used in all mode regardless of the bit15,
bit14:MOD[1:0] setting in the TMCSR register.
The TMRLRB is to be used based on the bit15, bit14:MOD[1:0] setting in the TMCSR register specified following:
Mode
MOD[1:0]
TMRLRB functions
Single mode
00
Not used
Dual mode
01
H width (when OUTL=0) counter value
Compare mode
10
Compare register (when H width setting is OUTL=0)
Capture mode
11
Capture register (TMR value upon retrigger input)
When using as a counter value, underflow is generated if 1 count is set when writing 0x0000 and 65,536 is set when
writing 0xFFFF.
H width and L width of the timer output waveform (TOUT) are determined by the MOD[1:0] (bit15, bit14 of the
TMCSR register), RELD (bit4 of the TMCSR register), and OUTL (bit5 of the TMCSR register) bit setting as well as
the TMRLRA/B register value.
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H width and L width setting of the waveform(TOUT) to be output is shown in the table below.
TOUT output
MOD[1:0]
Mode
RELD
OUTL
H width
L width
0
TMRLRA+1
-
1
-
TMRLRA+1
0
00
Single
0
1
TMRLRA+1
1
0
TMRLRB+1
TMRLRA+1
1
TMRLRA+1
TMRLRB+1
0
TMRLRB+1
TMRLRA+1
1
TMRLRA+1
TMRLRB+1
0
01
Dual
1
0
0
1
10
Compare
See the explanation below.*
0
1
1
0
TMRLRA+1
-
1
-
TMRLRA+1
0
11
Capture
0
1
TMRLRA+1
1
*: H width and L width are as follows in the compare mode:
When TMRLRB < TMRLRA
(OUTL=0) "L" width of TMRLRA-TMRLRB + 1, "H" width of TMRLRB
(OUTL=1) "H" width of TMRLRA-TMRLRB + 1, "L" width of TMRLRB
When TMRLRB = 0
(OUTL=0) "L" output fixed
(OUTL=1) "H" output fixed
When TMRLRB > TMRLRA
(OUTL=0) "H" output fixed
(OUTL=1) "L" output fixed
When TMRLRB = TMRLRA
(OUTL=0) "L" output of 1 cycle, "H" width of TMRLRB
(OUTL=1) "H" output of 1 cycle, "L" width of TMRLRB
The following formula represents the TOUT output time (TOUT) when the register is used as the single mode and
dual mode in the interval timer mode:
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TOUT = (Setting value of this register + 1) × count source cycle
* : The formula described above is effective only in the interval timer mode.
5. Operation
This section explains the operation of the reload timer.
5.1 Setting
5.2 Operation Procedure
5.3 Operations of Each Counter
5.4 Cascade Input
5.5 Priority of Concurrent Operations
5.1. Setting
Setting of the reload timer is shown below.
The operation of this timer is set based on the "count source" (select in the TMCSR.CSL[2:0]) and counter operation
({TMCSR.MOD[1:0], TMCSR.RELD}).
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5.1.1.
Count Source
The count source of the reload timer is shown below.
Select decrement conditions of the down counter in the TMCSR:CSL[2:0].
Table 5-1 List of Count Source
CSL[2:0]
Count source
000
Division of the peripheral clock frequency by 2 (initial value)
001
Division of the peripheral clock frequency by 4
010
Division of the peripheral clock frequency by 8
011
Division of the peripheral clock frequency by 16
100
Division of the peripheral clock frequency by 32
101
Division of the peripheral clock frequency by 64
110
Cascade mode
(ch.0:TIN0, ch.1:TOUT0, ch.2:TOUT1, ch.3:TOUT2,
ch.4: TIN4, ch.5:TOUT4, ch.6:TOUT5, ch.7:TOUT6)
Operation mode
Interval timer mode
111
5.1.2.
Event counter mode
External event (TIN input)
Timer Underflow cycle
The timer underflow cycle is shown below.
Underflow is defined as counter down-counting from 0x0000. Set the time (cycle) to underflow occurrence since
timer count operation start in the reload register (TMRLRA/TMRLRB). After loading to the reload register,
underflow takes place if the count value reaches "reload register setting value + 1" count. The timer underflow cycle,
TUF, in the interval timer mode can be represented as follows:
TUF = Peripheral clock (PCLK) cycle × prescaler division value (2 to 64) ×
(Reload register value (TMRLRA/B) + 1)
5.1.3.
Trigger
The trigger of the reload timer is shown below.
The trigger consists of the following two types:
Software trigger ... Generated when writing "1" to the TMCSR.TRG
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External pin trigger ... Inputted from the TIN pin.
The TIN pin is used as a count source in the event counter mode. Hence, a software trigger is always used.
In the interval timer mode, settings are made in the TMCSR register.
5.1.4.
Gate
The gate of the reload timer is shown below.
When configuring gate input (TMCSR.GATE = "1") in the interval timer mode, it is possible to stop counter down
counting using the TIN external pin.
Table 5-2 TIN Effective Level
TRGM[0]
5.1.5.
TIN Effective Level
0
Counted only during the input period for TIN pin "L" (initial value)
1
Counted only during the input period for TIN pin "H"
Counter Operation Selection
The counter operation selection is shown below.
Select the operation in case of counter underflow using the mode selection bits (bit15, bit14:MOD[1:0] of the
TMCSR register) and the reload operation enabling bit (bit4:RELD of the TMCSR register). For details of operation
in each mode, see the section of each counter operation.
Table 5-3 List of Counter Operation
MOD[1:0] RELD
Operation in case of underflow
Counter operation name
0
Stop the counter with 0xFFFF
Single one-shot
1
Reload TMRLRA
Single reload
0
(1) Reload TMRLRB
(2) Stop the counter with 0xFFFF
(See "5.3.3Dual One-shot Operation")
Dual one-shot
1
Reload TMRLRA and TMRLRB in turns
Dual reload
0
Stop the counter with 0xFFFF
Compare one-shot
1
Reload TMRLRA
Compare reload
0
Stop the counter with 0xFFFF
Capture one-shot
1
Reload TMRLRA
Capture reload
00
01
10
11
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5.1.6.
TOUT Pin Level Setting
The TOUT Pin level setting is shown below.
Set pin output polarity using bit5:OUTL bit in the TMCSR register.
The relationships between events and the TOUT pin in each function are as follows:
A/B of the UF (underflow) section below indicates whether down counting underflow has occurred with a value when
loading TMRLRA data or TMRLRB data. CMP (compare-match) shows the timing of down counting from
TMRLRB = TMR.
Figure 5-1 TOUT Output Change in Each Event (1 / 3)
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Figure 5-2 TOUT Output Change in Each Event (2 / 3)
Figure 5-3 TOUT Output Change in Each Event (3 / 3)
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5.2. Operation Procedure
Operation procedures are shown.
5.2.1.
Activation
Activation is shown below.
Writing "1" into the bit1:CNTE bit of the TMCSR register changes the counter state to activation trigger waiting.
TIN input during trigger input functioning
If writing "1" to the bit0:TRG bit of the TMCSR register or inputting external trigger through TIN input takes
place during activation trigger waiting, the prescaler will be cleared and the timer will load a value from the reload
register to start down count operation. For TIN, input pulse of 2 × T (T indicates the peripheral clock (PCLK)
cycle) or more.
TIN input during gate input functioning
If writing "1" to the bit0:TRG bit of the TMCSR register during activation trigger waiting, the prescaler will be
cleared and the timer will load a value from the reload register and change the state to effective input polarity
waiting. If there is any gate input with effective polarity from TIN input in the effective input polarity waiting, the
timer initiates down count operation. For TIN, input pulse of 2 × T (T indicates the peripheral clock (PCLK)
cycle) or more.
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Figure 5-4 Timer Activation
Peripheral clock
CNTE (register)
TIN (pin)
TIN pin
effective edge
Prescaler clear
Prescaler clock
Data load
Counter value
Reload data
-1
-1
-1
Timer Activation (when the trigger input function and the rising edge trigger are selected)
Peripheral clock
CNTE (register)
TRG (register)
Prescaler clear
Prescaler clock
Data load
TIN (Pin)
Counter value
Reload data
-1
-1
Timer Activation (when in the gate input function)
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5.2.2.
Retrigger
The retrigger is explained.
The trigger which is generated during timer counting is called "retrigger". In this case, the following actions are
taken:
1.
2.
3.
4.
Initialize TOUT
Load the reload register value to the counter
Clear the 6-bit prescaler
Continue counting
Only in the capture mode, retrigger generation transfers a value being counted to the TMRLRB to set the EF bit of the
TMCSR register.
Note:
TOUT is not initialized in the one shot mode at retrigger.
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Figure 5-5 Retrigger Operation
Count clock
TIN(pin)
TIN pin
effective edge
TRG(register)
Retrigger
Trigger
CNTE(register)
Prescaler clear
Reload data
Count value
-1
-1
Reload data
-1
-1
-1
TOUT
(When OUTL=0)
Retrigger Operation (TIN is trigger input, the rising edge trigger, one-shot output)
Count clock
TIN(pin)
CNTE(register)
Prescaler
clear
Count value
TRG(register)
Reload data
-1
-1
-1
Reload data
-1
-1
-1
Retrigger
TOUT
(When OUTL=0)
Retrigger Operation (TIN is gate input, count in H level, one-shot output)
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5.2.3.
Underflow/Reload
Underflow/reload is shown below.
Underflow is defined as the timer down-counting from 0x0000. When underflow occurs, the bit2:UF bit of the
TMCSR register is set. Underflow takes place in the timer if the count value reaches "reload register setting value +
1" count.
5.2.4.
Generation of Interrupt Requests
Generation of interrupt requests is shown below.
When bit3:INTE bit of the TMCSR register is "1", if bit2:UF bit/bit7:EF bit are set, an interrupt request is generated.
In interval timer mode, the UF bit and the EF bit will be set under the following conditions.
UF bit is set: A counter underflow occurred
EF bit is set: A capture input occurred in capture mode
When a set of bit2:UF bit of the TMCSR register and a clear of the UF bit by writing "0" occurred concurrently,
writing "0" to the UF bit will be invalid and the UF bit will be set. When a set of bit7:EF bit and a clear of the EF bit
by writing "0" occurred concurrently, writing "0" to the EF bit will be invalid and the EF bit will be set.
The following is the example of generation of interrupt requests.
Figure 5-6 Example of UF Interrupt Request Output Operation
Count clock
Counter value
0x0001
0x0000
Reload data
-1
-1
-1
Underflow
UF bit
Interrupt request
UF interrupt request output operation (bit4:RELD= "1" and bit3:INTE="1" of TMCSR register)
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5.2.5.
Concurrent Operation of Register Write and Timer
Activation
The concurrent operation of register write and timer activation is shown below.
The following table shows the operation when a register write by a user and the timer operation occurred
simultaneously.
Table 5-4 Concurrent Operation
Writing to register
Operation of timer
Operation to execute
A clear of the UF bit by writing
"0"
Setting of the UF bit
Setting of the UF bit
(Writing "0" is ignored)
A clear of the EF bit by
writing "0"
Setting of the EF bit
Setting of the EF bit
(Writing "0" is ignored)
Writing to the reload register
Loading of timer by
retrigger
Reloading old data
(The written value will be loaded next time)
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5.3. Operations of Each Counter
Operations of each counter are shown.
5.3.1.
Single One-shot Operation
The single one-shot operation is shown below.
When bit15, 14: MOD[1:0] = "00" and bit4: RELD of the TMCSR register = "0", the timer performs single one-shot
operation triggered by an underflow occurrence, that stops at 0xFFFF.
In the single one-shot configuration, if an underflow occurs, the following operation will be performed.
Sets the UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Stops the count with 0xFFFF.
Initializes TOUT output.
Timer is waiting for a trigger.
For the single one-shot timer, TMRLRA turns to the initial value of the counter when a reload took place. TMRLRB
is not used.
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Figure 5-7 Single One-shot Operation
Count clock
TIN
(pin)
TTRG(pin)
TTRG
TIN pinpin
effectiveedge
edge
effective
Counter value
0x0001
0x0000
0xFFFF
TMRLRA
-1
-1
Underflow
UF bit
TOUT
(When OUTL=0)
Reload
Count operation
waiting for
activation trigger
Details of Underflow operation
(When the trigger input and rising edge trigger are selected)
Underflow
TOUT
(When OUTL=0)
CNTE(register)
TTRG(pin)
TIN (pin)
TTRG
TIN pinpin
effective
effectiveedge
edge
Count operation
waiting for
activation trigger
TMRLRA+1
count
Single one-shot timer
Single one-shot timer (GATE="1":
gate input, TRGM:H input interval count)
(GATE="0": When the trigger input and rising edge trigger are selected)
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Underflow
TOUT
(When OUTL=0)
CNTE(register)
TTRG(pin)
TIN
(pin)
TRG(register)
Waiting for
activation trigger
Count operation
waiting for
effective gate input
TMRLRA+1
count
TMRLRA+1
count
Single one-shot timer
Single (GATE="0":
one-shot timer
gate
TRGM:
input
interval count)
When (GATE="1":
the trigger input
and input,
rising edge
triggerHare
selected)
5.3.2.
Single Reload Operation
The single reload operation is shown below.
When bit15, 14: MOD[1:0] = "00" and bit4: RELD of the TMCSR register = "1", the single reload operation will be
performed.
In single reload operation, a value will be loaded from TMRLRA to the timer by trigger input, a down count
(decrementing the count) will start. When an underflow occurs, the value is reloaded from TMRLRA again and the
down count operation continues. The value of TMRLRA represents the time the timer will reload. The TMRLRB
register is not used. In single reload configuration, if an underflow occurs, the following operation will be performed.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Loads TMRLRA register onto the counter.
Inverts TOUT output.
Continues decrementing count.
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Figure 5-8 Single Reload Operation
Timer reloaded
register
TMRLRA
TMRLRA
TMRLRA
TMRLRA
TMRLRA
TMRLRA+1
count
TMRLRA+1
count
TMRLRA
TMRLRA
Underflow
UF bit
TMRLRA+1
count
TMRLRA+1
count
TMRLRA+1
count
TMRLRA+1
count
TMRLRA+1
count
TOUT
(When OUTL=0)
CNTE(register)
Data load
TRG(register)
Count operation
waiting for
activation trigger
Single reload function (GATE="0": trigger input)
Timer loaded
register
TMRLRA
TMRLRA
TMRLRA
TMRLTA+1
count
TMRLTA+1
count
TMRLRA TMRLRA
TMRLRA
Underflow
UF bit
TOUT
(When OUTL=0)
TMRLTA+1
count
TMRLTA+1
count
TMRLTA+1
count
TMRLTA+1
count
TIN (pin)
TTRG(pin)
CNTE(register)
Data load
TRG(register)
Waiting for
activation trigger
Count operation waiting
for effective gate input
Single reload function (GATE="1": gate input, TRGM: H input interval count)
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5.3.3.
Dual One-shot Operation
The dual one-shot operation is shown below.
When bit15, 14: MOD[1:0] = "01" and bit4: RELD of the TMCSR register = "0", the timer performs the dual
one-shot operation. This can be used as a one-shot PPG.
In dual one-shot operation, values are loaded into the counter one by one in the order of TMRLRA then TMRLRB,
and the down count is executed for each of the loaded values. The counter stops when the second underflow occurs.
When bit5: OUTL of the TMCSR register = "0" , the value of TMRLRA represents the time interval between a timer
activation (TOUT output is in L level) to a toggling of the TOUT output to "H", and the value of TMRLRB represents
the time interval of H width of the TOUT output.
Figure 5-9 TOUT Pulse Width
H width = TMRLRB
Trigger
TOUT external pin output
Delay = TMRLRA
When the first underflow occurs (UF-A), the following operation will take place.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Loads TMRLRB to the counter.
Inverts TOUT output.
Starts a down count from TMRLRB.
When the second underflow (UF-B) occurs, the following operation will take place.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Stops the count with 0xFFFF.
Initializes TOUT output.
Timer is waiting for an activation trigger.
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Figure 5-10 Dual One-shot Operation
Count clock
Underflow
UF-A
UF-B
UF-A
UF bit
CNTE(register)
TIN
(pin)
TTRG(pin)
TIN
pin
TTRG
pin
effective
effective edge
edge
TOUT
(When OUTL=0)
TMRLRA + 1
count
Waiting for
activation trigger
Timer reloaded
register
Counter value
TMRLRB + 1
count
TMRLRA
A:TMRLRA
B:TMRLRB
A
-1
TMRLRB
0
B -1 -1 -1 -1
0
TMRLRB + 1
count
TMRLRA + 1
count
Waiting for
activation trigger
TMRLRA
0xFFFF
A
-1
TMRLRB
0
B
-1 -1
Dual one-shot operation ( When the trigger input and rising edge trigger are selected)
Count clock
Underflow
UF-A
UF-B
UF-A
UF bit
CNTE(register)
TRG(register)
TIN (pin)
TTRG(pin)
TOUT
(OUTL=0)
Waiting for
activation trigger
Timer reloaded
register
Counter value
TMRLRA + 1
count
TMRLRA
A:TMRLRA
B:TMRLRB
A -1
TMRLRB + 1
count
Waiting for
activation trigger
TMRLRB
0 B -1 -1 -1 -1
0
0xFFFF
TMRLRA + 1
count
TMRLRB + 1
count
TMRLRA
TMRLRB
A -1
0 B
-1
Dual one-shot operation (gate input)
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5.3.4.
Dual Reload Operation
The dual one-shot operation is shown below.
When bit15, 14: MOD[1:0] = "01" and bit4: RELD of the TMCSR register = "1", the timer performs the dual reload
operation.
In dual reload operation, the values of TMRLRA and TMRLRB are loaded alternatively and decrement the counters
for each load, that is, loads TMRLRA onto the counter and decrements the counter, and if an underflow occurs, loads
TMRLRB onto the counter and decrement the counter, and if an another underflow occurs, loads TMRLRA onto the
counter and decrements the counter, and so on.
When bit5: OUTL of the TMCSR register = "0", the value of TMRLRA represents the time interval between a timer
activation (TOUT output is in L level) to a toggling of the TOUT output to "H", and the value of TMRLRB represents
the time interval of H width of the TOUT output.
If an underflow (UF-A) occurs at the down count after loading a value from the TMRLRA, the following operation
will be performed.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Loads TMRLRB to the counter.
Inverts TOUT output.
Starts a down count from TMRLRB.
If an underflow (UF-B) occurs at the down count after loading a value from the TMRLRB, the following operation
will be performed.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Loads TMRLRA to the counter.
Inverts TOUT output.
Starts a down count from TMRLRA.
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Figure 5-11 Dual Reload Operation
A:TMRLRA
B:TMRLRB
Timer reloaded
register
A
Underflow
B
UF-A
A
B
A
UF-B
B
A
B
UF-B
UF-A
A
UF-B
UF-A
UF-A
UF bit
TOUT
(When OUTL=0)
CNTE(register)
Data load
TRG(register)
Waiting for activation trigger
Count from TMRLRA
Count from TMRLRB
(GATE= "0"
: trigger
input)
Dual Reload function (GATE=0
: trigger
input)
Timer reloaded
register
A:TMRLRA
B:TMRLRB
Underflow
A
B
A
B
A
B
UF-B
UF-A
A
UF-B
UF-A
UF-A
UF bit
TOUT
(When OUTL=0)
TTRG(pin)
TIN (pin)
CNTE(register)
Data load
TRG(register)
Waiting for activation trigger
Waiting for effective gate input
Count from TMRLRA
Count from TMRLRB
(GATE= "1"
: gate
input,
inputinterval
intervalcount)
count)
Dual Reload function (GATE=1
: gate
input,
H Hinput
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5.3.5.
Compare One-shot Operation
The compare one-shot operation is shown below.
When bit15, 14: MOD[1:0] = "10" and bit4: RELD in TMCSR register = "0", the compare one-shot operation in
which the counter value (TMR) and the value of TMRLRB register are compared for each down count will be
performed. After accepting a trigger, the value of the TMRLRA register is loaded and the down count starts. When
decrementing the count from the value of compare match (TMR = TMRLRB), the TOUT output will be inverted.
When an underflow occurs, count operations stopped, TOUT output is initialized, and the timer go into the activation
trigger wait state.
The value of TMRLRA indicates the time interval between the activation of a timer and the end of it and the value of
TMRLRB indicates the counter value when an output of the H width of TOUT output starts. When OUTL="0" and
TMR < TMRLRB, the TOUT output will become the "H level".
Figure 5-12 TOUT Interval, Pulse Width
H width = TMRLRB
Trigger input
TOUT external pin output
Cycle = TMRLRA
From the start of a down count to TMR = TMRLRB (while TMR is greater than or equal to TMRLRB), the following
operation will be performed.
TOUT output continues to hold the initial value.
The timer continues to count.
If a down count from TMR = TMRLRB occurs, the following operation will be performed.
Inverts TOUT output.
The timer continues to count.
(For the compare operation in interval timer mode, bit7:EF bit of TMCSR register will not be set.)
If an underflow occurs, the following operation will be performed.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Initializes TOUT output.
The timer stops with 0xFFFF.
Timer is waiting for an activation trigger.
The operation of the compare function changes depending on the setting relation between TMRLRA and TMRLRB.
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Figure 5-13 Compare One-shot Operation (1 / 2)
• Sets TMRLRB < TMRLRA
When the register relation is as described above, the TOUT output is the "L" level until TMR and TMRLRB match
after loading to the timer. When down counting from the compare match (TMR=TMRLRB), the TOUT output is "H"
level until the TOUT output is inverted and an underflow occurs. When an underflow occurs the TOUT output will be
initialized. Then, the timer will stop counting operation and turn into the activation trigger waiting state (for
OUTL="0").
Count clock
Underflow
UF bit
Reload
TOUT
(for OUTL=0)
TMRLRA + 1
count
TMRLRB
count
Activation trigger waiting
Activation trigger
Compare-match
Counting from
comparison match
Register reloaded
by timer
TMRLRA
TMRLRA
Compare one-shot function (TMRLRB < TMRLRA)
• Sets TMRLRB > TMRLRA
When the register relation is as described above, the TOUT output is the "H" level between an activation trigger
generation and an underflow occurrence because TMR is already smaller than TMRLRB after loading to the
timer. When an underflow occurs, the timer will turn into the activation trigger waiting state and the TOUT output
will be the "L" level (for OUTL="0").
Count clock
Register reloaded
by timer
TMRLRA
TMRLRA
TMRLRA+1
TMRLRA+1
Underflow
TOUT
(for OUTL=0)
Activation trigger
Activation
trigger waiting
Activation
trigger waiting
Compare one-shot function (TMRLRB > TMRLRA)
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Chapter 21: Reload Timer
Figure 5-14 Compare One-shot Operation (2 / 2)
• Sets TMRLRB = TMRLRA
When the register relation is as described above, After loading to the timer, TMR will become
smaller than TMRLRB after 1 count. Thus the TOUT output is the "L" level for 1 down count
and then the "H" level until an underflow occurs. When an underflow occurs, the timer will
turn into the activation trigger waiting state and the TOUT output will be the "L" level (for
OUTL="0").
Register reloaded
by timer
TMRLRA
TMRLRA
Count clock
Underflow
TOUT
(for OUTL=0)
1 count
1 count
TMRLRA+1
Activation
trigger
TMRLRA+1
Activation trigger
waiting
Activation trigger
waiting
Compare one-shot function (TMRLRB=TMRLRA)
• Sets TMRLRB = 0
When the register relation is as described above, the TOUT output is the "L" level between
down count start and an underflow occurrence because TMR will not become smaller than
TMRLRB. The level will remain to be "L" even when an underflow occurs (for OUTL="0").
Count clock
Register reloaded
by timer
TMRLRA
TMRLRA
Underflow
TOUT
H
(for OUTL=0) L
Activation trigger
waiting
Activation
trigger waiting
TMRLRA+1
Activation
trigger waiting
TMRLRA+1
Activation
trigger
Compare one-shot function (TMRLRB="0")
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5.3.6.
Compare Reload Operation
The compare reload operation is shown below.
When bit15, 14: MOD[1:0] = "10" and bit4: RELD of the TMCSR register = "1", the timer compares a counter value
(TMR) to the value of TMRLRB for each down count and if a compare match (TMR = TMRLRB) is detected, a
down count starts and the TOUT output will be inverted. When an underflow occurs, the compare reload operation
will be performed, in which a value is loaded from TMRLRA again and the down count operation starts. A load onto
the counter starts from TMRLRA.
The value of TMRLRA indicates the counter interval from a timer activation until a reload and the value of TMRLRB
indicates the "H level width" after the TOUT output inverted from "L level output" to "H level output".
When TMR + 1 = TMRLRB, TOUT output will invert to the "H level" (when OUTL= "0").
Figure 5-15 TOUT Interval, Pulse Width
H width = TMRLRB
TOUT external pin output
Cycle = TMRLRA
From the start of a down count to TMR = TMRLRB (while TMR is greater than or equal to TMRLRB), the following
operation will be performed.
TOUT output continues to hold the initial value.
Count continues
When a down count starts from TMR = TMRLRB, the following operation will be performed.
Inverts TOUT output.
Count continues.
(For the compare operation in interval timer mode, bit7:EF bit of TMCSR register will not be set.)
If an underflow occurs, the following operation will be performed.
Sets bit2:UF bit of the TMCSR register.
When interrupts are enabled (bit3:INTE= "1" of TMCSR register), an interrupt occurs.
Initializes TOUT output.
Reloads a value from TMRLRA.
The timer continues to count.
The operation of a compare feature depends on the relationship between TMRLRA and TMRLRB.
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Figure 5-16 Compare Reload Operation (1 / 2)
• Sets TMRLRB < TMRLRA
When the register relation is as described above, the TOUT output is the "L" level until TMR and
TMRLRB match after loading to the timer. When down counting from the compare match
(TMR=TMRLRB), the TOUT output is "H" level until the TOUT output is inverted and an underflow
occurs. When an underflow occurs the TOUT output will be initialized. When an under flow occurs, the
timer will reload from TMRLRA and continue counting operation (for OUTL="0").
Count clock
Underflow
UF bit
Reload
TOUT
(for OUTL=0)
TMRLRA + 1
count
TMRLRB
count
TMRLRA + 1
count
TMRLRA + 1
count
TMRLRB
count
TMRLRB
count
Compare-match
Counting from
comparison match
EF bit
Register
reloaded by timer
TMRLRA
TMRLRA
TMRLRA
Compare reload function (TMRLRB < TMRLRA) trigger input
• Sets TMRLRB > TMRLRA
When the register relation is as described above, the TOUT output is the "H" level after an activation
trigger is generated and an underflow occurs because TMR is always smaller than TMRLRB. The level
will remain to be "H" even when an underflow occurs. When an underflow occurs, the timer will load
from TMRLRA and continue counting operation (for OUTL="0").
Count clock
Register
reloaded by timer
TMRLRA
TMRLRA
TMRLRA
Underflow
UF bit
TOUT
(for OUTL=0)
TMRLRA+1
TMRLRA+1
TMRLRA+1
Activation trigger
Compare reload function (TMRLRB > TMRLRA) trigger input
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Figure 5-17 Compare Reload Operation (2 / 2)
• Sets TMRLRB = TMRLRA
When the register relation is as described above, 1 count up after loading to the timer makes
TMR become smaller than TMRLRB. Thus the TOUT output is the "L" level for 1 down count
and then the "H" level until an underflow occurs. When an underflow occurs, the timer will
reload from TMRLRA and continue counting operation. The TOUT output will remain to be
the L level. (For OUTL= "0")
Register
reloaded by timer
TMRLRA
TMRLRA
TMRLRA
Count clock
Underflow
UF bit
TOUT
(for OUTL=0)
1 count
1 count
TMRLRB
1 count
TMRLRB
1 count
TMRLRB
TMRLRA+1
TMRLRA+1
TMRLRA+1
Compare-match
Down
count from
comparison match
EF bit
L
Activation trigger
Compare reload function (TMRLRB = TMRLRA) trigger input
• Sets TMRLRB = 0
When the register relation is as described above, the TOUT output is the "L" level between down
count start and an underflow occurrence after loading to the timer because TMR will not become
smaller than TMRLRB. The level will remain to be "L" even when an underflow occurs.
Count clock
Register
reloaded by timer
TMRLRA
TMRLRA
TMRLRA
TMRLRA+1
TMRLRA+1
Underflow
UF bit
H
TOUT
(for OUTL=0)L
TMRLRA+1
Activation trigger
Compare reload function (TMRLRB = "0") trigger input
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Chapter 21: Reload Timer
5.3.7.
Capture Mode
The capture mode is shown below.
When bit15, 14: MOD[1:0] of the TMCSR register = "11", the timer will perform capture operation. When a retrigger
occurs, TMRLRB register captures the TMR value and sets bit7:EF of the TMCSR register.
When you use TIN input as the gate input (when bit8:GATE= "1" of the TMCSR register), generate a retrigger by
bit0:TRG of the TMCSR register.
In a mode other than capture, a capture will not be performed at a retrigger. The EF interrupt will also not be
generated.
The timer operation and the TOUT output will be the same for the single one-shot feature and the single reload
feature.
Note:
TOUT is not initialized in the one shot mode at retrigger.
Figure 5-18 Operation of Capture
Trigger input
Retrigger input
Counter value
TMRLRA
Underflow
Underflow
Capture TMR
to TMRLRB
0
UF interrupt
&
Reload (TMRLRA)
EF interrupt
&
Capture (TMRLRB)
&
Reload (TMRLRA)
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Figure 5-19 Flowchart of Trigger Input Features in Interval Timer Mode
GATE=0 AND
CSL[2:0]=000 to 101
CNTE=1?
NO
YES
TRG=1
TRG=1 or
or
TTRG
effectiveedge
edgeinput
input
TIN effective
NO
YES
Reloads to the timer
NO
Clock?
YES
Count-1
NO
Underflow occurs?
NO
RELD = 1?
YES
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Chapter 21: Reload Timer
Figure 5-20 Flowchart in Event Counter Mode
CSL [2:0] = 111
NO
CNTE=1?
YES
NO
TRG=1?
YES
Loads to the counter
Valid event input?
NO
YES
Count-1
Underflow occurs?
NO
YES
NO
RELD = 1?
YES
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5.4. Cascade Input
Cascade input is shown below.
When you select cascade input (bit11 to bit9:CSL[2:0]=110 of TMCSR register), you can use the timer's ch.0 output
(TOUT0) for the input for ch.1 (TIN1), ch.1 output (TOUT1) for the input for ch.2 (TIN2), and ch.2 output (TOUT2)
for the input for ch.3 (TIN3).
ch.4 to ch.7 are also similar to the above.
Figure 5-21 Timer Input/Output in Cascade Input Configuration
(1) Using ch.1 in cascade settings
Timer ch.0
TOT0
Timer ch.1
TIN1
(2) Using ch.2 in cascade settings
Timer ch.1
TOT1
Timer ch.2
TIN2
(3) Using ch.3 in cascade settings
Timer ch.2
TOT2
Timer ch.3
TIN3
5.5. Priority of Concurrent Operations
The priority of concurrent operations is shown below.
When two events to decide the timer operation occur simultaneously, the priority of deciding the operating state is
indicated.
1.
2.
3.
4.
Writing to register
Trigger input
Underflow
Clock input
When a set of each flag by the timer operation and a clear of a flag by register write occur concurrently, the priority of
deciding the operation is indicated.
1.
2.
718
Setting flag by the timer operation
Writing to a register for a clear of flag to the UF bit/EF bit
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Chapter 21: Reload Timer
6. Application Note
This section explains an application note concerning the register for the reload timer.
This section shows the typical functions which can be realized with this timer.
Figure 6-1 Example
Single one-shot timer
TOUT output
Activation trigger
Reload timer
Retrigger
TOUT output
Underflow
Compare match
PPG
(Dual one-shot timer)
Capture to the TMLRB
Downcount
TMRLRA
Down
count from TMRLRA
TOUT output
Down
count from TMRLRB
Downcount
TMRLRB
Interrupt can be generated(Set UF bit)
PPG
(Dual reload timer)
TOUT output
PWM
(Reload output compare)
TOUT output
PWC
Activation trigger
(Reload input capture)
Capture input
(TIN effective
(TTRG
effectiveedge)
edge)
Underflow
TTRG
input
TIN input
Counter value
TMRLRA
TMRLRB register
CNT_a
Reload
TMRLRA0
TMRLRA
Reload
0
CNT_a
CNT_b
Reload
TMRLRA
Down count from
from TMRLRA
Downcount
TMRLRA
Interrupt can be generated(Set UF bit)
Interrupt can be generated(Set EF bit)
CNT_b
Note: When the rising edge is specified as effective edge.
Following are some configurations for use of example figure above.
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Table 6-1 Example of Configuration
Function
MOD[1:0]
RELD
TMRLRA
TMRLRB
Single one-shot timer
00
(Single mode)
0
Mandatory
-
Reload timer
00
(Single mode)
1
Mandatory
-
01
(Dual mode)
0 or 1
Mandatory
Mandatory
PWM
(Pulse Width Modulator)
10
(Compare mode)
1
Mandatory
Mandatory
PWC
(Pulse Width Counter)
11
(Capture mode)
1
Mandatory
-
PPG
(Programmable Pulse Generator)
6.1. Single One-shot Timer
The single one-shot timer is shown below.
The single one-shot timer loads a value from the TMRLRA register onto the counter and starts to decrement the
counter (down count operation) when a trigger is input. When an underflow occurs, the counting stops.
The TOUT pin outputs the "H level" in counting and when an underflow occurs it will output the "L level". (When
OUTL= "0")
[Configuration] To use this timer as a single one-shot timer, configure as follows.
1.
When TIN input is not used
TMCSR
MOD TRGM
[1:0]
[1:0]
00
00
CSL
[2:0]
*1
TMRLRA
GATE EF OUTL RELD INTE
0
-
*2
0
*3
UF
CNTE TRG
-
1
Count initial
value setting
S
S :Use at timer activation
-:Does not influence operation
*1:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*2:TOUT output polarity setting
OUTL=0------Initial value L=> Count starts H=> Underflow occurs L
OUTL=1------Initial value H=> Count starts L=> Underflow occurs H
*3:Interrupt request enable setting
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INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
2.
When using TIN input as a gate input
TMCSR
MOD TRGM
[1:0]
[1:0]
00
*1
CSL
[2:0]
*2
TMRLRA
GATE EF OUTL RELD INTE
1
-
*3
0
UF
*4
-
CNTE TRG
1
Count initial value
setting
S
S :Use at timer activation
-:Does not influence operation
*1: TIN effective level setting
TRGM[1:0]=x0------Count only for L input interval
TRGM[1:0]=x1------Count only for H input interval
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:TOUT output polarity setting
OUTL= 0------Initial value L=> Count starts H=> Underflow occurs L
OUTL= 1------Initial value H=> Count starts L=> Underflow occurs H
*4:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
3.
When using TIN input as a trigger input
TMCSR
MOD TRGM
[1:0]
[1:0]
00
*1
CSL
[2:0]
*2
TMRLRA
GATE EF OUTL RELD INTE
0
-
*3
0
UF
*4
-
CNTE TRG
1
Count initial value
setting
S
S :Use at timer activation
-:Does not influence operation
*1: TIN effective level setting
TRGM[1:0]= 00------Does not detect external trigger edge
TRGM[1:0]= 01------Rising edge
TRGM[1:0]= 10------Falling edge
TRGM[1:0]= 11------Both edges
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
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CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:OUT output polarity setting
OUTL= 0------Initial value L=> Count starts H=> Underflow occurs L
OUTL= 1------Initial value H=> Count starts L=> Underflow occurs H
*4:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
[Timer activation] Follow the steps below to activate the timer.
Input an activation trigger (a write of "1" to the TRG bit or an input of effective external edge from TIN pin)
Input an effective level when you use TIN pin input as the gate input
Figure 6-2 Example of Operation (OUTL = 0)
TOUT
(TMRLRA + 1)
Counter value
TMRLRA
0x0000
0xFFFF
Activation trigger
Underflow
Down
count
Downcount
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6.2. Reload Timer
The reload timer is shown below.
The reload timer loads from the TMRLRA register onto the counter and repeats the down count operation each time
underflow occurs. The TOUT outputs the "L level" while the count is ongoing from the activation trigger to the
occurrence of the first underflow. The output is inverted each time an underflow occurs, and the TOUT outputs "H
level" with the occurrence of the first underflow. When a retrigger occurs, TOUT output returns to its initial value.
(When OUTL= "0")
[Configuration] To use the timer as the reload timer, configure as follows.
1.
When TIN input is not used
TMCSR
MOD TRGM
[1:0]
[1:0]
00
00
CSL
[2:0]
*1
TMRLRA
GATE EF OUTL RELD INTE
0
-
*2
1
*3
UF
-
CNTE TRG
1
Count initial value
setting
S
S :Use at timer activation
-:Does not influence operation
*1:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*2:TOUT output polarity setting
OUTL=0------Initial value L=> Count starts L=> Invert whenever an underflow occurs
OUTL=1------Initial value H=> Count starts H=> Invert whenever an underflow occurs
*3:Interrupt request enable setting
INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
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2.
When using TIN input as a gate input
TMCSR
MOD TRGM
[1:0]
[1:0]
00
*1
CSL
[2:0]
*2
TMRLRA
GATE EF OUTL RELD INTE
1
-
*3
1
*4
UF
-
CNTE TRG
1
Count initial value
setting
S
S :Use at timer activation
-:Does not influence operation
*1: TIN effective level setting
TRGM[1:0]=x0------Count only for TIN=L input interval
TRGM[1:0]=x1------Count only for TIN=H input interval
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:OUT output polarity setting
OUTL=0------Initial value L=> Count starts L=> Invert whenever an underflow occurs
OUTL=1------Initial value H=> Count starts H=> Invert whenever an underflow occurs
*4:Interrupt request enable setting
INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
3.
When using TIN input as a trigger input
TMCSR
MOD TRGM
[1:0]
[1:0]
00
*1
CSL
[2:0]
*2
TMRLRA
GATE EF OUTL RELD INTE
0
-
*3
1
*4
UF
-
CNTE TRG
1
Count initial value
setting
S
S :Use at timer activation
-:Does not influence operation
*1: TIN effective edge setting
TRGM[1:0]= 00------Does not detect external trigger edge
TRGM[1:0]= 01------Rising edge
TRGM[1:0]= 10------Falling edge
TRGM[1:0]= 11------Both edges
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:OUT output polarity setting
OUTL= 0------Initial value L=> Count starts L=> Invert whenever an underflow occurs
OUTL= 1------Initial value H=> Count starts H=> Invert whenever an underflow occurs
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*4:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
[Timer activation] Follow the steps below to activate the timer.
Input an activation trigger (a write of "1" to the TRG bit or an input of effective external edge from TIN pin)
Input an effective level when you use TIN pin input as the gate input
Figure 6-3 Example of Operation (OUTL=0)
TOUT
(TMRLRA + 1)
Counter value
TMPLRA
0x0000
(TMRLRA + 1)
TMRLRA
0x0000
TMRLRA
Activation trigger
Underflow
Downcount
Down count
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Chapter 21: Reload Timer
6.3. PPG
PPG is shown below.
PPG is the feature which generates an output pulse by configuring L width/H width of the pulse. An activation trigger
launches a load from TMRLRA to the counter and the operation switches to load the value from TMRLRB and
executes a down count when an underflow occurs.
When RELD=0, "Activation trigger => TMRLRA load => Down count=> Underflow => TMRLRB
load => Down count => Underflow, " then stops the down count.
When RELD=1, counter is loaded with TMRLRA/TMRLRB alternatively and executes down count whenever an
underflow occurs, such as Activation trigger => TMRLRA load => Down count => Underflow => TMRLRB load =>
Down count => Underflow => TMRLRA load => Down count => Underflow => TMRLRB load and so on.
The TOUT outputs the "L level" while counting until the occurrence of an underflow caused by the down count from
TMRLRA, and outputs the "H level" while counting until the occurrence of an underflow caused by the down count
from TMRLRB. When a retrigger occurs, TOUT output returns to its initial value.
Note:
TOUT is not initialized in the one shot mode at retrigger.
[Configuration] To use the timer as PPG, configure as follows.
1.
When TIN input is not used
TMCSR
MOD TRGM
[1:0] [1:0]
01
00
TMRLRA TMRLRB
CSL
GATE EF OUTL RELD INTE
[2:0]
*1
0
-
*2
*3
*4
UF CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value at an activation trigger/The reload value at an underflow caused by the count
from the TMRLRB value (when RELD=1)
(B): The reload value at an underflow caused by the count from the TMRLRA value
S :Use at timer activation
-:Does not influence operation
* 1:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
* 2:TOUT output polarity setting
OUTL= 0-----Initial value L => Count L from TMRLRA => H when an underflow occurs =>
Count H from TMRLRB => L when an underflow occurs
OUTL= 1------
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Chapter 21: Reload Timer
Initial value H => Count H from TMRLRA => L when an underflow occurs =>
Count L from TMRLRB => H when an underflow occurs
*3:Reload setting when an underflow occurs
RELD= 0------One-shot mode
RELD= 1------Reload mode
*4:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
2.
When using TIN input as a gate input
TMCSR
MOD TRGM
[1:0] [1:0]
01
*1
TMRLRA TMRLRB
CSL
GATE EF OUTL RELD INTE
[2:0]
*2
1
-
*3
*4
*5
UF CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value at an activation trigger/The reload value at an underflow caused by the count
from the TMRLRB value (when RELD=1)
(B): The reload value at an underflow caused by the count from the TMRLRA value
S :Use at timer activation
-:Does not influence operation
* 1: TIN effective level setting
TRGM[1:0]= x0------Count only for TIN=L input interval
TRGM[1:0]= x1------Count only for TIN=H input interval
* 2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
* 3:TOUT output polarity setting
OUTL= 0-----Initial value L=> Count L from TMRLRA => H when an underflow occurs =>
Count H from TMRLRB => L when an underflow occurs
OUTL= 1-----Initial value H=> Count H from TMRLRA => L when an underflow occurs =>
Count L from TMRLRB => H when an underflow occurs
*4:Reload setting when an underflow occurs
RELD=0------One-shot mode
RELD=1------Reload mode
*5:Interrupt request enable setting
INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
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3.
When using TIN input as a trigger input
TMCSR
MOD TRGM
[1:0] [1:0]
01
*1
TMRLRA TMRLRB
CSL
GATE EF OUTL RELD INTE
[2:0]
*2
0
-
*3
*4
*5
UF CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value at an activation trigger/The reload value at an underflow caused by the count
from the TMRLRB value (when RELD=1)
(B): The reload value at an underflow caused by the count from the TMRLRA value
S :Use at timer activation
-:Does not influence operation
*1: TIN effective edge setting
TRGM[1:0]= 00------Does not detect external trigger edge
TRGM[1:0]= 01------Rising edge
TRGM[1:0]= 10------Falling edge
TRGM[1:0]= 11------Both edges
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => Invert whenever an underflow occurs
OUTL= 1------Initial value H=> Count H from TMRLRA => Invert whenever an underflow occurs
*4:Reload setting when an underflow occurs
RELD=0------One-shot mode
RELD=1------Reload mode
*5:Interrupt request enable setting
INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
[Timer activation] Follow the steps below to activate the timer.
Input an activation trigger (a write of "1" to the TRG bit or an input of effective external edge from TIN pin)
Input an effective level when you use TIN pin input as the gate input
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Chapter 21: Reload Timer
Figure 6-4 Example of Operation (OUTL=0)
TOUT
(TMRLRA + 1)
Counter value
TMPLRA
(TMRLRB + 1)
0000
TMRLRB
0x0000
TMRLRA
Activation trigger
Underflow
Downcount
Down count
6.4. PWM
PWM is shown below.
PWM is the feature which generates an output pulse by configuring the pulse interval and H width.
An activation trigger launches a load from TMRLRA to the counter and executes a down count.
TOUT outputs the "L level" after an activation trigger and then outputs the "H level" when the counter value becomes
smaller than the TMRLRB value. When an underflow occurs, TOUT output returns to its initial value. (When
OUTL= "0")
When RELD= "0", Activation trigger=> TMRLRA load => Down count => Underflow, then counter stops the down
count.
When RELD= "1", counter is loaded with TMRLRA, and it is decremented for each load whenever an underflow
occurs, such as Activation trigger=> TMRLRA load=> Down count=> Underflow=> TMRLRA load=> Down count,
and so on.
[Configuration] To use the timer as PWM, configure as follows.
1.
When TIN input is not used
TMCSR
MOD TRGM
[1:0] [1:0]
10
0
TMRLRA TMRLRB
CSL
GATE EF OUTL RELD INTE
[2:0]
*1
0
-
*2
*3
*4
UF
CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value when activation trigger occurs/The reload value at an underflow (when
RELD=1)
(B): Set the value to compare to the counter value (TMRLRB < TMRLRA) *5
S :Use at timer activation
-:Does not influence operation
*1:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
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Chapter 21: Reload Timer
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*2:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => H, the counter value is smaller than TMRLRB
OUTL= 1------Initial value H=> Count H from TMRLRA => L, the counter value is smaller than TMRLRB
*3:Reload setting when an underflow occurs
RELD= 0------One-shot mode
RELD= 1------Reload mode
*4:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
*5:To use TOUT output with L clip output, set to TMRLRB = "0".
To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1".
2.
When using TIN input as a gate input
TMCSR
MOD TRGM
[1:0] [1:0]
10
*1
TMRLRA TMRLRB
CSL
GATE EF OUTL RELD INTE
[2:0]
*2
1
-
*3
*4
*5
UF
CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value when activation trigger occurs/The reload value at an underflow (when
RELD=1)
(B): Set the value to compare to the counter value(TMRLRB < TMRLRA) *6
S :Use at timer activation
-:Does not influence operation
*1: TIN effective level setting
TRGM[1:0]= x0------Count only for TRGM=L input interval
TRGM[1:0]= x1------Count only for TRGM=H input interval
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => H, the counter value is smaller than TMRLRB
OUTL= 1------Initial value H=> Count H from TMRLRA => L, the counter value is smaller than TMRLRB
*4:Reload setting when an underflow occurs
RELD=0------One-shot mode
RELD=1------Reload mode
*5:Interrupt request enable setting
INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
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Chapter 21: Reload Timer
*6:To use TOUT output with L clip output, set to TMRLRB = "0".
To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1".
3.
When using TIN input as a trigger input
TMCSR
TMRLRA TMRLRB
MOD TRGM CSL
GATE EF OUTL RELD INTE
[1:0] [1:0] [2:0]
10
*1
*2
0
-
*3
*4
*5
UF
CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value when activation trigger occurs/The reload value at an underflow (when
RELD=1)
(B): Set the value to compare to the counter value (TMRLRB < TMRLRA) *6
S :Use at timer activation
-:Does not influence operation
*1: TIN effective edge setting
TRGM[1:0]= 00------Does not detect external trigger edge
TRGM[1:0]= 01------Rising edge
TRGM[1:0]= 10------Falling edge
TRGM[1:0]= 11------Both edges
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => H, the counter value is smaller than TMRLRB
OUTL= 1------Initial value H=> Count H from TMRLRA => L, the counter value is smaller than TMRLRB
*4:Reload setting when an underflow occurs
RELD= 0------One-shot mode
RELD= 1------Reload mode
*5:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
*6:To use TOUT output with L clip output, set to TMRLRB = "0".
To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1".
[Timer activation] Follow the steps below to activate the timer.
Input an activation trigger (a write of "1" to TRG bit or an input of effective external edge from TIN pin)
Input an effective level when you use TIN pin input as the gate input
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Chapter 21: Reload Timer
Figure 6-5 Example of Operation (OUTL=0)
TOUT
TMRLRB + 1
TMRLRA + 1
Counter
value
TMRLRA
TMRLRB
0000
TMRLRA
: Activation trigger
: Compare-match
: Underflow
: Downcount
Down count
6.5. PWC
PWC is shown below.
PWC is the feature to measure the time interval between triggers to input.
An activation trigger launches a load of a value from TMRLRA onto the counter and executes a down count
operation. A trigger input during a count enables the counter value at that time to be captured onto TMRLRB, which
allows measuring the time interval between triggers to input.
[Configuration] To use the timer as PWC, configure as follows.
TMCSR
MOD TRGM
[1:0] [1:0]
11
*1
TMRLRA TMRLRB
CSL
GATE EF OUTL RELD INTE
[2:0]
*2
0
-
*3
*4
*5
UF
CNTE TRG
(A)
-
1
(B)
S
(A): The count initial value when activation trigger occurs/The reload value at an underflow (when RELD=1)
(B): The count value when trigger occurs during count operation
S :Use at timer activation
-:Does not influence operation
*1: TIN effective edge setting
TRGM[1:0]= 00------Does not detect external trigger edge
TRGM[1:0]= 01------Rising edge
TRGM[1:0]= 10------Falling edge
TRGM[1:0]= 11------Both edges
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => Invert whenever an underflow occurs
OUTL= 1------Initial value H=> Count H from TMRLRA => Invert whenever an underflow occurs
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Chapter 21: Reload Timer
*4:Reload setting when an underflow occurs
RELD= 0------One-shot mode
RELD= 1------Reload mode
*5:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
[Timer activation] Follow the steps below to activate the timer.
Input an activation trigger (a write of "1" to TRG bit or an input of effective external edge from TIN pin) While
down counting, the counter value will be captured onto the TMRLRB whenever a trigger input occurs. The time
interval between edges of the triggers to input will be obtained by the following formula.
T = (The set value for TMRLRA - The captured value for TMRLRB) × Peripheral clock (PCLK) cycle ×
Division ratio set with CSL
Figure 6-6 Example of Operation (TRGM=01)
TTRG
input
TIN input
TMRLRA
Counter value
CNT_A
TMRLRA
(reload)
TMRLRA
TMRLRB
0xXXXX
Activation trigger
(reload)
CNT_B
CNT_A
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Retrigger input
CNT_B
Downcount
Down
count
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Chapter 22: 32-Bit Free-Run Timer
This chapter explains the 32-bit free-run timer.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Setting
7.
Q&A
8.
Sample Program
9.
Notes
Code : FG61-1v0-91528-3-E
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Chapter 22: 32-Bit Free-Run Timer
1. Overview
This section explains the overview of the 32-bit free-run timer.
The 32-bit free-run timer consists of a 32-bit up counter and a control circuit. The free-run timer can be used in
combination with input capture and output compare.
Figure 1-1 Block Diagram (Overview)
External clock
(FRCK pin)
To output compare
Peripheral clock
(PCLK)
To input capture
Overflow
Clear
Up counter
Compare clear register
Compare
circuit
Interrupt
The numbers of channels available from external clocks are shown below.
MB91F52xR (144pin) : 3
MB91F52xU (176pin) : 3
MB91F52xM (208pin) : 8
MB91F52xY (416pin) : 8
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Chapter 22: 32-Bit Free-Run Timer
2. Features
This section explains the features of the 32-bit free-run timer.
2.1 Functions of the 32-bit Free-run Timer
2.2 Functions of the Free-run Timer Selector
2.1. Functions of the 32-bit Free-run Timer
The functions of the 32-bit free-run timer is shown.
Format : 32-bit up counter
Number of units : 8
Clock source : One of 9 internal clocks (peripheral clock (PCLK)/1, /2, /4, /8, /16, /32, /64, /128, /256) or one of
two external clocks (FRCK)
Count clear factors :
Software
Reset
Compare match (count value of the free-run timer matches the compare clear register)
Operation start/stop: The operation can be started and stopped by software.
Interrupt : Compare clear interrupt
Count value : Read/write enabled (writing is only enabled while counting is inactive)
The 32-bit free-run timer consists of a 32-bit up counter, control register, 32-bit compare clear register, and
prescaler.
A compare clear interrupt will be generated when a compare clear register matches the 32-bit free-run timer upon
comparison of the two.
If there is a compare match with reset, software clear or compare clear register, the counter value will be reset to
"0000_0000H".
It is used as the reference count for 32-bit output compare and 32-bit input capture.
2.2. Functions of the Free-run Timer Selector
The functions of the free-run timer selector is shown.
The allocation of the free-run timer can be selected from output compare and the input capture according to the
free-run timer selection register.
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Chapter 22: 32-Bit Free-Run Timer
3. Configuration
This section explains configuration of the free-run timer.
3.1 Configuration Diagram of the 32-bit Free-run Timer
3.2 Configuration Diagram of the Free-run Timer Selector
3.1. Configuration Diagram of the 32-bit Free-run Timer
The configuration diagram of the 32-bit free-run timer is shown.
Figure 3-1 Configuration Diagram of the 32-bit free-run timer (only one channel)
Count clock
CLK[3:0]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
TCCSn : bit3-0
CLKP
CLKP / 2
CLKP / 4
CLKP / 8
CLKP / 16
CLKP / 32
CLKP / 64
CLKP / 128
CLKP / 256
Setting is prohibited
0
Compare circuit
Compare clear register n
CPCLRn
Peripheral clock
(PCLK)
FRCKn
Timer data register n
Divider
TCDTn
External clock
synchronization
circuit
1
Internal clock
External clock
0
n=3 to 10
1
Free-run timer
interrupt
No interrupt request
Interrupt request
WRITE 0: Flag clear
1
0
1
Clear
To input capture and
output compare
SCLR
0
0
1
ICRE TCCSn:bit8
Clock selection
Count
ECKE TCCSn:bit15
value
0
Compare clear match flag
ICLR TCCSHn:bit9
TCCSn:bit4
1
Disable interrupt
Enable interrupt
1
0
STOP
TCCSn:bit6
0 Counting operation
1 Counting operation stop
Cancel timer initialization clear request
Timer clear
n=3 to 5
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Chapter 22: 32-Bit Free-Run Timer
3.2. Configuration Diagram of the Free-run Timer Selector
The configuration diagram of the free-run timer selector is shown.
Figure 3-2 Configuration Diagram of the Free-run Timer Selector
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Chapter 22: 32-Bit Free-Run Timer
4. Registers
This section explains the registers of the free-run timer.
Table 4-1 Base Address (Base_Addr) and External Pin Table
External pin (FRCK)
Channel
Base_addr
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
3
0x0240
FRCK3_0
FRCK3_0/FRCK3_1
FRCK3_0/FRCK3_1
4
0x024C
FRCK4_0
FRCK4_0/FRCK4_1
FRCK4_0/FRCK4_1
5
0x0FA0
FRCK5_0
FRCK5_0/FRCK5_1
FRCK5_0/FRCK5_1
6
0x0FAC
−
−
FRCK6_0
7
0x0FB8
−
−
FRCK7_0
8
0x0FC4
−
−
FRCK8_0
9
0x0EB4
−
−
FRCK9_0
10
0x0EF0
−
−
FRCK10_0
Table 4-2 Registers Map of 32-bit Free-run Timer
Registers
Address
Register function
+0
+1
+2
+3
0x0240
CPCLR3
Compare clear register 3
0x0244
TCDT3
Timer data register 3
0x0248
TCCSH3
TCCSL3
Reserved
Timer control register (Upper Bit) 3
Timer control register (Lower Bit) 3
0x024C
CPCLR4
Compare clear register 4
0x0250
TCDT4
Timer data register 4
0x0254
TCCSH4
TCCSL4
Reserved
Timer control register (Upper Bit) 4
Timer control register (Lower Bit) 4
0x0FA0
CPCLR5
Compare clear register 5
0x0FA4
TCDT5
Timer data register 5
0x0FA8
TCCSH5
TCCSL5
Reserved
Timer control register (Upper Bit) 5
Timer control register (Lower Bit) 5
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Chapter 22: 32-Bit Free-Run Timer
Registers
Address
Register function
+0
+1
+2
+3
0x0FAC
CPCLR6
Compare clear register 6
0x0FB0
TCDT6
Timer data register 6
0x0FB4
TCCSH6
TCCSL6
Reserved
Timer control register (Upper Bit) 6
Timer control register (Lower Bit) 6
0x0FB8
CPCLR7
Compare clear register 7
0x0FBC
TCDT7
Timer data register 7
0x0FC0
TCCSH7
TCCSL7
Reserved
Timer control register (Upper Bit) 7
Timer control register (Lower Bit) 7
0x0FC4
CPCLR8
Compare clear register 8
0x0FC8
TCDT8
Timer data register 8
0x0FCC
TCCSH8
TCCSL8
Reserved
Timer control register (Upper Bit) 8
Timer control register (Lower Bit) 8
0x0EB4
CPCLR9
Compare clear register 9
0x0EB8
TCDT9
Timer data register 9
0x0EBC
TCCSH9
TCCSL9
Reserved
Timer control register (Upper Bit) 9
Timer control register (Lower Bit) 9
0x0EF0
CPCLR10
Compare clear register 10
0x0EF4
TCDT10
Timer data register 10
0x0EF8
TCCSH10 TCCSL10
Reserved
Timer control register (Upper Bit) 10
Timer control register (Lower Bit) 10
Table 4-3 Registers Map of Free-run Timer Selector
Registers
Address
Register function
+0
+1
+2
+3
0x0070
Reserved
FRS8
Free-run timer selection register 8
0x0074
Reserved
FRS9
Free-run timer selection register 9
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Chapter 22: 32-Bit Free-Run Timer
4.1. Registers of the 32-bit Free-run Timer
The registers of the 32-bit free-run timer is shown.
4.1.1.
Timer Control Register (Upper Bit) : TCCSH
The bit configuration of the timer control register (Upper bit) is shown.
This register controls the operation of the free-run timer.
TCCSH3-10 (Free-run timer 3-10): Address Base_addr+08H (Access: Byte, Half-word,
Word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECKE
-
-
-
-
-
ICLR
ICRE
0
0
0
0
0
0
0
0
R/W
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R(RM1),W
R/W
[bit15] ECKE : Clock selection
ECKE
Count clock selection
0
Internal clock
1
External clock (FRCK)
When this bit is set to "0": Internal clock is selected. To select the count clock frequency, select the clock frequency
selection bits (CLK3 to CLK0:bit3 to bit0) of the TCCSL register.
When this bit is set to "1": External clock is selected. The external clock is input from the "FRCK" pin. Therefore,
enable external clock input by writing "0" to the bit of the port direction register (DDR) corresponding to the
FRCK input pin and writing "0" to the bit of the corresponding port function register (PFR) to switch to port input
state. If external clock is selected by the ECKE bit, clock count will detect both edges. Set the pulse width of the
external clock to 4/FPCLK or more.
Note:
Change for the count clock selection bit while other peripheral modules using the free-run timer output (output
compare and input capture) are inactive.
[bit14 to bit10] - : Undefined
The read value is always "0". Writing to these bits has no effect on operation.
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Chapter 22: 32-Bit Free-Run Timer
[bit9] ICLR : Compare clear interrupt flag
State
ICLR
Read
Write
0
No compare clear match
Clear the flag (ICLR)
1
Compare clear match
No effect on operation
This bit will be set to "1" when the compare clear value matches the 32-bit free-run timer value.
[bit8] ICRE : Compare clear interrupt request enabled
ICRE
Operation
0
Interrupt disabled
1
Interrupt enabled
When the ICRE bit and compare clear interrupt flag bit (ICLR) are set to "1", an interrupt request for CPU will be
generated.
4.1.2.
Timer Control Register (Lower Bit) : TCCSL
The bit configuration of timer control register (Lower bit) is shown.
This register controls the operation of the free-run timer.
TCCSL3-10 (Free-run timer 3-10): Address Base_addr+09H (Access: Byte, Half-word,
Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
STOP
-
SCLR
CLK3
CLK2
CLK1
CLK0
0
1
0
0
0
0
0
0
R0,WX
R/W
R0,WX
R0,W
R/W
R/W
R/W
R/W
[bit7] - : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit6] STOP : Timer enabled
STOP
Operation
0
Count enabled (operation)
1
Count disabled (stop)
The STOP bit is used to start/stop counting of the 32-bit free-run timer.
When the STOP bit is "0": Counter of the 32-bit free-run timer is started.
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Chapter 22: 32-Bit Free-Run Timer
When the STOP bit is "1": Counter of the 32-bit free-run timer is stopped.
Note:
If output compare is in use, the output compare operation will stop when the free-run timer stops.
[bit5] - : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit4] SCLR : Timer clear
State
SCLR
Read
Write
0
Writing "0" has no meaning.
The read value is always "0".
1
Clears the free-run timer.
When this bit is set to "1", the count value of the free-run timer is cleared to "00000000H". The prescaler within the
macro is also cleared at this time.
The value read out is always "0".
Note:
If you set this bit to "1", timer clear will be performed at the next internal clock timing.
[bit3 to bit0] CLK3 to CLK0 : Clock frequency selection (when internal clock is selected)
Clock frequency selection (FPCLK: Peripheral clock (PCLK))
CLK3
CLK2
CLK1
CLK0
0
0
0
0
0
0
Count
clock
FPCLK
=16MHz
FPCLK
=8MHz
FPCLK
=4MHz
FPCLK
=1MHz
0
1/FPCLK
62.5ns
125ns
0.25μs
1μs
0
1
2/FPCLK
125ns
0.25μs
0.5μs
2μs
0
1
0
4/FPCLK
0.25μs
0.5μs
1μs
4μs
0
0
1
1
8/FPCLK
0.5μs
1μs
2μs
8μs
0
1
0
0
16/FPCLK
1μs
2μs
4μs
16μs
0
1
0
1
32/FPCLK
2μs
4μs
8μs
32μs
0
1
1
0
64/FPCLK
4μs
8μs
16μs
64μs
0
1
1
1
128/FPCLK
8μs
16μs
32μs
128μs
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Clock frequency selection (FPCLK: Peripheral clock (PCLK))
CLK3
CLK2
CLK1
CLK0
1
0
0
0
Other settings prohibited
Count
clock
FPCLK
=16MHz
FPCLK
=8MHz
FPCLK
=4MHz
FPCLK
=1MHz
256/FPCLK
16μs
32μs
64μs
256μs
-
-
-
-
-
The frequency is changed at the same time as the setting change to the clock frequency selection bit. If internal
clock is selected as the count clock of the free-run timer (clock selection bit (ECKE= "0")), change the setting
while other peripheral modules (output compare and input capture) using the free-run timer output are inactive.
When the free-run timer is used as compare data for the output compare, the free-run timer clock frequency cannot
be set as CLK[3:0]= "0000B".
4.1.3.
Compare Clear Register : CPCLR
The bit configuration of the compare clear register is shown.
Compare clear register is a 32-bit register to be used for comparison with the free-run timer.
CPCLR3-10 (Free-run timer 3-10): Address Base_Addr+00H (Access: Word)
bit
31
0
CL[31:0]
Initial value
Attribute
1111
1111
1111
1111
1111
1111
1111
1111
R/W
[bit31 to bit0] CL[31:0] : Compare clear
The compare clear register is used for comparison with the count value of the 32-bit free-run timer. If the count
value of this register matches that of the free-run timer, the 32-bit free-run timer will be reset to "00000000H" and
an interrupt will be generated when the value set to this register matches the counter value. However, the value
needs to be written while the timer is inactive (the STOP bit of timer state control register lower (TCCSL) = "1").
Writing to this register during operation will have no meaning.
When accessing this register, use a word access instruction.
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Chapter 22: 32-Bit Free-Run Timer
4.1.4.
Timer Data Register : TCDT
The bit configuration of the timer data register is shown.
The timer data register reads the count value of the 32-bit free-run timer.
TCDT3-10 (Free-run timer 3-10): Address Base_addr+04H (Access: Word)
bit
31
0
T[31:0]
Initial value
Attribute
0000
0000
0000
0000
0000
0000
0000
0000
R,W
[bit31 to bit0] T[31:0] :
The count value of the 32-bit free-run timer can be read by reading the timer data register.
Timer value can be written to the free-run timer by writing to the timer data register. Always write to this register
while the free-run timer is inactive (timer control register lower (STOP of TCCSL = "1")).
When accessing this register, use a word access instruction.
The 32-bit free-run timer will be initialized as soon as any of the following occurs.
Reset
The Clear bit (SCLR = "1") of the timer state control register (TCCSL)
The timer count value matches the compare clear register
Writing to this register while it is in operation will have no meaning.
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Chapter 22: 32-Bit Free-Run Timer
4.2. Registers of the Free-run Timer Selector
The registers of the free-run timer selector is shown.
4.2.1.
Free-run Timer Selection Register : FRS
The bit configuration of the free-run timer selection register is shown.
This register controls the operation of the free-run timer.
FRS8: Address 0070H (Access: Byte, Half-word, Word)
Initial value
Attribute
Initial value
Attribute
Initial value
Attribute
Initial value
Attribute
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
-
OS133
OS131
OS130
-
OS122
OS121
OS120
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
-
OS112
OS111
OS110
-
OS102
OS101
OS100
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
OS92
OS91
OS90
-
OS82
OS81
OS80
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
OS72
OS71
OS70
-
OS62
OS61
OS60
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
[bit31] : Undefined
The read value is always "0". Writing to this bits has no effect on operation.
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[bit30, bit29, bit28] OS132, OS131, OS130 : Free-run timer selector for output compare 13
OS132
OS131
OS130
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 13.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit27] : Undefined
The read value is always "0". Writing to this bits has no effect on operation.
[bit26, bit25, bit24] OS122, OS121, OS120 : Free-run timer selector for output compare 12
OS122
OS121
OS120
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 12.
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Chapter 22: 32-Bit Free-Run Timer
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit23] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit22, bit21, bit20] OS112, OS111, OS110 : Free-run timer selector for output compare 11
OS112
OS111
OS110
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 11.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit19] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit18, bit17, bit16] OS102, OS101, OS100 : Free-run timer selector for output compare 10
748
OS102
OS101
OS100
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
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Chapter 22: 32-Bit Free-Run Timer
OS102
OS101
OS100
Function
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 10.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit15] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit14, bit13, bit12] OS92, OS91, OS90 : Free-run timer selector for output compare 9
OS92
OS91
OS90
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 9.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit11] : Undefined
The read value is always "0". Writing to this bits has no effect on operation.
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[bit10, bit9, bit8] OS82, OS81, OS80 : Free-run timer selector for output compare 8
OS82
OS81
OS80
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 8.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit7] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit6, bit5, bit4] OS72, OS71, OS70 : Free-run timer selector for output compare 7
OS72
OS71
OS70
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 7.
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Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit3] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit2, bit1, bit0] OS62, OS61, OS60 : Free-run timer selector for output compare 6
OS62
OS61
OS60
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the output compare 6.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
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FRS9: Address 0074H (Access: Byte, Half-word, Word)
Initial value
Attribute
Initial value
Attribute
Initial value
Attribute
Initial value
Attribute
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
-
IS112
IS111
IS110
-
IS102
IS101
IS100
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
-
IS92
IS91
IS90
-
IS82
IS81
IS80
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
IS72
IS71
IS70
-
IS62
IS61
IS60
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
IS52
IS51
IS50
-
IS42
IS41
IS40
0
0
0
0
0
0
0
0
R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
[bit31] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit30, bit29, bit28] IS112, IS111, IS110 : Free-run timer selector for input capture 11
752
IS112
IS111
IS110
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
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Chapter 22: 32-Bit Free-Run Timer
IS112
IS111
IS110
Function
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 11.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit27] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit26, bit25, bit24] IS102, IS101, IS100 : Free-run timer selector for input capture 10
IS102
IS101
IS100
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 10.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit23] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit22, bit21, bit20] IS92, IS91, IS90 : Free-run timer selector for input capture 9
IS92
IS91
IS90
Function
0
0
0
Free-run timer 3
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IS92
IS91
IS90
Function
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 9.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit19] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit18, bit17, bit16] IS82, IS81, IS80 : Free-run timer selector for input capture 8
IS92
IS81
IS80
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 8.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
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[bit15] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit14, bit13, bit12] IS72, IS71, IS70 : Free-run timer selector for input capture 7
IS72
IS71
IS70
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 7.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit11] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit10, bit9, bit8] IS62, IS61, IS60 : Free-run timer selector for input capture 6
IS62
IS61
IS60
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 6.
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Chapter 22: 32-Bit Free-Run Timer
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit7] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit6, bit5, bit4] IS52, IS51, IS50 : Free-run timer selector for input capture 5
IS52
IS51
IS50
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 5.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit3] : Undefined
The read value is always "0". Writing to this bit has no effect on operation.
[bit2, bit1, bit0] IS42, IS41, IS40 : Free-run timer selector for input capture 4
756
IS42
IS41
IS40
Function
0
0
0
Free-run timer 3
0
0
1
Free-run timer 4
0
1
0
Free-run timer 5
0
1
1
Free-run timer 6
1
0
0
Free-run timer 7
1
0
1
Free-run timer 8
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Chapter 22: 32-Bit Free-Run Timer
IS42
IS41
IS40
Function
1
1
0
Free-run timer 9
1
1
1
Free-run timer 10
These bits configure the free-run timer assigned to the input capture 4.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
5. Operation
This section explains the operations of the free-run timer.
5.1 Operation of the 32-bit Free-run Timer
5.2 Operation of the 32-bit Free-run Timer Selector
5.1. Operation of the 32-bit Free-run Timer
This section shows the operations of the 32-bit free-run timer.
5.1.1.
Count Operation
This section shows the count operation.
Ex ternal clock input
TCCSH.ECKE
Count clock
Coun v alue
t
The first edge immediately after ex ternal
clock selection is ignored
N
N+ 1
The free-run timer will be incremented based on the input clock (internal clock or external clock). If the external
clock mode (TCCSH.ECKE = 1) is selected, the free-run timer starts counting up by the rising and falling edges of
the external input clock.
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Chapter 22: 32-Bit Free-Run Timer
The first rising and falling edges of the external clock immediately after the selection of external clock mode will be
ignored. This means that the first falling edge will be ignored if the initial value of the external clock input is "1", and
the first rising edge will be ignored if the initial value is "0".
(Ex ternal clock FPCL K/ 2 )
(I nternal clock )
Ex ternal pin
(CKI )
Peripheral
clock (PCL K)
I nternal clock
Coun
(FPCL K/ 2 )
timing
Coun
timing
(7 )
Count of free-
run timer
Count of free-
run timer
(8 )
CPCLR
FFFF
Count of
free-run
timer
(3 )
(2 )
(5 )
Time
0 0000 00H
0
Reset
Compare clear match
interrupt req uest
Clearing
(1)
(4 )
(2 )
Clearing b y software Clearing b y software
(5 )
free-run timer
(1) Reset
(2) Clearing of the free-run timer by reset (Count value "0000_0000H")
(3) Count up operation by the free-run timer
(4) Compare clear match of the free-run timer and interrupt generation
(5) Clearing of the free-run timer by compare clear match (Count value "0000_0000 H")
(6) Repetition of step (3) to (5)
(7) The free-run timer counts up in the clock obtained by dividing the internal clock (count clock).
(8) The free-run timer counts up in the count clock obtained by synchronizing the external clock with the internal
clock.
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Chapter 22: 32-Bit Free-Run Timer
5.1.2.
Counting Up
This section shows counting up.
32-bit free-run timer is an up counter. The counter starts counting up from the timer data register (TCDT) configured
in advance. It continues to count up until the count value matches the value of the compare clear register (CPCLR).
The counter will then be cleared to "0000_0000H" and start counting up again.
Figure 5-1 Up Counter Operation
Count value
FFFFFFFF H
BFFFFFFF H
7FFFFFFF H
3FFFFFFF H
00000000 H
Time
Timer operation start
Compare clear match
Reset
Compare clear
register
5.1.3.
BFFFFFFF H
FFFFFFFF H
7FFFFFFF H
Timer Clear
This section shows timer clear.
The count value of the free-run timer will be cleared in any of the followings:
When there is a match with the compare clear register
When "1" is written to the SCLR bit of the TCCSL register while it is in operation
When "0000_0000H" is written to the TCDT register while it is in stop
When it has been reset.
The counter will be cleared as soon as it has been reset. When there is a match with the compare clear register, the
counter will be cleared in synchronization with the count timing.
Figure 5-2 Clear Timing of the Free-run Timer
Compare clear
register value
N
Compare match
Count value
N
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Chapter 22: 32-Bit Free-Run Timer
5.1.4.
Each Clear Operations of the Free-run Timer
This section shows each clear operations of the free-run timer.
Count of
free-run
timer
00000000 H
(1)
(2)
(3)
Time
(4)
Reset
“00000000 H” Write
Clear
Clearing by software
or compare match
Enable/disabl
operatio
(software)
Operation
stop
Operation stop
Timing of clearing by compare match
(Internal clock)
Peripheral
clock (PCLK)
Count timing
Count value N -1
N
Compare value
“00000000”
“00000001”
Compare value=N
Compare match
Clearing free-run timer
Interrupt request
Clearing of the free-run timer (4 types)
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Chapter 22: 32-Bit Free-Run Timer
(1) When it has been reset
(2) When "1" is written to SCLR: bit4 of the TCCSL register while it is in operation
(3) When there is a match with the compare clear register
(4) When "0000_0000H" is written to the TCDT register while it is in stop
5.1.5.
Timer Interrupt
This section shows timer interrupt.
For the free-run timer, you will be able to generate the following type of interrupt.
Compare clear interrupt
The compare clear interrupt will be generated when the timer value matches the value of the compare clear
register (CPCLR).
Figure 5-3 Interrupt
Count value
Compare clear interrupt
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Chapter 22: 32-Bit Free-Run Timer
5.2. Operation of the 32-bit Free-run Timer Selector
This section shows the operations of the 32-bit free-run timer selector.
32-bit free-run timer selector is used to set the free-run timer input of 32-bit output compare and 32-bit input capture.
This series consists of 32-bit free-run timer (8 channels), 32-bit output compare (8 channels) and 32-bit input capture
(8 channels). The free-run timer used in the register setting shown in the following tables can be selected.
Table 5-1 Table for Registers
Resource
Register
OCU6
OCU7
OCU8
OCU9
OCU10
OCU11
OCU12
OCU13
ICU4
ICU5
ICU6
ICU7
ICU8
ICU9
ICU10
ICU11
FRS8.OS6[2:0]
FRS8.OS7[2:0]
FRS8.OS8[2:0]
FRS8.OS9[2:0]
FRS8.OS10[2:0]
FRS8.OS11[2:0]
FRS8.OS12[2:0]
FRS8.OS13[2:0]
FRS9.IS4[2:0]
FRS9.IS5[2:0]
FRS9.IS6[2:0]
FRS9.IS7[2:0]
FRS9.IS8[2:0]
FRS9.IS9[2:0]
FRS9.IS10[2:0]
FRS9.IS11[2:0]
Remarks
32-bit output compare
32-bit input capture
Table 5-2 Table for Setting Values of Registers
Setting Value
Free-run Timer
000B
001 B
010 B
011 B
100B
101 B
110 B
111 B
FRT3 (Initial Value)
FRT4
FRT5
FRT6
FRT7
FRT8
FRT9
FRT10
Note:
Before configuring the free-run timer selection register, make sure to verify that the free-run timer is inactive.
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Chapter 22: 32-Bit Free-Run Timer
6. Setting
This section explains setting of the free-run timer.
Table 6-1 Settings Required for Using the Free-run Timer
Configuration
Register to be configured
Timer initialization condition setting
Count clock setting
Internal clock selection
External clock selection
See 7.4.
Timer control registers
(TCCSH3 to TCCSH10)
(TCCSL3 to TCCSL10)
Count operation start
For external clock,
set the clock input pins (FRCK) for input.
Setting
method
See 7.1.
See 7.2.
See 7.3.
Set the pins for peripheral input.
See "CHAPTER: I/O PORTS".
Table 6-2 Settings Required for Performing Free-run Timer Interrupt
Configuration
Register to be configured
Setting
method
Free-run timer interrupt vector,
Free-run timer interrupt level setting
See "CHAPTER: INTERRUPT
CONTROL".
See 7.5.
Free-run timer interrupt setting
Interrupt request clear
Interrupt request enable
Timer control registers
(TCCSH3 to TCCSH10)
See 7.6
Table 6-3 Settings Required for Stopping the Free-run Timer
Configuration
Register to be configured
Setting
method
Free-run timer stop bit setting
Timer control registers
(TCCSL3 to TCCSL10)
See 7.7.
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Chapter 22: 32-Bit Free-Run Timer
7. Q&A
This section explains Q&A of the free-run timer.
7.1 How to Select Internal Clock Dividers
7.2 How to Select the External Clock
7.3 How to Enable/Disable the Count Operation of the Free-run Timer
7.4 How to Clear the Free-run Timer
7.5 About Interrupt Related Registers
7.6 How to Enable Compare Clear Interrupt
7.7 How to Stop the Free-run Timer Operation
7.1. How to Select Internal Clock Dividers
This section shows how to select internal clock dividers.
There are nine types of internal clock dividers. You can configure it using the clock selection bits (TCCSHn.ECKE
[n=3 to 10]) and count clock bits (TCCSLn.CLK[3:0] [n=3 to 10]).
Configuration
Internal clock
764
Clock selection
bit (ECKE)
Count clock bits (CLK[3:0])
To select FPCLK
Set "0".
Set "0000".
To select 2/FPCLK
Set "0".
Set "0001".
To select 4/FPCLK
Set "0".
Set "0010".
To select 8/FPCLK
Set "0".
Set "0011".
To select 16/FPCLK
Set "0".
Set "0100".
To select 32/FPCLK
Set "0".
Set "0101".
To select 64/FPCLK
Set "0".
Set "0110".
To select 128/FPCLK
Set "0".
Set "0111".
To select 256/FPCLK
Set "0".
Set "1000".
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Chapter 22: 32-Bit Free-Run Timer
7.2. How to Select the External Clock
This section shows how to select the external clock.
You can configure it using the clock selection bits (TCCSHn.ECKE [n=3 to 10]), data direction bits and port function
bits.
To set to external
clock input
Configuration
Pin
Free-run timer 3
Set the FRCK3 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK3
Free-run timer 4
Set the FRCK4 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK4
Free-run timer 5
Set the FRCK5 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK5
Set the FRCK6 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK6
Set the FRCK7 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK7
Free-run timer 8
Set the FRCK8 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK8
Free-run timer 9
Set the FRCK9 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK9
Free-run timer 10
Set the FRCK10 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK1
0
Free-run timer 6
Free-run timer 7
Set the clock
selection bit
(ECKE) to "1".
Pulse width
(H width,
L width)
4/FPCLK
or higher
7.3. How to Enable/Disable the Count Operation of the Free-run
Timer
This section shows how to enable/disable the count operation of the free-run timer.
Set the count operation bits (TCCSLn.STOP [n=3 to 10]).
Operation
Count operation bit (STOP)
To operate the free-run timer
Set "0".
To stop the free-run timer
Set "1".
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Chapter 22: 32-Bit Free-Run Timer
7.4. How to Clear the Free-run Timer
This section shows how to clear the free-run timer.
You can clear the free-run timer using the following method.
Set using the clear bits (TCCSLn.SCLR [n=3 to 10]).
Operation
Clear bit (SCLR)
To clear the free-run timer
Write "1".
Perform a reset.
When a reset is performed (RSTX pin input, watchdog reset, software reset, etc.), the free-run timer will be cleared
to its initial state.
Write "0000_0000H" while the free-run timer is inactive.
If "0000_0000H" is written while the free-run timer is inactive, the count value will be "0000_0000H".
Overflow of the free-run timer will result in the count value returning to "0000_0000 H".
It will be cleared if there is a match with the compare clear register.
7.5. About Interrupt Related Registers
This section shows interrupt related registers.
Free-run timer interrupt vector and free-run timer interrupt level settings
The relationship between free-run timer numbers, interrupt levels and interrupt vectors is as shown in "4. Table of
Interrupt Vector" in "APPENDIX".
For details of the interrupt levels and interrupt vectors, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
766
Number
Interrupt vector (default)
Interrupt level setting bit (ICR[4:0])
Free-run timer 3
#51
Address: 0F_FF30H
Interrupt level register (ICR35)
Address: 0_0463H
Free-run timer 4
#50
Address: 0F_FF34H
Interrupt level register (ICR34)
Address: 0_0462H
Free-run timer 5
#51
Address: 0F_FF30H
Interrupt level register (ICR35)
Address: 0_0463H
Free-run timer 6
#50
Address: 0F_FF34H
Interrupt level register (ICR34)
Address: 0_0462H
Free-run timer 7
#51
Address: 0F_FF30H
Interrupt level register (ICR35)
Address: 0_0463H
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Chapter 22: 32-Bit Free-Run Timer
Number
Interrupt vector (default)
Interrupt level setting bit (ICR[4:0])
Free-run timer 8
#50
Address: 0F_FF34H
Interrupt level register (ICR34)
Address: 0_0462H
Free-run timer 9
#51
Address: 0F_FF30H
Interrupt level register (ICR35)
Address: 0_0463H
Free-run timer 10
#50
Address: 0F_FF34H
Interrupt level register (ICR34)
Address: 0_0462H
Since interrupt request flags (TCCSHn.ICLR [n=3 to 10]) will not be cleared automatically, clear the flags using
software before returning from interrupt processing. (Write "0" to the ICLR bit)
7.6. How to Enable Compare Clear Interrupt
This section shows how to enable compare clear interrupt.
Enable interrupt request, interrupt request flag
Interrupt enable setting can be performed using interrupt request enable bits (TCCSHn.ICRE [n=3 to 10]).
Operation
Compare clear interrupt request enable bit (ICRE)
Interrupt disabled
Set "0".
Interrupt enabled
Set "1".
Clearing of the interrupt request can be configured using interrupt flag bits (TCCSHn.ICLR [n=3 to 10]).
Operation
Compare clear interrupt flag bit (ICLR)
Interrupt request clear
Write "0".
7.7. How to Stop the Free-run Timer Operation
This section shows how to stop the free-run timer operation.
See "7.3. How to Enable/Disable the Count Operation of the Free-run Timer".
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Chapter 22: 32-Bit Free-Run Timer
8. Sample Program
This section explains sample program of the free-run timer.
Setting procedure example 1
Program example 1
Free-run timer 3, Clock=PCLK/2^6,
Count the number of compare matches using interrupt
processing.
void FREE_RUN_TIMER3_sample(void)
{
FREERUN3_initial();
FREERUN3_start();
}
< Initial setting>
-Free-run timer ch.3 control
Control register setting
Clock selection>>
void FREERUN3_initial(void)
{
IO_TCCS3.word = 0x0041; /* Setting value=0000_0000_0100_0001 */
/* bit15 = 0
ECKE internal clock source */
/* bit14 -10= 00000 Reserved bit */
/* bit9 = 0
ICLR compare interrupt request flag */
/* bit8 = 0
ICRE compare interrupt disabled */
/* bit7 = 0
Reserved bit */
/* bit6 = 1
STOP count disabled */
/* bit5 = 0
Reserved bit */
/* bit4 = 0
Initialization of SCLR free-run timer value
(no) */
/* bit3-0 = 0001
CLK3-0 Count clock PCLK/2=32MHz/2 */
Register name.Bit name
TCCSH3/TCCSL3
.ECKE
Compare interrupt request flag>>
Compare interrupt request
enabled>>
.ICLR
.ICRE
Counting Operation>>
.STOP
TCDT clear>>
Count clock>>
Timer data value setting
.CLR
.CLK3-0
TCDT3
-Interrupt-related
Register name.Bit name
Interrupt level setting
ICR35
I flag setting
(CCR)
-Variable setting
IO_TCDT3 = 0x0000;
/* Initialization of timer data value */
IO_ICR[35].byte = 0x10;
__EI();
count = 0;
/* Free-run timer 3 interrupt level setting (any value) */
/* Interrupt enabled */
}
-Free-run timer ch.3 activation
Count operation activation
Register name.Bit name
TCCSL3 .STOP
-Interrupt processing
Register name.Bit name
Clearing of interrupt request flag
TCCSH3.ICLR
(Any process)
Variable counting
void FREERUN3_start(void)
{
IO_TCCSL3.bit.STOP = 0; /* bit6 = 0 STOP count enabled */
}
__interrupt void
FREE_RUN_TIMER3_int(void)
{
IO_TCCSH3.bit.ICLR = 0; /* bit9 = 0 Clearing of ICLR compare match flag */
count++;
}
Vector table setting
Specification of interrupt routine required in vector table
#pragma intvect FREE_RUN_TIMER3_int 50
Note:
Clock-related settings and the setting of __set_il (numeric
value) need to be configured in advance. See "CHAPTER:
CLOCK" and "CHAPTER: INTERRUPT CONTROL
(INTERRUPT CONTROLLER)"
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Chapter 22: 32-Bit Free-Run Timer
9. Notes
This section explains notes of the free-run timer.
Clear Timing of the Free-run Timer
When a reset is performed (RSTX pin input, watchdog reset, software reset, etc.), the counter will stop counting
after initializing to "0000_0000H".
A software clear (TCCSL.SCLR=1) clears the counter in the following cycle when a clear request is generated.
However, in the case of compare match, the counter is cleared in the same timing as the counting up.
Counter clear operation (software, compare match) will only be enabled while the free-run timer is in operation. To
clear the counter while the free-run timer is in stop, you need to write "0000_0000 H" to the timer count data
register.
Writing to the timer data register
Always write a value to the free-run timer while the free-run timer is inactive (STOP = "1"), using a word access
instruction.
External clock operation
The timings of the compare match output and generation of interrupt of the external clock will be the next count clock
timing after the compare match. Therefore, in order to the generate compare match output and interrupt, 1 clock
(external clock) must at least be input after the compare match.
Read-modify-write
Compare clear interrupt flag bits of the timer control register are "1" when read using a read-modify-write instruction.
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Chapter 23: 32-Bit Output Compare
This chapter explains the 32-bit output compare.
1.
Overview
2.
Features
3.
Configuration Diagram
4.
Registers
5.
Operation
6.
Setting
7.
Q&A
8.
Sample Program
9.
Notes
Code : BIP009-1v1-91528-3-E
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Chapter 23: 32-Bit Output Compare
1. Overview
This section explains the overview of the 32-bit output compare.
The output compare consists of a 32-bit compare register, a compare output latch, a compare control register, and an
output control register. When the 32-bit free-run timer value matches the compare register value, the output level is
inverted or the H/L level is output and an interrupt also can be generated.
Figure 1-1 Block Diagram (Overview)
Free-run timer value
Output compare 6
OCU6
Comp
Latch
Toggle
OCU7 Output
Comp
Latch
Output compare 7
Same as ch.8 to ch.13
Interrupts
The numbers of available external output pins are shown below.
MB91F52xR (144pin) : 6
MB91F52xU (176pin) : 6
MB91F52xM (208pin) : 8
MB91F52xY (416pin) : 8
2. Features
This section explains the features of the 32-bit output compare.
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Chapter 23: 32-Bit Output Compare
Figure 2-1 Output Waveform
Toggled output 2 channels
T1 or T(max.)
T1
(OCU6 pin)
(OCU7 pin)
T2
PWM output 1 channel
(OCU7)
T2
T1
13
Same as ch.8 to ch.11
Figure 2-2 Output Level specification Waveform
Count value
FFFFFFFF
H
BFFFFFFF
H
7FFFFFFF
H
3FFFFFFF
H
00000000 H
time
Reset
Compare register 6
BFFFFFFFH
Compare register 7
7FFFFFFFH
External pin OCU 6
External pin OCU 7
Compare 6 interrupt
Compare 7 interrupt
Reverse or level
specification output
Level specification
772
Reverse
Initial value L
Level specification
When compare match, the output level is made "H"
When compare match,
the output level is made "L".
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Chapter 23: 32-Bit Output Compare
Type : 32-bit compare register × 4 + compare circuit
Corresponding timer : Free-run timer is used
Number of units 8 channels
Operation by compare match
Pin output value invert (toggle output) or signal output of H/L level specified
Interrupt occurrence
Count accuracy : Peripheral clock (PCLK/2, PCLK/4, PCLK/8, PCLK/16, PCLK/32, PCLK/64, PCLK/128,
PCLK/256) (Dependent on the free-run timer)
Note:
The setting of the peripheral clock (PCLK) divided by 1 is prohibited.
Toggle change width (T): 1 × count accuracy to 100000000H × count accuracy
Interrupt : Compare match interrupt
Others :
Output level initial value setting is enabled. ("H"/"L")
Unused pins as OCU output can be used as general-purpose ports.
6 compare registers can be used for independence.
Output pins and interrupt flags correspond to the compare register.
Output pins can be inverted with the use of two compare registers. (Function only for OCU7, 9, 11 and 13)
The initial value of each output pin can be set.
When the output compare register matches the 32-bit free-run timer, an interrupt can be generated.
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Chapter 23: 32-Bit Output Compare
3. Configuration Diagram
This section explains the configuration diagram of the 32-bit output compare.
Figure 3-1 Configuration Diagram (Detail)
CH6
Compare register 6
OCCP6
OMS6
compare
OLS6
from 32-bit free-run timer
-
Level
Control
circuit
IOE6
External pin
OCU6
OCU6
interrupt
IOP6
OMS7
CH7
OLS7
Compare register
OCCP7
compare
CMOD
from 32-bit free-run timer
-
Level
Control
circuit
External pin
OCU7
IOE
Same as ch.8 to ch.11
13
774
IOP
OCU7
interrupt
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Chapter 23: 32-Bit Output Compare
4. Registers
This section explains the registers of the 32-bit output compare.
Table 4-1 Table of Base_addr and External Pins
External pin (OCU output)
Channel
Base_addr
MB91F52xR
NB91F52xU
MB91F52xM
MB91F52xY
6
0x0120
OCU6_0/OCU6_1
OCU6_0/OCU6_1
7
0x0120
OCU7_0/OCU7_1
OCU7_0/OCU7_1
8
0x012C
OCU8_0/OCU8_1
OCU8_0/OCU8_1
9
0x012C
OCU9_0/OCU9_1
OCU9_0/OCU9_1
10
0x0F90
OCU10_0/OCU10_1
OCU10_0/OCU10_1
11
0x0F90
OCU11_0/OCU11_1
OCU11_0/OCU11_1
12
0x0138
−
OCU12_0
13
0x0138
−
OCU13_0
Table 4-2 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
0x0120
OCCP6
Compare register 6
0x0124
OCCP7
Compare register 7
0x0128
Reserved
Reserved
OCSH67
OCSL67
Output control register 67 upper
Output control register 67 lower
0x012C
OCCP8
Compare register 8
0x0130
OCCP9
Compare register 9
0x0134
Reserved
Reserved
OCSH89
OCSL89
Output control register 89 upper
Output control register 89 lower
0x0F90
OCCP10
Compare register 10
0x0F94
OCCP11
Compare register 11
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Chapter 23: 32-Bit Output Compare
Registers
Address
Register function
+0
0x0F98
Reserved
+1
+2
+3
Reserved OCSH1011 OCSL1011
Output control register 1011 upper
Output control register 1011 lower
0x0138
OCCP12
Compare register 12
0x013C
OCCP13
Compare register 13
0x0078
Reserved
OCLS67
Output level control register 67
0x007C
Reserved
OCLS89
Output level control register 89
0x0F9C
Reserved
OCLS1011 Output level control register 1011
0x0F3C
Reserved
OCLS1213 Output level control register 1213
4.1.
Output Control Register (Upper Bit) : OCSH
The bit configuration of the output control register (Upper bit) is shown below.
Compare control register (OCSH) controls compare output (OCU pin) level, output enable, output level invert mode, compare
operation enable, compare match interrupt enable, and compare match interrupt flag.
This register is to control operations of the output compare.
x: Channel number 6, 8, 10, and 12.
y: Channel number 7, 9, 11, and 13.
OCSHxy (Output compare xy): Address Base_addr+0AH (Access: Byte, Half-word,
Word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
-
-
-
CMOD
-
-
-
0
0
R1,WX
R1,WX
R1,WX
R/W
R,W0
bit10
bit9
bit8
OTDy
OTDx
0
0
0
R,W0
R,W
R,W
Reserved Reserved
[bit15 to bit13] : Undefined
Writing to these bits has no effect on operation.
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Chapter 23: 32-Bit Output Compare
[bit12] CMOD : Output level switch mode
CMOD
Operating mode
0
Independent operation (OCU6 to OCU13 pins output level invert operation is independent.)
OCU6, 8, 10, 12 pins: When the free-run timer value corresponds to the compare register 6, 8, 10,
12 (OCCP6, 8, 10, 12) value, the output is inverted.
OCU7, 9, 11, 13 pins: When the free-run timer value corresponds to the compare register 7, 9, 11,
13 (OCCP7, 9, 11, 13) value, the output is inverted.
The comparison target free-run timer is selected by FRS8 register.
1
Coordinated operation
OCU6, 8, 10, 12 pins: When the free-run timer value corresponds to the compare register 6, 8, 10,
12 (OCCP6, 8, 10, 12), the output is inverted.
OCU7, 9, 11, 13 pins: When the free-run timer value corresponds to either the compare register (6
or 7), (8 or 9), (10 or 11), (12 or 13), the output is inverted.
The comparison target free-run timer is selected by FRS8 register.
When the compare register 6 and 7 have the same value, the operation is the same one as when only one compare
register is used. Same as the compare register 8 to 13.
[bit11, bit10] : Reserved
The read value is always "0".
Write "0" to these bits.
[bit9] OTD : Pin level setting (Output compare y)
[bit8] OTD : Pin level setting (Output compare x)
This bit specifies the pin output level (initial value) when OCU pins output is enabled.
Operation
OTD
Read
0
OCU pins output level (initial value) is set to "L".
OCU pins output
1
Write
OCU pins output level (initial value) is set to
"H".
When OCU pins output is performed, the setting of a general-purpose port is required.
Writing to these bits is enabled when the compare operation is stopped (OCSL.CSTx or CSTy="0"). The setting
should be performed after the compare operation is stopped.
With the reading operation, the output compare pin output is read.
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4.2.
Output Control Register (Lower Bit) : OCSL
The bit configuration of the output control register (Lower bit) is shown below.
Compare control register (OCSL) controls compare output (OCU pin) level, output enable, output level invert mode,
compare operation enable, compare match interrupt enable, and compare match interrupt flag.
This register is to control operations of the output compare.
x: Channel number 6, 8, 10, and 12.
y: Channel number 7, 9, 11, and 13.
OCSLxy (Output compare xy): Address Base_addr+0x0BH (Access: Byte, Half-word,
Word)
Initial value
bit7
bit6
bit5
bit4
IOPy
IOPx
IOEy
IOEx
0
0
0
0
1
R/W
R/W
R1,W1
Attribute R(RM1),W R(RM1),W
bit3
bit2
bit1
bit0
CSTy
CSTx
1
0
0
R1,W1
R/W
R/W
Reserved Reserved
[bit7] IOP : Interrupt request flag (output compare y)
[bit6] IOP : Interrupt request flag (output compare x)
State
IOP
Read
Write
0
No compare match interrupt occurs for
the compare register.
Flag (IOP) is cleared.
1
Compare match interrupt occurs for the
compare register.
No effect on operations
This bit is an interrupt flag that indicates whether the value of the compare register matched that of the free-run
timer.
This bit becomes "1" when the count value of free-run timer (TCDT) corresponds to the output compare compare
register (OCCP).
The interrupt request becomes enabled when the interrupt enable bit (IOE) is "1".
If a read-modify-write (RMW) instruction is executed, "1" is always read.
[bit5] IOE : Interrupt request enable (Output compare y)
[bit4] IOE : Interrupt request enable (Output compare x)
IOE
778
State
0
Output compare interrupt request is disabled.
1
Output compare interrupt request is enabled.
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This bit enables the output compare interrupt for the compare register.
While "1" is written to this bit, if the compare match interrupt flag bit (IOP) is set, the output compare interrupt is
generated.
[bit3, bit2] Reserved
The read value is always "1".
Write "1" to these bits.
[bit1] CST : Operation enable (Output compare y)
[bit0] CST : Operation enable (Output compare x)
CST
Operation
0
Operation of the output compares is stopped.
1
Operation of the output compares is enabled.
This bit enables the compare operation for the count value of free-run timer (TCDT) and the output compare
compare register.
The compare registers (OCCP) must be set with values before the compare operation is enabled
Because the output compare is synchronized with the free-run timer, when the free-run timer is stopped, the output
compare operation is also stopped.
4.3.
Compare Register : OCCP
The bit configuration of the compare register is shown below.
These registers set the values to be compared with the 32-bit free-run timer count value.
x: Channel number 6, 8, 10, and 12.
y: Channel number 7, 9, 11, and 13.
OCCPx (Output compare x): Address Base_addr+00H (Access: Word)
OCCPy (Output compare y): Address Base_addr+04H (Access: Word)
bit31
32Bit
bit0
OP[31:0]
Initial value
Attribute
0000
0000
0000
0000
0000
0000
0000
0000
R/W
The compare registers OCCP is compared with the count value of free-run timer (TCDT).
When the OCCP register values correspond to the 32-bit free-run timer value, a compare signal is generated and an
output compare interrupt flag is set. The compare value is reflected after the write instruction is completed.
Therefore, the compare value change during operation might generate an interrupt twice per one free-run counting
if the newly written compare value is larger than the previous compare value.
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In addition, when the corresponding OCU of the port function register (PFR) is set and output is enabled, the
output level corresponding to the compare register is changed.
For access to this register, use a word access instruction.
4.4.
Output Level Control Register : OCLS
The bit configuration of the output level control register is shown below.
This register controls compare output (OUT pin) operation mode and compare output level.
x: Channel number 6, 8, 10, and 12
y: Channel number 7, 9, 11, and 13
OCLS67 (Output compare 67): Address 007BH (Access: Byte, Half-word, Word)
OCLS89 (Output compare 89): Address 007FH (Access: Byte, Half-word, Word)
OCLS1011 (Output compare 1011): Address 0F9FH (Access: Byte, Half-word, Word)
OCLS1213 (Output compare 1213): Address 0F3FH (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
OLSy
OLSx
OMSy
OMSx
X
X
X
X
0
0
0
0
RX,WX
RX,WX
RX,WX
RX,WX
R/W
R/W
R/W
R/W
Initial value
Attribute
[bit7 to bit4] : Undefined
The read value is undefined. Writing has no effect on operation.
[bit3] OLS : Output level specification (Output compare y)
[bit2] OLS : Output level specification (Output compare x)
OLS
Operation
0
When compare match, the output level is made "L".
1
When compare match, the output level is made "H".
This bit specifies the pin output level of the compare register.
When output mode selection bit(OMS) is "1", the pin output outputs the level specified by this bit when the
free-run timer is corresponding to the compare register.
When output mode selection bit(OMS) is "0", the pin output is inverted regardless of this bit value.
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[bit1] OMS : Output mode selection (Output compare y)
[bit0] OMS : Output mode selection (Output compare x)
OMS
Operation
0
When compare match, the output level is reversed.
1
When compare match, the level specified by output level specification bit(OLS) is
output.
This bit specifies the operation of the output pin when the free-run timer is corresponding to the compare register.
5. Operation
This section explains the operations of the 32-bit output compare.
5.1 Output Compare Output (Independent Invert) CMOD = "0"
5.2 Output Compare Output (Coordinated Invert) CMOD = "1"
5.3 Output Compare Operation Timing
5.1.
Output Compare Output (Independent Invert) CMOD = "0"
This section shows the output compare output (independent invert) CMOD="0".
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Peripheral clock
(CLKP)
(PCLK)
Compare
register value
Compare
match signal
OP pin output
Interrupt
request
(1) A compare value is set.
(2) Compare operation is enabled (CST = "1")
(3) Free-run timer count up (example of one count per four clocks)
(4) A free-run timer value is compared with a compare value and they match (Compare match)
(5) OCU output level is inverted.
(6) A compare match interrupt request is generated.
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5.2.
Output Compare Output (Coordinated Invert) CMOD = "1"
This section shows the output compare output (coordinated invert) CMOD="1".
Compare register 6
Compare register 7
OST6
OST7
OCU6 output
CMOD="0"
OCU7 output
OCU6 output
CMOD="1"
OCU7 output
Interrupt request 6
Interrupt request 7
(1) Values of Compare 6 and Compare 7 are set.
(2) Compare operation is enabled.
(3) Free-run timer count up
(4) Compare 7 match
(5) OCU7 output level is inverted.
(6) Compare 7 match interrupt
(7) Free-run timer count up
(8) Compare 6 match
(9) OCU6 output level is inverted.
When CMOD = "1", OCU7 output level is also inverted.
(10) Compare 6 match interrupt
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5.3.
Output Compare Operation Timing
This section shows the output compare operation timing.
With the use of two pairs of compare registers, the output level can be changed. (For CMOD = "1")
The output compare can invert the output as well as generate an interrupt when the free-run timer value matches the
specified compare register value and a compare match signal is generated. The output invert timing on compare
match is synchronized with the counter count timing.
5.3.1.
Compare Register Write
Compare register write is shown below.
The compare operation with the counter value is not performed on compare register rewrite.
Figure 5-1 Compare Register Write Timing
N
Counter value
N+1
N+2
N+3
A match signal is not generated
Compare
clear
register
Compare
register
6 value
0 value
M
N+1
Compare register 0
Compare
write register 6 write
Compare
clear
register
Compare
register
7 value
1 value
L
N+3
Compare register 1
Compare
write register 7 write
Compare 0
Compare
6 stop
stop
784
Compare
Compare17stop
stop
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5.3.2.
Compare Match, Interrupt
Compare match, interrupt are shown below.
Figure 5-2 Compare match, Interrupt Timing
5.3.3.
Pin Output
This section shows the pin output.
Figure 5-3 Pin Output Timing
Counter value
Value of
Compare register
Compare match
Pin output
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6. Setting
This section explains settings of the 32-bit output compare.
Table 6-1 Configuration Necessary for Use of Output Compare
Configuration
Register to be configured
Setting of the free-run timer
See "CHAPTER: 32-BIT FREE-RUN
TIMER".
Setting of the compare value
Compare register: (OCCPx)
Setting of the compare mode
Compare operation stop
Setting
Method
See 7.1.
See 7.2.
Output control register (OCSHxx, OCSLxx)
Setting of the compare pin output initial level
See 7.3.
See 7.4.
Setting of OCU6, OCU7 pins to output
Set each pin for peripheral output.
See "CHAPTER: I/O PORTS", for the setting method.
The free-run timer clear
Timer control register (TCCSL)
See "CHAPTER: 32-BIT FREE-RUN
TIMER ".
See 7.6.
Compare operation enable (activation)
Output control register (OCSLxx)
See 7.7.
Operation mode selection
Output level control register (OCLS)
See 7.12.
Table 6-2 Items Necessary for Interrupt Execution
Configuration
Register to be configured
Setting
Method
Setting of output compare interrupt vector
and output compare interrupt level
See "CHAPTER: INTERRUPT CONTROL
(INTERRUPT CONTROLLER)".
See 7.8.
Setting of output compare interrupt
Interrupt request clear
Interrupt request enable
Output control register (OCSHxx, OCSLxx)
See 7.10.
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7. Q&A
This section explains Q&A of the 32-bit output compare.
7.1 How to Set the Compare Value
7.2 How to Set the Compare Mode (Example with OCU7)
7.3 How to Enable/Disable the Compare Operation (Example with OCU6, 7)
7.4 How to Set the Compare Pin Output Initial Level (Example with OCU6, 7)
7.5 How to Set the Compare Pin OCU6-OCU7 for Output
7.6 How to Clear the Free-run Timer
7.7 How to Enable the Compare Operation (Example with OCU6, 7)
7.8 Interrupt Related Register
7.9 Interrupt Type
7.10 How to Enable the Interrupt
7.11 Calculation Method for the Compare Value
7.12 How to Set the Operation Mode
7.1.
How to Set the Compare Value
This section shows how to set the compare value.
Write the compare value to the compare register OCCPx.
7.2.
How to Set the Compare Mode (Example with OCU7)
This section shows how to set the compare mode.
Set with the compare mode bit (OCSH67.CMOD)
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Operation
Compare mode bit
To invert the OCU7 pin output when the free-run timer value matches the
compare register 7 (OCCP7)
Set (OCSH67.CMOD) to "0".
To invert the OCU7 pin output when the free-run timer value matches either
the compare register 6 (OCCP6) or the compare register 7 (OCCP7)
Set (OCSH67.CMOD) to "1".
Regardless of the CMOD bit, the operation is as follows:
Regardless of the compare mode bit (OCSH67.CMOD) setting, the OCU6 output is inverted when the free-run timer
value matches the compare register 6 (OCCP6).
7.3.
How to Enable/Disable the Compare Operation (Example
with OCU6, 7)
This section shows how to enable/disable the compare operation.
Set the compare operation enable bit (OCSL67.CST6), (OCSL67.CST7).
Operation
Compare
Compare operation enable bit
Compare 6
Set (OCSL67.CST6) to "0".
Compare 7
Set (OCSL67.CST7) to "0".
Compare 6
Set (OCSL67.CST6) to "1".
Compare 7
Set (OCSL67.CST7) to "1".
To stop (disable) the compare operation
To enable the compare operation
7.4.
How to Set the Compare Pin Output Initial Level (Example
with OCU6, 7)
This section shows how to set the compare pin output initial level.
Set the compare pin output specification bit (OCSH67.OTD6), (OCSH67.OTD7).
Operation
Compare pin output specification bit
To set the compare 6 pin to "L"
Set (OCSH67.OTD6) to "0".
To set the compare 6 pin to "H"
Set (OCSH67.OTD6) to "1".
To set the compare 7 pin to "L"
Set (OCSH67.OTD7) to "0".
To set the compare 7 pin to "H"
Set (OCSH67.OTD7) to "1".
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7.5.
How to Set the Compare Pin OCU6-OCU7 for Output
This section shows how to set the compare pin OCU6-OCU7 for output.
Set the pin for peripheral output. For setting method, see "CHAPTER: I/O PORTS".
7.6.
How to Clear the Free-run Timer
This section shows how to clear the free-run timer.
Set the clear bit (TCCSL.SCLR) of the free-run timer used.
Operation
Clear bit (SCLR)
To clear the free-run timer
Write "1".
For other methods, see "CHAPTER: 32-BIT FREE-RUN TIMER".
7.7.
How to Enable the Compare Operation (Example with
OCU6, 7)
This section explains how to enable the compare operation.
Set the compare operation enable bit (OCSL67.CST6, OCSL67.CST7).
See "7.3 How to Enable/Disable the Compare Operation (Example with OCU6, 7)".
7.8.
Interrupt Related Register
This section shows the interrupt related register.
Both the output compare interrupt vector and the output compare interrupt level are set.
The relation among the output compare channel, interrupt level, and interrupt vector is shown in the table below:
For the interrupt level and interrupt vector, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
Channel
Interrupt Vector (Default)
Interrupt Level Setting Bit (ICR[4:0])
Output compare #58
6/7/10/11
Address: 0FFF14H
Interrupt level register (ICR42)
Address: 0046AH
Output compare #59
8/9/12/13
Address: 0FFF10H
Interrupt level register (ICR43)
Address: 0046BH
The interrupt request flag (OCSLxy.IOPx, OCSLxy.IOPy x=6, 8, 10, 12 y=7, 9, 11, 13) are not cleared automatically.
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Before recovering from the interrupt process, write "0" to each bit to clear with software.
7.9.
Interrupt Type
This section shows the interrupt type.
The interrupt has one type only. It is generated by a compare match.
7.10. How to Enable the Interrupt
This section shows how to enable the interrupt.
Configure the interrupt request enable bit (OCSLxy.IOEx, OCSLxy.IOEy x=6, 8, 10, 12 y=7, 9, 11, 13) for the
interrupt enable setting.
Operation
Interrupt request enable bit
(OCSLxy.IOEx, OCSLxy.IOEy x=6, 8, 10, 12 y=7, 9, 11, 13)
To disable interrupt
Set "0".
To enable input
Set "1".
Set the interrupt request flag bit (OCSLxy.IOPx, OCSLxy.IOPy x=6, 8, 10, 12 y=7, 9, 11, 13) for the interrupt request
clear.
Operation
To clear interrupt request
Interrupt request flag bit
(OCSLxy.IOPx, OCSLxy.IOPy x=6, 8, 10, 12 y=7, 9, 11, 13)
Write "0".
7.11. Calculation Method for the Compare Value
This section shows the calculation method for the compare value.
7.11.1. Toggle Output Pulse
This section shows the toggle output pulse.
(Example) To calculate a two-phase pulse with OCU6, 7, cycle A, and one-fourth phase difference
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A
A/2
OCU0
OCU6
OCU1
OCU7
Formula:
Set as follows.
Set Free-run Timer Compare Clear Value = (A/2)-1
Compare Register 6 value = (A/2x3/4)-1
Compare Register 7 value = (A/2x1/4)-1
OCSH67.CMOD = 0
7.11.2. PWM Output
This section shows the PWM output.
(Example) To calculate the PWM with OCU6, 7, cycle A, and duty 1/4
A
A/2
OCU7
OCU1
Formula:
Set as follows.
Set Free-run Timer Compare Clear Value = (A/2)-1
Compare Register 6 value = (A/2x1/2)-1
Compare Register 7 value = (A/2x1/4)-1
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OCSH67.CMOD = 1
7.12. How to Set the Operation Mode
This section shows how to set operation mode.
Use the OMS bit to specify the operation of the output pin when the free-run timer is corresponding to the compare
register.
OCLS.OMS=0 : compare match, the output level is reversed.
OCLS.OMS=1 : compare match, the level specified by output level specification bit (OLS) is output.
8. Sample Program
This section explains a sample program for 32-bit output compare.
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Configuration procedure example 1
Program example 1
.2 channels independent output
Compare operation (7FFF, BFFF)
Compare not cleared for interrupt occurrence
void OUTPUT67_sample(void)
{
freerun4_initial();
OUTPUT67_initial();
OUTPUT67_start();
freerun4_start();
}
1. Initial setting
- Free-run timer ch.4 control
void freerun4_initial(void)
{
IO_TCCS4.word = 0x0041;
Register name.bit name
Setting of control register
Clock selection>>
TCCSH4, TCCSL4
.ECKE
Compare interrupt request flag>>
Compare interrupt request
enable>>
.ICLR
.ICRE
.STOP
Counting Operation>>
TCDT clear>>
Count clock>>
Setting of the timer data value
- Port
Port OCU6 output setting
Port OCU7 output setting
- Output compare control
Free-run timer selection
Setting of control register
.SCLR
.CLK3-0
}
TCDT4
Register name.bit name
See "CHAPTER: I/O
PORTS"
.CMOD
Pin output level specification>>
Interrupt request flag>>
Interrupt request enable>>
.OTD7, OTD6
.IOP7, IOP6
.IOE7, IOE6
2. Activation
- Output compare activation
Interrupt control
Compare operation activation
- Free-run timer ch.4 activation
Counting operation activation
3. Interrupt
- Interrupt process
Clearing of interrupt request flag
.CST7, CST6
OCCP6
OCCP7
Register name.bit name
ICR42
(CCR)
Register name.bit name
OCSL67.IOE7
OCSL67.IOE6
OCSL67.CST7
OCSL67.CST6
Register name.bit name
TCCSL4.STOP
Register name.bit name
OCSL67.IOP6
(any process)
......
Clearing of interrupt request flag
(any process)
......
void OUTPUT67_initial(void)
{
PORT_SETTING_OCU6_OUT(); /* Set the OCU6 pin for peripheral input. */
PORT_SETTING_OCU7_OUT(); /* Set the OCU7 pin for peripheral input. */
IO_OCFS67.hword = 0x0003;
IO_OCS67.hword = 0xEC0C;
Register name.bit name
OCFS67
OCSH67, OCSL67
Pin output level invert operation>>
Operation enable setting>>
Setting of compare value ch.6
Setting of compare value ch.7
- Interrupt relation
Setting of an interrupt level.
Setting of I flag
IO_TCDT4 = 0x0000;
/* Setting value =0000_0000_0100_0001 */
/* bit15 = 0
ECKE internal clock source */
/* bit14 -10 =0 Reserved Bit */
/* bit9 = 0
ICLR interrupt flag clear */
/* bit8 = 0
ICLR interrupt disable */
/* bit7 = 0
Reserved Bit */
/* bit6 = 1
STOP Counting disable */
/* bit5 = 0
Reserved Bit */
/* bit4 = 0
SCLR free-run timer value (no) initialization */
/* bit3-0 = 0001 CLK3-0 count clock PCLK/2=32MHz/2 */
/* Timer data value initialization */
OCSL67.IOP7
IO_OCCP6 = BFFF
IO_OCCP7 = 7FFF
/* Select the free-run timer 4. */
/* Setting value =1110_1100_0000_1100 */
/* bit15-13 = 111 Undefined bit*/
/* bit12 = 0
CMOD ch.6, ch.7 level invert */
/* bit11-10 = 11
Undefined bit*/
/* bit9-8 = 00
OTD7, OTD6 Compare pin output L */
/* bit7-6 = 00
IOP7, IOP6 Output compare no match */
/* bit5-4 = 00
IOE7, IOE6 Output compare interrupt disable */
/* bit3-2 = 11
Undefined bit*/
/* bit1-0 = 00
CST7, CST6 Compare operation disable */
/* Setting of compare register ch.6 */
/* Setting of compare register ch.7 */
IO_ICR[42].byte = 0x10;
_EI();
/* Output compare ch.6, ch.7 interrupt level setting (any value) */
/* Interrupt enable */
}
void OUTPUT67_start(void)
{
IO_OCS67.hword = 0xEC3C;
IO_OCS67.hword = 0xEC3F;
}
void freerun4_start(void)
{
IO_TCCSL4.bit.STOP = 0;
}
__interrupt void INPUT67_int(void)
{
IO_OCSL67.byte & = 0xBF;
……
}
__interrupt void INPUT67_int(void)
{
IO_OCSL67.byte & = 0x7F;
……
}
/* bit5-4 = 11 IOE7, IOE6 Output compare interrupt enable */
/* bit1-0 = 11 CST7, CST6 Compare operation enable */
/* bit4 = 0 STOP Counting enable */
/* bit6 = 0 IOP6 Clearing of interrupt flag */
/* bit7 = 0 IOP7 Clearing of interrupt flag */
Interrupt routine specification with the vector table is required.
#pragma intvect OUTPUT6_int 58
4. Interrupt vector
- Setting of the vector table
Note:
Clock-related setting and setting of __set_il(numerical value) in advance
are required. See "CHAPTER: CLOCK" and "CHAPTER: INTERRUPT
CONTROL (INTERRUPT CONTROLLER)".
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Configuration procedure example 2
Program example 2
.Compare for two pairs
Output of ch.4
Compare operation (7FFF, BFFF)
Compare is cleared with a cycle of a larger compare value.
Interrupt occurrence
void OUTPUT67_sample(void)
{
freerun4_initial();
OUTPUT67_initial();
OUTPUT67_start();
freerun4_start();
}
1. Initial setting
- Free-run timer ch.4 control
Setting of control register
Clock selection>>
Compare interrupt request flag>>
Compare interrupt request
enable>>
Register name.bit name
TCCSH4, TCCSL4
.ECKE
void freerun4_initial(void)
{
IO_TCCS4.word = 0x0041;
.ICLR
.ICRE
.STOP
Counting Operation>>
TCDT clear>>
Count clock>>
Setting of the timer data value
- Port
Port OCU7 output setting
- Output compare control
Free-run timer selection
Setting of control register
.SCLR
.CLK3-0
IO_TCDT4 = 0x0000;
TCDT4
Register name.bit name
See "CHAPTER: I/O
PORTS ".
Register name.bit name
OCFS67
OCSH67, OCSL67
Pin output level invert operation>>
.CMOD
Pin output level specification>>
Interrupt request flag>>
Interrupt request enable>>
.OTD7, OTD6
.IOP7, IOP6
.IOE7, IOE6
Operation enable setting>>
Setting of the compare value ch.6
Setting of the compare value ch.7
- Interrupt relation
Setting of an interrupt level.
Setting of I flag
2. Activation
- Output compare activation
Interrupt control
Compare operation activation
- Free-run timer ch.4 activation
Counting operation activation
3. Interrupt
- Interrupt process
Clearing of interrupt request flag
}
void OUTPUT67_initial(void)
{
PORT_SETTING_OCU7_OUT(); /* Set the OCU7 pin for peripheral input. */
IO_OCFS67.hword = 0x0003;
IO_OCS67.hword = 0xEC0C;
.CST7, CST6
OCCP6
OCCP7
Register name.bit name
ICR42
ICR43
(CCR)
Register name.bit name
OCSL67.IOE7
OCSL67.IOE6
OCSL67.CST7
OCSL67.CST6
Register name.bit name
TCCSL4.STOP
Register name.bit name
OCSL67.IOP6
(any process)
......
/* Setting value =0000_0000_0100_0001 */
/* bit15 = 0
ECKE internal clock source */
/* bit14 -10 =0 Reserved Bit */
/* bit9 = 0
ICLR interrupt flag clear */
/* bit8 = 0
ICLR interrupt disable */
/* bit7 = 0
Reserved Bit */
/* bit6 = 1
STOP Counting disable */
/* bit5 = 0
Reserved Bit */
/* bit4 = 0
SCLR free-run timer value (no) initialization */
/* bit3-0 = 0001 CLK3-0 count clock PCLK/2=32MHz/2 */
/* timer data value initialization */
IO_OCCP6 = BFFF
IO_OCCP7 = 7FFF
/* Select the free-run timer 4. */
/* Setting value =1110_1100_0000_1100 */
/* bit15-13 = 111 Undefined bit */
/* bit12 = 0
CMOD ch.6, ch.7 Level invert */
/* bit11-10 = 11
Undefined bit */
/* bit9-8 = 00
OTD7, OTD6 Compare pin output L*/
/* bit7-6 = 00
IOP7, IOP6 Output compare no match */
/* bit5-4 = 00
IOE7, IOE6 Output compare interrupt disable */
/* bit3-2 = 11
Undefined bit*/
/* bit1-0 = 00
CST7, CST6 Compare operation disable */
/* Setting of compare register ch.6 */
/* Setting of compare register ch.7 */
IO_ICR[42].byte = 0x10;
IO_ICR[43].byte = 0x10;
__EI();
/* Output compare ch.6 interrupt level setting (any value) */
/* Output compare ch.7 interrupt level setting (any value) */
/* Interrupt enable */
}
void OUTPUT67_start(void)
{
IO_OCS67.hword = 0xEC3C;
IO_OCS67.hword = 0xEC3F;
}
void freerun4_start(void)
{
IO_TCCSL4.bit.STOP = 0;
}
__interrupt void INPUT0_int(void)
{
IO_OCSL67.byte & = 0xBF;
……
IO_OCSL67.byte & = 0x7F;
……
}
/* bit5-4 = 11 IOE7, IOE6 Output compare interrupt enable */
/* bit1-0 = 11 CST7, CST6 Compare operation enable */
/* bit4 = 0 STOP Counting enable */
/* bit6 = 0 IOP6 Clearing of interrupt flag */
/* bit7 = 0 IOP7 Clearing of interrupt flag */
Interrupt routine specification with the vector table is required.
#pragma intvect OUTPUT6_int 58
4. Interrupt vector
- Setting of the vector table
Note:
Clock-related setting and setting of __set_il(numerical value) in advance
are required. See "CHAPTER: CLOCK" and "CHAPTER: INTERRUPT
CONTROL (INTERRUPT CONTROLLER)".
794
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Chapter 23: 32-Bit Output Compare
9. Notes
This section explains the notes of the 32-bit output compare.
About the compare stop interval during compare operation
For one count right after the writing of a compare value to the compare register, there is no compare operation as
shown below.
Compare
timing
Count value of free-run timer
N -2
N -1
N
N+ 1
N+ 2
N+ 3
Writing to compare register
Compare register value
X
N
N
Compare stop interval
In this case, a match signal is not generated.
For the setting of CMOD= "1" and OCCP6 = OCCP7, when compare match occurs, the port inverts only once.
(Similar in ch.8 to ch.13)
When the output level of compare output pins (OCU6 to OCU13) is specified, first stop the compare operation, and
then specify it.
Because the 32-bit output compare is synchronized with the free-run timer, when the free-run timer is stopped, the
compare operation is also stopped.
When the compare mode bit is set to CMOD = "1" also, the interrupt operation occurs for each OCU6 and OCU7
independently. (The same is true for ch.8 to ch.13.)
When the free-run timer is used as the compare data of the output compare, the setting of "0000B"(1/FPCLK) is
disabled for the free-run timer clock frequency TCCSL.CLK[3:0].
About read-modify-write
When the interrupt request flag bits (IOP6 to IOP13) are read with read-modify-write instruction, "1" is read.
About interrupt
Please clear the compare match interrupt request flag (IOP6 to IOP13) with "0" to return from the interrupt
processing when "1" is set to compare match interrupt request flag (IOPx) of the compare control register, and the
compare match interrupt request is permitted next (IOE6 to IOE13 ="1").
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795
Chapter 24: 32-Bit Input Capture
This chapter explains the 32-bit input capture.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Setting
7.
Q&A
8.
Sample Program
9.
Notes
Code : FIP008-1v1-91528-3-E
796
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Chapter 24: 32-Bit Input Capture
1. Overview
This section explains the overview of the 32-bit input capture.
The input capture stores the count value of the 32-bit free-run timer at the timing when the signal from the external
source is detected. The time between signals can then be calculated from the count values that have been recorded
repeatedly. An interrupt can be generated when an effective edge from the external input pin is detected.
Moreover, the cycle and the pulse width of the input effective edge can be measured.
Figure 1-1 Block Diagram
LIN Sync Field detection
Free-run timer
Capture
Buffer
Edge detection circuit
External pin ICU
Interrupt
The numbers of available external input pins are shown below.
MB91F52xR (144pin) : 6
MB91F52xU (176pin) : 6
MB91F52xM (208pin) : 8
MB91F52xY (416pin) : 8
2. Features
This section explains features of the 32-bit input capture.
Format :
Number of units :
Edge detection :
Interrupt :
Capture value :
Timer :
See "CHAPTER:
Count accuracy:
Edge detection circuit + 32-bit buffer (capture register)
8
Rising/falling/both edges
Edge detection interrupt
Timer count value (00000000H to FFFFFFFFH)
Use free-run timer 3 to 10.
32-BIT FREE-RUN TIMER" for the selection method.
Peripheral clocks (PCLK)/1, /2, /4, /8, /16, /32, /64, /128, /256
(count clock of the free-run timer)
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Chapter 24: 32-Bit Input Capture
Capture signal
Count value
of free-run
timer
1FFFFFFFH
t
Buffer value
1FFFFFFFH
Cycle and pulse width measurement function
The cycle and the pulse width can be measured by the following settings.
798
When setting of rising edge detection
When setting of falling edge detection
When setting of both edge detection
: Cycle from rising edge to rising edge
: Cycle from falling edge to falling edge
: Cycle from rising edge to rising edge,
Cycle from falling edge to falling edge,
Pulse width from rising edge to falling edge,
Pulse width from falling edge to rising edge
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 24: 32-Bit Input Capture
3. Configuration
This section explains the configuration of the 32-bit input capture.
Figure 3-1 Block Diagram (detailed; per 2 channel)
CH4
ICS
EGI40/41
Input capture
Data register 4
(IPCP4)
Edge detect
MSC
External Pin ICU4 /
LIN synch Fieldch.4
MFS ch4
OVP4
MSO4
MSC
Measurement
counter 4
From 32bit freerun timer
OVC4
MSC
cycle
calculate
control
MSC
ICS
ICP4
ICS
ICE4
ICU4 interrupt
MSC4
cycle・pulse
Measurement control
Cycle measurement data register
4 (MSCY4)
CYC4
PLS4
MSC
MSC
CH5
ICS
EGI50/51
Input capture
Data register 5
(IPCP5)
Edge detect
MSC
External pin ICU5 /
LIN synch Fieldch.5
MFS ch5
OVP5
MSC5
MSC
Measurement
counter 5
From from 32bit free-
run timer
ICS
ICP5
ICS
ICE5
ICU5 interrupt
OVC5
MSC
cycle
calculate
control
Cycle measurement data register
5 (MSCY5)
MSC
MSC5
cycle・pulse
Measurement control
CYC5
PLS5
MSC
MSC
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Chapter 24: 32-Bit Input Capture
4. Registers
This section explains registers of the 32-bit input capture.
Table of Base Addresses (Base_addr) and External Pins
Table 4-1 Table of Base Addresses (Base_addr) and External Pins
External pin (ICU input)
Channel
Base_addr
4
MB91F52xR
MB91F52xU
MB91F52xM
MB91F52xY
0x0FD0
ICU4_0/ICU4_1/ICU4_2
ICU4_0/ICU4_1/ICU4_2
5
0x0FD0
ICU5_0/ICU5_1
ICU5_0/ICU5_1
6
0x0FDC
ICU6_0/ICU6_1
ICU6_0/ICU6_1
7
0x0FDC
ICU7_0/ICU7_1
ICU7_0/ICU7_1
8
0x0FE8
ICU8_0/ICU8_1
ICU8_0/ICU8_1
9
0x0FE8
ICU9_0/ICU9_1
ICU9_0/ICU9_1
10
0x002C
−
ICU10_0
11
0x002C
−
ICU11_0
Table 4-2 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
0x0FD0
IPCP4
Input capture data register 4
0x0FD4
IPCP5
Input capture data register 5
0x0FD8
Reserved
LSYNS2
LSYNS1
ICS45
LIN SYNCH FIELD switching register 2
LIN SYNCH FIELD switching register 1
Input capture control register 45
0x0FDC
IPCP6
Input capture data register 6
0x0FE0
IPCP7
Input capture data register 7
0x0FE4
Reserved
Reserved
ICS67
Input capture control register 67
0x0FE8
IPCP8
Input capture data register 8
0x0FEC
IPCP9
Input capture data register 9
800
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Chapter 24: 32-Bit Input Capture
Registers
Address
Register function
+0
0x0FF0
Reserved
+1
+2
Reserved
+3
ICS89
Input capture control register 89
0x002C
IPCP10
Input capture data register 10
0x0030
IPCP11
Input capture data register 11
0x0034
Reserved
ICS1011 Input capture control register 1011
0x0118
MSCY4
Cycle measurement data register 4
0x011C
MSCY5
Cycle measurement data register 5
0x0F88
Reserved
Reserved
MSCH45
MSCL45
Cycle and pulse width measurement control
register 45
0x0F68
MSCY6
Cycle measurement data register 6
0x0F6C
MSCY7
Cycle measurement data register 7
0x0F8C
Reserved
MSCH67
MSCL67
Cycle and pulse width measurement control
register 67
0x0FF4
MSCY8
Cycle measurement data register 8
0x0FF8
MSCY9
Cycle measurement data register 9
0x0FFC
Reserved
MSCH89
MSCL89
Cycle and pulse width measurement control
register 89
0x0020
MSCY10
Cycle measurement data register 10
0x0024
MSCY11
Cycle measurement data register 11
0x0028
Reserved
MSCH101 MSCL101 Cycle and pulse width measurement control
1
1
register 1011
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801
Chapter 24: 32-Bit Input Capture
4.1.
Input Capture Data Register : IPCP
The bit configuration for the input capture data register is shown.
This register can hold and read the count value or the pulse width measurement data value of the free-run timer using
a change in the input signal from the external source as a trigger.
x: Channel number 4, 6, 8, 10
y: Channel number 5, 7, 9, 11
IPCPx (Input capture x): Address Base_addr+00H (Access: Word)
IPCPy (Input capture y): Address Base_addr+04H (Access: Word)
bit31
bit0
CP[31:0]
Initial value
XXXX
XXXX
XXXX
XXXX
Attribute
XXXX
XXXX
XXXX
XXXX
R,WX
[bit31 to bit0] CP[31:0] :
When MSCL.MSCx or MSCy is "0", this register indicates the value of free-run timer at the edge detection.
When MSCL.MSCx or MSCy is "1", this register indicates the value of the pulse width at the edge detection.
Note:
When accessing this register, use a word access instruction. No data can be written to this register.
4.2.
Input Capture Control Register : ICS
The bit configuration the input capture control register is shown.
This register controls the input capture.
x: Channel number 4, 6, 8, 10
y: Channel number 5, 7, 9, 11
ICSxy (Input capture xy): Address Base_addr+0BH (Access: Byte, Half-word, Word)
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICPy
ICPx
ICEy
ICEx
EGy1
EGy0
EGx1
EGx0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Attribute R(RM1),W R(RM1),W
[bit7, bit6] ICPn : Input capture interrupt request flag
802
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Chapter 24: 32-Bit Input Capture
State
ICPn
Read
Write
0
No interrupt request
Clear the flag
1
Interrupt request present (edge detected)
No effect on operation
This flag will be set to "1" when the signal change (edge) selected in the capture effective edge selection bit
(EG[n1:n0]) is detected in the input signal from the external pin.
To enable the CPU interrupt request, you need to enable interrupt request enable setting (ICEn="1").
Note:
ICPn: n corresponds to the input capture channel numbers.
[bit5, bit4] ICEn : Input capture interrupt request enabled
ICEn
Operation
0
Interrupt disabled
1
Interrupt enabled
An input capture interrupt is generated when the input capture interrupt request flag is set to "1" while the input
capture interrupt request enable bit is set to "1".
Note:
ICEn: n corresponds to the input capture channel numbers.
[bit3 to bit0] EGn1, EGn0 : Input capture n effective edge selection
EGn1
EGn0
Edge selection
0
0
Input capture stopped
0
1
Rising edge
1
0
Falling edge
1
1
Both edges (rising and falling edges)
These bits select the capture effective edge(s) for the input capture signal from the external pin.
The input capture will be in stop if the effective edge selection bit is "00B".
Note:
EGn1, EGn0: n corresponds to the input capture channel numbers.
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Chapter 24: 32-Bit Input Capture
4.3.
LIN SYNCH FIELD Switching Register : LSYNS
The bit configuration for the LIN SYNCH FIELD switching register is shown.
When the capture operation is enabled (ICS.EG[n1:n0] is other than "00") and input is switched while the signal level
of the external pin input and the state of the LIN synch field detection signal (level) are different, edges will be
detected and will operate as capture effective edges.
LSYNS2 (Input capture 10, 11): Address 0FD9H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved Reserved LSYN112 LSYN111 LSYN110 LSYN102 LSYN101 LSYN100
Initial value
Attribute
0
0
0
0
0
0
0
0
R0/W0
R0/W0
R/W
R/W
R/W
R/W
R/W
R/W
Note:
The input for the input capture must be switched while the capture is inactive (ICS.EG[n1:n0]= "00").
[bit7, bit6] Reserved
The read value is always "0".
Always write "0" to these bits.
[bit5 to bit3] LSYN112 to LSYN110 : Input capture ch.11 input selection
LSYN112 LSYN111
LSYN110
Input selection
0
0
0
External pin input (ICU11)
0
0
1
LIN synch field detection signal input from the
multi-function serial interface ch.16.
0
1
0
LIN synch field detection signal input from the
multi-function serial interface ch.17.
0
1
1
LIN synch field detection signal input from the
multi-function serial interface ch.18.
1
0
0
LIN synch field detection signal input from the
multi-function serial interface ch.19.
Other settings
Setting prohibited. (Operation is not guaranteed.)
[bit2 to bit0] LSYN102 to LSYN100 : Input capture ch.10 input selection
LSYN102 LSYN101 LSYN100
0
804
0
0
Input selection
External pin input (ICU10)
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Chapter 24: 32-Bit Input Capture
LSYN102 LSYN101 LSYN100
Input selection
0
0
1
LIN synch field detection signal input from the
multi-function serial interface ch.12.
0
1
0
LIN synch field detection signal input from the
multi-function serial interface ch.13.
0
1
1
LIN synch field detection signal input from the
multi-function serial interface ch.14.
1
0
0
LIN synch field detection signal input from the
multi-function serial interface ch.15.
Other settings
Setting prohibited. (Operation is not guaranteed.)
LSYNS1 (Input capture 4-9): Address 0FDAH (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LSYN91
LSYN90
LSYN81
LSYN80
LSYN7
LSYN6
LSYN5
LSYN4
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
The input for the input capture must be switched while the capture is inactive (ICS.EG[n1:n0]= "00").
[bit7, bit6] LSYN91, LSYN90 : Input capture ch.9 input selection
LSYN91, LSYN90
Input selection
00
External pin input (ICU9)
01
LIN synch field detection signal input from the multi-function serial
interface ch.10.
10
LIN synch field detection signal input from the multi-function serial
interface ch.11.
11
Setting prohibited. (Operation is not guaranteed.)
[bit5, bit4] LSYN81, LSYN80 : Input capture ch.8 input selection
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Chapter 24: 32-Bit Input Capture
LSYN81, LSYN80
Input selection
00
External pin input (ICU8)
01
LIN synch field detection signal input from the multi-function serial
interface ch.8.
10
LIN synch field detection signal input from the multi-function serial
interface ch.9.
11
Setting prohibited. (Operation is not guaranteed.)
[bit3 to bit0] LSYN7 to LSYN4 : Input capture ch.4 to ch.7 input selection
LSYNn (n=4 to 7)
4.4.
Input selection
0
External pin input (ICUn)
1
LIN synch field detection signal input from the multi-function
serial interface ch.n.
Cycle Measurement Data Register : MSCY
The cycle measurement data register is shown.
This register stores the measured cycle data value, when an effective edge of the corresponding external input pin
signal was detected.
MSCY4 (Input capture 4): Address 0118H (Access: Half-word, Word)
MSCY5 (Input capture 5): Address 011CH (Access: Half-word, Word)
MSCY6 (Input capture 6): Address 0F68H (Access: Half-word, Word)
MSCY7 (Input capture 7): Address 0F6CH (Access: Half-word, Word)
MSCY8 (Input capture 8): Address 0FF4H (Access: Half-word, Word)
MSCY9 (Input capture 9): Address 0FF8H (Access: Half-word, Word)
MSCY10 (Input capture 10): Address 0020H (Access: Half-word, Word)
MSCY11 (Input capture 11): Address 0024H (Access: Half-word, Word)
bit31
bit0
CY[31:0]
Initial value
Attribute
806
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
R,WX
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Chapter 24: 32-Bit Input Capture
When MSCL.MSCn(n=4 to 11) is "0", "0000_0000 H " is set in this register.
When MSCL.MSCn(n=4 to 11) is "1", the cycle value when the edge is detected is set in this register.
Note:
Please use the half-word or the word access instruction for this register. Moreover, data cannot be written in this
register.
4.5.
Cycle and Pulse Width Measurement Control Register
(Upper bit) : MSCH
The bit configuration of the cycle and pulse width measurement control register (upper bit) is shown.
This register controls the input capture.
x: Channel number 4, 6, 8, 10
y: Channel number 5, 7, 9, 11
MSCH45 (Input capture 45): Address 0F8AH (Access: Byte, Half-word, Word)
MSCH67 (Input capture 67): Address 0F8EH (Access: Byte, Half-word, Word)
MSCH89 (Input capture 89): Address 0FFEH (Access: Byte, Half-word, Word)
MSCH1011 (Input capture 1011): Address 002AH (Access: Byte, Half-word, Word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CYCy
CYCx
PLSy
PLSx
OVCy
OVCx
OVPy
OVPx
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15, bit14] CYCn : Cycle measurement flag
CYCn
Explanation
0
Cycle data from falling edge to falling edge.
1
Cycle data from rising edge to rising edge.
These bits show that the data stored in the cycle measurement data register (MSCYn) is either rising cycle or falling
cycle. Whenever an effective edge is detected and measured, these bits are updated.
Note:
CYCn : n corresponds to the channel number of the input capture.
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Chapter 24: 32-Bit Input Capture
[bit13, bit12] PLSn : Pulse width measurement flag
PLSn
Explanation
0
L pulse width.
1
H pulse width.
These bits show that the data stored in the input capture data register (IPCPn) is either H pulse width or L pulse width.
Whenever an effective edge is detected and measured, these bits are updated.
Note:
PLSn : n corresponds to the channel number of the input capture.
[bit11, bit10] OVCn : Cycle measurement over flag
OVCn
Explanation
0
The cycle data value is maximum value FFFF_FFFFH or less.
1
The cycle data value exceeds maximum value FFFF_FFFFH.
These bits show that the data stored in the cycle measurement data register (MSCYn) have exceeded the maximum
value. Whenever an effective edge is detected and measured, these bits are updated.
Note:
OVCn : n corresponds to the channel number of the input capture.
[bit9, bit8] OVPn : Pulse width measurement over flag
OVPn
Explanation
0
The pulse width data value is maximum value FFFF_FFFFH or less.
1
The pulse width data value exceeds maximum value FFFF_FFFF H.
These bits show that the data stored in the input capture data register (IPCPn) have exceeded the maximum value.
Whenever an effective edge is detected and measured, these bits are updated.
Note:
OVPn : n corresponds to the channel number of the input capture.
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Chapter 24: 32-Bit Input Capture
4.6.
Cycle and Pulse Width Measurement Control Register
(Lower bit) : MSCL
The configuration of the cycle and pulse width measurement control register (lower bit) is shown.
This register controls the input capture.
x: Channel number 4, 6, 8, 10
y: Channel number 5, 7, 9, 11
MSCL45 (Input capture 45): Address 0F8BH (Access: Byte, Half-word, Word)
MSCL67 (Input capture 67): Address 0F8FH (Access: Byte, Half-word, Word)
MSCL89 (Input capture 89): Address 0FFFH (Access: Byte, Half-word, Word)
MSCL1011 (Input capture 1011): Address 002BH (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
-
-
MSCy
MSCx
1
1
1
1
1
1
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R/W
[bit7 to bit2] : Undefined
The read value is always "1". Writing has no effect on operation.
[bit1, bit0] MSCn : Operation mode setting
MSCn
Explanation
0
Input capture operation
1
Measurement operation of cycle and pulse width
These bits select the operation mode when the edge of external input ICUn is detected.
Note:
MSCn : n corresponds to the channel number of the input capture.
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Chapter 24: 32-Bit Input Capture
5. Operation
This section explains the operation of the 32-bit input capture.
When a set effective edge is detected, the 32-bit input capture can retrieve the value of the 32-bit free-run timer into
the capture register and generate an interrupt.
This section explains the input capture operation.
5.1 Capture and Interrupt Timings
5.2 Edge Detection Specifications for Input Capture And Their Operations
5.3 Cycle and Pulse Width Measurement Operation
5.1.
Capture and Interrupt Timings
This section shows capture and interrupts timings.
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Chapter 24: 32-Bit Input Capture
Figure 5-1 Example of 32-Bit Input Capture Operation
(1)
Input capture
Peripheral clock
(PCLK)
(2)
Effective edge
Free-run timer 3
N
N+1
(3)
Capture register
Interrupt
request
(4)
FFFFFFFF H
Count of
free-run
timer 3
00000000 H
Enable free-run
timer operation
Input capture
Interrupt request
(1) Rising edge of the input signal
(2) Internal signal generated by edge detection (synchronized to the peripheral clock)
(3) Free-run timer value is recorded to the capture register (capture).
(4) Input capture interrupt is generated (ICP(4 to 11)="1").
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Chapter 24: 32-Bit Input Capture
5.2.
Edge Detection Specifications for Input Capture And Their
Operations
This section shows edge detection specifications for the input capture and their operations.
Figure 5-2 Example of the Edge Detection Specifications Operation
Count value of
free-run timer 3
When rising edge is selected
(1) Rising edge of the input signal is detected.
(2) Free-run counter value is recorded to the capture register (capture).
(3) Input capture interrupt is generated.
When falling edge is selected
(4) Falling edge of the input signal is detected.
(5) Free-run counter value is recorded to the capture register (capture).
(6) Input capture interrupt is generated.
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Chapter 24: 32-Bit Input Capture
Both edges
(7) Rising edge of the input signal is detected.
(8) Free-run counter value is recorded to the capture register (capture).
(9) Input capture interrupt is generated.
(10) Interrupt request flag ((ICS45.ICP4), (ICS45.ICP5), (ICS67.ICP6), (ICS67. ICP7), ....) is cleared
using software.
(11) Falling edge of the input signal is detected.
(12) Free-run counter value is recorded to the capture register (capture).
(13) Input capture interrupt is generated.
5.3.
Cycle and Pulse Width Measurement Operation
This section shows the cycle and pulse width measurement operation.
The edge of the external pin input is detected, and the cycle (rising or falling) and the pulse width (H or L)
are measured with a counter clocked by the peripheral clock PCLK2.
When measuring, a measurement value is stored in the input capture data register (MSCYn: n=4 to 11) and
the pulse width measurement data register (IPCPn: n=4 to 11). At the same time, the input capture is
displayed that a cycle of measurement, a type of pulse width, and whether the measurement value exceeds
the maximum value in the cycle and pulse width measurement control register (MSCHxy.CYCx/y, PLSx/y,
OVCx/y, OVPx/y: x=4, 6, 8, 10 y=5, 7, 9, 11).
The maximum value of the cycle and pulse width is FFFF_FFFFh. When the maximum value is exceeded,
the capture value of the counter is displayed as a measuring data. At the same time, the input capture is
displayed that the measurement value exceeded the maximum value in the cycle measurement overflow
flag (MSCH:OVCn: n=4 to 11) and the pulse width measurement overflow flag (MSCH:OVPn: n=4 to 11)
of the cycle and pulse width measurement control register.
After the measurement operation starts, the measurement is started by cycle or pulse width from the first
edge.
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Chapter 24: 32-Bit Input Capture
Figure 5-3 Example of the Cycle and Pulse Width Measurement Operation (The both edges are
specified).
Counter value
Full count
FFFFFFFFh
A
7FFFFFFFh
B
Full count
C
D
E
00000000h
input
Input capture
Input
capture 4/5
data
data register
register 0/1
0
A
B
C(max value)
* The first edge is not measured.
Cycle measurement ※do not measurement by first edge
Cycle measurement
0
A+B
data register
register 0/1
4/5
data
↑-↑
↑～↑
Overflow
detect
Over flow
detect
B+C(max value)
↓-↓
↓～↓
D(max value)
E
C(max value)
C(max value)+D(max
value)+ E
D(max value)
+ D(max value)
↑ - ↑ ↑～↑
↓-↓
Pulsewidth
width measurement
Pulse
measurement
flow
Overflow flagover
bit 4/5
flag bit 0/1
measurement
Cycle measurement
over
flow flag
flag bit
bit 4/5
0/1
Overflow
Pulse width
measurement flag bit
0/1
Cycle
Cycle measurement
measurement
flag
flag bit
bit 0/1
4/5
H
L
↑～↑
↑ - ↑
↓ - ↓
↓～↓
Interrupt factor
（cycle・pulse width
measurement by both
edge ）)
edges
interrupt
↑
↑
Interrupt clear
When both edges are specified, cycle of from rising edge to rising edge and from falling edge to falling
edge, pulse width of from rising edge to falling edge and from falling edge to rising edge are measured.
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Chapter 24: 32-Bit Input Capture
Figure 5-4 Example of the Cycle and Pulse Width Measurement Operation (The rising edge is
specified).
Counter
value
Count value
Full count
FFFFFFFFh
FFFFFFFF
H
A
7FFFFFFFh
7FFFFFFF
H
B
Full count
C
D
E
00000000
H
00000000h
input
Input
Inputcapture
capture data
register
0/1 4/5
data
register
0
A
B
C(max value)
D(max value)
E
* Thenot
first measurement
edge is not measured.
※do
by first edge
Cyclemeasurement
measurement
Cycle
data register 0/1
0
A+B
C(max value)+D(max value)
data register 4/5
↑～↑
↑ - ↑
Over flow
detect
Overflow
detect
↑～↑
↑ - ↑
Pulse
Pulsewidth
width measurement
measurement over flow
overflow flag bit 4/5
flag bit 0/1
Cycle measurement
measurement
Cycle
over flow flag bit 0/1
overflow flag bit 4/5
Pulse width
Pulse
width measurement
measurement
flag bit
H
L
H
L
H
0/1bit 4/5
flag
Cyclemeasurement
measurement
Cycle
flag bit 0/1
↑～↑
↑ - ↑
flag bit 4/5
Interrupt factor
（cycle measurement by
↑
↑edge）
interrupt
↑
↑
Interrupt clear
When the rising edge is specified, cycle of from rising edge to rising edge is measured.
At this time, interrupt is not output though pulse width of from rising edge to falling edge and from falling
edge to rising edge is stored in input capture data register (IPCPn).
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Chapter 24: 32-Bit Input Capture
Figure 5-5 Example of the Cycle and Pulse Width Measurement Operation (The falling edge is
specified).
Counter
value
Count value
Full count
FFFFFFFFh
FFFFFFFF
H
A
7FFFFFFFh
7FFFFFFF
H
B
Full count
C
D
E
00000000
00000000h
H
input
Input capture
data register
Input
capture 4/5
data
register 0/1
Cycle measurement
0
A
B
C(max value)
D(max value)
E
* The not
first measurement
edge is not measured.
※do
by first edge
Cycle measurement
data register
register 0/1
4/5
data
0
C(max value)+D(max
value)
B+C(max value)
↓～↓
↓-↓
Overflow detect
↓～↓
↓-↓
Over flow detect
Pulse width measurement
Pulse width
overflow flag bit 4/5
measurement overflow
flag bit 0/1
Cycle measurement
Cycle measurement
overflow flag bit 4/5
overflow flag bit 0/1
Pulse width
width measurement
Pulse
measurement
flag bit 4/5 flag bit
0/1
Cycle measurement
Cycle measurement
flag bit
bit 0/1
4/5
flag
Interrupt factor
（cycle measurement by
↓edge）
↓
H
L
H
L
H
↓～↓
↓ - ↓
interrupt
↑
↑
Interrupt clear
When the falling edge is specified, cycle of from falling edge to falling edge is measured.
At this time, interrupt is not output though pulse width of from rising edge to falling edge and from falling
edge to rising edge is stored in input capture data register (IPCPn).
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Chapter 24: 32-Bit Input Capture
6. Setting
This section explains setting of the 32-bit input capture.
Table 6-1 Settings Required for Using Input Capture
Configuration
Register to be configured
Setting
method
Free-run timer setting
See "CHAPTER: 32-BIT FREE-RUN TIMER".
-
Free-run timer activation
If the linkage function for multi-function serial interface is used:
Setting for switching
LIN SYNCH FIELD switching register (LSYNS1, 2)
inputs between input pins External input:
ICU4 to ICU11 and input Settings of the LIN SYNCH FIELD switching register (LSYNS1, 2),
capture
Setting of ICU4 to ICU11 pins
(See "CHAPTER: I/O PORTS").
See 7.2.
Effective edge polarity
selection for external
input
Input capture control registers
(ICS45), (ICS67), (ICS89), (ICS1011)
See 7.1.
Operation mode setting
Operation mode setting bit (MSCn) is set.
See 7.7.
Table 6-2 Settings Required for Performing Input Capture Interrupt
Configuration
Input capture interrupt vector and
input capture interrupt level settings
Input capture interrupt setting
Interrupt request clear
Interrupt request enable
Register to be configured
See "CHAPTER: INTERRUPT CONTROL
(INTERRUPT CONTROLLER)".
Input capture control registers
(ICS45), (ICS67), (ICS89), (ICS1011)
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Setting
method
See 7.3.
See 7.5.
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Chapter 24: 32-Bit Input Capture
7. Q&A
This section explains Q&A of the 32-bit input capture.
7.1 Effective Edge Polarity of External Input: Types and How to Select Them
7.2 How to Enable External Input Pins (ICU4 to ICU11)
7.3 About Interrupt Related Registers
7.4 About Interrupt Types
7.5 How to Enable Interrupt
7.6 How to Measure the Pulse Width of the Input Signal
7.7 How to Set the Operation Mode
7.1.
Effective Edge Polarity of External Input: Types and How
to Select Them
This section shows types of the effective edge polarity of external input and the selection method.
There are 3 types of the effective edge polarity: rising, falling and both edges.
You can configure it using the effective edge polarity bits of the external input (ICS45.EG[41:40]),
(ICS45:EG[51:50]), (ICS67.EG[61:60]), (ICS67:EG[71:70]), (ICS89.EG[81:80]), (ICS89:EG[91:90]),
(ICS1011.EG[101:100]), (ICS1011:EG[111:110]).
Operation
Effective edge polarity bits of the external input
(EG[n1:n0] n=4 to11)
To select rising edge
Select "01".
To select falling edge
Select "10".
To select both edges
Select "11".
7.2.
How to Enable External Input Pins (ICU4 to ICU11)
This section shows how to enable setting of external input pins (ICU4 to ICU11).
Set the LSYNS1 and LSYNS2 registers for external pin input. Also, set the ICU pin for peripheral input. For
information on the setting method of peripheral input, see "CHAPTER: I/O PORTS".
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Chapter 24: 32-Bit Input Capture
7.3.
About Interrupt Related Registers
This section shows interrupt related registers.
Input capture interrupt vector and input capture interrupt level settings
See "Table of Interrupt Vector" in "APPENDIX" for interrupt number.
Set interrupt level by the ICR register. For details of the interrupt levels, see "CHAPTER: INTERRUPT CONTROL
(INTERRUPT CONTROLLER)".
Interrupt request flags ((ICS45.ICP4), (ICS45.ICP5), (ICS67.ICP6), (ICS67.ICP7), (ICS89.ICP8), (ICS89.ICP9),
(ICS1011.ICP10), (ICS1011.ICP11)) are not cleared automatically. Therefore, clear the input capture interrupt request
flags by writing "0" using software before returning from interrupt processing.
7.4.
About Interrupt Types
This section shows interrupt types.
There are 2 types of interrupts.
When the input capture operates:
The interrupt is generated by an edge detection of the input
signal.
When the cycle and pulse width measurement operates: The interrupt is generated by an edge detection of the input
signal, and completion of measurement of cycle or pulse
width.
7.5.
How to Enable Interrupt
This section shows how to enable interrupt.
Set enable interrupt request and interrupt request flag.
You can configure the interrupt enable setting using the following interrupt request enable bits:
(ICS45.ICE4), (ICS45.ICE5), (ICS67.ICE6), (ICS67.ICE7), (ICS89.ICE8), (ICS89.ICE9), (ICS1011.ICE10),
(ICS1011.ICE11)
Operation
Interrupt request enable bits (ICE4 to ICE11)
Interrupt disabled
Set "0".
Interrupt enabled
Set "1".
You can clear the interrupt request using the following interrupt request flags:
(ICS45.ICP4), (ICS45.ICP5), (ICS67.ICP6), (ICS67.ICP7), (ICS89.ICP8), (ICS89.ICP9), (ICS1011.ICP10),
(ICS1011.ICP11)
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Chapter 24: 32-Bit Input Capture
Operation
Interrupt request flag bits (ICP4 to ICP11)
Interrupt request clear
7.6.
Write "0".
How to Measure the Pulse Width of the Input Signal
This section shows how to measure the pulse width of the input signal.
The setting example in ch.4 is shown.
(1) Set the operation mode to the cycle measurement mode. (MSCL.MSC4: 1)
(2) Specify both edges for the edge detection. (ICSL.EG41-40: 11B)
(3) Set enable to the interrupt request bit. (ICSL.ICE4: 1)
(4) Clear the interrupt request flag. (ICSL.ICP4: 0)
The cycle measurement data is stored to MSCY4 and the pulse width measurement data is stored in input capture data
register IPCP4.
7.7.
How to Set the Operation Mode
This section shows how to set the operation mode.
You can select the operation mode when the edge is detected using the MSCn bit.
MSCL.MSCn=0: Input capture operation
MSCL.MSCn=1: Measurement operation of cycle and pulse width
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Chapter 24: 32-Bit Input Capture
8. Sample Program
This section explains the sample program of the 32-bit input capture.
Setting procedure example 1
Program example 1
Detect the rising edge of the pulse for input to ICU4 and record the value of
free-run timer.
This process is repeated twice to measure the time from one trigger to
another. However, reading and calculation of the capture value are to be
handled as interrupt processes.
void INPUT0_sample_1(void)
{
freerun0_initial();
INPUT4_initial();
INPUT4_start();
freerun0_start();
}
1. Initial setting
-Free-run timer ch.3 control
Control register setting
Clock selection>>
Register name.Bit.name
TCCSH3/TCCSL3
.ECKE
Compare interrupt request flag>>
Compare interrupt request enable>>
.ICLR
.ICRE
Counting operation>>
.STOP
TCDT clear
Count clock>>
.SCLR
.CLK3-0
Timer data value setting
TCDT3
void freerun0_initial(void)
{
IO_TCCS3.word = 0x0041;
IO_TCDT3 = 0x0000;
/* Setting value=0000_0000_0100_0001 */
/* bit15 = 0
ECKE internal clock source */
/* bit14 to 10 =0 Reserved bit */
/* bit9 = 0
Interrupt flag clear */
/* bit8 = 0
Interrupt disabled */
/* bit7 = 0
Reserved bit */
/* bit6 = 1
*/
/* bit5 = 0
Reserved bit */
/* bit4 = 0
*/
/* bit3 to 0 = 0001 */
/* Initialization of timer data value */
}
-Port
Port ICU4 input setting
Register name.Bit name
See "CHAPTER: I/O
PORTS".
-Input capture control
Register name.Bit name
Control register setting
ICS45
Interrupt request flag>>
.ICP5, ICP4
Interrupt request enabled>>
.ICE5, ICE4
ch.5 Effective edge polarity selection>>
.EG51, EG50
ch.4 Effective edge polarity selection>>
.EG41, EG40
-Interrupt-related
Sets an interrupt level.
I flag setting
Register name.Bit name
ICR36
(CCR)
-Variable setting
2. Activation
-Input capture ch.4 activation
Interrupt control
void INPUT4_initial(void)
{
PORT_SETTING_ICU4_IN(); /* Set the ICU0 pin for peripheral input. */
IO_ICS45.byte = 0x01;
/* Setting value=0000_0001 */
/* bit7 to 6 = 00 ICP5, 4, 0 Interrupt request flag clear */
/* bit5 to 4 = 00 ICE5, 4, 0 Interrupt disabled */
/* bit3 to 2 = 00 EG51, EG50 ch.5 No edge detected */
/* bit1 to 0 = 01 EG41, EG40 ch.4 Rising edge detected */
IO_ICR[36].byte = 0x10;
__EI();
count = 0;
/* Input capture ch.4 interrupt level setting (any value) */
/* Interrupt enabled */
}
Register name.Bit name
ICS45.ICE4
void INPUT4_start(void)
{
IO_ICS45.bit.ICE4 = 1;
}
-Free-run timer ch.3 activation
Count operation activation
Register name.Bit name
TCCSL3.STOP
void freerun3_start(void)
{
IO_TCCSL3.bit.STOP = 0;
}
3. Interrupt
-Interrupt processing
Clearing of interrupt request flag
Register name.Bit name
ICS45.ICP4
__interrupt void INPUT4_int(void)
{
IO_ICS45.bit.ICP4 = 0;
} count++;
(Any process)
......
/* bit4 = 1 ICE45 ch.4 Interrupt enabled */
/* bit6 = 0 STOP count enabled */
/* bit6 = 0 Clearing of ICP4 effective edge detection flag */
Specification of interrupt routine required in vector table
#pragma intvect INPUT4_int 52
4. Interrupt vector
-Vector table setting
Note:
Clock-related settings and the setting of __set_il (numeric value) need to be
configured in advance. See "CHAPTER: CLOCK" and "CHAPTER:
INTERRUPT CONTROL (INTERRUPT CONTROLLER)".
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Chapter 24: 32-Bit Input Capture
9. Notes
This section explains notes of the 32-bit input capture.
Input capture data register
The input capture register value is undefined after a reset.
Reading of the input capture data register must be performed in word (32-bit mode) access.
Cycle measurement data register
Reading of the cycle measurement data register must be performed in word (32-bit mode) access.
Read-modify-write
The input capture interrupt request bits (ICP4 to ICP11) are "1" when read using a read-modify-write.
Notes when interrupt is processed
It is necessary to clear the interrupt request flag (ICPn) to "0" to return from the interrupt processing, when "1" is
set to interrupt request flag (ICPn) of input capture control register (ICS), and the interrupt request is set to enable
(ICS.ICEn=1).
When the cycle and pulse width measurement operates, the edge of the external input pin (ICUn) is detected while
the interrupt routine is being processed, and the cycle and the pulse width are measured, measured latest
information is shown in the cycle measurement data register (MSCYn) and the input capture data register (IPCPn).
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Chapter 25: 16-Bit Free-Run Timer
This chapter explains the 16-bit free-run timer.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FS17-1v0-91528-3-E
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823
Chapter 25: 16-Bit Free-Run Timer
1. Overview
This section is explains the overview of 16-bit free-run timers.
The free-run timer consists of one free-run timer simultaneous activation, three 16-bit free-run timers (1 channel each
and total of 3 channels), and one free-run timer selector.
2. Features
This section is explains the features of 16-bit free-run timers.
Function of the Free-run Timer Simultaneous Activation
Of the three 16-bit free-run timers, the selected 16-bit free-run timers can be activated or cleared simultaneously.
It simultaneously controls the timer clear bit (SCLR) and the timer enable bit (STOP) of the timer state register
(TCCS) for each 16-bit free-run timer that enables the free-run timer simultaneous activation.
If the timers are not activated or cleared simultaneously, it is possible to activate or clear each 16-bit free-run timer
individually by setting the timer enable bit (STOP) and timer clear bit (SCLR) of the timer state register (TCCS).
Function of the 16-bit Free-run Timer
The 16-bit free-run timer consists of 16-bit up/down counter, control register, 16-bit compare clear register (with
buffer register), and prescaler.
You can select one of the nine counter operation clocks (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256). (φ:
peripheral clock)
A compare clear interrupt will be generated when a compare clear register matches the 16-bit free-run timer upon
comparison of the two. "0" detection interrupt will be generated while the 16-bit free-run timer is detecting the
count value "0".
The compare clear register comes with selectable buffer registers (Data written to this buffer register will be
transferred to the compare clear register). Once data is written to the buffer after the 16-bit free-run timer has
stopped, the transfer will be executed immediately. If the timer value "0" is detected while the 16-bit free-run timer
is active, data will be transferred from the buffer.
If there is a reset or if there is a compare match with the software clear or compare clear register, the counter value
will be reset to "0000H".
This counter output value can be used as a clock count of the output compare, the input capture and the A/D
activation compare.
Function of the Free-run Timer Selector
The free-run timer selection register allows you to select the assignment of the free-run timer from among the
16-bit output capture, the 16-bit input capture, and the A/D activation compare.
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Chapter 25: 16-Bit Free-Run Timer
3. Configuration
This section is explains the configuration of 16-bit free-run timers.
Configuration of the 16-bit Free-run Timer Simultaneous Activation
Figure 3-1 Configuration of the Free-run Timer Simultaneous Activation
Simultaneous activation of free-run timers
( TCGS )
GSTOP
Enable pulse
generation
Disable pulse
generation
( TCGS )
GSCLR
Clear pulse
generation
Clear
cancellation pulse
generation
( TCGSE)
Free-run timer enable signal 0
FRT0
Free-run timer disable signal 0
Free-run timer clear signal 0
Free-run
Free-run timer
timer clear
clear
cancellation
cancellationsignal
signal00
( TCGSE)
Free-run timer enable signal 25
FRT52
Free-run timer disable signal 25
Free-run timer clear signal 25
Free-run timer clear
cancellation signal 25
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825
Chapter 25: 16-Bit Free-Run Timer
Configuration of the 16-bit Free-run Timer
Figure 3-2 Configuration of the 16-bit Free-run Timer (only one channel)
Enabling free-run timer 0,
Disabling free-run timer 0,
Clearing free-run timer 0
Free-run timer 0
( TCCS0 )
STOP
( TCCS0)
( TCCS0 )
( TCCS0 )
ECKE
MODE
CLK3-CLK0
Peripheral clock
SCLR
0
Prescaler
Timer 0
16-bit free-run timer 0
FRCK0
1
Timer data register 0
(TCDT0)
"0"0detection
detection0 0
Compare clear buffer register 0
(CPCLRB0)
0 detection
"0" detection
Compare clear 0
( TCCS0 )
Compare clear register 0
(CPCLR0)
BFE
Compare
circuit
Interrupt
generation
circuit
( TCCS0 )
MSI2-MSI0
Interrupt
generation
circuit
( TCCS0)
MODE 2 MSI5-MSI3
( TCCS0)
IRQZE
IRQZF
ICRE
ICLR
Compare clear
interrupt 0
"0"0 detection
Interrupt 0
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Chapter 25: 16-Bit Free-Run Timer
Configuration of the Free-run Timer Selector
Figure 3-3 Configuration of the Free-run Timer Selector
Free-run timer selection
#0 (for OCU)
( FRS 0 )
O S01- O S00
Timer 1 (16-bit free-run timer 1)
Select
Timer 0 (16-bit free-run timer 0)
Timer
(16-bit output compare 0)
Timer 2 (16-bit free-run timer 2)
0 detection
"0"
detection1,1,
compare clear 1,
down count status 1,
count mode 1 (free-run timer 1)
Select
0 detection
"0"
detection0,0,
compare clear 0,
down count status 0,
count mode 0 (free-run timer 0)
0 detection
"0"
detection2,2,
compare clear 2,
down count status 2,
count mode 2 (free-run timer 2)
#1 to 5 (for OCU)
0 detection,
"0"
compare clear,
down count status,
count mode
(16-bit output compare 0)
Timer,
"0"
0 detection,
compare clear,
down count status,
count mode
(16-bit output compare 1 to 5)
#0 (for ICU)
( FRS1)
Select
IS01- IS00
#1 to 3 (for ICU)
Timer
(16-bit input capture 0)
Timer
(16-bit input capture 1 to 3)
#0 (for A/D activation
compare)
( FRS 2 )
Select
Select
ADT01- ADT00
#1 to 63
47
(for A/D activation
compare)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Timer
(A/D activation compare 0)
0 detection,
"0"
compare clear,
down count status,
(A/D activation compare 0)
Timer,
"0"
detection,
0 detection,
compare clear,
down count status,
(A/D activation compare 1 to 63
47)
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Chapter 25: 16-Bit Free-Run Timer
4. Registers
This section is explains the registers of 16-bit free-run timers.
Table of external pins
Channel
External pins (FRCK)
MB91F52xR, MB91F52xU, MB91F52xM, MB91F52xY
0
1
2
FRCK0_0
FRCK1_0/FRCK1_1
FRCK2_0
List of registers
Table 4-1 List of Registers for the Free-run Timer Simultaneous Activation
Address
+0
+1
+2
0x1200
Timer synchronous
activation register
(TCGS)
Reserved
Reserved
Table 4-2 List of Registers for the 16-bit Free-run Timer
Address
+0
+1
828
0x1204
Compare clear buffer register 0 (CPCLRB0)
Compare clear register 0 (CPCLR0)
0x1208
Timer state control register 0 (TCCS0)
0x120C
Compare clear buffer register 1 (CPCLRB1)
Compare clear register 1 (CPCLR1)
0x 1210
Timer state control register 1 (TCCS1)
0x1214
Compare clear buffer register 2 (CPCLRB2)
Compare clear register 2 (CPCLR2)
0x1218
Timer state control register 2 (TCCS2)
+3
Timer synchronous
activation enable
register
(TCGSE)
+2
+3
Timer data register (TCDT0)
Reserved
Timer data register (TCDT1)
Reserved
Timer data register (TCDT2)
Reserved
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Chapter 25: 16-Bit Free-Run Timer
Table 4-3 List of Registers for the Free-run Timer Selector
Address
+0
+1
0x1234
Reserved
0x1238
Reserved
+3
Free-run timer selection register 0 (FRS0)
Reserved
0x123C
Free-run timer selection register 2 (FRS2)
0x1240
Free-run timer selection register 3 (FRS3)
0x1244
Free-run timer selection register 4 (FRS4)
0x12D0
Free-run timer selection register 5 (FRS5)
0x12D4
Free-run timer selection register 6 (FRS6)
0x12D8
Free-run timer selection register 7 (FRS7)
0x12DC
Free-run timer selection register 10 (FRS10)
0x12E0
Free-run timer selection register 11 (FRS11)
4.1.
+2
Free-run timer selection register 1 (FRS1)
Registers for the Free-run Timer Simultaneous Activation
Registers for the free-run timer simultaneous activation are explained.
The free-run simultaneous activation consists of the timer synchronous activation register and the timer synchronous
enable register.
4.1.1.
Timer Synchronous Activation Register : (TCGS)
This section explains the bit structure of the timer synchronous activation register.
The timer synchronous activation register (TCGS) is used for enabling simultaneous timer and controlling
simultaneous timer clear of the free-run timer. The free-run timer for enabling and clearing the simultaneous timer can
be set by the timer synchronous activation enable register (TCGSE).
TCGS: Address 1200H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
GSTOP
GSCLR
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W
R0,W
[bit7 to bit2] Reserved
Always write "0" to these bits.
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Chapter 25: 16-Bit Free-Run Timer
[bit1] GSTOP: Simultaneous timer enable bit
GSTOP
Function
Read
Write
Enable the counting simultaneously.
(Start the counting)
Disable the counting simultaneously.
(Stop the counting)
0
"0" is always read out.
1
This bit is used to simultaneously start/stop the counting of the free-run timer specified by the timer synchronous
activation enable register (TCGSE).
When this bit is set to "0":
Starts the counting of the 16-bit free-run timer of the free-run timer specified by the timer synchronous activation
enable register (TCGSE). At this time, the STOP bit of the timer state control register (TCCS) of the free-run
timer specified by the timer synchronous activation enable register (TCGSE) will be cleared to "0".
When this bit is set to "1":
Stops the counting of the 16-bit free-run timer of the free-run timer specified by the timer synchronous activation
enable register (TCGSE). At this time, the STOP bit of the timer state control register (TCCS) of the free-run
timer specified by the timer synchronous activation enable register (TCGSE) will be set to "1".
The value read out is always "0".
[bit0] GSCLR: Simultaneous timer clear bit
GSCLR
Function
Read
0
1
"0" is always read out
Write
Counter will not be initialized
Counter will be initialized to "0000H"
simultaneously.
This bit is used to initialize the free-run timer 16-bit free-run timer specified by the timer synchronous activation
enable register (TCGSE) to "0000H".
When this bit is set to "1":
Initializes the 16-bit free-run timer of the free-run timer specified by the timer synchronous activation enable
register (TCGSE). At this time, the SCLR bit of the timer state control register (TCCS) of the free-run timer
specified by the timer synchronous activation enable register (TCGSE) will be set to "1".
When this bit is set to "0":
Cancels the instruction for initializing the 16-bit free-run timer of the free-run timer specified by the timer
synchronous activation enable register (TCGSE). At this time, the SCLR bit of the timer state control register
(TCCS) of the free-run timer specified by the timer synchronous activation enable register (TCGSE) will be
cleared to "0".
The value read out is always "0".
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Chapter 25: 16-Bit Free-Run Timer
4.1.2.
Timer Synchronous Activation Enable Register :
TCGSE
This section explains the bit structure of timer synchronous activation enable register.
The timer synchronous activation enable register (TCGSE) sets the free-run timer that enables the simultaneously
activation/clear.
TCGSE: Address 1203H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
FRT2
FRT1
FRT0
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
[bit7 to bit3] Reserved
Always write "0" to these bits.
[bit2 to bit0] FRT2 to FRT0: Simultaneous activation/clear setting bits
FRT2 to
FRT0
0
1
Function
Do not allow simultaneous activation/clear
Allow simultaneous activation/clear
These bits allow you to set the free-run timer that enables the simultaneous activation/clear.
When these bits are set to "0":
The free-run timer will not be activated nor cleared when configuring the timer synchronous activation register
(TCGS).
When these bits are set to "1":
The free-run timer will be activated or cleared when configuring the timer synchronous activation register (TCGS).
4.2.
Registers for the 16-bit Free-run Timer
Registers for the 16-bit free-run timer are explained.
The 16-bit free-run timer consists of the compare clear buffer register, the compare clear register, the timer data
register, and the timer state control register.
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Chapter 25: 16-Bit Free-Run Timer
4.2.1.
Compare Clear Buffer Register : CPCLRB/ Compare
Clear Register : CPCLR
This section explains the bit structures of the compare clear buffer register and compare clear register.
The compare clear buffer register (CPCLRB) is a 16-bit buffer register contained in the compare clear register
(CPCLR).
The CPCLRB and CPCLR registers are located at the same address.
CPCLRB0, 1, 2: Address 1204H, 120CH, 1214H (Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
Initial value
1
1
1
1
1
1
1
1
Attribute
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
Initial value
1
1
1
1
1
1
1
1
Attribute
W
W
W
W
W
W
W
W
[bit15 to bit0] CL15 to CL00: Compare clear value buffer bits
CL15 to CL00
Function
Compare clear value buffer
The compare clear buffer register is a buffer register located at the same address of the compare clear register
(CPCLR).
If the buffer function is disabled (BFE:bit23 of timer state control register (TCCS) is 0) or the free-run timer stops,
the value of the compare clear buffer register will be immediately transferred to the compare clear register.
If the buffer function is enabled, the value will be transferred to the compare clear register when the count value
"0" of the 16-bit free-run timer is detected.
Note:
Do not set "0000H" for the compare clear buffer register.
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing this register.
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Chapter 25: 16-Bit Free-Run Timer
CPCLR0, 1, 2: Address 1204H, 120CH, 1214H (Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
Initial value
1
1
1
1
1
1
1
1
Attribute
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
Initial value
1
1
1
1
1
1
1
1
Attribute
R
R
R
R
R
R
R
R
[bit15 to bit0] CL15 to CL00: Compare clear value bits
CL15 to CL00
Function
Compare clear value
The compare clear register is used for comparison with the count value of the 16-bit free-run timer.
In the up-count mode, if this register matches the count value of the 16-bit free-run timer, the 16-bit free-run timer
will be reset to "0000H".
In the up/down count mode, if this register matches the count value of the 16-bit free-run timer, the 16-bit free-run
timer will be converted from up count to down count or it will be converted from down count to up count when "0"
is detected.
Note:
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing this register.
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Chapter 25: 16-Bit Free-Run Timer
4.2.2.
Timer Data Register : TCDT0 to TCDT2
This section explains the bit structure of the timer data register.
The timer data register (TCDT) reads the count value of the 16-bit free-run timer. It is also possible to set the count
value of the 16-bit free-run timer.
TCDT0: Address 1206H (Access: Half-word, Word)
TCDT1: Address 120EH (Access: Half-word, Word)
TCDT2: Address 1216H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
T15
T14
T13
T12
T11
T10
T09
T08
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
T06
T05
T04
T03
T02
T01
T00
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
[bit15 to bit0] T15 to T00: Count value bits
T15 to T00
Function
Count value
The timer data register is used for reading the count value of the 16-bit free-run timer.
The count value will be cleared to "0000H" as soon as reset occurs.
The timer value can be set by writing a value to this register. However, a value needs to be written while the timer
is inactive (STOP:bit22 of timer state control register (TCCS) is 1).
The 16-bit free-run timer will be initialized as soon as any of the following occurs.
Reset
While the 16-bit free-run timer is active (STOP:bit22 of timer state control register (TCCS) is 0), the clear bit
(SCLR:bit20) of the timer state control register (TCCS) is 1
The timer count value matches the compare clear register in the up-count mode (MODE: bit21 of timer state
control register (TCCS) is 0)
Note:
The 16-bit free-run timer will not be initialized even when the clear bit (SCLR: bit20) of the timer state control
register (TCCS) is set to 1 while the 16-bit free-run timer is inactive (STOP: bit22=1 of timer state control register
(TCCS)).
When accessing the timer data register, use a half-word or word access instruction.
If a count value is written during the up/down counter mode (MODE:bit21=1 of timer state control register (TCCS)),
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Chapter 25: 16-Bit Free-Run Timer
an unintended counting may be performed.
To write a count value in the up/down counter mode (MODE:bit21=1 of timer state control register (TCCS)), perform
the following steps.
1.
2.
3.
4.
Stop the 16-bit free-run timer counter. (Writing "1" in STOP:bit21 of timer state control register (TCCS))
Set a count value for the timer data register.
Perform software clear. (Writing "1" in SCLR:bit20 of timer state control register (TCCS))
Start the 16-bit free-run timer counter.
4.2.3.
Timer State Control Register : TCCS0 to TCCS2
This section explains the bit structure of timer state control register.
The timer state control register (TCCS) controls the operation of the 16-bit free-run timer.
TCCS0: Address 1208H (Access: Byte, Half-word, Word)
TCCS1: Address 1210H (Access: Byte, Half-word, Word)
TCCS2: Address 1218H (Access: Byte, Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
ECKE
IRQZF
IRQZE
MSI2
MSI1
MSI0
ICLR
ICRE
0
0
R(RM1),
W
0
0
0
0
0
R/W
R,W
R,W
R,W
0
R(RM1),
W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
BFE
STOP
MODE
SCLR
CLK3
CLK2
CLK1
CLK0
0
R/W
1
R,W
0
R/W
0
R0,W
0
R/W
0
R/W
0
R/W
0
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MODE2
MSI5
MSI4
MSI3
Reserved
Initial value
Attribute
R/W
0
R0,W0
0
R0,W0
0
R0,W0
0
R0,W0
0
R/W
0
R,W
0
R,W
0
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1
R1,W1
1
R1,W1
1
R1,W1
Reserved
Initial value
Attribute
1
R1,W1
1
R1,W1
1
R1,W1
1
R1,W1
1
R1,W1
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Chapter 25: 16-Bit Free-Run Timer
[bit31] ECKE: Clock selection bit
ECKE
0
1
Function
Peripheral clock
External clock
This bit is used for selecting the peripheral clock or external clock as a count clock for the 16-bit free-run timer.
When this bit is set to "0":
The peripheral clock is selected. To select the count clock frequency, you will also need to select the clock
frequency selection bits (CLK3 to CLK0) of the TCCS register.
When this bit is set to "1":
The external clock (FRCK) is selected.
Note:
The count clock will be changed as soon as this bit is set. Therefore, change this bit while the output compare and
input capture are inactive.
[bit30] IRQZF: "0" detection interrupt flag bit
Function
IRQZF
0
1
Read
No "0" detected
"0" detected
Write
This bit is cleared
This bit remains unaffected
When the count value of the 16-bit free-run timer is set to "0000H", this bit will be set to "1".
When this bit is set to "0": This bit is cleared.
When this bit is set to "1": This bit remains unaffected.
This bit is cleared when the "0" detection interrupt clear signal is "H".
Note:
If a read-modify-write (RMW) instruction is executed, "1" is always read.
This bit will not be set by software clear (write "1" to the SCLR: bit20 of the timer state control register (TCCS))
while the 16-bit free-run timer is active (STOP:bit22 of timer state control register (TCCS) is 0).
In the up/down count mode (MODE: bit21 of the timer state control register (TCCS) is 1), this bit will be set to "1"
when an interrupt configured by the interrupt mask selection bits (MSI2 to MSI0: bit28 to bit26 of the timer state
control register (TCCS) is other than "000B") occurs. If no interrupt occurs, this bit will not be set to "1".
In the up count mode (MODE:bit21=0), this bit will be set every time "0" detection occurs regardless of the value of
MSI2 to MSI0: bit28 to bit26.
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set occur at the same
time, the hardware set takes precedence.
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Chapter 25: 16-Bit Free-Run Timer
[bit29] IRQZE: "0" detection interrupt request enable bit
IRQZE
Function
0
1
Interrupt request disabled
Interrupt request enabled
When this bit and interrupt flag bit (IRQZF: bit30) are set to "1", an interrupt request for CPU will be generated.
[bit28 to bit26] MSI2 to MSI0: Interrupt mask selection bits
MSI2
MSI1
MSI0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Function
An interrupt will be generated when there is a match for the first
time
An interrupt will be generated when there is a match for the second
time
An interrupt will be generated when there is a match for the third
time
An interrupt will be generated when there is a match for the fourth
time
An interrupt will be generated when there is a match for the fifth
time
An interrupt will be generated when there is a match for the sixth
time
An interrupt will be generated when there is a match for the seventh
time
An interrupt will be generated when there is a match for the eighth
time
When MODE2: bit11 of the timer state control register (TCCS) is 0:
These bits are used for configuring the mask count of compare clear interrupt in the up count mode (MODE:
bit21 of the timer state control register (TCCS) is 0). In the up/down count mode (MODE: bit21 of the timer
state control register (TCCS) is 1), they are used to configure the mask count of "0" detection interrupt.
When this bit is set to "0", the interrupt factor will not be masked.
When MODE2: bit11 of the timer state control register (TCCS) is 1:
In the up/down count mode (MODE: bit21 of the timer state control register (TCCS) is 1), these bits are used
to configure the mask count of "0" detection interrupt.
Settings of the up count mode (MODE: bit21 of the timer state control register (TCCS) is 0) are disabled.
Note:
The value read is a mask counter value.
If a read-modify-write instruction is executed, the value read is a mask register value.
The written data will be written to the mask register.
The written value to the mask register while the free-run timer is active (STOP: bit22 of the timer state control
register (TCCS) is 0) will be reloaded to the counter only when the mask counter becomes "0".
The written value to the mask register while the free-run timer is inactive (STOP: bit22 of the timer state control
register (TCCS) is 1) will be immediately reloaded to the counter.
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Chapter 25: 16-Bit Free-Run Timer
[bit25] ICLR: Compare clear interrupt flag bit
ICLR
0
1
Function
Read
No compare clear match
Compare clear match
Write
This bit is cleared
This bit remains unaffected.
This bit will be set to "1" when the compare clear value matches the 16-bit free-run timer value.
When this bit is set to "0": This bit is cleared.
When this bit is set to "1": This bit remains unaffected.
This bit will be cleared when the compare clear match interrupt clear signal is "H".
Note:
If a read-modify-write (RMW) instruction is executed, "1" is always read.
In the up count mode (MODE: bit21 of the timer state control register (TCCS) is 0), this bit will be set to "1" when an
interrupt configured by the interrupt mask selection bits occurs.
If no interrupt occurs, this bit will not be set to "1".
In the up/down count mode (MODE: bit21 of the timer state control register (TCCS) is 1), this bit will be set every
time a compare clear occurs regardless of the value of the MSI2 to MSI0 bits.
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set occur at the same
time, the hardware set takes precedence.
[bit24] ICRE: Compare clear interrupt request enable bit
ICRE
0
1
Function
Interrupt request disabled
Interrupt request enabled
When this bit and compare clear interrupt flag bit (ICLR: bit25) are set to "1", an interrupt request for CPU will be
generated.
[bit23] BFE: Compare clear buffer enable bit
BFE
0
1
Function
Invalidate the compare clear buffer
Validate the compare clear buffer
This bit is used for validating the compare clear buffer register (CPCLRB).
When this bit is set to "0":
Compare clear buffer register (CPCLRB) will be invalidated. Thus, you can write to the compare clear register
(CPCLR) directly.
When this bit is set to "1":
Compare clear buffer register (CPCLRB) will be validated. Data written to and retained in the compare clear
buffer register (CPCLRB) will be transferred to the compare clear register once the count value "0" from the
16-bit free-run timer has been detected.
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Chapter 25: 16-Bit Free-Run Timer
[bit22] STOP: Timer enable bit
STOP
0
1
Function
Enable counting (Start the counting)
Disable counting (Stop the counting)
This bit is used to start/stop counting of the 16-bit free-run timer.
When this bit is set to "0":
Start counting the 16-bit free-run timer.
When this bit is set to "1":
Stop counting the 16-bit free-run timer.
The free-run timer will not be initialized even when the SCLR: bit20 of the timer state control register (TCCS) is
set to "1" while the free-run timer is inactive (this bit=1).
The value to be reflected to this bit is the one specified at the GSTOP bit of the timer synchronous activation
register (TCGS) while the FRT bit of the timer synchronous activation enable register (TCGSE) is set to "1".
[bit21] MODE: Timer count mode bit
MODE
0
1
Function
Up count mode
Up/down count mode
This bit is used to select the count mode of the 16-bit free-run timer.
When this bit is set to "0":
The up count mode is selected. The timer continues to count up until the count value matches the compare clear
register to be reset to "0000H". After that, it starts counting up again.
When this bit is set to "1":
The up/down count mode is selected. The timer continues to count up until the count value matches the compare
clear register. After that, it will be converted to down count. Then, when the count value reaches to "0000 H", it will
change to up count once again.
You can write to this bit regardless of the timer is active or inactive. If the timer is active, the value written to this
bit will be transferred to the buffer. Then, when the timer value becomes "0000 H", the count mode changes based
on the buffer value.
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Chapter 25: 16-Bit Free-Run Timer
[bit20] SCLR: Timer clear bit
Function
SCLR
0
1
Read
Write
Counter will not be initialized.
Counter will be initialized to "0000H".
"0" is always read out.
This bit is used to initialize the 16-bit free-run timer to "0000H".
Initialization of the 16-bit free-run timer:
When this bit is set to "1" while the 16-bit free-run timer is active (STOP: bit22 of the timer state control register
(TCCS) is 0), the 16-bit free-run timer will be initialized to "0000H" in the next count clock. The 16-bit free-run
timer will not be initialized when this bit is set to "1" while the 16-bit free-run timer is inactive (STOP: bit22 of
the timer state control register (TCCS) is 1).
The value read out is always "0".
The value to be reflected to this bit is the one specified at the GSTOP bit of the timer synchronous activation
register (TCGS) while the FRT bit of the timer synchronous activation enable register (TCGSE) is set to 1.
Note:
Writing "1" to this bit will not generate the "0" detection interrupt.
If you write "0" to this bit prior to the next count clock after setting "1", the timer clear will not be executed.
[bit19 to bit16] CLK3 to CLK0 : Clock frequency selection bits
CLK
3
CLK
2
CLK
1
CLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
Function
φ=20M φ=10M
Hz
Hz
Count
Clock
φ=40M
Hz
φ=5MH
z
φ=2.5MH
z
0
1
φ
φ/2
25ns
50ns
50ns
100ns
100ns
200ns
200ns
400ns
400ns
800ns
0
1
0
1
0
φ/4
φ/8
φ/16
φ/32
φ/64
100ns
200ns
400ns
800ns
1.6μs
200ns
400ns
800ns
1.6μs
3.2μs
400ns
800ns
1.6μs
3.2μs
6.4μs
800ns
1.6μs
3.2μs
6.4μs
12.8μs
1.6μs
3.2μs
6.4μ
12.8μs
25.6μs
1
1
1
φ/128
3.2μs
6.4μs
12.8μs
25.6μs
0
0
0
φ/256
6.4μs
12.8μs
25.6μs
51.2μs
Other settings disabled
These bits are used to select the count clock frequency of the 16-bit free-run timer.
51.2μs
102.4μs
-
Note:
When setting CLK3 to CLK0 bits, confirm that the free-run timer stops firmly.
[bit15 to bit12] Reserved
Always write "0" to these bits.
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Chapter 25: 16-Bit Free-Run Timer
[bit11] MODE2 : Interrupt mask mode bit2
MODE2
MODE*
0
0
1
1
0
1
0
1
Function
Value set for MSI5 to MSI3 will be invalid
Value set for MSI5 to MSI3 will be invalid
Setting disabled (operation is not guaranteed)
Value set for MSI5 to MSI3 will be valid
In the up/down count mode (MODE: bit21 of the timer state control register (TCCS) is 1) of the 16-bit free-run
timer, this bit will be used to mask the "0" detection interrupt and compare clear interrupt independently.
During the MODE:bit21="1" of the timer state control register (TCCS) and if this bit is set to "1", the value
configured at MSI5 to MSI3: bit10 to bit8 of this register becomes valid and the compare clear interrupt is masked
for the number of times specified. For the mask count of "0" detection interrupt, the value configured at MSI2 to
MSI0: bit28 to bit26 of the timer state control register (TCCS) becomes valid.
Note:
During MODE:bit21="0" of the timer state control register (TCCS) and if this bit is set to "1", the operation is not
guaranteed.
[bit10 to bit8] MSI5 to MSI3 : Compare clear interrupt mask selection bits
MSI5
MSI4
MSI3
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
An interrupt occurs when there is a match for the first time
An interrupt occurs when there is a match for the second time
An interrupt occurs when there is a match for the third time
An interrupt occurs when there is a match for the fourth time
An interrupt occurs when there is a match for the fifth time
An interrupt occurs when there is a match for the sixth time
An interrupt occurs when there is a match for the seventh time
An interrupt occurs when there is a match for the eighth time
These bits, which are used to configure the mask count of compare clear interrupt, are valid only when MODE:
bit21 of the timer state control register (TCCS) as well as MODE2: bit11 of this register are 1. Value that can be
configured for the mask count of "0" detection interrupt is MSI2 to MSI0: bit28 to bit26 of the timer state control
register (TCCS).
When these bits are set to "000B", the compare clear interrupt factor will not be masked.
Note:
The value read is a mask counter value.
If a read-modify-write instruction is executed, the value read is a mask register value.
The written data will be written to the mask register.
The written value to the mask register while the free-run timer is active (STOP: bit22 of the timer state control
register (TCCS) is 0) will be reloaded to the counter only when the mask counter becomes "0".
The written value to the mask register while the free-run timer is inactive (STOP: bit22 of the timer state control
register (TCCS) is 1) will be immediately reloaded to the counter.
[bit7 to bit0] Reserved
Always write "1" to these bits.
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Chapter 25: 16-Bit Free-Run Timer
4.3.
Register for the Free-run Timer Selector
Register for the free-run timer selector is explained.
The free-run timer selector has the free-run timer selection register.
4.3.1.
Free-run Timer Selection Register : FRS
This section explains the bit structure of the free-run timer selection register.
The free-run timer selection register (FRS) sets any of 3 channels in the free-run timers for the input capture, output
compare, A/D activation compare respectively.
FRS0: Address 1234H (Access: Byte, Half-word, Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
Initial value
Attribute
1
1
1
1
1
1
1
1
R1,W1
R1,W1
R1,W1
R1,W1
R1,W1
R1,W1
R1,W1
R1,W1
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
OS51
OS50
OS41
OS40
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OS31
OS30
OS21
OS20
Reserved
Initial value
Attribute
Attribute
842
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OS11
OS10
OS01
OS00
Reserved
Initial value
Reserved
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 25: 16-Bit Free-Run Timer
[bit31 to bit24] Reserved
Always write "1" to these bits.
[bit23, bit22] Reserved
Always write "0" to these bits.
[bit21, bit20] OS51, OS50: Output compare free-run timer selector selection bits
OS51
OS50
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the output compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit19, bit18] Reserved
Always write "0" to these bits.
[bit17, bit16] OS41, OS40: Output compare free-run timer selector selection bits
OS41
OS40
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the output compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit15, bit14] Reserved
Always write "0" to these bits.
[bit13, bit12] OS31, OS30: Output compare free-run timer selector selection bits
OS31
OS30
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the output compare.
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Chapter 25: 16-Bit Free-Run Timer
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit11, bit10] Reserved
Always write "0" to these bits.
[bit9, bit8] OS21, OS20: Output compare free-run timer selector selection bits
OS21
OS20
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the output compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit7, bit6] Reserved
Always write "0" to these bits.
[bit5, bit4] OS11, OS10: Output compare free-run timer selector selection bits
OS11
OS10
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the output compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit3, bit2] Reserved
Always write "0" to these bits.
[bit1, bit0] OS01, OS00: Output compare free-run timer selector selection bits
OS01
OS00
0
0
1
0
1
0
Others
844
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Chapter 25: 16-Bit Free-Run Timer
These bits are used to configure the free-run timer assigned to the output compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
FRS1: Address 123AH (Access: Byte, Half-word, Word)
bit15
bit14
Reserved
Initial value
Attribute
bit12
IS31
IS30
bit11
bit10
Reserved
bit9
bit8
IS21
IS20
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IS11
IS10
IS01
IS00
Reserved
Initial value
Attribute
bit13
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
[bit15, bit14] Reserved
Always write "0" to these bits.
[bit13, bit12] IS31, IS30: Input capture free-run timer selector selection bits
IS31
IS30
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the input capture.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit11, bit10] Reserved
Always write "0" to these bits.
[bit9, bit8] IS21, IS20: Input capture free-run timer selector selection bits
IS21
IS20
0
0
0
1
Function
Free-run timer 0
Free-run timer 1
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Chapter 25: 16-Bit Free-Run Timer
IS21
IS20
1
0
Others
Function
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the input capture.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit7, bit6] Reserved
Always write "0" to these bits.
[bit5, bit4] IS11, IS10: Input capture free-run timer selector selection bits
IS11
IS10
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the input capture.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit3, bit2] Reserved
Always write "0" to these bits.
[bit1, bit0] IS01, IS00: Input capture free-run timer selector selection bits
IS01
IS00
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the input capture.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
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Chapter 25: 16-Bit Free-Run Timer
FRS2: Address 123CH (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
AS70
bit26
Reserved
bit25
bit24
AS61
AS60
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS51
AS50
AS41
AS40
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS31
AS30
AS21
AS20
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS11
AS10
AS01
AS00
Reserved
Initial value
AS71
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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Chapter 25: 16-Bit Free-Run Timer
FRS3: Address 1240H (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
848
AS150
bit26
Reserved
bit25
bit24
AS141
AS140
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS131
AS130
AS121
AS120
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS111
AS110
AS101
AS100
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS91
AS90
AS81
AS80
Reserved
Initial value
AS151
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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Chapter 25: 16-Bit Free-Run Timer
FRS4: Address 1244H (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
AS230
bit26
Reserved
bit25
bit24
AS221
AS220
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS211
AS210
AS201
AS200
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS191
AS190
AS181
AS180
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS171
AS170
AS161
AS160
Reserved
Initial value
AS231
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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Chapter 25: 16-Bit Free-Run Timer
FRS5: Address 12D0H (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
850
AS310
bit26
Reserved
bit25
bit24
AS301
AS300
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS291
AS290
AS281
AS280
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS271
AS270
AS261
AS260
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS251
AS250
AS241
AS240
Reserved
Initial value
AS311
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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Chapter 25: 16-Bit Free-Run Timer
FRS6: Address 12D4H (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
AS390
bit26
Reserved
bit25
bit24
AS381
AS380
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS371
AS370
AS361
AS360
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS351
AS350
AS341
AS340
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS331
AS330
AS321
AS320
Reserved
Initial value
AS391
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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FRS7: Address 12D8H (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
852
AS470
bit26
Reserved
bit25
bit24
AS461
AS460
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS451
AS450
AS441
AS440
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS431
AS430
AS421
AS420
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS411
AS410
AS401
AS400
Reserved
Initial value
AS471
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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Chapter 25: 16-Bit Free-Run Timer
FRS10: Address 12DCH (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
AS550
bit26
Reserved
bit25
bit24
AS541
AS540
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS531
AS530
AS521
AS520
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS511
AS510
AS501
AS500
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS491
AS490
AS481
AS480
Reserved
Initial value
AS551
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
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FRS11: Address 12E0H (Access: Byte, Half-word, Word)
bit31
bit30
Reserved
Initial value
Attribute
Attribute
Attribute
Attribute
AS630
bit26
Reserved
bit25
bit24
AS621
AS620
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
AS611
AS610
AS601
AS600
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
AS591
AS590
AS581
AS580
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AS571
AS570
AS561
AS560
Reserved
Initial value
AS631
bit27
0
Reserved
Initial value
bit28
0
Reserved
Initial value
bit29
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R/W
R/W
R0,W0
R0,W0
R/W
R/W
[bit31, bit30] Reserved
Always write "0" to these bits.
[bit29, bit28] AS471, AS470: A/D activation compare free-run timer selector selection bits
AS71/AS151/ AS70/AS150/
AS231/AS311/ AS230/AS310/
AS391/AS471 AS390/AS470
AS551/AS631 AS550/AS630
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
854
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Chapter 25: 16-Bit Free-Run Timer
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit27, bit26] Reserved
Always write "0" to these bits.
[bit25, bit24] AS461, AS460: A/D activation compare free-run timer selector selection bits
AS61/AS141/ AS60/AS140/
AS221/AS301/ AS220/AS300/
AS381/AS461 AS380/AS460
AS541/AS621 AS540/AS620
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit23, bit22] Reserved
Always write "0" to these bits.
[bit21, bit20] AS451, AS450: A/D activation compare free-run timer selector selection bits
AS51/AS131/ AS50/AS130/
AS211/AS291/ AS210/AS290/
AS371/AS451 AS370/AS450
AS531/AS611 AS530/AS610
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit19, bit18] Reserved
Always write "0" to these bits.
[bit17, bit16] AS441, AS440: A/D activation compare free-run timer selector selection bits
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AS41/AS121/ AS40/AS120/
AS201/AS281/ AS200/AS280/
AS361/AS441 AS360/AS440
AS521/AS601 AS520/AS600
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit15, bit14] Reserved
Always write "0" to these bits.
[bit13, bit12] AS431, AS430: A/D activation compare free-run timer selector selection bits
AS31/AS111/
AS30/AS110/
AS191/AS271/ AS190/AS270/
AS351/AS431 AS350/AS430
AS511/AS591 AS510/AS590
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit11, bit10] Reserved
Always write "0" to these bits.
[bit9, bit8] AS421, AS420: A/D activation compare free-run timer selector selection bits
AS21/AS101/
AS20/AS100/
AS181/AS261/ AS180/AS260/
Function
AS341/AS421
AS340/AS420
AS501/AS581
AS500/AS580
0
0
Free-run timer 0
0
1
Free-run timer 1
1
0
Free-run timer 2
Others
856
Setting disabled (operation is not guaranteed)
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Chapter 25: 16-Bit Free-Run Timer
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit7, bit6] Reserved
Always write "0" to these bits.
[bit5, bit4] AS411, AS410: A/D activation compare free-run timer selector selection bits
AS11/AS91/
AS10/AS90/
AS171/AS251/ AS170/AS250/
AS331/AS411 AS330/AS410
AS491/AS571 AS490/AS570
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
[bit3, bit2] Reserved
Always write "0" to these bits.
[bit1, bit0] AS401, AS400: A/D activation compare free-run timer selector selection bits
AS01/AS81/
AS00/AS80/
AS161/AS241/ AS160/AS240/
AS321/AS401 AS320/AS400
AS481/AS561 AS480/AS560
0
0
1
0
1
0
Others
Function
Free-run timer 0
Free-run timer 1
Free-run timer 2
Setting disabled (operation is not guaranteed)
These bits are used to configure the free-run timer assigned to the A/D activation compare.
Note:
Before configuring these bits, make sure to verify that the free-run timer is inactive.
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Chapter 25: 16-Bit Free-Run Timer
5. Operation
The section explains the operation description of the 16-bit free-run timer.
Free-run timer simultaneous activation
Of the 3-channel 16-bit free-run timers, the selected 16-bit free-run timers will be activated or cleared simultaneously.
16-bit free-run timer
The 16-bit free-run timer starts counting up from the value configured at the timer data register (TCDT) once the
count operation is enabled. The count value will be used as base time of the 16-bit output compare and 16-bit input
capture.
Free run-timer selector
You will be able to select the free run-timer input for the 16-bit output compare and 16-bit input capture respectively.
5.1.
Interrupt for the 16-bit Free-run Timer
Interrupt for the 16-bit free-run timer is explained.
Table 5-1 shows the interrupt control bits and interrupt factor of the 16-bit free-run timer.
Table 5-1 Interrupt Control Bits and Interrupt Factor of the 16-bit Free-run Timer
16-bit free-run timer
Compare clear
"0" detection
Interrupt request
flag bit
Interrupt request
enable bit
Interrupt factor
Timer state control register
(TCCS), ICLR: bit25
Timer state control register
(TCCS), ICRE: bit24
The 16-bit free-run timer value
matches the compare clear register
(CPCLR).
Timer state control register
(TCCS), IRQZF: bit30
Timer state control register
(TCCS), IRQZE: bit29
The 16-bit free-run timer value becomes
"0000H".
When the value of the 16-bit free-run timer matches the compare clear register (CPCLR), ICLR: bit25 of the timer
state control register (TCCS) will be set. If interrupt requests are enabled (ICRE: bit24 of TCCS is 1) while this bit is
set, an interrupt request is output to the interrupt controller.
When the timer value becomes "0000H", IRQZF: bit30 of the timer state control register (TCCS) will be set.
If interrupt requests are enabled (IRQZE: bit29 of TCCS is 1) while this bit is set, an interrupt request is output to the
interrupt controller.
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Chapter 25: 16-Bit Free-Run Timer
5.2.
Operation of the 16-bit Free-run Timer
Operation of the 16-bit free-run timer is explained.
The 16-bit free-run timer starts counting up from the value configured at the timer data register (TCDT) after reset.
The count value will be used as base time of the 16-bit output compare and 16-bit input capture.
5.2.1.
Timer Clear
This section explains timer clear.
The count value of the 16-bit free-run timer will be cleared in any of the followings:
When there is a match with the compare clear register by the up count mode (MODE:bit21 of TCCS register is 0).
When "1" is written to SCLR: bit20 of the TCCS register while it is active.
When "0000H" is written to the TCDT register while it is inactive.
When it has been reset.
The counter will be cleared as soon as it has been reset. In the case of a software clear or when there is a match with
the compare clear register, the counter will be cleared synchronously with the count timing.
Note:
Even when "1" is written to the SCLR: bit20 of the TCCS register while it is inactive, the count value of the 16-bit
free-run timer will not be cleared.
If "0000H" is written in TCDT register during the up/down count mode (MODE:bit21=1 of timer state control register
(TCCS)), an unintended counting may be performed.
See Section "4.2.2 Timer Data Register : TCDT0 to TCDT2" for the setting procedure of TCDT register during the
up/down count mode (MODE:bit21=1 of timer state control register (TCCS)).
Figure 5-1 Clear Timing of the 16-bit Free-run Timer
Peripheral clock
Compare clear
register value
N
Compare match
Count value
N
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0000 H
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Chapter 25: 16-Bit Free-Run Timer
5.2.2.
Timer Mode
This section explains timer mode.
For the 16-bit free-run timer, you will be able to select either one of the following modes:
Up count mode (MODE: bit21 of the TCCS register is 0)
Up/down count mode (MODE: bit21 of the TCCS register is 1)
In the up count mode, the counter starts counting from the timer data register (TCDT) configured in advance. It
continues to count up until the count value matches the value of the compare clear register (CPCLR). The counter will
be cleared to "0000H" and start counting up again.
In the up/down count mode, the counter starts counting from the timer data register (TCDT) configured in advance. It
continues to count up until the count value matches the value of the compare clear register (CPCLR). Then, the
counter changes counting method from up count to down count. The counter continues to count down until the
counter value reaches "0000H" and starts counting up again.
You will be able to write a value to the mode bit (MODE: bit21 of the TCCS register) whether the timer is active or
inactive. If the timer is active, the value written to this bit will be transferred to the buffer. Then, when the timer value
becomes "0000H", the count mode changes.
Figure 5-2 Changing the Timer Mode While the Timer Is Active
Count value
FFFFH
BFFFH
7FFF H
3FFF H
0000H
Time
Change to up count mode
Change to up/down count mode
Timer operation start
Compare clear
register
BFFFH
TCCS.MODE
860
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Chapter 25: 16-Bit Free-Run Timer
5.2.3.
Compare Clear Buffer
This section explains compare clear buffer.
The compare clear register (CPCLR) has a buffer function that can be enabled or disabled. When the buffer function
is enabled (BFE: bit23 of the TCCS register is 1), data written to the compare clear buffer register (CPCLRB) will be
transferred to the CPCLR register once the 16-bit free-run timer value "0" has been detected. When the buffer
function is disabled (BFE: bit23 of the TCCS register is 0), you will be able to write data to the CPCLR register
directly.
Figure 5-3 Operation in the Up Count Mode when the Compare Clear Buffer is Disabled
(BFE: bit23 of the TCCS register is 0)
Count value
FFFFH
BFFFH
7 FFF H
3FFF H
0000H
Time
Compare clear match
0 detection
"0"
detection
Timer operation start
Compare clear
buffer register
Compare clear
register
BFFFH
7FFF H
FFFF H
BFFFH
7FFF H
FFFF H
Figure 5-4 Operation in the Up Count Mode when the Compare Clear Buffer is Enabled
(BFE: bit23 of the TCCS register is 1)
Count value
FFFFH
BFFFH
7FFF H
3FFF H
0000H
Time
Compare clear match
0 detection
"0"
detection
Timer operation start
Compare clear
buffer register
Compare clear
register
BFFFH
BFFFH
7FFFH
7FFFH
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FFFF H
FFFFH
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Chapter 25: 16-Bit Free-Run Timer
Figure 5-5 Operation in the Up/Down Count Mode when the Compare Clear Buffer is Enabled
(BFE: bit23 of the TCCS register is 1)
Count value
Compare clear match
FFFFH
BFFFH
7FFF H
3FFF H
0000H
Time
0 detection
"0"
detection
Timer operation start
Compare clear
buffer register
Compare clear
register
5.2.4.
BFFFH
7FFF H
FFFF H
BFFF H
7FFF H
FFFFH
Timer Interrupt
This section explains timer interrupt.
For the 16-bit free-run timer, you will be able to generate the following two types of interrupt.
Compare clear interrupt
"0" detection interrupt
The compare clear interrupt will be generated when the timer value matches the value of the compare clear register.
The "0" detection interrupt will be generated when the timer value becomes "0000 H".
Note:
Software clear (SCLR: bit20 of the TCCS register is 1) does not generate the "0" detection interrupt.
Figure 5-6 Interrupt Generated in the Up Count Mode (MODE: bit21 of the TCCS register is 0)
Count value
N- 3
N- 2
N- 1
N
0
1
2
3
4
5
6
7
Compare clear
interrupt
0 detection
"0"
detection
interrupt
interrupt
862
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Chapter 25: 16-Bit Free-Run Timer
Figure 5-7 Interrupt Generated in the Up/Down Count Mode (MODE: bit21 of the TCCS register is 1)
Count value
N- 2
N- 1
N
N- 1
N- 2
Compare clear
interrupt
0
"0"detection
detection
interrupt
interrupt
5.2.5.
∬
∬
∬
2
1
0
1
2
3
∬
Interrupt Mask Function
This section explains the interrupt mask function.
You can mask either or both of the "0" detection interrupt and compare match interrupt. The following explains how
to mask either one of the interrupts.
You will be able to mask the interrupt request by setting the MSI2 to MSI0: bit28 to bit26 of the TCCS register.
MSI2 to MSI0 bits are 3-bit reload down register that reloads the value once the count value reaches "000 B". You
can also load the count value by writing the value to the MSI2 to MSI0 bits directly. Mask count is the value
configured at MSI2 to MSI0. When the MSI2 to MSI0 bits become "000 B", the interrupt request will not be
masked.
The interrupt request varies depending on the count mode (MODE: bit21 of the TCCS register). In the up count
mode, you will be able to mask the compare clear interrupts only while the "0" detection interrupts will be
generated every time "0" is detected. In the up/down count mode, you will be able to mask the "0" detection
interrupts only.
The following explains how to mask both types of interrupt requests.
Only when the free-run timer is in the up/down count mode, you will be able to mask both types of interrupts by
setting MODE2 of the TCCS register to 1 and MODE of the TCCS register to 1.
MSI2 to MSI0 bits of the TCCS register are used for masking the "0" detection interrupts and MSI5 to MSI3 bits of
the TCCS register are used for masking the compare clear interrupts.
Note:
Software clear (SCLR: bit20 of the TCCS register is 1) does not generate the "0" detection interrupt.
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Chapter 25: 16-Bit Free-Run Timer
Figure 5-8 Compare Clear Interrupt Masked in the Up Count Mode
Count value
FFFFH
BFFFH
7FFF H
3FFF H
0000H
Time
First
Second
time
time
Timer operation start
Third
time
Fourth
time
Fifth
time
Sixth
time
Seventh
time
Eighth
time
Ninth
time
0 detection
interrupt
"0"
detection
interrupt
Compare clear interrupt
TCCS.MSI2-MSI0=000B
TCCS.MSI2-MSI0=001B
TCCS.MSI2-MSI0=010B
detection
interrupts
and
compare
clear
interrupts
are are
cleared
by software.
Note: Both
Both 0"0"
detection
interrupts
and
compare
clear
interrupts
cleared
by software.
Figure 5-9 "0" Detection Interrupt Masked in the Up/Down Count Mode
Count value
First time
Second time
Third time
Fourth time
Fifth time
Sixth time
FFFFH
BFFFH
7FFF H
3FFF H
0000H
First time
Second time
Third time
Fourth time
Fifth time
Time
Sixth time
Timer operation start
Compare clear interrupt
0 detection
interrupt
"0"
detection
interrupt
TCCS.MSI2-MSI0=000B
TCCS.MSI2-MSI0=001B
TCCS.MSI2-MSI0=010B
Note: Both
Both 0"0"
detection
interrupts
and
compare
clear
interrupts
cleared
by software.
detection
interrupts
and
compare
clear
interrupts
are are
cleared
by software.
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Chapter 25: 16-Bit Free-Run Timer
Figure 5-10 "0" Detection Interrupt and Compare Clear Interrupt Masked in the Up/Down Count Mode
Count value
First time
Second time
Third time
Fourth time
Fifth time
Sixth time
FFFFH
BFFFH
7FFF H
3FFF H
0000H
First time
Second time
Third time
Fourth time
Fifth time
Time
Sixth time
Timer operation start
Compare clear interrupt
TCCS.MSI5-MSI3=000B
001
TCCS.MSI5-MSI3=01
BB
TCCS.MSI5-MSI3=010B
0 detection
interrupt
"0"
detection
interrupt
TCCS.MSI2-MSI0=000B
TCCS.MSI2-MSI0=001B
TCCS.MSI2-MSI0=010B
Note: Both 0"0"
detection
interrupts
and
compare
clear
interrupts
cleared
by software.
detection
interrupts
and
compare
clear
interrupts
are are
cleared
by software.
5.2.6.
Selected External Count Clock
This section explains the selected external count clock.
The 16-bit free-run timer will be incremented based on the input clock (peripheral clock or external clock). If you
select the external clock, the 16-bit free-run timer starts counting up by a rising edge after the external clock mode is
selected (ECKE: bit31 of the TCCS register is 1) when the initial value of external input is "1". After that, the timer
will count up by both edges. When the initial value of external input is "0", the timer starts counting up by a falling
edge. After that, the timer will count up by both edges.
Figure 5-11 Count Timing of the 16-bit Free-run Timer
External clock input
TCCS.ECKE
Count clock
Count value
N
N+1
N+2
N+3
N+4
Note:
Counting of the external clock input uses both edges of the external clock.
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Chapter 25: 16-Bit Free-Run Timer
5.3.
Operation of the Free-run Timer Selector
Operation of the free-run timer selector are explained.
The free-run timer selector is used to configure the free-run timer input for output compare, input capture, and A/D
activation compare.
This chip consists of three free-run timers, three (6-channel) output compares, and two (4-channel) input captures. In
addition, the A/D activation compare consists of 64 channels maximum, so you will be able to select any of the
following registers shown in the table below.
Table 5-2 Table for Registers
Resources
OCU0
OCU1
OCU2
OCU3
OCU4
OCU5
ICU0
ICU1
ICU2
ICU3
ADT0
ADT1
ADT2
ADT3
ADT4
ADT5
ADT6
ADT7
ADT8
ADT9
ADT10
ADT11
ADT12
ADT13
ADT14
ADT15
ADT16
ADT17
ADT18
ADT19
ADT20
ADT21
ADT22
ADT23
ADT24
866
Register
FRS0:OS0[1:0]
FRS0:OS1[1:0]
FRS0:OS2[1:0]
FRS0:OS3[1:0]
FRS0:OS4[1:0]
FRS0:OS5[1:0]
FRS1:IS0[1:0]
FRS1:IS1[1:0]
FRS1:IS2[1:0]
FRS1:IS3[1:0]
FRS2:AS0[1:0]
FRS2:AS1[1:0]
FRS2:AS2[1:0]
FRS2:AS3[1:0]
FRS2:AS4[1:0]
FRS2:AS5[1:0]
FRS2:AS6[1:0]
FRS2:AS7[1:0]
FRS3:AS8[1:0]
FRS3:AS9[1:0]
FRS3:AS10[1:0]
FRS3:AS11[1:0]
FRS3:AS12[1:0]
FRS3:AS13[1:0]
FRS3:AS14[1:0]
FRS3:AS15[1:0]
FRS4:AS16[1:0]
FRS4:AS17[1:0]
FRS4:AS18[1:0]
FRS4:AS19[1:0]
FRS4:AS20[1:0]
FRS4:AS21[1:0]
FRS4:AS22[1:0]
FRS4:AS23[1:0]
FRS5:AS24[1:0]
Remarks
16-bit output compare
16-bit input capture
A/D activation compare
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Chapter 25: 16-Bit Free-Run Timer
Resources
ADT25
ADT26
ADT27
ADT28
ADT29
ADT30
ADT31
ADT32
ADT33
ADT34
ADT35
ADT36
ADT37
ADT38
ADT39
ADT40
ADT41
ADT42
ADT43
ADT44
ADT45
ADT46
ADT47
ADT48
ADT49
ADT50
ADT51
ADT52
ADT53
ADT54
ADT55
ADT56
ADT57
ADT58
ADT59
ADT60
ADT61
ADT62
ADT63
Register
FRS5:AS25[1:0]
FRS5:AS26[1:0]
FRS5:AS27[1:0]
FRS5:AS28[1:0]
FRS5:AS29[1:0]
FRS5:AS30[1:0]
FRS5:AS31[1:0]
FRS6:AS32[1:0]
FRS6:AS33[1:0]
FRS6:AS34[1:0]
FRS6:AS35[1:0]
FRS6:AS36[1:0]
FRS6:AS37[1:0]
FRS6:AS38[1:0]
FRS6:AS39[1:0]
FRS7:AS40[1:0]
FRS7:AS41[1:0]
FRS7:AS42[1:0]
FRS7:AS43[1:0]
FRS7:AS44[1:0]
FRS7:AS45[1:0]
FRS7:AS46[1:0]
FRS7:AS47[1:0]
FRS8:AS48[1:0]
FRS8:AS49[1:0]
FRS8:AS50[1:0]
FRS8:AS51[1:0]
FRS8:AS52[1:0]
FRS8:AS53[1:0]
FRS8:AS54[1:0]
FRS8:AS55[1:0]
FRS9:AS56[1:0]
FRS9:AS57[1:0]
FRS9:AS58[1:0]
FRS9:AS59[1:0]
FRS9:AS60[1:0]
FRS9:AS61[1:0]
FRS9:AS62[1:0]
FRS9:AS63[1:0]
Remarks
A/D activation compare
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Chapter 25: 16-Bit Free-Run Timer
Table 5-3 Table for Setting Values
Setting
Free-run timer
value
00B
01B
10B
11B
FRT0 (initial state)
FRT1
FRT2
Setting disabled (operation is not guaranteed)
Note:
Before configuring the free-run timer selection register, make sure to verify that the free-run timer is inactive.
5.4.
Notes on Operating Specifications
Notes on operating specifications are explained.
5.4.1.
Notes at Accessing the Buffer Registers
This section explains notes to observe when accessing the buffer registers.
The CPCLR register in the free-run timer has a buffer function. Do not use a read-modify-write instruction when
accessing this register.
5.4.2.
Notes on Using the 16-bit Free-run Timer
This section explains the notes on using the 16-bit free-run timer.
Notes on setting by a program
When you execute reset, the timer value becomes "0000H", however, the "0" detection interrupt flag will not be
configured.
Since the timer mode bit (MODE of the TCCS register) has a buffer, the timer mode changed after the 0 detection
becomes valid.
Software clear (SCLR of the TCCS register is 1) initializes the timer, but it does not generate the 0 detection
interrupt.
When you start counting while the compare value and count value match, the compare clear flag will not be
configured.
Set the value other than "0000H" for the compare value. When setting the value, consider that the following
operation will happen.
When the timer mode bit (MODE in TCCS register) is in the up count mode, the timer value is updated to
"0000H" and then is fixed to "0000H". The "0" detection interrupt flag and the compare clear flag continue to
be set every count clock.
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Chapter 25: 16-Bit Free-Run Timer
When the timer mode bit (MODE in TCCS register) is in the up down count mode, the timer value repeats the
up count operation from "0000H" to "FFFFH". The "0" detection interrupt flag and the compare clear flag are
set when the timer value and "0000H" match.
Notes on interrupts
Always clear the interrupt flag (IRQZF) before setting the interrupt request enable bit (IRQZE) of the timer state
control register (TCCS) to "1".
Always clear the interrupt flag (ICLR) before setting the interrupt request enable bit (ICRE) of the timer state
control register (TCCS) to "1".
Notes on accessing the TCCS register
For the read-modify-write instruction, setting value will be read out from the MSI2 to MSI0/MSI5 to MSI3.
For the normal reading mode, the counter value will be read out from the MSI2 to MSI0/MSI5 to MSI3.
5.4.3.
Notes on Using the Free-run Timer Selector
This section explains notes on using the free-run timer selector.
Be sure to configure selection while the free-run timer is inactive.
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Chapter 26: 16-Bit Output Compare
This chapter explains the 16-bit output compare.
1.
Overview
2.
Features
3.
Configuration Diagram
4.
Registers
5.
Operation
Code : FS18-2v4-91528-3-E
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Chapter 26: 16-Bit Output Compare
1. Overview
This section explains the overview of the 16-bit output compare.
This product includes 6-channel 16-bit output compare.
2. Features
This section explains the features of the 16-bit output compare.
Functions of 16-bit Output Compare
16-bit output compare consists of six 16-bit compare registers (with selectable buffer registers), compare output
latch, 3 compare control registers, and compare mode control registers. When the 16-bit free-run timer value
matches a compare register, an interrupt is generated and the output level is inverted.
The 6 compare registers can be operated independently. An output pin and an interrupt flag correspond to each of
the compare registers.
Two compare registers can be used as a pair to control output pins. Two compare registers combined as a pair can
be used to invert the output pins.
The initial values for output pins can be set.
An interrupt can be generated when an output compare register matches the 16-bit free-run timer.
Any desired free-run timer channel can be set for each compare unit.
Any of free-run timers 0 through 2 can be selected as the input for output compare 0 through 5 among output
compare 6 channels. This can be set at the free-run timer selection register (FRS0). See "Free-run Timer Selection
Register: FRS" of "CHAPTER: 16-BIT FREE-RUN TIMER" for details.
The compare output for an output compare can be output from the waveform generator output pin.
The PPG timer's GATE signal output can be also controlled. See "CHAPTER: WAVEFORM GENERATOR" for
details.
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3. Configuration Diagram
This section explains the configuration diagram of the 16-bit output compare.
Configuration of 16-bit Output Compare
Figure 3-1 Configuration of 16-bit Output Compare (For ch.0, ch.1)
Output compare 0, 1
Output compare buffer register 0
(OCCPB0)
0 detection (for OCU0)
Compare clear (for OCU0)
(OCS01)
BUF0
BTS0
Output compare register 0
(OCCP0)
Compare output 0
Compare
circuit
Timer (for OCU0)
(OCS01)
ICP0
ICE0
Interrupt 0
Compare mode control register 01
(OCMOD0)
Output compare buffer register 1
(OCCPB1)
0 detection (for OCU1)
Compare clear (for OCU1)
Timer (for OCU1)
( OCS01)
BUF1
BTS1
Output compare register 1
(OCCP1)
(OCS01)
CMOD
Compare output 1
Compare
circuit
(OCS01)
ICP1
ICE1
Interrupt 1
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Chapter 26: 16-Bit Output Compare
4. Registers
This section explains the registers of the 16-bit output compare.
List of 16-bit Output Compare Registers
Table 4-1 List of 16-bit Output Compare Registers
Address
+0
+1
0x0000124C
0x00001250
Output compare buffer register 0
(OCCPB0),
Output compare register 0
(OCCP0)
Compare control register 01
(OCS01)
0x00001254
Output compare buffer register 2
(OCCPB2),
Output compare register 2
(OCCP2)
0x00001258
Compare control register 23
(OCS23)
0x0000125C
Output compare buffer register 4
(OCCPB4),
Output compare register 4
(OCCP4)
0x00001260
Compare control register 45
(OCS45)
4.1.
+2
+3
Output compare buffer register 1
(OCCPB1),
Output compare register 1
(OCCP1)
Compare mode
Reserved
control register 01
(OCMOD01)
Output compare buffer register 3
(OCCPB3),
Output compare register 3
(OCCP3)
Compare mode
control register 23
(OCMOD23)
Output compare buffer register 5
(OCCPB5),
Output compare register 5
(OCCP5)
Compare mode
Reserved
control register 45
(OCMOD45)
Reserved
16-bit Output Compare Registers
This section explains the registers of the 16-bit output compare.
The 16-bit output compare consists of output compare buffer registers, output compare registers, compare control
registers, and compare mode selection registers.
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4.1.1.
Output Compare Buffer Registers (OCCPB0 to
OCCPB5)/Output Compare Registers (OCCP0 to
OCCP5)
The bit configuration of the output compare buffer registers / the output compare registers is shown
below.
The output compare buffer register (OCCPB) is a 16-bit buffer register for the output compare register (OCCP).
The output compare register (OCCP) is a 16-bit register to be used for comparison with the count value of the 16-bit
free-run timer.
Both the OCCPB and OCCP registers are located at the same address.
OCCPB0, 2, 4: Address 124CH, 1254H, 125CH (Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
Initial value
0
0
0
0
0
0
0
0
Attribute
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
Initial value
0
0
0
0
0
0
0
0
Attribute
W
W
W
W
W
W
W
W
[bit15 to bit0] OP15 to OP00: Compare value buffer bits
Function
OP15 to OP00
Compare value buffer
The output compare buffer register is a buffer register for the output compare register (OCCP). If the buffer function
is disabled (BUF0: bit2 = 1 in the compare control register (OCS)) or the free-run timer stops, the value of the output
compare buffer register will be immediately transferred to the output compare register. If the buffer function is
enabled (BUF0: bit2 = 0 in the compare control register (OCS)), the value will be transferred to the output compare
register when a compare clear match or 0 is detected in accordance with the transfer selection bit (BTS0:bit2) in the
compare control register (OCS).
Note:
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing this register.
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OCCPB1, 3, 5: Address 124EH, 1256H, 125EH (Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
Initial value
0
0
0
0
0
0
0
0
Attribute
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
Initial value
0
0
0
0
0
0
0
0
Attribute
W
W
W
W
W
W
W
W
[bit15 to bit0] OP15 to OP00: Compare value buffer bits
Function
OP15 to OP00
Compare value buffer
The output compare buffer register is a buffer register for the output compare register (OCCP). If the buffer function
is disabled (BUF1: bit3 = 1 in the compare control register (OCS)) or the free-run timer stops, the value of the output
compare buffer register will be immediately transferred to the output compare register. If the buffer function is
enabled (BUF1: bit3 = 0 in the compare control register (OCS)), the value will be transferred to the output compare
register when a compare clear match or 0 is detected in accordance with the transfer selection bit (BTS1:bit3) in the
compare control register (OCS).
Note:
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing this register.
OCCP0, 2, 4: Address124CH, 1254H, 125CH (Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
Initial value
0
0
0
0
0
0
0
0
Attribute
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
Initial value
0
0
0
0
0
0
0
0
Attribute
R
R
R
R
R
R
R
R
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[bit15 to bit0] OP15 to OP00: Compare value bits
Function
OP15 to OP00
Compare value
The output compare register is a 16-bit register to be used for comparison with the count value of the 16-bit
free-run timer. Before enabling the operation of the 16-bit free-run timer, set a value in the output compare buffer
register (OCCPB).
When the value of the output compare register matches the count value of the 16-bit free-run timer, a compare
signal is generated and the output compare interrupt flag bit (IOP0: bit6 in the compare control register (OCS)) is
set. When the output level is set (OTD0: bit8 in the compare control register (OCS)), the compare output level for
the output compare register (OCCP) can be inverted.
When all the conditions listed below are met and a value that exceeds the peak value of the 16-bit free-run timer is
set to this register, the output compare output is "1" right after the buffer transfer. When this register is set to
"0000H", the output compare output is "0" right after the buffer transfer.
The free-run timer is in up/down count mode.
When the BUF bit in the compare control register (OCS) is "0" (buffer function enabled)
When the BTS bit in the compare control register (OCS) is "1" (transfer when there is a compare clear match)
When the CMD bit in the compare control register (OCS) is "1"
When the MOD bit in the compare mode control register (OCMOD) is "1"
When all the conditions listed above are not met, even if the value of this register matches the peak value of the
16-bit free-run timer in up/down mode, no compare signal is generated. The outcome is as follows according to the
settings of the CMD bit in the compare control register (OCS)
When the CMOD bit in the compare control register (OCS) is 1
When this register is set to "FFFFH", the output compare output is "1" regardless of the value of the 16-bit
free-run timer and the inversion mode.
When this register is set to "0000H", the output compare output is "0".
When the CMOD bit in the compare control register (OCS) is 0
When this register is set to "FFFFH", the output compare output is "0" regardless of the value of the 16-bit
free-run timer and the inversion mode.
When this register is set to "0000H", the output compare output is "1".
Note:
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing this register.
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OCCP1, 3, 5: Address 124EH, 1256H, 125EH (Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
Initial value
0
0
0
0
0
0
0
0
Attribute
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
Initial value
0
0
0
0
0
0
0
0
Attribute
R
R
R
R
R
R
R
R
[bit15 to bit0] OP15 to OP00: Compare value bits
Function
OP15 to OP00
Compare value
The output compare register is a 16-bit register to be used for comparison with the count value of the 16-bit
free-run timer. Before enabling the operation of the 16-bit free-run timer, set a value in the output compare buffer
register (OCCPB).
When the value of the output compare register matches the count value of the 16-bit free-run timer, a compare
signal is generated and the output compare interrupt flag bit (IOP1: bit7 in the compare control register (OCS)) is
set. When the output level is set (OTD1: bit9 in the compare control register (OCS)), the compare output level for
the output compare register (OCCP) can be inverted.
When all the conditions listed below are met and a value that exceeds the peak value of the 16-bit free-run timer is
set to this register, the output compare output is "1" right after the buffer transfer. When this register is set to
"0000H", the output compare output is "0" right after the buffer transfer.
The free-run timer is in up/down count mode.
When the BUF bit in the compare control register (OCS) is "0" (buffer function enabled)
When the BTS bit in the compare control register (OCS) is "1" (transfer when there is a compare clear match)
When the CMD bit in the compare control register (OCS) is "1"
When the MOD bit in the compare mode control register (OCMOD) is "1"
When all the conditions listed above are not met, even if the value of this register matches the peak value of the
16-bit free-run timer in up/down mode, no compare signal is generated. The outcome is as follows according to the
settings of the CMD bit in the compare control register (OCS).
When the CMOD bit in the compare control register (OCS) is 1
When this register is set to "FFFFH", the output compare output is "1" regardless of the value of the 16-bit
free-run timer and the inversion mode.
When this register is set to "0000H", the output compare output is "0".
When the CMOD bit in the compare control register (OCS) is 0
When this register is set to "FFFFH", the output compare output is "0" regardless of the value of the 16-bit
free-run timer and the inversion mode.
When this register is set to "0000H", the output compare output is "1".
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Note:
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing this register.
4.1.2.
Compare Control Register (OCS)
The bit configuration of the compare control register is shown below.
The compare control register (OCS) controls the output level, output level inversion mode, compare operation enable,
compare match interrupt enable, and compare match interrupt flag in OUT0 to OUT5.
OCS01: Address 1250H (Access: Byte, Half-word, Word)
OCS23: Address 1258H (Access: Byte, Half-word, Word)
OCS45: Address 1260H (Access: Byte, Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
Reserved
BTS1
BTS0
CMOD
0
1
1
0
0
R0,W0
R/W
R/W
R/W
bit7
bit6
bit5
IOP1
IOP0
0
R(RM1),
W
bit10
bit9
bit8
OTD1
OTD0
0
0
0
R/W0
R/W0
R,W
R,W
bit4
bit3
bit2
bit1
bit0
IOE1
IOE0
BUF1
BUF0
CST1
CST0
0
0
0
1
1
0
0
R(RM1),
W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
[bit15] Reserved
Always write 0 to this bit.
[bit14] BTS1: Buffer transfer selection bit
BTS1
Function
0
Transfer is activated when "0" is detected (ch.1).
1
Transfer is activated when a compare clear match occurs (ch.1).
This bit is used to select the timing of data transfer from the output compare buffer register (OCCPB1) to the
output compare register (OCCP1).
When this bit is set to "0":
Data transfer is activated when the count value of "0" is detected on the 16-bit free-run timer.
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When this bit is set to "1":
Data transfer is activated when a compare clear match occurs on the 16-bit free-run timer.
For ch.3 and 5, the operation is the same as ch.1.
[bit13] BTS0: Buffer transfer selection bit
BTS0
Function
0
Transfer is activated when "0" is detected (ch.0).
1
Transfer is activated when a compare clear match occurs (ch.0).
This bit is used to select the timing of data transfer from the output compare buffer register (OCCPB0) to the
output compare register (OCCP0).
When this bit is set to "0":
Data transfer is activated when the count value of "0" is detected on the 16-bit free-run timer.
When this bit is set to "1":
Data transfer is activated when a compare clear match occurs on the 16-bit free-run timer.
For ch.2 and 4, the operation is the same as ch.0.
[bit12] CMOD: Output level invert mode bit
CMOD
0
1
Function
For the compare mode control register:
MOD0=0
The compare output 0 is immediately
inverted when there is a match with the
output compare register (OCCP0).
For the compare mode control register:
MOD1=0
The compare output 1 is immediately
inverted when there is a match with the
output compare register (OCCP1).
For the compare mode control register:
MOD0=0
The compare output 0 is immediately
inverted when there is a match with the
output compare register (OCCP0).
For the compare mode control register:
MOD1=0
The compare output 1 is immediately
inverted when there is a match with the
output compare register (OCCP0 or
OCCP1).
For the compare mode control register: MOD0=1
or MOD1=1
Set to "1" when a match is detected in up-count
mode.
Reset to "0" when a match is detected in
down-count mode.
For the compare mode control register: MOD0=1
or MOD1=1
Set to "0" when a match is detected in up-count
mode.
Reset to "1" when a match is detected in
down-count mode.
This bit is used to switch the compare output level inversion mode immediately when a match is detected.
The compare output for an output compare can be output from the waveform generator output pin (RTO).
See "CHAPTER: WAVEFORM GENERATOR" for the output setting method.
When this bit is set to "0":
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When the compare mode control register: MOD0/MOD1=0
For the compare mode control register: MOD0=0
The compare output 0 is immediately inverted when there is a match between the 16-bit free-run timer and the
output compare register (OCCP6).
For the compare mode control register: MOD1=0
The compare output 1 is immediately inverted when there is a match between the 16-bit free-run timer and the
output compare register (OCCP7).
For the compare mode control register: MOD0/MOD1=1
Set to "1" when a match is detected in up-count mode.
Reset to "0" when a match is detected in down-count mode.
When this bit is set to "1":
When the compare mode control register: MOD0/MOD1=0
For the compare mode control register: MOD0=0
The compare output 0 is immediately inverted when there is a match between the 16-bit free-run timer and the
output compare register (OCCP0).
For the compare mode control register: MOD1=0
The compare output 1 is immediately inverted when there is a match between the 16-bit free-run timer and the
output compare register (OCCP0 or OCCP1).
When the output compare registers (OCCP0 and OCCP1) have the same value, the operation is the same as
when one compare register is used.
For the compare mode control register: MOD0/MOD1=1
Reset to "0" when a match is detected in up-count mode.
Set to "1" when a match is detected in down-count mode.
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
[bit11, bit10] Reserved
Always write 0 to these bits
[bit9] OTD1: Output level bit
OTD1
0
1
Function
Read
Output value of the compare output 1
Write
The compare output 1 outputs
The compare output 1 outputs
"0".
"1".
This bit is used to change the compare output 1 level of the output compare.
The initial value of the compare pin output is "0".
Be sure to stop the compare operation before writing a value to this bit. The value read from this bit is the output
compare value (compare output 1).
Note:
A value can be written to this bit when CST1: bit1=0 in the compare control register (OCS).
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[bit8] OTD0: Output level bit
OTD0
0
1
Function
Read
Write
The compare output 0 outputs
The compare output 0 outputs
Output value of the compare output 0
"0".
"1".
This bit is used to change the compare output 0 level of the output compare.
The initial value of the compare pin output is "0".
Be sure to stop the compare operation before writing a value to this bit. The value read from this bit is the output
compare value (compare output 0).
Note:
A value can be written to this bit when CST0: bit0=0 in the compare control register (OCS).
[bit7] IOP1: Compare match interrupt flag bit
IOP1
0
1
Function
Read
Write
No compare match interrupt occurs for the
output compare register (OCCP1).
Compare match interrupt occurs for the
output compare register (OCCP1).
This bit is cleared.
This bit remains unaffected.
This bit is an interrupt flag that indicates whether the value of the output compare register (OCCP1) matched that
of the 16-bit free-run timer.
This bit is set to "1" when the output compare register value matches the 16-bit free-run timer value.
An output compare interrupt occurs if this bit is set while the compare match interrupt enable bit (IOE1:bit5) is
enabled ("1").
When this bit is set to "0": This bit is cleared.
When this bit is set to "1": This bit remains unaffected.
For ch.3 and 5, the operation is the same as ch.1.
Note:
If a read-modify-write instruction is executed, "1" is always read.
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set occur at the same
time, the hardware set takes precedence.
[bit6] IOP0: Compare match interrupt flag bit
IOP0
0
1
Function
Read
No compare match interrupt occurs for the
output compare register (OCCP0).
Compare match interrupt occurs for the output
compare register (OCCP0).
Write
This bit is cleared.
This bit remains unaffected.
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This bit is an interrupt flag that indicates whether the value of the output compare register (OCCP0) matched that
of the 16-bit free-run timer.
This bit is set to "1" when the compare register value matches the 16-bit free-run timer value.
An output compare interrupt occurs if this bit is set while the compare match interrupt enable bit (IOE0:bit4) is
enabled ("1").
When this bit is set to "0": This bit is cleared.
When this bit is set to "1": This bit remains unaffected.
For ch.2 and 4, the operation is the same as ch.0.
Note:
If a read-modify-write instruction is executed, "1" is always read.
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set occur at the same
time, the hardware set takes precedence.
[bit5] IOE1: Compare match interrupt enable bit
IOE1
0
1
Function
Compare match interrupt is disabled for the output compare register (OCCP1).
Compare match interrupt is enabled for the output compare register (OCCP1).
This bit is used to enable an output compare interrupt for the output compare register (OCCP1).
An output compare interrupt occurs if the compare match interrupt flag bit (IOP1: bit7) is set while this bit is set to
"1".
For ch.3 and 5, the operation is the same as ch.1.
[bit4] IOE0: Compare match interrupt enable bit
IOE0
0
1
Function
Compare match interrupt is disabled for the output compare register (OCCP0).
Compare match interrupt is enabled for the output compare register (OCCP0).
This bit is used to enable an output compare interrupt for the output compare register (OCCP0).
An output compare interrupt occurs if the compare match interrupt flag bit (IOP0: bit6) is set while this bit is set to
"1".
For ch.2 and 4, the operation is the same as ch.0.
[bit3] BUF1: Compare buffer invalidating bit
BUF1
0
1
Function
Validates the compare buffer of the output compare register (OCCP1).
Invalidates the compare buffer of the output compare register (OCCP1).
This bit is used to invalidate the buffer function of the output compare register (OCCP1).
When this bit is set to "0": This buffer function is validated.
For ch.3 and 5, the operation is the same as ch.1.
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[bit2] BUF0: Compare buffer invalidating bit
BUF0
0
1
Function
Validates the compare buffer of the output compare register (OCCP0).
Invalidates the compare buffer of the output compare register (OCCP0).
This bit is used to invalidate the buffer function of the output compare register (OCCP0).
When this bit is set to "0": This buffer function is validated.
For ch.2 and 4, the operation is the same as ch.0.
[bit1] CST1: Compare operation enable bit
CST1
0
1
Function
Disables the compare operation of the output compare register (OCCP1).
Enables the compare operation of the output compare register (OCCP1).
This bit is used to enable the compare operation between the 16-bit free-run timer and the output compare register
(OCCP1).
Before enabling the compare operation, be sure to write a value to the output compare register (OCCP1) and the
timer data register of the free-run timer (TCDT[x], where x is a pertinent free-run timer).
For ch.3 and 5, the operation is the same as ch.1.
[bit0] CST0: Compare operation enable bit
CST0
0
1
Function
Disables the compare operation of the output compare register (OCCP0).
Enables the compare operation of the output compare register (OCCP0).
This bit is used to enable the compare operation between the 16-bit free-run timer and the output compare register
(OCCP0).
Before enabling the compare operation, be sure to write a value to the output compare register (OCCP0) and the
timer data register of the free-run timer (TCDT[x], where x is a pertinent free-run timer).
For ch.2 and 4, the operation is the same as ch.0.
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4.1.3.
Compare Mode Control Register (OCMOD)
The bit configuration of the compare Mode control register is shown below.
The compare mode control register (OCMOD) controls the output level upon detection of a compare match by
specifying to invert, set, or reset the output level.
OCMOD01: Address 1253H (Access: Byte, Half-word, Word)
OCMOD23: Address 125BH (Access: Byte, Half-word, Word)
OCMOD45: Address 1263 H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
bit1
bit0
MOD1
MOD0
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
[bit7 to bit2] Reserved
Always write 0 to these bits.
[bit1] MOD1: Compare match mode setting bit
MOD1
Function
0
Inverts the previous output value.
Sets the output value to "1" or resets it to "0" according to the setting of the CMOD bit in
the compare control register (OCS01).
1
This bit specifies the operation to be performed when a compare match is detected in the output compare output 1.
When this bit is set to "0", the output value is inverted upon a compare match.
When this bit is set to "1", the output value is set to "1" or reset to "0" upon a compare match. The switch between
setting and resetting is performed according to the CMOD bit (common to ch.0 and ch.1) in the compare control
register (OCS01).
For ch.3 and 5, the operation is the same as ch.1.
Note:
Be sure to stop the compare operation before writing a value to this bit.
[bit0] MOD0: Compare match mode setting bit
MOD0
0
1
Function
Inverts the previous output value.
Sets the output value to "1" or resets it to "0" according to the setting of the CMOD bit in
the compare control register (OCS01).
This bit specifies the operation to be performed when a compare match is detected in the output compare output 0.
When this bit is set to "0", the output value is inverted upon a compare match.
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When this bit is set to "1", the output value is set to "1" or reset to "0" upon a compare match. The switch between
setting and resetting is performed according to the CMOD bit (common to ch.0 and ch.1) in the compare control
register (OCS01).
For ch.2 and 4, the operation is the same as ch.0.
Note:
Be sure to stop the compare operation before writing a value to this bit.
5. Operation
This section explains the operations.
5.1 Interrupts for 16-bit Output Compare
5.2 Operation of 16-bit Output Compare
5.3 Notes on Using 16-bit Output Compare
5.1.
Interrupts for 16-bit Output Compare
This section explains the interrupts for 16-bit output compare.
Table 5-1 shows the interrupt control bits and interrupt factor of the 16-bit output compare.
Table 5-1 Interrupt Control Bits and Interrupt Factor of 16-bit Output Compare
16-bit output compare
Even-number channel
Odd-number channel
Interrupt request
flag bit
Interrupt request
enable bit
Interrupt factor
Compare control register
(OCS) IOP0:bit6
Compare control register
(OCS) IOE0:bit4
The 16-bit free-run timer value
matches the output compare
register 0 (OCCP0).
Compare control register
(OCS) IOP1:bit7
Compare control register
(OCS) IOE1:bit5
The 16-bit free-run timer value
matches the output compare
register 1 (OCCP1).
When the 16-bit free-run timer value matches the output compare register (OCCP), IOP1/IOP0: bit7/bit6 in the
compare control register (OCS) are set to "1". If interrupt requests are enabled (IOE1/IOE0: bit5/bit4 = 1 of OCS) in
this state, an interrupt request is output to the interrupt controller.
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5.2.
Operation of 16-bit Output Compare
This section explains the operation of 16-bit output compare.
The output compare is used to compare the value set in the specified compare clear register and the value of the 16-bit
free-run timer. When a match is detected, the interrupt flag is set and the output level is inverted. If there is a match
between the count peak and the compare register value while the free-run timer is in up/down count mode, the match
signal is ignored.
5.2.1.
Operation of 16-bit Output Compare (Inverted Mode,
MOD0= 0 in OCMOD01 Register)
The operation of 16-bit output compare (Inverted mode, MOD0= 0 in OCMOD01 register) is shown.
The compare operation can be performed in each of the channels (CMOD: bit12=0 in the compare control register
(OCS01)).
Figure 5-1 Example of Output Waveform When the Initial Output Value Is "0" and Compare Registers
0 and 1 Are Used Independently (With the free-run timer in up count mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare register 0
BFFFH
Compare register 1
7FFFH
Compare output 0
Compare output 1
Compare 0 interrupt
Compare 1 interrupt
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
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Figure 5-2 Example of Output Waveform When the Initial Output Value Is "0" and Compare Registers
0 and 1 Are Used Independently (With the free-run timer in up/down count mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare register 0
BFFFH
Compare register 1
7FFFH
Compare output 0
Compare output 1
Compare 0 interrupt
Compare 1 interrupt
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
The output level can be changed using a pair of compare registers (CMOD: bit12 = 1
in OCS01).
Figure 5-3 Example of Output Waveform When the Initial Output Value Is "0" and Compare Registers
0 and 1 Are Used as a Pair (With the free-run timer in up count mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare register 0
BFFFH
Compare register 1
7FFFH
Compare output 0
(for compare register 0)
Compare output 1
(for compare registers 0 and 1)
Compare 0 interrupt
Compare 1 interrupt
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
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Figure 5-4 Example of Output Waveform When the Initial Output Value Is "0" and Compare Registers
0 and 1 Are Used Simultaneously (With the free-run timer in up/down count mode)
Count value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Compare register 0
BFFFH
Compare register 1
7FFFH
Compare output 0
(for compare register 0)
Compare output 1
(for compare registers 0 and 1)
Compare 0 interrupt
Compare 1 interrupt
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
Output level when the compare buffer is invalid
Figure 5-5 Example of Output Waveform When the Compare Buffer Is Invalid
(With the free-run timer in up count mode)
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare clear match
Compare clear match
Timer operation start
Compare buffer
register 0
BFFFH
3FFFH
BFFFH
Compare register 0
BFFFH
3FFFH
BFFFH
Compare output 0
Compare 0 interrupt
For ch.1, 2, 3, 4 and 5, the operation is the same as ch.0.
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Output level when the compare buffer is selected upon a compare clear match
Figure 5-6 Example of Output Waveform When the Compare Buffer Is Valid
(With the free-run timer in up/down count mode)
Count value
Compare clear match
Compare clear match
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
0 detection
Timer operation start
Compare buffer
register 0
Compare register 0
BFFFH
BFFFH
3FFFH
BFFFH
3FFFH
BFFFH
Compare output 0
Compare 0 interrupt
For ch.1, 2, 3, 4 and 5, the operation is the same as ch.0.
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5.2.2.
Operation of 16-bit Output Compare (Set/Reset Mode,
MOD0 = 1 in OCMOD01 Register)
The operation of 16-bit output compare (Set/Reset mode, MOD0 = 1 in OCMOD01 register) is shown.
Figure 5-7 Operation of 16-bit Output Compare (Set/Reset Mode) #1
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare register 0
BFFFH
Compare register 12
7FFFH
Compare output 0
Compare output 1
2
Compare 0 interrupt
Compare 12 interrupt
Compare output 0: Setting up count and resetting down count
Compare output 1:
2: Resetting up count and setting down count
Note: Compare output 0 is left "1" for compare match. Compare output 12 is always "0".
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
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Chapter 26: 16-Bit Output Compare
Figure 5-8 Operation of 16-bit Output Compare (Set/Reset Mode) #2
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Compare register 0
BFFFH
Compare register 21
7FFFH
Compare output 0
Compare output 21
Compare 0 interrupt
Compare 21 interrupt
Compare output 0: Setting up count and resetting down count
Compare output 2:
1: Resetting up count and setting down count
For ch.2, 3 and ch.4, 5, the operation is the same as ch.0, 1.
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5.2.3.
16-bit Output Compare Timing
This section explains the 16-bit output compare timing.
When the free-run timer value matches the compare register value, the output compare generates a compare match
signal and inverts the output to generate an interrupt. When a compare match occurs, the output is inverted in
synchronization with the counter count timing.
Figure 5-9 Compare Register Interrupt Timing
Peripheral clock
Count value
N
N+1
N+2
N
Compare register
Compare match
Interrupt
Figure 5-10 Pin Output Change Timing
Peripheral clock
Count value
Compare register
N
N+1
N
N
N+1
N+2
N
Compare match
Compare output
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5.2.4.
Operation of 16-bit Output Compare and Free-run Timer
This section explains the operation of 16-bit output compare and free-run timer.
Case #1 where the free-run timer is in up count mode
Figure 5-11 Case #1 Where the Free-run Timer Is in Up Count Mode
Count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
BFFFH
0000H
0000H
BFFFH
0000H
CFFFH
CFFFH
0000H
0000H
Compare output
The timing of data transfer from the compare buffer of the output compare is
when there is a compare clear match of the free-run timer.
Case #2 where the free-run timer is in up count mode
Figure 5-12 Case #2 Where the Free-run Timer Is in Up Count Mode
Count value
CFFF H
BFFF H
0000 H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
BFFFH
0000H
0000H
BFFFH
0000H
BFFF H
0000H
CFFFH
CFFFH
0000H
0000H
Compare output
The timing of data transfer from the compare buffer of the output
compare is when "0" is detected on the free-run timer.
Case #1 where the free-run timer is in up/down count mode
The timing of data transfer from the compare buffer of the output compare is when there is a compare clear match
of the free-run timer.
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When there is an output compare output match, the output is in inverted mode.
Notes:
When the compare register value is set to "0000H", the output compare output is set to "1" regardless of the count
value of the free-run timer (or reset to "0" when CMOD: bit12 = 1 in OCS).
When the compare register value is set to "FFFFH", the output compare output is reset to "0" regardless of the
count value of the free-run timer (or set to "1" when CMOD: bit12 = 1 in OCS).
No comparison is made when there is a match between the compare clear register value of the free-run timer and
the compare register value of the output compare. Note that a compare match occurs only once at the time of
starting the free-run timer when the initial value of the free-run timer is same as the compare clear register value. If,
at this time, both the compare clear register value and the compare register value are set to "FFFF H", the output
compare output is reset to "0" regardless of the count value of the free-run timer.
Figure 5-13 Case #1 Where the Free-run Timer Is in Up/Down Count Mode
Count value
For CMOD=0
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
Compare output
initial value 0
Compare output
initial value 1
Case #2 where the free-run timer is in up/down count mode
The timing of data transfer from the compare buffer of the output compare is when "0" is detected on the free-run
timer.
When there is an output compare output match, the output is in inverted mode.
Notes:
When the compare register value is set to "0000H", the output compare output is set to "1" regardless of the count
value of the free-run timer (or reset to "0" when CMOD: bit12 = 1 in OCS).
When the compare register value is set to "FFFFH", the output compare output is reset to "0" regardless of the
count value of the free-run timer (or set to "1" when CMOD: bit12 = 1 in OCS).
No comparison is made when there is a match between the compare clear register value of the free-run timer and
the compare register value of the output compare. Note that a compare match occurs only once at the time of
starting the free-run timer when the initial value of the free-run timer is same as the compare clear register value. If,
at this time, both the compare clear register value and the compare register value are set to "FFFF H", the output
compare output is reset to "0" regardless of the count value of the free-run timer.
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Figure 5-14 Case #2 Where the Free-run Timer Is in Up/Down Count Mode
Count value
For CMOD=0
CFFF H
BFFF H
0000 H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFF H
0000H
Compare output
initial value 0
Compare output
initial value 1
Case #3 where the free-run timer is in up/down count mode
The timing of data transfer from the compare buffer of the output compare is when there is a compare clear match
of the free-run timer.
The output compare output is set to "1" upon a match in up count mode or reset to "0" upon a match in down count
mode (CMOD: bit12=0 in OCS01).
The ch.2, 3 and ch.4, 5 have the same operation.
Notes:
When the compare register value is set to "0000H", the output compare output is set to "1" regardless of the count
value of the free-run timer.
When the compare register value is set to "FFFFH", the output compare output is reset to "0" regardless of the
count value of the free-run timer.
No comparison is made when there is a match between the compare clear register value of the free-run timer and
the compare register value of the output compare. Note that a compare match occurs only once at the time of
starting the free-run timer when the initial value of the free-run timer is same as the compare clear register value. If,
at this time, both the compare clear register value and the compare register value are set to "FFFF H", the output
compare output is reset to "0" regardless of the count value of the free-run timer.
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Figure 5-15 Case #3 Where the Free-run Timer Is in Up/Down Count Mode
Count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
BFFFH
Compare register
BFFFH
CFFFH
BFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
Compare output
initial value 0
Compare output
initial value 1
Case #4 where the free-run timer is in up/down count mode
The timing of data transfer from the compare buffer of the output compare is when "0" is detected on the free-run
timer.
The output compare output is set to "1" upon a match in up count mode or reset to "0" upon a match in down count
mode (CMOD: bit12=0 in OCS01).
The ch.2, 3 and ch.4, 5 have the same operation.
Notes:
When the compare register value is set to "0000H", the output compare output is set to "1" regardless of the count
value of the free-run timer.
When the compare register value is set to "FFFFH", the output compare output is reset to "0" regardless of the
count value of the free-run timer.
No comparison is made when there is a match between the compare clear register value of the free-run timer and
the compare register value of the output compare. Note that a compare match occurs only once at the time of
starting the free-run timer when the initial value of the free-run timer is same as the compare clear register value. If,
at this time, both the compare clear register value and the compare register value are set to "FFFF H", the output
compare output is reset to "0" regardless of the count value of the free-run timer.
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Chapter 26: 16-Bit Output Compare
Figure 5-16 Case #4 Where the Free-run Timer Is in Up/Down Count Mode
Count value
CFFF H
BFFF H
0000 H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFF H
0000H
Compare output
initial value 0
Compare output
initial value 1
Case #5 where the free-run timer is in up/down count mode
The timing of data transfer from the compare buffer of the output compare is when there is a compare clear match
of the free-run timer.
The output compare output is reset to "0" upon a match in up count mode or set to "1" upon a match in down count
mode (CMOD: bit12=1 in OCS01).
The ch.2, 3 and ch.4, 5 have the same operation.
Notes:
When the compare register value is set to "0000H", the output compare output is reset to "0" regardless of the count
value of the free-run timer.
When the compare register value is set to "FFFFH", the output compare output is set to "1" regardless of the count
value of the free-run timer.
No comparison is made when there is a match between the compare clear register value of the free-run timer and
the compare register value of the output compare. Note that a compare match occurs only once at the time of
starting the free-run timer when the initial value of the free-run timer is same as the compare clear register value. If,
at this time, both the compare clear register value and the compare register value are set to "FFFF H", the output
compare output is reset to "0" regardless of the count value of the free-run timer.
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Figure 5-17 Case #5 Where the Free-run Timer Is in Up/Down Count Mode
Countカウント値
value
CFFF
CFFF
HH
BFFFH
BFFF
H
0000H
0000
H
時間
Time
コンペアバッファ
Compare
buffer
レジスタ
register
BFFFH
コンペアレジスタ
Compare
register
BFFFH
CFFFH
BFFFH
BFFFH
CFFFH
DFFFH
BFFFH
0000H
DFFFH
FFFFH
0000H
Compare output
コンペア出力
initial value 0
初期値0
コンペア出力
Compare output
初期値1
initial value 1
Compare
interrupt
コンペア割込み
注）上記の割込みの波形は割込み発生後、直ちにクリアした場合の波形です。
Note) The waveform of the above
interrupt is the waveform when the interrupt is cleared immediately after it occurs.
Case #6 where the free-run timer is in up/down count mode
The timing of data transfer from the compare buffer of the output compare is when "0" is detected on the free-run
timer.
The output compare output is reset to "0" upon a match in up count mode or set to "1" upon a match in down count
mode (CMOD: bit12=1 in OCS01).
The ch.2, 3 and ch.4, 5 have the same operation.
Notes:
When the compare register value is set to "0000H", the output compare output is reset to "0" regardless of the count
value of the free-run timer.
When the compare register value is set to "FFFFH", the output compare output is set to "1" regardless of the count
value of the free-run timer.
No comparison is made when there is a match between the compare clear register value of the free-run timer and
the compare register value of the output compare. Note that a compare match occurs only once at the time of
starting the free-run timer when the initial value of the free-run timer is same as the compare clear register value. If,
at this time, both the compare clear register value and the compare register value are set to "FFFF H", the output
compare output is reset to "0" regardless of the count value of the free-run timer.
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Figure 5-18 Case #6 Where the Free-run Timer Is in Up/Down Count Mode
Count value
CFFFH
BFFFH
0000H
Time
Compare buffer
register
Compare register
BFFFH
BFFFH
CFFFH
BFFFH
CFFFH
0000H
BFFFH
FFFFH
0000H
0000H
FFFFH
0000H
Compare output
initial value 0
Compare output
initial value 1
5.3.
Notes on Using 16-bit Output Compare
The notes on using 16-bit output compare is shown.
If the settings are CMOD = 1 and OCCP0 = OCCP1, OCCP2 = OCCP3 and OCCP4 = OCCP5, the port is inverted
only once when a compare match occurs.
Be sure to stop the compare operation before specifying the output level of the output compare output.
Stopping the free-run timer stops the compare operation because the output compare is in synchronization with the
free-run timer.
An interrupt operation occurs independently for each of OCU0 to OCU5 when the compare mode bit CMOD is set
to 1.
When the free-run timer is used as compare data for the output compare, the free-run timer clock frequency
(TCCSL.CLK[3:0]) cannot be set to "0000B".
Read-modify-write
The interrupt request flag bits (IOP0), (IOP1) are "1" when read using a read-modify-write instruction.
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This chapter explains the 16-bit input capture.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FS23-1v0-91528-3-E
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Chapter 27: 16-Bit Input Capture
1. Overview
This section explains the overview of the 16-bit input capture.
This product includes four 16-bit input capture channels.
2. Features
This section explains features of the 16-bit input capture.
Functions of 16-bit Input Capture
The 16-bit input capture consists of 4 independent external input pins, capture registers corresponding to this pin,
and capture control registers. When an edge of the input signal from the external pin is detected, the value of the
16-bit free-run timer can be stored in the capture register and an interrupt is generated simultaneously.
3 types of trigger edge (rising edge, falling edge, and both edges) of the external input signal can be selected and
there is a register that indicates whether the trigger edge is rising or falling.
The 4 input capture channels can be operated independently.
An interrupt is generated when a valid edge from the external input is detected.
Any desired free-run timer channel can be set for each compare unit.
There are 4 input capture channels, input capture 0 through 3, for which any of free-run timers 0 through 2 can be
selected as the input. This can be set at the free-run timer selection register (FRS1). See "Free-run Timer Selection
Register" of "CHAPTER: 16-BIT FREE-RUN TIMER" for details.
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Chapter 27: 16-Bit Input Capture
3. Configuration
This section explains the configuration of the 16-bit input capture.
Configuration of 16-bit Input Capture
Figure 3-1 Configuration of 16-bit Input Capture (For ch.0, ch.1)
Input capture 0,1
(ICS01)
IEI 0
Timer (ICU0)
Input capture data register 0
(IPCP0)
EG01, EG00
Edge Detection
External pulse input 0
( ICS01)
ICP0
ICE 0
Interrupt 0
( ICS01)
IEI1
Timer (ICU1)
Input capture data register 1
(IPCP1)
EG11, EG10
Edge Detection
External pulse input 0
( ICS01)
ICP1
ICE1
Interrupt 0
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Chapter 27: 16-Bit Input Capture
4. Registers
This section explains registers of the 16-bit input capture.
Table of external pins
Channel
External pin (ICU input)
MB91F52xR, MB91F52xU, MB91F52xM, MB91F52xY
0
ICU0_0/ICU0_1/ICU0_2/ICU0_3
1
ICU1_0/ICU1_1/ICU1_2/ICU1_3
2
ICU2_0/ICU2_1/ICU2_2/ICU2_3
3
ICU3_0/ICU3_1/ICU3_2/ICU3_3
List of 16-bit Input Capture Registers
Table 4-1 List of 16-bit Input Capture Registers
Address
+0
+1
0x0000127C
Input capture data register 0
(IPCP0)
0x00001280
Input capture state control register 01
(ICS01)
0x00001284
Input capture data register 2
(IPCP2)
0x00001288
Input capture state control register 23
(ICS23)
4.1.
+2
+3
Input capture data register 1
(IPCP1)
Reserved
LIN SYNCH FIELD
switching register
(LSYNS)
Input capture data register 3
(IPCP3)
Reserved
Reserved
16-bit Input Capture Registers
This section explains registers of the 16-bit input capture.
The 16-bit input capture consists of input capture data registers and input capture state control registers.
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Chapter 27: 16-Bit Input Capture
4.1.1.
Input Capture Data Register : IPCP0 to IPCP3
This section explains registers of the 16-bit input capture.
An input capture data register (IPCP) retains the count value of the free-run timer at the time of detection of an
effective edge of the input waveform.
IPCP0: Address 127CH (Access: Half-word, Word)
IPCP1: Address 127EH (Access: Half-word, Word)
IPCP2: Address 1284H (Access: Half-word, Word)
IPCP3: Address 1286H (Access: Half-word, Word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15 to bit0] CP15 to CP00: Free-run timer value
CP15 to CP00
Function
Free-run timer value
This register is used to store a free-run timer value at the time of detection of an effective edge of the
corresponding external pin input waveform.
The free-run timer value in the above explanation represents the operating state of a free-run timer for which the
input capture has been selected.
Note:
When accessing this register, use a half-word or word access instruction. No data can be written to this register.
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Chapter 27: 16-Bit Input Capture
4.1.2.
Input Capture State Control Register : ICS
The bit configuration for the input capture state control register is shown below.
An input capture state control register (ICS) is used to select an edge, enable interrupt request, and control an
interrupt request flag. It is also used to indicate an effective edge detected by the input capture.
ICS01: Address 1280H (Access: Byte, Half-word, Word)
ICS23: Address 1288H (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
Reserved
Initial value
Attribute
Initial value
Attribute
bit9
bit8
IEI1
IEI0
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
0
0
0
0
0
0
0
0
R (RM1),
W
R (RM1),
W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit10] Reserved
Always write 0 to these bits.
[bit9] IEI1: Effective edge indication bit
IEI1
0
1
Function
A falling edge is detected.
A rising edge is detected.
This effective edge indication bit for the capture register (IPCP) indicates that a rising or falling edge has been
detected.
When a falling edge is detected, this bit is set to "0".
When a rising edge is detected, this bit is set to "1".
This bit is read-only.
Note:
If EG11, EG10: bit3, bit2 of the input capture state control register (ICS) are set to 00 B, the value read from this
register is meaningless.
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Chapter 27: 16-Bit Input Capture
[bit8] IEI0: Effective edge indication bit
IEI0
0
1
Function
A falling edge is detected.
A rising edge is detected.
This effective edge indication bit for the capture register (IPCP) indicates that a rising or falling edge has been
detected.
When a falling edge is detected, this bit is set to "0".
When a rising edge is detected, this bit is set to "1".
This bit is read-only.
Note:
If EG01, EG00: bit1, bit0 of the input capture state control register (ICS) are set to 00 B, the value read from this
register is meaningless.
[bit7] ICP1: Interrupt request flag bit
ICP1
0
1
Function
Read
No effective edge is detected.
An effective edge is detected.
Write
This bit is cleared.
This bit remains unaffected.
This bit is used as an interrupt request flag for the input capture.
This bit is immediately set to "1" when an effective edge from the external input pin is detected.
An interrupt is immediately generated when an effective edge is detected while the interrupt request enable bit
(ICE1: bit5) is set.
When this bit is set to "0": This bit is cleared.
When this bit is set to "1": This bit remains unaffected.
Notes:
If a read-modify-write (RMW) instruction is executed, "1" is always read.
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set occur at the
same time, the hardware set takes precedence.
[bit6] ICP0: Interrupt request flag bit
ICP0
0
1
Function
Read
No effective edge is detected.
An effective edge is detected.
Write
This bit is cleared.
This bit remains unaffected.
This bit is used as an interrupt request flag for the input capture.
This bit is immediately set to "1" when an effective edge from the external input pin is detected.
An interrupt is immediately generated when an effective edge is detected while the interrupt request enable bit
(ICE0: bit4) is set.
When this bit is set to "0": This bit is cleared.
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Chapter 27: 16-Bit Input Capture
When this bit is set to "1": This bit remains unaffected.
Notes:
If a read-modify-write (RMW) instruction is executed, "1" is always read.
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set occur at the
same time, the hardware set takes precedence.
[bit5] ICE1: Interrupt request enable bit
ICE1
0
1
Function
Interrupt request disabled
Interrupt request enabled
This bit is used to enable an input capture interrupt request for the input capture.
An input capture interrupt is generated when an interrupt request flag bit (ICP1: bit7) is set while this bit is set to
"1".
[bit4] ICE0: Interrupt request enable bit
ICE0
0
1
Function
Interrupt request disabled
Interrupt request enabled
This bit is used to enable an input capture interrupt request for the input capture.
An input capture interrupt is generated when an interrupt request flag bit (ICP0: bit6) is set while this bit is set to
"1".
[bit3, bit2] EG11, EG10: Edge selection bits
EG11
EG10
0
0
1
1
0
1
0
1
Function
No edge is detected (Stopped).
A rising edge is detected.
A falling edge is detected.
Both edges are detected.
These bits are used to specify an effective edge polarity of the external input for the input capture.
These bits are also used to enable the operation of input capture.
[bit1, bit0] EG01, EG00: Edge selection bits
EG01
EG00
0
0
1
1
0
1
0
1
Function
No edge is detected (Stopped).
A rising edge is detected.
A falling edge is detected.
Both edges are detected.
These bits are used to specify an effective edge polarity of the external input for the input capture.
These bits are also used to enable the operation of input capture.
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Chapter 27: 16-Bit Input Capture
4.1.3.
LIN SYNCH FIELD Switching Register : LSYNS
The bit configuration of the LIN SYNCH FIELD switching register is shown below.
The LIN SYNCH FIELD switching register (LSYNS) is used for LIN linkage control.
LSYNS: Address 1283H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
Reserved
Initial value
Attribute
bit3
bit2
bit1
bit0
LSYN3
LSYN2
LSYN1
LSYN0
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
R/W
[bit7 to bit4] Reserved
Always write 0 to these bits.
[bit3 to bit0] LSYN3 to LSYN0: Input capture 3 to 0 input selection
LSYN3 to LSYN0
0
1
Function
External pin input (ICU3 to ICU0)
Input Lin Synch Field detection signals from the multi-function serial
interface ch.3 to ch.0.
These bits are used to enable Lin Synch Field from the multi-function serial interface ch.3 to ch.0.
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Chapter 27: 16-Bit Input Capture
5. Operation
This section explains the operation.
5.1 Interrupts for 16-bit Input Capture
5.2 Operation of 16-bit Input Capture
5.3 Notes on Using the 16-bit Input Capture
5.1.
Interrupts for 16-bit Input Capture
This section explains the interrupts for 16-bit input capture
Table 5-1shows the interrupt control bits and interrupt factor of the 16-bit input capture.
Table 5-1 Interrupt Control Bits and Interrupt Factor of 16-bit Input Capture
16-bit input capture
Even-number channel
Odd-number channel
Interrupt request
flag bit
Interrupt request
enable bit
Interrupt factor
Input capture state
control register (ICS) ICP0: bit6
Input capture state
control register (ICS) ICE0: bit4
An effective edge is detected
at the IN pin.
Input capture state
control register (ICS) ICP1: bit7
Input capture state
control register (ICS) ICE1: bit5
An effective edge is detected
at the IN pin.
With 16-bit input capture, when an effective edge is detected at a pin, the input capture state control register (ICS)
ICP1/ICP0: bit7/bit6 are set to "1". If interrupt requests are enabled (ICE1/ICE0:bit5 and bit4 of ICS01 is 1) with this
state, an interrupt request is output to the interrupt controller.
5.2.
Operation of 16-bit Input Capture
The operation of 16-bit Input capture is shown below.
Input capture is used to detect a specified effective edge. When an effective edge is detected, an interrupt flag is set
and the value of the 16-bit free-run timer is loaded to the capture register.
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Chapter 27: 16-Bit Input Capture
5.2.1.
Operation of 16-bit Input Capture
The operation of 16-bit Input capture is shown below.
Figure 5-1 Example of Input Capture Timing
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
IN0
IN1
IN2
Capture
register 0
Capture
register 1
Capture
register 2
3FFFH
7FFFH
BFFFH
3FFFH
Capture 0
interrupt
Capture 1
interrupt
Capture 2
interrupt
Generating interrupt by valid edge again
Clearing interrupt by software
Capture 0: rising edge
Capture 1: falling edge
Capture 2: both edges
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Chapter 27: 16-Bit Input Capture
5.2.2.
16-bit Input Capture Input Timing
The operation of 16-bit Input capture input timing is shown below.
Figure 5-2 Example of 16-bit Input Capture Timing for Input Signals
Peripheral clock
Count value
N
N+1
N+2
Input
Capture input
Capture signal
Capture
register
N+1
Interrupt
5.3.
Notes on Using the 16-bit Input Capture
This section explains the notes on using the 16-bit input capture.
If the input capture pin (IN) level is changed during the period from the bit setting of ICP1/ICP0 of the input capture
state control register (ICS01) to the processing of an interrupt routine, the ICP1/ICP0 effective edge indication bits
(IEI1 and IEI0 of ICS01 register) indicate the latest edge detected.
For ch.2, 3, the same notes as ch.0, 1 are required.
Input capture data register
Reading from the input capture data register must be performed in 16-bit or 32-bit access.
Read-modify-write
When reading is performed using a read-modify-write instruction, ICP1 and ICP0 of the input capture state control
register (ICS01) are read as "1".
For ch.2, 3, the same notes as ch.0, 1 are required.
Note on interrupts
Before the input capture state control register (ICS) interrupt request enable bits (ICE1/ICE0) are set to "1", be sure to
clear the interrupt flags (ICP1/ICP0).
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Chapter 28: Up/Down Counter
This chapter explains the up/down counter.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Interrupt
6.
Operation and Setting Procedure Examples
Code : FG20-1v0-91528-3-E
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Chapter 28: Up/Down Counter
1. Overview
This section explains the overview of the up/down counter.
The up/down counter counts up or down depending on the setting.
The 16-bit up/down counter can be used as an 8-bit up/down counter by using its low-order byte only.
The 8-bit up/down counter can count up or down in the range of "00 H" to "FFH". The 16-bit up/down counter can
count up or down in the range of "0000H" to "FFFFH".
This product incorporates up to 4 channels of the 16-bit up/down counter. However, only the low-order byte can be
used as the 8-bit up/down counter. So, the number of channels usable for 8 and 16 bits is up to 4 in total.
2. Features
This section explains the features of the up/down counter.
Counter mode: You can select one of the following two:
8-bit up/down counter (8-bit mode)
16-bit up/down counter (16-bit mode)
Operating mode: You can select one of the following three (four types):
Timer mode
The time is counted down in synchronization with the count clock.
As the count clock, the internal clock is used which is generated by dividing the peripheral clock (PCLK) by 2
or 8 using the prescaler.
Up/down count mode
Signals entered from the two external signal input pins are counted up or down. The edge to be counted can be
selected from among the rising edge, falling edge, and both edges.
Phase difference count mode
The phase difference of signals entered from the two external signal input pins are counted up or down.
The phase difference count mode is suitable for counting of encoders such as motors. This mode enables
high-precision counting of rotation angles, number of rotations and the like, by inputting outputs of phases A,
B, and Z of the encoder.
There are two types of phase difference count mode: the two-time multiplication mode and four-time
multiplication mode. The counting differs between the two mode types.
Table 2-1 lists the up/down counter operating modes.
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Chapter 28: Up/Down Counter
Table 2-1 Up/Down Counter Operating Modes
Operation mode
Count timing
Count direction
Timer mode
Internal clock
Count down
Up/down count mode
External clock
Count up/Count down
Phase difference count mode
(multiply-by 2/ multiply-by 4)
Phase of the input signal from an
external signal input pin
Count up/Count down
Reload compare function: You can select one of the following three:
Compare function
The compare function clears the counter and continues counting when counting reaches the preset value.
Reload function
The reload function loads the reload value and continues counting if an underflow occurs.
Reload compare function
Both the compare function and reload function can be combined for use.
Counting direction: The last counting direction (count up/count down) can be checked.
Interrupt request: An interrupt request can be generated in one of the following events:
The counting direction was inverted.
The counter value matches the preset value.
An overflow occurs.
An underflow (reload) occurs.
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Chapter 28: Up/Down Counter
3. Configuration
This section explains the configuration of the up/down counter.
Block Diagram of the Up/Down Counter
Figure 3-1 shows the block diagram of the up/down counter using ch.0 as an example.
Figure 3-1 Block Diagram of the Up/Down Counter
Peripheral bus
8-bit
CGE1
CGE0
To upper byte
CGSC
CTUT
ZIN pin
M16E
RCRL
Carry
Reload control
Edge/level detection
UCRE
UDCC
RLDE
Counter
clear
8-bit
CES
CES0
CMS
CMS0
UDCRL
CMPF
UDFF
AI N pin
OVFF
Count clock
BI N pin
Count
Clock selection
CSTR
UDF1
PCLK
UDIE
UDF0
CDCF
Prescaler
CITE
CLKS
CFIE
Interrupt output
RCRL : Reload compare register lower (RCRL0, RCRL1, RCRL2, RCRL3)
UDCRL : Up/down count register lower (UDCRL0, UDCRL1, UDCRL2, UDCRL3)
Reload compare register (RCR)
This register sets reload and compare values of the up/down counter.
As shown below, this counter consists of upper 8 bits and lower 8 bits.
To use the register in 8-bit mode, use the lower side.
Reload compare register upper (RCRH)
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Chapter 28: Up/Down Counter
Reload compare register lower (RCRL)
Up/down count register (UDCR)
This register operates as the counter for the up/down counter.
As shown below, this counter consists of upper 8 bits and lower 8 bits.
To use the register in 8-bit mode, use the lower side.
Up/down count register upper (UDCRH)
Up/down count register lower (UDCRL)
Counter control register (CCR)
This register controls the up/down counter.
Counter status register (CSR)
This register checks the up/down counter status or controls an interrupt request.
Count clock selection circuit
This circuit is used to select a count clock of the up/down counter.
Prescaler
In using the up/down counter in the timer mode, this prescaler is used to select a division ratio of the peripheral
clock (PCLK).
Clock
Table 3-1 lists the clocks used for the up/down counter.
Table 3-1 Clocks Used for the Up/Down Counter
Clock name
Operation clock
Description
Peripheral clock (PCLK)
Remarks
-
Internal clock (peripheral clock)
Generated by dividing the peripheral
clock (PCLK)
Counting of inputs from an external
pin
Input from AIN and BIN pins
Count clock
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Chapter 28: Up/Down Counter
4. Registers
This section explains the registers of the up/down counter.
Correspondence between Pins and Channels
Table 4-1 shows the correspondence between channels and pins.
Table 4-1 Correspondence between Pins and Channels
External signal input pins
Channel
MB91F52xR, MB91F52xU
MB91F52xM, MB91F52xY
AIN
BIN
ZIN
AIN
BIN
ZIN
0
AIN0_0/
AIN0_1
BIN0_0/
BIN0_1
ZIN0_0/
ZIN0_1/
ZIN0_2
AIN0_0/
AIN0_1
BIN0_0/
BIN0_1
ZIN0_0/
ZIN0_1/
ZIN0_2
1
AIN1_0/
AIN1_1
BIN1_0/
BIN1_1
ZIN1_0/
ZIN1_1
AIN1_0/
AIN1_1
BIN1_0/
BIN1_1
ZIN1_0/
ZIN1_1
2
−
−
−
AIN2_0/
AIN2_1
BIN2_0/
BIN2_1
ZIN2_0/
ZIN2_1
3
−
−
−
AIN3_0
BIN3_0
ZIN3_0
ch.0, ch.1, and ch.2 select the external pin used by the IO relocation function.
Registers Map
Table 4-2 lists the up/down counter register map.
Table 4-2 Registers Map
Registers
Register function
Address
+0
0x0F70
0x0F74
0x0F80
+1
RCRH0
RCRL0
CCR0
RCRH1
RCRL1
+2
+3
UDCRH0
UDCRL0
Reserved
CSR0
UDCRH1
UDCRL1
Reload compare register upper 0
Reload compare register lower 0
UP/down count register upper 0
UP/down count register lower 0
Counter control register 0
Counter Status register 0
Reload compare register upper 1
Reload compare register lower 1
UP/down count register upper 1
UP/down count register lower 1
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Chapter 28: Up/Down Counter
Registers
Register function
Address
+0
0x0F84
0x0F10
0x0F14
0x0F18
0x0F1C
918
+1
CCR1
RCRH2
RCRL2
CCR2
RCRH3
RCRL3
CCR3
+2
+3
Reserved
CSR1
UDCRH2
UDCRL2
Reserved
CSR2
UDCRH3
UDCRL3
Reserved
CSR3
Counter control register 1
Counter Status register 1
Reload compare register upper 2
Reload compare register lower 2
UP/down count register upper 2
UP/down count register lower 2
Counter control register 2
Counter Status register 2
Reload compare register upper 3
Reload compare register lower 3
UP/down count register upper 3
UP/down count register lower 3
Counter control register 3
Counter Status register 3
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Chapter 28: Up/Down Counter
4.1.
Reload Compare Register (RCR0, RCR1, RCR2, RCR3)
The bit configuration of the reload compare register is shown below.
This register sets reload and compare values of the up/down counter.
The reload value is the one from which counting starts at counting down; the compare value is compared with the
value counted at counting up (in other words, this value indicates that counting continues until this value is reached).
The reload and compare values are the same.
RCRH0 : Address 0F70H (Access : Half-word, Word)
RCRH1 : Address 0F80H (Access : Half-word, Word)
RCRH2 : Address 0F10H (Access : Half-word, Word)
RCRH3 : Address 0F18H (Access : Half-word, Word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RCRL0 : Address 0F71H (Access : Byte, Half-word, Word)
RCRL1 : Address 0F81H (Access : Byte, Half-word, Word)
RCRL2 : Address 0F11H (Access : Byte, Half-word, Word)
RCRL3 : Address 0F19H (Access : Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
As shown below, this register consists of a high-order byte and a low-order byte.
Reload compare register high-order (RCRH0, RCRH1, RCRH2, RCRH3)
Reload compare register low-order (RCRL0, RCRL1, RCRL2, RCRL3)
In the 16-bit mode, both byte values are used. In the 8-bit mode, the low-order value is used.
When the value written in this register is transferred to the up/down count register (UDCR), the up/down counter
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Chapter 28: Up/Down Counter
performs counting in the range from "0000 H" ("00H" for 8 bits) to that value set in this register.
Notes:
When "1" is written to the CTUT bit of the counter control register (CCR), a value set in this register can be
transferred to the up/down count register (UDCR). However, write the value in this CTUT bit of the counter
control register (CCR) while the up/down counter stops.
If the 16-bit mode is set with the M16E bit of the counter control register (CCR) (M16E=1), this register must
always be written by half-word access.
If the 8-bit mode is set with the M16E bit of the counter control register (CCR) (M16E=0), this register must
always be written in the reload compare register low-order side (RCRL) by byte access.
4.2.
Up/Down Count Register (UDCR0, UDCR1, UDCR2,
UDCR3)
The bit configuration of the up/down count register is shown below.
This register operates as the counter for the up/down counter. The counter value can be checked by reading these
registers.
UDCRH0 : Address 0F72H (Access : Half-word, Word)
UDCRH1 : Address 0F82H (Access : Half-word, Word)
UDCRH2 : Address 0F12H (Access : Half-word, Word)
UDCRH3 : Address 0F1AH (Access : Half-word, Word)
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
UDCRL0 : Address 0F73H (Access : Byte, Half-word, Word)
UDCRL1 : Address 0F83H (Access : Byte, Half-word, Word)
UDCRL2 : Address 0F13H (Access : Byte, Half-word, Word)
UDCRL3 : Address 0F1BH (Access : Byte, Half-word, Word)
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Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
As shown below, this register consists of a high-order byte and a low-order byte.
Up/down count register high-order (UDCRH0, UDCRH1, UDCRH2, UDCRH3)
Up/down count register low-order (UDCRL0, UDCRL1, UDCRL2, UDCRL3)
In the 8-bit mode, the high-order byte value is invalid.
The low-order byte of the up/down count register (UDCRL) must be read.
Notes:
This is a read-only register. To set a value in this register, transfer the reload compare register (RCR) value to this
register in the following procedure.
1. Write a value in the reload compare register (RCR)
2. Write the CSTR bit of the counter status register (CSR) to "0"
3. Write the CTUT bit of the counter control register (CCR) to "1"
If the 16-bit mode is set with the M16E bit of the counter control register (CCR) (M16E=1), this register must
always be read by half-word access.
If the 8-bit mode is set with the M16E bit of the counter control register (CCR) (M16E=0), the low-order side of
the up/down count register (UDCRL) must be read.
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4.3.
Counter Control Register (CCR0, CCR1, CCR2, CCR3)
The bit configuration of the counter control register is shown below.
This register controls the up/down counter operations.
CCR0 : Address 0F74H (Access : Byte, Half-word)
CCR1 : Address 0F84H (Access : Byte, Half-word)
CCR2 : Address 0F14H (Access : Byte, Half-word)
CCR3 : Address 0F1CH (Access : Byte, Half-word)
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
0
0
0
0
0
0
0
0
R/W
R(RM1),W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
CTUT
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
0
0
0
0
1
0
0
0
R0,W0
R0,W
R/W
R/W
R1,W
R/W
R/W
R/W
[bit15] M16E : 16-bit mode selection bit
This bit specifies that the up/down counter is used in 8-bit mode or in 16-bit mode.
Write value
Description
0
Uses the counter in the 8-bit mode (1 channel).
1
Uses the counter in the 16-bit mode (1 channel).
[bit14] CDCF : Count direction change flag bit
This bit indicates that the counting direction has changed from counting down to counting up or from counting up to
counting down once or more.
When this bit is "1" and the CFIE bit is set to "1", a counting direction change interrupt request is generated.
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CDCF
Read
Write
0
The counting direction is not changed.
This bit is cleared to "0".
1
The counting direction was changed once or more.
Ignored
Notes:
If the counter is reset, the counting down direction is set. Therefore, if the counting up is set immediately after the
reset, this bit is changed to "1".
If the counting direction is continuously changed in a short time, the counting direction may be returned to the
original direction and the UDF1 and UDF0 bits of counter status register (CSR) may not change.
[bit13] CFIE : Counting direction change interrupt enable bit
Sets whether or not to generate a counting direction change interrupt request when the counting direction is changed
(CDCF=1).
Write value
Description
0
Disables to generate a counting direction change interrupt request.
1
Enables to generate a counting direction change interrupt request.
[bit12] CLKS : Internal clock division selection bit
This bit specifies that the peripheral clock (PCLK) divided by the division ratio (set by this bit) is used as the count
clock when the timer mode is selected.
Write value
Description
0
Peripheral clock (PCLK) divided by 2
1
Peripheral clock (PCLK) divided by 8
Note:
This bit is valid only if the timer mode has been set with the CMS1 and CMS0 bits (CMS1, CMS0=00). This bit
setting is ignored if another operation mode has been selected.
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[bit11, bit10] CMS1, CMS0 : Operation mode select bits
Select an operation mode of the up/down counter as follows.
Timer mode
The timer is counted down in synchronous with the count clock.
Up/down count mode
Input signals entered from the two external signal input pins are counted up or down.
Phase difference count mode
A phase difference at the two external signal input pins is counted up or down. There are two types of phase
difference count mode: the two-time multiplication mode and four-time multiplication mode. The counting differs
between the two mode types.
CMS1
CMS0
Operation mode
0
0
Timer mode
0
1
Up/down count mode
1
0
Phase difference count mode (multiply-by-2)
1
1
Phase difference count mode (multiply-by-4)
[bit9, bit8] CES1, CES0 : Count clock edge selection bits
Select a detection edge of the AIN and BIN pins.
If the up/down count mode is selected, the signal is counted each time a signal edge selected by these bits is detected.
CES1
CES0
Detection edge
0
0
Disables signal edge detection
0
1
Falling edge
1
0
Rising edge
1
1
Both edges
Note:
These bits are valid only if the up/down count mode has been set by the CMS1 and CMS0 bits (CMS1,
CMS0=01). This bit setting is ignored if another operating mode has been selected.
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[bit7] Reserved bit
Write
This bit must always be written to "0".
Read
"0" is read.
[bit6] CTUT : Counter write bit
This bit transfers a value being set in the reload compare register (RCR) to the up/down count register (UDCR).
Read
CTUT
Write
0
Ignored
"0" is read.
1
The value is transferred.
Note:
When this bit is written to "1", the reload compare register (RCR) value is transferred. Therefore, if the CSTR bit
of counter status register (CSR) is "1" (the counter is operating), this bit must not be rewritten to "1".
[bit5] UCRE : Counter clear enable bit
This bit enables or disables to use the compare function.
The compare function clears the counter value to "0000 H" and continues counting if the counter value matches the
value being set in the reload compare register (RCR).
Write value
Description
0
Disables to use the compare function.
1
Enables to use the compare function.
Note:
This bit can only clear the counter value using the compare function.
This bit cannot control the following clearing operations.
Clear the counter when this device is reset.
Clear the counter when an effective edge signal is input from the ZIN pin (if CGSC bit is 0).
Clear the counter by writing the UDCC bit to "0". (Software-triggered clear).
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[bit4] RLDE : Reload enable bit
This bit enables or disables to use the reload function.
The reload function continues counting by reloading the value, being set in the reload compare register (RCR), onto
the counter when the counter has underflowed during counting down.
Write value
Description
0
Disables to use the reload function.
1
Enables to use the reload function.
[bit3] UDCC : Counter clear bit
Clears the counter value to "0000H".
UDCC
Read
0
Write
This bit is cleared to "0".
"1" is read.
1
Ignored
[bit2] CGSC : Counter clear/gate selection bit
This bit selects a function to be assigned to the ZIN pin as follows.
Counter clear function
Clears the counter value to "0000H" when an effective edge signal is entered from the ZIN pin.
Gate function
Operates the counter only when an effective level of signal is being entered from the ZIN pin.
Write value
Description
0
Counter clear function
1
Gate function
Note:
The ZIN pin functions if a combination of this bit and CGE1 and CGE0 bits is set.
Therefore, the CGE1 and CGE0 bits must always be set.
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[bit1, bit0] CGE1, CGE0 : Edge/level selection bits
These bits select an effective edge or an effective level of signal at the ZIN pin. The meaning of these bits depends on
the CGSC bit setting as follows.
If the counter clear function is selected by the CGSC bit (if CGSC=0)
An effective edge of signal is selected.
When a signal edge, selected by this bit, is detected at the ZIN pin, the counter value is cleared to "0000 H".
If the gate function is selected by the CGSC bit (if CGSC=1)
An effective level of signal is selected.
The counter operates only when a signal having the level, selected by this bit, is being entered from the ZIN pin.
CGE1 CGE0
4.4.
If the counter clear function is
selected (CGSC=0)
If the gate function is selected
(CGSC=1)
0
0
Disables signal edge detection.
Disables signal level detection
(disabled counting)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting disabled
Setting disabled
Counter Status Register (CSR0, CSR1, CSR2, CSR3)
The bit configuration of the counter status register is shown below.
This register is used to check the status of the up/down counter and control interrupt requests.
CSR0 : Address 0F77H (Access : Byte)
CSR1 : Address 0F87H (Access : Byte)
CSR2 : Address 0F17H (Access : Byte)
CSR3 : Address 0F1FH (Access : Byte)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R(RM1),W
R(RM1),W
R(RM1),W
R,WX
R,WX
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[bit7] CSTR : Count activation bit
This bit starts and stops the up/down counter.
Write value
Description
0
Stops the counting.
1
Starts the up/down counter.
[bit6] CITE : Compare result match interrupt enable bit
This bit sets whether or not to generate a compare result match interrupt request when the counter value matches the
value set in the reload compare register (RCR) (CMPF=1).
Write value
Description
0
Disables compare result match interrupt requests.
1
Enables compare result match interrupt requests.
[bit5] UDIE : Overflow/underflow interrupt enable bit
This bit sets whether or not to generate an overflow/underflow interrupt request when the up/down counter
overflows/underflows (OVFF/UDFF=1).
Write value
Description
0
Disables overflow/underflow interrupt requests.
1
Enables overflow/underflow interrupt requests.
[bit4] CMPF : Compare result match detection flag bit
This bit indicates that the counter value has matched the value set in the reload compare register (RCR).
When this bit is "1" and the CITE bit is set to "1", a compare result match interrupt request is generated.
CMPF
Read
Write
0
The value did not match.
This bit is cleared to "0".
1
The value matched.
Ignored
Note:
This bit changes to "1" in the following cases:
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The value matched in counting up.
The value of the reload compare register (RCR) is reloaded to the counter.
The value has already matched when the up/down counter is started.
[bit3] OVFF : Overflow detection flag bit
This bit indicates that the up/down counter has overflowed.
When this bit is "1" and the UDIE bit is set to "1", an overflow interrupt request is generated.
OVFF
Read
Write
0
No overflow has occurred.
This bit is cleared to "0".
1
An overflow has occurred.
Ignored
An overflow occurs if counting up is attempted when the counter value is "FFFF H".
[bit2] UDFF : Underflow detection flag bit
This bit indicates that the up/down counter has underfollowed.
When this bit is "1" and the UDIE bit is set to "1", an underflow interrupt request is generated.
UDFF
Read
Write
0
No underflow has occurred.
This bit is cleared to "0".
1
An underflow has occurred.
Ignored
An underflow occurs if counting down is attempted when the counter value is "0000 H".
[bit1, bit0] UDF1, UDF0 : Up/down flag bits
These bits indicate the last counting direction.
These bits are updated every time the up/down counter counts.
UDF1
UDF0
Description
0
0
No input
0
1
Count down
1
0
Count up
1
1
Count up/count down at the same time
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5. Interrupt
This section shows the interrupt of the up/down counter.
An interrupt request is generated in one of the following events:
The counting direction is inverted (Counting direction change interrupt request).
The counter value matches the value set in the reload compare register (RCR) (Compare result match interrupt
request).
An overflow occurs (Overflow interrupt request).
An underflow occurs (Underflow interrupt request).
Different interrupt requests are generated depending on the up/down counter operating mode.
Table 5-1 shows the correspondence between operating modes and interrupt requests.
Table 5-1 Correspondence between Operating Modes and Interrupt Requests
Timer mode
Up/down count
mode
Phase difference count
mode (multiply-by-2/
multiply-by-4)
Counting direction change
interrupt request
×
○
○
Compare result match interrupt
request
○
○
○
Overflow interrupt request
×
○
○
Underflow interrupt request
○
○
○
Interrupt request
Table 5-2 shows interrupts that can be used for the up/down counter.
Table 5-2 Up/Down Counter Interrupts
Interrupt request
Interrupt request
flag
Interrupt request
enable
Clearing of interrupt
request
Counting direction
change interrupt request
CDCF=1 in CCR
CFIE=1 in CCR
Writing of CDCF bit to "0" in
CCR.
Compare result match
interrupt request
CMPF=1 in CSR
CITE=1 in CSR
Writing of CMPF bit to "0" in
CSR.
Overflow interrupt
request
OVFF=1 in CSR
UDIE=1 in CSR
Writing of OVFF bit to "0" in
CSR.
Underflow interrupt
request
UDFF=1 in CSR
UDIE=1 in CSR
Writing of UDFF bit to "0" in
CSR.
CCR : Counter control register
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CSR : Counter status register
Notes:
Once an interrupt request is generated, the up/down counter stops operation until the interrupt request flag is
cleared.
The CMPF bit in the counter control register (CCR) changes to "1" if the value matches in counting up, if the value
of the reload compare register (RCR) is reloaded, or if the value has already matched when the up/down counter is
started.
For the clearing of the counter and the reload timing, see "■ Clear Events" and "■ Reload Event" in "Operation and
Setting Procedure Examples".
Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request
will be issued when the interrupt is enabled.
To enable the generation of an interrupt request, perform one of the following operations:
Clear the current interrupt request before enabling the generation of an interrupt request.
Clear the current interrupt request when enabling the interrupt.
For interrupt vector numbers used for issuing an interrupt request, see "APPENDIX B. List of Interrupt Vector".
Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00
to ICR47). For information on interrupt level setting, see the chapter of "Interrupt Control(Interrupt Controller)".
6. Operation and Setting Procedure Examples
This section explains the operation of the up/down counter. An example is also given to set operating
state.
Overview
Counter mode
Depending on the setting, the up/down counter can be used as a 16-bit up/down counter or an 8-bit up/down counter.
Set the counter mode in the M16E bit in the counter control register (CCR).
8-bit mode (M16E=0)
Only the up/down count register low-order bit (UDCRL) is used. Write the reload and compare values only to the
reload compare register low-order bit (RCRL) using byte access.
16-bit mode (M16E=1)
Both the high-order and low-order bytes of the up/down count register (UDCR) are used. Write the reload and
compare values to the reload compare register (RCR) using half-word access.
Operation mode
One of the following three modes (four types) can be selected as the operation mode of the up/down counter using the
CMS1 and CMS0 bits of the counter control register (CCR).
Timer mode (CMS1, CMS0=00)
The counter decrements from a preset value in synchronization with the count clock.
The count clock is generated by dividing the peripheral clock (PCLK) by 2 or 8 using the prescaler.
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Up/down count mode (CMS1, CMS0=01)
The counter increments or decrements based on signals supplied from the external signal input pin.
Phase difference count mode (multiply-by-two) (CMS1, CMS0=10)/Phase difference count mode
(multiply-by-four) (CMS1, CMS0=11)
The counter increments or decrements based on phase differences of signals supplied from the external signal
input pin. This mode is suitable for counting of encoders such as motors because it enables high-precision
counting of rotation angles and number of rotations and detection of the rotation direction by entering the encoder
A-phase to the AIN pin, B-phase to the BIN pin, and Z-phase to the ZIN pin.
Available Functions
Reload/compare functions
For the 8/16-bit up/down counter, the reload and compare functions can be enabled and disabled using the RLDE and
UCRE bits of the counter control register (CCR).
Reload function
When an underflow occurs during countdown, the value set in the reload compare register (RCR) is reloaded and
counting down is restarted. For the operations, see "■ Counting" in "6.1 Operation in Timer Mode".
Compare function
If the up/down counter value matches the value set in the reload compare register (RCR) (compare result match)
and further counting up is attempted, the value of the up/down counter is cleared to "0000 H" and counting up is
restarted. For the operations, see "■ Counting" in "6.2 Operation in Up/down Count Mode".
Reload compare function
This function is a combination of the reload and compare functions. The counter decrements and increments
between "0000H" and a value set in the reload compare register (RCR), enabling counting in any range. See "■
Counting" in "6.2 Operation in Up/down Count Mode".
This function is not available in timer mode.
Table 6-1 shows the setting method for the reload/compare functions.
Table 6-1 Setting Method for Reload/Compare Functions
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RLDE
UCRE
Description
0
0
Disables the reload and compare functions.
0
1
Disables the reload function.
Enables the compare function
1
0
Enables the reload function.
Disables the compare function.
1
1
Enables the reload and compare functions.
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Functions of ZIN pin
One of the following functions can be selected as the function of the ZIN pin using the CGSC bit of the counter
control register (CCR).
Counter clear function (CGSC=0)
If an effective edge is input from the ZIN pin during counting, the counter value is cleared to "0000 H".
Gate function (CGSC=1)
Operates the counter only when an effective level of signal is being entered from the ZIN pin.
Using the CGE1 and CGE0 bits of the counter control register (CCR), select either the effective edge if the counter
clear function is selected or the effective level if the gate function is selected.
If the counter clear function is
selected (CGSC=0)
If the gate function is selected
(CGSC=1)
CGE1
CGE0
0
0
Disables signal edge detection.
Disables signal level detection
(disabled counting)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Disables setting
Disables setting
Clear Events
The counter value is cleared to "0000H" in one of the following events.
This device is reset.
An effective edge is entered from the ZIN pin.
(If the CGSC bit of the counter control register (CCR) is set to make the ZIN pin work for the counter clear
function (CGSC=0).)
Software-triggered clear
The UDCC bit of the counter control register (CCR) is written to "0".
Clear due to the compare function
The counter value matches the value set in the reload compare register (RCR) and an attempt is made to increment
the counter.
(The counter is not cleared if an attempt is made to decrement or stop the counter.)
Clear due to overflow
Count up timing after the counter reaches "FFFF H" (or "FFH" in 8-bit mode).
The time the counter is cleared to "0000H" depends on the up/down counter operating status as follows.
If a clear event occurs during counting, the counter will be cleared in synchronization with the count clock.
Figure 6-1 shows clear event occurrence timing.
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Figure 6-1 Clear Event Occurrence Timing
UDCR
0065H
0066H
0000H
0001H
Synchronized with this clock pulse
Clear event
Count clock
UDCR : Up/down count register
If a clear event occurs during counting and the counting stops before the next count clock pulse is entered (the CSTR
bit of the counter status register (CSR) is "0"), the value will be cleared when the up/down counter stops.
Figure 6-2 shows the clear event occurrence timing.
Figure 6-2 Clear Event Occurrence Timing
UDCR
0065H
0066H
0000H
Clear event
Count clock
Count enable
Enable
Disable
UDCR : Up/down count register
Reload Event
The up/down counter value is reloaded in one of the following events.
The CTUT bit of the counter control register (CCR) is written to "1".
The reload function is activated to reload the value:
The timing the up/down counter value is reloaded depends on the up/down counter operating status as follows.
If a reload event occurs during counting:
The value will be reloaded in synchronization with the count clock.
If a reload event occurs except during counting:
The value will be reloaded when a reload event occurs.
Notes:
During counting, do not write "1" to the CTUT bit of the counter control register (CCR).
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If a reload event and a clear event occur at the same time, the clear event takes precedence.
6.1.
Operation in Timer Mode
This section explains the operation in timer mode.
Overview
In this mode, the up/down counter counts down from the value set in the reload compare register (RCR). The
frequency of the peripheral clock (PCLK) is divided by the prescaler to ensure that the result can be used as the count
clock.
It is also possible to use the reload function in order to reload the value of the reload compare register (RCR) when
the counter underflows, so that counting-down can be restarted from the reloaded value.
Counting
Normal operation
1.
2.
3.
The reload/compare value is set in the reload compare register (RCR).
When "1" is written to the CTUT bit of the counter control register (CCR), the set value is transferred to the
up/down count register (UDCR).
When "1" is written to the CSTR bit of the counter status register (CSR) to enable up/down counter operation,
the counter begins to count down from the value set in the reload compare register (RCR).
When the counter underflows, the UDFF bit of the counter status register (CSR) changes to "1". At this time, an
underflow interrupt request occurs if the UDIE bit of the counter status register is set to "1".
If the CGSC bit of the counter control register (CCR) is set to make the ZIN pin work for the gate function (CGSC=1),
the counter will only count while the effective level specified by the CGE1 and CGE0 bits is entered from the ZIN
pin.
For information on effective level setting, see "4.3 Counter Control Register (CCR0, CCR1, CCR2, CCR3)".
Note:
The minimum pulse width required at the ZIN pin is 2T (T is the cycle of the peripheral clock (PCLK)).
Operation performed when the reload function is in use
When the counter underflows during counting down, the UDFF bit of the counter status register (CSR) changes to "1".
At the time of the next count-down operation after the occurrence of underflow, the value of the reload compare
register (RCR) is reloaded to the counter, which then resumes counting down. At this time, an underflow interrupt
request occurs if the UDIE bit of the counter status register (CSR) is set to "1".
Figure 6-3 shows the operation performed when the reload function is in use.
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Chapter 28: Up/Down Counter
Figure 6-3 Operation Performed When the Reload Function Is in Use
(0FFFFH)
FFH
RCR
Reload (underflow interrupt
request generation)
Reload (underflow interrupt
request generation)
00H
Underflow
Underflow
RCR : Reload compare register
Note:
The value of the reload compare register (RCR) serves as both the reload value and compare value. Therefore, when a
value is reloaded to the reload compare register (RCR), the CMPF bit of the counter status register (CSR) also
changes to "1".
6.2.
Operation in Up/down Count Mode
This section explains the operation in up/down count mode.
Overview
In this mode, the up/down counter counts up/down with count clocks that are external signals entered from the AIN
and BIN pins.
When the external signal is entered from the AIN pin, the up/down counter counts up. When the external signal is
entered from the BIN pin, the up/down counter counts down.
Which edge of the external signal is used to trigger counting is determined by the CES1 and CES0 bits of the counter
control register (CCR) as follows.
Falling edge (CES1, CES0=01)
Rising edge (CES1, CES0=10)
Both edges (CES1, CES0=11)
In up/down count mode, the following three functions can be used.
Reload function
Compare function
Reload compare function
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Chapter 28: Up/Down Counter
Counting
Normal operation
When the effective edge is entered from the AIN pin while the counter is enabled to operate, the counter counts up.
When it is entered from the BIN pin while the counter is enabled to operate, the counter counts down.
When the counter changes its counting direction from counting up to counting down or vice versa, the CDCF bit of
the counter control register (CCR) changes to "1". At this time, a counting direction change interrupt request occurs if
the CFIE bit of the counter control register (CCR) is set to "1".
If the CGSC bit of the counter control register (CCR) is set to make the ZIN pin work for the gate function (CGSC=1),
the counter will only count while the effective level specified by the CGE1 and CGE0 bits is entered from the ZIN
pin.
For information on effective level setting, see "4.3 Counter Control Register (CCR0, CCR1, CCR2, CCR3)".
Note:
The minimum pulse width required at the AIN, BIN, and ZIN pins is 2T (T is the cycle of the peripheral clock
(PCLK)).
Operation performed when the reload function is in use
The operation is similar to that in timer mode. See "■ Counting" in "6.1 Operation in Timer Mode".
Operation performed when the compare function is in use
When the up/down counter value matches the value set in the reload compare register (RCR), the CMPF bit of the
counter status register (CSR) changes to "1". At this time, a compare result match interrupt request occurs if the CITE
bit of the counter status register (CSR) is set to "1".
If an attempt is made to further increment the counter in this condition, the up/down counter value is cleared to
"0000H" and counting-up restarts.
Figure 6-4 shows the operation performed when the compare function is in use.
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Chapter 28: Up/Down Counter
Figure 6-4 Operation Performed When the Compare Function is in Use
(0FFFFH)
Compare result
match
FFH
Compare result
match
RCR
00H
Counter clear
(Compare result match interrupt
request generation)
Counter clear
(Compare result match interrupt
request generation)
RCR : Reload compare register
Note:
If the compare function is in use, the up/down counter value will be cleared to "0000H" when one of the following
conditions is fulfilled.
The up/down counter value matches the value set in the reload compare register (RCR) (compare result match) and
further, the next counting up operation is performed.
However, a comparison result match does not cause clearing of the up/down counter value if one of the following
conditions is fulfilled:
The next operation is counting down.
The up/down counter is inactive.
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Chapter 28: Up/Down Counter
Operation performed when the reload compare function is in use
The reload function is used at counting down and the compare function is used at counting up.
Figure 6-5 shows operation performed when the reload compare function is in use.
Figure 6-5 Operation Performed When the Reload Compare Function is in Use
FFH
Compare
result match
RCR
Compare
result match
Reload
Reload
Reload
Compare
result match
00H
Counter clear
Counter clear
Underflow
Underflow
Underflow
Counter clear
RCR : Reload compare register
Checking counting direction
This mode involves both the counting up and counting down. So, the counting direction can be confirmed with the
UDF1 and UDF0 bits of the counter status register (CSR). These bits are rewritten each time counting occurs, so
enabling the current counting direction to be checked. These bits are useful to know the rotation direction during
motor control or the like.
Table 6-2 lists the counting directions indicated with the UDF1 and UDF0 bits.
Table 6-2 Correspondence between UDF1 and UDF0 Bits and Counting Directions
UDF1
UDF0
Count direction
0
0
No input
0
1
Counting down
1
0
Counting up
1
1
Concurrent generation of counting up and counting down
If the counting direction is inverted one or more times from the counting down to counting up or vice versa, the
CDCF bit of the counter control register (CCR) changes to "1". In this case, a direction change interrupt request can
also be generated. So, using the CDCF bit and the direction change interrupt request, you can check whether the
counting direction has been inverted.
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Chapter 28: Up/Down Counter
Note:
If the counting direction is continuously changed in a short period of time, the counting direction is restored and so
the direction indicated with the UDF1 and UDF0 bits of the counter status register (CSR) may be the same as the
direction set before the CDCF bit changes to "1".
6.3.
Operation in the Phase Difference Count Mode
(Multiply-by-Two)
This section explains the operation in the phase difference count mode (multiply-by-two).
Overview
This mode involves counting the phase difference of the signal input from two external signal input pins. This mode
is suitable to count the phase difference of phases A and B of encoder outputs.
When a rising edge or falling edge is detected from the BIN pin, the input level of the AIN pin is verified to count up
or down the phase difference of the BIN and AIN pins. If phase A advances faster than phase B, their phase
difference is counted up. If the former is delayed more than the latter, their phase difference is counted down.
Counting up or counting down is determined depending on the BIN pin detection edge and AIN pin input level.
Table 6-3 lists the count methods.
Table 6-3 Count Methods
BIN pin
AIN pin
Count Direction
"H" level
Counting up
"L" level
Counting down
"H" level
Counting down
"L" level
Counting up
Rising edge
Falling edge
Moreover, the following three types of functions can be used in the phase difference count mode (multiply-by-two).
Reload function
Compare function
Reload compare function
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Chapter 28: Up/Down Counter
Counting
Normal operation
If the counter is operable and the rising or falling edge is input from the BIN pin, the input level of the AIN pin is
detected and the counter counts up or down.
Figure 6-6 shows the operation in the phase difference count mode (multiply-by-two).
Figure 6-6 Operation in the Phase Difference Count Mode (Multiply-by-two)
AIN pin
BIN pin
Count value
0
+1
1
+1
2
+1
3
+1
4
+1
5
-1
4
+1
5
-1
4
-1
3
-1
2
-1
1
-1
0
If, however, the ZIN pin is set as the gate function (CGSC=1) with the CGSC bit of the counter control register
(CCR), counting occurs only while the effective level set with the CGE1 and CGE0 bits is input from the ZIN pin.
For information on effective level setting, see "4.3 Counter Control Register (CCR0, CCR1, CCR2, CCR3)".
Note:
The minimum pulse width required at the AIN, BIN, and ZIN pins is 2T (T is the cycle of the peripheral clock
(PCLK)).
Operation performed when the reload function is in use
The operation is similar to that in timer mode. See "■ Counting" in "6.1 Operation in Timer Mode".
Operation performed when the compare function is in use
The operation is similar to that in up/down count mode. See "■ Counting" in "6.2 Operation in Up/down Count
Mode".
Operation performed when the reload compare function is in use
The operation is similar to that in up/down count mode. See "■ Counting" in "6.2 Operation in Up/down Count
Mode".
Checking Counting Direction
The operation is similar to that in the up/down count mode. See "● Checking counting direction" in "6.2 Operation in
Up/down Count Mode".
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Chapter 28: Up/Down Counter
6.4.
Operation in the Phase Difference Count Mode
(Multiply-by-Four)
This section explains the operation in the phase difference count mode (multiply-by-four).
Overview
This mode involves counting the phase difference of the signal input from two external signal input pins. This mode
is suitable to count the phase difference of phases A and B of encoder outputs.
When a rising or falling edge is detected from the AIN or BIN pin, the input level from the other pin is verified to
count up or down the phase difference of the AIN and BIN pins.
Counting up or counting down is determined depending on the combination of the edge to be detected and the input
level.
Table 6-4 lists the count methods.
Table 6-4 Count Methods
Edge detection
pin
Detection
edge
Level check pin
Input level
Count direction
"H" level
Counting up
"L" level
Counting down
"H" level
Counting down
"L" level
Counting up
"H" level
Counting down
"L" level
Counting up
"H" level
Counting up
"L" level
Counting down
Rising edge
BIN pin
AIN pin
Falling edge
Rising edge
AIN pin
BIN pin
Falling edge
Moreover, the following three types of functions can be used in the phase difference count mode (multiply-by-four).
Reload function
Compare function
Reload compare function
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Chapter 28: Up/Down Counter
Counting
Normal operation
If the counter is operable and the rising or falling edge is input from the AIN or BIN pin, the input level of the other
pin is detected and the counter counts up or down.
Figure 6-7 shows the operation in the phase difference count mode (multiply-by-four).
Figure 6-7 Operation in the Phase Difference Count Mode (Multiply-by-four)
AIN pin
BIN pin
Count value
0
+1 +1
1 2
+1 +1
3 4
+1 +1
5 6
+1 +1
7 8
+1 +1
9 10
-1
9
+1
10
-1
9
-1 -1
8 7
-1 -1
6 5
-1 -1
4 3
-1 -1
2 1
If, however, the ZIN pin is set as the gate function (CGSC=1) with the CGSC bit of the counter control register
(CCR), counting occurs only while the effective level set with the CGE1 and CGE0 bits is input from the ZIN pin.
For information on effective level setting, see "4.3 Counter Control Register (CCR0, CCR1, CCR2, CCR3)".
Note:
The minimum pulse width required at the AIN, BIN, and ZIN pins is 2T (T is the cycle of the peripheral clock
(PCLK)).
Operation performed when the reload function is in use
The operation is similar to that in timer mode. See "■ Counting" in "6.1 Operation in Timer Mode".
Operation performed when the compare function is in use
The operation is similar to that in up/down count mode. See "■ Counting" in "6.2 Operation in Up/down Count
Mode".
Operation performed when the reload compare function is in use
The operation is similar to that in up/down count mode. See "■ Counting" in "6.2 Operation in Up/down Count
Mode".
Checking Counting Direction
The operation is similar to that in the up/down count mode. See "■ Checking counting direction" in "6.2 Operation in
Up/down Count Mode".
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Chapter 29: Real-Time Clock (RTC)
This chapter explains the real-time clock (RTC).
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Setting
7.
Q&A
8.
Sample Program
9.
Notes
Code : FS57-1v0-91528-3-E
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Chapter 29: Real-Time Clock (RTC)
1. Overview
This section explains the overview of the real-time clock (RTC).
The real-time clock (watch timer) consists of the timer control register, sub-second register, Second/ Minute/ Hour/
Day registers, 1/2 clock frequency divider, sub-second counter(22-bit down counter) and Second/ Minute/ Hour/ Day
counters. The real-time clock operates as the real-world timer and provides the real-world timer information.
Figure 1-1 Block Diagram (Overview)
RTC clock
Interrupt
Sub-second register
Second
1/2
divider
Sub-second counter
0.5 Second
Counter
Minute
Hour
Day
Counter
WOT External pin
2. Features
This section explains features of the real-time clock (RTC).
Function : Counts the number of days and time (day/ hour/ minute/ second) (operations are kept on in the
watch mode too.)
The default values of the number of days and time can be set and modified.
Operation clock : RTC clock (See "CHAPTER: CLOCK" for the selection of the clock source of the RTC clock.
See "CHAPTER: RTC/WDT1 CALIBRATION" for the correction when a
sub-clock(only dual clock product) is selected as a source.)
Interrupt : Interrupts can be generated based on five intervals: 0.5second, 1second, 1minute, 1hour, and
1day. In addition, interrupts at any interval (from short interval to long interval) can be
generated by changing the sub-second value.
Note:
If the real-time clock is used as source for recovering from the watch mode with power-shutdown, set the
interrupt level to ‘31’, before CPU state changes to the watch mode with power-shutdown.
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Chapter 29: Real-Time Clock (RTC)
3. Configuration
This section explains the configuration of the real-time clock (RTC).
Figure 3-1 Configuration Diagram
INTE2
0
1
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Chapter 29: Real-Time Clock (RTC)
4. Registers
This section explains registers of the real-time clock (RTC).
Table 4-1 Registers Map
Registers
Address
Register function
+0
+1
0x055C
Reserved
Reserved
0x0560
Reserved
WTCR
RTC control register
0x0564
Reserved
WTBR
Sub-second register
WTSR
Day/Hour/Minute/Second
registers(hour)
Day/Hour/Minute/Second
registers(minute)
Day/Hour/Minute/Second
registers(second)
0x0568
WTHR
WTMR
+2
+3
WTDR
Reserved
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Day/Hour/Minute/Second
Registers(day)
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Chapter 29: Real-Time Clock (RTC)
4.1.
RTC Control Register : WTCR
The bit configuration of the RTC control register is shown below.
This register controls the operations of the real-time clock module.
WTCRH : Address 0561H (Access: Byte)
WTCRM : Address 0562H (Access: Byte, Half-word)
WTCRL : Address 0563H (Access: Byte, Half-word)
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
-
-
-
-
-
-
INTE4
INT4
-
-
-
-
-
-
0
0
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
R(RM1), W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
INTE3
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
0
0
0
0
0
0
0
0
R/W
R(RM1), W
R/W
R(RM1), W
R/W
R(RM1), W
R/W
R(RM1), W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RUN
UPDT
Reserved
ST
Initial value
Attribute
Initial value
Attribute
Reserved Reserved Reserved Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W0
R/W0
R/W0
R/W0
R,WX
R(RM0),W
R/W0
R/W
This register will be initialized by all reset factors without the return reset from watch mode (power- shutdown).
[bit23 to bit18] - : Undefined
The read value is always "1". The data writing does not affect the operation.
[bit17] INTE4 : 0.5 second interrupt request enable
INTE4
948
Operation
0
0.5 second interrupt request disabled
1
0.5 second interrupt request enabled
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Chapter 29: Real-Time Clock (RTC)
[bit16] INT4 : 0.5 second interrupt request flag
State
INT4
Read
Write
0
0.5 second interrupt request not
generated
Flag clear
1
0.5 second interrupt request generated
This does not affect the operations
When the frequency division output of the borrow signal of the sub-second counter (22-bit down counter) is enabled,
the flag will be set to "1".
[bit15] INTE3 : 1 day interrupt request enable
INTE3
Operation
0
1 day (24 hours) interrupt request disabled
1
1 day (24 hours) interrupt request enabled
[bit14] INT3 : 1 day interrupt request flag
State
INT3
Read
Write
0
1 day (24 hours) interrupt request not
generated
Flag clear
1
1 day (24 hours) interrupt request
generated
This does not affect the operations
When overflow occurs in the hour counter, the flag will be set to "1".
[bit13] INTE2 : 1 hour interrupt request enable
INTE2
Operation
0
1 hour interrupt request disabled
1
1 hour interrupt request enabled
[bit12] INT2 : 1 hour interrupt request flag
State
INT2
Read
Write
0
1 hour interrupt request not generated
Flag clear
1
1 hour interrupt request generated
This does not affect the operations
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Chapter 29: Real-Time Clock (RTC)
When overflow occurs in the minute counter, the flag will be set to "1".
[bit11] INTE1 : 1 minute interrupt request enable
INTE1
Operation
0
1 minute interrupt request disabled
1
1 minute interrupt request enabled
[bit10] INT1 : 1 minute interrupt request flag
Operation
INT1
Read
Write
0
1 minute interrupt request not generated
Flag clear
1
1 minute interrupt request generated
This does not affect the operations
When overflow occurs in the second counter, the flag will be set to "1".
[bit9] INTE0 : 1 second interrupt request enable
INTE0
Operation
0
1 second interrupt request disabled
1
1 second interrupt request enabled
[bit8] INT0 : 1 second interrupt request flag
State
INT0
Read
Write
0
1 second interrupt request not generated
Flag clear
1
1 second interrupt request generated
This does not affect the operations
When overflow occurs in the 0.5 second counter, the flag will be set to "1".
[bit7 to bit4] Reserved
These bits must always be written to "0".
[bit3] RUN : Operation state
RUN
950
State
0
Real-time clock module is stopped
1
Real-time clock module is running
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Chapter 29: Real-Time Clock (RTC)
[bit2] UPDT : Update
State/Operation
UPDT
Read
Write
0
Update completed
This does not affect the operations
1
Updating
The counter values of the Hour/ Minute/ Second counters are
updated to Day/ Hour/Minute/ Second register values
respectively.
Before writing "1" to the update bit (UPDT), set the value to be updated in the Day/ Hour/ Minute/ Second registers.
Update for Day/ Hour/ Minute/ Second registers will be performed when reload occurs at the sub-second counter
(22-bit down counter).
When the counter value is updated, the UPDT bit will be cleared by hardware. However, when update is completed at
the same time as writing "1", the UPDT bit will not be cleared to "0".
[bit1] Reserved
This bit must always be written to "0".
[bit0] ST : Start
ST
Operation
0
Real-time clock module is stopped. All the counters are cleared.
1
Values set at Day/Hour/Minute/Second registers are loaded into
Day/Hour/Minute/Second counters, and the real-time clock starts to run.
Notes:
When writing "1" to the start bit (ST) from RTC stop state (ST=0) (RTC operation start), do not write "1" to the
update bit (UPDT) at the same time as the start bit.
(While ST=0, writing "1" as byte immediate value to the ST bit and the UPDT bit at the same time is
prohibited.)
To write "1" to the update bit (UPDT), do it while RTC is working (ST=1).
While the update bit (UPDT) is "1", writing "0" to the start bit (ST) (RTC stop) is prohibited.
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Chapter 29: Real-Time Clock (RTC)
4.2.
Sub-second Register : WTBR
The bit configuration of the sub-second register is shown below.
This register contains the reload value of the sub-second counter (22-bit down counter).
WTBRH : Address 0565H
(Access: Byte)
WTBRM : Address 0566H
(Access: Byte)
WTBRL : Address 0567H
(Access: Byte)
WTBRH
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
D21
D20
D19
D18
D17
D16
-
-
X
X
X
X
X
X
R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
WTBRM
Initial value
Attribute
WTBRL
Initial value
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The sub-second register contains the reload value used in the sub-second counter (22-bit down counter).
This value will be reloaded as soon as the sub-second counter (22-bit down counter) becomes "0". To modify the
sub-second register, confirm that no reload operations are being performed during the writing instruction. Otherwise,
the sub-second counter (22-bit down counter) will load a wrong value that combines both new and old data bytes.
Perform update while the ST bit is "0". While the sub-second register is set to "0", the sub-second counter (22-bit
down counter) will not run at all.
The sub-second register settings for counting 0.5 second are as follows:
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Chapter 29: Real-Time Clock (RTC)
Table 4-2 WTBR Setting Example
4.3.
RTC clock frequency
WTBR Setting value
32kHz
0x001F3F
50kHz
0x0030D3
4MHz
0x0F423F
Day/Hour/Minute/Second Register : WTDR/ WTHR/
WTMR/ WTSR
The bit configuration of the Day/Hour/Minute/Second register (WTDR/WTHR/WTMR/WTSR) is shown
below.
These registers indicate the time information of the real-time clock (Day/ Hour/ Minute/ Second).
WTDR (day register) : Address 055EH
(Access: Half-word)
WTHR (hour register) : Address 0568H
(Access: Byte, Half-word)
WTMR (minute register) : Address 0569H (Access: Byte, Half-word)
WTSR (second register) : Address 056AH (Access: Byte)
WTDR
Initial value
Attribute
Initial value
Attribute
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
N15
N14
N13
N12
N11
N10
N9
N8
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
N7
N6
N5
N4
N3
N2
N1
N0
0
0
0
0
0
0
0
0
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
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Chapter 29: Real-Time Clock (RTC)
WTHR
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
H4
H3
H2
H1
H0
-
-
-
0
0
0
0
0
R1,WX
R1,WX
R1,WX
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
M5
M4
M3
M2
M1
M0
-
-
0
0
0
0
0
0
R1,WX
R1,WX
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
S5
S4
S3
S2
S1
S0
-
-
0
0
0
0
0
0
R,W
R,W
R,W
R,W
WTMR
Initial value
Attribute
WTSR
Initial value
Attribute R1,WX
R1,WX
R,W
R,W
This register will be initialized by power-on reset factor.
The Second/ Minute/ Hour/ Day registers contain day and time information. Binary-coded notation is used for
second, minute, hour, and day.
When the register is read out, the counter value will be read out. The written data will be loaded to the counter after
the UPDT bit is set to "1".
As word access is not available, perform access for the respective registers.
Word access is not available for the number of days register either. In addition, be sure to perform halfword access
for the number of days register as the number of days is counted using a 16-bit counter. As byte access may cause
carry during read, having the possibility of getting an inappropriate read value, byte access and word access are
prohibited.
Set the Hour/Minute/Second registers within the following ranges:
Hour (WTHR) :
0 to 17H (0 hour to 23 hours)
Minute (WTMR) :
0 to 3BH (0 minute to 59 minutes)
Second (WTSR) :
0 to 3BH (0 second to 59 seconds)
Confirm that there are no contradictions among the values output from the four registers: Day/Hour/Minute/Second
registers. The following example may occur.
[Ex.] Output value "1 day, 23 hours, 59 minutes, 59 seconds", "0 day, 23 hours, 59 minutes, 59 seconds". "1 day, 0
hour, 0 minute, 0 second", "1 day, 22 hours, 59 minutes, 59 seconds", 1 day, 23 hours, 0 minute, 0 second, "2 days,
0 hour, 0 minute, 0 second"
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Figure 4-1 Diagram of Day, Hour, Minute and Second Register Transitions
If 1 day, 23 hours, 59 minutes is output, the current hour depends on the reading order of the registers.
Day register
0 day
Hour register
23 hours
Minute register
……
1 day
0 hour
……
22 hours
2 days
23 hours
…… 59 minutes 0 minute ……
……
……
1 day, 0 hour, 0 minute
1 day, 23 hours, 0 minute
59 minutes 0 minute
0 day, 23 hours,
59 minutes
1 day, 22 hours, 59 minutes
0 hour
……
……
2 days, 0 hour, 0 minute
59minutes 0 minute
1 day, 23 hours, 59 minutes
When the operation clock frequency is obtained by dividing the frequency of the main clock by 2 (while PLL is
stopped), the wrong values may be read out from the Hour/Minute/Second registers. This is caused due to
synchronization adjustment between reading operations and count operations. Therefore, use second interrupts in
the trigger for reading instructions.
To restart operations with the duration the counter has stopped as the initial value, read the
Day/Hour/Minute/Second registers prior to restart and write these values to the Day/Hour/Minute/Second registers
to start.
As this series does not provide the RTC detection reset function, the Day/Hour/Minute/Second registers are cleared
only in case of power-on reset. Therefore, when the microcomputer internal low-voltage detection flag is set, clear
the Day/Hour/Minute/Second registers.
5. Operation
This section explains the operation of the real-time clock (RTC).
This section explains the operations of the real-time clock.
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Figure 5-1 Operation Descriptions for the Real-time Clock
(1) Use the start bit (ST="0") to reset the sub-second counter (22-bit down counter) and Day/ Hour/ Minute/ Second
timers (0), and then stop them.
(2) -Write the values of Day/ Hour/ Minute/ Second to Day/ Hour/ Minute/ Second registers: WTDR, WTHR, WTMR,
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WTSR by software.
-Write "0FH", "42H", "3FH" to sub-second registers: WTBRH, WTBRM, WTBRL by software.
-Initialize the interrupt request bits (INT0, INT1, INT2, INT3, INT4), and set the interrupt request enable bits (INTE0,
INTE1, INTE2, INTE3, INTE4) (enable interrupts to be used).
(3) Set the start bit (ST) to "1".
(4) Use the start bit (ST="1") to load the values in the Day/ Hour/ Minute/ Second registers: WTDR, WTHR, WTMR,
WTSR to the Day/ Hour/ Minute/ Second timers.
(5) Moreover, as the count value of the sub-second counter (22-bit down counter) is "000000H", load the values in second
registers: WTBRH, WTBRM, WTBRL to the sub-second counter (22-bit down counter).
(6) The operation flag (RUN) becomes "1".
(7) The sub-second counter (22-bit down counter) starts to count using a clock obtained by dividing the main clock
frequency by 2 (4/2MHz).
(8) When the sub-second counter (22-bit down counter) becomes "000000H", load the sub-second register value
"0F423FH" to the sub-second counter (22-bit down counter).
In addition, an interrupt request of 0.5 second counter occurs.
Moreover, when the real-time clock output enable is set (WOT pin output enable), an "H" level with a width twice as
long as that of the main clock is output to the WOT pin.
(Example: For main clock 4MHz, "H" output with a width of 500ns)
(9) After the 0.5 second counter is counted up, it is cleared at the next count up, the second counter of the Day/ Hour/
Minute/ Second counters is counted up, and a second interrupt request occurs.
(10) The second counter of the Day/ Hour/ Minute/ Second counters is counted up, it is cleared at the next count up when
the value is "59", the minute counter is counted up, and the minute interrupt request occurs at this time.
(11) The minute counter of Day/ Hour/ Minute/ Second counters is counted up, it is cleared at the next count up when the
value is "59", the hour counter is counted up, and the hour interrupt request occurs at this time.
(12) The hour counter of the Day/ Hour/ Minute/ Second counters is counted up, it is cleared at the next count up when the
value is "23", the day counter is counted up, and the day interrupt request occurs at this time.
(13) The day counter of the Day/ Hour/ Minute/ Second counters is counted up, it is cleared at the next count up when the
value is "65535".
(14) Move to the watch mode by software.
The real-time clock will continue to run in the watch mode.
(15) Input a signal from an interrupt pin (INTxx) to restore from the watch mode and restart CPU.
(16) Set the start bit (ST) to "0".
(17) Use the start bit ST="0" to clear(reset) the sub-second counter (22-bit down counter) and the Day/ Hour/ Minute/
Second counters, and then stop them.
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6. Setting
This section explains setting of the real-time clock (RTC).
Table 6-1 Settings Required for Starting the Real-time Clock
Settings
Setting Registers
Setting
procedure
Setting of the reload value (sub-second register)
Sub-second register
(WTBRH, WTBRM, WTBRL)
See 7.1.
Initialization of the real-time clock
RTC Control Register (WTCR)
See 7.2.
Setting of number of days, time
(Day/Hour/Minute/Second)
Day/ Hour/ Minute/ Second registers
(WTDR, WTHR, WTMR, WTSR)
See 7.3.
Startup of the real-time clock
RTC Control Register (WTCR)
See 7.4.
Table 6-2 Settings Required for Knowing the Time
Settings
Reading of number of days and time
Setting Registers
Day/ Hour/ Minute/ Second registers
(WTDR, WTHR, WTMR, WTSR)
Setting
procedure
See 7.6.
Table 6-3 Settings Required for Stopping the Real-time Clock
Settings
Stop of the real-time clock
Setting Registers
RTC Control Register (WTCR)
Setting
procedure
See 7.7.
Table 6-4 Settings Required for Performing Real-time Clock Interrupts
Settings
Setting Registers
Setting
procedure
Setting of the RTC interrupt vector and the RTC
interrupt level
See "CHAPTER: INTERRUPT CONTROL
(INTERRUPT CONTROLLER)".
See 7.10.
RTC interrupt setting
Interrupt request clear
Interrupt request enable
RTC Control Register (WTCR)
See 7.11.
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7. Q&A
This section explains Q&A of the real-time clock (RTC).
7.1 How to Set the 0.5 Second Count Interval
7.2 How to Initialize the Real-time Clock
7.3 How to Set/Update Number of Days (Day) and Time (Hour/Minute/Second)
7.4 How to Start/Stop the Count of the Real-time Clock
7.5 How to Confirm That the Real-time Clock Is Running
7.6 How to Know the Number of Days and Time
7.7 How to Stop the Real-time Clock
7.8 How to Calibrate the Real-time Clock
7.9 Interrupt Related Registers
7.10 Interrupt Types and How to Select Them
7.11 How to Enable Interrupts
7.1.
How to Set the 0.5 Second Count Interval
This section explains how to set the 0.5 second count interval.
Stop the real-time clock, and set the value indicated in Table 4-2 WTBR Setting Example to the sub-second
register(WTBR) according to the RTC clock frequency.
7.2.
How to Initialize the Real-time Clock
This section explains how to initialize the real-time clock.
Perform initialization using the start bit (WTCR.ST).
Write "0" instead of "1" to the start bit to reset all the bits of the Hour/ Minute/ Second counters and the subsecond
counter (22-bit down counter) to "0" (initialization) and to stop counting.
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7.3.
How to Set/Update Number of Days (Day) and Time
(Hour/Minute/Second)
This section explains how to set/update number of days (day) and time (hour/minute/second).
Write the values in Day/ Hour/ Minute/ Second registers(WTDR, WTHR, WTMR, WTSR), and then update them
using the update bit (UPDT).
Operation
Update bit (UPDT)
To update the Day/ Hour/ Minute/ Second counters
7.4.
Set to "1"
How to Start/Stop the Count of the Real-time Clock
This section explains how to start/stop the count of the real-time clock.
Use the start bit (WTCR.ST) to set.
Operation
Start bit (ST)
To stop the count of the real-time clock
Set to "0"
To start the count of the real-time clock
Set to "1"
7.5.
How to Confirm That the Real-time Clock Is Running
This section explains how to confirm that the real-time clock is running.
Confirm using the operation flag (WTCR.RUN).
Operation
Operation flag (RUN)
The real-time clock has stopped
"0" can be read
The real-time clock is running
"1" can be read
7.6.
How to Know the Number of Days and Time
This section explains how to know the number of days and time.
They can be known by reading Day/ Hour/ Minute/ Second registers: WTDR, WTHR, WTMR, WTSR.
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However, as word access is not available, access to the respective registers is required. As the time may be misread
when the value is read in the boundary of the hour/minute count, perform multiple reads and use the logically correct
time.
Example:
When read from second:
1 day 2 hours 59 minutes 59 seconds => 1 day 3 hours 59 minutes 59 seconds => 1 day 3 hours 0 minute 0
secondWhen read from hour:
1 day 2 hours 59 minutes 59 seconds => 1 day 2 hours 0 minute 0 second => 1 day 3 hours 0 minute 0 second
7.7.
How to Stop the Real-time Clock
This section explains how to stop the real-time clock.
See "7.4 How to Start/Stop the Count of the Real-time Clock".
7.8.
How to Calibrate the Real-time Clock
This section explains how to calibrate the real-time clock.
When the sub clock(only dual clock product) is selected as the RTC clock, the ratio of main clock: sub clock can be
used for calibration. See "CHAPTER: RTC/WDT1 CALIBRATION".
7.9.
Interrupt Related Registers
This section explains interrupt related registers.
Setting of RTC interrupt vector and the RTC interrupt level.
The following table shows the relationship between interrupt levels and interrupt vectors.
For details on interrupt levels and interrupt vectors, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
Interrupt vector (default)
#37 (0FFF68H)
Interrupt level setting bit(ICR[4:0])
Interrupt level register ICR21 (00455H)
The interrupt request flags (INT0, INT1, INT2, INT3, INT4) are not automatically cleared. Therefore, use software to
clear the flags prior to restoration from interrupt processing. (Write "0" to INT0, INT1, INT2, INT3, INT4 bits)
Note:
If the real-time clock is used as source for recovering from the watch mode with power-shutdown, set the
interrupt level to ‘31’, before CPU state changes to the watch mode with power-shutdown.
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7.10. Interrupt Types and How to Select Them
This section explains the interrupt types and selection method.
There are five interrupt factors as follows:
Interrupt request bit
Interrupt request
enable bit
Time (1second) count timing
INT0
INTE0
Time (minute) count timing
INT1
INTE1
Time (hour) count timing
INT2
INTE2
1 day count timing
INT3
INTE3
Time(0.5 second) count timing
INT4
INTE4
Interrupt factor
As interrupt occurs by OR of these five factors, select using the interrupt request enable bit.
7.11. How to Enable Interrupts
This section explains how to enable interrupts.
Use the interrupt request enable bits (WTCR.INTE0, WTCR.INTE1, WTCR.INTE2, WTCR.INTE3, WTCR.INTE4)
to perform the operation.
Setting procedure
Operation
Interrupt request enable bits
(INTE0, INTE1, INTE2, INTE3, INTE4)
To disable interrupts
Set to "0"
To enable interrupts
Set to "1"
Use the interrupt request bits (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT3, WTCR.INT4) to clear
interrupt requests.
Setting procedure
Operation
Interrupt request bits (INT0, INT1, INT2, INT3, INT4)
To clear interrupt requests
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8. Sample Program
This section explains the sample program of the real-time clock(RTC).
Setting Procedure Example 1
Program Example 1
Start to count the real-time clock from 10 days 10 hours 10 minutes 00
second, enable the external interrupt (INT0) for "H" level detection, and
move to the watch mode.
Restore from the watch mode in case of external interrupt detection, and
read the time of the real-time clock.
RTC initialization
void RTC_sample1(void)
{
RTC_initial();
RTC_start();
EX_INT0_initial();
/* Subroutine for external interrupt setting*/
STOP_Hiz_hold_with_clock(); /* Subroutine for moving to the watch mode*/
RTC_read();
}
RTC startup, interrupt level setting
External interrupt settings
Move to the watch mode
Reading RTC
after restoration from the watch mode
-RTC
Register initialization
Setting of interval time (1second)
Setting of the time initialization
values
Initialization setting for RTC
interrupts
Register name. bit name
WTCR.ST
WTBR
WTSR
WTMR
WTHR
WTDR
WTCRM,WTCRL
WTCRH
void RTC_initial(void)
{
IO_WTCR.bit.ST = 1;
IO_WTCR.bit.ST = 0;
IO_WTBR.word = 0x0F423F;
IO_WTSR.byte = 0x00;
IO_WTMR.byte = 0x0A;
IO_WTHR.byte = 0x0A;
IO_WTDR.hword = 0x000A;
IO_WTCRL.hword = IO_WTCRL.hword & 0x0000;
IO_WTCRH.byte = 0x00
}
Register name. bit name
WTCR.ST
ICR21
ICR00
(CCR)
void RTC_start(void)
{
IO_WTCR.bit.ST = 1;
IO_ICR[21].bit.ICR = 18;
IO_ICR[00].bit.ICR = 20;
__EI();
}
Register name. bit name
RTC interrupt setting
WTCR
.INT0
.INTE0
RTC_read(void)
{
IO_WTCR.bit.INT0 = 0;
IO_WTCR.bit.INTE0 = 1;
}
RTC startup
Setting of interrupt level (RTC)
Setting of interrupt level (INT0)
Setting of the I flag
Register name. bit name
Time reading
Interrupt disable
WTHR
WTMR
WTSR
WTDR
WTCR.INTE0
Clearing of interrupt request flag
Register name. bit name
EIRR.ER0
/* Initialization preparation*/
/* Stop (register initialization)*/
/* Count value setting 4MHz/2 × 0x0F423F=0.5 second */
/* Second setting */
/* Minute setting */
/* Hour setting */
/* Day setting */
/* Interrupt flag clear, interrupt disable*/
/* Interrupt flag clear, interrupt disable*/
/* RTC startup*/
/* The value is arbitrary */
/* The value is arbitrary */
/* Interrupt enable */
/* RTC second interrupt request flag clear*/
/* RTC second interrupt request enable */
__interrupt void RTC_read_int(void) /* RTC interrupt */
{
JIKAN(char) = IO_WTHR.byte & 0x1F;
/*Hour*/
FUNN(char) = IO_WTMR.byte & 0x3F; /*Minute*/
BYOU(char) = IO_WTSR.byte & 0x3F;
/*Second*/
HI(char) = IO_WTDR.hword ;
/*Day*/
/*Multiple reads*/
IO_WTCR.bit.INTE0 = 0;
/* RTC interrupt disable */
}
__interrupt void INT0_int() /* External interrupt */
{
IO_EIRR0.bit.ER0= 0; /* ER0 second interrupt request flag clear*/
}
Setting of the vector table
Note:
Clock related settings and __set_il (number) setting are required to be
performed in advance. See "CHAPTER: CLOCK" and "CHAPTER:
INTERRUPT CONTROL (INTERRUPT CONTROLLER)".
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9. Notes
This section explains notes of the real-time clock.
The interrupt request flags (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT3, WTCR.INT4) will be set to
"1" when they are written to "0" at the same time when they are set to "1" in case of overflow. (Flag setting takes
precedence)
When reload occurs while update on the sub-second register (WTBRH, WTBRM, WTBRL) is in progress, an
unexpected value may be reloaded to the sub-second counter (22-bit down counter). Therefore, update the
sub-second register (WTBR) while the start bit (WTCR:ST) is "0".
When all the bits of the sub-second register (WTBRH, WTBRM, WTBRL) are set to "0", the sub-second counter
(22-bit down counter) will not run. Therefore, the real-time clock will not run.
Carry may occur while Day/Hour/Minute/Second registers (WTDR, WTHR, WTMR, WTSR) are being read,
leading to inappropriate read values. Therefore, use interrupt (INT0) to read the number of days and time
(Day/Hour/Minute/Second).
As word access is not available for Day/Hour/Minute/Second registers (WTDR, WTHR, WTMR, WTSR), access
to the respective registers is required. Therefore, as the time may be misread when the value is read in the
boundary of the hour/minute count, perform multiple reads and use the logically correct time.
Example:
When read from second:
1 day 23 hours 59 minutes 59 seconds= >2 days 0 hour 59 minutes 59 seconds=>2 days 0 hour 0 minute 0
second
When read from hour:
1 day 23 hours 59 minutes 59 seconds= >2 days 23 hours 0 minute 0 second=>2 days 0 hour 0 minute 0
second
When read from day:
1 day 23 hours 59 minutes 59 seconds=>1 day 0 hour 0 minute 0 second=>2 days 0 hour 0 minute 0 second
This case is judged as 2 days 0 hour.
Day/Hour/Minute/Second registers are not cleared by internal reset, while Day/Hour/Minute/Second counters are
cleared by internal reset. After internal reset occurs, the ST flag is cleared, and the RTC macro is in the stop state.
In addition, counter values prior to internal reset are set to Day/Hour/Minute/Second registers. To use
Day/Hour/Minute/Second in case of internal reset, set the values read from the Day/Hour/Minute/Second counters
to the Day/Hour/Second registers.
The number of days register has a built-in function for counting the number of days from "0 day" to "65535 days".
Notes on Setting the RTC Control Register
When writing "1" to the start bit (ST) from RTC stop state (ST=0) (RTC operation start), do not write "1" to the
update bit (UPDT) at the same time as the start bit.
(While ST=0, writing "1" as byte immediate value to the ST bit and the UPDT bit at the same time is
prohibited.)
To write "1" to the update bit (UPDT), do it while RTC is running (ST=1).
While the update bit (UPDT) is "1", writing "0" to the start bit (ST) (RTC stop) is prohibited.
When returning from the standby watch mode (power shutdown), the register of RTC is not initialized.
If the real-time clock is used as source for recovering from the watch mode with power-shutdown, set the interrupt
level to ‘31’, before CPU state changes to the watch mode with power-shutdown.
[MB91F52xxxC/MB91F52xxxE] The internal reset is issued at the return from the standby watch mode (power
shutdown). Therefore, only the reset causes (power-on reset, internal low-voltage reset, and simultaneous assertion
of RSTX and NMIX) are recognized. At this time, the register of the RTC is not initialized. If the flag for RSTX
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reset or the flag for the external low-voltage detection reset is set after wake-up, the user needs to initialize the
register of RTC before using it.
[MB91F52xxxD] The internal reset is issued at the return from the standby watch mode (power-shutdown).
Therefore, only the reset causes (power-on reset, internal low-voltage reset, and assertion of RSTX) are recognized.
At this time, the register of the RTC is not initialized. If the flag for RSTX reset or the flag for the external
low-voltage detection reset is set after the return, the user needs to initialize the register of RTC before using it.
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This chapter explains the RTC/WDT1 calibration.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : RTCCAL-1v0-91528-3-E
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1. Overview
This section gives an overview of the RTC/WDT1 calibration.
This module calculates the values to calibrate the real-time clock.
2. Features
This section explains features of the RTC/WDT1 calibration.
RTC Clock source select register
The main clock or the sub clock can be selected. For information on how to select, see "CHAPTER: CLOCK".
Real-Time Clock (RTC) Calibration (This function is effective only when the sub
clock is used.)
Values of the sub second register of the RTC are determined by calculating the sub clock frequency from the main
clock frequency on the condition that both the main clock driven counter and the sub clock driven counter operate
concurrently (Figure 2-1).
WDT1 (CR clock) calibration
This device has no CR clock calibration function. CR clock errors, however, can be measured by using the register of
this module.
Figure 2-1 Comparison of Counters Driven by Different Clocks
Sub clock/
CR oscillation clock
Sub/CR counter
CUTD
CUTD-1
2
Main oscillation Old CUTR
counter
1
0
New CUTR
Comparison in progress
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Chapter 30: RTC/WDT1 Calibration
3. Configuration
This section explains configuration of the RTC/WDT1 calibration.
Figure 3-1 Block Diagram
Bus access
Main clock
Sub clock
Calibration unit 0
(for RTC)
Calibration unit 1
(for WDT)
To CSV
CR oscillation circuit
CR oscillation clock
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4. Registers
This section explains the registers of the RTC/WDT1 calibration.
Table 4-1 Register Map
Registers
Address
Register function
+0
0x4B8
+1
CUCR0
Calibration unit control register 0
Sub clock timer data register
CUTR0
Reserved
0x4C4
Reserved
Main oscillation timer data register 0
Reserved
CUCR1
Reserved
Reserved
Calibration unit control register 1
CR oscillation timer data register
CUTD1
0x4C8
4.1.
+3
CUTD0
0x4BC
0x04C0
+2
CUTR1
Main oscillation timer data register 1
Calibration Unit Control Register 0 : CUCR0 (Calibration
Unit Control Register 0)
The bit configuration of the calibration unit control register 0 is shown.
This register configures calibration start and interrupts for RTC calibration unit.
CUCR0 : Address 04B8H (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
Attribute
1
1
1
1
1
1
1
1
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
INT
INTEN
Reserved
Initial value
Attribute
Reserved
STRT
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,WX
R0,WX
R,W
R0,WX
R0,WX
R,W
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[bit15 to bit8] Reserved
The read value of these bits is always "0". Writing to these bits does not influence other functions.
[bit7] Reserved
Be sure to write "0" to this bit.
[bit6, bit5, bit3, bit2] Reserved
The read value of these bits is always "0". Writing to these bits does not influence other functions.
[bit4] STRT (calibration STaRT) : Calibration start
This bit starts counters driven by the main clock and the sub clock. The INT bit will be set after the comparison is
completed.
STRT
Function
"0" write
Stops comparison
"1" write
Starts comparison
Setting "0" to this bit stops comparison. While comparing, writing "1" to this bit will not take effect. This bit will be
cleared to "0" after the comparison is completed.
[bit1] INT (calibration INTerrupt) : Interrupt
The INT bit will be set to "1" after the comparison is completed. If the INTEN bit is set, an interrupt will occur. This
bit is cleared by writing "0".
[bit0] INTEN (calibration INTerrupt ENable) : Interrupt enable
This bit sets whether to generate an interrupt when the INT bit is set.
INTEN
970
Interrupt
0
Disabled
1
Enabled
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Chapter 30: RTC/WDT1 Calibration
4.2.
Sub Clock Timer Data Register : CUTD0 (Calibration Unit
Timer Data register 0)
The bit configuration of the sub clock timer data register is shown.
This register configures a period of the time during which the sub clock driven counter operates.
CUTD0 : Address 04BAH (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TDD[15:8]
Initial value
Attribute
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TDD[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] TDD[15:0] (Timer Data Data field) : Timer data
These bits configure the comparison time interval in the number of the sub clock pulses.
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Chapter 30: RTC/WDT1 Calibration
4.3.
Main Oscillation Timer Result Register 0 : CUTR0
(Calibration Unit Timer Result register 0)
The bit configuration of the main oscillation timer result register 0 is shown.
This register indicates the number of the main clock pulses counted within the time interval set by CUTD0.
CUTR0 : Address 04BCH (Access: Byte, Half-word, Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
Initial value
0
Attribute R0,WX
bit23
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
bit22
bit21
bit20
bit19
bit18
bit17
bit16
TDR[23:16]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TDR[15:8]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TDR[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit31 to bit24] Reserved
The reading value of these bits is always "0". Writing to these bits does not influence other functions.
[bit23 to bit0] TDR[23:0] (Timer Data Register) : Timer data
These bits indicate the number of counts counted in the comparison interval. Read the results after the comparison is
completed. The read value during comparison is undefined. Writing has no effect on operation.
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Chapter 30: RTC/WDT1 Calibration
4.4.
Calibration Unit Control Register 1 : CUCR1 (Calibration
Unit Control Register 1)
The bit configuration of the calibration unit control register 1 is shown.
This register configures calibration start and interrupts for the WDT calibration unit.
CUCR1 : Address 04C4H (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
Attribute
1
1
1
1
1
1
1
1
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
INT
INTEN
Reserved
Initial value
Attribute
Reserved
STRT
Reserved
0
0
0
0
0
0
0
0
R0,W0
R0,WX
R0,WX
R,W
R0,WX
R0,WX
R,W0
R/W
[bit15 to bit8] Reserved
The read value of these bits is always "0". Writing to these bits does not influence other functions.
[bit7] Reserved
Be sure to write "0" to this bit.
[bit6, bit5, bit3, bit2] Reserved
The read value of these bits is always "0". Writing to these bits does not influence other functions.
[bit4] STRT (calibration STaRT) : Calibration start
This bit starts counters driven by main clock and CR clock. The INT bit will be set after the comparison is completed.
STRT
Function
"0" write
Stops comparison
"1" write
Starts comparison
Setting "0" to this bit stops comparison. While comparing, writing "1" to this bit will not take effect. This bit will be
cleared to "0" after the comparison is completed.
[bit1] INT (calibration INTerrupt) : Interrupt
The INT bit will be set to "1" after the comparison is completed. If the INTEN bit is set, an interrupt will occur. This
bit is cleared by writing "0".
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[bit0] INTEN (calibration INTerrupt Enable) : Interrupt enable
This bit sets whether to generate an interrupt or not when the INT bit is set.
INTEN
4.5.
Interrupt
0
Disabled
1
Enabled
CR Clock Timer Data Register : CUTD1 (Calibration Unit
Timer Data register 1)
The bit configuration of the CR clock timer data register is shown.
This register sets the time interval during which the CR clock driven counter operates.
CUTD1 : Address 04C6H (Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TDD[15:8]
Initial value
Attribute
1
1
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TDD[7:0]
Initial value
Attribute
0
1
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] TDD[15:0] (Timer Data Data field) : Timer data
These bits configure the comparison time interval in the number of the CR clock pulses.
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Chapter 30: RTC/WDT1 Calibration
4.6.
Main Oscillation Timer Result Register 1 : CUTR1
(Calibration Unit Timer Result register 1)
The bit configuration of the main oscillation timer result register 1 is shown.
This register indicates the number of the main clock pulses counted within the time interval set by CUTD1.
CUTR1 : Address 04C8H (Access: Byte, Half-word, Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
Initial value
0
Attribute R0,WX
bit23
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
bit22
bit21
bit20
bit19
bit18
bit17
bit16
TDR[23:16]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
TDR[15:8]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TDR[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit31 to bit24] Reserved
Always "0" is read. Writing to these bits does not influence other functions.
[bit23 to bit0] TDR[23:0] (Timer Data Register) : Timer data
These bits indicate the number of counts counted in the comparison interval. Read the results after the comparison is
completed. The read value during comparison is undefined. Writing has no effect.
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Chapter 30: RTC/WDT1 Calibration
5. Operation
This section explains operation.
5.1 Real-Time Clock (RTC) Calibration
5.2 Measurement of Errors in CR Clock
5.3 Note
5.1.
Real-Time Clock (RTC) Calibration
This section shows real-time clock (RTC) calibration.
The calibration procedure is as follows:
1.
2.
3.
4.
5.
6.
7.
Setting CUTD0
Setting CUCR0.INTEN
Setting CUCR0.STRT
Loop waiting for interrupt
Occurrence of interrupt
Reading CUTR0
Comparison of CUTR0 and CUTD0 can be used to calculate the ratio between the main clock frequency and the
sub clock frequency.
8. Setting values of the sub-second register in RTC using the value calculated at (7).
5.2.
Measurement of Errors in CR Clock
This section shows measurement of errors in the CR clock.
The procedure for measuring errors in the CR clock is as follows:
1.
2.
3.
4.
5.
6.
7.
976
Setting CUTD1
Setting CUCR1.INTEN
Setting CUCR1.STRT
Loop waiting for interrupt
Occurrence of interrupt
Reading CUTR1
Comparison of CUTR1 and CUTD1 can be used to calculate the ratio between the main clock frequency and the
CR clock frequency.
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Chapter 30: RTC/WDT1 Calibration
5.3.
Note
This section gives a note.
The counter value will become invalid in such a case that transition to standby mode occurs. Write "0" to the STRT
bit to stop, and then write "1" again to redo.
TOSC32/OSC100 > 2 × TOSC4 + 3 × TCLKP needs to be satisfied.
TOSC4 : main clock cycle
TOSC32 : sub clock cycle
TOSC100 : oscillation cycle of CR oscillation circuit
TCLKP : peripheral clock oscillation cycle
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Chapter 31: Power Consumption Control
This chapter explains the power consumption control.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Usage Example
Code : BZPMU-3v1-91528-3-E
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Chapter 31: Power Consumption Control
1. Overview
This section gives an overview of the power consumption control.
This device has a variety of low-power consumption modes and can perform the power consumption control
according to situations.
2. Features
This section explains features of the power consumption control.
Clock control
Clock division
By changing the division ratio for each running clock, the operating frequency can be lowered accordingly. See
"CHAPTER: CLOCK".
Sleep mode
CPU sleep mode
In this mode, the only CPU core stops operating.
Bus sleep mode
In this mode, both the CPU core and on-chip buses stop operating.
Standby mode
Watch mode
In this mode, all operations except some clock oscillations and the timer stop.
Stop mode
In this mode, all clock oscillations and operations stop.
Standby mode with power-shutdown
Watch mode with power-shutdown
In this mode, the device is turned the power off. And all operations except some clock oscillations and the timer
stop.
Stop mode with power-shutdown
In this mode, the device is turned the power off and all clock oscillations and operations stop.
Note:
In case of using the watch mode with power-shutdown, it is necessary to satisfy the below both conditions of (1) and
(2).
(1)Interrupt levels that are used as sources for recovering from the watch mode with power-shutdown are‘31’, before
CPU state changes to the watch mode with power-shutdown.
(2) Don’t use NMIX pin as source for recovering from the watch mode with power-shutdown.
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Chapter 31: Power Consumption Control
3. Configuration
This section shows the configuration of the power consumption control.
Figure 3-1 Block Diagram of Overall Control
I/O
I/O Power
Supply
Signal (Microcontroller → I/O)
Always ON Block
Signal (Microcontroller →Always ON)
Regulator 0
5V Power
Supply
PSW
Target block for
Power-shutdown
PD
RDY
PSW*1 control
shutdown
IO shutdown
FR81S
OSCD
Oscillation IO
PMU
*1: PSW (Power Switch)
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Chapter 31: Power Consumption Control
Figure 3-2 Block Diagram of Control
1'b0
CPU sleep request
Bus sleep request
SLEEP
STBCR read
SLVL[1]
TIMER
Clock stop request
STBCR read
Bus acknowledge
STOP
STBCR read
Oscillator stop
request
Return
Reset factor
STBCR : Standby control register
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Chapter 31: Power Consumption Control
4. Registers
This section shows the registers of the power consumption control.
Table 4-1 Register Map
Address
Registers
Register function
+0
+1
+2
+3
0x0480
Reserved
Reserved
STBCR
Reserved
Standby control register
0x0590
Reserved
PMUCTLR
PWRTMCTL
Reserved
PMU control register
PoWeR on TiMing control register
0x0594
PMUINTF0
PMUINTF1
PMUINTF2
PMUINTF3
PMU interrupt flag register 0 to 3
Note:
The addresses 0x0480 to 0x0481 and 0x0590 are allocated for the register "RESET". (See "CHAPTER: RESET".)
The group of registers (except STBCR) is initialized only in accordance with one or some of the following factors:
1. Power-on reset
2. Internal low-voltage detection
3. [MB91F52xxxC/MB91F52xxxE] Simultaneous assertion of RSTX and NMIX external pins
[MB91F52xxxD] Assertion of RSTX external pin
4. Hardware watchdog timer reset
* Registers are not initialized by reset of the INIT level and RST level. (except for STBCR)
4.1.
Standby Control Register: STBCR (STandBy mode Control
Register)
The bit configurations of the standby control register are shown below.
This register configures low-power consumption modes.
STBCR : Address 0482H (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
STOP
TIMER
SLEEP
Reserved
0
0
0
0
0
0
1
1
R,W
R,W
R,W
R0,W0
R0,W0
R0,W0
R/W
R/W
Reserved
bit1
bit0
SLVL[1:0]
Note:
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Chapter 31: Power Consumption Control
Writing to this register by DMA is prohibited.
[bit7] STOP (STOP mode): Stop mode enable
[bit6] TIMER (TIMER mode): Watch mode enable
[bit5] SLEEP (SLEEP mode): Sleep mode enable
Transitions to each standby mode (stop, watch, and sleep) are specified and enabled by these 3 bits. After writing the
values shown below to these 3 bits and reading STBCR, the CPU goes into each standby mode.
STOP
TIMER
SLEEP
Enabled transition to each standby mode
0
0
0
No transition (initial value)
0
0
1
Transition to sleep mode by reading STBCR
0
1
X
Transition to watch mode by reading STBCR
1
X
X
Transition to stop mode by reading STBCR
The read value of each bit is as follows regardless of the writing value:
STOP
TIMER
SLEEP
Enabled transition to each standby mode
0
0
0
No transition
0
0
1
Transition to sleep mode
0
1
0
Transition to watch mode
1
0
0
Transition to stop mode
These bits are returned to their initial values by wake up factors arising from each low-power consumption mode.
[bit4] Reserved
The read value is always "0". Be sure to write "0" to this bit.
[bit3, bit2] Reserved
The read value is always "0". Be sure to write "0" to these bits.
[bit1, bit0] SLVL[1:0] (Standby LeVeL) : Standby level setting
These bits control the operations in standby mode and sleep mode as shown below.
Mode
Stop mode
Watch mode
SLVL[1:0]
Operation control
0x
Does not make pins high impedance.
1x
Makes pins high impedance.
0x
Does not make pins high impedance.
1x
Makes pins high impedance.
0x
CPU sleep mode (stop only CPU)
1x
Bus sleep mode (stop CPU and on-chip bus) *
Sleep mode
* : On-chip bus will run only when DMA transfer is in progress.
For information on the pins with high impedance, see "APPENDIX".
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Chapter 31: Power Consumption Control
4.2.
PMU Control Register : PMUCTLR (Power Management
Unit ConTroL Register)
The bit configurations of the PMU control register are shown below.
This register controls PMU.
PMUCTLR : Address 0591H (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
SHDE
Reserved
IOCTMD
IOCT
BRAMSC
0
R/W
0
R0,W0
0
R/W
0
R/W
0
R/W
bit2
bit1
bit0
Reserved
0
R0,W0
0
R0,W0
0
R0,W0
[MB91F52xxxC/MB91F52xxxE] This register will be initialized by power-on reset, internal low-voltage reset, reset
by simultaneous assertion of RSTX and NMIX, and hardware watchdog timer reset.
[MB91F52xxxD] This register will be initialized by power-on reset, internal low-voltage reset, reset by assertion of
RSTX, and hardware watchdog timer reset.
[bit7] SHDE (SHut Down Enable)
This setting is for whether you establish shutdown mode when the CPU mode transits to standby (watch/stop).
SHDE
0
1
SHDE mode enable
When transiting to standby, you must not execute shutdown process.
When transiting to standby, you must execute shutdown process.
[bit6] Reserved
The read value is always "0". Be sure to write this bit to "0".
[bit5] IOCTMD (I/O Clear Timing MoDe)
This bit selects timing to maintain the I/O state when returning from standby (ShutDown) mode. (Hardware process)
IOCTMD
0
1
I/O maintain cancellation request mode
I/O state is maintained until returning from standby (WATCH and STOP) mode.
I/O state is maintained until IOCT register is cleared.
[bit4] IOCT (I/O Clear Timing)
By setting this bit to "1"when IOCTMD=1, I/O state maintaining are cancelled.
IOCT
I/O maintain cancellation request
0
No request
1
Requesting
This bit is cleared to "0" automatically after writing "1" to this bit and cancellation of I/O maintaining by I/O state
maintaining cancellation request is accepted.
Writing at times other than when I/O is maintained is invalid.
Writing this bit does not affect operation.
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[bit3]BRAMSC
BRAMSC
0
1
Backup RAM sleep control in standby mode
Backup RAM does not sleep in standby mode
Backup RAM sleeps in standby mode
[bit2 to bit0] Reserved
The read value is always "0". Be sure to write these bits to "0".
4.3.
Power on Timing Control Register : PWRTMCTL (PoWeR
on TiMing ConTroL register)
The bit configurations of the Power on Timing control register are shown below.
This register controls timing for power-on.
PWRTMCTL : Address 0592H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
Reserved
Initial value
Attribute
0
R0,W0
0
R0,W0
0
R0,W0
bit1
bit0
PTC
0
R0,W0
0
R0,W0
0
R/W
1
R/W
1
R/W
[MB91F52xxxC/MB91F52xxxE] This register will be initialized by power-on reset, internal low-voltage reset, reset
by simultaneous assertion of RSTX and NMIX, and hardware watchdog timer reset.
[MB91F52xxxD] This register will be initialized by power-on reset, internal low-voltage reset, reset by assertion of
RSTX, and hardware watchdog timer reset.
[bit7 to bit3] Reserved
The read value is always "0". Be sure to write these bits to "0".
[bit2 to bit0] PTC (Power on Timing Cycle setting)
These bits set the rise time for PSW.
PTC[2:0]
000
001
010
011
100
101
110
111
Rise time
5×(1/PMUCLK)
11×(1/PMUCLK)
17×(1/PMUCLK)
29×(1/PMUCLK)
Prohibit
8×(1/PMUCLK)
14×(1/PMUCLK)
23×(1/PMUCLK)
Remarks (PMUCLK=32 kHz)
150μs
330μs
510μs
870μs
240μs
420μs
690μs
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Chapter 31: Power Consumption Control
4.4.
PMU Interrupt Flag Register 0 : PMUINTF0 (Power
Management Unit INTerrupt Flag0 register)
The bit configurations of the PMU interrupt flag register 0 are shown below.
This register indicates the interrupt request by external input at shutdown.
PMUINTF0 : Address 0594H (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EIF15
EIF14
EIF13
EIF12
EIF11
EIF10
EIF9
EIF8
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
[MB91F52xxxC/MB91F52xxxE] This register will be initialized by power-on reset, internal low-voltage reset, reset
by simultaneous assertion of RSTX and NMIX, and hardware watchdog timer reset.
[MB91F52xxxD] This register will be initialized by power-on reset, internal low-voltage reset, reset by assertion of
RSTX, and hardware watchdog timer reset.
[bit7 to bit0] EIF15 to EIF8 (External Interrupt Flag15 to 8)
These flags indicate the interrupt request by external input at shutdown.
EIFxx
External interrupt request
0
No request
1
Request
xx -> The number from 15 to 8 is assigned.
These registers are enabled only at shutdown.
These registers are cleared by writing "0". Writing "1" does not affect operation.
4.5.
PMU Interrupt Flag Register 1 : PMUINTF1 (Power
Management Unit INTerrupt Flag1 register)
The bit configurations of the PMU interrupt flag register 1 are shown below.
This register indicates the interrupt request by external input at shutdown.
PMUINTF1 : Address 0595H (Access: Byte, Half-word, Word)
Initial value
Attribute
986
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EIF7
EIF6
EIF5
EIF4
EIF3
EIF2
EIF1
EIF0
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
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Chapter 31: Power Consumption Control
[MB91F52xxxC/ MB91F52xxxE] This register will be initialized by power-on reset, internal low-voltage reset, reset
by simultaneous assertion of RSTX and NMIX, and hardware watchdog timer reset.
[MB91F52xxxD] This register will be initialized by power-on reset, internal low-voltage reset, reset by assertion of
RSTX, and hardware watchdog timer reset.
[bit7 to bit0] EIF7 to EIF0 (External Interrupt Flag7 to 0)
These flags indicate the interrupt request by external input at shutdown.
EIFxx
External interrupt request
0
No request
1
Request
xx -> The number from 7 to 0 is assigned.
These registers are enabled only at shutdown.
These registers are cleared by writing "0". Writing "1" does not affect operation.
4.6.
PMU Interrupt Flag Register 2 : PMUINTF2 (Power
Management Unit INTerrupt Flag2 register)
The bit configurations of the PMU interrupt flag register 2 are shown below.
This register indicates the interrupt request at shutdown.
PMUINTF2 : Address 0596H (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
RIF
NIF
MTIF
STIF
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
bit3
bit2
bit1
bit0
Reserved
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
[MB91F52xxxC/MB91F52xxxE] This register will be initialized by power-on reset, internal low-voltage reset, reset
by simultaneous assertion of RSTX and NMIX, and hardware watchdog timer reset.
[MB91F52xxxD] This register will be initialized by power-on reset, internal low-voltage reset, reset by assertion of
RSTX, and hardware watchdog timer reset.
[bit7] RIF (Rtc Interrupt Flag)
This flag indicates the interrupt request by RTC at shutdown.
RIF
RTC interrupt request
0
No request
1
Request
This bit is enabled only at shutdown.
This bit is cleared by writing "0". Writing "1" does not affect operation.
[bit6] NIF (NmI Flag)
This flag indicates the interrupt request by NMI at shutdown.
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NIF
NMI interrupt request
0
No request
1
Request
This bit is valid only at shutdown.
This bit is cleared by writing "0". Writing "1" does not affect operation.
[bit5] MTIF (Main Timer Interrupt Flag)
This flag indicates the interrupt request by Main Timer at shutdown.
MTIF
Main timer interrupt request
0
No request
1
Request
This bit is enabled only at shutdown.
This bit is cleared by writing "0". Writing "1" does not affect operation.
The internal reset is issued at the return from the standby mode (power-shutdown) and the main timer interrupt flag is
not set.
[bit4] STIF (Sub Timer Interrupt Flag)
This flag indicates the interrupt request by Sub Timer at shutdown.
STIF
Sub timer interrupt request
0
No request
1
Request
This bit is enabled only at shutdown.
This bit is cleared by writing "0". Writing "1" does not affect operation.
The internal reset is issued at the return from the standby mode (power-shutdown) and the sub timer interrupt flag is
not set.
[bit3 to bit0] Reserved
The read value is always "0". Be sure to write these bits to "0".
4.7.
PMU Interrupt Flag Register 3 : PMUINTF3 (Power
Management Unit INTerrupt Flag3 register)
The bit configurations of the PMU interrupt flag register 3 are shown below.
This register indicates the interrupt request by external input at shutdown.
PMUINTF3 : Address 0597H (Access: Byte, Half-word, Word)
Initial value
Attribute
988
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EIF23
EIF22
EIF21
EIF20
EIF19
EIF18
EIF17
EIF16
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
0
R(RM1),
W
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[MB91F52xxxC/MB91F52xxxE] This register will be initialized by power-on reset, internal low-voltage reset, reset
by simultaneous assertion of RSTX and NMIX, and hardware watchdog timer reset.
[MB91F52xxxD] This register will be initialized by power-on reset, internal low-voltage reset, reset by assertion of
RSTX, and hardware watchdog timer reset.
[bit7 to bit0] EIF23 to EIF16 (External Interrupt Flag23 to 16)
These flags indicate the interrupt request by external input at shutdown.
EIFxx
External interrupt request
0
No request
1
Request
xx -> The number from 23 to 16 is assigned.
These registers are enabled only at shutdown.
These registers are cleared by writing "0". Writing "1" does not affect operation.
5. Operation
Operations of the power consumption control are explained.
Features of the power consumption control of the device are explained in the following sections.
5.1 Clock Control
5.2 List of Clocks Supplied in Low-power Consumption Mode
5.3 Sleep Mode
5.4 Standby Mode : Watch Mode
5.5 Standby Mode : Watch Mode with Power-shutdown
5.6 Standby Mode : Stop Mode
5.7 Standby Mode : Stop Mode with Power-shutdown
5.8 Stop State of Microcontroller
5.9 Transition to Illegal Standby Mode
5.10 Restrictions on Power-Shutdown and Normal Standby Control
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5.1.
Clock Control
This section shows the clock control of the power consumption control.
By adjusting each operating clock of the device, its power consumption and processing capability can be optimized.
5.1.1.
Division Setting
This section shows division setting of the clock.
See "CHAPTER: CLOCK".
5.1.2.
Stopping of Unused Clocks
This section shows stopping of unused clocks.
The following clock can be independently stopped by settings:
External bus clock (TCLK): Can be selected to supply/stop in bus sleep mode
For details of the setting, see "CHAPTER: CLOCK".
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5.2.
List of Clocks Supplied in Low-power Consumption Mode
The list of clocks supplied in low-power consumption mode is shown below.
Table 5-1 List of Clocks Supplied in Low-power Consumption Mode
Clock
Standby
Sleep
Stop
Watch
Bus
CPU
CPU clock (CCLK)
○
○
○
×
CAN Prescaler Clock
○
○
*1
×
On-chip bus clock (HCLK)
○
○
○
×
Peripheral clock (PCLK)
○
○
×
×
External bus I/F clock (TCLK)
○
○
*2
×
PLL clock (PLLCLK)
○
○
×
×
Main clock (MCLK)
○
×
×
×
Sub clock (SBCLK)
○
×
×
×
FlexRay Clock (When HCLK is
selected)
○
○
○
×
FlexRay Clock (When PLLCLK
is selected)
○
○
×
×
FlexRay Clock (When CLKPLL
is selected)
○
×
×
×
○*4
○*4
×*3
×*3
CR oscillation
○:
×:
Stops
Does not stop.
(If the main clock/sub clock/PLL clock are stopped by each clock setting register, supply of each clock stops,
accordingly.)
*1: When on-chip bus clock (HCLK) is selected as CAN prescaler clock, this clock stops. When PLL
clock is selected, whether CAN prescaler stops or not depends on PLL output. Otherwise, CAN prescaler
clock does not stop.
*2: This clock is set by the DIVR1:TSTP bit. See "CHAPTER: CLOCK".
*3: During sleep mode, the CR oscillation does not stop, but the watchdog timer 1 (HWWDT) stops.
*4: In order to stop the CR oscillation in standby mode, a setting is needed in advance. See the description of
CSVCR.RCE in "CHAPTER: CLOCK SUPERVISOR".
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5.3.
Sleep Mode
This section describes sleep mode.
Sleep mode is the mode in which CPU and on-chip bus are stopped and only the peripherals run. In sleep mode, there
are the following modes according to the difference in the range of functional blocks to be stopped.
CPU sleep mode
Bus sleep mode
: Only CPU is stopped.
: Both CPU and on-chip bus are stopped.
The stop state continues until a wake up request occurs. It is possible to return to programmed operation within a few
clock times by generating a wake up request.
Operation of each mode are explained in the following sections
5.3.1.
CPU Sleep Mode
This section describes CPU sleep mode.
CPU sleep mode is the mode to stop the CPU operating.
In this mode, the DMA controller and on-chip bus can continue operating, but more power will be consumed than that
in bus sleep mode.
5.3.2.
Bus Sleep Mode
This section describes bus sleep mode.
Bus sleep mode is the mode to stop CPU and on-chip bus operations. In this mode, the CPU clock (CCLK) and
on-chip bus clock (HCLK) will stop.
When accepting a DMA transfer request in bus sleep mode, on-chip bus clock (HCLK) supply resumes temporarily
and performs DMA transfers. After the DMA transfer, stop the on-chip bus clock (HCLK) again.
In this mode, you can decrease the amount of power consumption more than that of CPU sleep mode, but the
response time to the DMA transfer request will be somewhat degraded.
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5.3.3.
Configuration of Sleep Mode
The configuration of sleep mode is described below.
Before activating sleep mode, select whether to supply/stop external bus clock in sleep mode with the values set to
bit7:TSTP in the DIVR1 register.
When setting bit7:TSTP="0" in the DIVR1 register, the external bus clock does not stop.
When setting bit7:TSTP="1" in the DIVR1 register, the external bus clock stops.
When activating sleep mode, select the level of sleep mode with the values set to bit1:SLVL1 in the STBCR register.
When setting bit1:SLVL1="0" in the STBCR register, CPU goes into CPU sleep mode.
When setting bit1:SLVL1="1" in the STBCR register, CPU goes into bus sleep mode.
5.3.4.
Activation of Sleep Mode
Activation of sleep mode is described below.
To activate sleep mode, follow the steps below.
Write "001" to bit7:STOP, bit6:TIMER, bit5:SLEEP in the STBCR register.
Read STBCR
In FR81S core, if the read value will not be used in the next instruction, that instruction is executed before the read is
completed. Perform dummy processing to use the read value in the next instruction so as not to make the program
progress before entering sleep mode.
[Example] Sample program of sleep mode activation
LDI
LDI
STB
LDUB
MOV
NOP
#value_of_sleep, R0
#_STBCR, R12
R0, @R12
@R12, R0
R0, R0
; SLEEP bit ="1", SLVL setting
;
; Write
; Read (activation of sleep mode)
; Dummy processing for pipeline adjustment
; Dummy processing for pipeline adjustment
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5.3.5.
Wake Up from the Sleep Mode
Wake up from the sleep mode is described below.
The sleep mode is terminated under the following conditions:
Reset
Generation of interrupt request whose value of corresponding ICR register is value other than "0x1F"
Generation of NMI request
Generation of tool break while connected to ICE
For the wake up caused by an interrupt request, the CPU does not necessarily have to be set so as to accept this
interrupt request. When an interrupt request is not accepted, the program starts from the instruction next to the
instruction which activated the sleep mode.
In the bus sleep mode, the on-chip bus clock (HCLK) is temporarily returned by generating the DMA transfer request
and DMA transfer is performed. After the DMA transfer is ended, the on-chip bus clock (HCLK) is stopped again.
5.3.6.
Effect of Sleep Mode
Effect of sleep mode is described below.
You can reduce power consumption on the peripheral or external input event wait state drastically by using sleep
mode. This mode does not decrease power consumption as much as that of in watch mode or stop mode because the
peripheral clock (PCLK) will continue to run. While, a return to the program operation within several clock times is
possible by generating a wake up request.
5.4.
Standby Mode : Watch Mode
This section describes standby mode: watch mode.
Watch mode is the mode to continue oscillation only for the specific clock and count the clock timer corresponding to
that clock. When the sub clock (SBCLK) is selected as the clock source, only the sub clock oscillates and only the sub
timer counts.
Notes:
994
Enter the device into the standby mode only when main RUN or sub RUN is in progress. For the operation at a
transition from the PLL-run state to its standby mode, see "5.9 Transition to Illegal Standby Mode".
Transition to the standby mode while the FLASH memory is being programmed / erased is prohibited.
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5.4.1.
Configuration of Watch Mode
The configuration of watch mode is described below.
Before activating watch mode, set the state of external pins in watch mode with the bit1:SLVL1 in the STBCR
register.
When setting bit1:SLVL1="0" in the STBCR register, the external pins hold previous state.
When setting bit1:SLVL1="1" in the STBCR register, the external pins become high impedance.
Pins whose state is controlled differ according to product types. See "APPENDIX".
5.4.2.
Activation of Watch Mode
Activation of watch mode is described below.
To activate watch mode, follow the steps below.
"0" is written in bit7:SHDE of the PMUCTLR register.
When performing PLL RUN, CPU must go into main RUN state first. (When performing sub RUN state, it transits
directly to watch mode.)
Write "010" to bit7:STOP, bit6:TIMER, bit5:SLEEP in the STBCR register.
Read the STBCR register.
In FR81S core, if the read value will not be used in the next instruction, that instruction is executed before the read is
completed. Perform dummy processing to use the read value in the next instruction so as not to make the program
progress before entering watch mode.
[Example] Sample program of watch mode activation
LDI
LDI
STB
LDUB
MOV
NOP
#value_of_timer, R0
#_STBCR, R12
R0, @R12
@R12, R0
R0, R0
; TIMER bit ="1", SLVL setting
;
; Write
; Read (activation of watch mode)
; Dummy processing for pipeline adjustment
; Dummy processing for pipeline adjustment
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5.4.3.
Wake Up from the Watch Mode
Wake up from the watch mode is described below.
The watch mode is terminated under the following conditions:
Reset
Generation of interrupt request whose value of corresponding ICR register is value other than "0x1F" (see
"CHAPTER: INTERRUPT CONTROL (INTERRUPT CONTROLLER)")
Generation of NMI request
Generation of tool break while connected to ICE
For the wake up caused by an interrupt request, the CPU does not necessarily have to be set so as to accept this
interrupt request. When an interrupt request is not accepted, the program continues to run from the instruction next to
the instruction which activated the watch mode.
5.4.4.
Effect of Watch Mode
The effect of watch mode is described below.
You can reduce power consumption on the external input event wait state drastically by using watch mode. This mode
does not decrease power consumption as much as that of in stop mode because enabled clock oscillation will continue
to run. On the other hand, a clock timer can continue to run and a return to the program operation is possible by
generating a wake up request in a short time compared with the return from the stop mode.*
* : When continue to run program with activate clocks.
5.5.
Standby Mode : Watch Mode with Power-shutdown
This section describes standby mode : watch mode with power-shutdown.
Watch mode with power-shutdown is the mode to continue oscillation only for the specific clock and to continue
counting the clock timer corresponding to that clock while power supply to the microcontroller is shut off. When the
sub clock (SBCLK) is selected as the clock source, only the sub clock oscillates and only the sub timer counts.
Notes:
Enter the device into the standby mode only when main RUN or sub RUN is in progress. For the operation at a
transition from the PLL-run state to its standby mode, see "5.9 Transition to Illegal Standby Mode".
Transition to the standby mode while the FLASH memory is being programmed / erased is prohibited.
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5.5.1.
Configuration of Watch Mode with Power-shutdown
The configuration of watch mode with power-shutdown is described below.
Before activating watch mode with power-shutdown, set and control the followings.
(1) Set the state of external pins in watch mode with power-shutdown with the bit1:SLVL1 in the STBCR register.
When setting bit1:SLVL1="0" in the STBCR register, the external pins hold previous state.
When setting bit1:SLVL1="1" in the STBCR register, the external pins become high impedance.
Pins whose state is controlled differ according to product types. See "APPENDIX".
(2) Interrupt levels that are used as sources for recovering from the watch mode with power-shutdown are‘31’, before
CPU state changes to the watch mode with power-shutdown.
(3) Don’t use NMIX pin as source for recovering from the watch mode with power-shutdown.
5.5.2.
Activation of Watch Mode with Power-shutdown
Activation of watch mode with power-shutdown is described below.
To activate watch mode with power-shutdown, follow the steps below:
"1" is written in bit7:SHDE of the PMUCTLR register.
When performing PLL RUN, CPU must go into main RUN state first. (When performing sub RUN state, it transits
directly to watch mode with power-shutdown.)
Write "010" to bit7:STOP, bit6:TIMER, bit5:SLEEP in the STBCR register.
Read the STBCR register.
In FR81S core, if the read value will not be used in the next instruction, that instruction is executed before the read is
completed. Perform dummy processing to use the read value in the next instruction so as not to make the program
progress before entering watch mode with power-shutdown.
[Example] Sample program of watch mode activation (power-shutdown)
LDI
LDI
STB
LDI
LDI
STB
LDUB
MOV
NOP
#value_of_PMU, R0
#_PMUCTLR, R12
R0, @R12
#value_of_timer, R0
#_STBCR, R12
R0, @R12
@R12, R0
R0, R0
; SHDE bit ="1", IOCTMD/IOCT bit setting
;
; Write
; TIMER bit ="1", SLVL setting
;
; Write
; Read (activation of watch mode with power-shutdown)
; Dummy processing for pipeline adjustment
; Dummy processing for pipeline adjustment
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Figure 5-1 Transition Sequence to Watch Mode with Power-shutdown
Microco ntr oller
ope rati on
Registe r settin g
SHDE vali d
Watch mode setting register
(Read/Write)
Watch mode
Transition wait
TIMER = 0
Flash OFF
control
TIMER = 1
Latch of signal
(necessary signal)
Reset (5V)
Issue
Flash OFF
control
Return
Microcontroller
Microco ntr oller
OFF control
OFF control
Watch
(Shu tDown)
(Clock, Reset)
Isol atio n valid
PSW OFF
(Weak, Strong)
Return
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5.5.3.
Wake Up from the Watch Mode with Power-shutdown
Wake up from the watch mode with power-shutdown is described below.
The watch mode with power-shutdown is terminated under the following conditions:
Reset
Generation of external interrupt request
Generation of RTC interrupt request
Generation of main/sub timer interrupt request
For the wake up caused by an interrupt request, the CPU and the interrupt controller do not necessarily have to be set
so as to accept this interrupt request. The CPU always starts operation from the reset state.
The register of RTC and external interrupt input (IOCTMD=1) is not initialized.
[MB91F52xxxC/MB91F52xxxE] Only the reset factors (power-on reset, internal low-voltage reset, and simultaneous
assertion of RSTX and NMIX) are accepted during wake-up. At this time, the register of the RTC and external
interrupt input (IOCTMD=1) is not initialized. If the flag for RSTX reset or the flag for the external low-voltage
detection reset is set after the start-up, the user needs to initialize the RTC/external interrupt input register before
using it.
[MB91F52xxxD] Only the reset factors (power-on reset, internal low-voltage reset, and assertion of RSTX) are
accepted during wake-up. At this time, the register of the RTC and external interrupt input (IOCTMD=1) is not
initialized. If the flag for RSTX reset or the flag for the external low-voltage detection reset is set after the start-up,
the user needs to initialize the RTC/external interrupt input register before using it.
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Figure 5-2 Restore Sequence from Watch Mode with Power-shutdown
Watch
(Shu t Down )
Interrupt / Reset
Release Latch
(necessary signal)
Microco ntr oller
Microco ntr oller
ON control
PSW ON
(Weak, Strong)
ON control
Return
Flash ON
control
Flash ON
control
Isol atio n in val id
Reset (5V)
Release
(Clock, Reset)
Microco ntr oller
ope rati on
RDY = 0
RDY wait
RDY = 1
Return
5.5.4.
Effect of Watch Mode with Power-shutdown
The effect of watch mode with power-shutdown is described below.
You can reduce wait current for unnecessary circuit greatly by watch mode with power-shutdown. This mode does not
decrease power consumption as much as that of in stop mode because enabled clock oscillation will continue to run.
On the other hand, a clock timer can continue to run and a return to the program operation without clock oscillation
stabilization wait is possible by generating a wake up request.
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5.6.
Standby Mode : Stop Mode
This section describes standby mode: stop mode.
Stop mode is the mode to stop all clock oscillations and minimize power consumption of this device.
Notes:
Enter the device into the standby mode only when main RUN or sub RUN is in progress. For the operation at a
transition from the PLL-run state to its standby mode, see "5.9 Transition to Illegal Standby Mode".
Transition to the standby mode while the FLASH memory is being programmed / erased is prohibited.
5.6.1.
Configuration of Stop Mode
The configuration of stop mode is described below.
Before activating stop mode, set the state of external pins in stop mode with the bit1:SLVL1 in the STBCR register.
When setting bit1:SLVL1="0" in the STBCR register, the external pins hold previous state.
When setting bit1:SLVL1="1" in the STBCR register, the external pins become high impedance.
Pins whose state is controlled differ according to product types. See "APPENDIX".
5.6.2.
Activation of Stop Mode
Activation of stop mode is described below.
To activate stop mode, follow the steps below.
"0" is written in bit7:SHDE of the PMUCTLR register.
When performing PLL RUN, CPU must go into main RUN state first. (When performing sub RUN state, it transits
directly to stop mode.)
Write "100" to bit7:STOP, bit6:TIMER, bit5:SLEEP in the STBCR register.
Read the STBCR register.
In FR81S core, if the read value will not be used in the next instruction, that instruction is executed before the read is
completed. Perform dummy processing to use the read value in the next instruction so as not to make the program
progress before entering stop mode.
[Example] Sample program of stop mode activation
LDI
#value_of_stop, R0
; STOP bit ="1", SLVL setting
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LDI
STB
LDUB
MOV
NOP
5.6.3.
#_STBCR, R12
R0, @R12
@R12, R0
R0, R0
;
; Write
; Read (activation of stop mode)
; Dummy processing for pipeline adjustment
; Dummy processing for pipeline adjustment
Wake Up from the Stop Mode
Wake up from the stop mode is described below.
The stop mode is terminated under the following conditions:
Reset
Generation of interrupt request in which the value of corresponding ICR register is other than "0x1F" (see
"CHAPTER: INTERRUPT CONTROL (INTERRUPT CONTROLLER)")
Generation of NMI request
Generation of tool break while being connected to ICE
For the wake up caused by an interrupt request, the CPU does not necessarily have to be set so as to accept this
interrupt request. When an interrupt request is not accepted, the program continues to run from the instruction next to
the instruction which activated the stop mode.
5.6.4.
Effect of Stop Mode
The effect of stop mode is described below.
You can minimize power consumption on the external input event wait state by using stop mode. While, a return to
the program operation after generating a wake up request needs the oscillation stabilization wait time.
5.7.
Standby Mode : Stop Mode with Power-shutdown
This section describes standby mode: stop mode with power-shutdown.
Stop mode with power-shutdown is the mode to stop all clock oscillations and minimize power consumption of the
device.
Notes:
Enter the device into the standby mode only when main RUN or sub RUN is in progress. For the operation at a
transition from the PLL-run state to its standby mode, see "5.9 Transition to Illegal Standby Mode".
Transition to the standby mode while the FLASH memory is being programmed / erased is prohibited.
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5.7.1.
Configuration of Stop Mode with Power-shutdown
The configuration of stop mode with power-shutdown is described below.
Before activating stop mode with power-shutdown, set and control the followings.
(1) Set the state of external pins in stop mode with power-shutdown with the bit1:SLVL1 in the STBCR register.
When setting bit1:SLVL1= "0" in the STBCR register, the external pins hold previous state.
When setting bit1:SLVL1= "1" in the STBCR register, the external pins become high impedance.
Pins whose state is controlled differ according to product types. See "APPENDIX".
5.7.2.
Activation of Stop Mode with Power-shutdown
Activation of stop mode with power-shutdown is described below.
To activate stop mode with power-shutdown, follow the steps below:
"1" is written in bit7:SHDE of the PMUCTLR register.
When performing PLL RUN, CPU must go into main RUN state first. (When performing sub RUN state, it transits
directly to stop mode with power-shutdown.)
Write "100" to bit7:STOP, bit6:TIMER, bit5:SLEEP in the STBCR register.
Read the STBCR register.
In FR81S core, if the read value will not be used in the next instruction, that instruction is executed before the read is
completed. Perform dummy processing to use the read value in the next instruction so as not to make the program
progress before entering stop mode with power-shutdown.
[Example] Sample program of stop mode with power-shutdown activation
LDI
LDI
STB
LDI
LDI
STB
LDUB
MOV
NOP
#value_of_PMU, R0
#_PMUCTLR, R12
R0, @R12
#value_of_stop, R0
#_STBCR, R12
R0, @R12
@R12, R0
R0, R0
; SHDE bit ="1", IOCTMD/IOCT bit setting
;
; Write
; STOP bit ="1", SLVL setting
;
; Write
; Read (activation of stop mode with power-shutdown)
; Dummy processing for pipeline adjustment
; Dummy processing for pipeline adjustment
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Figure 5-3 Transition Sequence to Stop Mode with Power-shutdown
Microco ntr oller
ope rati on
Registe r settin g
SHDE vali d
STOP mode setting
regi ster (Read/Write)
STOP mode
Transition wait
STOP = 0
Flash OFF
control
STOP = 1
Latch o f si gnal
(necessary signal)
Reset (5V)
Issue
Flash OFF
control
Return
Microco ntr oller
OFF control
STOP
(Shu tDown)
Microco ntr oller
OFF control
Isol atio n valid
(Clock, Reset)
PSW OFF
(Weak, Strong)
Return
1004
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Chapter 31: Power Consumption Control
5.7.3.
Wake Up from the Stop Mode with Power-shutdown
Wake up from stop mode with power-shutdown is described below.
The stop mode with power-shutdown is terminated under the following conditions:
Reset
Generation of external interrupt request
Generation of NMI request
For the wake up caused by an interrupt request, the CPU and the interrupt controller do not necessarily have to be set
so as to accept this interrupt request. The CPU always starts operation from the reset state.
The register of the external interrupt input (IOCTMD=1) is not initialized.
[MB91F52xxxC/MB91F52xxxE] Only the reset factors (power-on reset, internal low-voltage reset and simultaneous
assertion of RSTX and NMIX) are accepted during wake-up. At this time, the register of the external interrupt input
(IOCTMD=1) is not initialized. If the flag for RSTX reset or the flag for the external low-voltage detection reset is set
after the start-up, the user needs to initialize the register before using it.
[MB91F52xxxD] Only the reset factors (power-on reset, internal low-voltage reset, and assertion of RSTX) are
accepted during wake-up. At this time, the register of the external interrupt input (IOCTMD=1) is not initialized. If
the flag for RSTX reset or the flag for the external low-voltage detection reset is set after the start-up, the user needs
to initialize the register before using it.
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Chapter 31: Power Consumption Control
Figure 5-4 Return Sequence from Stop Mode with Power-shutdown
STOP(ShutDown)
Interrupt / Reset
Release Latch
(necessary signal)
Oscillation stabili zation
wait (CGEN)
Microco ntr oller
ON control
ON
control
Flash
Isol atio n in val id
(Clock, Reset)
Microco ntr oller
ope rati on
Microco ntr oller
ON control
PSW ON
(Weak, Strong)
Return
ON
control
Flash
Reset (5V)
Release
RDY = 0
RDY wait
RDY = 1
Return
1006
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Chapter 31: Power Consumption Control
5.7.4.
Effect of Stop Mode with Power-shutdown
The effect of stop mode with power-shutdown is described below.
You can minimize wait current for unnecessary circuit by stop mode with power-shutdown. While, a return to the
program operation after generating a wake up request needs the oscillation stabilization wait time.
5.8.
Stop State of Microcontroller
The stop state of the microcontroller is described below.
When the transition from the state of the standby mode (watch mode/watch mode with power-shutdown /stop
mode/stop mode with power-shutdown) transition prohibition to the standby is controlled, the standby transition is not
concluded.
< State of standby transition prohibition >
1. Connecting OCD
2. Operating PLL
3. Flash memory power saving control
4. Oscillation stop (At the stop mode or stop mode with power-shutdown)
However, the oscillation stop operation is done detecting the illegal standby mode transition when the standby mode
transition control is done while PLL is operating. See "5.9. Transition to Illegal Standby Mode" for the illegal standby
mode transition.
5.9.
Transition to Illegal Standby Mode
Transition to illegal standby mode is described below.
If the transition from PLL run state to standby mode (watch mode/watch mode with power-shutdown/stop mode/stop
mode with power shutdown) is made, standby mode is set and PLL oscillation stabilization is canceled. (Transition to
illegal standby mode)
After returning from standby mode, CSELR.CKS[1:0]=00 and CMONR.CKM[1:0]=00 (divide-by-two output of the
main clock).
The PSTF flag of the CPUAR register is set concurrently with the transition to standby mode. When the PSTRE bit in
the CPUAR register is set, reset occurs by illegal standby mode transition detection reset factor. For the CPUAR
register, see " CPU Abnormal Operation Register: CPUAR (CPU Abnormal operation Register) " in "CHAPTER:
RESET".
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Chapter 31: Power Consumption Control
Figure 5-5 Generation Diagram of Illegal Standby Mode Transition Detection Reset Factor
set
PLL/SSCG clock is being
selected as a clock source.
CPUAR.
PSTF
Generation of transition to
Watch mode/Stop mode
Illegal standby mode
transition detection reset
factor
CPUAR.
PSTRE
5.10. Restrictions on Power-Shutdown and Normal Standby
Control
Restrictions on power-shutdown and normal standby control are described below.
The microcontroller has some restrictions on standby control under the following conditions:
When the CPU is operating with PLL
When the OCD is being enabled to operate
The standby control does not operate in the states above, but the CPU is in the standby state (see 5.8).
When missing the clock by CSV function *2, *3.
If there is a standby (power-shutdown) transition instruction in the state above, the CPU performs normal standby.
1008
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Chapter 31: Power Consumption Control
Figure 5-6 Restriction on Power-Shutdown and Normal Standby Control
Microcontroller
operation
Standby(Power-shutdown)
transition instruction
STOP=0 and
TIMER=0
Standby(Power-shutdown)
transition wait
STOP=1 or
TIMER=1
OCD connection
Operate by PLL clock
Illegal check
Detecting CSV
CSV check
Detecting no CSV
SHDE=0
SHDE check
SHDE=1
Power-shutdown
Normal Standby
Microcontroller
Stop
*1
*1: This state is not recognized as power-shutdown and the state that the CPU transits to standby mode.
*2: It is the case when stop of operating clock source are detected by CSV circuit. For instance, in the case that the
CPU operates with the CR clock after main clock stop are detected, the CPU does not perform standby control.
However, it is not the limitation case, when sub-clock stop is detected while the CPU run with the main clock.
*3: When standby or power-shutdown transition is directed after the operating clock source is missing, it usually
becomes standby processing. Also, note that the CSV function stops if you enable power-shutdown permission in
a state in which clock stop is not detected.
Only a part of registers is maintained at returning, because power is not being supplied to almost all blocks inside in
standby mode with power-shutdown. Table 5-2 shows the list of registers that are stored at return from standby mode
with power-shutdown.
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Chapter 31: Power Consumption Control
Table 5-2 List of Registers stored at Return from Standby Mode with Power-shutdown
Register group
Register, flag name
Type
Address
Rem
arks
PMUSTR.PMUST
Flag
0590H bit7
PMUSTR.PONR_F
Flag
0590H bit1
PMUSTR.RSTX_F
Flag
0590H bit0
PMUCTLR
Register
0591H
PWRTMCTL
Register
0592H
PMUINTF0
Register
0594H
PMUINTF1
Register
0595H
PMUINTF2
Register
0596H
PMUINTF3
Register
0597H
CPUAR.PMDF
Flag
051AH bit2
CPUAR.PSTF
Flag
051AH bit1
CPUAR.HWDF
Flag
051AH bit0
LVD5R.LVD5R_F
Flag
0584H bit0
LVD5F.LVD5F_F
Flag
0585H bit0
LVD5F.LVD5F_PD
Register
0585H bit7
LVD5F.LVD5F_OE
Register
0585H bit3
LVD.LVD_F
Flag
0586H bit0
LVD.LVD_PD
Register
0586H bit7
LVD.LVD_OE
Register
0586H bit3
CSVCR
Register
056DH
EIRR0/1/2
Register
0550H/0554H/0540H
*2
ENIR0/1/2
Register
0551H/0555H/0541H
*2
ELVR0/1/2
Register
0552H/0556H/0542H
*2
WTDR
Register
055EH-055FH
WTCR
Register
0561H-0563H
WTBR
Register
0565H-0567H
WTHR
Register
0568H
WTMR
Register
0569H
WTSR
Register
056AH
CSELR.SCEN
Flag
0510H bit7
*1
CMONR.SCRDY
Flag
0511H bit7
CCRTSELR.CST
Flag
0530H bit7
CCRTSELR.CSC
Flag
0530H bit0
*1: These registers are initialized at return from stop mode with power-shutdown.
*2: These registers are initialized at PMUCTLR.IOCTMD=0.
*1
*1
*1
PMU register
Reset factor register
Low-voltage detection register
(External low-voltage detection)
Low-voltage detection register
(Internal low-voltage detection)
CSV register
External interrupt register
RTC register
Clock selection register
1010
*1
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Chapter 31: Power Consumption Control
6. Usage Example
Power consumption control usage examples are shown below.
These are examples of activation of sleep mode and standby mode.
Figure 6-1 Examples of Activation of Sleep Mode and Standby Mode
Example when using sleep mode
mode
Example when using standby
- Able to recover on interrupts from peripherals that also operate in sleep mode.
- (Example) Enable interrupts from PPG.
- (Example) Enable interrupts from the base timer
- (Example) Because interrupts from an interval timer are already begin
serviced in order to clear the watchdog timer regularly, perform no preparation
in particular.
- Able to recover on interrupts from external interrupt pins or the NMI pin.
- (Example) Enable external interrupts.
- (Example) Issue instruction so that the NMI pin is used for a companion
chip.
- Not required. Enters sleep from any of the main, PLL, or sub
clock modes.
- Change to the main clock if using the PLL clock.
- Clear the watchdog timer.
Final
preparations
- Configure the pin states before entering standby.
- Clear the watchdog timer.
Final
preparations
- [Example] Sample program that activates sleep mode
LD1 #value_of_sleep, R0 : SLEEP bit = '1', SLVL setting
LD1 #_STBCR,R12
STB R0,@R12
; Write
LDUB @R12,R0
; Read (Enter sleep)
MOV R0,R0
; Dummy operation to adjust pipeline
NOP
; Dummy operation to adjust pipeline
NOP
; Dummy operation to adjust pipeline
- [Example] Sample program that activates watch mode
LD1 #value_of_time, R0: TIMER bit = '1', SLVL setting
LD1 #_STBCR,R12
STB R0,@R12
; Write
LDUB @R12,R0
; Read (Enter watch mode)
MOV R0,R0
; Dummy operation to adjust pipeline
NOP
; Dummy operation to adjust pipeline
NOP
; Dummy operation to adjust pipeline
- Able to recover on interrupts from peripherals that also
operate in sleep mode.
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
- Able to recover on interrupt requests from external interrupt pins and
interrupt requests from the NMI.
- The main clock oscillation stabilization wait time is required in stop mode.
- Return to the clock settings immediately before entering standby as
required.
1011
Chapter 32: Low-Voltage Detection (Internal Low-Voltage
Detection)
This chapter explains the low-voltage detection (internal low-voltage detection).
1. Overview
2. Features
3. Configuration
4. Registers
5. Operation
6. Notes
Code : BZLVDR_LVDI-2v2-91528-3-E
1012
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Chapter 32: Low-Voltage Detection (Internal Low-Voltage Detection)
1. Overview
This section gives an overview of the low-voltage detection (internal low-voltage detection).
The internal low-voltage detection is the function that monitors an internal power supply voltage and detects a fall of
the power supply voltage below the low-voltage detection voltage level. When the internal low-voltage below the
detection voltage level is detected, a detection flag is set and the device goes to the reset state by the low-voltage
detection reset.
Figure 1-1 Block Diagram (Overview)
Voltage Detection circuit
LVDV*:0.9V
0.1V
(To reset control circuit)
Internal power supply low-voltage
detection reset factor
*: The detection voltage of the internal low voltage detection is 0.9V±0.1V. This LVD cannot be used to reliably
generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as this detection level is
below the minimum guaranteed MCU operation voltage.
2. Features
This section explains features of the low-voltage detection (internal low-voltage detection).
The internal low-voltage detection circuit
Function: Generates a reset signal to initialize settings if a voltage LVDV
± 0.1V or less is detected. (LVDV : 0.9 V)
Number of units: 1
Operation: Continues to operate in sleep mode, stop mode, and watch mode.
Voltage comparator: Compares the internal power supply voltage to the detection voltage level, and changes output
from "H" to "L" if a low-voltage is detected.
After the power is turned on the voltage comparator operates constantly.
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Chapter 32: Low-Voltage Detection (Internal Low-Voltage Detection)
3. Configuration
This section shows the configuration of the low-voltage detection (internal low-voltage detection).
Figure 3-1 Configuration Diagram
Voltage comparator
VCC
(To reset control circuit)
Noise canceller
VSS
Internal power supply
low-voltage detection
reset factor
Constant voltage source
4. Registers
This section shows the registers of the low-voltage detection (internal low-voltage detection).
Table 4-1 Registers Map
Registers
Address
0x0584
1014
Register function
+0
+1
+2
+3
LVD5R
LVD5F
LVD
Reserved
Internal low-voltage detection
register
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Chapter 32: Low-Voltage Detection (Internal Low-Voltage Detection)
4.1.
Internal Low-Voltage Detection Register : LVD
(Low-Voltage Detect internal power fall register)
The bit configuration of the internal low-voltage detection register is shown.
This register has the internal low-voltage detection flag (LVD_F) and the control bit.
LVD : Address 0586H (Access : Byte, Half-word, Word)
bit7
bit6
LVD_P
D
bit5
bit4
LVD_SEL[2:0]
bit3
bit2
LVD_OE
bit1
bit0
Reserved
Initial value
0
1
0
0
0
0
Attribute
R/W
R/W1
R/W0
R/W0
R/W
R0,WX
LVD_F
0
0
R0,WX R(RM1), W
[bit7] LVD_PD (Low Voltage Detect fall Power Down)
This bit sets whether a fall of the internal power supply voltage in the microcontroller should be detected or not.
LVD_PD
Setting for detection of internal power
supply voltage fall power down in the
microcontroller
0
Disabled (Detection is executed.)
1
Enabled (Detection is stopped.)
Notes:
·This bit is initialized by only power-on reset.
·Set detection enable (OE = 0) after 100 μs, if this bit sets the status of power-down enable to disable (operation start).
If set it before 100 μs, some detection flag setting will be occur.
[bit6 to bit4] LVD_SEL[2:0] (Low Voltage Detect power fall SELect)
These bits select the detection level of a fall of the internal power supply voltage.
LVD_SEL[2:0]
Setting for detection level of fall of
internal power supply voltage
Guaranteed MCU operation
voltage range
100 *
0.9V ± 0.1V
No
Other than those above
Setting is prohibited
-
Note:
These bits can be rewritten only when LVD_OE="1".
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Chapter 32: Low-Voltage Detection (Internal Low-Voltage Detection)
*: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU
operation voltage, as this detection level is below the minimum guaranteed MCU operation voltage.
[bit3] LVD_OE (Low Voltage Detect power fall Output Enable)
This bit is the output enable signal for internal voltage fall detection.
Internal voltage fall detection output
enable setting
LVD_OE
0
Enable
1
Disable
Note:
This bit is initialized by only power-on reset.
[bit2, bit1] Reserved
[bit0] LVD_F (Low Voltage Detect power fall Flag)
This bit indicates an internal power supply voltage fall detection flag.
Internal power supply fall detection flag
LVD_F
Read
Write
0
Not detected
Clear the flag
1
Detected
No effect on operation
If a fall in the internal power supply voltage is detected, the LVD_F bit is set to "1".
It will be initialized only when the external reset is input.
5. Operation
This section explains operations of the low-voltage detection (internal low-voltage detection).
5.1 Internal Low-voltage Detection
5.1.
Internal Low-voltage Detection
The internal low-voltage detection is explained.
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Chapter 32: Low-Voltage Detection (Internal Low-Voltage Detection)
The internal low-voltage detection is the function that monitors an internal power supply voltage and detects it falling
below the detection voltage level. When the internal low-voltage below the detection level is detected, a detection
flag is set and a reset signal to initialize setting is generated.
If the internal voltage falls below the detection voltage level, it takes the oscillation stabilization wait time after the
internal voltage is recovered. For details, see "CHAPTER: RESET".
Oscillation stabilization wait time
215 × Main clock cycle
6. Notes
This section provides notes on the low-voltage detection (internal low-voltage detection).
Operation of internal low-voltage detection
If the internal power supply voltage falls and the internal low-voltage detection flag in the microcontroller is set
(LVD:LVD_F="1"), internal reset is generated by the function of low-voltage detection reset. Thus, writing and
reading of the internal low-voltage detection register (LVD) in the microcontroller is not allowed.
The internal low-voltage detection circuit can operate even though the device is in its sleep mode, stop mode, and
watch mode, consuming a certain amount of current.
The internal low-voltage detection circuit can be set to operate/stop by a user.
Initial value of internal low-voltage detection flag (LVD:LVD_F)
The internal low-voltage detection flag is cleared by external reset or by writing "0" to the LVD_F bit of the internal
low-voltage detection register (LVD).
Oscillation stabilization wait time
If the internal voltage falls below the detection voltage level, it takes the oscillation stabilization wait time after the
internal voltage recovers. For details, see "CHAPTER: RESET".
Hysteresis of detection/reset release voltage
Since the detection voltage and reset release voltage exhibit hysteresis of 0.1V, the reset release voltage becomes the
set detection voltage + 0.1V. For example, when LVD: 0.9V ± 0.1V is set, the reset release voltage becomes 1.0V ±
0.1V.
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1017
Chapter 33: Low-Voltage Detection (External
Low-Voltage Detection)
This chapter explains the low-voltage detection (external low-voltage detection).
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Notes
Code : BZLVDR_LVDE-2v2-91528-3-E
1018
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Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
1. Overview
This section gives an overview of the low-voltage detection (external low-voltage detection).
The external low-voltage detection is the function that monitors external voltage and detects a fall of the power
supply voltage below the low-voltage detection voltage level.
Figure 1-1 Block Diagram
Voltage
detection circuit
LVDV ± 8%
(Note)
(To reset control circuit)
External Low-Voltage
Detection
Rising LVDV: 2.3V
Falling LVDV: 2.8 to 4.3V (11 steps) variable*
*: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V).
This LVD setting cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU
operation voltage, as this detection level is below the minimum guaranteed MCU operation voltage (2.7V).
2. Features
This section explains features of the low-voltage detection (external low-voltage detection).
Function : Generates the reset signal to initialize settings if the voltage LVDV ±8% or less is detected.
(Rising: LVDV: 2.3V (fixed), falling LVDV: 2.8 to 4.3V (variable))
Number of units : One
· Detects low-voltage at the VCC pin, not at the VCCE pin.
Operation : Switches operation/stop by user’s settings.
During writes to the internal RAM, the low-voltage reset occurs after the write has finished.
Voltage comparator : Compares the detection voltage and the power supply voltage, outputting "L" if low-voltage
is detected.
Either to apply a reset or to generate an interrupt, when a low-voltage is detected, can be selected.
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Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
3. Configuration
This section explains the configuration of the low-voltage detection (external low-voltage detection).
Figure 3-1 Configuration Diagram
VCC
Voltage comparator
(To reset control circuit)
Noise canceller
+
External Low-Voltage
Detection Reset factor
VSS
Constant
voltage supply
4. Registers
This section explains the registers of the low-voltage detection (external low-voltage detection).
Table 4-1 Registers Map
Registers
Address
Register function
+0
0x0584
1020
LVD5R
+1
LVD5F
+2
LVD
+3
Reserved
External low-voltage detection rise detection
register
External low-voltage detection fall detection
register
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Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
4.1.
External Low-Voltage Detection Rise Detection Register :
LVD5R (Low-Voltage Detect external 5v Rise register)
The bit configuration of the external low-voltage detection rise detection register (LVD5R) is shown.
This register is the external power supply voltage rise detection flag.
LVD5R : Address 0584H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
Attribute
bit0
LVD5R_F
0
0
0
0
0
0
0
1
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R(RM1), W
[bit7 to bit1] Reserved
[bit0] LVD5R_F (Low Voltage Detect external 5v Rise Flag): External voltage rise detection flag
This bit is an external voltage rise detection flag.
External power supply rise detection flag
LVD5R_F
Read
Write
0
Not detected
Clear the flag
1
Detected
No effect on operation
If a power-on reset is detected, the LVD5R_F bit is set to "1".
The bit will be cleared when external reset is input.
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1021
Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
4.2.
External Low-Voltage Detection Fall Detection Register :
LVD5F (Low-Voltage Detect external 5v Fall register)
The bit configuration of the external low-voltage detection fall detection register (LVD5F) is shown.
This register is used in order to clear the low-voltage detection reset flag and set the low-voltage detection circuit.
LVD5F : Address 0585H (Access: Byte, Half-word, Word)
bit7
LVD5F_PD
bit6
bit5
bit4
LVD5F_SEL[3:1]
bit3
bit2
bit1
bit0
LVD5F_OE
LVD5F_SEL[0]
LVD5F_RI
LVD5F_F
Initial value
1/0
0
0
0
0
0
0
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R(RM1),W
Note:
The initial value of bit7 is different by device.
[bit7] LVD5F_PD (Low Voltage Detect external 5v Fall Power Down): External power supply fall power down
setting
This bit is used in order to set whether to detect a fall in external voltage or not.
LVD5F_PD
External power supply fall power down setting
0
Invalid (Performs detection) (Initial value "ON". Device option.)
1
Valid (Stops detection) (Initial value "OFF". Device option.)
Notes:
·This bit is initialized by only power-on reset.
·When setting this bit from power down enable to disable (operation start), set to detection enable (LVD5F_OE=0)
100μs after setting LVD5F_OE=1. If set it before 100 μs, some detection flag setting will be occur.
The initial state of external low-voltage detection is different by device. Therefore, the initial value of this bit is
different by device. For details of device, see "3. Product Line-up" in "CHAPTER 1: OVERVIEW".
[bit6 to bit4, bit2] LVD5F_SEL (Low Voltage Detect external 5v Fall SELect): External fall detection voltage
setting
These bits are the selection signal for a detection level of external voltage fall detection.
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Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
LVD5F_SEL[3:0]
External power supply fall
detection voltage setting
Guaranteed MCU operation
voltage range
0000 *
2.80V ±8%
No
0001
3.00V ±8%
0010
3.20V ±8%
0011
3.60V ±8%
0100
3.70V ±8%
0101
3.80V ±8%
0110
3.90V ±8%
0111
4.00V ±8%
1000
4.10V ±8%
1001
4.20V ±8%
1010
4.30V ±8%
others
Setting prohibited
Yes
-
Note:
LVD5F_SEL[3:0] bits can be rewritten only when LVD5F_OE = "1".
*: This LVD setting cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU
operation voltage, as this detection level (2.8V±8% = 2.576V to 3.024V) is below the minimum guaranteed MCU
operation voltage (2.7V).
[bit3] LVD5F_OE (Low Voltage Detect external 5v Fall Output Enable): External power-supply fall detection
output enable setting
This bit is the output enable signal for external voltage fall detection.
LVD5F_OE
External power supply fall detection output enable setting
0
Enable
1
Stop
Note:
This bit is initialized by only power-on reset.
[bit1] LVD5F_RI (Low Voltage Detect external 5v Fall Reset Interrupt select):
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Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
This bit selects either low-voltage detection reset or interrupt.
LVD5F_RI
Low-voltage detection reset / Interrupt selection setting
0
Reset
1
Interrupt
[bit0] LVD5F_F (Low Voltage Detect external 5v Fall Flag): External fall detection flag
This bit is an external voltage fall detection flag.
External voltage fall detection flag
LVD5F_F
Read
Write
0
Not detected
Clear the flag
1
Detected
No effect on operation
If a fall in external voltage is detected, the LVD5F_F bit is set to "1".
This bit is cleared when an external reset is input.
5. Operation
This section explains operation of the low-voltage detection (external low-voltage detection).
The external low-voltage detection monitors the external voltage and generates an initialization reset or interrupt if
the external voltage drops below the configured value.
Those values of this register cannot be guaranteed if a low-voltage is detected and a settings initialization reset occurs.
After the low-voltage reset is released, the reset sequence will be executed without the oscillation stabilization wait
time, and then the program is restarted from the address specified by the reset vector.
6. Notes
This section provides notes on the low-voltage detection (external low-voltage detection).
Notes on using the low-voltage detection reset circuit
Operation by program
The low-voltage detection reset circuit operates in accordance with settings, except for the external low-voltage
detection rise detection which is used as power-on reset.
Because the external low-voltage detection rise detection operates constantly, current is consumed even in sleep
mode, stop mode, and watch mode.
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Chapter 33: Low-Voltage Detection (External Low-Voltage Detection)
Operation in stop mode
The low-voltage detection reset can continue to operate even in stop mode by settings. If a low-voltage is then
detected in stop mode, the settings initialization reset is generated and the stop mode is cleared.
Hysteresis of detection/reset release voltage
Since the detection voltage and reset voltage exhibit hysteresis of 0.1V, the reset release voltage becomes the set
detection voltage + 0.1V.
For fall detection power supply voltage, the set detection voltage indicates the detection voltage. For example,
when 4.1V ± 8% is set, the release voltage becomes 4.2V ± 8%.
For rise detection power supply voltage, the set detection voltage indicates the reset release voltage. For example,
when 2.5V ± 8% is set, the detection voltage becomes 2.4V ± 8%.
Be sure to connect an external reset IC if an interrupt is generated when low-voltage
is detected.
In addition, be sure to set voltage of the reset request signal 2.7V or more at which operation of the CPU is assured.
Figure 6-1 External Reset IC
Low-voltage detection interrupt (2.8V,3.0V,3.2V,3.6V,3.7V,3.8V,3.9V,4.0V,4.1V,4.2V,4.3V)
Reset IC (external)
Low-voltage detection (Internal power supply low-voltage
detection) (fixed at 0.9V)
Vcc5
MB91F52x
Vcc
RSTX
Pxx
Reset IC
Vcc
Reset
xx
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Chapter 34: Wild Register
This chapter explains the wild register.
1. Overview
2. Features
3. Configuration
4. Registers
5. Operation
6. Usage Example
Code : FR81S10_WR-1v1-91528-2-E
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Chapter 34: Wild Register
1. Overview
This section explains the overview of the wild register.
The function of the wild register is to switch the patch target address data that has been set to the address register with
the data that has been set to the data register.
2. Features
This section explains features of the wild register.
Allows 16 locations of 1 word each to be patched.
The target is only the Flash area.
One 16-bit control register
Sixteen 32-bit address setting registers
Sixteen 32-bit data setting registers
3. Configuration
This section explains the configuration of the wild register.
Figure 3-1 Configuration Diagram
To FR81s core
Wild register
S
Flash
S
M
M
M
S
RAM
XBS
On-chip bus
Note:
When the access wait to the Flash memory is set to one cycle, this function cannot be used.
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Chapter 34: Wild Register
4. Registers
This section explains registers of the wild register.
Table 4-1 Registers Map
Registers
Address
Register function
+0
0x0858
+1
+2
Reserved
+3
WREN
Wild register data enabled register
0x0880
WRAR00
Wild register address register 00
0x0884
WRDR00
Wild register data register 00
0x0888
WRAR01
Wild register address register 01
0x088C
WRDR01
Wild register data register 01
0x0890
WRAR02
Wild register address register 02
0x0894
WRDR02
Wild register data register 02
0x0898
WRAR03
Wild register address register 03
0x089C
WRDR03
Wild register data register 03
0x08A0
WRAR04
Wild register address register 04
0x08A4
WRDR04
Wild register data register 04
0x08A8
WRAR05
Wild register address register 05
0x08AC
WRDR05
Wild register data register 05
0x08B0
WRAR06
Wild register address register 06
0x08B4
WRDR06
Wild register data register 06
0x08B8
WRAR07
Wild register address register 07
0x08BC
WRDR07
Wild register data register 07
0x08C0
WRAR08
Wild register address register 08
0x08C4
WRDR08
Wild register data register 08
0x08C8
WRAR09
Wild register address register 09
0x08CC
WRDR09
Wild register data register 09
0x08D0
WRAR10
Wild register address register 10
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Chapter 34: Wild Register
Registers
Address
Register function
+0
+1
+2
+3
0x08D4
WRDR10
Wild register data register 10
0x08D8
WRAR11
Wild register address register 11
0x08DC
WRDR11
Wild register data register 11
0x08E0
WRAR12
Wild register address register 12
0x08E4
WRDR12
Wild register data register 12
0x08E8
WRAR13
Wild register address register 13
0x08EC
WRDR13
Wild register data register 13
0x08F0
WRAR14
Wild register address register 14
0x08F4
WRDR14
Wild register data register 14
0x08F8
WRAR15
Wild register address register 15
0x08FC
WRDR15
Wild register data register 15
4.1.
Wild Register Data Enable Register : WREN
(Wild Register ENable register)
The bit configuration of the wild register data enable register is shown.
This register sets whether the wild register function is enabled or disabled on each channel.
WREN : Address 085AH (Access: Half-word)
bit15
bit14
•
•
•
bit2
bit1
bit0
WREN[15:0]
Initial value
Attribute
0
0
•
•
•
0
0
0
R/W
R/W
•
•
•
R/W
R/W
R/W
[bit15 to bit0] WREN[15:0] (Wild Register ENable) : Enable bits
These bits set whether the wild register function is enabled or disabled on each channel.
WRENn (n = 0 to 15)
Function
0
Disables the wild register function of channel n
1
Enables the wild register function of channel n
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Chapter 34: Wild Register
4.2.
Wild Register Address Register 00 to 15 : WRAR00 to 15
(Wild Register Address Register 00 to 15)
The bit configuration of wild register address register 00 to 15 is shown.
These registers set the address to be amended by the wild register function. The read value is undefined when the wild
register operation is enabled.
Always set these registers in units of 32 bits.
WRAR : Address 0880H to 08F8H (Access: Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
Initial value
0
Attribute R0,WX
bit23
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Reserved
Initial value
0
Attribute R0,WX
bit15
WRAR[21:16]
0
X
X
X
X
X
X
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
bit14
bit13
bit12
bit11
bit10
bit9
bit8
WRAR[15:8]
Initial value
Attribute
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WRAR[7:2]
Initial value
Attribute
Reserved
X
X
X
X
X
X
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R0,WX
R0,WX
[bit21 to bit2] WRAR[21:2] (Wild Register Address Register) : Address register
These bits set the address to patch. The target address is (WRAR & 0x003FFFFC).
The read value is undefined when the wild register operation is enabled.
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Chapter 34: Wild Register
4.3.
Wild Register Data Register 00 to 15 : WRDR00 to 15 (Wild
Register Data Register 00 to 15)
The bit configuration of wild register data register 00 to 15 is shown.
These registers set the replacement data. When the contents of the memory at the addresses specified by the wild
register address registers (WRAR00 to WRAR15) are read, the value set in these registers is returned instead of the
actual contents of the memory.
The read value of these registers is undefined while the wild register function is operating.
Always set these registers in units of 32 bits.
WRDR : Address 0884H to 08FCH (Access: Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
WRDR[31:0]
Initial value
Attribute
X
X
•
•
•
X
X
X
R/W
R/W
•
•
•
R/W
R/W
R/W
[bit31 to bit0] WRDR[31:0] (Wild Register Data Register) : Data register
These bits set the replacement value.
The read value of these registers is undefined while the wild register function is operating.
5. Operation
This section explains the operation of the wild register.
This function is used to patch the Flash area. Because the enable register is initialized by reset, this register needs to
be set on each reset when being used.
Addresses need to be set so that they do not overlap each other. When addresses overlap, the read value is undefined.
The data's byte line is the big endian.
The target area to replace is the Flash area only.
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Chapter 34: Wild Register
6. Usage Example
This section explains a usage example of the wild register.
This section gives an example of using this function. In this example, the settings of this function are called from an
externally attached device after reset is released.
Figure 6-1 Usage Example
• Call the wild register setting routine.
Start
• Prepare communication with externally connected non-volatile
memory or companion chips using CSIO, I 2C, external bus, etc.
Communication
setting
Obtain wild
register content
from external
chip
Check received
content
Wild register
setting
• End if no communication pa rtner.
• Receive 4 bytes (WREN, dummy 2 bytes)
• Receive 128 bytes (WRAR00 to WRAR15, WRDR00 to WRDR15)
• Receive 4 bytes (CRC32)
• Use the CRC to check that no data was lost
notcorrect
correct
• End
EndififCRC
CRCisnot
• If CRC is correct, go to next
• Set WRAR, WRDR, WREN in this order using recei ved data.
• Wild register function becomes acti ve
• Wild register setting routine ends and processing continues.
End
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Chapter 35: Clock Supervisor
This chapter explains the clock supervisor.
1.
Overview
2.
Configuration
3.
Register
4.
Operation
Code : FJ58-1v1-91528-3-E
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Chapter 35: Clock Supervisor
1. Overview
This section explains the overview of the clock supervisor.
If some kind of problem occurs in the clock and it stops unintentionally, the built-in CR oscillator can substitute for
the clock.
The supervisor for the sub clock is independent of the supervisor for the main. The clock supervisor can be enabled,
and disabled separately.
2. Configuration
This section shows the configuration of the clock supervisor.
The blocks that configure the clock supervisor are shown below.
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Clock supervisor
Timeout counter
Control logic
CR oscillator
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Chapter 35: Clock Supervisor
Figure 2-1 Block Diagram (detailed)
32-bit peripheral
Control Logic
* External reset
RST level reset
CSVCR
Power-on reset
Oscillation
stable state
signal
7
6
5
4
3
2
1
0
SCKS
MM
SM
RCE
MSVE
SSVE
-
-
RC-Oscillator
Sub clock missing
detected
Main clock missing
detected
Timeout Counter
NO_MCLK
NO_SCLK
Main clock supervisor
operation enable
RC_CLK
Sub clock supervisor
operation enable
RC_CLK
Sync
Main
Oscillation
MUX
Stage
MUX
Stage
Main clock
MAIN Clock
Main clock
stable state
signal
Supervisor
Sync
Sub-source
oscillation
Sub clock
Sub Clock
Sub clock stable
state signal
Supervisor
RC_CLK
1/2
* : External reset: On assert of RSTX pin (including simultaneous assert with NMIX)
Note:
The sub clock supervisor can be used for dual clock products.
3. Register
This section explains a register of the clock supervisor.
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Chapter 35: Clock Supervisor
Table 3-1 Register Map
Register
Address
Register function
0x056C
3.1.
+0
+1
+2
+3
Reserved
CSVCR
Reserved
Reserved
Clock supervisor control register
Clock Supervisor Control Register : CSVCR (Clock
SuperVisor Control Register)
The bit configuration of the clock supervisor control register (CSVCR) is explained.
This register sets operation mode of clock supervisor.
This register has the bit that shows the breakdown of the clock.
CSVCR : Address 056DH (Access: Byte)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCKS
MM
SM
RCE
MSVE
SSVE
0
0
0
1
1/0
1
0
0
R/W
R,W
R,W
R/W
R/W
R/W
R0/W0
R0/W0
Reserved Reserved
Note:
The initial value of bit3 is different by device.
[bit7] SCKS (Sub Clock mode Select) : Selecting sub clock mode
Be sure to set this bit to "1" when sub clock mode is used with the single clock product.
The sub clock mode, same as the dual clock product, originates from divide-by-two output of the CR.
While the sub clock is being selected as a source clock (CSELR:CKS=11), writing "0" is ignored.
For dual clock product, this bit cannot be used. Be sure to write "0" to this bit.
[MB91F52xxxC/MB91F52xxxE] This bit will be cleared to "0" on power-on, external reset, or simultaneous
assertion with NMIX. Other kind of reset does not affect this bit.
[MB91F52xxxD] This bit will be cleared to "0" on power-on, or external reset. Other kind of reset does not affect this
bit.
SCKS
Description
0
Sub clock mode with CR clock as a source clock is disabled. (Initial value)
1
Sub clock mode with CR clock as a source clock is enabled.
[bit6] MM (Main clock Missing) : Main clock stop
When this bit is "1", it indicates that any problem is found in the main oscillation clock.
When this bit is "0", there are no problems in the main clock.
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Chapter 35: Clock Supervisor
When the main clock is not restored, "0" write access is ignored.
This bit will be cleared to "0" on power-on or external reset. Other types of resets do not affect this bit.
MM
Read
Write
0
Main oscillation clock stop undetected
When the main clock is restored
oscillating, this bit can be cleared
1
Main oscillation clock stop detected
No effect
Note:
Do not enable the PLL/SSCG oscillation operation when this bit is "1".
[bit5] SM (Sub clock Missing) : Sub clock stop
When this bit is "1", it indicates that any problem is found in the sub oscillation clock.
When this bit is "0", there are no problems in the sub clock.
When the sub clock is not restored, "0" write access is ignored.
This bit will be cleared to "0" on power-on or external reset. Other types of resets have no effect on this bit.
This bit will be invalid when the single clock product is set to operate in the sub clock mode (SCKS=1,
CSELR:SCEN=1).
SM
Read
Write
0
Sub oscillation clock stop undetected
When the sub clock is restored oscillating,
this bit can be cleared
1
Sub oscillation clock stop detected
No effect
[bit4] RCE (RC-oscillator Enable) : CR oscillator Enable
The oscillation of the CR oscillator is permitted at the standby mode when this bit is set to "1". Setting this bit to "0"
is prohibited while main clock supervisor or the sub-clock supervisor has been still permitted.
First of all, it is necessary to confirm the MM bit and the SM bit are "0" after prohibiting the supervisor. Afterwards,
sets the RCE bit to "0".
Please do not set the RCE bit to "0" when either of the MM bit or the SM bit is "1". This bit is cleared to "1" by
turning on the power supply or external reset. Other types of resets do not affect this bit.
This bit will be invalid when the single clock product is set to operate in the sub clock mode (SCKS=1,
CSELR:SCEN=1).
RCE
Description
0
CR oscillation disabled at STBY mode
1
CR oscillation enabled at STBY mode (Initial value)
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Chapter 35: Clock Supervisor
[bit3] MSVE (Main clock SuperVisor Enable) : Main clock supervisor enable
When this bit is set to "1", the main clock supervisor is enabled.
This bit is initialized to "1" only when the power is turned on.
Other types of resets do not affect this bit.
MSVE
Description
0
Main clock supervisor disabled (Initial value "OFF". Device option.)
1
Main clock supervisor enabled (Initial value "ON". Device option.)
The initial state of main clock supervisor is different by device. Therefore, the initial value of this bit is different by
device. For details of device, see "3. Product Line-up" in "CHAPTER 1: OVERVIEW".
[bit2] SSVE (Sub clock SuperVisor Enable) : Sub clock supervisor enable
When this bit is set to "1", the sub clock supervisor is enabled.
This bit is initialized to "1" only when the power is turned on.
Other types of resets do not affect this bit.
This bit will be invalid when the single clock product is set to operate in the sub clock mode (SCKS=1,
CSELR:SCEN=1).
SSVE
Description
0
Sub clock supervisor disabled
1
Sub clock supervisor enabled (Initial value)
[bit1] Reserved
"0" should be written to this bit.
[bit0] Reserved
"0" should be written to this bit.
4. Operation
This section explains the operation of the clock supervisor.
After the clock replaces the CR oscillator, it is reset at once when the main clock stops while CPU is operating with
the main clock. When the period of 20μs to 80μs and the clock is not input, it is judged that it stops. Because the bit
indicating that the main clock has stopped remains in the register, it is possible to judge that a problem has occurred
with the software.
After the clock replaces the CR oscillator, it is reset at once when sub clock stops while CPU is operating with sub
clock. When the period of 206μs to 640μs and the clock is not input, it is judged that it stops. Because the bit
indicating that the sub clock has stopped remains in the register, it is possible to judge that a problem has occurred
with the software.
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Chapter 35: Clock Supervisor
When sub clock stops while CPU is working with the main clock, reset is not generated at once. It operates with the
CR clock when changing to the sub clock mode. As for the stop of the sub clock, you can recognize by reading the
register.
The main clock supervisor stops automatically when the main clock is intentionally stopped. When the sub clock is
intentionally stopped, the sub clock supervisor stops automatically.
The CR oscillator stops automatically when the standby mode changes when the CR oscillation at the standby mode
is prohibited. The CR oscillator reactivates automatically when returning from the standby mode.
Note:
Please do not permit the PLL oscillation operation if the main clock operates as a replacement for the CR oscillator
after detecting the main clock stop.
The following explains the operational mode of the clock supervisor.
4.1.
Initial State
This section explains the initial state.
At initial setting, the oscillation of the CR oscillator, main clock supervisor function, and sub clock supervisor
function have been enabled.
CR Oscillator
The oscillation is enabled when the power is turned on.
Only when changing to the standby mode with "0" written in oscillation enable bit (CSVCR.RCE) at the standby
mode, it stops. When the standby mode is released, the oscillation is automatically restarted.
Main Clock Supervisor
For devices whose initial value is ON, the main clock supervisor is enabled after the main oscillation stabilization
wait time has elapsed.
For devices whose initial value is OFF, it is disabled in the initial state. It can be enabled when the clock supervisor is
enabled again.
When the main clock supervisor is enabled, if the main clock stops, the main clock is replaced by the CR oscillation
clock.
Moreover, the MM bit of the CSVCR register is set to "1" and an RST level reset is generated.
For details of the ON/OFF initial settings for devices, refer to "3. Product Line-up" in chapter "OVERVIEW".
Because the main oscillation stabilization wait time is measured by the main clock itself, if the main clock stops
before the oscillation stabilization wait time has elapsed, the main oscillation stabilization wait time does not end and
the main clock supervisor is not enabled.
In this case, after the timeout period measured by the internal CR oscillator has elapsed, the main supervisor function
is enabled regardless of the oscillation stabilization wait time and the main clock stop is detected.
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Chapter 35: Clock Supervisor
Sub Clock Supervisor
After the timeout period measured by internal CR oscillator passes, it is enabled.
When the sub-clock supervisor is enabled, the behavior when a sub-clock stops changes according to whether MCU is
operating with the main clock or with a sub-clock.
For the main clock mode
When a sub-clock stops while operating in the main clock mode, the sub-clock is replaced by the CR oscillation
clock divided by 2. Afterwards, although the SM bit of the CSVCR register is set to "1", operation continues in
the main clock mode with no reset generated.
Under such conditions, if a change to the sub-clock mode takes place, the clock changes to the sub-clock mode
that operates with the CR oscillation clock.
For the sub clock mode
When a sub clock stops while operating in the sub-clock mode, CR oscillation clock divided by 2 replaces a
sub-clock. Afterwards, the SM bit of the CSVCR register is set to "1", and reset of the RST level is generated.
4.2.
Stopping CR Oscillator and the Clock Supervisor Function
This section explains stopping CR oscillator and the clock supervisor function.
CR Oscillator
The CR oscillator can be stopped only at the standby mode. Please change to the standby mode after setting
oscillation permission bit (CSVCR.RCE) at the standby mode to "0".
When there is a problem with the main clock or the sub-clock, the stop of the CR oscillator is prohibited. It can be
confirmed whether or not the problem exists in the clock by the MM bit and the SM bit of the CSVCR register.
The operation clock stops, too, when the CR oscillation is stopped because the operation clock has already replaced
the CR oscillation clock when there is a problem in the clock.
Main Clock Supervisor
The MSVE bit of the CSVCR register is set to "0".
Sub Clock Supervisor
The SSVE bit of the CSVCR register is set to "0".
4.3.
Re-enabling the Clock Supervisor
This section explains re-enabling the clock supervisor.
Main Clock Supervisor
To re-enable the main clock supervisor function, set the MSVE bit of the CSVCR register to "1".
When the CR oscillator is stopped, enabling the main clock supervisor function is prohibited.
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Chapter 35: Clock Supervisor
Because the main oscillation stabilization wait time is measured by the main clock itself, if the main clock stops
before the oscillation stabilization wait time has elapsed, the main oscillation stabilization wait time does not end and
the main clock supervisor is not enabled.
In this case, after the timeout period measured by the internal CR oscillator has elapsed, the main supervisor function
is enabled regardless of the oscillation stabilization wait time and the main clock stop is detected.
Sub Clock Supervisor
To permit the sub clock supervisor function again, the SSVE bit of the CSVCR register is set to "1". When the CR
oscillator is stopped, enabling the sub-clock supervisor function is prohibited.
4.4.
Sub Clock Mode
This section explains the sub clock mode of the clock supervisor.
When the device changes to the sub-clock mode with the main clock supervisor function enabled, the main clock
supervisor function stops automatically.
The main clock supervisor enable bit (CSVCR.MSVE) does not become "0".
After the oscillation stabilization wait time of the main clock passes, the main clock supervisor function is permitted
again when the device changes from the sub-clock mode to the main clock mode.
Because the main oscillation stabilization wait time is measured by the main clock itself, if the main clock stops
before the oscillation stabilization wait time has elapsed, the main oscillation stabilization wait time does not end and
the main clock supervisor is not enabled.
In this case, after the timeout period measured by the internal CR oscillator has elapsed, the main clock supervisor
function is enabled regardless of the oscillation stabilization wait time and the main clock stop is detected.
4.5.
Stop Mode
This section explains stop mode of the clock supervisor.
CR Oscillator
The oscillation stops when oscillation permission bit (CSVCR.RCE) at the stop mode is set to "0" by changing to the
stop mode.
After the stop mode is made clear, it is permitted automatically again.
Main Clock Supervisor
When the main clock supervisor function is enabled, it automatically stops when stop mode is entered.
The main clock supervisor enable bit (CSVCR.MSVE) does not change to "0".
After stop mode is released, the supervisor is automatically re-enabled after waiting for the main oscillation
stabilization wait time.
Because the main oscillation stabilization wait time is measured by the main clock itself, if the main clock stops
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Chapter 35: Clock Supervisor
before the oscillation stabilization wait time has elapsed, the main oscillation stabilization wait time does not end and
the main clock supervisor is not enabled.
In this case, after the timeout period measured by the internal CR oscillator has elapsed, the main supervisor function
is enabled regardless of the oscillation stabilization wait time and the main clock stop is detected.
Note:
When the main clock supervisor function is disabled, if stop mode is entered, the supervisor remains disabled even
after recovering from stop mode.
Sub Clock Supervisor
When the sub clock supervisor function is enabled, it automatically stops when stop mode is entered.
The sub clock supervisor enable bit (CSVCR.SSVE) does not change to "0".
After stop mode is released, the supervisor is automatically re-enabled after waiting for the main oscillation
stabilization wait time.
Note:
When the sub clock supervisor function is disabled, if stop mode is entered, the supervisor remains disabled even
after recovering from stop mode.
4.6.
Watch Mode
This section explains watch mode.
Main Clock Supervisor
The main clock supervisor function is not influenced from the transition to the watch mode.
When the RTC is connected to the main clock with the main clock supervisor function enabled, the system switches
to the CR oscillation clock and a reset is issued when the main clock stops.
The watch mode is made clear, and RTC is initialized.
When the RTC is connected to the main clock with the main clock supervisor function prohibited, even if the main
clock stops it is not detected, with the result that RTC simply stops.
Sub Clock Supervisor
The sub clock supervisor function is not influenced from the transition to the watch mode.
When the RTC is connected to the sub-clock with the sub-clock supervisor function enabled, the system switches to
the CR oscillation clock and a reset is not issued when the sub-clock stops.
When the RTC is connected to the sub-clock with the sub-clock supervisor function prohibited, even if the sub-clock
stops it is not detected, with the result that RTC simply stops.
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Chapter 35: Clock Supervisor
4.7.
Checking the Reset Factor Using the Clock Supervisor
Checking the reset factor using the clock supervisor is shown.
The method for checking whether or not the clock supervisor detected a clock problem and generated a reset is shown
below.
First, read the RSTRR register (see "4.1 Reset Source Register: RSTRR (ReSeT Result Register)" in "CHAPTER:
RESET") to check the reset factor.
[MB91F52xxxC/MB91F52xxxE] If the ERST bit of the RSTRR register is "1", this indicates that either reset input
from the RSTX external pin, illegal standby mode transition detection reset, external power supply low-voltage
detection, clock supervisor reset, or simultaneous assertion of RSTX and NMIX external pins was generated.
[MB91F52xxxD] If the ERST bit of the RSTRR register is "1", this indicates that either reset input from the RSTX
external pin, illegal standby mode transition detection reset, external power supply low-voltage detection, or clock
supervisor reset was generated.
Please read the CSVCR register in this case, and confirm the MM bit. Also, read the RSTRR register (see "4.1 Reset
Source Register: RSTRR (ReSeT Result Register)" in "CHAPTER: RESET") and confirm the reset factor.
The reset factor can be checked as follows.
Table 4-1 Reset Factor
MM
SM
Reset factor
1
0
Main clock supervisor reset
0
1
Sub clock supervisor reset
1
1
Main clock supervisor reset or Sub clock supervisor reset
Because the MM bit and SM bit are not cleared in conditions other than turning the power-on and the external reset, it
is necessary to confirm other reset factors reading the RSTRR register (see "4.1 Reset Source Register: RSTRR
(ReSeT Result Register)" in "CHAPTER: RESET").
4.8.
Return from CR Clock
Return from the CR clock is shown.
Main Clock Supervisor
The main clock stops when the CPU detects that the MM bit has been set after recovering from a reset, and it is
possible to determine that the system has switched to the CR oscillation clock. At this time, it is possible to return to
the main clock by writing "0" in the MM bit if it can be confirmed that the main clock is restored.
When the main clock is not restored, writing "0" in the MM bit does not have any influence. The MM bit keeps
maintaining "1".
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Chapter 35: Clock Supervisor
The MM bit is cleared if the main clock is under operation when "0" is written in the MM bit, and the clock returns to
the main clock via a synchronous stage.
It can perform polling on the MM bit until the main clock is restored.
ldi #_csvcr,r1
clear_CSV_loop:
bandh #0b1001,@r1 ;; Clear MM+SM
btsth #0b0110,@r1 ;; Check: Is one of them 1?
bne clear_CSV_loop
Note:
Set "0" to PMUCTLR.SHDE to return to the main clock.
Sub Clock Supervisor
A sub clock stops when the CPU detects that the SM bit has been set and it is possible to determine that the system
has switched to the CR oscillation clock. At this time, it is possible to return to the sub clock by writing "0" in the SM
bit if it can be confirmed that the sub clock is restored.
When a sub clock is not restored, writing "0" in the SM bit does not have any influence. The SM bit keeps
maintaining "1".
The SM bit is cleared if a sub clock is under operation when "0" is written in the SM bit, and the clock returns to a
sub clock via a synchronous stage.
It can perform polling on the SM bit until a sub-clock is restored. (The same method as main clock supervisor can be
used.)
Note:
Set "0" to PMUCTLR.SHDE to return to the sub clock.
4.9.
Sub Clock Mode Enabled by Setting SCKS Bit
Sub clock mode enabled by setting the SCKS bit is shown.
If the SCKS bit of the single clock product is set to "1", the device can be used in sub clock mode which originates
from divide-by-two output (50kHz) of the CR clock.
For details of procedures to select sub clock mode, see "CHAPTER: CLOCK".
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Chapter 36: Regulator Control
This chapter explains the regulator control.
1.
Overview
2.
Features
3.
Configuration
4.
Register
5.
Operation
Code : BZLVDR_REGU-2v1-91528-2-E
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1045
Chapter 36: Regulator Control
1. Overview
This section explains the overview of the regulator control.
The operation of the regulator that generates the internal voltage is automatically changed according to the device
state transition.
It is changed automatically to following two regulator modes.
Main mode (except when shut down)
Standby mode (at STOP (shutdown) mode and Watch (shutdown) mode)
2. Features
This section explains features of the regulator control.
The regulator mode is automatically changed according to the device state transition.
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Chapter 36: Regulator Control
3. Configuration
This section explains the configuration of the regulator control.
Figure 3-1 Regulator Control Overview Diagram
Output voltage setting
REGSEL
MRSEL
Main
SRSEL
Sub
STRSEL
Regulator
control
Regulator
Standby
Sub/Standby
select (voltage)
To internal
circuit
Mode Select
VCC5
(Note) The difference between the sub mode and the standby mode is only the output voltage settings.
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Chapter 36: Regulator Control
4. Register
This section explains a register of the regulator control.
Table 4-1 Register Map
Registers
Address
0x0580
4.1.
Register Function
+0
+1
+2
+3
REGSEL
Reserved
Reserved
Reserved Regulator Output Voltage Selection Register
Regulator Output Voltage Select Register : REGSEL
(REGulator output voltage SELect register)
The bit configuration of the regulator output voltage selection register is shown below.
This register selects the output voltage level of each regulator mode (main/sub/standby).
REGSEL : Address 0580H (Access : Byte, Half-word, Word)
bit7
bit5
bit4
bit3
bit2
bit1
STRSEL[2:0]
bit0
MRSEL[1:0]
SRSEL[1:0]
0
1
1
0
0
1
1
0
R/W0
R/W1
R/W1
R/W0
R/W1
R/W1
R/W0
R0,WX
Initial value
Attribute
bit6
Reserved
[bit7, bit6] MRSEL[1:0] (Main Regulator voltage SELect)
These bits set the output voltage level of main regulator (regulator mode : main mode).
MRSEL[1:0]
Main regulator output voltage
00
Reserved
01
1.2±0.1V
10
Reserved
11
Reserved
[bit5, bit4] SRSEL[1:0] (Sub Regulator voltage SELect)
These bits set the output voltage level of sub regulator (regulator mode : sub mode).
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Chapter 36: Regulator Control
SRSEL[1:0]
Sub regulator output voltage
00
Reserved
01
Reserved
10
1.2±0.1V
11
Reserved
[bit3 to bit1] STRSEL[2:0] (STandby Regulator voltage SELect)
These bits set the output voltage level of standby regulator (regulator mode : standby mode).
STRSEL[2:0]
Standby regulator output voltage
000
Reserved
001
Reserved
010
Reserved
011
0.9±0.1V
100
Reserved
101
Reserved
110
1.2±0.1V
111
Reserved
Note:
Please use 1.2V as the set value (STRSEL[2:0]=110).
[bit0] Reserved
5. Operation
This section explains the operation of the regulator control.
Before entering standby mode, set STRSEL[2:0] to "110". Note that this value is not set immediately after a reset.
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Chapter 37: External Bus Interface
This chapter explains the external bus interface.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FR81S10_EBI-1v1-91528-3-E
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Chapter 37: External Bus Interface
1. Overview
This section explains the overview of the external bus interface.
This chapter explains each of the functions of the external bus interface.
2. Features
This section explains the features of the external bus interface.
Address up to 22 bits long (4 MByte space) can be output. (The address space can be extended to 8 MByte by
treating the lowermost bit as fixed and extending the upper bit by 1 bit, depending on setting the ACR0 to
ACR3:ADTY bit.)
Supports Address/data split bus
Able to connect to asynchronous memory
Supports Address/data multiplexed bus
Four independent chip select areas (called CS areas below) can be configured, and chip select output
corresponding to each area can be performed
The size of each CS area can be selected from 16 options in the range of 64 KByte to 4 MByte
Each CS area can be set to an arbitrary position within the external bus area
The following functions can be set independently for each CS area
Enabled or disabled
Data bus width (8-bit or 16-bit)
Write prohibited (read-only) setting
Byte order
CS0 area : Big endian
Not CS0 area : Supports big and little endian
Address shift output mode
Bus type selectable for each CS area
Address/data split bus
Address/data multiplexed bus
Type 0 (byte write strobe signal output)
The following timings are configurable for each CS area
Common to read/write access
Address → CS signal setup cycle count
Address strobe signal output cycle count
Extend read/write bus cycle by external ready input
Read access
Read access automatic wait
CS signal → Read strobe signal setup cycle count
Read strobe signal → CS signal hold cycle count
Insert idle cycle between read access and write access
Write access
Write access automatic wait
CS signal → Write strobe signal setup cycle count
Write strobe signal → CS signal hold cycle count
Insert write recovery cycles
Address/data multiplexed bus
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Chapter 37: External Bus Interface
Address output cycle count
When interfacing an external bus at 3.3 V (at 5.0 V for other functions), use bus ready input by selecting RDY_1.
(For information on pin switching, see "CHAPTER: I/O PORTS.")
3. Configuration
This section shows the configuration of the external bus interface.
External bus
Signal generator
Area discriminator
AHB bus controller
1052
External bus control
IO cell
On-chip bus
On chip bus
access acceptor
Register
Figure 3-1 Block Diagram of External Bus Interface
External bus
Access controller
Write data buffer
External bus generation
Buffer
Read data assembly buffer
Read data buffer
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Chapter 37: External Bus Interface
4. Registers
This section explains the registers of the external bus interface.
Table 4-1 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
0x0600
ASR0
CS0 area register
0x0604
ASR1
CS1 area register
0x0608
ASR2
CS2 area register
0x060C
ASR3
CS3 area register
0x0640
ACR0
CS0 bus setting register
0x0644
ACR1
CS1 bus setting register
0x0648
ACR2
CS2 bus setting register
0x064C
ACR3
CS3 bus setting register
0x0680
AWR0
CS0 wait register
0x0684
AWR1
CS1 wait register
0x0688
AWR2
CS2 wait register
0x068C
AWR3
CS3 wait register
0x06C0
Reserved (DMAR0)
ch.0 external DMA transfer register
(This function is not supported by this series.)
0x06C4
Reserved (DMAR1)
ch.1 external DMA transfer register
(This function is not supported by this series.)
0x06C8
Reserved (DMAR2)
ch.2 external DMA transfer register
(This function is not supported by this series.)
0x06CC
Reserved (DMAR3)
ch.3 external DMA transfer register
(This function is not supported by this series.)
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Chapter 37: External Bus Interface
4.1.
CS Area Setting Registers: ASR0 to ASR3 (Area Setting
Register 0-3)
The bit configuration of the CS area setting registers is shown below.
These registers configure the CS areas CS0 to CS3. Each CS area has a single ASR register. Set the CS areas such
that they do not overlap. See "5.10 CS Setting Flow" for the setting procedure for these registers.
ASR0 : Address 0600H (Access : Word)
ASR1 : Address 0604H (Access : Word)
ASR2 : Address 0608H (Access : Word)
ASR3 : Address 060CH (Access : Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
SADR[31:24]
Initial value
Attribute
*1
*1
*1
*1
*1
*1
*1
*1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
SADR[23:16]
Initial value
Attribute
*1
*1
*1
*1
*1
*1
*1
*1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
Attribute
*1
*1
*1
*1
*1
*1
*1
*1
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
WREN
LEDN
CSEN
*1
*1
*1
*1
ASZ[3:0]
Initial value
Attribute
*1 : [Initial value]
*1
R/W
*1
R/W
*1
R/W
*1
R/W
R0,W0
R/W
2
R/W*
R/W
ASR0
0000_0000_0000_0000_0000_0000_1111_0001 B
Other than ASR0 XXXX_XXXX_XXXX_XXXX_0000_0000_XXXX_0XX0 B
*2 : "R0, W0" for ASR0 register.
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Chapter 37: External Bus Interface
[bit31 to bit16] SADR[31:16] (Start ADdRess) : CS Area Start Address
SADR specifies the start address of the CS area. The initial value for ASR0 is "0000_0000_0000_0000", and initial
values for other than ASR0 are undefined. Set the start address in the upper 16 bits of the 32-bit address. The CS area
is the area starting from the address specified in these registers with a range as specified by ASZ[3:0]. The CS area
boundary is determined according to the setting of bits 7 to 4:ASZ[3:0] of these registers. For example, when the CS
area is configured as 1Mbyte using ASZ[3:0]=0100, bit[19:16] of SADR are ignored and only SADR[31:20] has
meaning.
Note:
The address range that can be allocated to the CS area depends on the model. See "APPENDIX".
[bit15 to bit8] Reserved
Always write "0" to these bits.
[bit7 to bit4] ASZ[3:0] (Area SiZe) : CS Area Size
These bits configure the size of the CS area as follows. These bits also specify the bit position within SADR that is
actually compared to the address.
ASZ[3:0]
CS area size
SADR bits that are actually compared to the
address
0000
64Kbyte
SADR[31:16]
0001
128Kbyte
SADR[31:17]
0010
256Kbyte
SADR[31:18]
0011
512Kbyte
SADR[31:19]
0100
1Mbyte
SADR[31:20]
0101
2Mbyte
SADR[31:21]
0110
4Mbyte
SADR[31:22]
0111
8Mbyte
SADR[31:23]
1000
16Mbyte
SADR[31:24]
1001
32Mbyte
SADR[31:25]
1010
64Mbyte
SADR[31:26]
1011
128Mbyte
SADR[31:27]
1100
256Mbyte
SADR[31:28]
1101
512Mbyte
SADR[31:29]
1110
1Gbyte
SADR[31:30]
1111
2Gbyte (Initial value)
SADR[31]
[bit3] Reserved
Always write "0" to this bit.
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Chapter 37: External Bus Interface
[bit2] WREN (WRite ENable) : Write Enable
This bit sets whether writes to the CS area are enabled or disabled.
WREN
Writes enabled or disabled
0
Writes disabled
1
Writes enabled
The initial value for ASR0 is "0", and initial values for other than ASR are undefined.
If a write to a write-disabled area is generated from the internal bus, that access is ignored and the external access is
not performed. For an area to be written such as data area, set WREN to "1".
[bit1] LEDN (Little EnDiaN) : Little Endian
LEDN sets the byte order of the CS area.
ASR0 does not have this bit, and reading this bit always returns "0".
LEDN
Endian
0
Big endian
1
Little endian
Initial values other than ASR0 are undefined.
[bit0] CSEN (Chip Select ENable) : CS Area Enable
This bit sets whether the CS area is enabled or disabled. Operation starts according to the settings of the ASR register,
ACR register, and AWR register by setting CSEN to "1".
CSEN
CS area enabled or disabled
0
Disabled
1
Enabled
The initial value for ASR0 is "1", and initial values for other than ASR are "0".
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Chapter 37: External Bus Interface
4.2.
CS Bus Setting Registers: ACR0 to ACR3 (Area
Configuration Register 0-3)
The bit configuration of the CS bus setting registers is shown below.
These registers set the bus of the CS area. Each CS area has a single ACR register. See "5.10 CS Setting Flow" for the
setting procedure for these registers.
ACR0 : Address 0640H (Access : Word)
ACR1 : Address 0644H (Access : Word)
ACR2 : Address 0648H (Access : Word)
ACR3 : Address 064CH (Access : Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
Initial value
Attribute
*
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Reserved
Initial value
Attribute
*
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
Attribute
*
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADTY
BSTY
Reserved
Reserved
DBW[1:0]
Initial value
*
Attribute
R/W
* [Initial value]
ACR0
Other than ACR0
Reserved
*
*
*
*
*
*
*
R/W
R0,W0
R0,W0
R/W
R/W
RX,W0
RX,W0
0000_0000_0000_0000_0000_0000_0100_0000 B
0000_0000_0000_0000_0000_0000_XX00_XX0XB
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Chapter 37: External Bus Interface
[bit31 to bit8] Reserved
Always write "0" to these bits.
[bit7, bit6] DBW[1:0] (Data Bus Width) : Data Bus Width
These bits set the data bus width.
DBW[1:0]
Data Bus Width
Positions of bits used (D31 to D16)
00
8-bit
D[31:24]
01
16-bit
D[31:16]
10
Reserved (32-bit)
-
11
Reserved (32-bit)
In this series, 32-bit data bus width is not supported.
The initial value for ACR0 is "01". The initial values for other than ACR0 are undefined.
[bit5, bit4] Reserved
Always write "0" to these bits.
[bit3] ADTY (ADdress output TYpe) : Address Type
This bit sets the address output type.
ADTY
Description
0
Normal output
1
During 16-bit addressing, addresses are shifted by 1 bit and output.
See "5.6 Address Information" for details.
The initial value for ACR0 is "00", and initial values for other than ASR are undefined.
[bit2] BSTY (BuS TYpe) : Bus Type
This bit sets the bus type.
BSTY
Description
0
Address/data split bus
1
Address/data multiplexed bus
The initial value for ACR0 is "00", and initial values for other than ASR are undefined.
[bit1, bit0] Reserved
Always write "0" to these bits.
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Chapter 37: External Bus Interface
4.3.
CS Wait Registers : AWR0 to AWR3 (Area Wait Register
0-3)
The bit configuration of the CS wait registers is shown below.
These registers configure each type of wait for the CS areas CS0 to CS3. Each CS area has a single AWR register.
See "5.10 CS Setting Flow" for the setting procedure for these registers.
AWR0 : Address 0680H (Access : Word)
AWR1 : Address 0684H (Access : Word)
AWR2 : Address 0688H (Access : Word)
AWR3 : Address 068CH (Access : Word)
bit31
bit30
bit29
bit28
bit27
bit26
Reserved
Initial value
Attribute
Attribute
*
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
RIDL[1:0]
Attribute
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
RDCS[1:0]
CSWR[1:0]
WRCS[1:0]
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ASCY
Reserved
RDYE
Reserved
*
*
*
*
R/W
R0,W0
ADCY[1:0]
Initial value
WRCV[1:0]
*
CSRD[1:0]
Initial value
bit24
RWT[3:0]
WWT[3:0]
Initial value
bit25
*
ACS[1:0]
*
*
*
Attribute
R/W
R/W
R/W
R/W
R/W
R0,W0
* [Initial value] AWR0
0000_1111_0000_0000_1111_0000_0000_0000B
Not AWR0 0000_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_X0X0B
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[bit31 to bit28] Reserved
Always write "0" to these bits.
[bit27 to bit24] RWT[3:0] (Read access auto WaiT) : Read Access Auto Wait
RWT[3:0] sets the number of auto wait cycles when fetching data during the read access cycle.
RWT[3:0]
Read access wait
0000
0 cycle
0001
1 cycle
0010
2 cycles
0011
3 cycles
:
:
1110
14 cycles
1111
15 cycles (AWR0 Initial value)
[bit23 to bit20] WWT[3:0] (Write access auto WaiT) : Write Access Auto Wait
WWT[3:0] sets the number of auto wait cycles during the write access cycle.
WWT[3:0]
Write access wait
0000
0 cycle (AWR0 Initial value)
0001
1 cycle
0010
2 cycles
0011
3 cycles
:
:
1110
14 cycles
1111
15 cycles
[bit19, bit18] RIDL[1:0] (Read access IDLe cycle) : Read Access Idle Cycle
RIDL[1:0] is configured in order to prevent conflicts on the data bus between the read data from a device with a long
output off time and the data of the subsequent access. If an access meeting any of the following conditions occurs in
sequence after a read access, the idle cycles specified in RIDL are inserted after the read access.
Write access
Access to another CS area
Access to a CS area configured with address/data multiplexed bus type
For the case of sequential read accesses to the same CS area configured with split bus type (ACR:BSTY=0), idle
cycles are not inserted by RIDL. During idle cycles, all CS signals are negated and the data pins are put in the
high-impedance state.
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RIDL[1:0]
Read Access Idle Cycle
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
[bit17, bit16] WRCV[1:0] (Write ReCoVery cycle) : Write Recovery Cycle
This bit sets the write recovery cycle and is configured to control access to devices that have a limit on the interval
between a write access and the next access. During write recovery cycles, all of the chip select signals are negated and
write strobe signal WRnX (n=0, 1) is also held negated. Furthermore, new accesses are not started within this period.
When the write recovery cycle is set to 1 cycle or higher, the write recovery cycle is always inserted after the write
access.
WRCV[1:0]
Write recovery cycle
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
[bit15, bit14] CSRD[1:0] (CSnX to RDX setup cycle) : CSnX to RDX Setup Cycle
CSRD[1:0] configures the read access CSnX to RDX setup cycles which set the period until RDX is asserted after
CSnX is asserted.
In order to correctly establish the protocol when address/data multiplexed bus is configured (ACR:BSTY=1), set the
AWR parameters to satisfy the following conditions.
ACS + CSRD ≥ 1 and ACS + CSWR ≥ 1
CSRD[1:0]
CSnX → RDX setup extension cycle
00
0 cycle
01
1 cycle
10
2cycles
11
3 cycles (AWR0 Initial value)
[bit13, bit12] RDCS[1:0] (RDX to CSnX hold cycle) : RDX to CSnX Hold Cycle
RDCS[1:0] configures the read access RDX to CSnX hold cycles which set the period until CSnX is negated after
RDX is negated.
RDCS[1:0]
RDX → CSnX hold extension cycle
00
0 cycle
01
1 cycle
10
2 cycles
11
3 cycles (AWR0 Initial value)
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[bit11, bit10] CSWR[1:0] (CSnX to WRnX setup cycle) : CSnX to WRnX Setup Cycle
CSWR[1:0] configures the write access CSnX to WRnX setup cycles which set the period until WRnX is asserted
after CSnX is asserted.
In order to correctly establish the protocol when address/data multiplexed bus is configured (ACR:BSTY=1), set the
AWR parameters to satisfy the following conditions.
ACS + CSRD ≥ 1 and ACS + CSWR ≥1
CSWR[1:0]
CSnX → WRnX setup extension cycle
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
[bit9, bit8] WRCS[1:0] (WRnX to CSnX hold cycle) : WRnX to CSnX Hold Cycle
WRCS[1:0] configures the write access WRnX to CSnX hold cycles which set the period until CSnX is negated after
WRnX is negated.
WRCS[1:0]
WRnX → CSnX hold extension cycle
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
[bit7, bit6] ADCY[1:0] (ADdress CYcle) : Address Output Extension Cycle Count
ADCY[1:0] sets the number of extension cycles for outputting addresses to the data bus during access to CS areas
configured with address/data multiplexed bus type. The settings of these bits are only valid when the bus type is set to
address/data multiplexed.
In order to correctly establish the protocol when ADCY is set to 1 or higher, set the AWR parameters to satisfy the
following conditions.
ADCY + 1 ≤ ACS + CSRD and ADCY + 1 ≤ ACS + CSWR
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ADCY[1:0]
Number of address output extension cycles during address/data
multiplexing
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
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[bit5, bit4] ACS[1:0] (A00 to A21 to CSnX delay cycle) : A00 to A21 to CSnX Delay Cycle Count
ACS[1:0] sets the number of delay cycles from outputting A00 to A21 and ASX to outputting CSnX. This is used
when the address for CSnX assert needs to be setup for a fixed time, or when CSnX edges are required when
accessing the same chip select area in sequence.
ACS[1:0]
A00 to A21 → CSnX delay cycle count
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
[bit3] ASCY (ASX CYcle) : ASX Output Extension Cycle Count
ASCY sets the number of cycles to extend ASX output. The minimum ASX output extension cycle is 1 cycle.
ASCY
ASX output extension delay cycle count
0
0 cycle (AWR0 Initial value)
1
1 cycle
[bit2] Reserved
Always write "0" to this bit.
[bit1] RDYE (RDY Enable) : RDY Enable
RDYE sets whether the wait insertion function by external RDY pin is enabled or disabled.
RDYE
RDY pin enable
0
Wait insertion by RDY pin disabled (AWR0 initial value)
1
Wait insertion by RDY pin enabled
Note:
When interfacing an external bus at 3.3 V (at 5.0 V for other functions), use bus ready input by selecting RDY_1.
(For information on pin switching, see "CHAPTER: I/O PORTS.")
[bit0] Reserved
Always write "0" to this bit.
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4.4.
External DMA Transfer Registers: DMAR0-3 (DMA transfer
Register 0-3)
The bit configuration of the external DMA transfer registers is shown below.
These registers set the external pins for DMA transfers. This function is not supported by this series.
DMAR0 : Address 06C0H (Access : Word)
DMAR1 : Address 06C4H (Access : Word)
DMAR2 : Address 06C8H (Access : Word)
DMAR3 : Address 06CCH (Access : Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Reserved
Initial value
*
Attribute R0,W0
bit23
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Reserved
Initial value
*
Attribute R0,W0
bit15
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
*
Attribute R0,W0
bit7
*
*
*
*
*
*
*
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit6
bit5
bit4
bit3
bit2
bit1
bit0
REQL
ACKMD
ACKL
EOPL
0
0
0
0
R/W0
R/W0
R/W0
Reserved
Initial value
*
*
*
*
Attribute R0,W0 R0,W0 R0,W0 R0,W0
R/W0
* [Initial value] 0000_0000_0000_0000_0000_0000_0000_0000 B
[bit31 to bit4] Reserved
Always write "0" to these bits.
[bit3] REQL
When writing, always write "0" to this bit.
[bit2] ACKMD
When writing, always write "0" to this bit.
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[bit1] ACKL
When writing, always write "0" to this bit.
[bit0] EOPL
When writing, always write "0" to this bit.
5. Operation
This section explains the operation of the external bus interface.
5.1 External Pin Table
5.2 External Bus Signal Protocol
5.3 Address Alignment
5.4 Split Access
5.5 Data Alignment
5.6 Address Information
5.7 Idle Cycle Insertion Function
5.8 External Bus Output Signal Timing Settings
5.9 RDY Pin Access Cycle Extension Function
5.10 CS Setting Flow
5.11 Example of Connecting to Asynchronous Memory
5.12 Example of Connection to Little Endian Device
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5.1.
External Pin Table
This section shows the external pin table.
Table 5-1 shows the external pins for the external bus interface of this series.
Table 5-1 External Pin Table
Pin number of this series
External pin of
BGA
this series
144pin 176pin 208pin
416pin
1066
Description
SYSCLK
35
43
51
AB2
System clock output
ASX
5
7
7
E1
CS0X
6
8
8
E2
CS1X
7
9
9
F1
CS2X
38
46
54
AF3
CS3X
39
49
57
AE3
RDX
8
10
10
F2
WR0X
9
11
11
G1
WR1X
10
12
12
G2
RDY_0
41
51
59
AE5
Bus ready input (0)
RDY_1
18
22
26
R3
Bus ready input (1)
D16
131
159
187
A10
D17
132
160
188
B10
D18
133
161
189
A9
D19
134
162
190
B9
D20
135
163
191
A8
D21
136
165
193
B8
D22
137
167
195
A7
D23
138
168
196
B7
D24
139
170
198
A6
D25
140
171
203
B6
D26
141
172
204
A5
D27
142
174
206
B5
D28
143
175
207
A4
D29
2
2
2
C1
D30
3
3
3
D1
D31
4
5
5
D2
Address strobe output
Chip selected output
Read strobe output
Write strobe output
Data input/output and address
output
(during address multiplexing)
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Pin number of this series
External pin of
BGA
this series
144pin 176pin 208pin
416pin
A00
11
14
14
H1
A01
12
15
15
J1
A02
13
17
17
J2
A03
14
18
18
K1
A04
15
19
19
K2
A05
16
20
24
L1
A06
17
21
25
L2
A07
20
24
28
R1
A08
21
25
29
R2
A09
22
26
30
T1
A10
23
29
33
T2
A11
24
30
34
U1
A12
25
31
35
U2
A13
26
32
36
V1
A14
27
33
37
V2
A15
28
34
38
W1
A16
29
35
43
W2
A17
30
37
45
Y1
A18
31
39
47
Y2
A19
32
40
48
AA1
A20
33
41
49
AA2
A21
34
42
50
AB1
Description
Address output
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5.2.
External Bus Signal Protocol
This section shows the external bus signal protocol.
5.2.1.
Address/Data Split Bus Read Protocol
This section shows the read protocol for address/data split bus.
This section shows the protocol for read access using an address/data split bus.
Figure 5-1 Address/Data Split Bus (Read Operation Example)
cycle no.
0
1
2
3
4
5
6
7
SYSCLK
ASX
A00 to A21
A0
CSnX
(n=0,1,2,3)
RDX
H: Dxx is input
L: Dxx is output
Dxx
D0
Operation example description
cycle1 : "L" is output to ASX for 1 cycle to indicate that access is starting from this cycle. A00 to A21 indicate the
address information of the access destination for this cycle.
cycle2 : After the configured count has finished from when the access started, "L" begins to be output to CSnX (n= 0
to 3), and continues until the access finishes. Devices on the external bus need to perform processing for the access
only within the period where CSnX="L".
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cycle3 : After the configured count has finished from when the output of CSnX="L" started, "L" is output to RDX.
External bus devices are required to return read data to D16 to D31 within the strobe period indicated by RDX="L".
cycle4 : After the configured count has finished from when the output of RDX="L" started, RDX output is returned to
"H". STU fetches data from D16 to D31 to the internal buffer at the rising edge for the last SYSCLK within the
period RDX=L.
cycle5 : The output of CSnX returns to "H" after the configured count finishes from when RDX returns to "H", and
the read access finishes. In this example, CSnX returns to "H" when this cycle ends and the read access finishes.
Signal description
External bus output signals are synchronized to the rising edge of SYSCLK.
ASX
Indicates the start of access. This also functions as the address strobe.
An "L" pulse is output for a period of 1 or 2 cycles from when the access starts.
A00 to A21
Outputs the address information of the access destination.
This is output from when the access starts and continues until the access finishes.
CSnX (n=0 to 3)
Indicates that the access destination address is within the corresponding CS area. External bus devices are required to
process requests from the bus only when this signal is "L". After the configured count has finished from when the
access started, "L" begins to be output, and this continues until the access finishes.
RDX
Indicates the period of the read strobe. After the configured count ends from when CSnX (n=0 to 3) is driven, this
outputs "L" for read access. This returns to output "H" after the read auto wait count has ended. The external bus
device is required to return valid data in D16 to D31 within the period where RDX="L". This module fetches the D16
to D31 data into the internal buffer on the rising edge of the final SYSCLK within the period where RDX="L".
D16 to D31
The external bus device is required to return valid data in D16 to D31 within the period where RDX="L". This
module fetches the D16 to D31 data into the internal buffer on the rising edge of the final SYSCLK within the period
where RDX="L".
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5.2.2.
Address/Data split bus write protocol
This section shows the write protocol for address/data split bus.
This section shows the protocol for write access using an address/data split bus.
Figure 5-2 Address/Data Split Bus (Write Operation Example)
cycle no.
0
1
2
3
4
5
6
7
SYSCLK
ASX
A00 to A21
A0
CSnX
(n=0,1,2,3)
WRnX
(n=0,1)
H: Dxx is input
L: Dxx is output
Dxx
D0
Operation example description
cycle1 : "L" is output to ASX for 1 cycle to indicate that access is starting from this cycle. A00 to A21 indicate the
address information of the access destination for this cycle.
cycle2 : After the configured count has finished from when the access was started, "L" is output to CSnX (n=0 to 3).
CSnX continues to output "L" until the access is complete. Devices on the external bus need to execute processing for
the access only within the period where CSnX="L".
cycle3 : After the configured count has finished after "L" starts being output to CSnX, "L" is output to WRnX (n=0,
1). External bus devices are required to fetch the value of D16 to D31 within the write strobe period where "L" is
output to WRnX.
cycle4 : After the configured count has finished from when WRnX="L" starts being output, the output of WRnX
returns to "H" and the write strobe period ends. In this example, the write strobe period is extended by 1 cycle. At the
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end of this cycle, the output of WRnX returns to "H" and the strobe period ends.
cycle5 : The output of CSnX returns to "H" after the configured count finishes from when WRnX returns to "H", and
the write access finishes. In this example, CSnX returns to "H" when this cycle ends and the write access finishes.
Signal description
External bus output signals are synchronized to the rising edge of SYSCLK.
ASX
Indicates the start of access. This also functions as the address strobe.
An "L" pulse is output for a period of 1 or 2 cycles from when the access starts.
A00 to A21
Outputs the address information of the access destination.
This is output from when the access starts and continues until the access finishes.
CSnX (n=0 to 3)
Indicates that the access destination address is within the corresponding CS area. External bus devices are required to
process requests from the bus only when this signal is "L". After the configured count has finished from when the
access started, "L" begins to be output, and this continues until the access finishes.
WRnX (n=0, 1)
Indicates the period of the write cycle strobe. After the configured count ends from when CSnX (n=0 to 3) is driven,
this outputs "L" for write access. This returns to output "H" after the write auto wait count has ended. External bus
devices are required to fetch the data of D16 to D31 within the period where WRnX (n=0, 1)="L".
D16 to D31
Write data is output from when the access begins. The write data output continues until the access finishes. External
bus devices are required to fetch the data of D16 to D31 within the period where WRnX="L".
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5.2.3.
Address/data multiplexed bus read protocol
This section shows the read protocol for address/data multiplexed bus.
This section shows the protocol for read access using an address/data multiplexed bus.
Figure 5-3 Address/Data Multiplexed Bus (Read Operation Example)
cycle no.
0
1
2
3
4
5
6
7
SYSCLK
ASX
CSnX
(n=0,1,2,3)
RDX
H: Dxx is input
L: Dxx is output
Dxx (output)
A0
Dxx (input)
D0
Operation example description
cycle1 : "L" is output to ASX to indicate that access is starting from this cycle. Address information A0 is output to
data bus D16 to D31. ASX functions as the strobe signal for this address information. This address information is
output for the configured count cycles. After the configured count has finished, D16 to D31 are put into the input
state.
cycle2 : After the configured count has finished from the access starting, "L" is output to CSnX (n= 0 to 3)
continually until the access is complete. Devices on the external bus need to perform processing for the access only
within the period where CSnX="L".
cycle3 : "L" is output to RDX after the configured count from when CSnX="L" output is started. External bus devices
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are required to return read data to D16 to D31 within the strobe period indicated by RDX="L".
cycle4 : The output to RDX returns to "H" after the configured count finishes after output of RDX="L" begins. The
data on D16 to D31 is fetched into the internal buffer on the rising edge of the final SYSCLK within the period where
RDX="L".
cycle5 : The output of CSnX (n=0 to 3) returns to "H" after the configured count finishes from when RDX returns to
"H", and the read access finishes. In this example, CSnX returns to "H" when this cycle ends and the read access
finishes.
Signal description
External bus output signals are synchronized to the rising edge of SYSCLK.
ASX
Indicates the start of access. This also functions as the address strobe.
An "L" pulse is output for a period of 1 or 2 cycles from when the access starts.
CSnX (n=0 to 3)
Indicates that the access destination address is within the corresponding CS area. External bus devices are required to
process requests from the bus only when this signal is "L". After the configured count has finished from when the
access started, "L" begins to be output, and this continues until the access finishes.
RDX
Indicates the period of the read strobe. After the configured count ends from when CSnX (n=0 to 3) is driven, this
outputs "L" for read access. This returns to output "H" after the read auto wait count has ended. The external bus
device is required to return valid data in D16 to D31 within the period where RDX="L". This module fetches the D16
to D31 data into the internal buffer on the rising edge of the final SYSCLK within the period where RDX="L".
D16 to D31
Address information is output from when the access begins. After the configured count has finished, this enters the
input state and accepts the read data from the external bus device. This module fetches the D16 to D31 data into the
internal buffer on the rising edge of the final SYSCLK within the period where RDX="L".
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5.2.4.
Address/Data multiplexed bus write protocol
This section shows the write protocol for address/data multiplexed bus.
This section shows the protocol for write access using an address/data multiplexed bus.
Figure 5-4 Address/Data Multiplexed Bus (Write Operation Example)
cycle no.
0
1
2
3
4
5
6
7
SYSCLK
ASX
CSnX
(n=0,1,2,3)
WRnX
(n=0,1)
H: Dxx is input
L: Dxx is output
Dxx
A0
D0
Operation example description
cycle1 : The cycle where access begins. "L" is output to ASX to indicate the start of access. Address information is
output to D16 to D31. ASX functions as the strobe signal for this address information. This address information is
output for the configured count cycles.
cycle2 : After the configured count has finished from the access starting, "L" is output to CSnX (n= 0 to 3)
continually until the access is complete. Devices on the external bus need to perform processing for the access only
within the period where CSnX="L".
cycle3 : After the configured count has finished after "L" starts being output to CSnX, "L" is output to WRnX (n=0,
1). External bus devices are required to fetch the value of D16 to D31 within the write strobe period indicated by
WRnX="L".
cycle4 : After the configured count has finished from when WRnX="L" starts being output, the output of WRnX
returns to "H" and the write strobe period ends. In this example, the write strobe period is extended by 1 cycle. At the
end of this cycle, the output of WRnX returns to "H" and the write strobe period ends.
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cycle5 : The output of CSnX returns to "H" after the configured count finishes from when WRnX returns to "H", and
the write access finishes. In this example, CSnX returns to "H" when this cycle ends and the write access finishes.
Signal description
External bus output signals are synchronized to the rising edge of SYSCLK.
ASX
Indicates the start of access. This also functions as the address strobe.
An "L" pulse is output for a period of 1 or 2 cycles from when the access starts.
CSnX (n=0 to 3)
Indicates that the access destination address is within the corresponding CS area. External bus devices are required to
process requests from the bus only when this signal is "L". After the configured count has finished from when the
access started, "L" begins to be output, and this continues until the access finishes.
WRnX (n=0, 1)
Indicates the period of the write strobe. After the configured count ends from when CSnX is driven, this outputs "L"
for write access. This returns to output "H" after the write auto wait count has ended. External bus devices are
required to fetch the data of D16 to D31 within the period where WRnX="L".
D16 to D31
Outputs the address information of the access destination from when the access starts. The write data begins to be
output after the configured count ends, and continues until the access finishes. External bus devices are required to
fetch the value of D16 to D31 within the write strobe period.
5.3.
Address Alignment
This section shows the address alignment.
The external bus interface does not detect misalignment errors in the access destination address. As a result, word
access and half-word access are performed as follows.
Word access
Regardless of whether the lowermost 2 bits of the address specified by the program are "00", "01", "10", or "11", the
lowermost 2 bits of the output address are "00".
Half-word access
If the lowermost 2 bits of the address specified by the program are "00" or "01, the lowermost 2 bits of the output
address are "00", and if the lowermost 2 bits are "10" or "11", then the lowermost 2 bits of the output address are
"10".
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5.4.
Split Access
This section shows the split access.
If the access size is larger than the bus width, this is executed by splitting a single access.
Table 5-2 Number of Split Accesses
Access size
Bus width
Byte
Half-word
Word
8-bit
1 time
2 times
4 times
16-bit
1 time
1 time
2 times
5.5.
Data Alignment
This section shows the data alignment.
Each CS area supports both big endian and little endian. However, CS0 only supports big endian. The data bus width
can be selected between 8-bit and 16-bit for each CS area.
The following shows the data alignment for the external access size and the corresponding control signals for each
endian setting and data bus width setting.
Table 5-3 Big Endian - 16 bits
Access
Size
Output pins
Address
lowermost
2 bits
Split
access
A01, A00
D31 to
D24
00
-
00
bit7 to bit0
01
-
01
10
-
10
11
-
11
0n
-
00
bit15 to bit8
bit7 to bit0
○
○
1n
-
10
bit15 to bit8
bit7 to bit0
○
○
First split
access
00
bit31 to
bit24
bit23 to
bit16
○
○
Second split
access
10
bit15 to bit8
bit7 to bit0
○
○
D23 to
D16
○
○
bit7 to bit0
○
bit7 to bit0
Half-word
1076
○
bit7 to bit0
Byte
Word
WR0X WR1X
nn
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Chapter 37: External Bus Interface
Table 5-4 Big Endian - 8 bits
Access
Size
Output pins
Address
lowermost
2 bits
Split
access
A01, A00
D31 to D24
D23 to
D16
WR0X WR1X
00
-
00
bit7 to bit0
-
○
-
01
-
01
bit7 to bit0
-
○
-
10
-
10
bit7 to bit0
-
○
-
11
-
11
bit7 to bit0
-
○
-
First split
access
00
bit15 to bit8
-
○
-
Second split
access
01
bit7 to bit0
-
○
-
First split
access
10
bit15 to bit8
-
○
-
Second split
access
11
bit7 to bit0
-
○
-
First split
access
00
bit31 to bit24
-
○
-
Second split
access
01
bit23 to bit15
-
○
-
Third split
access
10
bit15 to bit8
-
○
-
Fourth split
access
11
bit7 to bit0
-
○
-
Byte
0n
Half-word
1n
Word
nn
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Table 5-5 Little Endian - 16 bits
Access
Size
Output pins
Address
lowermost
2 bits
Split
access
A01, A00
D31 to
D24
D23 to
D16
00
-
00
bit7 to bit0
-
○
-
01
-
01
-
bit7 to bit0
-
○
10
-
10
bit7 to bit0
-
○
-
11
-
11
-
bit7 to bit0
-
○
0n
-
00
bit7 to bit0
bit15 to bit8
○
○
1n
-
10
bit7 to bit0
bit15 to bit8
○
○
First split
access
00
bit7 to bit0
bit15 to bit8
○
○
Second split
access
10
bit23 to
bit16
bit31 to
bit24
○
○
Byte
Half-word
Word
WR0X WR1X
nn
Table 5-6 Little Endian - 8 bits
Access
Size
Output pins
Address
lowermost
2 bits
Split access
00
-
00
bit7 to bit0
-
○
-
01
-
01
bit7 to bit0
-
○
-
10
-
10
bit7 to bit0
-
○
-
11
-
11
bit7 to bit0
-
○
-
First split access
00
bit7 to bit0
-
○
-
Second split
access
01
bit15 to bit8
-
○
-
First split access
10
bit7 to bit0
-
○
-
Second split
access
11
bit15 to bit8
-
○
-
A01, A00 D31 to D24 D23 to D16 WR0X WR1X
Byte
0n
Half-word
1n
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Access
Size
Word
5.6.
Output pins
Address
lowermost
2 bits
nn
Split access
A01, A00 D31 to D24 D23 to D16 WR0X WR1X
First split access
00
bit7 to bit0
-
○
-
Second split
access
01
bit15 to bit8
-
○
-
Third split access
10
bit23 to bit16
-
○
-
Fourth split access
11
bit31 to bit24
-
○
-
Address Information
This section shows the address information.
5.6.1.
Address information and output pins
This section shows the address information and output pins.
Address/data split bus
22-bit address information is output to A00 to A21.
Address/data multiplexed bus
In the address/data multiplexed bus, the address information is output to data bus pins D16 to D31 during the
address output cycle. The address bit width that can be output is determined by the data bus width setting. Even
while address/data multiplexed bus is selected, the address is output to address pins A00 to A21. The missing
parts of address information output to pins D16 to D31 can be supplemented by using address pins A00 to A21.
5.6.2.
Address type
This section shows the address type.
The output of address information can be selected from normal type that outputs as normal and the shift type that
outputs using bit shift. This is set using ACR:ADTY.
ADTY=0
The normal output mode. The address information is output directly to the pins without bit shifting.
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ADTY=1
Address shift output mode. The address bus information is output to the pins after bit shifting.
The relationship between the address type (ACR:ADTY), bus type (ACR:BSTY), bus width, output address
information, and address output pins is as follows.
Table 5-7 Output Address and Output Pins
ACR register
ADTY
BSTY
0
0
Bus
width
[bit]
A21 to A00
Output pins D31 to D16 during address output
cycle
D31 to D24
D23 to D16
Address[21:0]
-
-
8
Address[21:0]
Address[7:0]
-
16
Address[21:0]
Address[15:8]
Address[7:0]
8
Address[21:0]
-
-
16
Address[22:1]
8
Address[21:0]
Address[7:0]
-
16
Address[22:1]
Address[16:9]
Address[8:1]
8
16
0
1
1
5.7.
1
0
1
Idle Cycle Insertion Function
This section shows the idle cycle insertion function.
Idle cycles can be inserted between accesses. The next access does not start during the idle cycle even if there is a
request, but starts after the idle cycle count finishes.
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Chapter 37: External Bus Interface
Figure 5-5 Idle Cycle Inserted
SYSCLK
ASX
Idle cycle
0
3
CSnX
(n=0,1,2,3)
H: Dxx is input
L: Dxx is output
Read access idle cycles
If an access meeting any of the following conditions occurs in sequence after a read access, idle cycles are inserted
after the read access. This is configured using AWR:RIDL[1:0].
Write access
Access to another CS area
Access to a CS area configured with address/data multiplexed bus type
Note:
The only time when idle cycles are not inserted by RIDL is when sequential read accesses are performed on the same
CS area configured for split bus type.
Write recovery cycles
Idle cycles are inserted after a write access ends. This is configured using AWR:WRCV[1:0].
5.8.
External Bus Output Signal Timing Settings
This section shows the external bus output signal timing settings.
The external bus signal output timing is determined by the following parameters. The timing parameters are
determined by the values set in the registers.
Address/Data split bus timing parameters
This section shows the timing parameters that can be configured in the address/data split bus.
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Figure 5-6 Address/Data Split Bus Timing Parameters
SYSCLK
ASCY
1
0
ASX
RIDL[1:0] or
WRCV[1:0]
3
0
A CS [1 :0]
0
3
CSnX
(n=0,1,2,3)
RWT[3:0]
CSRD[1:0]
0
RDCS[1:0]
3 0
15
3 0
WWT[3:0]
15
3
0
RDX
CSWR[1:0]
0
WRCS[1:0]
3
0
WRnX (n=0,1)
*
A00 to A21, Dxx
H: Dxx is input
L: Dxx is output
* : A00 to A21 and Dxx extend the number of cycles and valid value output specified by RDCS during
read access and by WRCS during write access.
Table 5-8 Address/Data Split Bus Timing Parameters
Parameter name
Function name
Description
ASCY(ASX CYcle)
ASX output extension cycle
count
"L" is output to ASX for (ASCY+1) cycles
from when the access starts.
ACS[1:0]
(A00 to A21 to CSnX
delay cycle)
A00 to A21 → CSnX delay
cycle count
Output of "L" to CSnX (n=0 to 3) starts after
the ACS count has finished from ASX output.
CSRD[1:0]
(CSnX to RDX setup cycle)
CSnX → RDX setup cycle
During read access, after CSRD count from
CSnX "L" output start, "L" output to RDX
starts.
RWT[3:0]
(Read access auto WaiT)
Read access auto wait
During read access, after (RWT+1) count
from RDX "L" output start, RDX output is
returned to "H".
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Parameter name
Function name
Description
RDCS[1:0]
(RDX to CSnX hold cycle)
RDX → CSnX hold cycle
During read access, after RDCS count from
the cycle when RDX output is returned to
"H", CSnX output is returned to "H".
CSWR[1:0]
(CSnX to WRnX setup
cycle)
CSnX → WRnX setup cycle
During write access, after CSWR count from
CSnX "L" output start, "L" output to WRnX
starts.
WWT[3:0]
(Write access auto WaiT)
Write access auto wait
During write access, after (WWT+1) count,
WRnX (n=0, 1) output is returned to "H".
WRCS[1:0]
(WRnX to CSnX hold
cycle)
WRnX → CSnX hold cycle
During write access, after WRCS count from
the cycle when WRnX output is returned to
"H", CSnX output is returned to "H".
RIDL[1:0]
(Read access IDLe cycle)
Read access idle cycle
After a read access has finished, the next
access is able to start after RIDL count has
finished.
WRCV[1:0]
(Write ReCoVery cycle)
Write recovery cycle
After a write access has finished, the next access is
able to start after WRCV count has finished.
The number of access cycles is determined from the following formula.
Number of read access cycles = Address & data output (1) + ACS (0 to 3) + CSRD (0 to 3) + RWT (0 to 15) +RDCS
(0 to 3)
Minimum: 1 cycle; Maximum: 25 cycles
Number of write access cycles = Address & data output (1) + ACS (0 to 3) + CSWR (0 to 3) + WWT (0 to 15) +
WRCS (0 to 3)
Minimum: 1 cycle; Maximum: 25 cycles
The following conditions need to be met in order to correctly establish the protocol.
ASCY ≤ ACS + CSRD + RWT + RDCS and ASCY ≤ ACS + CSWR + WWT + WRCS
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Address/Data multiplexed bus timing parameters
This section shows the timing parameters that can be configured in the address/data multiplexed bus.
Figure 5-7 Address/Data Multiplexed Bus Timing Parameters
SY SCL K
ASCY
1
0
AS X
RIDL[1:0] or
WRCV[1:0]
3
0
ACS[1:0]
3
0
CSnX
(n=0,1,2,3)
CSRD[1:0]
0
RDCS[1:0]
RWT[3:0]
3 0
15
3
0
RDX
CSWR[1:0]
WWT[3:0]
3 0
15
0
WRCS[1:0]
3
0
WRnX (n=0,1)
0
Dxx
ADCY[1 :0 ]
3
*1
*2
data
address
H: Dxx is input
L: Dxx is output
*1 : During write access, Dxx outputs write data immediately after the address output cycle ends.
*2 : Dxx extends the number of cycles and valid value output specified by WRCS during write access.
Table 5-9 Address/Data Multiplexed Bus Timing Parameters
Parameter name
Function name
Description
ASCY(ASX CYcle)
ASX output extension
cycle count
"L" is output to ASX for (ASCY+1) cycles from
when the access starts.
ACS[1:0]
(A00 to A21 to CSnX delay
cycle)
A00 to A21 → CSnX
delay cycle count
Output of "L" to CSnX (n=0 to 3) starts after the
ACS count has finished from ASX output.
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Parameter name
Function name
Description
ADCY[1:0](ADdress CYcle)
Address output
extension cycle count
If ADCY ≥ ASCY
D16 to D31 output (ADCY+1) cycle address
information from when access starts. During writes,
write data is output after the count finishes until the
access finishes.
If ADCY < ASCY
The count value is changed from (ADCY+1) to
(ASCY+1).
There are no other differences.
The ADCY count operates independently of the
other counters. Furthermore, it does not affect the
start conditions of other counters. As a result, there
are some limits on setting the counter value in order
for the overall protocol to function correctly. See
the prohibited setting conditions outside of the
table.
CSRD[1:0]
(CSnX to RDX setup cycle)
CSnX → RDX
setup cycle
During read access, output of "L" to RDX begins
after the CSRD count finishes after "L" output to
CSnX begins.
RWT[3:0]
(Read access auto WaiT)
Read access
auto wait
During read access, the RDX output returns to "H"
after (RWT+1) count from when output of "L" to
RDX begins.
RDCS[1:0]
(RDX to CSnX hold cycle)
RDX → CSnX
hold cycle
During read access, the output of CSnX returns to
"H" after RDCS count from the cycle where the
output of RDX returns to "H".
CSWR[1:0]
(CSnX to WRnX setup cycle)
CSnX → WRnX
setup cycle
During write access, output of "L" to WRnX (n=0,
1) begins after the CSWR count finishes after "L"
output to CSnX begins.
WWT[3:0]
(Write access auto WaiT)
Write access
auto wait
During write access, the output to WRnX returns to
"H" after (WWT+1) count finishes.
WRCS[1:0]
(WRnX to CSnX hold cycle)
WRnX → CSnX
hold cycle
During write access, the output of CSnX returns to
"H" after WRCS count from the cycle where the
output of WRnX returns to "H".
RIDL[1:0]
(Read access IDLe cycle)
Read access
idle cycle
After a read access has finished, the next access is
able to start after RIDL count has finished.
WRCV[1:0]
(Write ReCoVery cycle)
Write recovery cycle
After a write access has finished, the next access is
able to start after WRCV count has finished.
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The number of access cycles is determined from the following formula.
Number of read access cycles = Address output (1) + ACS (0 to 3) + CSRD (0 to3) + Data output (1) + RWT (0 to 15)
+ RDCS (0 to 3)
Minimum: 2 cycles; Maximum: 26 cycles
Number of write access cycles = Address output (1) + ACS (0 to 3) + CSWR (0 to 3) + Data output (1) + WWT (0 to
15) + WRCS (0 to 3)
Minimum: 2 cycles; Maximum: 26 cycles
The following four conditions need to be met in order to correctly establish the protocol.
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
5.9.
RDY Pin Access Cycle Extension Function
This section shows the RDY pin access cycle extension function.
The read and write strobe cycles can be extended even after the auto wait cycles have finished by inputting "0" to the
RDY pin.
This function can be enabled by the RDY pin for access to the corresponding area when setting AWR: RDYE to "1".
Use this function by setting the auto wait cycles of the corresponding area to 2 or more.
After the auto wait cycle has finished, the read and write strobe cycles are extended while "0" is input to RDY. If "1"
is input to RDY after this, the read or write strobe cycle finishes in the next cycle.
RDY Signal Input Specifications
The input RDY signal adheres to the following specifications.
Input RDY=1 except when extending the auto wait cycles.
Begin inputting RDY=0 after checking that access to an area covered by auto wait cycle extension has started with
ASX="L" and CSnX="L".
Start inputting RDY=0 before the auto wait cycle ends. It is prohibited to input RDY=0 after the auto wait cycles
have ended.
Input RDY=1 after the required extension cycles have finished.
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Figure 5-8 RDY Timing Example
cycle no.
0
1
2
3
4
5
6
7
8
9
10
SYSCLK
ASX
Basic example when
auto wait cycles
set to 2 cycles
CSnX
(n=0,1,2,3)
RDX
WRnX
(n=0,1)
Auto wait cycle
RDY
Example of extending
wait cycles of basic
example by 3 cycles
using RDY
CSnX
(n=0,1,2,3)
RDX
WRnX
(n=0,1)
Auto wait cycle
Extension cycles by RDY
Note:
When interfacing an external bus at 3.3 V (at 5.0 V for other functions), use bus ready input by selecting RDY_1.
(For information on pin switching, see "CHAPTER: I/O PORTS.")
5.10. CS Setting Flow
This section explains the CS setting flow.
This section explains CS setting method.
Notes:
Perform the CS configuration during the initialization settings after reset, and do not change the settings thereafter.
In models with built-in ROM, perform changes and settings of CS area in the initial settings program located in
ROM.
In models without built-in ROM, because instruction fetch after reset is performed in the CS0 area, first transfer
the CS setting program to the built-in RAM and then branch to the program area in built-in RAM to configure the
CS area if the CS0 area is to be changed.
Operation is not guaranteed if the settings related to a CS area are changed while the CS area is being accessed.
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The flow for configuring CS is shown below.
Figure 5-9 CS Setting Flow
Set CS
Change the setting of CS0
or configure another CS area
in 0x00000000 to 0x7FFFFFFF
No
Yes
Disable CS0
(Write 0 to ASR0:CSEN)
Set ACR[i]
Set AWR[i]
Read the value of ASR[i]
Set ASR[i]
Enable CS[i]
Compare the setting value
of ASR[i] to the read value
No
Finish setting CS[i]
(not setting other CS[i])
Finished setting CS
Yes
Disabling CS0
In order to change CS0, CS0 first needs to be disabled. Write 0x0 to ASR0 as a word.
Setting ACR
The bus width, bus type, etc. of the CS area can be configured.
1.
2.
3.
1088
The data bus width of the configured CS area can be selected from 8 bits and 16 bits.
The address output type can be selected from normal output and shift output.
The bus type can be selected from address/data split bus and address/data multiplexed bus.
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Chapter 37: External Bus Interface
Write the above setting values to ACR as word units.
Setting AWR
The parameters that determine the output timing of the external bus signals and whether the RDY pin function is
enabled or disabled can be configured. Write the setting values to AWR as words.
Figure 5-10 Parameters that can be Configured in AWR
SYSCLK
ASCY
0 1
ASX
RIDL[1:0] or
WRCV[1:0]
3
0
ACS[ 1:0 ]
3
0
CSnX
(n=0,1,2,3)
CSRD[1:0]
RWT[3:0]
0
3 0
15
RDCS[1:0]
3
0
RDX
CSWR[1:0]
3 0
0
WWT[3:0]
15
WRnX
(n=0,1)
WRCS[1:0]
3
0
*1
A00 to A21
For address/
data split bus
Dxx
ADCY[1:0 ]
0
address
For address/data
multiplexed bus
*2
3
data
Dxx
: H: Dxx is input. L: Dxx is output.
*1: A00 to A21 and Dxx extend the number of cycles and valid value output specified by RDCS during read access
and by WRCS during write access.
*2: Dxx extends the number of cycles and valid value output specified by WRCS during write access.
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Table 5-10 List of Parameter
Parameter name
RWT[3:0]
WWT[3:0]
Description
Sets the auto wait cycle count during the read access cycle.
This is configured when you want to extend the read access cycle.
Sets the auto wait cycle count during the write access cycle.
This is configured when you want to extend the write access cycle.
Sets the idle cycle count after the read access.
RIDL[1:0]
RIDL is configured in order to prevent conflicts on the data bus between the
read data from a device with a long output off time and the data of the
subsequent access.
Sets the write recovery cycle count.
WRCV[1:0]
This is configured to control access to devices that have limits on the interval
when performing an access after a write access.
Sets the number of cycles after CSnX (n=0 to 3) is asserted until RDX is asserted.
CSRD[1:0]
This is configured if setup time is required for asserting CSnX when RDX is
asserted during read access.
Sets the number of cycles after RDX is negated until CSnX (n=0 to 3) is negated.
RDCS[1:0]
This is configured if hold time is required for the negation of CSnX after RDX
is negated during read access.
Sets the number of cycles after CSnX is asserted until WRnX (n=0, 1) is asserted.
CSWR[1:0]
This is configured if setup time is required for asserting CSnX when WRnX is
asserted during write access.
Sets the number of cycles after WRnX is negated until CSnX is negated.
WRCS[1:0]
ADCY[1:0]
ACS[1:0]
1090
This is configured if hold time is required for the negation of CSnX after
WRnX is negated during write access.
Sets the number of cycles to extend address output to the data bus while
address/data multiplexed bus is selected. Even if ADCY is set to "00", if ASCY
is set to "1" then the address output cycle is extended by 1 cycle. Set this to"00"
when the address/data split bus is selected.
Sets the number of delay cycles from outputting A00 to A21 and ASX to
outputting CSnX. This is used when the address for CSnX assert needs setup
time, or when CSnX edges are required when accessing the same chip select
area in sequence.
ASCY
Sets the number of ASX assert extensions cycles.
RDYE
Sets whether the wait insertion function by external RDY pin is enabled or
disabled.
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Chapter 37: External Bus Interface
Setting ASR
The following settings are made using ASR.
1. Configure the CS areas.
2. Select whether writes are enabled or disabled.
3. Select the byte ordering.
4. Enable the CS.
Write the above setting values to ASR as words.
The CS area settings are explained below.
1.
2.
Determine the size of the CS area and select the value of ASZ[3:0] from "4.1 CS Area Setting Registers:
ASR0 to ASR3 (Area Setting Register 0-3)".
Set the CS area start address. The starting address is configured by setting the upper bits of the address in
SADR. However, the starting address has the boundaries determined in advance depending on the size of the
area specified in the following table. Set the valid bits of SADR according to "4.1 CS Area Setting Registers:
ASR0 to ASR3 (Area Setting Register 0-3)". Set invalid SADR bits to "0".
The size of the CS area and the setting of ASZ and SADR
The size of the CS area
ASZ[3:0]
The valid SADR bit
64KB
128KB
256KB
512KB
1MB
2MB
4MB
8MB
16MB
32MB
64MB
128MB
256MB
512MB
1GB
2GB(initial value of ASR0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SADR[31:16]
SADR[31:17]
SADR[31:18]
SADR[31:19]
SADR[31:20]
SADR[31:21]
SADR[31:22]
SADR[31:23]
SADR[31:24]
SADR[31:25]
SADR[31:26]
SADR[31:27]
SADR[31:28]
SADR[31:29]
SADR[31:30]
SADR[31]
Note:
Arrange each of the CS areas such that they do not overlap. Operation is not guaranteed if the CS areas are
overlapping.
An example of the values set in SADR and ASZ and the actually allocated CS areas is shown below.
Setting example
CS0 settings
ASR0:ASZ[3:0]=0010
ASR0:SADR[31:16]=0x000C
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→ 0x000C0000 to 0x000FFFFF becomes the CS0 area.
CS1 settings
ASR1:ASZ[3:0]=0000
ASR1:SADR[31:16]=0x0006
→ 0x00060000 to 0x0006FFFF becomes the CS1 area.
CS2 settings
To allocate the space from 0x00110000 to 1MByte:
Set ASZ[3:0]=0100 to allocate a space of 1MByte. At that time, the SADR enable bit is [31:20]. SADR[19:16] is
not the target of the comparison with the address. Therefore, the starting address of the CS2 area is 0x00100000
rather than 0x00110000.
ASR2:ASZ[3:0]=0100
ASR2:SADR[31:16]=0x0010
→ 0x00100000 to 0x001FFFFF becomes the CS2 area.
CS3 settings
ASR3:ASZ[3:0]=0010
ASR3:SADR[31:16]=0x0FFC
→ 0x0FFC0000 to 0x0FFFFFFF becomes the CS3 area.
Figure 5-11 Setting Example
Setting example
Initial state
0x00000000
0x00000000
0x00060000
0x00070000
CS1 area
64Kbyte
CS0 area
256Kbyte
CS2 area
1Mbyte
CS3 area
256Kbyte
0x000C0000
0x00100000
CS0 area
0x00200000
0x0FFC0000
0x10000000
0x7FFFFFFF
0x7FFFFFFF
0xFFFFFFFF
0xFFFFFFFF
Reading and comparing ASR
After configuring the required ACR, AWR, and ASR settings for a CS, read the ASR which was configured last and
compare to the set value in order to ensure that the CS settings will apply to subsequent accesses.
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Chapter 37: External Bus Interface
CS settings and update sample program
This section shows a CS configuration sample program that configures CS1.
Figure 5-12 CS1 Settings Sample Program
ACR1 Setting Example
ASR1 Setting Example
Shows the setting values for the following table.
Data bus width
Address output type
Bus type
16bit
Normal
Address/data multiplexed bus
• CS1 area size : 64Kbyte
• CS1 area address: 0x0040_0000 to 0x0040_FFFF
• Write enable
• Big endian
• CS1 valid
ASR1 setting value : 0x00400005
Bits other than the above setting bits are reserved and are set to 0.
: value : 0x40
ACR1 setting
AWR1 Setting Example
Shows the setting values for the following table.
3 cycles
RW T
4 cycles
WWT
2 cycles
RID L
3 cycles
WRC V
1 cycle
CSR D
1 cycle
RDC S
2 cycles
CSW R
2 cycles
WRC S
Address/data multiplexed bus setting
ADC Y
0 cycle
AC S
0 cycle
ASC Y
RDY E
Invalid
Program Example
_disable_CS0
ld
#_ASR0, r0
ldi
0x0, r1
st
r1, @r0
_set_ACR1
ld
#_ACR1, r0
ld
#0x40, r1
st
r1, @r0
_set_AWR1
ld
# _ AWR 1 , r0
ld
#0x034b5a00 r1
st
r1, @r0
_set_ASR1
ld
#_ASR1, r0
ld
#0x00400005 r1
st
r1, @r0
ld
@r0, r2
cmp r1, r2
//# _ASR0 is the ASR0 address value
// #_ACR1 is the ACR1 address value
// Set ACR1 to 0x40
// #_AWR1 is the AWR1 address value
// Set AWR1 to 0x034b5a00
// #_ASR1 is the ASR1 address value
// Set ASR0 to 0x00400005
// Check the setting value of ASR1
Bits other than the above setting bits are reserved and are set to 0.
AWR1 setting value : 0x034b5a00
5.11. Example of Connecting to Asynchronous Memory
This section shows an example of connecting to asynchronous memory.
This section shows an example of connecting external bus pins to asynchronous memory.
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Chapter 37: External Bus Interface
Figure 5-13 Example 1 of Connection to SRAM (8-bit SRAM x 2)
LSI
A17 to A00
CS3 X
CS_X
WR0 X
WE_X
RD X
OE_X
IO7 to IO0
D31 to D24
256K 8-bit SRAM
A18 to A01
CS_X
WE_X
WR1 X
OE_X
IO7 to IO0
D23 to D16
256K 8-bit SRAM
A17 to A00
WE_X : Write enable
OE_X : Output enable
Figure 5-14 Example 2 of Connection to SRAM (8-bit SRAM x 1)
LSI
CS3 X
WR0 X
RD X
D31 to D24
A17 to A00
CS_ X
WE _X1, WE_X0
OE_X
IO7 to IO0
256K 8-bit SRAM
A17 to A00
WE_X : Write enable
OE_X : Output enable
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Chapter 37: External Bus Interface
5.12. Example of Connection to Little Endian Device
This section shows an example of connection to little endian device.
This section shows the method of connecting the data bus and byte enable signals to a little endian device.
Figure 5-15 16-bit Bus Width
LSI
External LSI (little endian)
A17 to A00
CS3X
WR0X, WR1X
RDX
A17 to A00
CS_X
WE_X1, We_X0
OE_X
D31 to D24
D15 to D8
D23 to D16
D7 to D0
WE_X : Write enable
OE_X : Output enable
Figure 5-16 8-bit Bus Width
LSI
External LSI (little endian)
A17 to A00
A17 to A00
CS3 X
CS_ X
WR0 X
WE _X
RDX
D31 to D24
OE_X
D7 to D0
WE_X : Write enable
OE_X : Output enable
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Chapter 38: Bus Performance Counters
This chapter explains the bus performance counters.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FR81S10_BPC-1v1-91528-2-E
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Chapter 38: Bus Performance Counters
1. Overview
This section explains the overview of the bus performance counters.
This series has a built-in bus performance counters (BPC) for measuring the performance of the on-chip bus. BPC
measures the breakdown of traffic on the on-chip bus, and provides information for strategies to improve bus
performance. Because the counters do not count while the on-chip bus is idle, use the timers in the system at the same
time to measure the time.
2. Features
This section explains the features of the bus performance counters.
Counter configuration
Count clocks :
Clock for the on-chip bus
Counter bit length :
32-bit × 3 channels (BPC-A, BPC-B, BPC-C)
Overflow detection :
None
Counter value rewrite :
Allowed
Main functions
The following operations can be selected for counting in each channel
Number of read accesses in the on-chip bus
Number of write accesses in the on-chip bus
Number of wait cycles in the on-chip bus
One of the following operations can be selected for counting in each channel
Specific bus master (CPU, DMAC, other, or all)
Specific target (ICH, MCH, other, or all)
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Chapter 38: Bus Performance Counters
3. Configuration
This section explains the configuration of the bus performance counters.
Figure 3-1 Block Diagram
8
BPCCRA
On-Chip Bus
Monitor
Event selection
Count
32
BPCTRA
BPC-A
BPC-B
BPC-C
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Chapter 38: Bus Performance Counters
4. Registers
This section explains the registers of the bus performance counters.
Table 4-1 Registers Map
Registers
Address
Register function
+0
+1
+2
+3
BPC-A control register
BPCCRA BPCCRB BPCCRC Reserved BPC-B control register
BPC-C control register
0x0710
0x0714
BPCTRA
BPC-A count register
0x0718
BPCTRB
BPC-B count register
0x071C
BPCTRC
BPC-C count register
4.1.
BPC-A Control Register : BPCCRA (Bus Performance
Counter Control Register A)
The bit configuration of the BPC-A control register is shown below.
This register configures the measurement target of bus performance counter A (BPC-A).
The bus performance counters have three channels, A, B, and C, and there is a control register for each of these
counters. Each field of the control register is common to each channel.
BPCCRA : Address 0710H (Access: Byte)
bit7
bit6
bit5
FUNC[1:0]
Initial value
Attribute
bit4
bit3
bit2
bit1
MST[3:0]
bit0
SLV[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, bit6] FUNC[1:0] (FUNCtion selection) : Measurement event selection
These bits select the event measured by BPC.
FUNC[1:0]
Event
00
BPC-A operation stopped (initial value)
01
Number of read accesses
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FUNC[1:0]
Event
10
Number of write accesses
11
Number of wait cycles
[bit5 to bit2] MST[3:0] (bus MaSTer select) : Bus master selection
These bits select the bus master for the events which are measured by BPC.
MST[3:0]
Bus master
0000
All bus masters (initial value)
0001
CPU (XBS)
0010
DMAC
0011
Reserved
0100
Reserved
Except for the
above
Reserved
[bit1, bit0] SLV[1:0] (SLaVe select) : Slave selection
These bits select the slave for the events which are measured by BPC.
SLV
4.2.
Slave
00
All slaves (initial value)
01
MCH (registers, external bus)
10
ICH (peripherals)
11
Slaves other than MCH/ICH
BPC-B Control Register : BPCCRB (Bus Performance
Counter Control Register B)
The bit configuration of the BPC-B control register is shown below.
This register configures the measurement target of bus performance counter B (BPC-B).
The function of each bit is the same as BPCCRA.
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Chapter 38: Bus Performance Counters
BPCCRB : Address 0711H (Access: Byte)
bit7
bit6
bit5
bit4
FUNC[1:0]
Initial value
Attribute
4.3.
bit3
bit2
bit1
MST[3:0]
bit0
SLV[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BPC-C Control Register : BPCCRC (Bus Performance
Counter Control Register C)
The bit configuration of the BPC-C control register is shown below.
This register configures the measurement target of bus performance counter C (BPC-C).
The function of each bit is the same as BPCCRA.
BPCCRC : Address 0712H (Access: Byte)
bit7
bit6
bit5
bit4
FUNC[1:0]
Initial value
Attribute
4.4.
bit3
bit2
bit1
MST[3:0]
bit0
SLV[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BPC-A Count Register : BPCTRA (Bus Performance
CounTer Register A)
The bit configuration of the BPC-A count register is shown below.
This register is a 32-bit length count register that counts the events configured by BPCCRA.
BPCTRA : Address 0714H (Access: Word)
bit31
bit30
•
•
•
bit3
bit2
bit1
bit0
BPCTRA[31:0]
Initial value
Attribute
0
0
•
•
•
0
0
0
0
R/W
R/W
•
•
•
R/W
R/W
R/W
R/W
[bit31 to bit0] BPCTRA[31:0] (Bus Performance CounTer Register A) : BPC-A count
If bit7, bit6: FUNC of the BPCCRA are set to a value other than "00", the count of the target events begins. This
register is readable and writable, and can only be accessed using 32-bit access. Because the counter is not initialized
when the count is started, set the initial value when starting a new count. Furthermore, because there is no overflow
control, if the counter overflows it returns to zero and continues counting.
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Chapter 38: Bus Performance Counters
4.5.
BPC-B Count Register : BPCTRB (Bus Performance
CounTer Register B)
The bit configuration of the BPC-B count register is shown below.
This register is a 32-bit length count register that counts the events configured by BPCCRB. The usage is the same as
BPCTRA.
BPCTRB : Address 0718H (Access: Word)
bit31
bit30
•
•
•
bit3
bit2
bit1
bit0
BPCTRB[31:0]
Initial value
Attribute
4.6.
0
0
•
•
•
0
0
0
0
R/W
R/W
•
•
•
R/W
R/W
R/W
R/W
BPC-C Count Register : BPCTRC (Bus Performance
CounTer Register C)
The bit configuration of the BPC-C count register is shown below.
This register is a 32-bit length count register that counts the events configured by BPCCRC. The usage is the same as
BPCTRA.
BPCTRC : Address 071CH (Access: Word)
bit31
bit30
•
•
•
bit3
bit2
bit1
bit0
BPCTRC[31:0]
Initial value
Attribute
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0
0
•
•
•
0
0
0
0
R/W
R/W
•
•
•
R/W
R/W
R/W
R/W
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Chapter 38: Bus Performance Counters
5. Operation
This section explains the operations.
5.1 Setting
5.2 Starting and Stopping
5.3 Operation
5.4 Measurement and Result Processing
5.1.
Setting
This section explains the setting.
Before starting each of the BPC channels, write "0x00000000" to BPCTRA, BPCTRB, and BPCTRC, and initialize
each counter. Initialize each counter in the same way when changing the measurement target. Because the counter
value is undefined after reset, always write the counter value before enabling operation.
When starting each BPC channel, configure the measurement target of each counter using BPCCRA, BPCCRB, and
BPCCRC.
The events monitored by the settings of the bus performance counter A (B, C) control register (BPCCRA (B, C)) are
as follows. Operation is not guaranteed for any combination that does not exist in the following table. Moreover, it
does not count in emulator mode.
Table 5-1 List of BPC Settings
FUNC[1:0]
MST[3:0]
0000
01
0001
0100
SLV[1:0]
Target event
00
Read access from XBS, DMAC
01
MCH read from XBS, DMAC
10
ICH read from XBS, DMAC
11
Other than MCH/ICH read from XBS, DMAC
00
Read access from XBS
01
MCH read from XBS
10
ICH read from XBS
11
Other than MCH/ICH read from XBS
00
Read access from DMAC
01
MCH read from DMAC
10
ICH read from DMAC
11
Other than MCH/ICH read from DMAC
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Chapter 38: Bus Performance Counters
FUNC[1:0]
MST[3:0]
0000
10
0001
0100
0000
11
0001
0100
5.2.
SLV[1:0]
Target event
00
Write access from XBS, DMAC
01
MCH write from XBS, DMAC
10
ICH write from XBS, DMAC
11
Other than MCH/ICH write from XBS, DMAC
00
Write access from XBS
01
MCH write from XBS
10
ICH write from XBS
11
Other than MCH/ICH write from XBS
00
Write access from DMAC
01
MCH write from DMAC
10
ICH write from DMAC
11
Other than MCH/ICH write from DMAC
00
Wait cycle of XBS, DMAC
01
MCH wait from XBS, DMAC
10
ICH wait from XBS, DMAC
11
Other than MCH/ICH wait from XBS, DMAC
00
Wait access from XBS
01
MCH wait from XBS
10
ICH wait from XBS
11
Other than MCH/ICH wait from XBS
00
Wait access from DMAC
01
MCH wait from DMAC
10
ICH wait from DMAC
11
Other than MCH/ICH wait from DMAC
Starting and Stopping
This section explains the starting and stopping.
The target event count is started by setting the FUNC[1:0] bits of the bus performance counter A control register
(BPCCRA) to a value other than "00". However, at this time the count starts from the current value without
initializing the bus performance counter A register (BPCTRA). The operation of the bus performance counter stops
when BPCCRA:FUNC[1:0] is set to "00".
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Chapter 38: Bus Performance Counters
5.3.
Operation
This section explains the operation.
Once operation has been enabled by setting the control register, each of the measurement target operations continues
to be counted while the on-chip bus is operating. However, the count is paused in the circumstances shown below.
While in emulator mode
The count operation when each of the low-power consumption modes is set is as follows.
CPU sleep mode
Each measurement target operation is counted.
Bus sleep mode
Only counted during DMA transfers that operate the on-chip bus. During other periods, counting is not performed
because the measurement target operations do not occur.
Standby mode (watch mode / stop mode)
Counting is not performed because the measurement target operations do not occur.
The control register is initialized when a reset occurs. Counting is not performed immediately after a reset occurs.
5.4.
Measurement and Result Processing
This section explains the measurement and result processing.
The use of BPC is anticipated for when ICE is connected or when using a monitor debugger. The configuring of
measurements and reading of results are performed in debug mode while the user program execution is halted.
Examples of measurements are as follows.
Measure between two points in a user program
Measure a reference time base
These are explained below.
Measuring between two points in a user program
During this measurement, the measurement starting point and measurement ending point in the user program are
configured as follows.
Measurement starting point: Starting point of the user program execution
Measurement ending point: Breakpoint in the user program
The measurement sequence is as follows.
1. Configure the measurement and initialize the counter in debug mode
2. Start executing the user program from the measurement starting point
3. Break on the measurement ending point and stop executing the user program
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4. Switch to debug mode and read the measurement results
Measuring the reference time base
During this measurement, switch to debug mode at each reference time, read out the measurement results and
initialize the counters.
The following two methods are available for switching to debug mode at each reference time.
Assert a tool break from the ICE at each reference time to switch to debug mode (when connected to ICE)
Set the interval time of a built-in timer to the reference time, and execute the INTE instruction in the timer
interrupt routine to switch to debug mode
The measurement sequence is as follows.
1. Configure the measurement and initialize the counter in debug mode
2. Begin executing the measurement target user program
3. Tool break by reference time, or execute the INTE instruction by built-in timer interrupt routine
4. Switch to debug mode and read the measurement results
5. Initialize the measurement counter
6. Repeat steps 2 to 5
Analyze the measurement results using a debugger host program, such as Softune Workbench. Visualize the analysis
results by displaying them in a graph so that they can be understood intuitively (pie graph, bar graph, line graph, etc.),
and provide information that is beneficial for user program tuning (bus performance analysis function). The following
is an analysis example.
Analysis example:
1. Bus master access proportion
Ex. Proportion of DMAC access vs. CPU access, specific bus master access that occupies the total access, etc.
2. Occurred event proportion
Ex. Proportion of write access vs. read access, proportion of total cycles made up of wait cycles, etc.
3. Target accessed proportion
Ex. Proportion of MCH vs. ICH, proportion of total accesses made up of accesses to a specific target, etc.
4. Proportion of specific accesses from a specific bus master to a specific target
Ex. Proportion of total access made up of read accesses from CPU to MCH, etc.
5. Proportion of wait cycles occurring in specific target
6. Ex. Proportion of total cycles made up of wait cycles during MCH access
7. Analyze operation of each bus between two specific points in a program
8. Ex. Proportion of total cycles between two specific points in the program consisting of read, write, wait cycles,
etc.
9. Analyze operation of each bus during progress of each specific time
Ex. Time course of proportion of all accesses consisting of accesses to specific bus masters and specific targets,
etc.
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Chapter 39: CRC
This chapter explains the CRC.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FS15-2v1-91528-2-E
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Chapter 39: CRC
1. Overview
This section explains the overview of the CRC.
This module calculates CRC values.
CRC (Cyclic Redundancy Check) is a kind of error detection methods. CRC codes are remainders left when input
data strings, regarded as high-degree polynomials, are divided by predefined generator polynomials. Normally, a CRC
code is attached at the end of a data string, and received data is regarded as correct if the data leaves no remainder
when divided by the same generator polynomial.
2. Features
This section explains features of the CRC.
This module calculates CCITT CRC16 and IEEE-802.3 CRC32. This module cannot calculate CRC values based on
other generator polynomials because the generator polynomials of this module are fixed for the values of CCITT
CRC16 and IEEE-802.3 CRC32.
CCITT CRC16 generator polynomials : 0x1021
IEEE-802.3 CRC32 generator polynomials : 0x04C11DB7
3. Configuration
This section explains the configuration of the CRC.
Figure 3-1 Block Diagram
Generator Polynomial
CRC Calculation
[CRC16 ] 0x1021
[CRC32 ] 0x04C11DB7
32-bit
Peripheral bus
Bus I/F
CRCCR
CRCINIT
CRCIN
CRCR
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Chapter 39: CRC
4. Registers
This section explains registers of the CRC.
Table 4-1 Registers Map
Registers
Address
Register function
+0
0x1130
+1
+2
+3
Reserved
CRCCR
CRC control register
0x1134
CRCINIT
0x1138
CRCIN
CRC input data register
0x113C
CRCR
CRC register
4.1.
CRC initial value register
CRC Control Register : CRCCR (CRC Control
Register)
The bit configuration of the CRC control register is shown below.
This register controls the CRC calculation.
CRCCR : Address 1133H (Access: Byte, Half-word, Word)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
FXOR
CRCLSF
CRCLTE
LSBFST
LTLEND
CRC32
INIT
0
0
0
0
0
0
0
0
R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
R0,W
[bit7] Reserved
This bit must always be written to "0".
[bit6] FXOR (Final XOR) : Final XOR Control bit
CRC results are output as the XOR value and XOR. The XOR values are ALL.H. and bit strings are inverted when
FXOR = 1 is true. This process is made in the latter part of the CRC register, and the result is reflected in the CRC
result readout value immediately after this bit setting.
[bit5] CRCLSF (CRC result LSb First) : CRC result bit order setting bit
This bit sets bit orders for CRC results. Changes the bit order in a byte. When this bit is "0", MSB First is applied, and
when this bit is "1", LSB First is applied. This process is made in the latter part of the CRC register, and the result is
reflected in the CRC result readout value immediately after this bit setting.
[bit4] CRCLTE (CRC result LiTtle-Endian) : CRC result byte order setting bit
This bit sets byte orders for CRC results. Changes the byte order in a word. When this bit is "0", big endian is applied,
and when this bit is "1", little endian is applied. This process is made in the latter part of the CRC register, and the
result is reflected in the CRC result readout value immediately after this bit setting. When this bit is set to 1 for
CRC16, the result is output in 31 to 16 bits.
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[bit3] LSBFST (LSB FirST) : Bit order setting bit
This bit sets bit orders. Specifies the first bit of a byte (8 bits). When this bit is "0", MSB First is applied, and when
this bit is "1", LSB First is applied. Four patterns of process order can be specified by combining the LTLEND
setting.
[bit2] LTLEND (LitTtLe-ENDian) : Byte order setting bit
This bit sets byte orders. Specifies byte orders in a writing width. When this bit is "0", big endian is applied, and
when this bit is "1", little endian is applied.
[bit1] CRC32 (CRC32) : CRC mode selecting bit
This bit selects a mode for CRC16 and CRC32. When CRC32=1 is true, the arithmetic operation mode of CRC32 is
applied.
[bit0] INIT (INITialize) : Initialization bit
Initialization bit. When "1" is written to this bit, software performs the initialization. This bit does not have a value
and "0" is always returned at readout. In initialization, hardware loads the value of the initial value register to the
CRC register. Initialization needs to be performed once at the beginning of the CRC calculation.
4.2.
CRC Initial Value Register : CRCINIT (CRC Initial value
register)
The bit configuration of the CRC initial value register is shown below.
This register sets the initial value for the CRC calculation.
CRCINIT : Address 1134H (Access: Byte, Half-word, Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
D[31:0]
Initial value
Attribute
1
1
•
•
•
1
1
1
R/W
R/W
•
•
•
R/W
R/W
R/W
[bit31 to bit0] D (Data) : Initialization Value bits
These bits store the initial value for the CRC calculation. Software writes the initial value for the CRC calculation.
(0xFFFF_FFFF is applied after reset.) For CRC16, D15 to D0 are used and D31 to D16 are ignored.
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Chapter 39: CRC
4.3.
CRC Input Data Register : CRCIN (CRC INput data register)
The bit configuration of the CRC input data register is shown below.
This register sets the input data for the CRC calculation.
CRCIN : Address 1138H (Access: Byte, Half-word, Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
D[31:0]
Initial value
Attribute
0
0
•
•
•
0
0
0
R/W
R/W
•
•
•
R/W
R/W
R/W
[bit31 to bit0] D (Data) : Input Data bits
These bits set the input data for the CRC calculation. Software writes the input data for the CRC calculation. The bit
width of 8, 16 or 32 is used. These bits width can be mixed. Bytes or half words can be written into any position. The
address position can be +0, +1, +2 or +3 for byte writing and +0 or +2 for half word writing.
4.4.
CRC Register : CRCR (CRC Register)
The bit configuration of the CRC register is shown below.
This register outputs the result for the CRC calculation.
CRCR : Address 113CH (Access: Byte, Half-word, Word)
bit31
bit30
•
•
•
bit2
bit1
bit0
D[31:0]
Initial value
Attribute
1
1
•
•
•
1
1
1
R,WX
R,WX
•
•
•
R,WX
R,WX
R,WX
[bit31 to bit0] D (Data) : CRC bits
These bits output the result for the CRC calculation. When software writes "1" to the initialization bit (CRCCR. INIT),
the value of the initial value register (CRCINIT) is loaded to this register. When software writes the input data for the
CRC calculation to the Input Data register (CRCIN), hardware immediately sets the CRC calculation result to this
register. When all input data has been written, this register holds the final CRC code. When CRC16 is used, the result
is output in D15 to D0 for big-endian (CRCLTE=0) byte order and in D31 to D16 for little-endian (CRCLTE=1) byte
order.
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Chapter 39: CRC
5. Operation
This section explains the CRC.
5.1 CRC Definition
5.2 Reset Operation
5.3 Initialization
5.4 Byte and Bit Orders
5.5 CRC Calculation Sequence
5.6 Examples
5.1.
CRC Definition
The CRC definition is shown below.
CCITT CRC16 Standard
Generator polynomials
0x1021
Initial value
0xFFFF
Final XOR value
0x0000
Bit order
MSB First
Output bit order
MSB First
(Any byte order can be set for input and output)
(CRCCR.CRC32=0)
(CRCCR.FXOR=0)
(CRCCR.LSBFST=0)
(CRCCR.CRCLSF=0)
IEEE-802.3 CRC32 Ethernet Standard
Generator polynomials
0x04C11DB7
Initial value
0xFFFF_FFFF
Final XOR value
0xFFFF_FFFF
Bit order
LSB First
Output bit order
LSB First
(Any byte order can be set for input and output)
5.2.
(CRCCR.CRC32=1)
(CRCCR.FXOR=1)
(CRCCR.LSBFST=1)
(CRCCR.CRCLSF=1)
Reset Operation
The reset operation of the CRC is shown below.
To reset, set 0xFFFF_FFFF to the initial value register (CRCINIT) and CRC register (CRCR). Others are cleared to
"0".
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Chapter 39: CRC
5.3.
Initialization
The initialization of the CRC is shown below.
In initialization by CRCCR.INIT, the value of the initial value register is loaded to the CRC register (CRCR).
5.4.
Byte and Bit Orders
The byte and bit orders of the CRC are shown below.
This section explains the byte and bit orders using examples. Inputs the following one word to the CRC calculator.
133.82.171.1 = 10000101 01010010 10101011 00000001
When the byte order is big endian (CRCCR.LTLEND=0), the transmission sequence in bytes is:
10000101
01010010
10101011
00000001
(First)
(Second)
(Third)
(Fourth)
When the bit order is LSB First (CRCCR.LSBFST=1), the transmission sequence in bits is:
10100001
01001010
11010101
(First)
10000000
(Last)
Notes:
When CRCCR.CRCLTE=1 is true, the byte order for the CRC result is changed in 32-bit width both for CRC16
and CRC32.
Note that output position for CRC16 is bit31 to bit16.
5.5.
CRC Calculation Sequence
The CRC calculation sequence is shown below.
The sequence for the CRC calculation is shown below. In the following explanation, the initial value register
(CRCINIT) setting, CRC16/32 selection (CRCCR.CRC32), byte order and bit order settings (CRCCR.LTLEND,
CRCCR.LSBFST) have been done. (When the initial value of ALL "H" is acceptable, the setting for the initial value
register (CRCINIT) can be omitted.)
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Chapter 39: CRC
Figure 5-1 CRC Calculation Sequence
sd CRC
CRC calculation ()
Initialization ()
Start ()
Data write ()
Data write ()
Data write ()
CRC read ()
To initialize, write "1" to the initialization bit (CRCCR.INIT). The value of the initial value register will be loaded
to the CRC register (CRCR).
Input data is written to the Input Data register (CRCIN). The writing operation starts the CRC calculation. Input
data can be written continuously. In addition, there can be different bit widths of writing in a sequence.
The CRC code is obtained with the readout of the CRC register (CRCR).
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Chapter 39: CRC
5.6.
Examples
The examples are shown below.
5.6.1 Example 1 CRC16, Fixed Byte Input
5.6.2 Example 2 CRC16, Mixture of Different Input Bit Widths
5.6.3 Example 3 CRC32, Byte Order, Big-endian
5.6.4 Example 4 CRC32, Byte Order, Little-endian
5.6.1.
Example 1 CRC16, Fixed Byte Input
Example 1 CRC16 and fixed byte input are shown below.
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Chapter 39: CRC
Figure 5-2 Example 1
//****************************************
// CRC16 (CRC ITU-T)
// polynomial: 0x1021
// initial value: 0xFFFF
// CRCCR.CRC32: 0 // CRC16
// CRCCR.LTLEND: 0 // big endian
// CRCCR.LSBFST: 0 // MSB First
// CRCCR.CRCLTE: 0 // CRC big endian
// CRCCR.CRCLSF: 0 // CRC MSB First
// CRCCR.FXOR: 0 // CRC Final XOR off
//****************************************
//
// Example 1-1 (Byte-unit writing)
//
(The following is assumed)
B_WRITE -- Byte writing
H_WRITE -- Half-word writing
W_WRITE -- Word writing
B_READ -- Byte reading
H_READ -- Half-word reading
W_READ -- Word reading
CRCCR
CRCINIT
CRCIN
CRCR
-----
Control register address
Initial value register address
Input data register address
Current CRC register address
// Initialization
B_WRITE (CRCCR, 0x01);
// data
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
write "123456789"
(CRCIN, 0x31);
(CRCIN, 0x32);
(CRCIN, 0x33);
(CRCIN, 0x34);
(CRCIN, 0x35);
(CRCIN, 0x36);
(CRCIN, 0x37);
(CRCIN, 0x38);
(CRCIN, 0x39);
Image of input order
into CRC calculator
MSB
LSB
3
1
// read result
H_READ (CRCR+2, data);
3
2
// check result
assert (data == 0x29B1);
3
3
3
9
//
// Example 1-2 (CRC check)
//
// Initialization
B_WRITE (CRCCR, 0x01);
// data
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
B_WRITE
write "123456789" + CRC
(CRCIN, 0x31);
(CRCIN, 0x32);
(CRCIN, 0x33);
(CRCIN, 0x34);
(CRCIN, 0x35);
(CRCIN, 0x36);
(CRCIN, 0x37);
(CRCIN, 0x38);
(CRCIN, 0x39);
(CRCIN, 0x29); //
(1) When arbitration lost is detected in the first byte
(2) When NACK received except for stop condition output setting (write "0" to MSS bit in
master operation)
(3) When WSEL is "0" and arbitration lost is detected in the second byte or later
(4) In the first byte, no reserved address is detected in the receiving direction in master or
slave mode (IBSR:TRX=0) and there are reception FIFO data at reception FIFO enable
state
< When DMA mode is disabled (SSR:DMA=0) >
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Bit name
Function
(1) When DMA mode is disabled (SSR:DMA=0), in the first byte, no reserved address is
bit0 INT:
detected and the SSR:TDRE bit is "1" in the transmission direction in master or slave
Interrupt flag
mode (IBSR:TRX=1)
bit
(2) When DMA mode is disabled (SSR:DMA=0), the SSR:TDRE bit is "1" when reception
FIFO is disabled without detecting the reserved address in the first byte in the receiving
direction in master or slave mode (IBSR:TRX=0)
(3) When DMA mode is disabled (SSR:DMA=0), WSEL is "0" and the SSR:TDRE bit is
"1" in the second byte or later in master operation
(4) When DMA mode is disabled (SSR:DMA=0), WSEL is "0" and the SSR:TDRE bit is
"1" in the second byte or later in slave transmission
(5) When DMA mode is disabled (SSR:DMA=0), WSEL is "0" and reception FIFO is
disabled in slave reception. However, for slave reception at the first byte where a
reserved address is detected, an interrupt will not occur at the 9th bit.
(6) When DMA mode is disabled (SSR:DMA=0), reception FIFO is enabled, for slave
reception, when FIFO is Full
< When DMA mode is enabled (SSR:DMA=1) >
(1) When DMA mode is enabled (SSR:DMA=1), in the first byte, no reserved address is
detected and the SSR:TDRE bit is "1" in the transmission direction in slave mode
(IBSR:TRX=1)
(2) When DMA mode is enabled (SSR:DMA=1), the SSR:TDRE bit is "1" when reception
FIFO is disabled without detecting the reserved address in the first byte in the receiving
direction in slave mode (IBSR:TRX=0).
(3) When DMA mode is enabled (SSR:DMA=1), WSEL is "0" and you write "1" in the INT
bit when the SSR:TBI bit is "1" in the second byte or later in master operation
(1) Bus error detected
INT bit reset conditions:
(1) write "0" to INT bit
(2) INT bit is "1", write "0" to MSS bit when ACT bit is "1"
(3) INT bit is "1", write "1" to SCC bit when ACT bit is "1"
When DMA mode is disabled (SSR:DMA=0), writing "1" to this bit will not be effective.
Notes:
When the DMA mode is permitted (SSR:DMA=1), writes "1" in the INT bit and the
master mode is operating when the SSR:TBI bit is "1" in the second byte or later, status
interrupt (SIRQ="1") is not generated.
When you issue the repeat start condition when the DMA mode is permitted
(SSR:DMA=1), the SSR:TBI bit is "1" and the IBCR:INT bit is "0", follow the steps
below.
1. Write "1" to IBCR:INT bit.
2. Make sure that "1" has been set to the IBCR:INT bit.
3. Write a slave address to the TDR.
4. Set "1" to the IBCR:SCC bit.
When "0" is written in the INT flag when the INT flag is set in "1", the waiting of the I2C
bus is released.
When the ISMK:EN bit is "0", the SSR:RDRF bit and the INT bit might be "1"
depending on the reception timings. In this case, read received data and clear the INT bit.
For read-modify-write instructions, "1" will be read.
When reception FIFO is enabled, even if reception FIFO is full on the master reception
operation, "1" will not be set to the INT bit.
Write "1" to this bit when issuing the start conditions (IBCR:MSS=1).
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Chapter 41: Multi-Function Serial Interface
4.5.2.
Serial Status Register: SSR
This section explains the bit structure of the serial status register.
Serial status register (SSR) checks for the transmission/reception states.
SSRn(3 to 8, 11 to 19) : Address Base addr + 02H (Access: Byte, Half-word, Word)
7
REC
0
R0,W
6
TSET
0
R0,W
5
DMA
0
R/W
Bit name
4
TBIE
0
R/W
3
ORE
0
R,WX
2
RDRF
0
R,WX
1
TDRE
1
R,WX
0
bit
TBI
1
Initial value
R,WX Attribute
Function
bit7 REC:
Reception error flag clear
bit
This bit clears the ORE bit of serial status register (SSR)
Writing "1" clears the ORE bit.
Writing "0" does not affect anything.
A read always results in "0".
bit6 TSET:
This bit sets the TDRE bit in serial status register (SSR)
Transmit buffer empty flag When writing "1", the TBI bit is set when the TDRE bit and DMA mode
set bit
are enabled (DMA="1").
Writing "0" does not affect anything.
A read always results in "0".
Note:
Write "1" in this bit when the IBCR:INT bit is "1".
bit5 DMA:
This bit enables/disables the DMA mode.
DMA mode enable bit
When this bit is set to "1", it becomes an interrupt condition
corresponding to the DMA Transfer.
When this bit is set to "0", it becomes an interrupt condition
corresponding to the case without the DMA Transfer.
See "Table 8-1 I2C Interface Interrupt Control Bits and Interrupt Factors"
for details.
"0": DMA mode is disabled
"1": DMA mode is enabled
Note:
When ISMK:EN=0 only, this bit can be changed.
bit4 TBIE:
This bit enables/disables transmission bus idle interrupt request output to
Transmission bus idle
the CPU.
interrupt enabled bit (Only The transmission bus idle interrupt request will be output when DMA
the DMA mode enabled is
mode is enabled (DMA="1") and both TBIE bit and TBI bit are "1".
effective.)
When DMA mode is disabled (DMA="0"), this bit becomes "0" and any
writing operation will be ignored and "0" will be retained.
"0": Transmission bus idle interrupt request is disabled
"1": Transmission bus idle interrupt request is enabled
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Bit name
bit3 ORE:
Overrun error flag bit
1254
Function
"0" Read: No overrun error
"1" Read: There is an overrun error
If an overrun error occurs while a reception is in progress, this bit will be
set to "1". To clear this bit, write "1" to the REC bit of the serial status
register (SSR).
When the ORE bit and SMR:RIE bit are set to "1", a reception interrupt
request will be output.
If this flag is set, the receive data register (RDR) will be disabled.
When reception FIFO is used, if this flag is set, the received data will not
be stored in the reception FIFO.
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Chapter 41: Multi-Function Serial Interface
Bit name
Function
bit2 RDRF:
"0" Read: Receive data register (RDR) is empty
Reception data full flag bit "1" Read: Receive data register (RDR) contains data.
The flag indicates the state of the receive data register (RDR).
When the SMR:RIE bit and the reception data flag bit (RDRF) are "1", a
reception interrupt request will be output.
When received data is loaded in the RDR, this flag will be set to "1" and
when RDR is read out, it will be cleared to "0".
Set at the SCL falling timing in 8th bit of the data.
Also set at the NACK response *.
While using reception FIFO, the RDRF will be set to "1" once the
reception FIFO has received the specified number of data sets.
While using reception FIFO, the bit will be cleared to "0" once the
reception FIFO becomes empty.
In the case where all the conditions below are met, when reception idle
continues for more than 8 baud rate clocks, interrupt flag (SSR:RDRF)
will be set to "1".
Reception FIFO idle detection enable bit (FCR:FRIIE) is "1"
Data count contained in the reception FIFO does not reach the transfer
count
IBCR:BER bit is "0"
If RDR is read while the counter is counting 8 clocks, the counter will be
reset to "0" and start counting 8 clocks again.
*: NACK response: indicates that SDA of I2C bus is "1" in the acknowledge
interval.
Note:
In the case where all of the conditions below are met, SCL is made "L" after
ACK is transmitted and SCL releases the state of "L" when the RDRF bit
becomes "0".
Reception FIFO is unused
DMA mode is enabled (IBCR:DMA="1")
RDRF bit is "1" while receiving second or latter byte data
(IBSR:TRX="0")
IBCR:WSEL="0"
In the case where all of the conditions below are met, SCL is made "L" after
1-byte data is received and SCL releases the state of "L" when the RDRF
bit becomes "0".
Reception FIFO is unused
DMA mode is enabled (IBCR:DMA="1")
RDRF bit is "1" while receiving second or latter byte data
(IBSR:TRX="0")
IBCR:WSEL="1"
In case of reception with the DMA mode enabled (DMA=1) and reception
FIFO used, SCL is made "L" when reception FIFO becomes full and SCL
releases the state of "L" when data is read out from RDR even once.
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Bit name
bit1 TDRE:
Transmission data empty
flag bit
Function
"0" Read: Transmit data register (TDR) contains data.
"1" Read: Transmit data register (TDR) is empty.
The flag indicates the state of the transmit data register (TDR).
When the TDRE bit and the SMR:TIE bit are set to "1", a transmission
interrupt request will be output.
When a transmit data is written to TDR, this flag becomes "0", which
indicates that a valid data exists in the TDR. Once a transmission starts
after data being loaded to the transmit shift register, the bit will be set to
"1", which indicates that the TDR does not contain any valid data.
Writing "1" to TSET bit on the serial status register (SSR) results in a
setting. Use this flag for setting "1" to the TDRE bit when detecting an
arbitration lost or a bus error.
bit0 TBI:
"0" Read: Transmitting
Transmission bus idle flag "1" Read: Not transmitting
bit (Only the DMA mode
enabled is effective.)
This bit indicates that I2C doesn't do the transmission operation when the
DMA mode is enabled (DMA=1). When SCL is made "L", and the TBI bit
becomes "0" when the TBI bit becomes "1" in the 2nd or subsequent byte in
DMA mode permission (DMA=1), the state of "L" of SCL is released.
Set condition of TBI bit:
(1) In the 2nd or subsequent byte, the SSR:TDRE bit is "1" while WSEL is
"1" and the master is operating
(2) In the 2nd or subsequent byte, the SSR:TDRE bit is "1" while WSEL is
"1" and the slave is transmitting
(1) The SSR:TDRE bit is "1" while reservation address is not detected in
the first byte and the master is operating
(2) In the 2nd or subsequent byte, the SSR:TDRE bit is "1" while WSEL is
"0" and the master is operating
(3) In the 2nd or subsequent byte, the SSR:TDRE bit is "1" while WSEL is
"0" and the slave is transmitting
When transmission buffer empty flag set bit (TSET) is set to "1"
Reset condition of TBI bit:
When writing transmission data in transmit data register (TDR)
When this bit is "1" and transmission bus idle interrupt is enabled
(SCR:TBIE=1), this bit outputs the transmission interrupt request.
When the DMA mode is disabled (DMA="0"), this bit becomes
undefined.
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Chapter 41: Multi-Function Serial Interface
4.5.3.
I2C Bus Status Register: IBSR
This section explains the bit structure of the I2C bus status register.
I2C bus status register (IBSR) indicates that repeat start, acknowledges, data directions, arbitration lost, stop
conditions, I2C bus states, and bus errors have been detected.
IBSRn(n=3 to 8, 11 to 19) : Address Base addr + 03H (Access: Byte, Half-word, Word)
7
FBT
0
6
RACK
0
5
RSA
0
4
TRX
0
3
AL
0
R,WX
R,WX
R,WX
R,WX
R,WX
Bit name
bit7 FBT:
First byte bit
bit6 RACK:
Acknowledge
flag bit
2
1
RSC
SPC
0
0
R(RM1), R(RM1),
W
W
0
BB
0
bit
Initial value
R,WX Attribute
Function
"0" Read: Other than the first byte
"1" Read: Transmitting/receiving the first byte
This bit indicates the first byte.
FBT bit set conditions:
(1) A (repeat) start condition detected
FBT bit clear conditions:
(1) Transmission/reception of the 2nd byte
(2) A stop condition detected
(3) I2C interface disabled (ISMK:EN bit="0")
(4) Bus error detected (IBCR:BER bit="1")
"0" Read: "L" Reception
"1" Read: "H" Reception
This bit indicates the acknowledges received on the first byte, in master or slave mode.
Update condition for RACK bit
(1) Acknowledgement at the first byte
(2) Acknowledgement of the data in master or slave mode
Clear condition of RACK bit (RACK bit="0")
(1) (Repeat) start condition detected
(2) I2C interface disabled (ISMK:EN bit="0")
(3) Bus error detected (IBCR:BER bit="1")
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Bit name
Function
bit5 RSA:
"0" Read: No reserved address detected
Reserved
"1" Read: Reserved address detected
address detect
bit
This bit indicates that a reserved address was detected.
RSA bit set condition (RSA="1")
(1) The first byte is (0000xxxx) or (1111xxxx). "x" represents "0" or "1".
RSA bit reset condition (RSA="0")
(1) A (repeat) start condition detected
(2) A stop condition detected
(3) I2C interface disabled (ISMK:EN bit="0")
(4) Bus error detected (IBCR:BER bit="1")
When the RSA bit is "1" at the first byte, the interrupt flag (IBCR:INT) becomes "1" and
SCL becomes "L" at SCL falling edge of the 8th bit on the first byte, regardless of the
FIFO enable/disable state. At that time, when you are planning to read the received data
and make it operate as slave, set IBCR:ACKE to "1" and set interrupt flag (IBCR:INT) to
"0". After that, if the TRX bit is "0", the data is received as a slave. When you are
planning to not receive data along the way, set "0" to the IBCR:ACKE bit. After that, no
data is received.
Notes:
When you turn IBCR:ACKE to "0" while data transfer is going on, do not set
IBCR:ACKE to "1" until a stop condition or a repeat start condition is detected.
When a reserved address detect interrupt occurs and a slave transmission is identified,
if the reception FIFO is enabled, it would respond with ACK, so disable the reception
FIFO and turn to IBCR:ACKE="0".
bit4 TRX:
"0" Read: Reception direction
Data direction "1" Read: Transmission direction
bit
This bit indicates the direction of data.
TRX bit set conditions:
(1) A (repeat) start condition is transmitted in master mode
(2) The 8th bit of the first byte is "1" in slave mode (transmission direction as a slave)
TRX bit reset conditions:
(1) Arbitration lost is generated (AL="1")
(2) The 8th bit of the first byte is "0" in slave mode (reception direction as a slave)
(3) The 8th bit of the first byte is "1" in master mode (reception direction as a master)
(4) A stop condition detected
(5) When a (repeat) start condition is detected in a mode other than master mode
(6) I2C interface disable (ISMK:EN bit="0")
(7) Bus error detected (IBCR:BER bit="1")
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Chapter 41: Multi-Function Serial Interface
Bit name
Function
bit3 AL:
"0" Read: No arbitration lost occurred
Arbitration lost "1" Read: Arbitration lost occurred
bit
This bit indicates an arbitration lost.
AL bit set conditions:
(1) Output data and received data are different in master mode.
(2) You set "1" to the IBCR:MSS bit but the operation is still in slave mode.
(3) A repeat start condition was detected at the first bit of the second byte or later in
master mode.
(4) A stop condition was detected at the first bit of the second byte or later in master
mode.
(5) Trying to generate a repeat start condition was disabled in master mode.
(6) Trying to generate a stop condition was disabled in master mode.
AL bit reset conditions:
(1) Writing "1" to the IBCR:MSS bit
(2) Writing "0" to the IBCR:INT bit
(3) Writing "0" to SPC bit when AL="1" and SPC="1"
(4) I2C interface disabled (ISMK:EN bit="0")
(5) Bus error detected (IBCR:BER bit="1")
bit2 RSC:
"0" Read: No repeated start condition detected
Repeat start
"1" Read: Repeated start condition detected
condition check
bit
This bit indicates that repeat start condition was detected in master mode or slave mode.
RSC bit set conditions
(1) A repeat start condition was detected after acknowledgement in master mode or slave
mode
RSC bit reset conditions:
(1) Writing "0" to the RSC bit
(2) Writing "1" to the IBCR:MSS bit
(3) I2C interface disabled (ISMK:EN bit="0")
There will be no effect on the operation of writing "1" to this bit.
Notes:
If an acknowledge response is not made when receiving data as the slave mode due to
the detection of the reserved address, "1" will not be set to this bit the next time the
detection of a repeat start condition occurred because it has already exited the slave
mode.
For read-modify-write instructions, "1" will be read.
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Bit name
Function
bit1 SPC:
"0" Read: No stop condition detected
Stop condition "1" Read: (Master) stop condition detected or generation of arbitration lost at stop
check bit
condition output
"1" Read: (Slave) stop condition detected
bit0 BB:
Bus state bit
This bit indicates that stop condition was detected in master mode or slave mode.
SPC bit set conditions:
(1) A stop condition was detected in master mode or slave mode
(2) An arbitration lost is generated on the stop condition generation in master mode
SPC bit reset conditions:
(1) Writing "0" to this bit
(2) Writing "1" to the IBCR:MSS bit
(3) I2C interface disabled (ISMK:EN bit="0")
Writing "1" to this bit does not effect on the operation.
Notes:
If an acknowledge response is not made when receiving data as the slave mode due to
the detection of the reserved address, "1" will not be set to this bit the next time the
detection of a stop condition occurred because it has already exited the slave mode.
For read-modify-write instructions, "1" will be read.
"0" Read: Bus idle state
"1" Read: Bus transmission/reception state
This bit indicates the bus state.
BB bit set conditions:
(1) When "L" was detected at SDA or SCL on I2C bus
BB bit reset conditions:
(1) When a stop condition detected
(2) I2C interface disabled (ISMK:EN bit="0")
(3) Bus error detected (IBCR: IBER bit="1")
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Chapter 41: Multi-Function Serial Interface
4.5.4.
Receive Data Register/Transmit Data Register: RDR/TDR
This section explains the bit structure of the receive data register/transmit data register.
Receive data register and transmit data register are located within the same addresses. When read, it functions as the
receive data register and when written, it functions as the transmit data register.
Read
RDR1n-0n(n=3 to 8, 11 to 19) : Address Base addr + 06H (Access: Byte, Half-word,
Word)
15
12
11
Reserved
0
0
0
0
0
RX,WX RX,WX RX,WX RX,WX RX,WX
7
D7
0
R,W
14
6
D6
0
R,W
13
5
D5
0
R,W
4
D4
0
R,W
3
D3
0
R,W
10
9
8
bit
0
0
0
Initial value
RX,WX RX,WX RX,WX Attribute
2
D2
0
R,W
1
D1
0
R,W
0
D0
0
R,W
bit
Initial value
Attribute
The receive data register (RDR) is the data buffer register for serial data reception.
Serial data signals sent to the serial data line (SDA pin) are converted in the shift register and stored in the receive
data register (RDR).
When you receive the first byte*, the least significant bit (RDR:D0) is the data direction bit.
When the received data is stored in the receive data register (RDR), the reception data full flag bit (SSR:RDRF)
will be set to "1".
The reception data full flag bit (SSR:RDRF) will be automatically cleared to "0" when the receive data register
(RDR) has been read out.
*: The first byte: indicates data after the (repeat) start condition
Notes:
When you use reception FIFO, if received data in the reception FIFO reaches specified number, "1" will be set to
SSR:RDRF.
When you are using reception FIFO, if the reception FIFO becomes empty, SSR:RDRF will be cleared to "0".
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Write
TDR1n-0n(n=3 to 8, 11 to 19) : Address Base addr + 06H (Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
RX,WX RX,WX RX,WX RX,WX
7
D7
1
RX,W
6
D6
1
RX,W
5
D5
1
RX,W
4
D4
1
RX,W
RX,WX
3
D3
1
RX,W
Initial value
RX,WX RX,WX RX,WX Attribute
2
D2
1
RX,W
1
D1
1
RX,W
0
bit
D0
1
Initial value
RX,W Attribute
The transmit data register (TDR) is the data buffer register for sending serial data.
Output to serial data line (SDA Pin) at the MSB first on transmit data register (TDR).
When you send the first byte, the least significant bit (TDR:D0) is the data direction bit.
Transmission data empty flag (SSR:TDRE) will be cleared to "0" when the transmission data is written to the
transmit data register (TDR).
Transmission data empty flag (SSR:TDRE) will be set to "1" when transferred to the transmit shift register.
If transmission FIFO is disabled and the transmission data empty flag (SSR:TDRE) is "0", the transmission data
cannot be written to the transmit data register (TDR).
When using transmission FIFO, the transmission data can be written to the amount of transmission FIFO, even if
the transmission data empty flag (SSR:TDRE) is "0".
Note:
Transmission data register is write-only register and receive data register is read-only register. Because the two
registers are located in the same address, write value and read value might be different. Therefore instructions such as
INC/DEC instructions which perform read-modify-write (RMW) operations cannot be used.
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Chapter 41: Multi-Function Serial Interface
4.5.5.
Serial Aid Control Status Register: SACSR
This section explains the bit structure of the serial aid control status register.
The serial aid control status register (SACSR) allows you to enable/disable timer interrupts, set the division value of
the operating clock of the serial timer, and enable/disable the serial timer.
SACSRn(n=3 to 8, 11 to 19) : Address Base addr + 08H (Access: Byte, Half-word,
Word)
15
14
13
11
10
0
12
Reserved
0
0
0
0
0
R0,W0
RX,W0
R0,W0
R0,W0
R0,W0
RX,W0
7
TINTE
0
R/W
6
5
4
Reserved TDIV3
0
0
0
R0,WX RX,W0
R,W
3
TDIV2
0
R,W
2
TDIV1
0
R,W
9
8
bit
TINT
0
0
Initial value
R(RM1),
RX,W0
Attribute
W
1
TDIV0
0
R,W
0
bit
TMRE
0
Initial value
R/W Attribute
[bit15 to bit9] Reserved bit
Always set these bits to "0".
[bit8] TINT: Timer interrupt flag
When the serial timer register (STMR) matches the serial timer compare register (STMCR), the serial timer register
(STMR) will be set to "0", and this bit will be set to "1".
When this bit is set to "1" and the timer interrupt enable bit (TINTE) is set to "1", a status interrupt request will be
output.
Writing "0" to this bit will reset it to "0".
Writing "1" to this bit has no effect.
TINT
0
1
Description
No timer interrupt request
Timer interrupt request
Note:
For read-modify-write instructions, "1" will be read.
[bit7] TINTE: Timer interrupt enable bit
This bit is used to enable/disable timer interrupts to the CPU.
When this bit is set to "1" and the timer interrupt flag (TINT) is set to "1", a status interrupt request will be output.
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TINTE
Description
0
1
Interrupts by the serial timer disabled
Interrupts by the serial timer enabled
[bit6] Undefined
The read value is "0". Writing has no effect on the operation.
[bit5] Reserved bit
Always set this bit to "0".
[bit4 to bit1] TDIV3-0: Timer operating clock division bits
These bits are used to set the division ratio of the serial timer.
Timer operating clock
TDIV3 TDIV2 TDIV1 TDIV0 Division
ϕ=
ϕ=
ϕ=
ϕ=
ϕ=
ϕ=
ratio
8MHz 10MHz 16MHz 20MHz 24MHz 32MHz
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
ϕ: Bus clock
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
ϕ
ϕ/2
ϕ/4
ϕ/8
ϕ/16
ϕ/32
ϕ/64
ϕ/128
ϕ/256
125ns
250ns
500ns
1μs
2μs
4μs
8μs
16μs
32μs
100ns
200ns
400ns
800ns
1.6μs
3.2μs
6.4μs
12.8μs
25.6μs
62.5ns
125ns
250ns
500ns
1μs
2μs
4μs
8μs
16μs
50ns
100ns
200ns
400ns
800ns
1.6μs
3.2μs
6.4μs
12.8μs
41.67ns 31.25ns
83.33ns 62.5ns
166.67ns 125ns
333.33ns 250ns
666.67ns 500ns
1.33μs
1μs
2.67μs
2μs
5.33μs
4μs
10.67μs
8μs
Notes:
These bits can be changed only when the serial timer enable bit (TMRE) is set to "0".
Settings other than those listed above are prohibited.
[bit0] TMRE: Serial timer enable bit
This bit is used to enable or disable the operation of the serial timer.
TMRE
0
1
1264
Serial timer enable bit
The operation of the serial timer will be stopped.
During stop, the value of the serial timer register (STMR)
will be retained.
If this bit is changed from "0" to"1", the value of the serial
timer register (STMR) will be initialized to "0", and the
operation of the serial timer will be started.
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Chapter 41: Multi-Function Serial Interface
4.5.6.
Serial Timer Register: STMR
This section explains the bit structure of the serial timer register.
The serial timer register (STMR) is used to indicate the timer value of the serial timer.
STMRn(n=3 to 8, 11 to 19) : Address Base addr + 0AH (Access: Byte, Half-word,
Word)
15
TM15
0
R,WX
14
TM14
0
R,WX
13
TM13
0
R,WX
12
TM12
0
R,WX
11
TM11
0
R,WX
10
TM10
0
R,WX
9
TM9
0
R,WX
8
bit
TM8
0
Initial value
R,WX Attribute
7
TM7
0
R,WX
6
TM6
0
R,WX
5
TM5
0
R,WX
4
TM4
0
R,WX
3
TM3
0
R,WX
2
TM2
0
R,WX
1
TM1
0
R,WX
0
bit
TM0
0
Initial value
R,WX Attribute
[bit15 to bit0] TM15-0: Timer data bits
These bits are used to indicate the timer value of the serial timer.
During timer operation, 1 will be added to the timer value of the serial timer for each timer operating clock (set by
SACSR:TDIV3-0).
Note:
At the start of timer operation, these bits will be initialized to "0".
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4.5.7.
Serial Timer Compare Register: STMCR
This section explains the bit structure of the serial timer compare register.
The serial timer compare register (STMCR) is used to set compared values of the serial timer.
STMCRn(n=3 to 8, 11 to 19) : Address Base addr + 0CH (Access: Byte, Half-word,
Word)
15
TC15
0
R/W
14
TC14
0
R/W
13
TC13
0
R/W
12
TC12
0
R/W
11
TC11
0
R/W
10
TC10
0
R/W
9
TC9
0
R/W
8
TC8
0
R/W
bit
7
TC7
0
R/W
6
TC6
0
R/W
5
TC5
0
R/W
4
TC4
0
R/W
3
TC3
0
R/W
2
TC2
0
R/W
1
TC1
0
R/W
0
TC0
0
R/W
bit
Initial value
Attribute
Initial value
Attribute
[bit15 to bit0] TC15 to TC0: Compare bits
These bits are used to set compared values of the serial timer.
These bits will be compared with the serial timer register (STMR), and when these bits match the value of the serial
timer register immediately after the serial timer register (STMR) is updated, they will set the serial timer register to
"0". Then, these bits will set the timer interrupt flag (SACSR:TINT) to "1".
The interval of the following operations is (STMCR: TC+1) x timer operating clock (set to SACSR:TDIV3-0).
SACSR:TINT is set to "1".
Notes:
When "0000H" is set to this register, the serial timer register will remain set to "0".
When "0000H" is set to this register, the timer interrupt flag (SACSR:TINT) will be fixed to "1", if the division
value of the timer operating clock (SACSR:TDIV) is set to "0000 B" during timer operation.
This register can be changed only when the serial timer is disabled (SACSR:TMRE="0").
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4.5.8.
7-bit Slave Address Mask Register: ISMK
This section explains the bit structure of the 7-bit slave address mask register.
7-bit slave address mask register (ISMK) compares and configures bits of slave address.
ISMKn(n=3 to 8, 11 to 19) : Address Base addr + 1EH (Access: Byte, Half-word, Word)
7
EN
0
R/W
6
SM6
1
R/W
5
SM5
1
R/W
4
SM4
1
R/W
3
SM3
1
R/W
2
SM2
1
R/W
1
SM1
1
R/W
0
SM0
1
R/W
bit
Initial value
Attribute
2
[bit7] EN: I C interface enable bit
This bit enables/disables I2C interface operation.
If this bit is set to "0", I2C interface becomes disabled.
If this bit is set to "1", I2C interface becomes enabled.
I2C-UART operation enable bit
EN
0
1
Disabled
Enabled
Notes:
When the BER bit of the IBSR register is set to "1", this bit will not be cleared to "0".
Configure the baud rate generator when this bit is "0".
When this bit is "0", configure 7-bit slave address and 7-bit slave mask register.
If the I2C interface is disabled (EN="0"), transmission/reception becomes disabled immediately.
When you disable the I2C interface operation after generating a stop condition by writing "0" to the IBCR:MSS bit,
disable it (EN="0") after checking for the generation of the stop condition.
Setting "0" to the EN bit during transmission could generate SDA/SCL pulse on the I 2C bus.
[bit6 to bit0] SM6-0: Slave address mask bits
These bits configure whether to exclude the 7-bit slave address and received address as the comparison targets.
If these bits are set to "0": treat as matched
If these bits are set to "1": compare
SM6-0
0
1
7-bit slave address mask bits
Bits not compared
Bits compared
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Note:
Configure this register when the EN bit is "0".
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4.5.9.
7-bit Slave Address Register: ISBA
This section explains the bit structure of the 7-bit slave address register.
7-bit slave address register (ISBA) sets slave addresses.
ISBAn(n=3 to 8, 11 to 19) : Address Base addr + 1FH (Access: Byte, Half-word, Word)
7
SAEN
0
R/W
6
SA6
0
R/W
5
SA5
0
R/W
4
SA4
0
R/W
3
SA3
0
R/W
2
SA2
0
R/W
1
SA1
0
R/W
0
SA0
0
R/W
bit
Initial value
Attribute
[bit7] SAEN: Slave address enable bit
This bit enables slave address detection.
Setting "0": Does not detect a slave address.
Setting "1": Compares the ISBA and ISMK values with the first byte received.
SAEN
0
1
Slave address enable bit
Disabled
Enabled
[bit6 to bit0] SA6-0: 7-bit slave address
If the slave address detect is enabled (SAEN=1), the 7-bit slave address register (ISBA) compares with the 7-bit
data received after a (repeat) start condition detected, and if all the bits are matched, it will operate as a slave and
output ACK. At that time, the slave address received will be set to this register. (If SAEN=0, ACK will not be
output.)
The address bits with "0" set on the ISMK register will be excluded from the comparison.
SA
6 to 0
Slave address setting bits
7-bit slave address
Notes:
The reserved address cannot be set.
Set this register when the EN bit of the ISMK register is "0".
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4.5.10. Baud rate Generator Register: BGR
This section explains the bit structure of the baud rate generator register.
Baud rate generator register (BGR) sets the division ratio of serial clock.
BGRn(n=3 to 8, 11 to 19) : Address Base addr + 1CH (Access: Half-word, Word)
15
RX,WX
14
13
12
0
R/W
0
R/W
0
R/W
7
6
5
0
R/W
0
R/W
0
R/W
11
BGR[14:8]
0
R/W
4
3
BGR[7:0]
0
0
R/W
R/W
10
9
8
0
R/W
0
R/W
0
R/W
2
1
0
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
bit
Initial value
Attribute
[bit15] Undefined
No effect for writing operations.
[bit14 to bit0] BGR (Baud rate GeneratoR): Baud Rate Generator Bit
These bits set division rate of the serial clock.
Capable of writing reload value to be counted and reading setup values.
Reload counter will start counting when a reload value is written.
Notes:
Write to the baud rate generator (BGR) in 16-bit access mode.
Configure the baud rate generator register when the EN bit of the ISMK register is "0".
Configure baud rate regardless of the master mode or slave mode.
Peripheral clock (PCLK) should be set with 8MHz or more in operating mode 4 (I 2C mode) and baud rate
generator configured in 400kbps or more should not be used.
5. Operation of UART
This section explains operation of UART.
5.1 Interrupt of UART
5.2 Operation of UART
5.3 Setup Procedure and Program Flow
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5.1.
Interrupt of UART
Interrupt of UART is shown.
There are interrupts for both transmission and reception in UART. You can generate an interrupt request for the
following factors.
Setting of reception data in the receive data register (RDR) or occurrence of a reception error
Start of transmission after transfer of transmission data from the transmit data register (TDR) to the transmit shift
register
Transmission bus idle (no transmission operation)
Transmission FIFO data request
5.1.1.
List of Interrupt of UART
This section explains the list of interrupt of UART.
The following table indicates how UART interrupt control bits relate to interrupt factors.
Table 5-1 Interrupt Control Bits and the Interrupt Factors of UART
Operatio
Interrupt
Interrupt
Interrup
Flag n mode
Interrupt
request
factor enable Interrupt request flag clear
t type
register
factor
flag bit
bit
0 1
RDRF
SSR
Reception
ORE
FRE
PE
SSR
SSR
SSR
-
1-byte reception
Reception of as
much data as
specified by
FBYTE
Detection of
reception idle
for 8-bit time or
more while there
is valid data in
the reception
FIFO with the
FRIIE bit set to
"1".
Overrun error
Framing error
Parity error
Reading of receive data (RDR)
SCR:RIE
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Reading of receive data (RDR) until
the reception FIFO is emptied
Writing of "1" to the reception error
flag clear bit (SSR:REC)
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Operatio
Interrupt
Interrup
Flag n mode
request
t type
register
flag bit
0 1
Transmission
Interrupt
factor
Interrupt
factor enable
bit
TDRE
SSR
Transmission
register is empty
SCR:TIE
TBI
SSR
No transmission
operation
SCR:TBIE
Interrupt request flag clear
Writing to the transmit data (TDR) or
writing of "1" to the transmission
FIFO operation enable bit while the
transmission FIFO operation enable
bit is "0" and there is valid data in the
transmission FIFO (retransmission)*
Writing the transmit data (TDR) or
writing of "1" to the transmission
FIFO operation enable bit while the
transmission FIFO operation enable
bit is "0" and there is valid data in the
transmission FIFO (retransmission)*
The storage data
value of the
Writing of "0" to the FIFO
transmission
transmission data request bit
FDRQ
FCR1
FCR1:FTIE
FIFO is FTICR
(FCR1:FDRQ) or the transmission
setting value or
FIFO is full
less, or empty
Serial Timer
Register
(STMR)
matched Serial
Writing "0" to the timer interrupt flag
Status
TINT
SACSR
SACSR:TINTE
Timer
bit (SACSR:TINT)
Comparison
Register
(STMCR)
*: Set the TIE bit to "1" after the TDRE bit is cleared to "0".
: Operation mode effective
-: Operation mode non-effective
5.1.2.
Reception Interrupts and Flag Setting Timing
This section explains the generation of reception interrupts and flag setting timing.
Reception interrupts occur either when the reception is completed (SSR:RDRF) or when a reception error occurs
(SSR:PE, ORE, FRE).
When the first stop bit is detected, reception data is stored in the receive data register (RDR). When reception is
completed (SSR:RDRF=1) or a reception error occurs (SSR:PE, ORE, FRE=1), a corresponding flag is set. If
reception interrupts are enabled (SCR:RIE=1) at this time, a reception interrupt occurs.
Note:
When a reception error occurs, the data in the receive data register (RDR) becomes invalid.
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Figure 5-1 Timing of Flag Bit Setting
Timing to set RDRF(reception data full) flag bit
Reception data
ST
D0
D1
D2
D5
D6
D7
SP
ST
RDRF
Generation of reception interrupt
Timing to set FRE(framing error) flag bit
Reception data
ST
D0
D1
D2
D5
D6
D7
SP
ST
RDRF
FRE
Generation of reception interrupt
(Notes)
• A framing error occurs when the first stop bit is at the “L” level.
• RDRF is set to “1” and data is received even when a framing error occurs, but the reception data is
invalid.
Timing to set ORE(overrun error) flag bit
Reception data
ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP
RDRF
ORE
(Note)
An overrun error occurs when the next data is transferred before the reception data is read (RDRF=1).
Note:
When any of following conditions is detected while receiving at the same time of or 1 to 2 bus clocks before the
sampling point for stop bit, its edge will be invalid and the next data may not be received correctly. To output frames
continuously, some space is required between the frames.
Trailing edge of serial data (when ESCR:INV="0")
Rising edge of serial data (when ESCR:INV="1")
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5.1.3.
Interrupts when Using Reception FIFO and Flag Setting
Timing
This section explains the generation of interrupts when using reception FIFO and flag setting timing.
When the reception FIFO is used, an interrupt occurs after as much data as the FBYTE register (FBYTE) setting is
received. The setting value of the FBYTE register determines the occurrence of an interrupt when the reception FIFO
is used.
After as much data as the transfer count setting of the FBYTE register is received, the reception data full flag of the
serial status register (SSR:RDRF) is set to "1". If the reception interrupt is enabled (SCR:RIE) at this time, a
reception interrupt is generated.
In the case where all the conditions below are met, when reception idle continues for more than 8 baud rate clocks,
interrupt flag (SSR:RDRF) will be set to "1".
Reception FIFO idle detection enable bit (FCR:FRIIE) is "1"
Data count contained in the reception FIFO does not reach the transfer count
If you read the RDR while the counter is counting 8 baud rate clocks, the counter will be reset to 0 and start counting
8 clocks again. When reception FIFO is disabled, the counter will be reset to "0". When the reception FIFO is enabled
while any data is left in the reception FIFO, counting will be started once again.
If the receive data (RDR) is read until the reception FIFO is empty, the reception data full flag (SSR:RDRF) is
cleared.
When the reception-enabled data count indication has shown the FIFO capacity, receiving the next data will
generate an overrun error (SSR:ORE=1) .
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Figure 5-2 Timing of Using FIFO
Timing to Generate Reception Interrupt when Reception FIFO is Used
Reception data
ST 1
st
Byte
SP
ST 2
nd
Byte SP
ST 3
FBYTE setting
(number of transfer)
rd
Byte SP
ST 4
th
Byte
SP
ST 5
th
Byte
SP
3
FBYTE reading
(Valid byte display)
1
0
2
3
2
1
0
1
2
RDRF
Reading RDR
Generation of interrupt by the match of number of FBYTE
setting(number of transfer) and number of reception data
Reading of
all reception data
Timing to Set ORE(Overrun Error) Flag Bit
Reception data
nd
ST 62
Byte SP
rd
ST 63
th
ST 64
Byte SP
th
ST 65
Byte SP
th
ST 66
Byte SP
62
FBYTE setting (number of transfer)
FBYTE reading(valid byte display)
Byte SP
62
63
64
RDRF
ORE
Overrun error occurrence
(Note)
An overrun error will occur if the next data is received when FBYTE reading indicates FIFO capacity.
The figure shows the case where 64-byte FIFO is used.
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5.1.4.
Transmission Interrupts and Flag Setting Timing
This section explains the generation of transmission interrupts and flag setting timing.
Transmission interrupts occur either when transmission is started after transfer of transmission data from the transmit
data register (TDR) to the transmit shift register (SSR:TDRE=1) or when the transmission operation is idle
(SSR:TBI=1).
When data written to the transmit data register (TDR) is transferred to the transmit shift register, writing of next data
is enabled (SSR:TDRE=1). If the transmission interrupt is enabled (SCR:TIE=1) at this time, a transmission interrupt
occurs. The TDRE bit, being a read-only bit, is cleared to "0" by writing of data to the transmit data register (TDR).
When the transmit data register is empty (TDRE=1) and no transmission operation is in progress, the SSR:TBI bit is
set to "1". If transmission bus idle interrupt is enabled (SCR:TBIE=1) at this time, a transmission interrupt will occur.
When transmission data is written to the transmit data register (TDR), the SSR:TBI bit and the transmission interrupt
request are cleared.
Figure 5-3 Timing of Transmission Interrupt Flag
Timing to Set Transmission Data Empty Flag (TDRE)
Generation of transmission interrupt
Transmission
data
(mode0,mode1)
ST
D0
D1
D2
D3
Generation of transmission interrupt
D4
D5
D6 D7
SP
ST
D0
D1 D2
TDRE
Writing to TDR
ST : Start bit
D0 to D7 : Data bit
SP : Stop bit
Timing to Set Transmission Bus Idle Flag (TBI)
Transmission
data
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
TBI
TDRE
Write to TDR
Generation of
transmission interrupt by
TBI bit
ST : Start bit D0 to D7 : Data bit SP : Stop bit
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5.1.5.
Interrupts When Using Transmission FIFO and Flag
Setting Timing
This section explains the generation of interrupts when using transmission FIFO and flag setting
timing.
When the transmission FIFO is used, an interrupt is generated when the data count stored at the transmission FIFO is
equal to or less than the count set for the FTICR register (FTICR).
When the transmission FIFO is used, the interrupt generation is decided depending on the FTICR register setting
value.
When the storage data value of the transmission FIFO is FTICR register (FTICR) setting value or less, the FIFO
transmission data request bit (FCR1:FDRQ) will be set to "1".
If FIFO transmission interrupt is enabled (FCR1:FTIE="1") at this time, a transmission interrupt will occur.
When required data is written to the transmission FIFO after the occurrence of a transmission interrupt, write "0" to
the FIFO transmission data request bit (FCR1:FDRQ) to clear the interrupt request.
When the transmission FIFO is full, the FIFO transmission data request bit (FCR1:FDRQ) is set to "0".
The presence of data in the transmission FIFO can be checked by reading the FIFO byte register (FBYTE) or the
transmission FIFO interrupt control register (FTICR).
When FBYTE=0x00 and FTICR=0x00, there is no data in the transmission FIFO.
Figure 5-4 Timing of Transmission Interrupts when Using Transmission FIFO
Transmission data
FBYTE
0
ST First byte SP
1
2
1
ST Second byte SP
0
1
ST Third byte ST
2
1
SP Fourth byte SP
SP Fifth byte
0
FDRQ
TDRE
Clearing by
Generation of
"0" writing transmission inter rupt *1
Clearing by
Generation of
"0" writing transmission inter rupt *1
Writing to
transmission
FIFO (TDR)
Empty transmission data register *2
*1: FDRQ=1 is set because transmission FIFO is empty.
*2: TDRE=1 is set because there is no data in the transmission shift register and t ransmission buffer register.
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5.1.6.
Timing of Timer Interrupt Generation and Flag Setting
This section explains the timing of timer interrupt generation and flag setting.
Timer interrupt is generated when Serial Timer Register (STMR) matched Serial Timer Comparison Register
(STMCR).
When Serial Timer Register (STMR) matched Serial Timer Comparison Register (STMCR), "1" will be set to
timer interrupt flag (SACSR:TINT).
At this time when the timer interrupt is enabled (SACSR:TINTE="1"), a status interrupt will be generated.
Figure 5-5 Timer Interrupt Generation Timing
STMR
0
1
2
・・・
9
10
0
1
10
STMCR
Generation of
status interrupt
TINT
Timer activation
5.2.
Operation of UART
Operation of UART is shown.
UART operates with the mode 0 bidirectional serial asynchronous communication and the mode 1 master/slave
multiprocessor communication.
5.2.1.
Transmission/Reception Data Format
This section explains the transmission/reception data format.
The transmission/reception data always starts from the start bit and after the transmission/reception of data have
taken place for the specified data bit length, ends at 1-bit or more length of stop bit.
The direction of data transfer (LSB first or MSB first) is determined by the BDS bit of the serial mode register
(SMR). If parity is used, the parity bit will always be placed between the last data bit and the first stop bit.
In operation mode 0 (normal mode), you can select whether to use parity.
In operation mode 1 (multiprocessor mode), the parity will not be added, instead AD bits will be added.
An example of transmission/reception data format (operation modes 0, 1) is shown in Figure 5-6:
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Figure 5-6 Example of Transmission/Reception Data Format (Operation Modes 0, 1)
［operation mode 0］
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP1
SP2
Without P
8 bit data
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
SP1
SP2
ST
D0
D1
D2
D3
D4
D5
D6
SP1
ST
D0
D1
D2
D3
D4
D5
D6
P
SP2
With P
Without P
7 bit data
SP1 SP2
With P
ST
D0
D1
D2
D3
D4
D5
D6
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
［operation mode 1］
SP1
SP2
8 bit data
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
SP1
ST
D0
D1
D2
D3
D4
D5
D6
AD
SP1
SP2
ST
D0
D1
D2
D3
D4
D5
D6
AD
SP1
7 bit data
ST ： Start bit
SP ： Stop bit
P : Parity bit
AD : Address/data bit
D : Data bit
Notes:
The Figure above shows the example of configurations with data length of 7 and 8 bits. (You can configure 5 to
9-bit data length in operation mode 0.)
When you set "1" to the BDS bit of serial mode register (SMR) (MSB first), the bits will be processed in the order,
D7, D6, D5, ..., D1, D0 (P).
When you configure x bit of data length, the lower x bits on transmission/receive data register (RDR/TDR) will be
enabled.
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5.2.2.
Transmission Operation
This section explains the transmission operation.
If the transmission data empty flag bit (TDRE) of the serial status register (SSR) is "1", the transmission data can
be written to the transmit data register (TDR). (If the transmission FIFO is enabled, transmission data can be
written even if TDRE="0").
When transmission data is written to the transmit data register (TDR), the transmission data empty flag bit
(SSR:TDRE) becomes "0".
When the transmission operation enable bit of the serial control register (SCR:TXE) is set to "1", the transmission
data is loaded into the transmit shift register and the transmission starts from the start bit sequentially.
When the transmission starts, the transmission data empty flag bit (SSR:TDRE) will be set to "1" again. If the
transmission interrupt is enabled (SCR:TIE=1) at this time, a transmission interrupt occurs. In interrupt processing,
the next transmission data can be written to the transmit data register.
Notes:
As soon as the transmission interrupt is enabled (SCR:TIE), a transmission interrupt occurs, because the
transmission data empty flag bit (SSR:TDRE) has the initial value "1".
As soon as the FIFO transmission interrupt is enabled (FCR1:FTIE=1), a transmission interrupt occurs, because the
FIFO transmission data request bit (FCR1:FDRQ) has the initial value "1".
5.2.3.
Reception Operation
This section explains the reception operation.
When reception operation is enabled (SCR:RXE=1), the reception operation will start.
When a start bit is detected, one frame data will be received according to the data format set in the extended
communication control register (ESCR:PEN, P, L2, L1, L0) and serial mode register (SMR:BDS). The start bit is
detected when the falling edge (at ESCR:INV="0") or the rising edge (at ESCR:INV="1") is detected after data
passes the noise filter (majority decision by sampling the serial data input with the bus clock three times), and the
passed data detects "L" at the sampling point.
When the reception of one frame data has completed, the reception data full flag bit (SSR:RDRF) will be set to "1".
If reception interrupts are enabled (SCR:RIE=1) at this time, a reception interrupt occurs.
Read reception data, after the one frame data reception has completed, and check for the state of error flag of the
serial status register (SSR). When a reception error has detected, correct the error.
After a read of reception data, the reception data full flag bit (SSR:RDRF) will be cleared to "0".
When reception FIFO is enabled, if as many frames as set in the reception FBYTE have been received, the
reception data full flag bit (SSR:RDRF) will be set to "1".
In the case where all the conditions below are met, when reception idle continues for more than 8 baud rate clocks,
interrupt flag (RDRF) will be set to "1".
Reception FIFO idle detection enable bit (FRIIE) is "1"
Data count contained in the reception FIFO does not reach the transfer count
If you read the RDR while the counter is counting 8 baud rate clocks, the counter will be reset to 0 and start
counting 8 clocks again. When reception FIFO is disabled, the counter will be reset to "0". When the reception
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FIFO is enabled while any data is left in the reception FIFO, counting will be started once again.
When the reception FIFO is enabled, if the error flag of the serial status register (SSR) is set to"1", the erroneous
data will not be stored in the reception FIFO. Also, the reception data full flag bit (SSR:RDRF) at that time will not
be set to "1". (However, when an overrun error does occur, the flag will be set to "1".) The reception FBYTE
indicates the number of data items which have been successfully received before the error occurs. Unless the error
flag of the serial status register (SSR) is cleared to "0", the reception FIFO will not be enabled.
When the reception FIFO is enabled, if the reception FIFO has no more data, the reception data full flag bit
(SSR:RDRF) will be cleared to "0".
Notes:
The data on the receive data register (RDR) will be enabled when the receive data register full flag bit
(SSR:RDRF) is set to "1" and a reception error does not occur (SSR:PE, ORE, FRE=0).
When the noise passes the filter, the incorrect data is received though the noise filter (where the serial data input is
sampled three times with the bus clock and decided by majority) is built in. As measures against this, design the
board so that the noise should not pass this filter or communicate so that noise passing may not become a problem
(for instance, add the checksum of data at the end, and send it again if an error occurs).
When any of following conditions is detected while receiving at the same time of or 1 to 2 bus clocks before the
sampling point for stop bit, its edge will be invalid and the next data may not be received correctly. To output
frames continuously, some space is required between the frames.
Trailing edge of serial data (when ESCR:INV="0")
Rising edge of serial data (when ESCR:INV="1")
5.2.4.
Clock Selection
This section explains the clock selection.
Internal clocks or external clocks can be used.
When you use an external clock, set BGR:EXT="1". In this case, the external clock is divided in the baud rate
generator.
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5.2.5.
Start Bit Detection
This section explains the start bit detection.
The start bit is recognized by the falling edge of the SIN signal in asynchronous mode.
Therefore even if you enable reception operation (SCR:RXE="1"), the reception operation will not start unless the
falling edge of the SIN signal is entered.
When the falling edge of the start bit is detected, the reception reload counter of the baud rate generator will be
reset, a reload will take place again, and the countdown will start. This will always launch a data sampling aimed at
the center of the data.
Figure 5-7 Start Bit Detection
Start bit
Data bit
SIN
SIN(OverSampled)
SEDGE
(internal signal)
Reload counter
reset
Data sampling
Reception
sampling clock
1bit time
5.2.6.
Stop Bit
This section explains the stop bit.
You can select 1-4 bit length.
The reception data full flag bit (SSR:RDRF) will be set to "1" when the first stop bit is detected.
5.2.7.
Error Detection
This section explains the error detection.
In operation mode 0, parity errors, overrun errors, frame errors can be detected.
In operation mode 1, overrun errors and frame errors can be detected. Parity errors cannot be detected.
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5.2.8.
Parity Bit
This section explains the parity bit.
Parity bit can be added only in operating mode 0. The parity enable bit (ESCR:PEN) can specify whether to enable
or disable the parity, and the parity selection bit (ESCR:P) can specify whether to use even parity or odd parity.
Operation mode 1 does not use parity.
Figure 5-8 Operation with Parity Enabled
ST
D0
D1
D2
D3
D4
D5
D6 D7
Reception
data(mode0)
SMR : PE
Transmission
data(mode0)
Transmission
data(mode0)
P
SP
Occurrence of parity
error at reception using
even-parity (ESCR :
P=0)
Transmission of even
parity (ESCR : P=0)
Transmission of odd
parity (ESCR : P=1)
ST : Start bit
SP : Stop bit
For 8-bit length including a parity (ESCR:PEN=1)
The parity bit cannot be used for operating mode 1.
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5.2.9.
Data Signaling Method
This section explains the data signaling method.
The INV bit setting of the extended communication control register enables you to select the NRZ (Non Return to
Zero) signaling method (ESCR:INV=0) or the inverted NRZ signaling method (ESCR:INV=1).
Figure 5-9 NRZ (Non Return to Zero) Signaling Method and Inverted NRZ Signaling Method
SIN (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SIN (inverted
NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SOT (NRZ)
INV = 0
SOT (inverted
NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
5.2.10. Operation of Serial Timer
This section explains the operation of the serial timer.
The serial timer can be used for either of the timer function or the synchronous transmission function.
How to Start Serial Timer
To start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE).
Start by using the serial timer enable bit (SACSR:TMRE)
When the serial timer enable bit (SACSR:TMRE) is set to "1", the serial timer starts and the serial timer register
(STMR) starts counting from 0.
Figure 5-10 Start by Using Serial Timer Enable Bit (STMCR="10")
Serial timer activation
STMR
STMCR
0
1
2
・・・
9
10
0
1
10
TINT
TMRE
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How to Stop Serial Timer
When the serial timer enable bit (SACSR:TMRE) is set to "0", the serial timer will stop. The value of the serial timer
register (STMR) is retained.
Timer Operation
The serial timer operates as a timer.
If the serial timer register (STMR) matches the serial timer comparison register (STMCR), the timer interrupt flag
(SACSR:TINT) is set to "1" and the serial timer register (STMR) is reset to "0".
Figure 5-11 Timer Operation (STMCR="10")
STMR
STMCR
0
1
2
・・・
9
10
0
1
2
・・・
9
10
0
1
10
TINT
Timer activation
Writing “0”
to TINT
Note:
When the timer comparison register (STMCR) is set to "0000H", the timer interrupt flag (SACSR:TINT) is fixed to
"1" if the timer is operating and the division value of the timer operating clock (SACSR:TDIV) is set to "0000B".
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5.2.11. Test Mode
This section explains the test mode.
This section explains the operation of the test mode.
Serial Test Mode
When the serial test mode is enabled (SACSR:STST="1"), SOT and SIN are connected inside the multi-function
serial interface, and then the data sent from SOT can be received from SIN directly.
When the serial test mode is enabled (SACSR:STST="1"), the SOT pin is fixed to "H", and the data input to the SIN
pin is ignored.
Figure 5-12 Serial Test Mode
SOT pin
SIN pin
H
SOT
Multi-function
serial interface
SIN
Note:
The serial test mode enable bit (SACSR:STST) can be changed only when transmission and reception are disabled
(SCR:TXE=RXE="0").
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5.2.12. UART Baud Rate Selection/Setting
This section explains the UART baud rate selection/setting.
The UART transmission/reception baud rate generator can be configured for the settings below.
Baud rate obtained when a dedicated baud rate generator (reload counter) divides
the frequency of the internal clock
There are two internal reload counters that correspond to the transmission and reception serial clocks, respectively.
The baud rate can be selected by setting a 15-bit reload value in the baud rate generator register (BGR).
The reload counter divides the internal clock with the set value.
To configure the clock source, select the internal clock (BGR:EXT=0).
Baud rate obtained when a dedicated baud rate generator (reload counter) divides
the frequency of the external clock
Use the external clock for the clock source of reload counter. The baud rate can be selected by setting a 15-bit reload
value in the baud rate generator register (BGR).
The reload counter divides the external clock with the set value.
To configure the clock source, select the external clock and the baud rate generator clock (BGR:EXT=1).
This mode is designed to accommodate the case where the division of an oscillator of a special frequency is used.
Notes:
Configure the external clock (EXT=1) after stopping the reload counter (BGR=15´ h00).
When an external clock (EXT=1) has been set, the "H" width and "L" width of the external clock should be set to 2
bus clocks or more.
Baud Rate Calculation
Set two 15-bit reload counters in the baud rate generator register (BGR).
The baud rate calculation formulas are as follows:
(1) Reload value
V=ϕ/b–1
V: Reload value
b: Baud rate
ϕ: Bus clock frequency, external clock frequency
(2) Example of calculation
Reload values when setting the bus clock frequency at 16 MHz, usage of internal clock, and baud rate at 19200 bps
are as follows:
Reload value:
V = (16 × 1,000,000) / 19200 – 1 = 832
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The baud rate is:
b = (16 × 1,000,000) / (832+1) = 19208 bps
(3) Baud rate error
The baud rate error can be obtained using the following formula:
Error (%) = (calculated value - desired value) / desired value × 100
(Example) Bus clock 20MHz, Target baud rate value 153600 bps
Reload value = (20 × 1,000,000) / 153600 - 1 = 129
Baud rate (calculated value) = (20 × 1,000,000) / (129 + 1) = 153846 bps
Error (%) = (153846 - 153600)/ 153600 × 100 = 0.16(%)
Notes:
Set the reload value to "0" to stop the reload counter.
If the reload value is an even number, the "L" width of the reception serial clock is 1 bus clock longer than "H"
width. If it is an odd number, the "H" and "L" widths of the serial clock are equal.
Set the reload value to 4 or higher. A normal data reception operation, however, could not be achieved due to some
baud rate error and reload value settings.
Allowed Baud Rate Error Range at Reception
This section explains the amount of the destination baud rate error that can be allowed at reception.
The baud rate error at reception should be set within the allowed error range by using following formula.
Figure 5-13 Allowed Baud Rate Range at Reception
UART
transfer rate
Sampling
▽
▽
Start
bit0
▽
bit1
▽
▽
bit7
Parity
▽
Stop
FL
1data·frame (11×FL)
Allowed minimum
transfer rate
Start
bit0
bit1
bit7
Parity
Stop
FLmin
Allowed maximum
transfer rate
Start
bit0
bit1
bit7
Parity
Stop
Flmax
As shown in the Figure the counter set by the BGR register will determine the sampling timing of the reception data
after having detected a start bit. A normal reception operation can be achieved if the last data (stop bit) have been
completed within this sampling timing.
In theory, the following is expected when this is applied to 11-bit reception.
If the margin of sampling timing is 1 clock of bus clock (ϕ), the allowed minimum transfer rate (FLmin) would be
calculated as follows.
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FLmin = (11bit × (V+1) – (V+1) / 2 +2) / ϕ = (21V+25) / 2ϕ (s)
V: Reload value
ϕ: Bus clock
Therefore, the allowed maximum baud rate (BGmax) at the destination would be calculated as follows.
BGmax = 11/FLmin = 22ϕ / (21V+25) (bps)
V: Reload value
ϕ: Bus clock
When receiving data at the allowed maximum transfer rate (FLmax), sampling is done in the starting point of receive
data in the 11th bit.
Therefore, the allowed maximum transfer rate (FLmax) is as follows.
10/11 × FLmax = (11bit × (V+1) – (V+1) / 2) / ϕ
FLmax= (21/20 × 11 × (V+1)) / ϕ (s)
V: Reload value
ϕ: Bus clock
When margin (ϕ) of the sampling timing is made two clocks, the allowed maximum transfer rate (FLmax) is as
follows:
FLmax = (21/20 × 11 × (V+1) – 2) / ϕ = (231V+191) / 20ϕ (s)
V: Reload value
ϕ: Bus clock
Therefore, the allowed minimum baud rate (BGmin) at the destination would be calculated as follows.
BGmin = 11 / FLmax = 220ϕ / (231V+191) (bps)
V: Reload value
ϕ: Bus clock
The allowed baud rate errors at UART and the destination can be obtained from above minimum/maximum baud rate
calculation formulas, the result of which are as follows.
Table 5-2 Allowed Baud Rate Error
Reload value
Allowed maximum baud
rate error
Allowed minimum baud rate error
3
0%
0%
10
2.98%
-3.24%
50
4.37%
-4.44%
100
4.56%
-4.60%
200
4.66%
-4.68%
32767
4.76%
-4.76%
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Note:
The accuracy of reception depends on the number of bits in a frame, bus clock, and the reload value. The higher the
bus clock and the division ratio are, the more accurate it will become.
Reload Values and Errors for Each Internal Clock (Peripheral Clock (PCLK)) and
Baud Rate
Table 5-3 Reload Values and Errors for Each Internal Clock (Peripheral Clock (PCLK)) and Baud Rate
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
32 MHz
Baud rate
(bps)
Value ERR Value ERR Value ERR Value ERR Value ERR Value ERR
4M
-
-
-
-
-
0
4
0
5
0
7
0
2.5M
-
-
-
0
-
-
-
-
-
-
-
-
2M
-
0
4
0
7
0
9
0
11
0
15
0
1M
7
0
9
0
15
0
19
0
23
0
31
0
500000
15
0
19
0
31
0
39
0
47
0
63
0
460800
-
-
-
-
-
-
-
-
51
-0.16
-
-
250000
31
0
39
0
63
0
79
0
95
0
127
0
230400
-
-
-
-
-
-
-
-
103
-0.16
-
-
153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
155
-0.16
207
-0.16
125000
63
0
79
0
127
0
159
0
191
0
255
0
115200
68
-0.64
86
0.22
138
0.88
173
0.22
207
-0.16
277
0.08
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
173
0.22
277
0.08
346
-0.16
416
0.08
555
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
346
TAEARH.ED14 to ED0
is disabled.
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Note:
The above-mentioned address is an offset of the word length.
The absolute address is calculated by adding the base address to the offset address where lower two bits were added.
(Absolute address) = (7FFE_0000H) + (Offset address set with TASARH + 2'b00)
4.25. TEST End Address Register AHB RAM : TAEARH
This section explains the bit structure of TEST End Address Register AHB RAM.
TEST end address register (TAEARH) specifies the end address of RAM diagnosis and initialization for AHB RAM.
TAEARH: Address 306CH (Access: Byte, Half-word, Word)
BIT
Initial values
Attributes
BIT
Initial values
Attributes
15
14
13
12
11
10
9
8
Reserved
ED14
ED13
ED12
ED11
ED10
ED9
ED8
0
1
1
1
1
1
1
1
R0, W0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15] Reserved
Reserved bit. These bits read out "0". Write "0" when writing.
[bit14 to bit0] ED14 to ED0: RAM diagnosis end address bits
These bits are used to specify the address with which the RAM diagnosis and initialization end for AHB RAM.
Note:
Setting of a value outside the AHB RAM area and a value that sets TASARH.ST14 to ST0 > TAEARH.ED14 to ED0
is disabled.
Note:
The above-mentioned address is an offset of the word length.
The absolute address is calculated by adding the base address to the offset address where lower two bits were added.
(Absolute address) = (7FFE_0000H) + (Offset address set with TAEARH + 2'b11)
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4.26. TEST Diagnosis Function Register AHB RAM : TTCRH
This section explains the bit structure of TEST Diagnosis Function Register AHB RAM.
The TEST diagnosis function register (TTCRH) specifies the RAM diagnosis content for AHB RAM, and holds the
diagnosis result and its status.
TTCRH: Address 3072H (Access: Byte, Half-word, Word)
BIT
15
14
13
12
11
10
Reserved
Initial values
Attributes
BIT
Initial values
Attributes
9
8
TSTAT
OVFLW
0
0
0
0
0
0
0
0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R, WX
R, WX
7
6
5
4
3
2
1
0
TEIE
TEI
TCIE
TCI
TTYP2
TTYP1
TTYP0
TRUN
0
0
0
0
1
1
0
0
R/W
R(RM1),W
R/W
R (RM1), W
R/W
R/W
R/W
R, WX
[bit15 to bit10] Reserved
Reserved bits. These bits read out "0". Write "0" when writing.
[bit9] TSTAT: RAM diagnosis error detection bit
TSTAT
Function
0
No error is detected with the RAM diagnosis
1
An error is detected with the RAM diagnosis
If an error occurs during RAM diagnosis for AHB RAM, this bit is set to "1".
This bit is initialized (cleared to "0") by hardware, using the RAM diagnosis start instruction as the trigger.
[bit8] OVFLW: RAM diagnosis error overflow bit
OVFLW
Function
0
During the RAM diagnosis, an error occurs in three or less addresses
1
During the RAM diagnosis, an error occurs in four or more addresses
If a RAM diagnosis error for AHB RAM occurs in four or more addresses, this bit is set to "1".
This bit is initialized (cleared to "0") by hardware, using the RAM diagnosis start instruction as the trigger.
[bit7] TEIE: Interrupt enable bit resulting from a diagnosis error
TEIE
Function
0
Prohibition of an interrupt resulting from a diagnosis error
1
Enabling of an interrupt resulting from a diagnosis error
This bit is used to enable an interrupt resulting from a RAM diagnosis error for AHB RAM.
"0": Prohibits an interrupt resulting from a RAM diagnosis error.
"1": Enables an interrupt resulting from a RAM diagnosis error. If TTCRH.TEI=1 is set and the RAM diagnosis
ends, the interrupt signal (RAM diagnosis error interrupt) is output.
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[bit6] TEI: Diagnosis error generation bit
TEI
Function
Read: No error occurrence during the RAM diagnosis.
0
Write: Flag clearing.
Read: Error occurred during the RAM diagnosis.
1
Write: No influence on the operation.
If TTCRH.TSTAT=1 is set when RAM diagnosis end for AHB RAM is detected, this bit is set to "1".
When "0" is written in this bit, it is cleared to "0". However, writing "1" to this bit is invalid and this bit holds the
previous value.
"1": Set TTCRH.TSTAT=1 when RAM diagnosis is ended.
"0": Set when "0" is written.
Note:
At read access of the read-modify-write instruction, "1" is always read.
[bit5] TCIE: Interrupt enable bit for a diagnosis end factor
TCIE
Function
0
Prohibition of an interrupt for the diagnosis end factor
1
Enabling of an interrupt for the diagnosis end factor
This bit is used to enable an interrupt for the RAM diagnosis end factor for AHB RAM.
"0": Prohibits an interrupt resulting from a RAM diagnosis end.
"1": Enables an interrupt resulting from a RAM diagnosis end. The interrupt signal (RAM diagnosis end interrupt)
is output with TTCRH.TCI= 1.
[bit4] TCI: Diagnosis end bit
TCI
Function
Read: The RAM diagnosis does not end.
0
Write: Flag clearing.
Read: The RAM diagnosis ended.
1
Write: No influence on the operation.
If RAM diagnosis end for AHB RAM is detected, this bit is set to "1".
When "0" is written in this bit, it is cleared to "0". However, writing "1" to this bit is invalid and this bit holds the
previous value.
"1": Set when a RAM diagnosis is ended. (It will not be set for forced termination by a key code)
"0": Set when "0" is written.
Note:
At read access of the read-modify-write instruction, "1" is always read.
[bit3 to bit1] TTYP2 to TTYP0: RAM diagnosis content indication bit
These bits are used to set the RAM diagnosis type for AHB RAM to be executed.
The RAM diagnosis types are executed in the following order.
1. Unique (unique data is {Address [3:0],{6{Address [7:0]}}})
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2. Checker
3. March (all "0" -> all "1" are executed in that order.)
These bits are used to determine whether or not each type is executed.
TTYP2
TTYP1
TTYP0
Function
1
1
0
Execution of unique and checker
1
Execution of march
1
Execution of checker
1
Execution of unique
By default, the unique and checker diagnoses are executed (110B). However, to change the RAM diagnosis content,
be sure to specify this change before the RAM diagnosis operation start instruction.
If march is executed last, the RAM content is all "1".
[bit0] TRUN: RAM diagnosis operation status bit
TRUN
Function
0
The RAM diagnosis is stopping
1
The RAM diagnosis is in progress
This bit is used to set or hold the RAM diagnosis status for AHB RAM.
"1": Set when a RAM diagnosis is started by the key code setting.
"0": Set when all diagnoses are complete or forcibly terminated by the key code.
4.27. TEST Initialization Function Register AHB RAM : TICRH
This section explains the bit structure of TEST Initialization Function Register AHB RAM.
The TEST initialization function register (TICRH) specifies the RAM initialization content, and holds the
initialization result and its status for AHB RAM.
TICRH: Address 3071H (Access: Byte, Half-word, Word)
BIT
7
6
5
4
Reserved
Initial values
Attributes
3
2
1
0
ICIE
ICI
ITYP
IRUN
0
0
0
0
0
0
0
0
R0, W0
R0, W0
R0, W0
R0, W0
R/W
R (RM1),
W
R/W
R, WX
[bit7 to bit4] Reserved
Reserved bits. These bits read out "0". Write "0" when writing.
[bit3] ICIE: Interrupt enable bit for a RAM initialization end factor
ICIE
Function
0
Prohibition of an interrupt for a RAM initialization end factor
1
Enabling of an interrupt for a RAM initialization end factor
This bit is used to enable an interrupt for the RAM initialization end factor for AHB RAM.
"0": Prohibits an interrupt resulting from a RAM initialization end.
"1": Enables an interrupt resulting from a RAM initialization end. The interrupt signal (RAM initialization
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complete interrupt) is output with TICRH.ICI= 1.
[bit2] ICI: RAM initialization end bit
ICI
Function
Read: The RAM initialization does not end.
0
Write: Flag clearing.
Read: The RAM initialization ended.
1
Write: No influence on the operation.
If RAM initialization end for AHB RAM is detected, this bit is set to "1".
When "0" is written in this bit, it is cleared to "0". However, writing "1" to this bit is invalid and this bit holds the
previous value.
"1": Set when a RAM initialization is ended. (It will not be set for forced termination by a key code)
"0": Set when "0" is written.
Note:
At read access of the read-modify-write instruction, "1" is always read.
[bit1] ITYP: RAM initialization content indication bit
ITYP
Function
0
Initialization to All "0"
1
Initialization to All "1"
This bit is used to set the type to be executed during RAM initialization for AHB RAM.
"0": Initializes to all "0".
"1": Initializes to all "1".
[bit0] IRUN: RAM initialization operation status bit
IRUN
Function
0
RAM Initialization is stopping
1
RAM Initialization is in progress
This bit is used to set or hold the RAM initialization status for AHB RAM.
"1": Set when RAM initialization is started by the key code setting.
"0": Set when all initialization is completed or forcibly terminated by the key code.
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4.28. TEST Software Reset Generation Control Register AHB
RAM : TSRCRH
This section explains the bit structure of TEST Soft Reset Generation Control Register AHB RAM.
The TEST software reset generation control register (TSRCRH) specifies the generation of the software reset for
initializing internal circuits for AHB RAM's RAM diagnosis.
TSRCRH: Address 3074H (Access: Byte, Half-word, Word)
BIT
7
6
5
4
SRST
Initial values
Attributes
3
2
1
0
Reserved
0
0
0
0
0
0
0
0
R0, W
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
[bit7] SRST: Software reset enabling bit
SRST
Function
0
Prohibition of a software reset
1
Enabling of a software reset
This bit is used to enable a software reset for the internal circuit for RAM diagnosis for AHB RAM.
This bit reads out "0".
"1": Reset pulses occur for 4τ only and the internal circuit for RAM diagnosis except this register is reset.
: Peripheral clock
[bit6 to bit0] Reserved
Reserved bits. These bits read out "0". Write "0" when writing.
4.29. TEST Fake Error Generation Control Register AHB RAM :
TFECRH
This section explains the bit structure of TEST Fake Error Generation Control Register AHB RAM.
TEST fake error generation control register (TFECRH) generates a fake error in RAM diagnosis operation for AHB
RAM. You can specify RAM diagnosis operations for which you want to generate an error.
TFECRH: Address 3070H (Access: Byte, Half-word, Word)
BIT
7
6
5
4
Reserved
Initial values
Attributes
3
2
1
0
FERR
ETYP2
ETYP1
ETYP0
0
0
0
0
0
0
0
0
R0, W0
R0, W0
R0, W0
R0, W0
R/W
R/W
R/W
R/W
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[bit7 to bit4] Reserved
Reserved bits. These bits read out "0". Write "0" when writing.
[bit3] FERR: Fake error enable bit for RAM diagnosis
FERR
Function
0
Prohibition of a fake error (normal operation)
1
Enabling of a fake error
This bit is used to enable a fake error for RAM diagnosis for AHB RAM.
"0": Prohibits a fake error. (normal operation)
"1": Enables a fake error. Data write including intentional error is enabled following ETYP2 to ETYP0.
[bit2 to bit0] ETYP2 to ETYP0: Fake error process specification bits
These bits are used to specify a process to generate a fake error.
ETYP2
ETYP1
ETYP0
1
1
-
1
-
Process to generate a fake error
March diagnosis
Checker diagnosis
Unique diagnosis
4.30. TEST Key Code Control Register AHB RAM : TKCCRH
This section explains the bit structure of TEST Key Code Control Register AHB RAM.
The TEST key code control register (TKCCRH) is used to start or forcibly terminate the RAM diagnosis or
initialization for AHB RAM.
TKCCRH: Address 3077H (Access: Byte, Half-word, Word)
BIT
Initial values
Attributes
7
6
5
4
3
KEY1
KEY0
0
0
0
0
0
R0, W
R0, W
R0, W0
R0, W0
R0, W0
2
1
0
CODE1
CODE0
0
0
0
R0, W0
R/W
R/W
Reserved
[bit7, bit6] KEY1, KEY0: Key code control bits
Key code control bits. Set the operation instruction content to CODE[1:0] (no change during operation) and perform
the operation.
The procedure is:
1. 00 -> 01 -> 10 -> 11 : Write in this order.
2. Same values in CODE[1:0].
3. Different operations (access or read other registers for RAM diagnosis, or continuous write in the different order
other than the above) within the procedure will be invalid.
Note:
The key code process will be continued even if any access to the registers in the RAMECC is made in the procedure.
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[bit5 to bit2] Reserved
Reserved bits. These bits read out "0". Write "0" when writing.
[bit1, bit0] CODE1, CODE0: RAM diagnosis/initialization control bits
These bits specify operational direction for the key code procedure above.
CODE1, CODE0
Function
00
Forced termination
01
Initialization start
10
Diagnosis start
11
Setting prohibited
If this value is changed or set to "11" during operating the key code above, the key code procedure itself will be
invalid.
5. Operation
This section explains the Operation of RAM diagnosis.
5.1 RAM Diagnosis
5.2 RAM Initialization
5.3 Interrupt-Related Register
5.4 RAM Diagnosis Fake Error Generation Procedure
5.5 Number of Required Cycles
5.6 Note
5.1.
RAM Diagnosis
This section explains the RAM diagnosis.
XBS RAM diagnosis is performed only in the following order.
1. Unique (unique data is {Address [3:0],{6{Address [7:0]}}})
2. Checker
3. March (all "0" -> all "1" are executed in that order.)
The RAM diagnosis is performed following the settings in the TTYP[2:0] bits of the TEST diagnosis function register
(TTCRX). By default, unique and checker are executed.
The coverage of the RAM diagnosis for XBS RAM is specified by the TEST start address register (TASARX) and
TEST end address register (TAEARX).
Following procedure is required for RAM diagnosis for XBS RAM.
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1. Before start diagnosing, read TRUN of the TEST diagnosis function register (TTCRX) and IRUN of the TEST
initialization function register (TICRX), and check that they are "0".
In the case where TTCRX.TRUN or TICRX,IRUN is not "0":
Wait for TTCRX.TRUN="0", then clear TTCRX.TCI.
Wait for TICRX.IRUN="0", then clear TICRX.ICI.
2. Write continuously "02H" -> "42H" -> "82H" -> "C2H" to the TEST key code control register (TKCCRX), then
start diagnosing.
When all RAM diagnosis types for XBS RAM are completed, TRUN bit of the TEST diagnosis function register
(TTCRX) becomes "0" to finish the RAM diagnosis. The results of the diagnosis is retained in the TEST error address
register 0 to 2 (TEAR0X to TEAR2X) and TEST diagnosis function register (TTCRX). The RAM holds the diagnosis
data.
In addition, write continuously "00H" -> "40H" -> "80H" -> "C0H" to the TEST key code control register (TKCCRX)
to terminate the RAM diagnosis for XBS RAM forcibly. RAM diagnosis ends even if it is in progress. In this case, the
diagnosis result is not reliable.
Perform the same procedure for RAM diagnosis for Backup RAM and AHB RAM.
5.2.
RAM Initialization
This section explains the RAM initialization.
Only either of the following RAM initialization operation types for XBS RAM is specified with the ITYP bit of the
TEST initialization function register (TICRX).
Write all "0" (default)
Write all "1"
ECC area has the values depending on the written values.
The coverage of the RAM initialization for XBS RAM is specified by the TEST start address register (TASARX) and
TEST end address register (TAEARX).
Following procedure is required for XBS RAM's RAM diagnosis.
1. Before start diagnosing, read TRUN of the TEST diagnosis function register (TTCRX) and IRUN of the TEST
initialization function register (TICRX), and check that they are "0".
In the case where TTCRX.TRUN or TICRX,IRUN is not "0":
Wait for TTCRX.TRUN="0", then clear TTCRX.TCI.
Wait for TICRX.IRUN="0", then clear TICRX.ICI.
2. Write continuously "01H" -> "41H" -> "81H" -> "C1H" to the TEST key code control register (TKCCRX), then
start diagnosing.
When RAM initialization is completed, IRUN bit of the TEST initialization function register (TICRX) becomes "0"
to finish the RAM initialization.
In addition, write continuously "00H" -> "40H" -> "80H" -> "C0H" to the TEST key code control register (TKCCRX)
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to terminate the RAM initialization forcibly. RAM initialization ends even if it is in progress. In this case, the
initialization results is not guaranteed.
Perform the same procedure for RAM diagnosis for Backup RAM and AHB RAM.
5.3.
Interrupt-Related Register
This section explains the interrupt-related register.
To generate an interrupt, write "1" to the interrupt generation enabling bits (TEIE, TCIE, and ICIE) according to the
purposes, and set the RAM diagnosis interrupt vector and RAM diagnosis interrupt level.
Interrupt factor
TTCRX.TEI
(RAM diagnosis error interrupt)
TTCRX.TCI
(RAM diagnosis end interrupt)
TICRX.ICI
(RAM initialization complete interrupt)
TTCRA.TEI
(Backup RAM diagnosis error interrupt)
TTCRA.TCI
(Backup RAM diagnosis end interrupt)
TICRA.ICI
(Backup RAM initialization complete
interrupt)
TTCRH.TEI
(AHB RAM diagnosis error interrupt)
TTCRH.TCI
(AHB RAM diagnosis end interrupt)
TICRH.ICI
(AHB RAM initialization complete
interrupt)
Interrupt vector
Interrupt level
#35(000FFF70H)
ICR19(0453H)
#35(000FFF70H)
ICR19(0453H)
#35(000FFF70H)
ICR19(0453H)
#35(000FFF70H)
ICR19(0453H)
#35(000FFF70H)
ICR19(0453H)
#35(000FFF70H)
ICR19(0453H)
#35(000FFF70 H)
ICR19(0453 H)
#35(000FFF70 H)
ICR19(0453 H)
#35(000FFF70 H)
ICR19(0453 H)
For details of the interrupt levels and interrupt vectors, see "CHAPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
The interrupt request flags (TEI, TCI, ICI) are not automatically cleared. So, to clear them, use software before return
from interrupt processing. (Write "0" in the TEI, TCI, and ICI bits.)
5.4.
RAM Diagnosis Fake Error Generation Procedure
This section explains the RAM diagnosis fake error generation procedure.
This function intentionally generates fake errors for software debugging.
Set the RAM diagnosis fake error generation for XBS RAM as following procedure:
1. Specify the error type with the TEST fake error generation control register (TFECRX).
(1) Set a diagnosis pattern to the TFECRX.ETYP[2:0] to generate a fake error.
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(2)
Specify a diagnosis pattern to generate a fake error by writing TFECRX.FERR="1".
2. Set the diagnosis start with the TEST diagnosis function register (TTCRX).
(1) Set a diagnosis pattern to operate with the TTCRX.TTYP[2:0].
(2) Write continuously "02H" -> "42H" -> "82H" -> "C2H" four times to the TEST key code control
register (TKCCRX), then start diagnosis pattern (See "5.1. RAM Diagnosis")
Perform the same procedure for RAM diagnosis for Backup RAM and AHB RAM.
5.5.
Number of Required Cycles
This section explains the number of required cycles.
The following shows the estimation of the cycle count required for various RAM diagnosis and initialization for XBS
RAM, Backup RAM.
XBS RAM : 192kByte = 48k word address
Backup RAM : 16kByte = 4k word address
AHB RAM : 128kByte = 32k word address (MB91F528)
(1) "RAM diagnosis (unique)"
Write (1 cycle)
Read 1 (1 cycle)
Read 2 (1 cycle)
The processes above exist for each word address, and a set of these processes exists for a portion equivalent to all
word addresses, and the entire number of cycles is as follows:
(
1
Write
+
1
Read 1
+
1
)x
Read 2
49152(48k)
Word
+1
=
147457
Total
(2) "RAM diagnosis (checker)"
Write 1 (1 cycle) : W1
Read 1 (1 cycle) : R1
The processes above exist for each word address, and a set of these processes exists for a portion equivalent to all
word addresses. To perform the partial write function diagnosis, five write processes and four read processes are
provided for each word address. So, the following is obtained.
Write 2 (1 × 5 cycles) : W2
Read 2 (2 × 4 cycles) : R2
Moreover, the same processing is repeated with data different from above data. The entire number of cycles is as
follows:
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((
1
+
1
W1
)x
R1
49152(48k)
+1
+
5
Word
+
W2
8
)x
2
R2
=
Repetition
196636
Total
(3) "RAM diagnosis (march)"
Write (1 × 3 cycles)
Read (2 × 2 cycles)
This diagnosis has 3 writes and 2 reads per a word address so that the processes above exist for each word address,
and a set of these processes exists for a portion equivalent to all word addresses, Moreover, the same processing is
repeated with data different from above data. So, the entire number of cycles is as follows:
(
3
+
4
Write
)x
49152(48k)
Read
x
Word
2
=
Repetition
688128
Total
(4) "RAM initialization"
Write (1 cycle)
The processes above exist for each word address, and a set of these processes exists for a portion equivalent to all
word addresses, The entire number of cycles is as follows:
1
x
Write
49152(48k)
Word
=
49152
Total
The time required for 192kByte RAM diagnosis of 2MHz and 80MHz operations is obtained as follows:
Table 5-1 Time Required for RAM Diagnosis and Initialization for 192kByte
Unique
Checker
March
Initialization
Number of cycles
2[MHz]
(=500[ns])
80MHz
(=12.5[ns])
Total
147457
73728.5[μs]
196636
98318[μs]
688128
344064[μs]
49152
24576[μs]
1081373
540[ms]
1843.2[μs]
2457.9[μs]
8601.6[μs]
614.4[μs]
13.5[ms]
Moreover, the time required for the diagnosis with initial register values is obtained as follows:
Table 5-2 Time Required of Diagnosis (Initial Setting) after Power-on Reset is Released (192kByte)
Unique
Checker
Total
Number of cycles
2[MHz]
(=500[ns])
147457
73728.5[μs]
196636
98318[μs]
344093
172[ms]
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5.6.
Note
This section explains the note.
Accessing to RAM is prohibited during RAM diagnosis or during initialization.
RAM diagnosis and initialization cannot be used during debugging with the on-chip debugger (OCD).
While performing diagnostic or initialization process, start setting is ignored and the currently running process will
continue. To start anything, perform steps below to make sure that no operation is being performed.
1. Make sure that all of TTCR:TRUN, TICR and IRUN are "0".
2. Start the key code operation with TKCCR (TKCCRX and TKCCRA) for diagnosis or initialization.
Forced termination can be performed by key code operation. Perform as shown below.
Input "00H"-> "40H"-> "80H"-> "C0H" to TKCCR continuously.
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Chapter 54: Timing Protection Unit
This chapter explains the Timing Protection Unit.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
Code : FR81S10_TPU-1v1-91528-2-E
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Chapter 54: Timing Protection Unit
1. Overview
This section explains the overview of the Timing Protection Unit.
Timing Protection Unit (TPU) is a timer that OS uses for the ensuring safety of the system by the watch of the time of
Task/ISR. The control target that OS supervises is as follows.
Resource lock time
Global interrupt lock time
Task/ISR dead line
Task/ISR runtime
Inter-arrival time (Interrupt Frequency)
The control registers can be accessed only in a privileged mode because the built-in timers of TPU are controlled by
OS, and the controls are all programmable.
2. Features
This section explains features of the Timing Protection Unit.
Count with system clock (HCLK)
Built-in timers. Max: 8 timers
24-bit Up-counter
Two operational modes of Normal/Overflow
Normal Mode: When a count value is exceeded to the setting value, interrupt is generated.
Overflow Mode: The interrupt is generated by the counter overflow.
Automatic restart function
Global prescaler (division factor 1/1 to 1/64)
Prescaler by timer (1, 1/2, 1/4, 1/16)
Reading function of counter value
Software control of Start/ Stop/ Continue
Status display of each timer (stopped/ active)
Debug mode support
Access protection function of TPU control register
3. Configuration
This section explains the configuration of the Timing Protection Unit.
There is no block diagram.
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Chapter 54: Timing Protection Unit
4. Registers
This section explains registers of the Timing Protection Unit.
For all registers, writing is permitted only for privileged mode/debugging access.
The area of 0x00000900-0x00009FF is TPU register area. The area not shown in the following is all reserved.
Table 4-1 Registers Map
Address
Registers
+0
0x0900
0x0904
+1
+2
+3
TPUUNLOCK
TPULST
0x0908
Reserved
TPUVST
Register function
TPU Unlock Register
Reserved
TPUCFG
TPU Lock Status Register
TPU Configuration Register
0x090C
TPUTIR
Reserved
Reserved
Reserved
TPU Timer Interrupt Request Register
0x0910
TPUTST
Reserved
Reserved
Reserved
TPU Timer Status Register
0x0914
TPUTIE
Reserved
Reserved
Reserved
TPU Timer Interrupt Enable Register
0x0918
TPUTMID
TPU Module ID Register
0x0930
TPUTCN00
TPU Timer Control Register 0 ch.0
0x0934
TPUTCN01
TPU Timer Control Register 0 ch.1
0x0938
TPUTCN02
TPU Timer Control Register 0 ch.2
0x093C
TPUTCN03
TPU Timer Control Register 0 ch.3
0x0940
TPUTCN04
TPU Timer Control Register 0 ch.4
0x0944
TPUTCN05
TPU Timer Control Register 0 ch.5
0x0948
TPUTCN06
TPU Timer Control Register 0 ch.6
0x094C
TPUTCN07
TPU Timer Control Register 0 ch.7
0x0950
TPUTCN10
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.0
0x0954
TPUTCN11
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.1
0x0958
TPUTCN12
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.2
0x095C
TPUTCN13
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.3
0x0960
TPUTCN14
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.4
0x0964
TPUTCN15
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.5
0x0968
TPUTCN16
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.6
0x096C
TPUTCN17
Reserved
Reserved
Reserved
TPU Timer Control Register 1 ch.7
0x0970
TPUTCC0
TPU Timer Current Count Register ch.0
0x0974
TPUTCC1
TPU Timer Current Count Register ch.1
0x0978
TPUTCC2
TPU Timer Current Count Register ch.2
0x097C
TPUTCC3
TPU Timer Current Count Register ch.3
0x0980
TPUTCC4
TPU Timer Current Count Register ch.4
0x0984
TPUTCC5
TPU Timer Current Count Register ch.5
0x0988
TPUTCC6
TPU Timer Current Count Register ch.6
0x098C
TPUTCC7
TPU Timer Current Count Register ch.7
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4.1.
TPU Unlock Register : TPUUNLOCK
The bit configuration of TPU unlock register is shown below.
TPUUNLOCK : Address 0900H (Access : Word)
bit31
bit0
UNLOCK[31:0]
Initial value
0000
0000
0000
0000
Attribute
0000
0000
0000
0000
R0,W
This register is used to specify access prohibition/permission to the TPU control register (TPUCFG and TPUTCN1n
(n: timer channel number)).
It is required to prevent the illegal update of TPU control registers due to the malfunction of system.
Writing to this register is permitted only at the privileged mode. The readout value is always "0".
Be sure to keep access within 32-bit width (word) because Lock/Unlock is judged with 32-bit.
[bit31 to bit0] UNLOCK[31:0] : LOCK/UNLOCK value
If present value of UNLCOK is written to the register, access to the TPU control register is permitted.
To prohibit accessing, write the values other than a present value of UNLOCK.
4.2.
TPU Lock Status Register : TPULST
The bit configuration of TPU lock status register is shown below.
TPULST : Address 0904H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
Reserved
Initial value
Attribute
bit0
LST
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R,WX
This register is used to indicate the lock status of TPU.
This register is read only, and writing to the register has no influence in operation.
[bit7 to bit1] (Reserved) : (Reserved bit)
These bits are reserved bits. When writing to those bits, "0" must be set. The readout value is always "0".
[bit0] LST (Lock Status) : Lock status display
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This bit indicates whether access to the TPU control register is locked.
LST
Lock Status
0
1
4.3.
Access permission
Access prohibition
TPU Access Violation Status Register : TPUVST
The bit configuration of TPU access violation status register is shown below.
TPUVST : Address 0906H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
IULST
ULVST
AVST
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R,W0
An illegal access to the TPU register is detected, and the factor is maintained. When an illegal access to the register is
detected, the corresponding bit of the detected violation factor is set, and it is processed as an illegal instruction
exception.
Writing to this register is permitted only at the privileged mode.
[bit7 to bit3] (Reserved) : (Reserved bit)
These bits are reserved bits. When writing to those bits, "0" must be set. The readout value is always "0".
[bit2] IULST (Illegal Unlock Access Status) : Illegal unlock operation detection
When an illegal unlock access is detected, this bit becomes "1". Writing to this bit is effective only the value is "0".
When a value other than the value set for UNLOCK is written in the TPUUNLOCK register in privileged mode when
TPU control register access is prohibited (TPULST.LST=1) (including cases other than word access), an illegal
unlock operation is detected.
[bit1] ULVST (Unlock Access Violation Status) : Control register access violation detection while access
prohibiting
When writing in TPU control register (TPUCFG, TPUTCN1n) is detected while prohibiting the TPU control register
access, this bit becomes "1". Only when "0" is written, it becomes effective.
When there is a write operation to TPUCFG, TPUTCN1n in privileged mode when TPU control register access is
prohibited (TPULST.LST=1), an illegal access is detected.
[bit0] AVST (Access Violation Status) : Access violation detection
When the access violations other than IULST and ULVST are detected, this bit becomes "1". Only when "0" is
written, it becomes effective. It concretely becomes a register access by the instruction fetch.
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4.4.
TPU Configuration Register : TPUCFG
The bit configuration of TPU configuration register is shown below.
TPUCFG : Address 0908H (Access : Byte, Half-word, Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
Reserved
Initial value
bit24
DBGE
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
GLBPSE
Reserved
0
0
0
0
0
0
0
0
R/W
R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Attribute
Initial value
Attribute
GLBPS[5:0]
Reserved
Initial value
Attribute
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Initial value
0
0
0
Attribute R0,W0
R0,W0
R0,W0
It is a register that controls the entire TPU.
INTE
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
[bit31 to bit25] (Reserved) : (Reserved bit)
These bits are reserved bits. Be sure to write "0". The readout value is "0".
[bit24] DBGE (Debug Mode Enable) : Debug mode transition
This bit is used to control transition to debug mode.
When debug mode is permitted, all timers stop operating. Each timer restarts operation when coming off debug mode.
DBGE
2074
Debug Mode
0
All timer operation permission (Normal mode)
1
All timer operation suppression (Debug mode)
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[bit23] GLBPSE (Global Prescaler Enable) : Global prescaler operation permission
The operation of global prescaler is controlled. When the operation is prohibited, all timers do not perform count
operation.
GLBPSE
Global Prescaler
0
Operation prohibition
1
Operation permission
[bit22] (Reserved) : (Reserved bit)
This is a reserved bit. Be sure to write "0". The readout value is "0".
[bit21 to bit16] GLBPS[5:0] (Global Prescaler Bits) : Global prescaler frequency setting
These bits are used to specify the frequency of the clock that supplied to all timers in common. Update of the bits has
to be done when TPUCFG.GLBPSE=0 (timer operation disabled).
In TPU, the system clock (HCLK) is divided with global prescaler and the clock is supplied to each timer.
GLBPS[5:0] indicates the value of dividing frequency as it is.
GLBPS[5:0]
Global Prescaler Output
000000
000001
000010
…
111111
HCLK / 1
HCLK / 2
HCLK / 3
…
HCLK / 64
[bit15 to bit1] (Reserved) : (Reserved bit)
These bits are reserved bits. Be sure to write "0". The readout value is "0".
[bit0] INTE (TPU Interrupt Enable) : TPU interrupt enable
This bit is used to enable the interrupt request from TPU.
INTE
TPU Interrupt
0
Interrupt disable
1
Interrupt enable
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4.5.
TPU Timer Interrupt Request Register : TPUTIR
The bit configuration of TPU timer interrupt request register is shown below.
TPUTIR : Address 0090CH (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IR[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
This register indicates interrupt request status from each timer in TPU . This register is read only. Writing to the
register causes no influence in operation.
[bit7 to bit0] IR[7:0] (Interrupt Request) : Interrupt request
These bits indicate presence of the interrupt request for each channel. These bits show that there is an interrupt
request factor regardless of timer interrupt enable register (TPUTIE). The requests are actually used as interrupt
requests only when they are from channels where TPUTIE is effective.
Bit 0 to 7 corresponds to channel 0 to 7 respectively.
IRn
Interrupt Request
0
Ch.n no Interrupt request
1
(n = 0 to 7)
4.6.
Ch.n Interrupt request
TPU Timer Status Register : TPUTST
The bit configuration of TPU timer status register is shown below.
TPUTST : Address 00910H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TS[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
This register indicates the operation status of each timer in TPU. This register is read only. Writing to the register
causes no influence in operation.
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[bit7 to bit0] TS[7:0] (Timer Status) : Timer operation status
These bits indicate timer operation status of each channel.
Bit 0 to 7 corresponds to channel 0 to 7 respectively.
TSn
Operation Status
0
Ch.n Stopped
1
(n = 0 to 7)
4.7.
Ch.n Operating
TPU Timer Interrupt Enable Register : TPUTIE
The bit configuration of TPU timer interrupt enable register is shown below.
TPUTIE : Address 00914H (Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IE[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register is used to enable interrupt of each timer in TPU.
[bit7 to bit0] IE[7:0] (Interrupt Enable): Timer interrupt enable
These bits are used to enable timer interrupt request for each channel.
Bit 0 to 7 corresponds to channel 0 to 7 respectively.
IEn
0
1
(n = 0 to 7)
Interrupt enable
Ch.n Interrupt disable
Ch.n Interrupt enable
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4.8.
TPU Module ID Register : TPUTMID
The bit configuration of TPU module ID register is shown below.
TPUTMID : Address 00918H (Access : Byte, Half-word, Word)
bit31
bit0
MID[31:0]
Initial value
0000
0000
0000
0000
Attribute
0000
0000
0000
0000
R,WX
This register is used to indicate the TPU module ID. It is read only. Writing to the register causes no influence in
operation.
It is used to identify the function of built-in TPU. In the OS, it is used to distinguish the type of TPU.
4.9.
TPU Timer Control Register 00 to 07 : TPUTCN00 to 07
The bit configuration of TPU timer control register 00 to 07 is shown below.
TPUTCN00 to TPUTCN07 : Address 00930H to 0094CH (Access : Byte, Half-word,
Word)
Initial value
Attribute
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
START
STOP
CONT
IES
IEC
IRC
0
0
0
0
0
0
0
0
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W0
R0,W0
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Reserved
ECPL[23:16]
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECPL[15:8]
Initial value
Attribute
2078
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Chapter 54: Timing Protection Unit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ECPL[7:0]
Initial value
Attribute
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
It is a control register of each timer.
[bit31] START (Start) : Timer operation start
This bit is used to instruct to start the timer operation. The timer operation is started to write "1" to this bit. The
readout value is always "0".
When operation is started by this bit at a normal mode, the timer starts counting from "0".
When operation is started by this bit at the overflow mode, the timer starts counting from "0" or
ECPL[23:0](TPUTCN1n.PL=1).
Writing "0" to the bit causes no influence in operation.
[bit30] STOP (Stop) : Timer operation stop
This bit is used to instruct to stop the timer operation. The timer operation is stopped to write "1" to this bit.
The readout value is always "0". Writing "0" to the bit causes no influence in operation.
[bit29] CONT (Continue) : Timer operation restart
This bit is used to instruct to restart the timer operation. The readout value is always "0".
When the operation is restarted by this bit, operation is restarted from the count value that has stopped.
When START, STOP, and the CONT bit are set at the same time, priority is judged in order of START > CONT >
STOP.
Writing "0" to the bit causes no influence in operation.
[bit28] IES (Interrupt Enable Set) : Interrupt enable bit Set
This bit is used to instruct to set timer interrupt enable. The interrupt enable bit (TPUTIE.IE[n]) is set by writing "1"
in this bit.
The readout value is always "0". Writing "0" to the bit causes no influence in operation.
[bit27] IEC (Interrupt Enable Clear) : Interrupt enable bit clear
This bit is used to instruct to clear timer interrupt enable. The interrupt enable bit (TPUTIE.IE[n]) is cleared by
writing "1" in this bit.
The readout value is always "0". Writing "0" to the bit causes no influence in operation.
[bit26] IRC (Interrupt Request Clear) : Interrupt request bit clear
This bit is used to instruct timer interrupt clear request . The interrupt request bit (TPUIR.IR[n]) is cleared by writing
"1" to this bit.
The readout value is always "0". Writing "0" to the bit causes no influence in operation.
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[bit25, bit24] (Reserved) : (Reserved bit)
These bits are reserved bit. Be sure to write "0". The readout value is "0".
[bit23 to bit0] ECPL[23:0] (End Count or Pre-load) : Counter End value or pre load value
The value used as the end value or pre-load value of the counter is set.
ECPL[23:0] is used as the end value of the counter in the normal mode.
ECPL[23:0] is used as pre-load value in the overflow mode.
4.10. TPU Timer Control Register 10 to 17 : TPUTCN10 to 17
The bit configuration of TPU timer control register 10 to 17 is shown below.
TPUTCN10 to TPUTCN17 : Address 00950H to 0096CH (Access : Byte, Half-word,
Word)
bit7
bit6
bit5
Reserved
Initial value
Attribute
bit4
bit3
bit2
PL
FRT
TMOD
bit1
bit0
PS[1:0]
0
0
0
0
0
0
0
0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
R/W
R/W
It is a control register for each timer.
[bit7 to bit5] (Reserved) : (Reserved bit)
These bits are reserved bit. Be sure to write "0". The readout value is "0".
[bit4] PL (Pre-load) : Pre-Load instructions
This bit is used to specify pre-load of ECPL[23:0] when the timer operation is started. This bit is effective when the
timer is in the overflow mode.
PL
Pre-load
0
Pre-load invalid
1
Pre-load valid
[bit3] FRT (Free-Running Timer) : Free-Running Timer instructions
This bit is used to instruct free-run operation. It is effective in both normal mode/overflow mode.
After the interrupt is generated by the end value of the counter, the count is restarted from "0" automatically when this
bit is made effective in the normal mode.
After the interrupt is generated by the counter overflow, the count is restarted from "0" (TPUTCN1n.PL=0) or
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ECPL[23:0] (TPUTCN1n.PL=1) automatically when this bit is made effective in the overflow mode.
FRT
Free-run
0
Free-run invalid
1
Free-run valid
[bit2] TMOD (TPU Mode) : TPU operation mode
This bit is used to specify TPU operation mode. In the operation mode of the timer, there is the normal mode in which
the count is incremented from "0" to ECPL[23:0], or the overflow mode in which the count is started from "0"
(TPUTCN1n.PL=0) or ECPL[23:0] (TPUTCN1n.PL=1) and the counter overflow is detected.
TMOD
Timer Operation Mode
0
Normal mode
1
Overflow mode
[bit1, bit0] PS[1:0] (Individual Prescaler) : Timer prescaler setting
The prescaler value of each timer is set. The output of global prescaler is input to each timer, and this input is divided
and used as the operating frequency of each timer.
PS[1:0]
Prescaler
00
01
10
11
1/1
1/2
1/4
1/16
4.11. TPU Timer Current Count Register 0 to 7 : TPUTCC0 to 7
The bit configuration of TPU timer current count register 0 to 7 is shown below.
TPUTCC0 to TPUTCC7 : Address 00970H to 0098CnH (Access : Byte, Half-word,
Word)
bit31
bit24
bit23
bit0
Reserved
Initial value
Attribute
0000
0000
R0,W0
R0,W0
TCC[23:0]
0000
0000
0000
0000
0000
0000
R,WX
This register indicates the present counter value of the timer. This register is read only.
[bit31 to bit24] (Reserved) : (Reserved bit)
These bits are reserved bit. Be sure to write "0". The readout value is "0".
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[bit23 to bit0] TCC[23:0] (Timer Current Count) : Timer Count value
These bits indicate the present counter value.
5. Operation
This section explains the operation.
5.1 TPU Control Register Access Protection
5.2 Global Prescaler
5.3 Interrupt Control
5.4 Timer Operation
5.5 Free-run Function
5.6 Individual Prescaler Function
5.7 Debug Support Function
5.8 Operation Flow
5.1.
TPU Control Register Access Protection
This section explains the TPU control register access protection.
The TPU register is permitted to be accessed only in the privileged mode because all TPU registers are the system
registers. The illegal instruction exception (data access error) is generated if accessing it in the user mode.
The TPU register not only has a function for access protection as the system register, it also has a function for register
access protection with the Lock code to prevent writing of the TPU control register as a result of malfunctioning.
The target registers of the access protection are the following two registers.
TPU configuration register (TPUCFG)
TPU timer control register 10 to 17 (TPUTCN 10 to 17)
To make the TPU configuration register access protection effective, write the values other than a present set value of
UNLOCK[31:0] in the TPU unlock register (TPUUNLOCK). When the access protection function becomes effective,
the LST bit of the TPU lock status register is set to indicate the lock state.
When writing it in the control register of the protection target, write the value set last time in UNLOCK[31:0]. It
becomes TPULST.LST=0 and the unlock state when the lock is released.
After generating reset, the register access protection function in the invalid state (TPULST.LST=0).
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Chapter 54: Timing Protection Unit
When the TPU control register access protection function is effective(TPULST.LST=1), and when the values other
than UNLOCK[31:0] are written in TPU unlock register (TPUUNLOCK), the error reply is returned to AHB and the
data access error is generated in CPU as an illegal access.
Then, the violation factor is set in the TPU access violation detection register (TPUVST.IULST=1) .
When the TPU control register access protection function is effective(TPULST.LST=1), and when there is a write
request to the TPU control register (TPUCFG) and TPU timer control register (TPUTCFG1n), the data access error is
generated in CPU as an illegal access.
Then, the violation factor is set in the TPU access violation detection register (TPUVST.ULVST =1) .
Moreover, it is judged that the access by the instruction fetch is a malfunction and generates the illegal instruction
exception. Then, it becomes TPUVST.AVST=1.
5.2.
Global Prescaler
This section explains the global prescaler.
The global prescaler is a common prescaler used with all timers of TPU. The global prescaler divides HCLK (input
clock of TPU) according to a set value of TPUCFG.GLBPS[5:0]. The value of division can be set by 1 to 64.
The global prescaler function controls operation by the TPUCFG.GLBPSE bit. The global prescaler function is
enabled by writing "1" in TPUCFG.GLBPSE and it is disabled by writing "0" in TPUCFG.GLBPSE.
When TPUCFG.GLBPSE=0, the prescaler function is disabled and the clock of all timers doesn't become valid.
Please, update TPUCFG.GLBPS[5:0] after setting the global prescaler function disabled (TPUCFG.GLBPSE=0).
5.3.
Interrupt Control
This section explains the Interrupt Control.
The generation of the interrupt request is controlled by the TPUCFG.INTE bit that controls the interrupt request by
TPU and the TPUTIE.IE[n] bits that controls the interrupt of each timer. When an effective interrupt request by each
timer exists in TPUCFG.INTE=1((TPUTIE.IE[n]=1)&(TPUTIR.IR[n]=1)), NMI is generated in TPU.
The interrupt factor of each channel can be confirmed with TPUTIR.IR[n].
Interrupt enable/disable of each channel is controlled with TPUTCN0n.IES/TPUTCN0n.IEC.
If 1 is written in TPUTCN0n.IES, the interrupt is permitted and it becomes TPUTIE.IE[n]=1. If "1" is written in
TPUTCN0n.IEC, the interrupt is prohibited and it becomes TPUTIE.IE[n]=0. If "1" is written to TPUTCN0n.IES and
TPUTCN0n.IEC at the same time, it gives higher priority to "clear" than "set".
Please write "1" in TPUTCN0n.IRC when you clear the interrupt request of each channel.
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2083
Chapter 54: Timing Protection Unit
5.4.
Timer Operation
This section explains the timer operation.
Each timer is configured by 24-bit Up-counter.
The timer has two operation modes of normal mode/overflow mode. The operation mode is controlled by the
TPUTCN1n.TMOD bit. The operation mode becomes the normal mode when TPUTCN1n.TMOD=0, and becomes
the overflow mode when TPUTCN1n.TMOD=1.
Normal Mode
The timer operates as the up-counter when the normal mode. When the counter value is equal or larger than
TPUTCN0n.ECPL [23:0], the interrupt flag (TPUTIR.IR[n] (n: the timer channel)) is set. An actual interrupt request
is generated when TPUTIE.IE [n]=1.
The timer starts counting from "0" by writing "1" to the TPUTCN0n.START bit.
During timer count, timer operation is indicated with TPUTST.TS[n]=1. If the interrupt flag is set (TPUTIR.IR[n]=1),
the count is stopped and TPUTST.TS[n]=0 is indicated.
If "1" is written in the TPUTCN0n.STOP bit, the counter stops operating, and TPUTST.TS[n]=0 is indicated. The
counter value at this time (When stopping) is maintained, and does not become 0.
If "1" is written in the TPUTCN0n.CONT bit, the counter operation is restarted, and becomes TPUTST.TS[n]=1.
Overflow Mode
When the overflow of the timer is detected in the overflow mode, the interrupt request flag (TPUTIR.IR[n]) is set. An
actual interrupt request is generated when TPUTIE.IE[n]=1.
Pre-load to the counter is possible in the overflow mode. The value of TPUTCN0n.ECPL[23:0] is pre-loaded and the
count is started after TPUTCN1n.PL=1 is set and operation starts. The timer starts counting from "0" if
TPUTCN1n.PL=0.
5.5.
Free-run Function
This section explains the free-run function.
Each timer can set free-run operation. The free-run operation is a function to restart the count automatically after the
timer counts to the interrupt generation factor. In this case, because the counter operation doesn't stop, it keeps
operating as timer operation status TPUTST.TS[n]=1.
The free-run function becomes effective if you set TPUTCN1n.FRT=1. The free-run function can use both normal
mode/overflow mode.
At the normal mode, the count is restarted from "0". At the overflow mode, the count is restarted from "0" when
TPUTCN1n.PL=0, and the count is restarted after the value of TPUTCN0n.ECPL[23:0] is loaded when
TPUTCN1n.PL=1.
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Chapter 54: Timing Protection Unit
5.6.
Individual Prescaler Function
This section explains the individual prescaler function.
TPU has the individual prescaler for each timer, and it can divide by 1, 2, 4, or 16 the global prescaler output.
Individual prescaler is set with TPUTCN1n.PS[1:0].
5.7.
Debug Support Function
This section explains the debug support function.
TPU can be stopped by writing "1" in the debug mode control bit of the TPU control register (TPUCFG.DBGE=1)
with software. The debug mode of TPU is released when "0" is written in TPUCFG.DBGE and operation is restarted.
5.8.
Operation Flow
This section explains the operation flow.
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Chapter 54: Timing Protection Unit
Initialization Flow
Reset
Register unlock
(TPUUNLOCK)
Individual timer setting
Individual prescaler & timer mode setting
(TPUCN1n)
End value (start value) & start setting
(TPUCN0n)
Timer interrupt enable
(TPUIE)
Global prescaler, interrupt, start
(TPUCFG)
Register lock
(TPUUNLOCK)
Reset
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Chapter 55: Clock Monitor
This chapter explains the clock monitor.
1.
Overview
2.
Features
3.
Configuration
4.
Registers
5.
Operation
6.
Setting
7.
Q&A
8.
Notes
Code : FJ43-1v0-91528-2-E
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Chapter 55: Clock Monitor
1. Overview
This section explains the overview of clock monitor.
The clock monitor is a macro that outputs and monitors internal clock signals to external pins. The clock monitor has
a function for dividing the frequency of a clock signal before output to the pin, allowing clock signals to be used for
synchronization of external circuits with MCU functions.
2. Features
This section explains the features of clock monitor.
Format: Divide the internal clock signal and output to a pin (MONCLK)
Channels: 1
Division ratio: CLK/1, CLK/2, CLK/3 to CLK/16
Allows for glitch-less output
Programmable mark level (outputs "L" or "H" before the clock output is enabled)
Interrupts: None
Stops clock output in stop mode and becomes high impedance
3. Configuration
This section explains the configuration of clock monitor.
Figure 3-1 Configuration Diagram of Clock Monitor
Clock monitor output anable/disable
Internal clock
2088
Clock
select
MONCLK
Prescaler
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Chapter 55: Clock Monitor
MB No. (number of pin)
MB91F52xR(144pin)
MB91F52xU(176pin)
MB91F52xM(208pin)
MB91F52xY(416pin)
Pin number of MONCLK
55
69
81
AD14
4. Registers
This section explains the registers of clock monitor
Table 4-1 Register Map
Address
0x04A8
4.1.
+0
Reserved
Register
+1
+2
Reserved
CSCFG
Register function
+3
CMCFG
Clock Monitor Configuration Registers
Clock Monitor Configuration Registers : CMCFG
The clock monitor configuration registers are shown.
CMCFG: Address 04ABH (Access: Byte, Half-word, Word)
BIT
7
6
5
4
3
2
1
0
CMPRE3
CMPRE2
CMPRE1
CMPRE0
CMSEL3
CMSEL2
CMSEL1
CMSEL0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit4] CMPRE3 to CMPRE0 (Output Frequency Prescaler Bits)
Division ratio setting of selected source clock by CMSEL bits.
CMPRE3
CMPRE2
CMPRE1
CMPRE0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock frequency output to the MONCLK pin
Source clock divided by 1 (Initial value)
Source clock divided by 2
Source clock divided by 3
Source clock divided by 4
Source clock divided by 5
Source clock divided by 6
Source clock divided by 7
Source clock divided by 8
Source clock divided by 9
Source clock divided by 10
Source clock divided by 11
Source clock divided by 12
Source clock divided by 13
Source clock divided by 14
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Chapter 55: Clock Monitor
CMPRE3
CMPRE2
CMPRE1
CMPRE0
1
1
1
1
1
1
0
1
Clock frequency output to the MONCLK pin
Source clock divided by 15
Source clock divided by 16
[bit3 to bit0] CMSEL3 to CMSEL0 (Output Source Clock Selection Bits)
Selected source clock for output signal of MONCLK pin.
CMSEL3
CMSEL2
CMSEL1
CMSEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock source output to MONCLK pin
MONCLK output disabled (high impedance state) (initial value)
Main oscillation before CSV input
CR oscillation
Main oscillation output from CSV
HCLK for FlexRay
SCLK for FlexRay
PLL output for FlexRay
PLL automatic gear output for FlexRay
PLL output
SSCG output
PLL output after CAN prescaler (CAN system clock)
CCLK
HCLK
PCLK1(Spread peripheral clock)
PCLK2 (Peripheral clock after spread/ non spread selection)
TCLK
CSCFG: Address 04AAH (Access: Byte, Half-word, Word)
BIT
7
6
5
4
3
Reserved
Reserved
Reserved
MONCKI
Initial value
0
0
0
0
0
Attribute
R/W0
R,WX
R,WX
R/W
R/W0
2
1
0
0
0
0
R/W0
R/W0
R/W0
Reserved
[bit7] Reserved
This bit is reserved. Always set this bit to "0" when writing.
[bit6, bit5] Reserved
These bits are reserved. Writing to these bits has no influence on operation.
[bit4] MONCKI : Clock Monitor MONCLK Inverter
MONCKI
0
1
Function
MONCLK mark level is low level (initial value)
MONCLK mark level is high level
[bit3 to bit0] Reserved
This bit is reserved. Always set this bit to "0" when writing.
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Chapter 55: Clock Monitor
5. Operation
This section explains operation description of clock monitor
Clock division example
Source clock
1/2
1/3
1/4
1/8
1/15
1/16
Clock switching sequence
CLKP
CMSEL
Source clock
frequency
divided by 1/n
MONCLK pin
(MONCKI = 0)
MONCLK pin
(MONCKI = 1)
High impedance state
High impedance state
1. The MONCLK pin is in the high impedance state.
2. CMSEL is set to the selected clock (prescaler) from 0000 B (no clock selected).
3. The MONCLK pin is set to the output "L" status (or output "H" if MONCKI is set to "1") for the duration of one
internal (prescaled) clock.
4. After one period of the selected (prescaler) internal clock, MONCLK outputs the selected (prescaler) internal
clock.
5. CMSEL is set to 0000B (no clock selected) from the selected clock (prescaler).
6. The MONCLK pin is set to the output "L" status (or output "H" if MONCKI is set to "1") for the duration of one
internal (prescaled) clock.
7. The MONCLK pin switches to the high impedance state.
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2091
Chapter 55: Clock Monitor
6. Setting
This section explains the setting of clock monitor.
Setting
Setting of the prescaler value
Setting of the source clock
Setting of the mark level
Enabling of clock monitor
output
Setting register
Output frequency prescaler
(CMCFG.CMPRE3 to CMPRE0)
Output source clock select
(CMCFG.CMSEL3 to CMSEL0)
Clock monitor inverter
(CSCFG.MONCKI)
Output source clock select
(CMCFG.CMSEL3 to CMSEL0)
Setting
procedure
Section 7.2
Section 7.1
Section 7.4
Section 7.3
7. Q&A
This section explains the Q&A of clock monitor
7.1 How to Configure the Output Pin (MONCLK)
7.2 How to Select the Output Frequency
7.3 How to Enable or Disable Clock Monitor Output
7.4 How to Set the Clock Output Mark Level
7.1.
How to Configure the Output Pin (MONCLK)
Setting of the output pin (MONCLK) is shown.
Use the output source clock selection bits (CMCFG.CMSEL3 to CMSEL0).
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Chapter 55: Clock Monitor
7.2.
How to Select the Output Frequency
Selection of the output frequency is shown.
Use the output frequency prescaler bits (CMCFG.CMPRE3 to CMPRE0).
Clock division
ratio
1/2
1/3
1/4
1/8
1/15
1/16
7.3.
When output frequency
(Example)
HCLK is selected
Output frequency prescaler
(CMCFG.CMPRE3 to CMPRE0)
HCLK=32MHz
HCLK=40MHz
16.0MHz
10.7MHz
8.0MHz
4.0MHz
2.1MHz
2.0MHz
20.0MHz
13.3MHz
10.0MHz
5.0MHz
2.7MHz
2.5MHz
Set to 0001B
Set to 0010B
Set to 0011B
Set to 0111B
Set to 1110B
Set to 1111B
How to Enable or Disable Clock Monitor Output
Enabling or disabling clock monitor output is shown.
Use the output source clock selection bits (CMCFG.CMSEL3 to CMSEL0).
Operation Description
Disable clock monitor output
(Set the pin to the high impedance state)
Enable clock monitor output
7.4.
Output source clock select bits
(CMCFG.CMSEL3 to CMSEL0)
Set to 0000B
Set to 0001B to 1111B
(However, setting to 0100B to 0111B are prohibited)
How to Set the Clock Output Mark Level
Setting of the clock output mark level is shown.
Use the clock monitor MONCLK inverter bit (CSCFG.MONCKI).
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2093
Chapter 55: Clock Monitor
8. Notes
This section explains the notes on clock monitor.
In order to achieve glitch-free switching, use the following procedure when changing the source clock (CMSEL3 to
CMSEL0) or prescaler ratio (CMPRE3 to CMPRE0).
The CMPRE3 to CMPRE0 registers can be written only when the CMSEL3 to CMSEL0 registers are "0 H".
The CMPRE3 to CMPRE0 registers can be written only when "0H" is written to the CMSEL3 to CMSEL0
registers during the same write access.
At least two cycles of the monitor clock division are required during the two write accesses to CMPRE and
CMCFG.
When selecting another effective clock while a clock is already selected as the clock source (CMSEL is not "0 H"),
first set CMSEL to "0H" and check that CMSEL returns "0H" on read before writing the target clock setting value to
CMSEL.
If the clock selected as the monitor clock is stopped during monitoring, rewriting to any registers have no effect
until the selected clock is started again or the unit is reset.
(Access example)
1. Access
CNCFG.CMSEL = 0
CMCFG.CMPRE = Prescaler
2. Access
CMCFG.CMSEL = Clock
The CSCFG.MONCKI flag can also be written in the same procedure as above only when CMSEL3 to CMSEL0 are
"0H".
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Appendix
Appendix is shown.
A.
I/O Map
B.
List of Interrupt Vector
C.
Pins Statuses in State of CPU
D.
JTAG Boundary Scan Test
E.
Major Changes
Code : APDX-1v0-91528-3-E
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2095
Appendix
A. I/O Map
IO map is shown.
The following I/O map shows the relationship between memory space and registers for peripheral resources.
Figure A-1 Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
000090 H
Address offset value/ register name
+0
+1
BT1TMR[R] H
0000000000000000
00009CH
0000A0 H
+3
BT1PCSR/BT1PRLL[R /W] H
0000000000000000
BTSEL[R /W] B
----000 0
Block
BT1TMCR[R/W]B,H,W
00000000 00000000
BT1STC[R/W] B
00000000
000094 H
000098 H
+2
BT1PDU T/BT1PRLH/BT1D TBF[R/W] H
0000000000000000
Base timer 1
BTSS SR[W] B,H
-------- ------11
ADERH [R/W]B, H, W
00000000 00000000
ADER L [R/W]B, H, W
00000000 00000000
0000A4 H
ADC S1 [R/W] B, H,W
00000000
ADCS0 [R/W] B, H,W
00000000
ADCR1 [R] B, H,W
------XX
ADCR 0 [R] B, H,W
XXXXX XXX
0000A8 H
ADCT1 [R/W] B, H,W
00010000
ADC T0 [R/W] B, H,W
00101100
ADSCH [R/W] B, H,W
---00000
ADECH [R/W] B, H,W
---00000
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)
The access by the data access attribute
not described is disabled.
Initial register value after reset
The initial register value after reset indicates as follows:
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting
Note:
It is prohibited to access addresses not described here.
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Appendix
Table A-1 : I/O Map
Address
000000H
000004H
000008H
00000CH
000010H
000014H
000018H
00001CH
000020H
000024H
000028H
00002CH
000030H
000034H
000038H
00003CH
000040H
000044H
000048H
to
00005CH
000060H
000064H
000068H
+0
Address offset value / Register name
+1
+2
+3
Block
PDR00 [R/W] B,H,W
XXXXXXXX
PDR04 [R/W] B,H,W
XXXXXXXX
PDR08 [R/W] B,H,W
XXXXXXXX
PDR12 [R/W] B,H,W
XXXXXXXX
PDR20 [R/W] B,H,W
XXXXXXXX
PDR24 [R/W] B,H,W
--XXXXXX
PDR16 [R/W] B,H,W
XXXXXXXX
PDR28 [R/W] B,H,W
XXXXXXXX
PDR01 [R/W] B,H,W PDR02 [R/W] B,H,W PDR03 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR05 [R/W] B,H,W PDR06 [R/W] B,H,W PDR07 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR09 [R/W] B,H,W PDR10 [R/W] B,H,W PDR11 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR13 [R/W] B,H,W PDR14 [R/W] B,H,W PDR15 [R/W] B,H,W
-XXX--XX
---------XXXXXX
Port Data Register
PDR21 [R/W] B,H,W PDR22 [R/W] B,H,W PDR23 [R/W] B,H,W
XXXXXXXX
XXX--XXX
XXXXXXXX
PDR25 [R/W] B,H,W PDR26 [R/W] B,H,W PDR27 [R/W] B,H,W
-XXXXXXX
XXXXXX-XXX-XXXX
PDR17 [R/W] B,H,W PDR18 [R/W] B,H,W PDR19 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR29 [R/W] B,H,W
―
―
XXXXXXXX
MSCY10 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY11 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCL1011 [R/W]
MSCH1011 [R] B,H,W
―
―
B,H,W
Input
00000000
------00
Capture 10,11
32-bit ICU
IPCP10 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP11 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS1011 [R/W] B,H,W
―
―
―
00000000
WDTECR0 [R/W]
B,H,W
―
―
―
---00000
Watchdog Timer
[S]
WDTCR0 [R/W]
WDTCPR0 [W]
WDTCR1 [R]
WDTCPR1 [W]
B,H,W
B,H,W
B,H,W
B,H,W
-0--0000
00000000
----0110
00000000
―
―
―
―
Reserved
DICR [R/W] B
―
―
―
Delayed Interrupt
-------0
―
―
TMRLRA0 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB0 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA7 [R/W] H
XXXXXXXX XXXXXXXX
―
―
TMR0 [R] H
XXXXXXXX XXXXXXXX
TMCSR0 [R/W] B,H,W
00000000 0-000000
TMR7 [R] H
XXXXXXXX XXXXXXXX
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Reserved
Reload Timer 0
Reload Timer 7
2097
Appendix
Address
00006CH
000070H
000074H
000078H
00007CH
000080H
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
to
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
000118H
00011CH
2098
+0
Address offset value / Register name
+1
+2
+3
TMRLRB7 [R/W] H
TMCSR7 [R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
FRS8 [R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
FRS9 [R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
OCLS67 [R/W]
―
―
―
B,H,W
----0000
OCLS89 [R/W]
―
―
―
B,H,W
----0000
BT0TMR [R] H
BT0TMCR [R/W] H
00000000 00000000
-000--00 -000-000
BT0TMCR2 [R/W] B BT0STC [R/W] B
―
―
-------0
-0-0-0-0
BT0PCSR/BT0PRLL [R/W] H
BT0PDUT/BT0PRLH/BT0DTBF [R/W] H
00000000 00000000
00000000 00000000
―
―
―
―
BT1TMR [R] H
BT1TMCR [R/W] H
00000000 00000000
-000--00 -000-000
BT1TMCR2 [R/W] B BT1STC [R/W] B
―
―
-------0
-0-0-0-0
BT1PCSR/BT1PRLL [R/W] H
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
00000000 00000000
BTSEL01 [R/W] B
BTSSSR [W] B,H
―
----0000
-------- ------11
―
―
TMRLRA1 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB1 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA2 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB2 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA3 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB3 [R/W] H
XXXXXXXX XXXXXXXX
―
―
TMR1 [R] H
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] B, H,W
00000000 0-000000
TMR2 [R] H
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] B,H,W
00000000 0-000000
TMR3 [R] H
XXXXXXXX XXXXXXXX
TMCSR3 [R/W] B,H,W
00000000 0-000000
MSCY4 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY5 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
Free-run timer
selection register 8
Free-run timer
selection register 9
OCU67 Output
level control
register
OCU89 Output
level control
register
Base Timer 0
Reserved
Base Timer 1
Base Timer 0,1
Reserved
Reload Timer 1
Reload Timer 2
Reload Timer 3
Input Capture 4,5
Cycle measurement
data register 45
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
+0
000120H
000124H
000128H
―
00012CH
000130H
000134H
―
000138H
00013CH
Address offset value / Register name
+1
+2
+3
OCCP6 [R/W] W
00000000 00000000 00000000 00000000
OCCP7 [R/W] W
00000000 00000000 00000000 00000000
OCSH67 [R/W] B,H,W OCSL67 [R/W] B,H,W
―
---0--00
0000--00
OCCP8 [R/W] W
00000000 00000000 00000000 00000000
OCCP9 [R/W] W
00000000 00000000 00000000 00000000
OCSH89 [R/W] B,H,W OCSL89 [R/W] B,H,W
―
---0--00
0000--00
OCCP12 [R/W] W
00000000 00000000 00000000 00000000
OCCP13 [R/W] W
00000000 00000000 00000000 00000000
OCSH1213 [R/W]
OCSL1213 [R/W]
―
B,H,W
B,H,W
---0--00
0000--00
Block
Output
Compare 6,7
32-bit OCU
Output
Compare 8,9
32-bit OCU
Output
Compare 12,13
32-bit OCU
000140H
―
000144H
to
0001B4H
―
―
―
―
Reserved
EPFR64 [R/W]
B,H,W
-----00EPFR68 [R/W]
B,H,W
----0000
EPFR72 [R/W]
B,H,W
000000-0
EPFR76 [R/W]
B,H,W
00000-0EPFR80 [R/W]
B,H,W
---00000
EPFR84 [R/W]
B,H,W
00000000
EPFR88 [R/W]
B,H,W
-------0
EPFR92 [R/W]
B,H,W
-0-0-0-0
EPFR65 [R/W]
B,H,W
0000-00EPFR69 [R/W]
B,H,W
----0000
EPFR73 [R/W]
B,H,W
00000000
EPFR77 [R/W]
B,H,W
--000000
EPFR81 [R/W]
B,H,W
00000000
EPFR85 [R/W]
B,H,W
--000000
EPFR89 [R/W]
B,H,W
-0-00000
EPFR93 [R/W]
B,H,W
00000000
EPFR66 [R/W]
B,H,W
--000000
EPFR70 [R/W]
B,H,W
---00000
EPFR74 [R/W]
B,H,W
00000000
EPFR78 [R/W]
B,H,W
------00
EPFR82 [R/W]
B,H,W
00000000
EPFR86 [R/W]
B,H,W
---00000
EPFR90 [R/W]
B,H,W
-0-0-0-0
EPFR94 [R/W]
B,H,W
-0-0-0-0
EPFR67 [R/W]
B,H,W
----0000
EPFR71 [R/W]
B,H,W
-0-0-0-0
EPFR75 [R/W]
B,H,W
00000000
EPFR79 [R/W]
B,H,W
00000000
EPFR83 [R/W]
B,H,W
-0000000
EPFR87 [R/W]
B,H,W
-------EPFR91 [R/W]
B,H,W
-0-0-0-0
EPFR95 [R/W]
B,H,W
-0-0-0-0
Extended port
function register
0001B8H
0001BCH
0001C0H
0001C4H
0001C8H
0001CCH
0001D0H
0001D4H
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
2099
Appendix
Address
0001D8H
0001DCH
0001E0H
0001E4H
0001E8H
0001ECH
0001F0H
0001F4H
0001F8H
0001FCH
000200H
to
000238H
00023CH
000240H
000244H
000248H
00024CH
000250H
000254H
000258H
to
0002C0H
2100
+0
Address offset value / Register name
+1
+2
TMRLRA4 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB4 [R/W] H
XXXXXXXX XXXXXXXX
EPFR96 [R/W]
EPFR97 [R/W]
B,H,W
B,H,W
-0-0-0-0
-0-0-0-0
EPFR100 [R/W]
EPFR101 [R/W]
B,H,W
B,H,W
-----00-----00EPFR104 [R/W]
EPFR105 [R/W]
B,H,W
B,H,W
-----00-----00EPFR108 [R/W]
EPFR109 [R/W]
B,H,W
B,H,W
---00000
--000000
TMRLRA5 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB5 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA6 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB6 [R/W] H
XXXXXXXX XXXXXXXX
―
―
+3
TMR4 [R] H
XXXXXXXX XXXXXXXX
TMCSR4 [R/W] B, H,W
00000000 0-000000
EPFR98 [R/W]
EPFR99 [R/W]
B,H,W
B,H,W
0000-0-0
----0000
EPFR102 [R/W]
EPFR103 [R/W]
B,H,W
B,H,W
-----00-----00EPFR106 [R/W]
EPFR107 [R/W]
B,H,W
B,H,W
-----00-----00EPFR110 [R/W]
EPFR111 [R/W]
B,H,W
B,H,W
--000000
-------0
TMR5 [R] H
XXXXXXXX XXXXXXXX
TMCSR5 [R/W] B, H,W
00000000 0-000000
TMR6 [R] H
XXXXXXXX XXXXXXXX
TMCSR6 [R/W] B, H,W
00000000 0-000000
―
―
Block
Reload Timer 4
Extended port
function register
Reload Timer 5
Reload Timer 6
Reserved
DACR0 [R/W] B,H,W DADR0 [R/W] B,H,W DACR1 [R/W] B,H,W DADR1 [R/W] B,H,W
DA Converter
-------0
XXXXXXXX
-------0
XXXXXXXX
CPCLR3 [R/W] W
11111111 11111111 11111111 11111111
TCDT3 [R/W] W
Free-run Timer 3
00000000 00000000 00000000 00000000
32-bit FRT
TCCSH3 [R/W]
TCCSL3 [R/W]
B,H,W
B,H,W
―
―
0-----00
-1-00000
CPCLR4 [R/W] W
11111111 11111111 11111111 11111111
TCDT4 [R/W] W
Free-run Timer 4
00000000 00000000 00000000 00000000
32-bit FRT
TCCSH4 [R/W]
TCCSL4 [R/W]
B,H,W
B,H,W
―
―
0-----00
-1-00000
―
―
―
―
Reserved
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
0002C4H
to
0002FCH
000300H
to
00030CH
+0
Address offset value / Register name
+1
+2
+3
Block
―
―
―
―
Reserved
―
―
―
―
Reserved
000310H
―
―
000314H
000318H
00031CH
―
―
―
―
―
MPU [S]
(Only CPU core
can access this
area)
―
000328H
00032CH
―
000330H
000334H
―
000338H
00033CH
―
000340H
000344H
―
―
000320H
000324H
MPUCR [R/W] H
000000-0 ----0100
―
―
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR [R/W] H
―
-------- 00000--0
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR [R/W] H
―
-------- 00000--0
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0 [R/W] H
―
000000-0 00000--0
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1 [R/W] H
―
000000-0 00000--0
PABR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2 [R/W] H
―
000000-0 00000--0
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
MPU [S]
(Only CPU core
can access this
area)
2101
Appendix
Address
+0
000348H
00034CH
―
000350H
000354H
―
000358H
00035CH
―
000360H
000364H
―
000368H
00036CH
000370H
to
0003ACH
0003B0H
to
0003FCH
000400H
000404H
000408H
00040CH
000410H
000414H
2102
―
Address offset value / Register name
+1
+2
+3
PABR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3 [R/W] H
―
000000-0 00000--0
PABR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4 [R/W] H
―
000000-0 00000--0
PABR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5 [R/W] H
―
000000-0 00000--0
PABR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6 [R/W] H
―
000000-0 00000--0
PABR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR7 [R/W] H
―
000000-0 00000--0
MPU [S]
(Only CPU core
can access this
area)
―
―
―
Block
Reserved [S]
―
―
ICSEL0 [R/W] B,H,W ICSEL1 [R/W] B,H,W ICSEL2 [R/W] B,H,W ICSEL3 [R/W] B,H,W
-----000
----0000
-------0
-------0
ICSEL4 [R/W] B,H,W ICSEL5 [R/W] B,H,W ICSEL6 [R/W] B,H,W ICSEL7 [R/W] B,H,W
-------0
-----000
----0000
----0000
ICSEL10 [R/W]
ICSEL11 [R/W]
ICSEL8 [R/W] B,H,W ICSEL9 [R/W] B,H,W
B,H,W
B,H,W
------00
------00
------00
-----000
ICSEL12 [R/W]
ICSEL13 [R/W]
ICSEL14 [R/W]
ICSEL15 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
-------0
------00
------00
------00
ICSEL16 [R/W]
ICSEL17 [R/W]
ICSEL18 [R/W]
ICSEL19 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
----0000
------00
--000000
-----000
ICSEL20 [R/W]
ICSEL21 [R/W]
ICSEL22 [R/W]
ICSEL23 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
-----000
------00
------00
------00
Reserved [S]
DMA request
generation and
clear
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
+0
Address offset value / Register name
+1
+2
000418H
IRPR0H [R] B,H,W
00------
IRPR0L [R] B,H,W
00------
00041CH
―
―
000420H
000424H
000428H
00042CH
000430H
000434H
000438H
00043CH
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
+3
Block
IRPR4H [R] B,H,W IRPR4L [R] B,H,W
0000---0000---IRPR6H [R] B,H,W IRPR6L [R] B,H,W
--00---0000---IRPR8H [R] B,H,W IRPR8L [R] B,H,W
--0-----00----IRPR10H [R] B,H,W IRPR10L [R] B,H,W
-0------0-----IRPR12H [R] B,H,W IRPR12L [R] B,H,W
--0000-----00-IRPR14H [R] B,H,W IRPR14L [R] B,H,W
00000000
00000000
ICSEL24 [R/W]
ICSEL25 [R/W]
B,H,W
B,H,W
------00
---00000
IRPR1H [R] B,H,W
00-----IRPR3H [R] B,H,W
000000-IRPR5H [R] B,H,W
0000---IRPR7H [R] B,H,W
-0-00--IRPR9H [R] B,H,W
-0-----IRPR11H [R] B,H,W
0------IRPR13H [R] B,H,W
00-----IRPR15H [R] B,H,W
000----ICSEL26 [R/W]
B,H,W
-------0
IRPR1L [R] B,H,W
00-----IRPR3L [R] B,H,W
000000-IRPR5L [R] B,H,W
0000000IRPR7L [R] B,H,W
------00
IRPR9L [R] B,H,W
-0-----IRPR11L [R] B,H,W
0------IRPR13L [R] B,H,W
00-----IRPR15L [R] B,H,W
00000000
ICSEL27 [R/W]
B,H,W
-------0
IRPR16H [R] B,H,W IRPR16L [R] B,H,W
000----00000---
IRPR17H [R] B,H,W
000-----
IRPR17L [R] B,H,W
000-----
ICR00 [R/W] B,H,W
---11111
ICR04 [R/W] B,H,W
---11111
ICR08 [R/W] B,H,W
---11111
ICR12 [R/W] B,H,W
---11111
ICR16 [R/W] B,H,W
---11111
ICR20 [R/W] B,H,W
---11111
ICR24 [R/W] B,H,W
---11111
ICR28 [R/W] B,H,W
---11111
ICR32 [R/W] B,H,W
---11111
ICR36 [R/W] B,H,W
---11111
ICR40 [R/W] B,H,W
---11111
ICR44 [R/W] B,H,W
---11111
ICR02 [R/W] B,H,W
---11111
ICR06 [R/W] B,H,W
---11111
ICR10 [R/W] B,H,W
---11111
ICR14 [R/W] B,H,W
---11111
ICR18 [R/W] B,H,W
---11111
ICR22 [R/W] B,H,W
---11111
ICR26 [R/W] B,H,W
---11111
ICR30 [R/W] B,H,W
---11111
ICR34 [R/W] B,H,W
---11111
ICR38 [R/W] B,H,W
---11111
ICR42 [R/W] B,H,W
---11111
ICR46 [R/W] B,H,W
---11111
ICR03 [R/W] B,H,W
---11111
ICR07 [R/W] B,H,W
---11111
ICR11 [R/W] B,H,W
---11111
ICR15 [R/W] B,H,W
---11111
ICR19 [R/W] B,H,W
---11111
ICR23 [R/W] B,H,W
---11111
Interrupt Controller
[S]
ICR27 [R/W] B,H,W
---11111
ICR31 [R/W] B,H,W
---11111
ICR35 [R/W] B,H,W
---11111
ICR39 [R/W] B,H,W
---11111
ICR43 [R/W] B,H,W
---11111
ICR47 [R/W] B,H,W
---11111
ICR01 [R/W] B,H,W
---11111
ICR05 [R/W] B,H,W
---11111
ICR09 [R/W] B,H,W
---11111
ICR13 [R/W] B,H,W
---11111
ICR17 [R/W] B,H,W
---11111
ICR21 [R/W] B,H,W
---11111
ICR25 [R/W] B,H,W
---11111
ICR29 [R/W] B,H,W
---11111
ICR33 [R/W] B,H,W
---11111
ICR37 [R/W] B,H,W
---11111
ICR41 [R/W] B,H,W
---11111
ICR45 [R/W] B,H,W
---11111
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Interrupt Request
Batch Reading
Register
Interrupt Request
Batch Reading
Register
DMA request
generation and
clear
Interrupt Request
Batch Reading
Register
2103
Appendix
Address
+0
Address offset value / Register name
+1
+2
000470H
to
00047CH
―
―
―
000480H
RSTRR [R]
B,H,W
XXXX--XX
RSTCR [R/W]
B,H,W
111----0
STBCR [R/W]
B,H,W *
000---11
000484H
000488H
00048CH
000490H
000494H
000498H
00049CH
0004A0H
0004A4H
0004A8H
0004ACH
0004B0H
0004B4H
0004B8H
0004BCH
0004C0H
0004C4H
0004C8H
0004CCH
0004D0H
0004D4H
2104
―
―
DIVR0 [R/W] B,H,W DIVR1 [R/W] B,H,W
000----0001---―
―
IORR0 [R/W] B,H,W IORR1 [R/W] B,H,W
-0000000
-0000000
IORR4 [R/W] B,H,W IORR5 [R/W] B,H,W
-0000000
-0000000
IORR8 [R/W] B,H,W IORR9 [R/W] B,H,W
-0000000
-0000000
IORR12 [R/W] B,H,W IORR13 [R/W] B,H,W
-0000000
-0000000
―
―
CANPRE [R/W]
B,H,W
―
---00000
―
DIVR2 [R/W] B,H,W
0011---―
IORR2 [R/W] B,H,W
-0000000
IORR6 [R/W] B,H,W
-0000000
IORR10 [R/W] B,H,W
-0000000
IORR14 [R/W] B,H,W
-0000000
―
―
+3
―
Block
Reserved [S]
―
Reset Control [S]
Power Control [S]
*: Writing STBCR
by DMA is
forbidden
Reserved [S]
―
Clock Control [S]
―
―
Reserved [S]
IORR3 [R/W] B,H,W
-0000000
IORR7 [R/W] B,H,W
-0000000
DMA request by
IORR11 [R/W] B,H,W peripheral [S]
-0000000
IORR15 [R/W] B,H,W
-0000000
―
Reserved
―
CAN prescaler
CSCFG[R/W]B,H,W CMCFG[R/W]B,H,W Clock monitor
---0---00000000
control register
ADERH0[R/W] B,H
ADERL0[R/W] B,H
Analog input
11111111 11111111
11111111 11111111
control register 0
ADERH1[R/W] B,H
ADERL1[R/W] B,H
Analog input
11111111 11111111
11111111 11111111
control register 1
―
―
―
―
Reserved
CUCR0 [R/W] B,H,W
CUTD0 [R/W] B,H,W
-------- ---0--00
10000000 00000000
CUTR0 [R] B,H,W
-------- 00000000 00000000 00000000
RTC/WDT1
―
―
―
―
calibration
CUCR1 [R/W] B,H,W
CUTD1 [R/W] B,H,W
-------- ---0--00
11000011 01010000
CUTR1 [R] B,H,W
-------- 00000000 00000000 00000000
―
―
―
―
Reserved
PLL2DIVM[R/W]
PLL2DIVN[R/W]
PLL2DIVG[R/W]
PLL2MULG[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
----0000
-0000000
----0000
00000000
Clock control for
FlexRay
PLL2CTRL[R/W]
PLL2DIVK[R/W]
CLKR2[R/W]
B,H,W
B,H,W
B,H,W
―
----0000
-------0
000--000
―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
0004D8H
0004DCH
0004E0H
to
00050CH
000510H
000514H
000518H
00051CH
000520H
000524H
000528H
00052CH
000530H
000534H
to
00053CH
000540H
000544H
to
00054CH
000550H
000554H
000558H
+0
Address offset value / Register name
+1
+2
+3
ICSEL28 [R/W]
B,H,W
-------0
ICSEL32 [R/W]
B,H,W
-------0
ICSEL29 [R/W]
B,H,W
-------0
ICSEL33 [R/W]
B,H,W
-------0
ICSEL30 [R/W]
B,H,W
-------0
ICSEL31 [R/W]
B,H,W
-------0
―
―
―
―
―
―
CSELR [R/W] B,H,W CMONR [R] B,H,W MTMCR [R/W] B,H,W STMCR [R/W] B,H,W
001---00
001---00
00001111
0000-111
PLLCR [R/W] B,H,W
CSTBR [R/W] B,H,W PTMCR [R/W] B,H,W
-------- 11110000
-0000000
00-----CPUAR [R/W] B,H,W
―
―
―
0----XXX
―
―
―
―
CCPSSELR [R/W]
CCPSDIVR [R/W]
B,H,W
―
―
B,H,W
-------0
-000-000
CCPLLFBR [R/W]
CCSSFBR0 [R/W]
CCSSFBR1 [R/W]
―
B,H,W
B,H,W
B,H,W
-0000000
--000000
---00000
CCSSCCR0 [R/W]
CCSSCCR1 [R/W] H,W
―
B,H,W
000----- -----------0000
CCCGRCR0 [R/W]
CCCGRCR1 [R/W]
CCCGRCR2 [R/W]
―
B,H,W
B,H,W
B,H,W
00----00
00000000
00000000
CCRTSELR [R/W]
CCPMUCR0 [R/W]
CCPMUCR1 [R/W]
B,H,W
―
B,H,W
B,H,W
0------0
0-----00
0--00000
―
―
EIRR2 [R/W] B,H,W ENIR2 [R/W] B,H,W
XXXXXXXX
00000000
―
―
EIRR0 [R/W] B,H,W ENIR0 [R/W] B,H,W
XXXXXXXX
00000000
EIRR1 [R/W] B,H,W ENIR1 [R/W] B,H,W
XXXXXXXX
00000000
―
―
―
―
ELVR2 [R/W] B,H,W
00000000 00000000
―
―
ELVR0 [R/W] B,H,W
00000000 00000000
ELVR1 [R/W] B,H,W
00000000 00000000
―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Block
DMA request
generation and
clear
Reserved
Clock Control [S]
Reset Control [S]
Reserved [S]
Clock Control 2
[S]
Clock Control 2
[S]
Reserved
External Interrupt
(INT16 to 23)
Reserved
External Interrupt
(INT0 to 7)
External Interrupt
(INT8 to 15)
Reserved
2105
Appendix
Address
+0
Address offset value / Register name
+1
+2
00055CH
―
―
000560H
―
000564H
―
000568H
WTHR [R/W] B,H
---00000
00056CH
―
WTCRH [R/W] B
------00
WTBRH [R/W] B
--XXXXXX
WTMR [R/W] B,H
--000000
CSVCR [R/W] B
000111--
000570H
to
00057CH
―
000580H
000584H
000588H,
00058CH
000590H
000594H
000598H
00059CH
to
0005FCH
Real Time Clock
(RTC)
―
―
Clock Supervisor
―
―
―
Reserved
―
―
―
LVD5F [R/W]
B,H,W
00000001
LVD [R/W]
B,H,W
01000--0
―
―
―
―
―
Reserved
PMUSTR [R/W]
B,H,W
0-----1X
PMUINTF0 [R/W]
B,H,W
00000000
―
PMUCTLR [R/W]
B,H,W
0-00---PMUINTF1 [R/W]
B,H,W
00000000
―
PWRTMCTL [R/W]
B,H,W
-----011
PMUINTF2 [R/W]
B,H,W
0000---―
―
PMU
PMUINTF3 [R/W]
B,H,W
00000000
―
PMU
―
―
―
―
Reserved
ASR0 [R/W] W
00000000 00000000 -------- 1111-001
ASR1 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
ASR2 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
ASR3 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000604H
000608H
00060CH
2106
WTDR [R/W] H
00000000 00000000
WTCRM [R/W] B,H WTCRL [R/W] B,H
00000000
----00-0
WTBRM [R/W] B
WTBRL [R/W] B
XXXXXXXX
XXXXXXXX
WTSR [R/W] B
―
--000000
Block
REGSEL [R/W]
B,H,W
0110011LVD5R [R/W]
B,H,W
-------1
000600H
000610H
to
00063CH
+3
―
―
―
Regulator Control /
Low-Voltage
Detection
External Bus
Interface [S]
External Bus
Interface [S]
―
Reserved [S]
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
Address offset value / Register name
+1
+2
+0
ACR0 [R/W] W
-------- -------- -------- 01--00-ACR1 [R/W] W
-------- -------- -------- XX--XX-ACR2 [R/W] W
-------- -------- -------- XX--XX-ACR3 [R/W] W
-------- -------- -------- XX--XX--
000640H
000644H
000648H
00064CH
000650H
to
00067CH
―
000684H
000688H
00068CH
000710H
―
Block
External Bus
Interface [S]
―
―
AWR0 [R/W] W
----1111 00000000 11110000 00000-0AWR1 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-XAWR2 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-XAWR3 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000680H
000690H
to
0006FCH
000700H
to
00070CH
+3
Reserved [S]
External Bus
Interface [S]
―
―
―
―
Reserved [S]
―
―
―
―
Reserved
BPCCRA [R/W] B
00000000
000714H
000718H
00071CH
BPCCRB [R/W] B
BPCCRC [R/W] B
00000000
00000000
BPCTRA [R/W] W
00000000 00000000 00000000 00000000
BPCTRB [R/W] W
00000000 00000000 00000000 00000000
BPCTRC [R/W] W
00000000 00000000 00000000 00000000
―
Bus Performance
Counter
000720H
to
0007F8H
―
―
―
―
Reserved
0007FCH
BMODR [R] B, H, W
XXXXXXXX
―
―
―
Mode Register
000800H
to
00083CH
―
―
―
―
Reserved [S]
―
FSTR [R/W] B
-----001
Flash Memory
Register [S]
―
―
Reserved [S]
FCTLR [R/W] H
-0--1000 0--0----
000840H
000844H
to
000854H
―
―
000858H
―
―
WREN [R/W] H
00000000 00000000
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Wild Register [S]
2107
Appendix
Address
00085CH
to
00087CH
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
0008D0H
0008D4H
2108
+0
―
Address offset value / Register name
+1
+2
―
―
WRAR00 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
―
Block
Reserved [S]
Wild Register [S]
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
+0
Address offset value / Register name
+1
+2
WRAR11 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11 [R/W] W
0008DCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12 [R/W] W
0008E0H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR12 [R/W] W
0008E4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13 [R/W] W
0008E8H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13 [R/W] W
0008ECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14 [R/W] W
0008F0H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14 [R/W] W
0008F4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15 [R/W] W
0008F8H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15 [R/W] W
0008FCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
TPUUNLOCK [R/W] W
000900H
00000000 00000000 00000000 00000000
TPUVST [R/W]
TPULST [R] B,H,W
000904H
―
B,H,W
-------0
-----000
TPUCFG [R/W] B,H,W
000908H
-------0 0-000000 -------- -------0
TPUTIR [R] B,H,W
00090CH
―
―
00000000
TPUTST [R] B,H,W
000910H
―
―
00000000
TPUTIE [R/W] B,H,W
000914H
―
―
00000000
TPUTMID [R] B,H,W
000918H
00000000 00000000 00000000 00000000
00091CH
to
―
―
―
00092CH
TPUTCN00 [R/W] B,H,W
000930H
000000-- 00000000 00000000 00000000
TPUTCN01 [R/W] B,H,W
000934H
000000-- 00000000 00000000 00000000
TPUTCN02 [R/W] B,H,W
000938H
000000-- 00000000 00000000 00000000
TPUTCN03 [R/W] B,H,W
00093CH
000000-- 00000000 00000000 00000000
TPUTCN04 [R/W] B,H,W
000940H
000000-- 00000000 00000000 00000000
+3
Block
0008D8H
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Wild Register [S]
―
―
―
―
Time Protection
Unit [S]
―
2109
Appendix
Address
+0
000948H
00094CH
000954H
000958H
00095CH
000960H
000964H
000968H
00096CH
000970H
000974H
000978H
00097CH
000980H
000984H
000988H
00098CH
2110
+3
Block
TPUTCN05 [R/W] B,H,W
000000-- 00000000 00000000 00000000
TPUTCN06 [R/W] B,H,W
000000-- 00000000 00000000 00000000
TPUTCN07 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000944H
000950H
Address offset value / Register name
+1
+2
TPUTCN10 [R/W]
B,H,W
---00000
TPUTCN11 [R/W]
B,H,W
---00000
TPUTCN12 [R/W]
B,H,W
---00000
TPUTCN13 [R/W]
B,H,W
---00000
TPUTCN14 [R/W]
B,H,W
---00000
TPUTCN15 [R/W]
B,H,W
---00000
TPUTCN16 [R/W]
B,H,W
---00000
TPUTCN17 [R/W]
B,H,W
---00000
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Time Protection
Unit [S]
TPUTCC0 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC1 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC2 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC3 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC4 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC5 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC6 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC7 [R] B,H,W
-------- 00000000 00000000 00000000
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
000990H
to
0009FCH
000A00H
to
000BECH
+0
Address offset value / Register name
+1
+2
+3
Block
―
―
―
―
Time Protection
Unit [S]
―
―
―
―
Reserved
000BF0H
000BF4H
―
000BF8H
―
000BFCH
―
HSCFR [R/W] B,H,W
-------- ------00 00000000 00000000
―
―
―
MBR [R/W] B,H,W
―
00------ XXXXXXXX
UER [W] B,H,W
―
-------- -------X
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
OCDU
2111
Appendix
Address
000C00H
000C04H
000C08H
000C0CH
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
000C48H
000C4CH
000C50H
000C54H
000C58H
000C5CH
2112
+0
Address offset value / Register name
+1
+2
DCCR0 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR0 [R/W] H
DTCR0 [R/W] H
0------- -----000
00000000 00000000
DSAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCSR1 [R/W] H
DTCR1 [R/W] H
0------- -----000
00000000 00000000
DSAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR2 [R/W] H
DTCR2 [R/W] H
0------- -----000
00000000 00000000
DSAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR3 [R/W] H
DTCR3 [R/W] H
0------- -----000
00000000 00000000
DSAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR4 [R/W] H
DTCR4 [R/W] H
0------- -----000
00000000 00000000
DSAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR5 [R/W] H
DTCR5 [R/W] H
0------- -----000
00000000 00000000
DSAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
DMA
Controller
[S]
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
000C80H
000C84H
000C88H
000C8CH
000C90H
000C94H
000C98H
000C9CH
000CA0H
000CA4H
000CA8H
000CACH
000CB0H
000CB4H
000CB8H
000CBCH
+0
Address offset value / Register name
+1
+2
DCCR6 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR6 [R/W] H
DTCR6 [R/W] H
0------- -----000
00000000 00000000
DSAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR7 [R/W] H
DTCR7 [R/W] H
0------- -----000
00000000 00000000
DSAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR8 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR8 [R/W] H
DTCR8 [R/W] H
0------- -----000
00000000 00000000
DSAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR9 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR9 [R/W] H
DTCR9 [R/W] H
0------- -----000
00000000 00000000
DSAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR10 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR10 [R/W] H
DTCR10 [R/W] H
0------- -----000
00000000 00000000
DSAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR11 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR11 [R/W] H
DTCR11 [R/W] H
0------- -----000
00000000 00000000
DSAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
+3
Block
DMA
Controller
[S]
2113
Appendix
Address
+0
000CC4H
000CC8H
000CCCH
000CD0H
000CD4H
000CD8H
000CDCH
000CE0H
000CE4H
000CE8H
000CECH
000CF0H
000CF4H
000CF8H
000CFCH
000D00H
to
000DF0H
―
000DF4H
―
000DF8H
2114
+3
DCCR12 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR12 [R/W] H
DTCR12 [R/W] H
0------- -----000
00000000 00000000
DSAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR13 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR13 [R/W] H
DTCR13 [R/W] H
0------- -----000
00000000 00000000
DSAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR14 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR14 [R/W] H
DTCR14 [R/W] H
0------- -----000
00000000 00000000
DSAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR15 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR15 [R/W] H
DTCR15 [R/W] H
0------- -----000
00000000 00000000
DSAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CC0H
000DFCH
Address offset value / Register name
+1
+2
―
―
―
DNMIR [R/W] B
0------0
DMACR[R/W] W
0------- -------- 0------- -------―
―
―
Block
DMA
Controller
[S]
―
DILVR [R/W] B
---11111
―
Reserved [S]
DMA
Controller
[S]
Reserved [S]
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
000E00H
000E04H
000E08H
000E0CH
000E10H
000E14H
000E18H
000E1CH
000E20H
000E24H
000E28H
000E2CH
000E30H
000E34H
000E38H
000E3CH
000E40H
000E44H
000E48H
000E4CH
000E50H
000E54H
000E58H
000E5CH
+0
Address offset value / Register name
+1
+2
DDR00 [R/W] B,H,W
00000000
DDR04 [R/W] B,H,W
00000000
DDR08 [R/W] B,H,W
00000000
DDR12 [R/W] B,H,W
00000000
DDR20 [R/W] B,H,W
00000000
DDR24 [R/W] B,H,W
--000000
DDR16 [R/W] B,H,W
00000000
DDR28 [R/W] B,H,W
00000000
PFR00 [R/W] B,H,W
00000000
PFR04 [R/W] B,H,W
00000000
PFR08 [R/W] B,H,W
00000000
PFR12 [R/W] B,H,W
00000000
PFR20 [R/W] B,H,W
00000000
PFR24 [R/W] B,H,W
--000000
PFR16 [R/W] B,H,W
00000000
PFR28 [R/W] B,H,W
00000000
PDDR00 [R] B,H,W
XXXXXXXX
PDDR04 [R] B,H,W
XXXXXXXX
PDDR08 [R] B,H,W
XXXXXXXX
PDDR12 [R] B,H,W
XXXXXXXX
PDDR20 [R] B,H,W
XXXXXXXX
PDDR24 [R] B,H,W
--XXXXXX
PDDR16 [R] B,H,W
XXXXXXXX
PDDR28 [R] B,H,W
XXXXXXXX
DDR01 [R/W] B,H,W
00000000
DDR05 [R/W] B,H,W
00000000
DDR09 [R/W] B,H,W
00000000
DDR13 [R/W] B,H,W
-000--00
DDR21 [R/W] B,H,W
00000000
DDR25 [R/W] B,H,W
-0000000
DDR17 [R/W] B,H,W
00000000
DDR29 [R/W] B,H,W
00000000
PFR01 [R/W] B,H,W
00000000
PFR05 [R/W] B,H,W
00000000
PFR09 [R/W] B,H,W
00000000
PFR13 [R/W] B,H,W
-000--00
PFR21 [R/W] B,H,W
00000000
PFR25 [R/W] B,H,W
-0000000
PFR17 [R/W] B,H,W
00000000
PFR29 [R/W] B,H,W
00000000
PDDR01 [R] B,H,W
XXXXXXXX
PDDR05 [R] B,H,W
XXXXXXXX
PDDR09 [R] B,H,W
XXXXXXXX
PDDR13 [R] B,H,W
-XXX--XX
PDDR21 [R] B,H,W
XXXXXXXX
PDDR25 [R] B,H,W
-XXXXXXX
PDDR17 [R] B,H,W
XXXXXXXX
PDDR29 [R] B,H,W
XXXXXXXX
+3
DDR02 [R/W] B,H,W
00000000
DDR06 [R/W] B,H,W
00000000
DDR10 [R/W] B,H,W
00000000
DDR14 [R/W] B,H,W
-------DDR22 [R/W] B,H,W
000--000
DDR26 [R/W] B,H,W
000000-DDR18 [R/W] B,H,W
00000000
DDR03 [R/W] B,H,W
00000000
DDR07 [R/W] B,H,W
00000000
DDR11 [R/W] B,H,W
00000000
DDR15 [R/W] B,H,W
--000000
DDR23 [R/W] B,H,W
00000000
DDR27 [R/W] B,H,W
000-0000
DDR19 [R/W] B,H,W
00000000
―
―
PFR02 [R/W] B,H,W
00000000
PFR06 [R/W] B,H,W
00000000
PFR10 [R/W] B,H,W
00000000
PFR14 [R/W] B,H,W
-------PFR22 [R/W] B,H,W
000--000
PFR26 [R/W] B,H,W
000000-PFR18 [R/W] B,H,W
00000000
PFR03 [R/W] B,H,W
00000000
PFR07 [R/W] B,H,W
00000000
PFR11 [R/W] B,H,W
00000000
PFR15 [R/W] B,H,W
--000000
PFR23 [R/W] B,H,W
00000000
PFR27 [R/W] B,H,W
000-0000
PFR19 [R/W] B,H,W
00000000
―
―
PDDR02 [R] B,H,W
XXXXXXXX
PDDR06 [R] B,H,W
XXXXXXXX
PDDR10 [R] B,H,W
XXXXXXXX
PDDR14 [R] B,H,W
-------PDDR22 [R] B,H,W
XXX--XXX
PDDR26 [R] B,H,W
XXXXXX-PDDR18 [R] B,H,W
XXXXXXXX
PDDR03 [R] B,H,W
XXXXXXXX
PDDR07 [R] B,H,W
XXXXXXXX
PDDR11 [R] B,H,W
XXXXXXXX
PDDR15 [R] B,H,W
--XXXXXX
PDDR23 [R] B,H,W
XXXXXXXX
PDDR27 [R] B,H,W
XXX-XXXX
PDDR19 [R] B,H,W
XXXXXXXX
―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Block
Data Direction
Register
Port Function
Register
Port Direct
Read Register
2115
Appendix
Address
+0
Address offset value / Register name
+1
+2
000E70H
000E74H
EPFR00 [R/W]
B,H,W
00000000
EPFR04 [R/W]
B,H,W
----00-0
EPFR08 [R/W]
B,H,W
---00000
EPFR12 [R/W]
B,H,W
----0000
―
―
EPFR01 [R/W]
B,H,W
-0-0-000
EPFR05 [R/W]
B,H,W
----0000
EPFR09 [R/W]
B,H,W
-----00EPFR13 [R/W]
B,H,W
------00
―
―
000E78H
―
―
000E7CH
EPFR28 [R/W]
B,H,W
--000-0-
000E80H
―
EPFR29 [R/W]
B,H,W
00000000
EPFR33 [R/W]
B,H,W
-----00-
000E84H
EPFR36 [R/W]
B,H,W
----0-0-
000E88H
000E60H
000E64H
000E68H
000E6CH
000E8CH
000E90H
000E94H
000E98H
000E9CH
000EA0H
to
000EB0H
2116
+3
EPFR02 [R/W]
B,H,W
----0000
EPFR06 [R/W]
B,H,W
----000EPFR10 [R/W]
B,H,W
----0000
EPFR14 [R/W]
B,H,W
------00
―
―
EPFR26 [R/W]
B,H,W
00000000
EPFR03 [R/W]
B,H,W
---000-0
EPFR07 [R/W]
B,H,W
---00000
EPFR11 [R/W]
B,H,W
----0000
EPFR15 [R/W]
B,H,W
-----000
―
―
EPFR27 [R/W]
B,H,W
---0----
―
―
EPFR34 [R/W]
B,H,W
-----00-
EPFR35 [R/W]
B,H,W
---00000
―
―
―
―
―
EPFR42 [R/W]
B,H,W
------00
EPFR43 [R/W]
B,H,W
0--0000-
EPFR44 [R/W]
B,H,W
-00---0EPFR48 [R/W]
B,H,W
-----0-0
―
EPFR56 [R/W]
B,H,W
-----0-0
EPFR60 [R/W]
B,H,W
----00--
EPFR45 [R/W]
B,H,W
-0000000
EPFR49 [R/W]
B,H,W
-----000
―
EPFR57 [R/W]
B,H,W
-----0-0
EPFR61 [R/W]
B,H,W
-----00-
―
―
EPFR50 [R/W]
B,H,W
------00
―
EPFR58 [R/W]
B,H,W
----00-0
EPFR62 [R/W]
B,H,W
-----00-
EPFR51 [R/W]
B,H,W
---00000
―
EPFR59 [R/W]
B,H,W
----00-0
EPFR63 [R/W]
B,H,W
---0-0--
―
―
―
―
Block
Extended Port
Function Register
Extended Port
Function Register
Reserved
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
Address offset value / Register name
+1
+2
+0
CPCLR9 [R/W] W
11111111 11111111 11111111 11111111
TCDT9 [R/W] W
00000000 00000000 00000000 00000000
000EB4H
000EB8H
TCCSH9 [R/W]
TCCSL9 [R/W] B,H,W
B,H,W
―
-1-00000
0-----00
PPER00 [R/W] B,H,W PPER01 [R/W] B,H,W PPER02 [R/W] B,H,W
000EC0H
00000000
00000000
00000000
PPER04 [R/W] B,H,W PPER05 [R/W] B,H,W PPER06 [R/W] B,H,W
000EC4H
00000000
00000000
00000000
PPER08 [R/W] B,H,W PPER09 [R/W] B,H,W PPER10 [R/W] B,H,W
000EC8H
00000000
00000000
00000000
PPER12 [R/W] B,H,W PPER13 [R/W] B,H,W PPER14 [R/W] B,H,W
000ECCH
00000000
-000--00
-------PPER20 [R/W] B,H,W PPER21 [R/W] B,H,W PPER22 [R/W] B,H,W
000ED0H
00000000
00000000
000--000
PPER24 [R/W] B,H,W PPER25 [R/W] B,H,W PPER26 [R/W] B,H,W
000ED4H
--000000
-0000000
000000-PPER16 [R/W] B,H,W PPER17 [R/W] B,H,W PPER18 [R/W] B,H,W
000ED8H
00000000
00000000
00000000
PPER28 [R/W] B,H,W PPER29 [R/W] B,H,W
000EDCH
―
00000000
00000000
PILR00[R/W] B,H,W PILR01[R/W] B,H,W
000EE0H
―
11-1--111111111
PILR05[R/W] B,H,W
000EE4H
―
―
-----1-000EBCH
000EE8H
―
―
―
000EECH
PILR12[R/W] B,H,W
----1--1
―
―
000EF0H
000EF4H
000EF8H
TCCSH10 [R/W]
B,H,W
0-----00
000EFCH
to
000F0CH
―
000F10H
000F14H
+3
CPCLR10 [R/W] W
11111111 11111111 11111111 11111111
TCDT10 [R/W] W
00000000 00000000 00000000 00000000
TCCSL10 [R/W]
B,H,W
―
-1-00000
―
―
RCRH2 [R/W] H,W RCRL2 [R/W] B,H,W UDCRH2 [R/W] H,W
XXXXXXXX
XXXXXXXX
00000000
CCR2 [R/W] B,H
00000000 -0001000
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Block
Free-run Timer 9
32-bit FRT
―
PPER03 [R/W] B,H,W
00000000
PPER07 [R/W] B,H,W
00000000
Port Pull-up/down
PPER11 [R/W] B,H,W Enable Register
00000000
PPER15 [R/W] B,H,W
--000000
PPER23 [R/W] B,H,W
00000000
PPER27 [R/W] B,H,W
000-0000
Port Pull-up/down
PPER19 [R/W] B,H,W Enable Register
00000000
―
―
―
PILR11[R/W] B,H,W
---1---PILR15[R/W] B,H,W
--1-----
Port Input
Level Register
Free-run Timer 10
32-bit FRT
―
―
Reserved
UDCRL2 [R/W]
B,H,W
00000000
CSR2 [R/W] B
00000000
UpDown Counter 2
2117
Appendix
Address
000F18H
+0
RCRH3 [R/W] H,W RCRL3 [R/W] B,H,W UDCRH3 [R/W] H,W
XXXXXXXX
XXXXXXXX
00000000
CCR3 [R/W] B,H
00000000 -0001000
000F1CH
000F20H
to
000F30H
000F34H,
000F38H
000F3CH
000F40H
000F44H
000F48H
to
000F64H
000F68H
000F6CH
000F70H
000F74H
000F78H,
000F7CH
000F80H
000F84H
Address offset value / Register name
+1
+2
―
Block
UDCRL3 [R/W]
B,H,W
00000000
CSR3 [R/W] B
00000000
UpDown Counter 3
―
―
―
―
Reserved
―
―
―
―
Reserved
―
―
―
OCLS1213 [R/W]
B,H,W
----0000
OCU12,13
Output level
control register
―
―
Port Enable
Register
―
―
KeyCodeRegister
―
―
Reserved
PORTEN [R/W]
B,H,W
―
-------0
KEYCDR [R/W] H
00000000 00000000
―
―
MSCY6 [R] H,W
Input
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Capture 6,7
Cycle measurement
MSCY7 [R] H,W
data register 67
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RCRH0 [W] H,W
RCRL0 [W] B,H,W
UDCRH0 [R] H,W
UDCRL0 [R] B,H,W
XXXXXXXX
XXXXXXXX
00000000
00000000
UpDown Counter 0
CCR0 [R/W] B,H
CSR0 [R/W] B
―
00000000 -0001000
00000000
―
―
RCRH1 [W] H,W
RCRL1 [W] B,H,W
XXXXXXXX
XXXXXXXX
CCR1 [R/W] B,H
00000000 -0001000
―
UDCRH1 [R] H,W
00000000
―
000F88H
―
―
MSCH45 [R]
B,H,W
00000000
000F8CH
―
―
MSCH67 [R]
B,H,W
00000000
2118
+3
―
Reserved
UDCRL1 [R] B,H,W
00000000
UpDown Counter 1
CSR1 [R/W] B
00000000
Input Capture 4,5
MSCL45 [R/W]
32-bit ICU
B,H,W
Cycle and pulse
------00
width measurement
control 45
Input Capture 6,7
MSCL67 [R/W]
32-bit ICU
B,H,W
Cycle and pulse
------00
width measurement
control 67
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
Address offset value / Register name
+1
+2
+0
OCCP10 [R/W] W
00000000 00000000 00000000 00000000
OCCP11 [R/W] W
00000000 00000000 00000000 00000000
OCSH1011 [R/W]
―
B,H,W
---0--00
000F90H
000F94H
000F98H
―
000F9CH
―
―
000FA4H
TCCSH5
[R/W]B,H,W
0-----00
000FB0H
TCCSH6
[R/W]B,H,W
0-----00
000FBCH
TCCSH7
[R/W]B,H,W
0-----00
000FC8H
TCCSH8
[R/W]B,H,W
0-----00
000FD0H
000FD4H
000FD8H
TCCSL6 [R/W]B,H,W
-1-00000
―
TCCSL7 [R/W]B,H,W
-1-00000
―
―
TCCSL8 [R/W]B,H,W
-1-00000
―
OCU10,11
Output level
control register
Free-run Timer 6
32-bit FRT
―
Free-run Timer 7
32-bit FRT
―
Free-run Timer 8
32-bit FRT
―
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
LSYNS2 [R/W] B,H,W LSYNS1 [R/W] B,H,W ICS45 [R/W] B,H,W
--000000
00000000
00000000
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Output Compare
10,11
32-bit OCU
―
CPCLR8 [R/W] W
11111111 11111111 11111111 11111111
TCDT8 [R/W] W
00000000 00000000 00000000 00000000
000FC4H
000FCCH
―
CPCLR7 [R/W] W
11111111 11111111 11111111 11111111
TCDT7 [R/W] W
00000000 00000000 00000000 00000000
000FB8H
000FC0H
TCCSL5 [R/W]B,H,W
-1-00000
Block
Free-run Timer 5
32-bit FRT
CPCLR6 [R/W] W
11111111 11111111 11111111 11111111
TCDT6 [R/W] W
00000000 00000000 00000000 00000000
000FACH
000FB4H
OCSL1011 [R/W]
B,H,W
0000--00
OCLS1011 [R/W]
B,H,W
----0000
CPCLR5 [R/W] W
11111111 11111111 11111111 11111111
TCDT5 [R/W] W
00000000 00000000 00000000 00000000
000FA0H
000FA8H
―
+3
Input
Capture 4,5
32-bit ICU
2119
Appendix
Address
000FDCH
000FE0H
000FE4H
000FE8H
000FECH
000FF0H
000FF4H
000FF8H
000FFCH
001000H
+0
Address offset value / Register name
+1
+2
+3
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS67 [R/W] B,H,W
―
―
―
00000000
IPCP8 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP9 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS89 [R/W] B,H,W
―
―
―
00000000
MSCY8 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY9 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCH89 [R] B,H,W MSCL89 [R/W] B,H,W
―
―
00000000
------00
SACR [R/W] B,H,W PICD [R/W] B,H,W
―
―
-------0
----0011
001004H
to
00112CH
―
―
―
―
001130H
―
―
―
CRCCR [R/W] B,H,W
-0000000
001134H
001138H
00113CH
2120
CRCINIT [R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN [R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR [R] B,H,W
11111111 11111111 11111111 11111111
Block
Input
Capture 6,7
32-bit ICU
Input
Capture 8,9
32-bit ICU
Clock Control
Reserved
CRC calculation
unit
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
001140H
001144H
001148H
00114CH
Address offset value / Register name
+1
+2
+0
SCR16/(IBCR16)
SMR16
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR116/(TDR116))[R/W] B,H,W
-------- --------*3
SACSR16[R/W] B,H,W
0----000 00000000
STMCR16[R/W] B,H,W
00000000 00000000
001150H
― /(SCSTR316)/
(LAMSR16)
[R/W] B,H,W
--------*3
001154H
―
001158H
―/(TBYTE316)/
(LAMESR16)
[R/W] B,H,W
--------*3
00115CH
001160H
001164H
― /(SCSTR216)/
(LAMCR16)
[R/W] B,H,W
--------*3
― /(SCSFR216)
[R/W] B,H,W
--------*3
―/(TBYTE216)/
(LAMERT16)
[R/W] B,H,W
--------*3
BGR16[R/W] H,W
00000000 00000000
FCR116
FCR016
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR16[R/W] B,H,W
00000000 00000000
+3
Block
SSR16
ESCR16/(IBSR16) Multi-UART16
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR016/(TDR016)[R/W] B,H,W
bits.
-------0 00000000*1
STMR16[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR16/SFUR16)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR116)/(SFLR11 /(SCSTR016)/(SFLR01 reset.
6)
6)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR116)
― /(SCSFR016)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE116)/
TBYTE016/(LAMRID
(LAMIER16)
16)/(LAMTID16) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK16)
― /(ISBA16)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE16[R/W] B,H,W
00000000 00000000
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
―
2121
Appendix
Address
001168H
00116CH
001170H
001174H
Address offset value / Register name
+1
+2
+0
SCR17/(IBCR17)
SMR17
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR117/(TDR117))[R/W] B,H,W
-------- --------*3
SACSR17[R/W] B,H,W
0----000 00000000
STMCR17[R/W] B,H,W
00000000 00000000
001178H
― /(SCSTR317)/
(LAMSR17)
[R/W] B,H,W
--------*3
00117CH
―
001180H
―/(TBYTE317)/
(LAMESR17)
[R/W] B,H,W
--------*3
001184H
001188H
00118CH
2122
― /(SCSTR217)/
(LAMCR17)
[R/W] B,H,W
--------*3
― /(SCSFR217)
[R/W] B,H,W
--------*3
―/(TBYTE217)/
(LAMERT17)
[R/W] B,H,W
--------*3
BGR17[R/W] H,W
00000000 00000000
FCR117
FCR017
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR17[R/W] B,H,W
00000000 00000000
+3
Block
SSR17
ESCR17/(IBSR17) Multi-UART17
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR017/(TDR017)[R/W] B,H,W
bits.
-------0 00000000*1
STMR17[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR17/SFUR17)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR117)/(SFLR11 /(SCSTR017)/(SFLR01 reset.
7)
7)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR117)
― /(SCSFR017)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE117)/
TBYTE017/(LAMRID
(LAMIER17)
17)/(LAMTID17) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK17)
― /(ISBA17)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE17[R/W] B,H,W
00000000 00000000
―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
001190H
001194H
001198H
00119CH
Address offset value / Register name
+1
+2
+0
SCR18/(IBCR18)
SMR18
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR118/(TDR118))[R/W] B,H,W
-------- --------*3
SACSR18[R/W] B,H,W
0----000 00000000
STMCR18[R/W] B,H,W
00000000 00000000
0011A0H
― /(SCSTR318)/
(LAMSR18)
[R/W] B,H,W
--------*3
0011A4H
―
0011A8H
―/(TBYTE318)/
(LAMESR18)
[R/W] B,H,W
--------*3
0011ACH
0011B0H
0011B4H
― /(SCSTR218)/
(LAMCR18)
[R/W] B,H,W
--------*3
― /(SCSFR218)
[R/W] B,H,W
--------*3
―/(TBYTE218)/
(LAMERT18)
[R/W] B,H,W
--------*3
BGR18[R/W] H,W
00000000 00000000
FCR118
FCR018
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR18[R/W] B,H,W
00000000 00000000
+3
Block
SSR18
ESCR18/(IBSR18) Multi-UART18
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR018/(TDR018)[R/W] B,H,W
bits.
-------0 00000000*1
STMR18[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR18/SFUR18)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR118)/(SFLR11 /(SCSTR018)/(SFLR01 reset.
8)
8)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR118)
― /(SCSFR018)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE118)/
TBYTE018/(LAMRID
(LAMIER18)
18)/(LAMTID18) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK18)
― /(ISBA18)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE18[R/W] B,H,W
00000000 00000000
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
―
2123
Appendix
Address
0011B8H
0011BCH
0011C0H
0011C4H
Address offset value / Register name
+1
+2
+0
SCR19/(IBCR19)
SMR19
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR119/(TDR119))[R/W] B,H,W
-------- --------*3
SACSR19[R/W] B,H,W
0----000 00000000
STMCR19[R/W] B,H,W
00000000 00000000
0011C8H
― /(SCSTR319)/
(LAMSR19)
[R/W] B,H,W
--------*3
0011CCH
―
0011D0H
―/(TBYTE319)/
(LAMESR19)
[R/W] B,H,W
--------*3
0011DCH
FCR119
FCR019
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR19[R/W] B,H,W
00000000 00000000
0011E0H
to
0011FCH
―
001200H
TCGS [R/W] B,H,W
------00
001204H
001208H
00120CH
001210H
001214H
001218H
2124
― /(SCSFR219)
[R/W] B,H,W
--------*3
―/(TBYTE219)/
(LAMERT19)
[R/W] B,H,W
--------*3
BGR19[R/W] H,W
00000000 00000000
0011D4H
0011D8H
― /(SCSTR219)/
(LAMCR19)
[R/W] B,H,W
--------*3
―
+3
Block
SSR19
ESCR19/(IBSR19) Multi-UART19
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR019/(TDR019)[R/W] B,H,W
bits.
-------0 00000000*1
STMR19[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR19/SFUR19)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR119)/(SFLR11 /(SCSTR019)/(SFLR01 reset.
9)
9)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR119)
― /(SCSFR019)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE119)/
TBYTE019/(LAMRID
(LAMIER19)
19)/(LAMTID19) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK19)
― /(ISBA19)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE19[R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved
16-bit Free-run
TCGSE [R/W] B,H,W
timer synchronous
-----000
activation
CPCLRB0/CPCLR0 [W] H,W
TCDT0 [R/W] H,W
11111111 11111111
00000000 00000000
16-bit Free-run
timer 0
TCCS0 [R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1 [W] H,W
TCDT1 [R/W] H,W
11111111 11111111
00000000 00000000
16-bit Free-run
timer 1
TCCS1 [R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2 [W] H,W
TCDT2 [R/W] H,W
11111111 11111111
00000000 00000000
16-bit Free-run
timer 2
TCCS2 [R/W] B,H,W
00000000 01000000 ----0000 -------―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
00121CH
to
001230H
001234H
001238H
00123CH
001240H
001244H
001248H
00124CH
001250H
001254H
001258H
00125CH
001260H
001264H
to
001278H
+0
―
―
―
+3
―
FRS0 [R/W] B,H,W
-------- --00--00 --00--00 --00--00
FRS1 [R/W] B,H,W
―
--00--00 --00--00
FRS2 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS3 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS4 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
―
―
―
―
OCCPB0/OCCP0 [R/W] H,W
OCCPB1/OCCP1 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD01 [R/W]
OCS01 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
OCCPB2/OCCP2 [R/W] H,W
OCCPB3/OCCP3 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD23 [R/W]
OCS23 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
OCCPB4/OCCP4 [R/W] H,W
OCCPB5/OCCP5 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD45 [R/W]
OCS45 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
―
―
IPCP0 [R] H,W
00000000 00000000
ICS01 [R/W] B,H,W
------00 00000000
IPCP2 [R] H,W
00000000 00000000
ICS23 [R/W] B,H,W
------00 00000000
00127CH
001280H
001284H
001288H
00128CH
to
001298H
00129CH
Address offset value / Register name
+1
+2
―
―
IPCP1 [R] H,W
00000000 00000000
LSYNS [R/W] B,H,W
―
----0000
IPCP3 [R] H,W
00000000 00000000
―
―
Block
Reserved
16-bit Free-run
timer selection
Reserved
16-bit Output
compare 0/1
16-bit Output
compare 2/3
16-bit Output
compare 4/5
Reserved
16-bit Input
capture 0/1
16-bit Input
capture 2/3
―
―
―
―
Reserved
―
―
―
―
Reserved
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
2125
Appendix
Address
0012A0H
0012A4H
0012A8H
0012ACH
0012B0H
0012B4H
0012B8H
to
0012CCH
+0
―
0012D8H
0012DCH
0012E0H
001308H
00130CH
001310H
001314H
001318H
00131CH
2126
―
―
―
FRS5 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS6 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS7 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS10 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS11 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
0012D4H
001304H
+3
TMRR0 [R/W] H,W
TMRR1 [R/W] H,W
00000000 00000001
00000000 00000001
TMRR2 [R/W] H,W
―
―
00000000 00000001
DTSCR0 [R/W]
DTSCR1 [R/W] B,H,W DTSCR2 [R/W] B,H,W
B,H,W
―
00000000
00000000
00000000
DTMNS0 [R/W]
DTIR0 [R/W] B,H,W
―
―
B,H,W
000000-00---000
SIGCR10 [R/W]
SIGCR20 [R/W]
―
B,H,W
―
B,H,W
00000000
000000-1
PICS0 [R/W] B,H,W
000000-- -------- -------- --------
0012D0H
0012E4H
to
0012FCH
001300H
Address offset value / Register name
+1
+2
―
―
―
―
Waveform
generator
0/1/2
Reserved
16-bit Free-run
timer selection
A/D activation
compare
―
―
ADTSS0[R/W]
B,H,W
-------0
Block
Reserved
Reserved
―
―
ADTSE0[R/W] B,H,W
00000000 00000000 00000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
12-bit A/D
converter
1/2 unit
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
001320H
001324H
001328H
00132CH
001330H
001334H
001338H
00133CH
001340H
001344H
001348H
00134CH
001350H
001354H
001358H
00135CH
001360H
001364H
001368H
+0
Address offset value / Register name
+1
+2
ADCOMP10/ADCOMPB10[R/W] H,W
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP16/ADCOMPB16[R/W] H,W
00000000 00000000
ADCOMP18/ADCOMPB18[R/W] H,W
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W
00000000 00000000
ADCOMP22/ADCOMPB22[R/W] H,W
00000000 00000000
ADCOMP24/ADCOMPB24[R/W] H,W
00000000 00000000
ADCOMP26/ADCOMPB26[R/W] H,W
00000000 00000000
ADCOMP28/ADCOMPB28[R/W] H,W
00000000 00000000
ADCOMP30/ADCOMPB30[R/W] H,W
00000000 00000000
ADTCS0[R/W] B,H,W
00000000 0010---ADTCS2[R/W] B,H,W
00000000 0010---ADTCS4[R/W] B,H,W
00000000 0010---ADTCS6[R/W] B,H,W
00000000 0010---ADTCS8[R/W] B,H,W
00000000 0010---ADTCS10[R/W] B,H,W
00000000 0010---ADTCS12[R/W] B,H,W
00000000 0010---ADTCS14[R/W] B,H,W
00000000 0010----
+3
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
ADCOMP15/ADCOMPB15[R/W] H,W
00000000 00000000
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
ADCOMP25/ADCOMPB25[R/W] H,W
00000000 00000000
ADCOMP27/ADCOMPB27[R/W] H,W
00000000 00000000
ADCOMP29/ADCOMPB29[R/W] H,W
00000000 00000000
ADCOMP31/ADCOMPB31[R/W] H,W
00000000 00000000
ADTCS1[R/W] B,H,W
00000000 0010---ADTCS3[R/W] B,H,W
00000000 0010---ADTCS5[R/W] B,H,W
00000000 0010---ADTCS7[R/W] B,H,W
00000000 0010---ADTCS9[R/W] B,H,W
00000000 0010---ADTCS11[R/W] B,H,W
00000000 0010---ADTCS13[R/W] B,H,W
00000000 0010---ADTCS15[R/W] B,H,W
00000000 0010----
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Block
12-bit A/D
converter
1/2 unit
2127
Appendix
Address
00136CH
001370H
001374H
001378H
00137CH
001380H
001384H
001388H
00138CH
001390H
001394H
001398H
00139CH
0013A0H
0013A4H
0013A8H
0013ACH
0013B0H
0013B4H
0013B8H
0013BCH
0013C0H
0013C4H
0013C8H
2128
+0
Address offset value / Register name
+1
+2
ADTCS16[R/W] B,H,W
00000000 0010---ADTCS18[R/W] B,H,W
00000000 0010---ADTCS20[R/W] B,H,W
00000000 0010---ADTCS22[R/W] B,H,W
00000000 0010---ADTCS24[R/W] B,H,W
00000000 0010---ADTCS26[R/W] B,H,W
00000000 0010---ADTCS28[R/W] B,H,W
00000000 0010---ADTCS30[R/W] B,H,W
00000000 0010---ADTCD0[R] B,H,W
10--0000 00000000
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD14[R] B,H,W
10--0000 00000000
ADTCD16[R] B,H,W
10--0000 00000000
ADTCD18[R] B,H,W
10--0000 00000000
ADTCD20[R] B,H,W
10--0000 00000000
ADTCD22[R] B,H,W
10--0000 00000000
ADTCD24[R] B,H,W
10--0000 00000000
ADTCD26[R] B,H,W
10--0000 00000000
ADTCD28[R] B,H,W
10--0000 00000000
ADTCD30[R] B,H,W
10--0000 00000000
+3
ADTCS17[R/W] B,H,W
00000000 0010---ADTCS19[R/W] B,H,W
00000000 0010---ADTCS21[R/W] B,H,W
00000000 0010---ADTCS23[R/W] B,H,W
00000000 0010---ADTCS25[R/W] B,H,W
00000000 0010---ADTCS27[R/W] B,H,W
00000000 0010---ADTCS29[R/W] B,H,W
00000000 0010---ADTCS31[R/W] B,H,W
00000000 0010---ADTCD1[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
ADTCD15[R] B,H,W
10--0000 00000000
ADTCD17[R] B,H,W
10--0000 00000000
ADTCD19[R] B,H,W
10--0000 00000000
ADTCD21[R] B,H,W
10--0000 00000000
ADTCD23[R] B,H,W
10--0000 00000000
ADTCD25[R] B,H,W
10--0000 00000000
ADTCD27[R] B,H,W
10--0000 00000000
ADTCD29[R] B,H,W
10--0000 00000000
ADTCD31[R] B,H,W
10--0000 00000000
Block
12-bit A/D
converter
1/2 unit
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
0013CCH
0013D0H
0013D4H
0013D8H
0013DCH
0013E0H
0013E4H
0013E8H
0013ECH
0013F0H
0013F4H
0013F8H
0013FCH
001400H
001404H
001408H
00140CH
001410H
001414H
001418H
+0
Address offset value / Register name
+1
+2
ADTECS0[R/W] B,H,W
-------0 ---00000
ADTECS2[R/W] B,H,W
-------0 ---00000
ADTECS4[R/W] B,H,W
-------0 ---00000
ADTECS6[R/W] B,H,W
-------0 ---00000
ADTECS8[R/W] B,H,W
-------0 ---00000
ADTECS10[R/W] B,H,W
-------0 ---00000
ADTECS12[R/W] B,H,W
-------0 ---00000
ADTECS14[R/W] B,H,W
-------0 ---00000
ADTECS16[R/W] B,H,W
-------0 ---00000
ADTECS18[R/W] B,H,W
-------0 ---00000
ADTECS20[R/W] B,H,W
-------0 ---00000
ADTECS22[R/W] B,H,W
-------0 ---00000
ADTECS24[R/W] B,H,W
-------0 ---00000
ADTECS26[R/W] B,H,W
-------0 ---00000
ADTECS28[R/W] B,H,W
-------0 ---00000
ADTECS30[R/W] B,H,W
-------0 ---00000
ADRCUT0[R/W] B,H,W
----0000 00000000
ADRCUT1[R/W] B,H,W
----0000 00000000
ADRCUT2[R/W] B,H,W
----0000 00000000
ADRCUT3[R/W] B,H,W
----0000 00000000
+3
ADTECS1[R/W] B,H,W
-------0 ---00000
ADTECS3[R/W] B,H,W
-------0 ---00000
ADTECS5[R/W] B,H,W
-------0 ---00000
ADTECS7[R/W] B,H,W
-------0 ---00000
ADTECS9[R/W] B,H,W
-------0 ---00000
ADTECS11[R/W] B,H,W
-------0 ---00000
ADTECS13[R/W] B,H,W
-------0 ---00000
ADTECS15[R/W] B,H,W
-------0 ---00000
ADTECS17[R/W] B,H,W
-------0 ---00000
ADTECS19[R/W] B,H,W
-------0 ---00000
ADTECS21[R/W] B,H,W
-------0 ---00000
ADTECS23[R/W] B,H,W
-------0 ---00000
ADTECS25[R/W] B,H,W
-------0 ---00000
ADTECS27[R/W] B,H,W
-------0 ---00000
ADTECS29[R/W] B,H,W
-------0 ---00000
ADTECS31[R/W] B,H,W
-------0 ---00000
ADRCLT0[R/W] B,H,W
----0000 00000000
ADRCLT1[R/W] B,H,W
----0000 00000000
ADRCLT2[R/W] B,H,W
----0000 00000000
ADRCLT3[R/W] B,H,W
----0000 00000000
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Block
12-bit A/D
converter
1/2 unit
2129
Appendix
Address
00141CH
001420H
001424H
001428H
00142CH
001430H
001434H
001438H
00143CH
001440H
001444H
001448H
00144CH
001450H
001454H
001458H
00145CH
001460H
2130
+0
ADRCCS0[R/W]
B,H,W
00000000
ADRCCS4[R/W]
B,H,W
00000000
ADRCCS8[R/W]
B,H,W
00000000
ADRCCS12[R/W]
B,H,W
00000000
ADRCCS16[R/W]
B,H,W
00000000
ADRCCS20[R/W]
B,H,W
00000000
ADRCCS24[R/W]
B,H,W
00000000
ADRCCS28[R/W]
B,H,W
00000000
Address offset value / Register name
+1
+2
ADRCCS1[R/W]
ADRCCS2[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS5[R/W]
ADRCCS6[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS9[R/W]
ADRCCS10[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS13[R/W]
ADRCCS14[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS17[R/W]
ADRCCS18[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS21[R/W]
ADRCCS22[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS25[R/W]
ADRCCS26[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS29[R/W]
ADRCCS30[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCOT0[R] B,H,W
00000000 00000000 00000000 00000000
ADRCIF0[R,W] B,H,W
00000000 00000000 00000000 00000000
+3
ADRCCS3[R/W]
B,H,W
00000000
ADRCCS7[R/W]
B,H,W
00000000
ADRCCS11[R/W]
B,H,W
00000000
ADRCCS15[R/W]
B,H,W
00000000
ADRCCS19[R/W]
B,H,W
00000000
ADRCCS23[R/W]
B,H,W
00000000
ADRCCS27[R/W]
B,H,W
00000000
ADRCCS31[R/W]
B,H,W
00000000
Block
12-bit A/D
converter
1/2 unit
ADSCANS0[R/W]
B,H,W
―
―
―
000----ADNCS0[R/W] B,H,W ADNCS1[R/W] B,H,W ADNCS2[R/W] B,H,W ADNCS3[R/W] B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS4[R/W] B,H,W ADNCS5[R/W] B,H,W ADNCS6[R/W] B,H,W ADNCS7[R/W] B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS10[R/W]
ADNCS11[R/W]
ADNCS8[R/W] B,H,W ADNCS9[R/W] B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS12[R/W]
ADNCS13[R/W]
ADNCS14[R/W]
ADNCS15[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADPRTF0[R] B,H,W
00000000 00000000 00000000 00000000
ADEOCF0[R] B,H,W
11111111 11111111 11111111 11111111
ADCS0[R] B,H,W
ADCH0[R] B,H,W ADMD0[R/W] B,H,W
0------- ----------00000
0---0000
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
001464H
001468H
+0
Address offset value / Register name
+1
+2
ADSTPCS0[R/W]
B,H,W
00000000
ADSTPCS4[R/W]
B,H,W
00000000
ADSTPCS1[R/W]
B,H,W
00000000
ADSTPCS5[R/W]
B,H,W
00000000
001474H
001478H
00147CH
001480H
001484H
001488H
00148CH
001490H
001494H
001498H
00149CH
0014A0H
0014A4H
0014A8H
0014ACH
0014B0H
0014B4H
0014B8H
0014BCH
ADSTPCS2[R/W]
B,H,W
00000000
ADSTPCS6[R/W]
B,H,W
00000000
ADSTPCS3[R/W]
B,H,W
00000000
ADSTPCS7[R/W]
B,H,W
00000000
―
―
Block
12-bit A/D
converter
1/2 unit
―
00146CH
001470H
+3
ADTSS1[R/W] B,H,W
-------0
―
ADTSE1[R/W] B,H,W
00000000 00000000 00000000 00000000
ADCOMP32/ADCOMPB32[R/W] H,W
ADCOMP33/ADCOMPB33[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP34/ADCOMPB34[R/W] H,W
ADCOMP35/ADCOMPB35[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP36/ADCOMPB36[R/W] H,W
ADCOMP37/ADCOMPB37[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP38/ADCOMPB38[R/W] H,W
ADCOMP39/ADCOMPB39[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP40/ADCOMPB40[R/W] H,W
ADCOMP41/ADCOMPB41[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP42/ADCOMPB42[R/W] H,W
ADCOMP43/ADCOMPB43[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP44/ADCOMPB44[R/W] H,W
ADCOMP45/ADCOMPB45[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP46/ADCOMPB46[R/W] H,W
ADCOMP47/ADCOMPB47[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP48/ADCOMPB48[R/W] H,W
ADCOMP49/ADCOMPB49[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP50/ADCOMPB50[R/W] H,W
ADCOMP51/ADCOMPB51[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP52/ADCOMPB52[R/W] H,W
ADCOMP53/ADCOMPB53[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP54/ADCOMPB54[R/W] H,W
ADCOMP55/ADCOMPB55[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP56/ADCOMPB56[R/W] H,W
ADCOMP57/ADCOMPB57[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP58/ADCOMPB58[R/W] H,W
ADCOMP59/ADCOMPB59[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP60/ADCOMPB60[R/W] H,W
ADCOMP61/ADCOMPB61[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP62/ADCOMPB62[R/W] H,W
ADCOMP63/ADCOMPB63[R/W] H,W
00000000 00000000
00000000 00000000
ADTCS32[R/W] B,H,W
ADTCS33[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS34[R/W] B,H,W
ADTCS35[R/W] B,H,W
00000000 0010---00000000 0010----
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
12-bit A/D
converter
2/2 unit
2131
Appendix
Address
0014C0H
0014C4H
0014C8H
0014CCH
0014D0H
0014D4H
0014D8H
0014DCH
0014E0H
0014E4H
0014E8H
0014ECH
0014F0H
0014F4H
0014F8H
0014FCH
001500H
001504H
001508H
00150CH
001510H
001514H
001518H
00151CH
2132
+0
Address offset value / Register name
+1
+2
ADTCS36[R/W] B,H,W
00000000 0010---ADTCS38[R/W] B,H,W
00000000 0010---ADTCS40[R/W] B,H,W
00000000 0010---ADTCS42[R/W] B,H,W
00000000 0010---ADTCS44[R/W] B,H,W
00000000 0010---ADTCS46[R/W] B,H,W
00000000 0010---ADTCS48[R/W] B,H,W
00000000 0010---ADTCS50[R/W] B,H,W
00000000 0010---ADTCS52[R/W] B,H,W
00000000 0010---ADTCS54[R/W] B,H,W
00000000 0010---ADTCS56[R/W] B,H,W
00000000 0010---ADTCS58[R/W] B,H,W
00000000 0010---ADTCS60[R/W] B,H,W
00000000 0010---ADTCS62[R/W] B,H,W
00000000 0010---ADTCD32[R] B,H,W
10--0000 00000000
ADTCD34[R] B,H,W
10--0000 00000000
ADTCD36[R] B,H,W
10--0000 00000000
ADTCD38[R] B,H,W
10--0000 00000000
ADTCD40[R] B,H,W
10--0000 00000000
ADTCD42[R] B,H,W
10--0000 00000000
ADTCD44[R] B,H,W
10--0000 00000000
ADTCD46[R] B,H,W
10--0000 00000000
ADTCD48[R] B,H,W
10--0000 00000000
ADTCD50[R] B,H,W
10--0000 00000000
+3
ADTCS37[R/W] B,H,W
00000000 0010---ADTCS39[R/W] B,H,W
00000000 0010---ADTCS41[R/W] B,H,W
00000000 0010---ADTCS43[R/W] B,H,W
00000000 0010---ADTCS45[R/W] B,H,W
00000000 0010---ADTCS47[R/W] B,H,W
00000000 0010---ADTCS49[R/W] B,H,W
00000000 0010---ADTCS51[R/W] B,H,W
00000000 0010---ADTCS53[R/W] B,H,W
00000000 0010---ADTCS55[R/W] B,H,W
00000000 0010---ADTCS57[R/W] B,H,W
00000000 0010---ADTCS59[R/W] B,H,W
00000000 0010---ADTCS61[R/W] B,H,W
00000000 0010---ADTCS63[R/W] B,H,W
00000000 0010---ADTCD33[R] B,H,W
10--0000 00000000
ADTCD35[R] B,H,W
10--0000 00000000
ADTCD37[R] B,H,W
10--0000 00000000
ADTCD39[R] B,H,W
10--0000 00000000
ADTCD41[R] B,H,W
10--0000 00000000
ADTCD43[R] B,H,W
10--0000 00000000
ADTCD45[R] B,H,W
10--0000 00000000
ADTCD47[R] B,H,W
10--0000 00000000
ADTCD49[R] B,H,W
10--0000 00000000
ADTCD51[R] B,H,W
10--0000 00000000
Block
12-bit A/D
converter
2/2 unit
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
001520H
001524H
001528H
00152CH
001530H
001534H
001538H
00153CH
001540H
001544H
001548H
00154CH
001550H
001554H
001558H
00155CH
001560H
001564H
001568H
00156CH
001570H
001574H
001578H
+0
Address offset value / Register name
+1
+2
ADTCD52[R] B,H,W
10--0000 00000000
ADTCD54[R] B,H,W
10--0000 00000000
ADTCD56[R] B,H,W
10--0000 00000000
ADTCD58[R] B,H,W
10--0000 00000000
ADTCD60[R] B,H,W
10--0000 00000000
ADTCD62[R] B,H,W
10--0000 00000000
ADTECS32[R/W] B,H,W
-------0 ---00000
ADTECS34[R/W] B,H,W
-------0 ---00000
ADTECS36[R/W] B,H,W
-------0 ---00000
ADTECS38[R/W] B,H,W
-------0 ---00000
ADTECS40[R/W] B,H,W
-------0 ---00000
ADTECS42[R/W] B,H,W
-------0 ---00000
ADTECS44[R/W] B,H,W
-------0 ---00000
ADTECS46[R/W] B,H,W
-------0 ---00000
ADTECS48[R/W] B,H,W
-------0 ---00000
ADTECS50[R/W] B,H,W
-------0 ---00000
ADTECS52[R/W] B,H,W
-------0 ---00000
ADTECS54[R/W] B,H,W
-------0 ---00000
ADTECS56[R/W] B,H,W
-------0 ---00000
ADTECS58[R/W] B,H,W
-------0 ---00000
ADTECS60[R/W] B,H,W
-------0 ---00000
ADTECS62[R/W] B,H,W
-------0 ---00000
ADRCUT4[R/W] B,H,W
----0000 00000000
+3
ADTCD53[R] B,H,W
10--0000 00000000
ADTCD55[R] B,H,W
10--0000 00000000
ADTCD57[R] B,H,W
10--0000 00000000
ADTCD59[R] B,H,W
10--0000 00000000
ADTCD61[R] B,H,W
10--0000 00000000
ADTCD63[R] B,H,W
10--0000 00000000
ADTECS33[R/W] B,H,W
-------0 ---00000
ADTECS35[R/W] B,H,W
-------0 ---00000
ADTECS37[R/W] B,H,W
-------0 ---00000
ADTECS39[R/W] B,H,W
-------0 ---00000
ADTECS41[R/W] B,H,W
-------0 ---00000
ADTECS43[R/W] B,H,W
-------0 ---00000
ADTECS45[R/W] B,H,W
-------0 ---00000
ADTECS47[R/W] B,H,W
-------0 ---00000
ADTECS49[R/W] B,H,W
-------0 ---00000
ADTECS51[R/W] B,H,W
-------0 ---00000
ADTECS53[R/W] B,H,W
-------0 ---00000
ADTECS55[R/W] B,H,W
-------0 ---00000
ADTECS57[R/W] B,H,W
-------0 ---00000
ADTECS59[R/W] B,H,W
-------0 ---00000
ADTECS61[R/W] B,H,W
-------0 ---00000
ADTECS63[R/W] B,H,W
-------0 ---00000
ADRCLT4[R/W] B,H,W
----0000 00000000
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Block
12-bit A/D
converter
2/2 unit
2133
Appendix
Address
00157CH
001580H
001584H
001588H
00158CH
001590H
001594H
001598H
00159CH
0015A0H
0015A4H
0015A8H
0015ACH
0015B0H
0015B4H
0015B8H
0015BCH
2134
+0
Address offset value / Register name
+1
+2
+3
ADRCUT5[R/W] B,H,W
ADRCLT5[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCUT6[R/W] B,H,W
ADRCLT6[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCUT7[R/W] B,H,W
ADRCLT7[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCCS32[R/W]
ADRCCS33[R/W]
ADRCCS34[R/W]
ADRCCS35[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS36[R/W]
ADRCCS37[R/W]
ADRCCS38[R/W]
ADRCCS39[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS40[R/W]
ADRCCS41[R/W]
ADRCCS42[R/W]
ADRCCS43[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS44[R/W]
ADRCCS45[R/W]
ADRCCS46[R/W]
ADRCCS47[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS48[R/W]
ADRCCS49[R/W]
ADRCCS50[R/W]
ADRCCS51[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS52[R/W]
ADRCCS53[R/W]
ADRCCS54[R/W]
ADRCCS55[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS56[R/W]
ADRCCS57[R/W]
ADRCCS58[R/W]
ADRCCS59[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS60[R/W]
ADRCCS61[R/W]
ADRCCS62[R/W]
ADRCCS63[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCOT1 [R] B,H,W
00000000 00000000 00000000 00000000
ADRCIF1 [R,W] B,H,W
00000000 00000000 00000000 00000000
ADSCANS1 [R/W]
B,H,W
―
―
―
000----ADNCS16 [R/W]
ADNCS17 [R/W]
ADNCS18 [R/W]
ADNCS19 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS20 [R/W]
ADNCS21 [R/W]
ADNCS22 [R/W]
ADNCS23 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS24 [R/W]
ADNCS25 [R/W]
ADNCS26 [R/W]
ADNCS27 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
Block
12-bit A/D
converter
2/2 unit
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
0015C0H
0015C4H
0015C8H
0015CCH
0015D0H
0015D4H
0015D8H
to
00174CH
001750H
001754H
001758H
00175CH
001760H
001764H
001768H
00176CH
001770H
001774H
Address offset value / Register name
+1
+2
+0
+3
ADNCS29 [R/W]
ADNCS30 [R/W]
ADNCS31 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADPRTF1 [R] B,H,W
00000000 00000000 00000000 00000000
ADEOCF1 [R] B,H,W
11111111 11111111 11111111 11111111
ADCS1 [R] B,H,W
ADCH1 [R] B,H,W ADMD1 [R/W] B,H,W
0------- ----------00000
0---0000
ADSTPCS8 [R/W]
ADSTPCS9 [R/W]
ADSTPCS10 [R/W] ADSTPCS11 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADSTPCS12[R/W]
ADSTPCS13[R/W]
ADSTPCS14[R/W]
ADSTPCS15[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
Block
ADNCS28 [R/W]
B,H,W
0-000-00
―
―
SCR0/(IBCR0)[R/W]
SMR0[R/W]
B,H,W
B,H,W
0--00000
000-00-0
― /(RDR10/(TDR10))[R/W] B,H,W
-------- --------*3
SACSR0[R/W] B,H,W
0----000 00000000
STMCR0[R/W] B,H,W
00000000 00000000
― /(SCSTR30)/
― /(SCSTR20)/
(LAMSR0)
(LAMCR0)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR20)
―
[R/W] B,H,W
--------*3
―/(TBYTE30)/
―/(TBYTE20)
(LAMESR0)
/(LAMERT0)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR0[R/W] H, W
00000000 00000000
FCR10[R/W]
FCR00[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR0[R/W] B,H,W
00000000 00000000
―
―
12-bit A/D
converter
2/2 unit
Reserved
SSR0[R/W]
ESCR0/(IBSR0)[R/W] Multi-UART0
B,H,W
B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR00/(TDR00)[R/W] B,H,W
bits.
-------0 00000000*1
STMR0[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR0/SFUR0)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR10)
― /(SCSTR00)/
reset.
/(SFLR10)
(SFLR00)
[R/W] B,H,W
--------*3
― /(SCSFR10)
[R/W] B,H,W
--------*3
―/(TBYTE10)/
(LAMIER0)
[R/W] B,H,W
--------*3
― /(ISMK0)
[R/W] B,H,W
--------*2
[R/W] B,H,W
*3: Reserved
--------*3
because CSIO
― /(SCSFR00)
mode is not set
[R/W] B,H,W
3
immediately after
--------*
TBYTE00/(LAMRID0) reset.
/(LAMTID0)
*4: Reserved
[R/W] B,H,W
because LIN2.1
00000000
mode is not set
― /(ISBA0)
immediately after
[R/W] B,H,W
2
reset.
--------*
FBYTE0[R/W] B,H,W
00000000 00000000
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
―
2135
Appendix
Address
001778H
00177CH
001780H
001784H
001788H
00178CH
001790H
001794H
001798H
00179CH
2136
+0
Address offset value / Register name
+1
+2
SCR1/(IBCR1) [R/W]
SMR1[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR11/(TDR11))[R/W] B,H,W
-------- --------*3
SACSR1[R/W] B,H,W
0----000 00000000
STMCR1[R/W] B,H,W
00000000 00000000
― /(SCSTR31)/
― /(SCSTR21)/
(LAMSR1)
(LAMCR1)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR21)[R/W]
―
B,H,W
--------*3
―/(TBYTE31)/
―/(TBYTE21)/
(LAMESR1)
(LAMERT1)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR1[R/W] H,W
00000000 00000000
FCR11[R/W]
FCR01[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR1[R/W] B,H,W
00000000 00000000
+3
Block
ESCR1/(IBSR1)[R/W] Multi-UART1
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR01/(TDR01)[R/W] B,H,W
bits.
-------0 00000000*1
STMR1[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR1/SFUR1)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR11)/
― /(SCSTR01)/
reset.
(SFLR11)
(SFLR01)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR11)
― /(SCSFR01)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE11)/
TBYTE01/(LAMRID1) reset.
(LAMIER1)
/(LAMTID1)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK1)[R/W]
― /(ISBA1)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR1[R/W] B,H,W
0-000011
FBYTE1[R/W] B,H,W
00000000 00000000
―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
0017A0H
0017A4H
0017A8H
0017ACH
0017B0H
0017B4H
0017B8H
0017BCH
0017C0H
0017C4H
+0
Address offset value / Register name
+1
+2
SCR2/(IBCR2)[R/W]
SMR2[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR12/(TDR12))[R/W] B,H,W
-------- --------*3
SACSR2[R/W] B,H,W
0----000 00000000
STMCR2[R/W] B,H,W
00000000 00000000
― /(SCSTR32)/
― /(SCSTR22)/
(LAMSR2)
(LAMCR2)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR22)
―
[R/W] B,H,W
--------*3
―/(TBYTE32)/
―/(TBYTE22)/
(LAMESR2)
(LAMERT2)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR2[R/W] H, W
00000000 00000000
FCR12[R/W]
FCR02[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR2[R/W] B,H,W
00000000 00000000
+3
Block
ESCR2/(IBSR2)[R/W] Multi-UART2
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR02/(TDR02)[R/W] B,H,W
bits.
-------0 00000000*1
STMR2[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR2/SFUR2)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR12)/
― /(SCSTR02)/
reset.
(SFLR12)
(SFLR02)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR12)
― /(SCSFR02)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE12)/
TBYTE02/(LAMRID2) reset.
(LAMIER2)
/(LAMTID2)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK2)[R/W]
― /(ISBA2)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR2[R/W] B,H,W
0-000011
FBYTE2[R/W] B,H,W
00000000 00000000
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
―
2137
Appendix
Address
0017C8H
0017CCH
0017D0H
0017D4H
0017D8H
0017DCH
0017E0H
0017E4H
0017E8H
0017ECH
2138
+0
Address offset value / Register name
+1
+2
SCR3/(IBCR3) [R/W]
SMR3[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR13/(TDR13))[R/W] B,H,W
-------- --------*3
SACSR3[R/W] B,H,W
0----000 00000000
STMCR3[R/W] B,H,W
00000000 00000000
― /(SCSTR33)/
― /(SCSTR23)/
(LAMSR3)
(LAMCR3)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR23)
―
[R/W] B,H,W
--------*3
―/(TBYTE33)/
―/(TBYTE23)/
(LAMESR3)
(LAMERT3)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR3[R/W] H, W
00000000 00000000
FCR13[R/W]
FCR03[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR3[R/W] B,H,W
00000000 00000000
+3
Block
ESCR3/(IBSR3)[R/W] Multi-UART3
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR03/(TDR03)[R/W] B,H,W
bits.
-------0 00000000*1
STMR3[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR3/SFUR3)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR13)/
― /(SCSTR03)/
reset.
(SFLR13)
(SFLR03)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR13)
― /(SCSFR03)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE13)/
TBYTE03/(LAMRID3) reset.
(LAMIER3)
/(LAMTID3)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK3)[R/W]
― /(ISBA3)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR3[R/W] B,H,W
0-000011
FBYTE3[R/W] B,H,W
00000000 00000000
―
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
Appendix
Address
0017F0H
0017F4H
0017F8H
0017FCH
001800H
001804H
001808H
00180CH
001810H
001814H
+0
Address offset value / Register name
+1
+2
SCR4/(IBCR4) [R/W]
SMR4[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR14/(TDR14))[R/W] B,H,W
-------- --------*3
SACSR4[R/W] B,H,W
0----000 00000000
STMCR4[R/W] B,H,W
00000000 00000000
― /(SCSTR34)/
― /(SCSTR24)/
(LAMSR4)
(LAMCR4)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR24)
―
[R/W] B,H,W
--------*3
―/(TBYTE34)/
―/(TBYTE24)/
(LAMESR4)
(LAMERT4)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR4[R/W] H, W
00000000 00000000
FCR14[R/W]
FCR04[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR4[R/W] B,H,W
00000000 00000000
+3
Block
ESCR4/(IBSR4)[R/W] Multi-UART4
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR04/(TDR04)[R/W] B,H,W
bits.
-------0 00000000*1
STMR4[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR4/SFUR4)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR14)/
― /(SCSTR04)/
reset.
(SFLR14)
(SFLR04)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR14)
― /(SCSFR04)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE14)/
TBYTE04/(LAMRID4) reset.
(LAMIER4)
/(LAMTID4)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK4)[R/W]
― /(ISBA4)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR4[R/W] B,H,W
0-000011
FBYTE4[R/W] B,H,W
00000000 00000000
―
MB91F527/MB91F528 Hardware Manual, Doc. No. 002-05578 Rev. *A
―
2139
Appendix
Address
001818H
00181CH
001820H
001824H
001828H
00182CH
001830H
001834H
001838H
00183CH
2140
+0
Address offset value / Register name
+1
+2
SCR5/(IBCR5) [R/W]
SMR5[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR15/(TDR15))[R/W] B,H,W
-------- --------*3
SACSR5[R/W] B,H,W
0----000 00000000
STMCR5[R/W] B,H,W
00000000 00000000
― /(SCSTR35)/
― /(SCSTR25)/
(LAMSR5)
(LAMCR5)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR25)
―
[R/W] B,H,W
--------*3
―/(TBYTE35)/
―/(TBYTE25)/
(LAMESR5)
(LAMERT5)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR5[R/W] H, W
00000000 00000000
FCR15[R/W]
FCR05[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR5[R/W] B,H,W
00000000 00000000
+3
Block
ESCR5/(IBSR5)[R/W] Multi-UART5
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR05/(TDR05)[R/W] B,H,W
bits.
-------0 00000000*1
STMR5[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR5/SFUR5)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR15)/
― /(SCSTR05)/
reset.
(SFLR15)
(SFLR05)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR15)
― /(SCSFR05)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE15)/
TBYTE05/(LAMRID5) reset.
(LAMIER5)
/(LAMTID5)
*4: Reserved
[R/W] B,H,W
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