CY96F386RSBPMC-GS-UJE2

CY96380 Series F2MC-16FX 16-bit Proprietary Microcontroller CY96380 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology ■ Low Voltage Reset 0.18 μm CMOS ■ CPU 2 ■ F MC-16FX Reset is generated when supply voltage is below minimum. Code Security CPU ■ ■ Up to 56 MHz internal, 17.8 ns instruction cycle time ■ Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) Protects ROM content from unintended read-out Memory Patch Function ■ Replaces ROM content ■ Can also be used to implement embedded debug support ■ 8-byte instruction execution queue DMA ■ Signed multiply (16-bit  16-bit) and divide (32-bit/16-bit) instructions available ■ System Clock Automatic transfer function independent of CPU, can be assigned freely to resources Interrupts ■ On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) ■ 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). ■ Up to 56 MHz external clock for devices with fast clock input feature ■ 32-100 kHz subsystem quartz clock ■ 100 kHz/2 MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog ■ Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. ■ Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) ■ Clock modulator ■ Fast Interrupt processing ■ 8 programmable priority levels ■ Non-Maskable Interrupt (NMI) Timers ■ Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) ■ Watchdog Timer On-chip Voltage Regulator ■ Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power consumption figures Cypress Semiconductor Corporation Document Number: 002-04582 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 22, 2020 CY96380 Series CAN Input Capture Units ■ Supports CAN protocol version 2.0 part A and B ■ 16-bit wide ■ ISO16845 certified ■ Signals an interrupt upon external event ■ Bit rates up to 1 Mbit/s ■ Rising edge, falling edge or rising & falling edge sensitive ■ 32 message objects Output Compare Units ■ Each message object has its own identifier mask ■ Programmable FIFO mode (concatenation of message objects) ■ Maskable interrupt ■ Disabled Automatic Retransmission mode for Time Triggered CAN applications Programmable Pulse Generator ■ Programmable loop-back mode for self-test operation ■ 16-bit down counter, cycle and duty setting registers ■ Interrupt at trigger, counter borrow and/or duty match ■ PWM operation and one-shot operation ■ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow as clock input ■ Can be triggered by software or reload timer USART ■ Full duplex USARTs (SCI/LIN) ■ Wide range of baud rate settings using a dedicated reload timer ■ Special synchronous options for adapting to different synchronous serial protocols ■ LIN functionality working either as master or slave LIN device I 2C ■ Up to 400 kbps ■ Master and Slave functionality, 8-bit and 10-bit addressing A/D Converter ■ SAR-type ■ 10-bit resolution ■ Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer A/D Converter Reference Voltage switch ■ 2 independent positive A/D converter reference voltages available Reload Timers ■ 16-bit wide ■ Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency ■ Event count function Free Running Timers ■ Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency Document Number: 002-04582 Rev. *C ■ 16-bit wide ■ Signals an interrupt when a match with 16-bit I/O Timer occurs ■ A pair of compare registers can be used to generate an output signal. Stepper Motor Controller ■ Stepper Motor Controller with integrated high current output drivers ■ Four high current outputs for each channel ■ Two synchronized 8/10-bit PWMs per channel ■ Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock ■ Separate power supply for high current output drivers LCD Controller ■ LCD controller with up to 4 COM × 65 SEG ■ Internal or external voltage generation ■ Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 ■ Fixed 1/3 bias ■ Programmable frame period ■ Clock source selectable from three options (peripheral clock, subclock or RC oscillator clock) ■ On-chip drivers for internal divider resistors or external divider resistors ■ On-chip data memory for display ■ LCD display can be operated in Timer Mode ■ Blank display: selectable ■ All SEG, COM and V pins can be switched between general and specialized purposes ■ External divided resistors can be also used to shut off the current when LCD is deactivated Page 2 of 119 CY96380 Series Sound Generator Alarm Comparator ■ 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter ■ Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds ■ PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock ■ Threshold voltages defined externally or generated internally ■ Status is readable, interrupts can be masked separately Real Time Clock ■ Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator ■ Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) ■ Read/write accessible second/minute/hour registers ■ Can signal interrupts every half second/second/minute/hour/day ■ Internal clock divider and prescaler provide exact 1s clock External Interrupts ■ Edge sensitive or level sensitive ■ Interrupt mask and pending bit per channel ■ Each available CAN channel RX has an external interrupt for wake-up ■ Selected USART channels SIN have an external interrupt for wake-up Non Maskable Interrupt ■ Disabled after reset ■ Once enabled, can not be disabled other than by reset. ■ Level high or level low sensitive ■ Pin shared with external interrupt 0. External Bus Interface ■ 8-bit or 16-bit bidirectional data ■ Up to 24-bit addresses ■ 6 chip select signals ■ Multiplexed address/data lines ■ Non-multiplexed address/data lines ■ Wait state request ■ External bus master possible ■ Timing programmable Document Number: 002-04582 Rev. *C I/O Ports ■ Virtually all external pins can be used as general purpose I/O ■ All push-pull outputs (except when used as I2C SDA/SCL line) ■ Bit-wise programmable as input/output or peripheral signal ■ Bit-wise programmable input enable ■ Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL ■ Bit-wise programmable pull-up resistor ■ Bit-wise programmable output driving strength for EMI optimization Package ■ 120-pin plastic LQFP Flash Memory ■ Supports automatic programming, Embedded Algorithm ■ Write/Erase/Erase-Suspend/Resume commands ■ A flag indicating completion of the algorithm ■ Number of erase cycles: 10,000 times ■ Data retention time: 20 years ■ Erase can be performed on each sector individually ■ Sector protection ■ Flash Security feature to protect the content of the Flash ■ Low voltage detection during Flash erase Page 3 of 119 CY96380 Series Contents Product Lineup ................................................................. 5 Block Diagram .................................................................. 7 Pin Assignment ................................................................ 8 Pin Function Description ................................................. 9 Pin Circuit Type .............................................................. 12 I/O Circuit Type ............................................................... 14 Memory Map ................................................................... 19 RAMSTART/END and External Bus End Addresses ... 20 User ROM Memory Map for Flash Devices .................. 21 User ROM Memory Map for Mask Rom Devices .......... 23 Serial Programming Communication Interface ........... 24 I/O Map ............................................................................ 25 Interrupt Vector Table .................................................... 55 Handling Devices ........................................................... 58 Latch-up prevention .................................................. 58 Unused pins handling ................................................ 58 External clock usage ................................................. 58 Unused sub clock signal ........................................... 59 Notes on PLL clock mode operation ......................... 59 Power supply pins (VCC/VSS) .................................. 59 Crystal oscillator and ceramic resonator circuit ......... 59 Turn on sequence of power supply to Document Number: 002-04582 Rev. *C A/D converter and analog inputs ............................... 59 Pin handling when not using the A/D converter ........ 59 Notes on Power-on ................................................... 59 Stabilization of power supply voltage ........................ 59 SMC power supply pins ............................................ 60 Serial communication ................................................ 60 Electrical Characteristics .............................................. 61 Absolute Maximum Ratings ...................................... 61 Recommended Operating Conditions ....................... 64 DC characteristics ..................................................... 65 AC Characteristics .................................................... 77 Analog Digital Converter ........................................... 99 Alarm Comparator ................................................... 103 Low Voltage Detector characteristics ...................... 105 FLASH memory program/erase characteristics ...... 107 Example Characteristics .............................................. 108 Package Dimension CY96(F)38x LQFP 120P ............. 112 Ordering Information ................................................... 113 Major Changes .............................................................. 114 Revision History ........................................................... 116 Document History ........................................................ 118 Page 4 of 119 CY96380 Series 1. Product Lineup Features CY96V300B CY96(F)38x Product type Evaluation sample Flash product: CY96F38x Mask ROM product: CY9638x Product options YS Low voltage reset persistently on / Single clock RS Low voltage reset can be disabled / Single clock YW Low voltage reset persistently on / Dual clock RW NA TS Low voltage reset can be disabled / Dual clock indep. 32 KB Flash / Low voltage reset persistently on / Single clock HS indep. 32 KB Flash / Low voltage reset can be disabled / Single clock TW indep. 32 KB Flash / Low voltage reset persistently on / Dual clock HW indep. 32 KB Flash / Low voltage reset can be disabled / Dual clock Flash/ROM RAM 128 KB 6 KB CY96384Y, CY96384R 160 KB 8 KB CY96385Y, CY96385R, CY96F385Y, CY96F385R 288 KB 16 KB 416 KB 16 KB 576 KB [Flash A: 544 KB, Flash B: 32 KB] 28 KB 832 KB [Flash A: 544 KB, Flash B: 288 KB] 32 KB CY96F386Y, CY96F386R ROM/Flash memory emulation by external RAM, 92KB internal RAM CY96F387Y, CY96F387R CY96F388T, CY96F388H CY96F389Y, CY96F389R Package BGA416 LQM120 DMA 16 channels 7 channels USART 10 channels 5 channels I2C 2 channels 1 channel A/D Converter 40 channels 16 channels A/D Converter Reference Voltage switch yes Only for CY96F386Y, CY96F386R, CY96F387Y, CY96F387R 16-bit Reload Timer 6 channels + 1 channel (for PPG) 4 channels + 1 channel (for PPG) 16-bit Free-Running Timer 4 channels 2 channels 16-bit Output Compare 12 channels 4 channels Document Number: 002-04582 Rev. *C Page 5 of 119 CY96380 Series Features CY96V300B CY96(F)38x 16-bit Input Capture 12 channels 8 channels 16-bit Programmable Pulse Generator 20 channels 8 channels CAN Interface 5 channels Other than below: 2 channels CY96384Y, CY96384R, CY96(F)385Y, CY96(F)385R,: 1 channel Stepping Motor Controller 6 channels 5 channels External Interrupts 16 channels 8 channels Non-Maskable Interrupt 1 channel Sound generator 2 channels 2 channels LCD Controller 4 COM x 72 SEG 4 COM x 65 SEG Real Time Clock 1 I/O Ports 136 Alarm comparator 2 channels 94 for part number with suffix "W", 96 for part number with suffix "S" Other than below: 2 channels CY96384Y, CY96384R, CY96(F)385Y, CY96(F)385R,: 1 channel External bus interface Yes Chip select 6 signals Clock output function 2 channels Low voltage reset Yes On-chip RC-oscillator Yes Document Number: 002-04582 Rev. *C Page 6 of 119 CY96380 Series 2. Block Diagram Block Diagram of CY96(F)38x AD00 ... AD15 A00 ... A23 ALE RDX WR(L)X, WRHX HRQ HAKX NMI RDY ECLK LBX, UBX CS0 ... CS5, CS3_R External Bus Interface CKOT0, CKOT1, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A *1 RSTX MD0...MD2 Interrupt Controller 16FX CPU Flash Memory A Flash Memory B *2 Memory Patch Unit Clock & Mode Controller 16FX Core Bus (CLKB) SCL0 AVCC AVSS AVRH AVRL/AVRH2 *4 AN0 ... AN15 ADTG TIN2_R TIN0 ... TIN3 TOT1_R, TOT2_R TOT0 ... TOT3 FRCK0 FRCK0_R IN0, IN1 IN0_R ... IN3_R OUT0 ... OUT3 OUT0_R...OUT3_R Peripheral Bus Bridge Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) SDA0 Watchdog I2C 1 ch. 10-bit ADC 16 ch. 16-bit Reload Timer 4 ch. I/O Timer 0 ICU 0/1/2/3 OCU 0/1/2/3 Peripheral Bus 1 (CLKP1) DMA Controller USART 5 ch. Alarm Comparator 2 ch. *3 16-bit PPG 8 ch. RLT6 FRCK1 IN6 ... IN7 IN4_R ... IN7_R INT0 ... INT7 I/O Timer 1 ICU 4/5/6/7 INT1_R ... INT7_R External Interrupt V0 ... V3 COM0 ... COM3 SEG0 ... SEG64 LCD controller/ driver Stepper Motor Controller 5 ch. Real Time Clock RAM Boot ROM VCC VSS C CAN Interface 2 ch. *3 Sound Generator 2 ch. TX0, TX1 *3 RX0, RX1 *3 SGO0, SGO1, SGO0_R, SGO1_R SGA0, SGA1, SGA0_R, SGA1_R SIN0...SIN2,SIN4,SIN5 SOT0...SOT2,SOT4,SOT5 SCK0...SCK2,SCK4,SCK5 ALARM0 ALARM1 *3 TTG0 ... TTG7 PPG0 ... PPG7 PPG0_R ... PPG5_R PWM1M0 ... PWM1M4 PWM1P0 ... PWM1P4 PWM2M0 ... PWM2M4 PWM2P0 ... PWM2P4 DVCC DVSS WOT *1: X0A, X1A only available on devices with suffix “W” *3: CAN1 and ALARM1 not available on CY96384 and CY96(F)385 *2: Flash B only available on CY96F388 and CY96F389 *4: AVRH2 only available on CY96F386 and CY96F387 Document Number: 002-04582 Rev. *C Voltage Regulator Page 7 of 119 CY96380 Series 3. Pin Assignment Vcc P00_2/INT5_R/RDY/SEG14 P00_1/INT4_R/WRHX/SEG13 P00_0/INT3_R/HAKX/SEG12 P12_7/INT1_R/HRQ/SEG11 P12_6/TOT2_R/A15/SEG10 P12_5/TIN2_R/A14/SEG9 P12_4/OUT3_R/A13/SEG8 P12_3/OUT2_R/A12/SEG7 P12_2/TOT1_R/A11/SEG6 P12_1/TIN1_R/A10/SEG5 P12_0/IN1_R/A09/SEG4 P11_7/IN0_R/A08/SEG3 P11_6/FRCK0_R/A07/SEG2 P11_5/PPG4_R/A06/SEG1 P11_4/PPG3_R/A05/SEG0 P11_3/PPG2_R/A04/COM3 P11_2/PPG1_R/A03/COM2 P11_1/PPG0_R/A02/COM1 P11_0/A01/COM0/CS5 RSTX X1A/P04_1 *1 X0A/P04_0 *1 Vss X1 X0 MD2 MD1 MD0 Vss Pin Assignment of CY96(F)38x 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 92 59 93 58 94 57 95 56 96 55 97 54 98 53 99 52 100 51 101 50 102 49 LQFP - 120 103 104 105 48 47 46 106 45 Package code (mold) LQM120 107 108 109 44 43 42 110 41 111 40 112 39 113 38 114 37 115 36 116 35 117 34 118 33 119 32 120 2 3 4 5 6 7 8 31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vss C P03_7/INT1/SIN1/CS0/A20/SEG40 P13_0/INT2/SOT1/CS1/A21/SEG41 P13_1/INT3/SCK1/CS2/A22/SEG42 P13_2/PPG0/TIN0/FRCK1/CS3/A23/SEG43 P13_3/PPG1/TOT0/WOT/UBX/SEG44 P13_4/SIN0/INT6/SEG45 P13_5/SOT0/ADTG/INT7/SEG46 P13_6/SCK0/CKOTX0/LBX/SEG47 P13_7/PPG2/CKOT0/CS4/SEG48 P04_4/PPG3/SDA0 P04_5/PPG4/SCL0 P06_0/AN0/SCK5/IN2_R/SEG49 P06_1/AN1/SOT5/IN3_R/SEG50 P06_2/AN2/INT5/SIN5/SEG51 P06_3/AN3/FRCK0/SEG52 P06_4/AN4/IN0/TTG0/TTG4/SEG53 P06_5/AN5/IN1/TTG1/TTG5/SEG54 P06_6/AN6/TIN1/IN4_R/SEG55 P06_7/AN7/TOT1/IN5_R/SEG56 AVcc AVRH 1 Vcc P10_3/PWM2M4/PPG7 P10_2/PWM2P4/SCK2/PPG6 P10_1/PWM1M4/SOT2/TOT3 P10_0/PWM1P4/SIN2/TIN3 P09_7/PWM2M3 DVss DVcc P09_6/PWM2P3 P09_5/PWM1M3 P09_4/PWM1P3 P09_3/PWM2M2 P09_2/PWM2P2 P09_1/PWM1M2 P09_0/PWM1P2 P08_7/PWM2M1 P08_6/PWM2P1 P08_5/PWM1M1 DVss DVcc P08_4/PWM1P1 P08_3/PWM2M0 P08_2/PWM2P0 P08_1/PWM1M0 P08_0/PWM1P0 P05_7/AN15/TOT2/SGA1_R/SEG64 P05_6/AN14/TIN2/SGO1_R/SEG63 P05_5/AN13/TX1/SEG62 *3 P05_4/AN12/RX1/INT2_R/SEG61 *3 Vss AVRL/AVRH2 *4 AVss P05_0/AN8/ALARM0/SEG57 P05_1/AN9/ALARM1/SEG58 *2 P05_2/AN10/OUT2/SGO1/SEG59 P05_3/AN11/OUT3/SGA1/SEG60 Vcc Vss P00_3/INT6_R/A00/CS3_R/SEG15 P00_4/INT7_R/ALE/SEG16 P00_5/TTG2/TTG6/IN6/RDX/SEG17 P00_6/TTG3/IN7/WR(L)X/TTG7/SEG18 P00_7/SGO0/ECLK/SEG19 P01_0/SGA0/AD00/SEG20 P01_1/OUT0/CKOT1/AD01/SEG21 P01_2/OUT1/CKOTX1/AD02/SEG22 P01_3/PPG5/AD03/SEG23 P01_4/AD04/SIN4/SEG24 P01_5/AD05/SOT4/SEG25 P01_6/AD06/SCK4/SEG26 P01_7/CKOTX1_R/AD07/SEG27 P02_0/CKOT1_R/AD08/SEG28 P02_1/IN6_R/AD09/SEG29 P02_2/IN7_R/AD10/SEG30 P02_3/SGO0_R/AD11/SEG31 P02_4/SGA0_R/AD12/SEG32 P02_5/OUT0_R/AD13/SEG33 P02_6/OUT1_R/AD14/SEG34 P02_7/PPG5_R/AD15/SEG35 P03_0/V0/A16/SEG36 P03_1/V1/A17/SEG37 P03_2/V2/A18/SEG38 P03_3/V3/A19/SEG39 P03_4/INT4/RX0 P03_5/TX0 P03_6/NMI/INT0 Vcc *1: Devices with suffix W: X0A, X1A Devices with suffix S: P04_0, P04_1 *2: Alarm1 not available on CY96384 and CY96(F)385 *3: TX1 resp. RX1 not available on CY96384 and CY96(F)385 *4: AVRH2 only available on CY96F386 and CY96F387 (LQM120) Document Number: 002-04582 Rev. *C Page 8 of 119 CY96380 Series 4. Pin Function Description Pin Function Description (1 of 3) Pin name Feature Description ADn External bus External bus interface (non multiplexed mode) data input/output. External bus interface (multiplexed mode) address output and data input/output ADTG ADC A/D converter trigger input ALARMn Alarm comparator Alarm Comparator n input ALE External bus External bus Address Latch Enable output An External bus External bus non-multiplexed address output ANn ADC A/D converter channel n input AVCC Supply Analog circuits power supply AVRH ADC A/D converter high reference voltage input AVRH2 ADC Alternative A/D converter high reference voltage input AVRL ADC A/D converter low reference voltage input AVSS Supply Analog circuits power supply C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock output function Clock Output function n output CKOTn_R Clock output function Relocated Clock Output function n output CKOTXn Clock output function Clock Output function n inverted output CKOTXn_R Clock output function Relocated Clock Output function n inverted output COMn LCD LCD COM pins ECLK External bus External bus clock output CSn External bus External bus chip select n output CSn_R External bus Relocated External bus chip select n output DVCC Supply SMC pins power supply FRCKn Free Running Timer Free Running Timer n input FRCKn_R Free Running Timer Relocated Free Running Timer n input HAKX External bus External bus Hold Acknowledge HRQ External bus External bus Hold Request INn ICU Input Capture Unit n input INn_R ICU Relocated Input Capture Unit n input INTn External Interrupt External Interrupt n input Document Number: 002-04582 Rev. *C Page 9 of 119 CY96380 Series Pin Function Description (2 of 3) Pin name Feature Description INTn_R External Interrupt Relocated External Interrupt n input LBX External bus External Bus Interface Lower Byte select strobe output MDn Core Input pins for specifying the operating mode. NMI External Interrupt Non-Maskable Interrupt input OUTn OCU Output Compare Unit n waveform output OUTn_R OCU Relocated Output Compare Unit n waveform output Pxx_n GPIO General purpose IO PPGn PPG Programmable Pulse Generator n output PPGn_R PPG Relocated Programmable Pulse Generator n output PWMn SMC SMC PWM high current RDX External bus External bus interface read strobe output RDY External bus External bus interface external wait state request input RSTX Core Reset input RXn CAN CAN interface n RX input SCKn USART USART n serial clock input/output SCLn I2C I2C interface n clock I/O input/output SDAn I2C I2C interface n serial data I/O input/output SEGn LCD LCD segment n SGA Sound Generator SG amplitude output SGO Sound Generator SG sound/tone output SGA_R Sound Generator Relocated SG amplitude output SGO_R Sound Generator Relocated SG sound/tone output SINn USART USART n serial data input SOTn USART USART n serial data output TINn Reload Timer Reload Timer n event input TINn_R Reload Timer Relocated Reload Timer n event input TOTn Reload Timer Reload Timer n output TOTn_R Reload Timer Relocated Reload Timer n output TTGn PPG Programmable Pulse Generator n trigger input TXn CAN CAN interface n TX output UBX External bus External Bus Interface Upper Byte select strobe output Document Number: 002-04582 Rev. *C Page 10 of 119 CY96380 Series Pin Function Description (3 of 3) Pin name Feature Description Vn LCD LCD voltage references VCC Supply Power supply VSS Supply Power supply WOT RTC Real Timer clock output WRHX External bus External bus High byte write strobe output WRLX/WRX External bus External bus Low byte / Word write strobe output X0 Clock Oscillator input X0A Clock Subclock Oscillator input (only for devices with suffix “W”) X1 Clock Oscillator output X1A Clock Subclock Oscillator output (only for devices with suffix “W”) Document Number: 002-04582 Rev. *C Page 11 of 119 CY96380 Series 5. Pin Circuit Type Pin Circuit Types (1 of 2) LQM120 Pin No. Circuit Type *1 1 Supply 2 F 3 to 11 J 12,13 N 14 to 21 K 22 Supply 23 to 24 G 25 Supply 26 to 29 K 30,31 Supply 32 to 35 K 36 to 40 M 41,42 Supply 43 to 52 M 53,54 Supply 55 to 59 M 60, 61 Supply 62 to 64 C 65, 66 A 67 Supply 68,69 B *2 68,69 H *3 70 E 71 to 89 J 90 to 91 Supply 92 to 112 J 113 to 116 L Document Number: 002-04582 Rev. *C Page 12 of 119 CY96380 Series Pin Circuit Types (2 of 2) LQM120 Pin No. Circuit Type *1 117 to 119 H 120 Supply *1: See 6.“I/O Circuit Type” for details on the I/O circuit types *2: Devices with suffix “W” *3: Devices without suffix “W” Document Number: 002-04582 Rev. *C Page 13 of 119 CY96380 Series 6. I/O Circuit Type Type Circuit Remarks X1 R A 0 MRFBE Xout 1 FCI R High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Programmable feedback resistor = approx. 2 * 0.5 M. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode X0 FCI or osc disable Xout X1A R B Low-speed oscillation circuit: • Programmable feedback resistor = approx. 2 * 5 M. Feedback resistor is grounded in the center when the oscillator is disabled SRFBE R X0A osc disable C E R Hysteresis inputs • Mask ROM and EVA device: CMOS Hysteresis input pin • Flash device: CMOS input pin • CMOS Hysteresis input pin • Pull-up resistor value: approx. 50 k Pull-up Resistor R Document Number: 002-04582 Rev. *C Hysteresis inputs Page 14 of 119 CY96380 Series Type Circuit Remarks F • Power supply input protection circuit ANE G AVR ANE • A/D converter ref+ (AVRH/AVRH2) power supply input pin with protection circuit • Flash devices do not have a protection circuit against VCC for pins AVRH/AVRH2 • Devices without AVRH reference switch do not have an analog switch for the AVRL pin pull-up control Pout Nout R H Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04582 Rev. *C • CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50 k approx. Page 15 of 119 CY96380 Series Type Circuit Remarks pull-up control Pout Nout R J Hysteresis input Standby control for input shutdown Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input • CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50 k approx. • SEG or COM output SEG, COM output pull-up control Pout Nout R K Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input • CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function. • Programmable pull-up resistor: 50 k approx. • Analog input • SEG output Analog input SEG output Document Number: 002-04582 Rev. *C Page 16 of 119 CY96380 Series Type Circuit Remarks pull-up control Pout Nout R L Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input • CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50 k approx. • Analog input • Vx input • SEG output Analog input SEG output Vx input pull-up control Pout Nout R M Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04582 Rev. *C • CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA, IOL = 30 mA, IOH = -30 mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50 k approx. Page 17 of 119 CY96380 Series Type Circuit Remarks pull-up control Pout Nout R N Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04582 Rev. *C • CMOS level output (IOL = 3 mA, IOH = -3 mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50 k approx. Page 18 of 119 CY96380 Series 7. Memory Map CY96V300B CY96(F)38x FF:FFFFH USER ROM / Emulation ROM External Bus*4 DE:0000H External Bus External Bus Boot-ROM Boot-ROM 10:0000H 0F:E000H Reserved 0E:0000H Reserved External RAM 02:0000H Internal RAM bank 1 RAMEND1*2 RAMSTART12 01:0000H ROM/RAM MIRROR Reserved Internal RAM bank 1 Reserved RAM availability depending on the device ROM/RAM MIRROR 00:8000H Internal RAM Internal RAM RAMSTART0*2 bank 0 Reserved bank 0 RAMSTART0*3 00:0C00H External Bus end address*2 External Bus External Bus Peripherals Peripherals GPR*1 GPR*1 DMA DMA External Bus External Bus Peripheral Peripheral 00:0380H 00:0180H 00:0100H 00:00F0H 00:0000H *1: Unused GPR banks can be used as RAM area *2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the configuration of the emulated device. *4: For details about USER ROM area, see the 9.“User ROM Memory Map for Flash Devices” and 10.“User ROM Memory Map for Mask Rom Devices” on the following pages. The External Bus area and DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04582 Rev. *C Page 19 of 119 CY96380 Series 8. RAMSTART/END and External Bus End Addresses Devices Bank 0 RAM size Bank 1 RAM size External Bus end address RAMSTART0 RAMSTART1 RAMEND1 CY96384 6 KByte - 00:61FFH 00:6A40H - - CY96385/F385 8 KByte - 00:61FFH 00:6240H - - CY96F386, CY96F387 16 KByte - 00:41FFH 00:4240H - - CY96F388 28 KByte - 00:11FFH 00:1240H - - CY96F389 28 KByte 4KByte 00:11FFH 00:1240H 01:8000H 01:8FFFH Document Number: 002-04582 Rev. *C Page 20 of 119 CY96380 Series 9. User ROM Memory Map for Flash Devices Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H CY96F385R CY96F385Y CY96F386R CY96F386Y CY96F387R CY96F387Y Flash size 160kByte Flash size 288kByte Flash size 416kByte S39 - 64K S39 - 64K S39 - 64K S38 - 64K S38 - 64K S38 - 64K S37 - 64K S37 - 64K S36 - 64K S36 - 64K S35 - 64K S34 - 64K External bus External bus External bus E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H Flash A Reserved Reserved Reserved SA3 - 8K SA3 - 8K SA3 - 8K SA2 - 8K SA2 - 8K SA2 - 8K SA1 - 8K SA1 - 8K SA1 - 8K SA0 - 8K *1 SA0 - 8K *1 SA0 - 8K *1 Reserved Reserved Reserved DE:0000H Flash A *1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH Document Number: 002-04582 Rev. *C Page 21 of 119 CY96380 Series Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:8000H DE:7FFFH DE:6000H DE:5FFFH DE:4000H DE:3FFFH DE:2000H DE:1FFFH DE:0000H 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H 1E:7FFFH 1E:6000H 1E:5FFFH 1E:4000H 1E:3FFFH 1E:2000H 1E:1FFFH 1E:0000H CY96F388T CY96F388H CY96F389R CY96F389Y Flash size 576kByte Flash size 832kByte S39 - 64K S39 - 64K S38 - 64K S38 - 64K S37 - 64K S37 - 64K S36 - 64K S36 - 64K S35 - 64K S35 - 64K S34 - 64K S34 - 64K S33 - 64K S33 - 64K S32 - 64K S32 - 64K Flash A S31 - 64K S30 - 64K S29 - 64K Flash B S28 - 64K External bus External bus Reserved Reserved SA3 - 8K SA3 - 8K SA2 - 8K SA2 - 8K SA1 - 8K SA1 - 8K SA0 - 8K *1 SA0 - 8K *1 Reserved Reserved SB3 - 8K SB3 - 8K SB2 - 8K SB2 - 8K SB1 - 8K SB1 - 8K SB0 - 8K *2 SB0 - 8K *2 Flash A Flash B *1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH *2: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH Document Number: 002-04582 Rev. *C Page 22 of 119 CY96380 Series 10. User ROM Memory Map for Mask Rom Devices CPU address CY96384 CY96385 ROM size 128kByte ROM size 160kByte 128K ROM 128K ROM External bus External bus FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH DF:FFFFH DF:8000H DF:7FFFH Reserved Reserved 32K ROM DF:0080H DF:007FH DF:0000H DE:FFFFH DE:0000H ROM configuration block RCB ROM configuration block RCB Reserved Reserved Document Number: 002-04582 Rev. *C Page 23 of 119 CY96380 Series 11. Serial Programming Communication Interface USART Pins for Flash Serial Programming (MD[2:0] = 010, Serial Communication Mode) CY96F38x Pin Number USART Number Normal Function LQFP-120 8 9 SIN0 USART0 SOT0 10 SCK0 3 SIN1 4 USART1 SOT1 5 SCK1 56 SIN2 57 58 USART2 SOT2 SCK2 Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least port P00_1 on pin 88. If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. Document Number: 002-04582 Rev. *C Page 24 of 119 CY96380 Series 12. I/O Map I/O Map CY96(F)38x (Sheet 1 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000000H I/O Port P00 - Port Data Register PDR00 - R/W 000001H I/O Port P01 - Port Data Register PDR01 - R/W 000002H I/O Port P02 - Port Data Register PDR02 - R/W 000003H I/O Port P03 - Port Data Register PDR03 - R/W 000004H I/O Port P04 - Port Data Register PDR04 - R/W 000005H I/O Port P05 - Port Data Register PDR05 - R/W 000006H I/O Port P06 - Port Data Register PDR06 - R/W 000007H Reserved - - - 000008H I/O Port P08 - Port Data Register PDR08 - R/W 000009H I/O Port P09 - Port Data Register PDR09 - R/W 00000AH I/O Port P10 - Port Data Register PDR10 - R/W 00000BH I/O Port P11 - Port Data Register PDR11 - R/W 00000CH I/O Port P12 - Port Data Register PDR12 - R/W 00000DH I/O Port P13 - Port Data Register PDR13 - R/W 00000EH000017H Reserved - - - 000018H ADC0 - Control Status register Low ADCSL ADCS R/W 000019H ADC0 - Control Status register High ADCSH - R/W 00001AH ADC0 - Data Register Low ADCRL ADCR R 00001BH ADC0 - Data Register High ADCRH - R 00001CH ADC0 - Setting Register - ADSR R/W 00001DH ADC0 - Setting Register - - R/W 00001EH ADC0 - Extended Configuration Register ADECR - R/W 00001FH Reserved - - - 000020H FRT0 - Data register of free-running timer - TCDT0 R/W 000021H FRT0 - Data register of free-running timer - - R/W 000022H FRT0 - Control status register of free-running timer Low TCCSL0 TCCS0 R/W 000023H FRT0 - Control status register of free-running timer High TCCSH0 - R/W 000024H FRT1 - Data register of free-running timer - TCDT1 R/W 000025H FRT1 - Data register of free-running timer - - R/W Document Number: 002-04582 Rev. *C Page 25 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 2 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000026H FRT1 - Control status register of free-running timer Low TCCSL1 TCCS1 R/W 000027H FRT1 - Control status register of free-running timer High TCCSH1 - R/W 000028H OCU0 - Output Compare Control Status OCS0 - R/W 000029H OCU1 - Output Compare Control Status OCS1 - R/W 00002AH OCU0 - Compare Register - OCCP0 R/W 00002BH OCU0 - Compare Register - - R/W 00002CH OCU1 - Compare Register - OCCP1 R/W 00002DH OCU1 - Compare Register - - R/W 00002EH OCU2 - Output Compare Control Status OCS2 - R/W 00002FH OCU3 - Output Compare Control Status OCS3 - R/W 000030H OCU2 - Compare Register - OCCP2 R/W 000031H OCU2 - Compare Register - 000032H OCU3 - Compare Register - OCCP3 R/W 000033H OCU3 - Compare Register - - R/W 000034H00003FH Reserved - - - 000040H ICU0/ICU1 - Control Status Register ICS01 - R/W 000041H ICU0/ICU1 - Edge register ICE01 - R/W 000042H ICU0 - Capture Register Low IPCPL0 IPCP0 R 000043H ICU0 - Capture Register High IPCPH0 - R 000044H ICU1 - Capture Register Low IPCPL1 IPCP1 R 000045H ICU1 - Capture Register High IPCPH1 - R 000046H ICU2/ICU3 - Control Status Register ICS23 - R/W 000047H ICU2/ICU3 - Edge register ICE23 - R/W 000048H ICU2 - Capture Register Low IPCPL2 IPCP2 R 000049H ICU2 - Capture Register High IPCPH2 - R 00004AH ICU3 - Capture Register Low IPCPL3 IPCP3 R 00004BH ICU3 - Capture Register High IPCPH3 - R 00004CH ICU4/ICU5 - Control Status Register ICS45 - R/W 00004DH ICU4/ICU5 - Edge register ICE45 - R/W 00004EH ICU4 - Capture Register Low IPCPL4 IPCP4 R Document Number: 002-04582 Rev. *C R/W Page 26 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 3 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 00004FH ICU4 - Capture Register High IPCPH4 - R 000050H ICU5 - Capture Register Low IPCPL5 IPCP5 R 000051H ICU5 - Capture Register High IPCPH5 - R 000052H ICU6/ICU7 - Control Status Register ICS67 - R/W 000053H ICU6/ICU7 - Edge register ICE67 - R/W 000054H ICU6 - Capture Register Low IPCPL6 IPCP6 R 000055H ICU6 - Capture Register High IPCPH6 - R 000056H ICU7 - Capture Register Low IPCPL7 IPCP7 R 000057H ICU7 - Capture Register High IPCPH7 - R 000058H EXTINT0 - External Interrupt Enable Register ENIR0 - R/W 000059H EXTINT0 - External Interrupt Interrupt request Register EIRR0 - R/W 00005AH EXTINT0 - External Interrupt Level Select Low ELVRL0 ELVR0 R/W 00005BH EXTINT0 - External Interrupt Level Select High ELVRH0 - R/W 00005CH00005FH Reserved - - - 000060H RLT0 - Timer Control Status Register Low TMCSRL0 TMCSR0 R/W 000061H RLT0 - Timer Control Status Register High TMCSRH0 - R/W 000062H RLT0 - Reload Register - for writing - TMRLR0 W 000062H RLT0 - Reload Register - for reading - TMR0 R 000063H RLT0 - Reload Register - for writing - - W 000063H RLT0 - Reload Register - for reading - - R 000064H RLT1 - Timer Control Status Register Low TMCSRL1 TMCSR1 R/W 000065H RLT1 - Timer Control Status Register High TMCSRH1 - R/W 000066H RLT1 - Reload Register - for writing - TMRLR1 W 000066H RLT1 - Reload Register - for reading - TMR1 R 000067H RLT1 - Reload Register - for writing - - W 000067H RLT1 - Reload Register - for reading - - R 000068H RLT2 - Timer Control Status Register Low TMCSRL2 TMCSR2 R/W 000069H RLT2 - Timer Control Status Register High TMCSRH2 - R/W 00006AH RLT2 - Reload Register - for writing - TMRLR2 W 00006AH RLT2 - Reload Register - for reading - TMR2 R Document Number: 002-04582 Rev. *C Page 27 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 4 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access - - W 00006BH RLT2 - Reload Register - for writing 00006BH RLT2 - Reload Register - for reading 00006CH RLT3 - Timer Control Status Register Low TMCSRL3 TMCSR3 R/W 00006DH RLT3 - Timer Control Status Register High TMCSRH3 - R/W 00006EH RLT3 - Reload Register - for writing - TMRLR3 W 00006EH RLT3 - Reload Register - for reading - TMR3 R 00006FH RLT3 - Reload Register - for writing - - W 00006FH RLT3 - Reload Register - for reading - R 000070H RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) TMCSRL6 TMCSR6 R/W 000071H RLT6 - Timer Control Status Register High (dedic. RLT for PPG) TMCSRH6 - R/W 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for writing - TMRLR6 W 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for reading - TMR6 R 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for writing - - W 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for reading - - R 000074H PPG3-PPG0 - General Control register 1 Low GCN1L0 GCN10 R/W 000075H PPG3-PPG0 - General Control register 1 High GCN1H0 - R/W 000076H PPG3-PPG0 - General Control register 2 Low GCN2L0 GCN20 R/W 000077H PPG3-PPG0 - General Control register 2 High GCN2H0 - R/W 000078H PPG0 - Timer register - PTMR0 R 000079H PPG0 - Timer register - - R 00007AH PPG0 - Period setting register - PCSR0 W 00007BH PPG0 - Period setting register - - W 00007CH PPG0 - Duty cycle register - PDUT0 W 00007DH PPG0 - Duty cycle register - - W 00007EH PPG0 - Control status register Low PCNL0 PCN0 R/W 00007FH PPG0 - Control status register High PCNH0 - R/W 000080H PPG1 - Timer register - PTMR1 R 000081H PPG1 - Timer register - - R 000082H PPG1 - Period setting register - PCSR1 W Document Number: 002-04582 Rev. *C R Page 28 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 5 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000083H PPG1 - Period setting register - - W 000084H PPG1 - Duty cycle register - PDUT1 W 000085H PPG1 - Duty cycle register - - W 000086H PPG1 - Control status register Low PCNL1 PCN1 R/W 000087H PPG1 - Control status register High PCNH1 - R/W 000088H PPG2 - Timer register - PTMR2 R 000089H PPG2 - Timer register - - R 00008AH PPG2 - Period setting register - PCSR2 W 00008BH PPG2 - Period setting register - - W 00008CH PPG2 - Duty cycle register - PDUT2 W 00008DH PPG2 - Duty cycle register - - W 00008EH PPG2 - Control status register Low PCNL2 PCN2 R/W 00008FH PPG2 - Control status register High PCNH2 - R/W 000090H PPG3 - Timer register - PTMR3 R 000091H PPG3 - Timer register - - R 000092H PPG3 - Period setting register - PCSR3 W 000093H PPG3 - Period setting register - - W 000094H PPG3 - Duty cycle register - PDUT3 W 000095H PPG3 - Duty cycle register - - W 000096H PPG3 - Control status register Low PCNL3 PCN3 R/W 000097H PPG3 - Control status register High PCNH3 - R/W 000098H PPG7-PPG4 - General Control register 1 Low GCN1L1 GCN11 R/W 000099H PPG7-PPG4 - General Control register 1 High GCN1H1 - R/W 00009AH PPG7-PPG4 - General Control register 2 Low GCN2L1 GCN21 R/W 00009BH PPG7-PPG4 - General Control register 2 High GCN2H1 - R/W 00009CH PPG4 - Timer register - PTMR4 R 00009DH PPG4 - Timer register - - R 00009EH PPG4 - Period setting register - PCSR4 W 00009FH PPG4 - Period setting register - - W 0000A0H PPG4 - Duty cycle register - PDUT4 W Document Number: 002-04582 Rev. *C Page 29 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 6 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access - - W 0000A1H PPG4 - Duty cycle register 0000A2H PPG4 - Control status register Low PCNL4 PCN4 R/W 0000A3H PPG4 - Control status register High PCNH4 - R/W 0000A4H PPG5 - Timer register - PTMR5 R 0000A5H PPG5 - Timer register - - R 0000A6H PPG5 - Period setting register - PCSR5 W 0000A7H PPG5 - Period setting register - - W 0000A8H PPG5 - Duty cycle register - PDUT5 W 0000A9H PPG5 - Duty cycle register - - W 0000AAH PPG5 - Control status register Low PCNL5 PCN5 R/W 0000ABH PPG5 - Control status register High PCNH5 - R/W 0000ACH I2C0 - Bus Status Register IBSR0 - R 0000ADH I2C0 - Bus Control Register IBCR0 - R/W 0000AEH I2C0 - Ten bit Slave address Register Low ITBAL0 ITBA0 R/W 0000AFH I2C0 - Ten bit Slave address Register High ITBAH0 - R/W 0000B0H I2C0 - Ten bit Address mask Register Low ITMKL0 ITMK0 R/W 0000B1H I2C0 - Ten bit Address mask Register High ITMKH0 - R/W 0000B2H I2C0 - Seven bit Slave address Register ISBA0 - R/W 0000B3H I2C0 - Seven bit Address mask Register ISMK0 - R/W 0000B4H I2C0 - Data Register IDAR0 - R/W 0000B5H I2C0 - Clock Control Register ICCR0 - R/W 0000B6H0000BFH Reserved - - - 0000C0H USART0 - Serial Mode Register SMR0 - R/W 0000C1H USART0 - Serial Control Register SCR0 - R/W 0000C2H USART0 - TX Register TDR0 - W 0000C2H USART0 - RX Register RDR0 - R 0000C3H USART0 - Serial Status SSR0 - R/W 0000C4H USART0 - Control/Com. Register ECCR0 - R/W 0000C5H USART0 - Ext. Status Register ESCR0 - R/W 0000C6H USART0 - Baud Rate Generator Register Low BGRL0 BGR0 R/W Document Number: 002-04582 Rev. *C Page 30 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 7 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0000C7H USART0 - Baud Rate Generator Register High BGRH0 - R/W 0000C8H USART0 - Extended Serial Interrupt Register ESIR0 - R/W 0000C9H Reserved - - - 0000CAH USART1 - Serial Mode Register SMR1 - R/W 0000CBH USART1 - Serial Control Register SCR1 - R/W 0000CCH USART1 - TX Register TDR1 - W 0000CCH USART1 - RX Register RDR1 - R 0000CDH USART1 - Serial Status SSR1 - R/W 0000CEH USART1 - Control/Com. Register ECCR1 - R/W 0000CFH USART1 - Ext. Status Register ESCR1 - R/W 0000D0H USART1 - Baud Rate Generator Register Low BGRL1 BGR1 R/W 0000D1H USART1 - Baud Rate Generator Register High BGRH1 - R/W 0000D2H USART1 - Extended Serial Interrupt Register ESIR1 - R/W 0000D3H Reserved - - - 0000D4H USART2 - Serial Mode Register SMR2 - R/W 0000D5H USART2 - Serial Control Register SCR2 - R/W 0000D6H USART2 - TX Register TDR2 - W 0000D6H USART2 - RX Register RDR2 - R 0000D7H USART2 - Serial Status SSR2 - R/W 0000D8H USART2 - Control/Com. Register ECCR2 - R/W 0000D9H USART2 - Ext. Status Register ESCR2 - R/W 0000DAH USART2 - Baud Rate Generator Register Low BGRL2 BGR2 R/W 0000DBH USART2 - Baud Rate Generator Register High BGRH2 - R/W 0000DCH USART2 - Extended Serial Interrupt Register ESIR2 - R/W 0000DDH0000EFH Reserved - - - 0000F0H0000FFH External Bus area EXTBUS0 - R/W 000100H DMA0 - Buffer address pointer low byte BAPL0 - R/W 000101H DMA0 - Buffer address pointer middle byte BAPM0 - R/W 000102H DMA0 - Buffer address pointer high byte BAPH0 - R/W Document Number: 002-04582 Rev. *C Page 31 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 8 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access DMACS0 - R/W 000103H DMA0 - DMA control register 000104H DMA0 - I/O register address pointer low byte IOAL0 IOA0 R/W 000105H DMA0 - I/O register address pointer high byte IOAH0 - R/W 000106H DMA0 - Data counter low byte DCTL0 DCT0 R/W 000107H DMA0 - Data counter high byte DCTH0 - R/W 000108H DMA1 - Buffer address pointer low byte BAPL1 - R/W 000109H DMA1 - Buffer address pointer middle byte BAPM1 - R/W 00010AH DMA1 - Buffer address pointer high byte BAPH1 - R/W 00010BH DMA1 - DMA control register DMACS1 - R/W 00010CH DMA1 - I/O register address pointer low byte IOAL1 IOA1 R/W 00010DH DMA1 - I/O register address pointer high byte IOAH1 - R/W 00010EH DMA1 - Data counter low byte DCTL1 DCT1 R/W 00010FH DMA1 - Data counter high byte DCTH1 - R/W 000110H DMA2 - Buffer address pointer low byte BAPL2 - R/W 000111H DMA2 - Buffer address pointer middle byte BAPM2 - R/W 000112H DMA2 - Buffer address pointer high byte BAPH2 - R/W 000113H DMA2 - DMA control register DMACS2 - R/W 000114H DMA2 - I/O register address pointer low byte IOAL2 IOA2 R/W 000115H DMA2 - I/O register address pointer high byte IOAH2 - R/W 000116H DMA2 - Data counter low byte DCTL2 DCT2 R/W 000117H DMA2 - Data counter high byte DCTH2 - R/W 000118H DMA3 - Buffer address pointer low byte BAPL3 - R/W 000119H DMA3 - Buffer address pointer middle byte BAPM3 - R/W 00011AH DMA3 - Buffer address pointer high byte BAPH3 - R/W 00011BH DMA3 - DMA control register DMACS3 - R/W 00011CH DMA3 - I/O register address pointer low byte IOAL3 IOA3 R/W 00011DH DMA3 - I/O register address pointer high byte IOAH3 - R/W 00011EH DMA3 - Data counter low byte DCTL3 DCT3 R/W 00011FH DMA3 - Data counter high byte DCTH3 - R/W 000120H DMA4 - Buffer address pointer low byte BAPL4 - R/W Document Number: 002-04582 Rev. *C Page 32 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 9 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000121H DMA4 - Buffer address pointer middle byte BAPM4 - R/W 000122H DMA4 - Buffer address pointer high byte BAPH4 - R/W 000123H DMA4 - DMA control register DMACS4 - R/W 000124H DMA4 - I/O register address pointer low byte IOAL4 IOA4 R/W 000125H DMA4 - I/O register address pointer high byte IOAH4 - R/W 000126H DMA4 - Data counter low byte DCTL4 DCT4 R/W 000127H DMA4 - Data counter high byte DCTH4 - R/W 000128H DMA5 - Buffer address pointer low byte BAPL5 - R/W 000129H DMA5 - Buffer address pointer middle byte BAPM5 - R/W 00012AH DMA5 - Buffer address pointer high byte BAPH5 - R/W 00012BH DMA5 - DMA control register DMACS5 - R/W 00012CH DMA5 - I/O register address pointer low byte IOAL5 IOA5 R/W 00012DH DMA5 - I/O register address pointer high byte IOAH5 - R/W 00012EH DMA5 - Data counter low byte DCTL5 DCT5 R/W 00012FH DMA5 - Data counter high byte DCTH5 - R/W 000130H DMA6 - Buffer address pointer low byte BAPL6 - R/W 000131H DMA6 - Buffer address pointer middle byte BAPM6 - R/W 000132H DMA6 - Buffer address pointer high byte BAPH6 - R/W 000133H DMA6 - DMA control register DMACS6 - R/W 000134H DMA6 - I/O register address pointer low byte IOAL6 IOA6 R/W 000135H DMA6 - I/O register address pointer high byte IOAH6 - R/W 000136H DMA6 - Data counter low byte DCTL6 DCT6 R/W 000137H DMA6 - Data counter high byte DCTH6 - R/W 000138H00017FH Reserved - - - 000180H00037FH CPU - General Purpose registers (RAM access) GPR_RAM - R/W 000380H DMA0 - Interrupt select DISEL0 - R/W 000381H DMA1 - Interrupt select DISEL1 - R/W 000382H DMA2 - Interrupt select DISEL2 - R/W 000383H DMA3 - Interrupt select DISEL3 - R/W Document Number: 002-04582 Rev. *C Page 33 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 10 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000384H DMA4 - Interrupt select DISEL4 - R/W 000385H DMA5 - Interrupt select DISEL5 - R/W 000386H DMA6 - Interrupt select DISEL6 - R/W 000387H00038FH Reserved - - - 000390H DMA - Status register low byte DSRL DSR R/W 000391H DMA - Status register high byte DSRH - R/W 000392H DMA - Stop status register low byte DSSRL DSSR R/W 000393H DMA - Stop status register high byte DSSRH - R/W 000394H DMA - Enable register low byte DERL DER R/W 000395H DMA - Enable register high byte DERH - R/W 000396H00039FH Reserved - - - 0003A0H Interrupt level register ILR ICR R/W 0003A1H Interrupt index register IDX - R/W 0003A2H Interrupt vector table base register Low TBRL TBR R/W 0003A3H Interrupt vector table base register High TBRH - R/W 0003A4H Delayed Interrupt register DIRR - R/W 0003A5H Non Maskable Interrupt register NMI - R/W 0003A6H0003ABH Reserved - - - 0003ACH EDSU communication interrupt selection Low EDSU2L EDSU2 R/W 0003ADH EDSU communication interrupt selection High EDSU2H - R/W 0003AEH ROM mirror control register ROMM - R/W 0003AFH EDSU configuration register EDSU - R/W 0003B0H Memory patch control/status register ch 0/1 - PFCS0 R/W 0003B1H Memory patch control/status register ch 0/1 - - R/W 0003B2H Memory patch control/status register ch 2/3 - PFCS1 R/W 0003B3H Memory patch control/status register ch 2/3 - - R/W 0003B4H Memory patch control/status register ch 4/5 - PFCS2 R/W 0003B5H Memory patch control/status register ch 4/5 - - R/W 0003B6H Memory patch control/status register ch 6/7 - PFCS3 R/W Document Number: 002-04582 Rev. *C Page 34 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 11 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access - - R/W 0003B7H Memory patch control/status register ch 6/7 0003B8H Memory Patch function - Patch address 0 low PFAL0 - R/W 0003B9H Memory Patch function - Patch address 0 middle PFAM0 - R/W 0003BAH Memory Patch function - Patch address 0 high PFAH0 - R/W 0003BBH Memory Patch function - Patch address 1 low PFAL1 - R/W 0003BCH Memory Patch function - Patch address 1 middle PFAM1 - R/W 0003BDH Memory Patch function - Patch address 1 high PFAH1 - R/W 0003BEH Memory Patch function - Patch address 2 low PFAL2 - R/W 0003BFH Memory Patch function - Patch address 2 middle PFAM2 - R/W 0003C0H Memory Patch function - Patch address 2 high PFAH2 - R/W 0003C1H Memory Patch function - Patch address 3 low PFAL3 - R/W 0003C2H Memory Patch function - Patch address 3 middle PFAM3 - R/W 0003C3H Memory Patch function - Patch address 3 high PFAH3 - R/W 0003C4H Memory Patch function - Patch address 4 low PFAL4 - R/W 0003C5H Memory Patch function - Patch address 4 middle PFAM4 - R/W 0003C6H Memory Patch function - Patch address 4 high PFAH4 - R/W 0003C7H Memory Patch function - Patch address 5 low PFAL5 - R/W 0003C8H Memory Patch function - Patch address 5 middle PFAM5 - R/W 0003C9H Memory Patch function - Patch address 5 high PFAH5 - R/W 0003CAH Memory Patch function - Patch address 6 low PFAL6 - R/W 0003CBH Memory Patch function - Patch address 6 middle PFAM6 - R/W 0003CCH Memory Patch function - Patch address 6 high PFAH6 - R/W 0003CDH Memory Patch function - Patch address 7 low PFAL7 - R/W 0003CEH Memory Patch function - Patch address 7 middle PFAM7 - R/W 0003CFH Memory Patch function - Patch address 7 high PFAH7 - R/W 0003D0H Memory Patch function - Patch data 0 Low PFDL0 PFD0 R/W 0003D1H Memory Patch function - Patch data 0 High PFDH0 - R/W 0003D2H Memory Patch function - Patch data 1 Low PFDL1 PFD1 R/W 0003D3H Memory Patch function - Patch data 1 High PFDH1 - R/W 0003D4H Memory Patch function - Patch data 2 Low PFDL2 PFD2 R/W Document Number: 002-04582 Rev. *C Page 35 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 12 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0003D5H Memory Patch function - Patch data 2 High PFDH2 - R/W 0003D6H Memory Patch function - Patch data 3 Low PFDL3 PFD3 R/W 0003D7H Memory Patch function - Patch data 3 High PFDH3 - R/W 0003D8H Memory Patch function - Patch data 4 Low PFDL4 PFD4 R/W 0003D9H Memory Patch function - Patch data 4 High PFDH4 - R/W 0003DAH Memory Patch function - Patch data 5 Low PFDL5 PFD5 R/W 0003DBH Memory Patch function - Patch data 5 High PFDH5 - R/W 0003DCH Memory Patch function - Patch data 6 Low PFDL6 PFD6 R/W 0003DDH Memory Patch function - Patch data 6 High PFDH6 - R/W 0003DEH Memory Patch function - Patch data 7 Low PFDL7 PFD7 R/W 0003DFH Memory Patch function - Patch data 7 High PFDH7 - R/W 0003E0H0003F0H Reserved - - - 0003F1H Memory Control Status Register A MCSRA - R/W 0003F2H Memory Timing Configuration Register A Low MTCRAL MTCRA R/W 0003F3H Memory Timing Configuration Register A High MTCRAH - R/W 0003F4H Reserved - - - 0003F5H Memory Control Status Register B MCSRB - R/W 0003F6H Memory Timing Configuration Register B Low MTCRBL MTCRB R/W 0003F7H Memory Timing Configuration Register B High MTCRBH - R/W 0003F8H Flash Memory Write Control register 0 FMWC0 - R/W 0003F9H Flash Memory Write Control register 1 FMWC1 - R/W 0003FAH Flash Memory Write Control register 2 FMWC2 - R/W 0003FBH Flash Memory Write Control register 3 FMWC3 - R/W 0003FCH Flash Memory Write Control register 4 FMWC4 - R/W 0003FDH Flash Memory Write Control register 5 FMWC5 - R/W 0003FEH0003FFH Reserved - - - 000400H Standby Mode control register SMCR - R/W 000401H Clock select register CKSR - R/W 000402H Clock Stabilisation select register CKSSR - R/W Document Number: 002-04582 Rev. *C Page 36 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 13 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access CKMR - R 000403H Clock monitor register 000404H Clock Frequency control register Low CKFCRL CKFCR R/W 000405H Clock Frequency control register High CKFCRH - R/W 000406H PLL Control register Low PLLCRL PLLCR R/W 000407H PLL Control register High PLLCRH - R/W 000408H RC clock timer control register RCTCR - R/W 000409H Main clock timer control register MCTCR - R/W 00040AH Sub clock timer control register SCTCR - R/W 00040BH Reset cause and clock status register with clear function RCCSRC - R 00040CH Reset configuration register RCR - R/W 00040DH Reset cause and clock status register RCCSR - R 00040EH Watch dog timer configuration register WDTC - R/W 00040FH Watch dog timer clear pattern register WDTCP - W 000410H000414H Reserved - - - 000415H Clock output activation register COAR - R/W 000416H Clock output configuration register 0 COCR0 - R/W 000417H Clock output configuration register 1 COCR1 - R/W 000418H Clock Modulator control register CMCR - R/W 000419H Reserved - - - 00041AH Clock Modulator Parameter register Low CMPRL CMPR R/W 00041BH Clock Modulator Parameter register High CMPRH - R/W 00041CH00042BH Reserved - - - 00042CH Voltage Regulator Control register VRCR - R/W 00042DH Clock Input and LVD Control Register CILCR - R/W 00042EH00042FH Reserved - - - 000430H I/O Port P00 - Data Direction Register DDR00 - R/W 000431H I/O Port P01 - Data Direction Register DDR01 - R/W 000432H I/O Port P02 - Data Direction Register DDR02 - R/W 000433H I/O Port P03 - Data Direction Register DDR03 - R/W Document Number: 002-04582 Rev. *C Page 37 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 14 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000434H I/O Port P04 - Data Direction Register DDR04 - R/W 000435H I/O Port P05 - Data Direction Register DDR05 - R/W 000436H I/O Port P06 - Data Direction Register DDR06 - R/W 000437H Reserved - - - 000438H I/O Port P08 - Data Direction Register DDR08 - R/W 000439H I/O Port P09 - Data Direction Register DDR09 - R/W 00043AH I/O Port P10 - Data Direction Register DDR10 - R/W 00043BH I/O Port P11 - Data Direction Register DDR11 - R/W 00043CH I/O Port P12 - Data Direction Register DDR12 - R/W 00043DH I/O Port P13 - Data Direction Register DDR13 - R/W 00043EH000443H Reserved - - - 000444H I/O Port P00 - Port Input Enable Register PIER00 - R/W 000445H I/O Port P01 - Port Input Enable Register PIER01 - R/W 000446H I/O Port P02 - Port Input Enable Register PIER02 - R/W 000447H I/O Port P03 - Port Input Enable Register PIER03 - R/W 000448H I/O Port P04 - Port Input Enable Register PIER04 - R/W 000449H I/O Port P05 - Port Input Enable Register PIER05 - R/W 00044AH I/O Port P06 - Port Input Enable Register PIER06 - R/W 00044BH Reserved - - - 00044CH I/O Port P08 - Port Input Enable Register PIER08 - R/W 00044DH I/O Port P09 - Port Input Enable Register PIER09 - R/W 00044EH I/O Port P10 - Port Input Enable Register PIER10 - R/W 00044FH I/O Port P11 - Port Input Enable Register PIER11 - R/W 000450H I/O Port P12 - Port Input Enable Register PIER12 - R/W 000451H I/O Port P13 - Port Input Enable Register PIER13 - R/W 000452H000457H Reserved - - - 000458H I/O Port P00 - Port Input Level Register PILR00 - R/W 000459H I/O Port P01 - Port Input Level Register PILR01 - R/W 00045AH I/O Port P02 - Port Input Level Register PILR02 - R/W Document Number: 002-04582 Rev. *C Page 38 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 15 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 00045BH I/O Port P03 - Port Input Level Register PILR03 - R/W 00045CH I/O Port P04 - Port Input Level Register PILR04 - R/W 00045DH I/O Port P05 - Port Input Level Register PILR05 - R/W 00045EH I/O Port P06 - Port Input Level Register PILR06 - R/W 00045FH Reserved - - - 000460H I/O Port P08 - Port Input Level Register PILR08 - R/W 000461H I/O Port P09 - Port Input Level Register PILR09 - R/W 000462H I/O Port P10 - Port Input Level Register PILR10 - R/W 000463H I/O Port P11 - Port Input Level Register PILR11 - R/W 000464H I/O Port P12 - Port Input Level Register PILR12 - R/W 000465H I/O Port P13 - Port Input Level Register PILR13 - R/W 000466H00046BH Reserved - - - 00046CH I/O Port P00 - Extended Port Input Level Register EPILR00 - R/W 00046DH I/O Port P01 - Extended Port Input Level Register EPILR01 - R/W 00046EH I/O Port P02 - Extended Port Input Level Register EPILR02 - R/W 00046FH I/O Port P03 - Extended Port Input Level Register EPILR03 - R/W 000470H I/O Port P04 - Extended Port Input Level Register EPILR04 - R/W 000471H I/O Port P05 - Extended Port Input Level Register EPILR05 - R/W 000472H I/O Port P06 - Extended Port Input Level Register EPILR06 - R/W 000473H Reserved - - - 000474H I/O Port P08 - Extended Port Input Level Register EPILR08 - R/W 000475H I/O Port P09 - Extended Port Input Level Register EPILR09 - R/W 000476H I/O Port P10 - Extended Port Input Level Register EPILR10 - R/W 000477H I/O Port P11 - Extended Port Input Level Register EPILR11 - R/W 000478H I/O Port P12 - Extended Port Input Level Register EPILR12 - R/W 000479H I/O Port P13 - Extended Port Input Level Register EPILR13 - R/W 00047AH00047FH Reserved - - - 000480H I/O Port P00 - Port Output Drive Register PODR00 - R/W 000481H I/O Port P01 - Port Output Drive Register PODR01 - R/W Document Number: 002-04582 Rev. *C Page 39 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 16 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000482H I/O Port P02 - Port Output Drive Register PODR02 - R/W 000483H I/O Port P03 - Port Output Drive Register PODR03 - R/W 000484H I/O Port P04 - Port Output Drive Register PODR04 - R/W 000485H I/O Port P05 - Port Output Drive Register PODR05 - R/W 000486H I/O Port P06 - Port Output Drive Register PODR06 - R/W 000487H Reserved - - - 000488H I/O Port P08 - Port Output Drive Register PODR08 - R/W 000489H I/O Port P09 - Port Output Drive Register PODR09 - R/W 00048AH I/O Port P10 - Port Output Drive Register PODR10 - R/W 00048BH I/O Port P11 - Port Output Drive Register PODR11 - R/W 00048CH I/O Port P12 - Port Output Drive Register PODR12 - R/W 00048DH I/O Port P13 - Port Output Drive Register PODR13 - R/W 00048EH00049BH Reserved - - - 00049CH I/O Port P08 - Port High Drive Register PHDR08 - R/W 00049DH I/O Port P09 - Port High Drive Register PHDR09 - R/W 00049EH I/O Port P10 - Port High Drive Register PHDR10 - R/W 00049FH0004A7H Reserved - - - 0004A8H I/O Port P00 - Pull-Up resistor Control Register PUCR00 - R/W 0004A9H I/O Port P01 - Pull-Up resistor Control Register PUCR01 - R/W 0004AAH I/O Port P02 - Pull-Up resistor Control Register PUCR02 - R/W 0004ABH I/O Port P03 - Pull-Up resistor Control Register PUCR03 - R/W 0004ACH I/O Port P04 - Pull-Up resistor Control Register PUCR04 - R/W 0004ADH I/O Port P05 - Pull-Up resistor Control Register PUCR05 - R/W 0004AEH I/O Port P06 - Pull-Up resistor Control Register PUCR06 - R/W 0004AFH Reserved - - - 0004B0H I/O Port P08 - Pull-Up resistor Control Register PUCR08 - R/W 0004B1H I/O Port P09 - Pull-Up resistor Control Register PUCR09 - R/W 0004B2H I/O Port P10 - Pull-Up resistor Control Register PUCR10 - R/W 0004B3H I/O Port P11 - Pull-Up resistor Control Register PUCR11 - R/W Document Number: 002-04582 Rev. *C Page 40 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 17 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0004B4H I/O Port P12 - Pull-Up resistor Control Register PUCR12 - R/W 0004B5H I/O Port P13 - Pull-Up resistor Control Register PUCR13 - R/W 0004B6H0004BBH Reserved - - - 0004BCH I/O Port P00 - External Pin State Register EPSR00 - R 0004BDH I/O Port P01 - External Pin State Register EPSR01 - R 0004BEH I/O Port P02 - External Pin State Register EPSR02 - R 0004BFH I/O Port P03 - External Pin State Register EPSR03 - R 0004C0H I/O Port P04 - External Pin State Register EPSR04 - R 0004C1H I/O Port P05 - External Pin State Register EPSR05 - R 0004C2H I/O Port P06 - External Pin State Register EPSR06 - R 0004C3H Reserved - - - 0004C4H I/O Port P08 - External Pin State Register EPSR08 - R 0004C5H I/O Port P09 - External Pin State Register EPSR09 - R 0004C6H I/O Port P10 - External Pin State Register EPSR10 - R 0004C7H I/O Port P11 - External Pin State Register EPSR11 - R 0004C8H I/O Port P12 - External Pin State Register EPSR12 - R 0004C9H I/O Port P13 - External Pin State Register EPSR13 - R 0004CAH0004CFH Reserved - - - 0004D0H ADC analog input enable register 0 ADER0 - R/W 0004D1H ADC analog input enable register 1 ADER1 - R/W 0004D2H ADC analog input enable register 2 ADER2 - R/W 0004D3H ADC analog input enable register 3 ADER3 - R/W 0004D4H ADC analog input enable register 4 ADER4 - R/W 0004D5H Reserved - - - 0004D6H Peripheral Resource Relocation Register 0 PRRR0 - R/W 0004D7H Peripheral Resource Relocation Register 1 PRRR1 - R/W 0004D8H Peripheral Resource Relocation Register 2 PRRR2 - R/W 0004D9H Peripheral Resource Relocation Register 3 PRRR3 - R/W 0004DAH Peripheral Resource Relocation Register 4 PRRR4 - R/W Document Number: 002-04582 Rev. *C Page 41 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 18 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0004DBH Peripheral Resource Relocation Register 5 PRRR5 - R/W 0004DCH Peripheral Resource Relocation Register 6 PRRR6 - R/W 0004DDH Peripheral Resource Relocation Register 7 PRRR7 - R/W 0004DEH Peripheral Resource Relocation Register 8 PRRR8 - R/W 0004DFH Peripheral Resource Relocation Register 9 PRRR9 - R/W 0004E0H RTC - Sub Second Register L WTBRL0 WTBR0 R/W 0004E1H RTC - Sub Second Register M WTBRH0 - R/W 0004E2H RTC - Sub-Second Register H WTBR1 - R/W 0004E3H RTC - Second Register WTSR - R/W 0004E4H RTC - Minutes WTMR - R/W 0004E5H RTC - Hour WTHR - R/W 0004E6H RTC - Timer Control Extended Register WTCER - R/W 0004E7H RTC - Clock select register WTCKSR - R/W 0004E8H RTC - Timer Control Register Low WTCRL WTCR R/W 0004E9H RTC - Timer Control Register High WTCRH - R/W 0004EAH CAL - Calibration unit Control register CUCR - R/W 0004EBH Reserved - - - 0004ECH CAL - Duration Timer Data Register Low CUTDL CUTD R/W 0004EDH CAL - Duration Timer Data Register High CUTDH - R/W 0004EEH CAL - Calibration Timer Register 2 Low CUTR2L CUTR2 R 0004EFH CAL - Calibration Timer Register 2 High CUTR2H - R 0004F0H CAL - Calibration Timer Register 1 Low CUTR1L CUTR1 R 0004F1H CAL - Calibration Timer Register 1 High CUTR1H - R 0004F2H0004F9H Reserved - - - 0004FAH RLT - Timer input select (for Cascading) TMISR - R/W 0004FBH00051FH Reserved - - - 000520H USART4 - Serial Mode Register SMR4 - R/W 000521H USART4 - Serial Control Register SCR4 - R/W 000522H USART4 - TX Register TDR4 - W Document Number: 002-04582 Rev. *C Page 42 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 19 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000522H USART4 - RX Register RDR4 - R 000523H USART4 - Serial Status SSR4 - R/W 000524H USART4 - Control/Com. Register (internal) ECCR4 - R/W 000525H USART4 - Ext. Status Register ESCR4 - R/W 000526H USART4 - Baud Rate Generator Register Low BGRL4 BGR4 R/W 000527H USART4 - Baud Rate Generator Register High BGRH4 - R/W 000528H USART4 - Extended Serial Interrupt Register ESIR4 - R/W 000529H Reserved - - - 00052AH USART5 - Serial Mode Register SMR5 - R/W 00052BH USART5 - Serial Control Register SCR5 - R/W 00052CH USART5 - RX Register TDR5 - W 00052CH USART5 - TX Register RDR5 - R 00052DH USART5 - Serial Status SSR5 - R/W 00052EH USART5 - Control/Com. Register ECCR5 - R/W 00052FH USART5 - Ext. Status Register ESCR5 - R/W 000530H USART5 - Baud Rate Generator Register Low BGRL5 BGR5 R/W 000531H USART5 - Baud Rate Generator Register High BGRH5 - R/W 000532H USART5 - Extended Serial Interrupt Register ESIR5 - R/W 000533H00055FH Reserved - - - 000560H ALARM0 - Control Status Register ACSR0 - R/W 000561H ALARM0 - Extended Control Status Register AECSR0 - R/W 000562H ALARM1 - Control Status Register ACSR1 - R/W 000563H ALARM1 - Extended Control Status Register AECSR1 - R/W 000564H PPG6 - Timer register - PTMR6 R 000565H PPG6 - Timer register - - R 000566H PPG6 - Period setting register - PCSR6 W 000567H PPG6 - Period setting register - - W 000568H PPG6 - Duty cycle register - PDUT6 W 000569H PPG6 - Duty cycle register - - W 00056AH PPG6 - Control status register Low PCNL6 PCN6 R/W Document Number: 002-04582 Rev. *C Page 43 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 20 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access PCNH6 - R/W 00056BH PPG6 - Control status register High 00056CH PPG7 - Timer register - PTMR7 R 00056DH PPG7 - Timer register - - R 00056EH PPG7 - Period setting register - PCSR7 W 00056FH PPG7 - Period setting register - 000570H PPG7 - Duty cycle register - PDUT7 W 000571H PPG7 - Duty cycle register - - W 000572H PPG7 - Control status register Low PCNL7 PCN7 R/W 000573H PPG7 - Control status register High PCNH7 - R/W 000574H0005DFH Reserved - - - 0005E0H SMC0 - PWM control register PWC0 - R/W 0005E1H SMC0 - Extended control register (Output enable) PWEC0 - R/W 0005E2H SMC0 - PWM compare register PWM 1 - PWC10 R/W 0005E3H SMC0 - PWM compare register PWM 1 - - R/W 0005E4H SMC0 - PWM compare register PWM 2 - PWC20 R/W 0005E5H SMC0 - PWM compare register PWM 2 - - R/W 0005E6H SMC0 - PWM Select register PWS10 - R/W 0005E7H SMC0 - PWM Select register PWS20 - R/W 0005E8H0005E9H Reserved - - - 0005EAH SMC1 - PWM control register PWC1 - R/W 0005EBH SMC1 - Extended control register (Output enable) PWEC1 - R/W 0005ECH SMC1 - PWM compare register PWM 1 - PWC11 R/W 0005EDH SMC1 - PWM compare register PWM 1 - - R/W 0005EEH SMC1 - PWM compare register PWM 2 - PWC21 R/W 0005EFH SMC1 - PWM compare register PWM 2 - - R/W 0005F0H SMC1 - PWM Select register PWS11 - R/W 0005F1H SMC1 - PWM Select register PWS21 - R/W 0005F2H0005F3H Reserved - - - 0005F4H SMC2 - PWM control register PWC2 - R/W Document Number: 002-04582 Rev. *C W Page 44 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 21 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access PWEC2 - R/W 0005F5H SMC2 - Extended control register (Output enable) 0005F6H SMC2 - PWM compare register PWM 1 - PWC12 R/W 0005F7H SMC2 - PWM compare register PWM 1 - - R/W 0005F8H SMC2 - PWM compare register PWM 2 - PWC22 R/W 0005F9H SMC2 - PWM compare register PWM 2 - - R/W 0005FAH SMC2 - PWM Select register PWS12 - R/W 0005FBH SMC2 - PWM Select register PWS22 - R/W 0005FCH0005FDH Reserved - - - 0005FEH SMC3 - PWM control register PWC3 - R/W 0005FFH SMC3 - Extended control register (Output enable) PWEC3 - R/W 000600H SMC3 - PWM compare register PWM 1 - PWC13 R/W 000601H SMC3 - PWM compare register PWM 1 - - R/W 000602H SMC3 - PWM compare register PWM 2 - PWC23 R/W 000603H SMC3 - PWM compare register PWM 2 - - R/W 000604H SMC3 - PWM Select register PWS13 - R/W 000605H SMC3 - PWM Select register PWS23 - R/W 000606H000607H Reserved - - - 000608H SMC4 - PWM control register PWC4 - R/W 000609H SMC4 - Extended control register (Output enable) PWEC4 - R/W 00060AH SMC4 - PWM compare register PWM 1 - PWC14 R/W 00060BH SMC4 - PWM compare register PWM 1 - - R/W 00060CH SMC4 - PWM compare register PWM 2 - PWC24 R/W 00060DH SMC4 - PWM compare register PWM 2 - - R/W 00060EH SMC4 - PWM Select register PWS14 - R/W 00060FH SMC4 - PWM Select register PWS24 - R/W 000610H00061BH Reserved - - - 00061CH LCD - Output Enable Register 0 (Seg 7-0) LCDER0 - R/W 00061DH LCD - Output Enable Register 1 (Seg 15-8) LCDER1 - R/W 00061EH LCD - Output Enable Register 2 (Seg 23-16) LCDER2 - R/W Document Number: 002-04582 Rev. *C Page 45 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 22 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 00061FH LCD - Output Enable Register 3 (Seg 31-24) LCDER3 - R/W 000620H LCD - Output Enable Register 4 (Seg 39-32) LCDER4 - R/W 000621H LCD - Output Enable Register 5 (Seg 47-40) LCDER5 - R/W 000622H LCD - Output Enable Register 6 (Seg 55-48) LCDER6 - R/W 000623H LCD - Output Enable Register 7 (Seg 63-56) LCDER7 - R/W 000624H LCD - Output Enable Register 8 (Seg 71-64) LCDER8 - R/W 000625H Reserved - - - 000626H LCD - Output Enable Register V (Vx) LCDVER - R/W 000627H LCD - Extended Control Register LECR - R/W 000628H LCD - Common pin switching register LCDCMR - R/W 000629H LCD - Control Register LCR - R/W 00062AH LCD - Data register for Segment 1-0 VRAM0 - R/W 00062BH LCD - Data register for Segment 3-2 VRAM1 - R/W 00062CH LCD - Data register for Segment 5-4 VRAM2 - R/W 00062DH LCD - Data register for Segment 7-6 VRAM3 - R/W 00062EH LCD - Data register for Segment 9-8 VRAM4 - R/W 00062FH LCD - Data register for Segment 11-10 VRAM5 - R/W 000630H LCD - Data register for Segment 13-12 VRAM6 - R/W 000631H LCD - Data register for Segment 15-14 VRAM7 - R/W 000632H LCD - Data register for Segment 17-16 VRAM8 - R/W 000633H LCD - Data register for Segment 19-18 VRAM9 - R/W 000634H LCD - Data register for Segment 21-20 VRAM10 - R/W 000635H LCD - Data register for Segment 23-22 VRAM11 - R/W 000636H LCD - Data register for Segment 25-24 VRAM12 - R/W 000637H LCD - Data register for Segment 27-26 VRAM13 - R/W 000638H LCD - Data register for Segment 29-28 VRAM14 - R/W 000639H LCD - Data register for Segment 31-30 VRAM15 - R/W 00063AH LCD - Data register for Segment 33-32 VRAM16 - R/W 00063BH LCD - Data register for Segment 35-34 VRAM17 - R/W 00063CH LCD - Data register for Segment 37-36 VRAM18 - R/W Document Number: 002-04582 Rev. *C Page 46 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 23 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 00063DH LCD - Data register for Segment 39-38 VRAM19 - R/W 00063EH LCD - Data register for Segment 41-40 VRAM20 - R/W 00063FH LCD - Data register for Segment 43-42 VRAM21 - R/W 000640H LCD - Data register for Segment 45-44 VRAM22 - R/W 000641H LCD - Data register for Segment 47-46 VRAM23 - R/W 000642H LCD - Data register for Segment 49-48 VRAM24 - R/W 000643H LCD - Data register for Segment 51-50 VRAM25 - R/W 000644H LCD - Data register for Segment 53-52 VRAM26 - R/W 000645H LCD - Data register for Segment 55-54 VRAM27 - R/W 000646H LCD - Data register for Segment 57-56 VRAM28 - R/W 000647H LCD - Data register for Segment 59-58 VRAM29 - R/W 000648H LCD - Data register for Segment 61-60 VRAM30 - R/W 000649H LCD - Data register for Segment 63-62 VRAM31 - R/W 00064AH LCD - Data register for Segment 65-64 VRAM32 - R/W 00064BH00065FH Reserved - - - 000660H Peripheral Resource Relocation Register 10 PRRR10 - R/W 000661H Peripheral Resource Relocation Register 11 PRRR11 - R/W 000662H Peripheral Resource Relocation Register 12 PRRR12 - R/W 000663H Peripheral Resource Relocation Register 13 PRRR13 - W 000664H0006DFH Reserved - - - 0006E0H External Bus - Area configuration register 0 Low EACL0 EAC0 R/W 0006E1H External Bus - Area configuration register 0 High EACH0 - R/W 0006E2H External Bus - Area configuration register 1 Low EACL1 EAC1 R/W 0006E3H External Bus - Area configuration register 1 High EACH1 - R/W 0006E4H External Bus - Area configuration register 2 Low EACL2 EAC2 R/W 0006E5H External Bus - Area configuration register 2 High EACH2 - R/W 0006E6H External Bus - Area configuration register 3 Low EACL3 EAC3 R/W 0006E7H External Bus - Area configuration register 3 High EACH3 - R/W 0006E8H External Bus - Area configuration register 4 Low EACL4 EAC4 R/W Document Number: 002-04582 Rev. *C Page 47 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 24 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0006E9H External Bus - Area configuration register 4 High EACH4 - R/W 0006EAH External Bus - Area configuration register 5 Low EACL5 EAC5 R/W 0006EBH External Bus - Area configuration register 5 High EACH5 - R/W 0006ECH External Bus - Area select register 2 EAS2 - R/W 0006EDH External Bus - Area select register 3 EAS3 - R/W 0006EEH External Bus - Area select register 4 EAS4 - R/W 0006EFH External Bus - Area select register 5 EAS5 - R/W 0006F0H External Bus - Mode register EBM - R/W 0006F1H External Bus - Clock and Function register EBCF - R/W 0006F2H External Bus - Address output enable register 0 EBAE0 - R/W 0006F3H External Bus - Address output enable register 1 EBAE1 - R/W 0006F4H External Bus - Address output enable register 2 EBAE2 - R/W 0006F5H External Bus - Control signal register EBCS - R/W 0006F6H0006FFH Reserved - - - 000700H CAN0 - Control register Low CTRLRL0 CTRLR0 R/W 000701H CAN0 - Control register High (reserved) CTRLRH0 - R 000702H CAN0 - Status register Low STATRL0 STATR0 R/W 000703H CAN0 - Status register High (reserved) STATRH0 - R 000704H CAN0 - Error Counter Low (Transmit) ERRCNTL0 ERRCNT0 R 000705H CAN0 - Error Counter High (Receive) ERRCNTH0 - R 000706H CAN0 - Bit Timing Register Low BTRL0 BTR0 R/W 000707H CAN0 - Bit Timing Register High BTRH0 - R/W 000708H CAN0 - Interrupt Register Low INTRL0 INTR0 R 000709H CAN0 - Interrupt Register High INTRH0 - R 00070AH CAN0 - Test Register Low TESTRL0 TESTR0 R/W 00070BH CAN0 - Test Register High (reserved) TESTRH0 - R 00070CH CAN0 - BRP Extension register Low BRPERL0 BRPER0 R/W 00070DH CAN0 - BRP Extension register High (reserved) BRPERH0 - R 00070EH00070FH Reserved - - - Document Number: 002-04582 Rev. *C Page 48 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 25 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000710H CAN0 - IF1 Command request register Low IF1CREQL0 IF1CREQ0 R/W 000711H CAN0 - IF1 Command request register High IF1CREQH0 - R/W 000712H CAN0 - IF1 Command Mask register Low IF1CMSKL0 IF1CMSK0 R/W 000713H CAN0 - IF1 Command Mask register High (reserved) IF1CMSKH0 - R 000714H CAN0 - IF1 Mask 1 Register Low IF1MSK1L0 IF1MSK10 R/W 000715H CAN0 - IF1 Mask 1 Register High IF1MSK1H0 - R/W 000716H CAN0 - IF1 Mask 2 Register Low IF1MSK2L0 IF1MSK20 R/W 000717H CAN0 - IF1 Mask 2 Register High IF1MSK2H0 - R/W 000718H CAN0 - IF1 Arbitration 1 Register Low IF1ARB1L0 IF1ARB10 R/W 000719H CAN0 - IF1 Arbitration 1 Register High IF1ARB1H0 - R/W 00071AH CAN0 - IF1 Arbitration 2 Register Low IF1ARB2L0 IF1ARB20 R/W 00071BH CAN0 - IF1 Arbitration 2 Register High IF1ARB2H0 - R/W 00071CH CAN0 - IF1 Message Control Register Low IF1MCTRL0 IF1MCTR0 R/W 00071DH CAN0 - IF1 Message Control Register High IF1MCTRH0 - R/W 00071EH CAN0 - IF1 Data A1 Low IF1DTA1L0 IF1DTA10 R/W 00071FH CAN0 - IF1 Data A1 High IF1DTA1H0 - R/W 000720H CAN0 - IF1 Data A2 Low IF1DTA2L0 IF1DTA20 R/W 000721H CAN0 - IF1 Data A2 High IF1DTA2H0 - R/W 000722H CAN0 - IF1 Data B1 Low IF1DTB1L0 IF1DTB10 R/W 000723H CAN0 - IF1 Data B1 High IF1DTB1H0 - R/W 000724H CAN0 - IF1 Data B2 Low IF1DTB2L0 IF1DTB20 R/W 000725H CAN0 - IF1 Data B2 High IF1DTB2H0 - R/W 000726H00073FH Reserved - - - 000740H CAN0 - IF2 Command request register Low IF2CREQL0 IF2CREQ0 R/W 000741H CAN0 - IF2 Command request register High IF2CREQH0 - R/W 000742H CAN0 - IF2 Command Mask register Low IF2CMSKL0 IF2CMSK0 R/W 000743H CAN0 - IF2 Command Mask register High (reserved) IF2CMSKH0 - R 000744H CAN0 - IF2 Mask 1 Register Low IF2MSK1L0 IF2MSK10 R/W 000745H CAN0 - IF2 Mask 1 Register High IF2MSK1H0 - R/W Document Number: 002-04582 Rev. *C Page 49 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 26 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000746H CAN0 - IF2 Mask 2 Register Low IF2MSK2L0 IF2MSK20 R/W 000747H CAN0 - IF2 Mask 2 Register High IF2MSK2H0 - R/W 000748H CAN0 - IF2 Arbitration 1 Register Low IF2ARB1L0 IF2ARB10 R/W 000749H CAN0 - IF2 Arbitration 1 Register High IF2ARB1H0 - R/W 00074AH CAN0 - IF2 Arbitration 2 Register Low IF2ARB2L0 IF2ARB20 R/W 00074BH CAN0 - IF2 Arbitration 2 Register High IF2ARB2H0 - R/W 00074CH CAN0 - IF2 Message Control Register Low IF2MCTRL0 IF2MCTR0 R/W 00074DH CAN0 - IF2 Message Control Register High IF2MCTRH0 - R/W 00074EH CAN0 - IF2 Data A1 Low IF2DTA1L0 IF2DTA10 R/W 00074FH CAN0 - IF2 Data A1 High IF2DTA1H0 - R/W 000750H CAN0 - IF2 Data A2 Low IF2DTA2L0 IF2DTA20 R/W 000751H CAN0 - IF2 Data A2 High IF2DTA2H0 - R/W 000752H CAN0 - IF2 Data B1 Low IF2DTB1L0 IF2DTB10 R/W 000753H CAN0 - IF2 Data B1 High IF2DTB1H0 - R/W 000754H CAN0 - IF2 Data B2 Low IF2DTB2L0 IF2DTB20 R/W 000755H CAN0 - IF2 Data B2 High IF2DTB2H0 - R/W 000756H00077FH Reserved - - - 000780H CAN0 - Transmission Request 1 Register Low TREQR1L0 TREQR10 R 000781H CAN0 - Transmission Request 1 Register High TREQR1H0 - R 000782H CAN0 - Transmission Request 2 Register Low TREQR2L0 TREQR20 R 000783H CAN0 - Transmission Request 2 Register High TREQR2H0 - R 000784H00078FH Reserved - - - 000790H CAN0 - New Data 1 Register Low NEWDT1L0 NEWDT10 R 000791H CAN0 - New Data 1 Register High NEWDT1H0 - R 000792H CAN0 - New Data 2 Register Low NEWDT2L0 NEWDT20 R 000793H CAN0 - New Data 2 Register High NEWDT2H0 - R 000794H00079FH Reserved - - - 0007A0H CAN0 - Interrupt Pending 1 Register Low INTPND1L0 INTPND10 R 0007A1H CAN0 - Interrupt Pending 1 Register High INTPND1H0 - R Document Number: 002-04582 Rev. *C Page 50 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 27 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0007A2H CAN0 - Interrupt Pending 2 Register Low INTPND2L0 INTPND20 R 0007A3H CAN0 - Interrupt Pending 2 Register High INTPND2H0 - R 0007A4H0007AFH Reserved - - - 0007B0H CAN0 - Message Valid 1 Register Low MSGVAL1L0 MSGVAL10 R 0007B1H CAN0 - Message Valid 1 Register High MSGVAL1H0 - R 0007B2H CAN0 - Message Valid 2 Register Low MSGVAL2L0 MSGVAL20 R 0007B3H CAN0 - Message Valid 2 Register High MSGVAL2H0 - R 0007B4H0007CDH Reserved - - - 0007CEH CAN0 - Output enable register COER0 - R/W 0007CFH Reserved - - - 0007D0H SG0 - Sound Generator Control Register Low SGCRL0 SGCR0 R/W 0007D1H SG0 - Sound Generator Control Register High SGCRH0 - R/W 0007D2H SG0 - Sound Generator Frequency Register SGFR0 - R/W 0007D3H SG0 - Sound Generator Amplitude Register SGAR0 - R/W 0007D4H SG0 - Sound Generator Decrement Register SGDR0 - R/W 0007D5H SG0 - Sound Generator Tone Register SGTR0 - R/W 0007D6H SG1 - Sound Generator Control Register Low SGCRL1 SGCR1 R/W 0007D7H SG1 - Sound Generator Control Register High SGCRH1 - R/W 0007D8H SG1 - Sound Generator Frequency Register SGFR1 - R/W 0007D9H SG1 - Sound Generator Amplitude Register SGAR1 - R/W 0007DAH SG1 - Sound Generator Decrement Register SGDR1 - R/W 0007DBH SG1 - Sound Generator Tone Register SGTR1 - R/W 0007DCH0007FFH Reserved - - - 000800H CAN1 - Control register Low CTRLRL1 CTRLR1 R/W 000801H CAN1 - Control register High (reserved) CTRLRH1 - R 000802H CAN1 - Status register Low STATRL1 STATR1 R/W 000803H CAN1 - Status register High (reserved) STATRH1 - R 000804H CAN1 - Error Counter Low (Transmit) ERRCNTL1 ERRCNT1 R 000805H CAN1 - Error Counter High (Receive) ERRCNTH1 - R Document Number: 002-04582 Rev. *C Page 51 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 28 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000806H CAN1 - Bit Timing Register Low BTRL1 BTR1 R/W 000807H CAN1 - Bit Timing Register High BTRH1 - R/W 000808H CAN1 - Interrupt Register Low INTRL1 INTR1 R 000809H CAN1 - Interrupt Register High INTRH1 - R 00080AH CAN1 - Test Register Low TESTRL1 TESTR1 R/W 00080BH CAN1 - Test Register High (reserved) TESTRH1 - R 00080CH CAN1 - BRP Extension register Low BRPERL1 BRPER1 R/W 00080DH CAN1 - BRP Extension register High (reserved) BRPERH1 - R 00080EH00080FH Reserved - - - 000810H CAN1 - IF1 Command request register Low IF1CREQL1 IF1CREQ1 R/W 000811H CAN1 - IF1 Command request register High IF1CREQH1 - R/W 000812H CAN1 - IF1 Command Mask register Low IF1CMSKL1 IF1CMSK1 R/W 000813H CAN1 - IF1 Command Mask register High (reserved) IF1CMSKH1 - R 000814H CAN1 - IF1 Mask 1 Register Low IF1MSK1L1 IF1MSK11 R/W 000815H CAN1 - IF1 Mask 1 Register High IF1MSK1H1 - R/W 000816H CAN1 - IF1 Mask 2 Register Low IF1MSK2L1 IF1MSK21 R/W 000817H CAN1 - IF1 Mask 2 Register High IF1MSK2H1 - R/W 000818H CAN1 - IF1 Arbitration 1 Register Low IF1ARB1L1 IF1ARB11 R/W 000819H CAN1 - IF1 Arbitration 1 Register High IF1ARB1H1 - R/W 00081AH CAN1 - IF1 Arbitration 2 Register Low IF1ARB2L1 IF1ARB21 R/W 00081BH CAN1 - IF1 Arbitration 2 Register High IF1ARB2H1 - R/W 00081CH CAN1 - IF1 Message Control Register Low IF1MCTRL1 IF1MCTR1 R/W 00081DH CAN1 - IF1 Message Control Register High IF1MCTRH1 - R/W 00081EH CAN1 - IF1 Data A1 Low IF1DTA1L1 IF1DTA11 R/W 00081FH CAN1 - IF1 Data A1 High IF1DTA1H1 - R/W 000820H CAN1 - IF1 Data A2 Low IF1DTA2L1 IF1DTA21 R/W 000821H CAN1 - IF1 Data A2 High IF1DTA2H1 - R/W 000822H CAN1 - IF1 Data B1 Low IF1DTB1L1 IF1DTB11 R/W 000823H CAN1 - IF1 Data B1 High IF1DTB1H1 - R/W Document Number: 002-04582 Rev. *C Page 52 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 29 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000824H CAN1 - IF1 Data B2 Low IF1DTB2L1 IF1DTB21 R/W 000825H CAN1 - IF1 Data B2 High IF1DTB2H1 - R/W 000826H00083FH Reserved - - - 000840H CAN1 - IF2 Command request register Low IF2CREQL1 IF2CREQ1 R/W 000841H CAN1 - IF2 Command request register High IF2CREQH1 - R/W 000842H CAN1 - IF2 Command Mask register Low IF2CMSKL1 IF2CMSK1 R/W 000843H CAN1 - IF2 Command Mask register High (reserved) IF2CMSKH1 - R 000844H CAN1 - IF2 Mask 1 Register Low IF2MSK1L1 IF2MSK11 R/W 000845H CAN1 - IF2 Mask 1 Register High IF2MSK1H1 - R/W 000846H CAN1 - IF2 Mask 2 Register Low IF2MSK2L1 IF2MSK21 R/W 000847H CAN1 - IF2 Mask 2 Register High IF2MSK2H1 - R/W 000848H CAN1 - IF2 Arbitration 1 Register Low IF2ARB1L1 IF2ARB11 R/W 000849H CAN1 - IF2 Arbitration 1 Register High IF2ARB1H1 - R/W 00084AH CAN1 - IF2 Arbitration 2 Register Low IF2ARB2L1 IF2ARB21 R/W 00084BH CAN1 - IF2 Arbitration 2 Register High IF2ARB2H1 - R/W 00084CH CAN1 - IF2 Message Control Register Low IF2MCTRL1 IF2MCTR1 R/W 00084DH CAN1 - IF2 Message Control Register High IF2MCTRH1 - R/W 00084EH CAN1 - IF2 Data A1 Low IF2DTA1L1 IF2DTA11 R/W 00084FH CAN1 - IF2 Data A1 High IF2DTA1H1 - R/W 000850H CAN1 - IF2 Data A2 Low IF2DTA2L1 IF2DTA21 R/W 000851H CAN1 - IF2 Data A2 High IF2DTA2H1 - R/W 000852H CAN1 - IF2 Data B1 Low IF2DTB1L1 IF2DTB11 R/W 000853H CAN1 - IF2 Data B1 High IF2DTB1H1 - R/W 000854H CAN1 - IF2 Data B2 Low IF2DTB2L1 IF2DTB21 R/W 000855H CAN1 - IF2 Data B2 High IF2DTB2H1 - R/W 000856H00087FH Reserved - - - 000880H CAN1 - Transmission Request 1 Register Low TREQR1L1 TREQR11 R 000881H CAN1 - Transmission Request 1 Register High TREQR1H1 - R 000882H CAN1 - Transmission Request 2 Register Low TREQR2L1 TREQR21 R Document Number: 002-04582 Rev. *C Page 53 of 119 CY96380 Series I/O Map CY96(F)38x (Sheet 30 of 30) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access TREQR2H1 - R - - - 000883H CAN1 - Transmission Request 2 Register High 000884H00088FH Reserved 000890H CAN1 - New Data 1 Register Low NEWDT1L1 NEWDT11 R 000891H CAN1 - New Data 1 Register High NEWDT1H1 - R 000892H CAN1 - New Data 2 Register Low NEWDT2L1 NEWDT21 R 000893H CAN1 - New Data 2 Register High NEWDT2H1 - R 000894H00089FH Reserved - - - 0008A0H CAN1 - Interrupt Pending 1 Register Low INTPND1L1 INTPND11 R 0008A1H CAN1 - Interrupt Pending 1 Register High INTPND1H1 - R 0008A2H CAN1 - Interrupt Pending 2 Register Low INTPND2L1 INTPND21 R 0008A3H CAN1 - Interrupt Pending 2 Register High INTPND2H1 - R 0008A4H0008AFH Reserved - - - 0008B0H CAN1 - Message Valid 1 Register Low MSGVAL1L1 MSGVAL11 R 0008B1H CAN1 - Message Valid 1 Register High MSGVAL1H1 - R 0008B2H CAN1 - Message Valid 2 Register Low MSGVAL2L1 MSGVAL21 R 0008B3H CAN1 - Message Valid 2 Register High MSGVAL2H1 - R 0008B4H0008CDH Reserved - - - 0008CEH CAN1 - Output enable register COER1 - R/W 0008CFH000BFFH Reserved - - - Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. Document Number: 002-04582 Rev. *C Page 54 of 119 CY96380 Series 13. Interrupt Vector Table Interrupt Vector Table CY96(F)38x (Sheet 1 of 3) Vector Number Offset in Vector Table Vector Name Cleared by DMA Index in ICR to Program 0 3FCH CALLV0 No - 1 3F8H CALLV1 No - 2 3F4H CALLV2 No - 3 3F0H CALLV3 No - 4 3ECH CALLV4 No - 5 3E8H CALLV5 No - 6 3E4H CALLV6 No - 7 3E0H CALLV7 No - 8 3DCH RESET No - 9 3D8H INT9 No - 10 3D4H EXCEPTION No - 11 3D0H NMI No - 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH RESERVED No 16 Reserved 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H EXTINT1 Yes 18 External Interrupt 1 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H EXTINT5 Yes 22 External Interrupt 5 23 3A0H EXTINT6 Yes 23 External Interrupt 6 24 39CH EXTINT7 Yes 24 External Interrupt 7 25 398H CAN0 No 25 CAN Controller 0 26 394H CAN1* No 26 CAN Controller 1 27 390H PPG0 Yes 27 Programmable Pulse Generator 0 28 38CH PPG1 Yes 28 Programmable Pulse Generator 1 29 388H PPG2 Yes 29 Programmable Pulse Generator 2 30 384H PPG3 Yes 30 Programmable Pulse Generator 3 31 380H PPG4 Yes 31 Programmable Pulse Generator 4 32 37CH PPG5 Yes 32 Programmable Pulse Generator 5 33 378H PPG6 Yes 33 Programmable Pulse Generator 6 34 374H PPG7 Yes 34 Programmable Pulse Generator 7 Document Number: 002-04582 Rev. *C Description Non-Maskable Interrupt Page 55 of 119 CY96380 Series Interrupt Vector Table CY96(F)38x (Sheet 2 of 3) Vector Number Offset in Vector Table Vector Name Cleared by DMA Index in ICR to Program 35 370H RLT0 Yes 35 Reload Timer 0 36 36CH RLT1 Yes 36 Reload Timer 1 37 368H RLT2 Yes 37 Reload Timer 2 38 364H RLT3 Yes 38 Reload Timer 3 39 360H PPGRLT Yes 39 Reload Timer 6 - dedicated for PPG 40 35CH ICU0 Yes 40 Input Capture Unit 0 41 358H ICU1 Yes 41 Input Capture Unit 1 42 354H ICU2 Yes 42 Input Capture Unit 2 43 350H ICU3 Yes 43 Input Capture Unit 3 44 34CH ICU4 Yes 44 Input Capture Unit 4 45 348H ICU5 Yes 45 Input Capture Unit 5 46 344H ICU6 Yes 46 Input Capture Unit 6 47 340H ICU7 Yes 47 Input Capture Unit 7 48 33CH OCU0 Yes 48 Output Compare Unit 0 49 338H OCU1 Yes 49 Output Compare Unit 1 50 334H OCU2 Yes 50 Output Compare Unit 2 51 330H OCU3 Yes 51 Output Compare Unit 3 52 32CH FRT0 Yes 52 Free Running Timer 0 53 328H FRT1 Yes 53 Free Running Timer 1 54 324H RTC0 No 54 Real Timer Clock 55 320H CAL0 No 55 Clock Calibration Unit 56 31CH SG0 No 56 Sound Generator 0 57 318H SG1 No 57 Sound Generator 1 58 314H IIC0 Yes 58 I2C interface 59 310H ADC0 Yes 59 A/D Converter 60 30CH ALARM0 No 60 Alarm Comparator 0 61 308H ALARM1* No 61 Alarm Comparator 1 62 304H LINR0 Yes 62 LIN USART 0 RX 63 300H LINT0 Yes 63 LIN USART 0 TX 64 2FCH LINR1 Yes 64 LIN USART 1 RX 65 2F8H LINT1 Yes 65 LIN USART 1 TX 66 2F4H LINR2 Yes 66 LIN USART 2 RX 67 2F0H LINT2 Yes 67 LIN USART 2 TX 68 2ECH LINR4 Yes 68 LIN USART 4 RX 69 2E8H LINT4 Yes 69 LIN USART 4 TX 70 2E4H LINR5 Yes 70 LIN USART 5 RX 71 2E0H LINT5 Yes 71 LIN USART 5 TX Document Number: 002-04582 Rev. *C Description Page 56 of 119 CY96380 Series Interrupt Vector Table CY96(F)38x (Sheet 3 of 3) Vector Number Offset in Vector Table Vector Name Cleared by DMA Index in ICR to Program Description 72 2DCH FLASH_A No 72 Flash memory A (only Flash devices) 73 2D8H FLASH_B No 73 Flash memory B (only CY96F388/F389) *: ALARM1 and CAN1 are not included on CY96384 and CY96(F)385 devices Document Number: 002-04582 Rev. *C Page 57 of 119 CY96380 Series 14. Handling Devices Special care is required for the following when handling the device: • • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Unused sub clock signal Notes on PLL clock mode operation Power supply pins (VCC/VSS) Crystal oscillator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on energization Stabilization of power supply voltage SMC power supply pins Serial communication 14.1 Latch-up prevention CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC pins and VSS pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 14.2 Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 14.3 External clock usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 1. Single phase external clock • When using a single phase external clock, X0 pin must be driven and X1 pin left open. X0 X1 Document Number: 002-04582 Rev. *C Page 58 of 119 CY96380 Series 2. Opposite phase external clock • When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 X1 14.4 Unused sub clock signal If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. 14.5 Notes on PLL clock mode operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 14.6 Power supply pins (VCC/VSS) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. VCC and VSS must be connected to the device from the power supply with lowest possible impedance. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 F between VCC and VSS as close as possible to VCC and VSS pins. 14.7 Crystal oscillator and ceramic resonator circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 14.8 Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 14.9 Pin handling when not using the A/D converter It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 14.10 Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50s from 0.2 V to 2.7 V. 14.11 Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1 V/s or less in instantaneous fluctuation for power supply switching. Document Number: 002-04582 Rev. *C Page 59 of 119 CY96380 Series 14.12 SMC power supply pins All DVSS pins must be set to the same level as the VSS pins. The DVCC power supply level can be set independently of the VCC power supply level. However note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3 V. To avoid this, we recommend to always power VCC before DVCC. 14.13 Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. Document Number: 002-04582 Rev. *C Page 60 of 119 CY96380 Series 15. Electrical Characteristics 15.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *1 AD Converter voltage references AVRH, AVRL VSS - 0.3 VSS + 6.0 V AVCC AVRH, AVCC AVRL, AVRH AVRL, AVRL AVSS SMC Power supply DVCC VSS - 0.3 VSS + 6.0 V See *7 V0 to V3 VSS - 0.3 VSS + 6.0 V V0 to V3 must not exceed VCC Input voltage VI VSS - 0.3 VSS + 6.0 V VI (D)VCC + 0.3 V *2 Output voltage VO VSS - 0.3 VSS + 6.0 V VO (D)VCC + 0.3 V *2 ICLAMP -4.0 +4.0 mA Applicable to general purpose I/O pins *3 |ICLAMP| - 40 mA Applicable to general purpose I/O pins *3 IOL1 - 15 mA Normal outputs with driving strength set to 5mA IOLSMC - 40 mA High current outputs with driving strength set to 30mA IOLAV1 - 5 mA Normal outputs with driving strength set to 5mA IOLAVSMC - 30 mA High current outputs with driving strength set to 30mA IOL1 - 100 mA Normal outputs IOLSMC - 330 mA High current outputs IOLAV1 - 50 mA Normal outputs IOLAVSMC - 250 mA High current outputs IOH1 - -15 mA Normal outputs with driving strength set to 5 mA IOHSMC - -40 mA High current outputs with driving strength set to 30 mA IOHAV1 - -5 mA Normal outputs with driving strength set to 5 mA IOHAVSMC - -30 mA High current outputs with driving strength set to 30 mA IOH1 - -100 mA Normal outputs IOHSMC - -330 mA High current outputs IOHAV1 - -50 mA Normal outputs IOHASMC - -250 mA High current outputs Power supply voltage LCD power supply voltage Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level average overall output current ”H” level maximum output current ”H” level average output current ”H” level maximum overall output current ”H” level average overall output current Document Number: 002-04582 Rev. *C Page 61 of 119 CY96380 Series Parameter Permitted Power dissipation (CY96F385) *4 Permitted Power dissipation (CY96F386/F387/F388/F389) *4 Permitted Power dissipation (CY96384/385) *4 Operating ambient temperature Storage temperature Symbol PD PD PD TA TSTG Rating Unit Remarks Min Max - 295*5 mW TA=105oC - 595*5 mW TA=85oC - 820*5 mW TA=70oC - 370*5 o mW TA=125 C, no Flash program/erase - 670*5 o mW TA=105 C, no Flash program/erase - 370*5 mW TA=105oC - 740*5 mW TA=85oC - 1000*5 mW TA=70oC - 460*5 o mW TA=125 C, no Flash program/erase - 800*5 o mW TA=105 C, no Flash program/erase - 310*5 mW TA=105oC - 625*5 mW TA=85oC - 800*5 mW TA=70oC - 390*5 mW TA=125oC *6 - 700*5 mW TA=105oC*6 0 +70 -40 +105 -40 +125 -55 +150 *6 *6 *6 *6 CY96V300B oC *6 oC *1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. *2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of high current ports depend on DVCC. Input/output voltages of standard ports depend on VCC. *3:  Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality.  Use within recommended operating conditions.  Use at DC voltage (current)  The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.  The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.  Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.  Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. Document Number: 002-04582 Rev. *C Page 62 of 119 CY96380 Series  Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode).  No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins).  Sample recommended circuits: Protective Diode VCC Limiting resistance P-ch +B input (0 V to 16 V) N-ch R *4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. *5: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *6: Please contact Cypress for reliability limitations when using under these conditions. *7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04582 Rev. *C Page 63 of 119 CY96380 Series 15.2 Recommended Operating Conditions Parameter Power supply voltage Symbol Unit Min Typ Max VCC, DVCC 3.0 - 5.5 V CS 3.5 4.7 - 10 15 F Smoothing capacitor at C pin WARNING: Value Remarks Use a low inductance capacitor (for example X7R ceramic capacitor) The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04582 Rev. *C Page 64 of 119 CY96380 Series 15.3 DC characteristics (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition Port inputs Max 0.8 VCC - (D)VCC + 0.3 V 0.7 VCC - (D)VCC + 0.3 V (D)VCC 4.5 V 0.74 VCC - (D)VCC + 0.3 V (D)VCC < 4.5 V AUTOMOTIVE Hysteresis input selected 0.8 VCC - (D)VCC + 0.3 V TTL input selected 2.0 - (D)VCC + 0.3 V CMOS Hysteresis 0.7/0.3 input selected VIHX0F X0 External clock in “Fast Clock Input mode” 0.8 VCC - VCC + 0.3 V VIHX0S X0,X1, X0A,X1A External clock in “oscillation mode” 2.5 - VCC + 0.3 V VIHR RSTX - 0.8 VCC - VCC + 0.3 V VIHM MD2-MD0 - VCC 0.3 - VCC + 0.3 V CMOS Hysteresis 0.8/0.2 input selected VSS 0.3 - 0.2 (D)VCC V CMOS Hysteresis 0.7/0.3 input selected VSS 0.3 - 0.3 (D)VCC V VSS 0.3 - 0.5 (D)VCC V VSS 0.3 - 0.46 (D)VCC TTL input selected VSS 0.3 - 0.8 V VIL Port inputs Pnn_m Input L voltage AUTOMOTIVE Hysteresis input selected Not available in CY96F386xxA/F387xxA CMOS Hysteresis input (D)VCC 4.5 V (D)VCC < 4.5 V VILX0F X0 External clock in “Fast Clock Input mode” VSS 0.3 - 0.2 VCC V VILX0S X0,X1, X0A,X1A External clock in “oscillation mode” VSS 0.3 - 0.4 V VILR RSTX - VSS 0.3 - 0.2 VCC V VILM MD2-MD0 - VSS 0.3 - VSS + 0.3 V Document Number: 002-04582 Rev. *C Remarks Typ Pnn_m Input H voltage Unit Min CMOS Hysteresis 0.8/0.2 input selected VIH Value Not available in CY96F386xxA/F387xxA CMOS Hysteresis input Page 65 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition Value Unit Remarks - V Driving strength set to 2 mA - - V Driving strength set to 5 mA - - V Driving strength set to 30 mA - - V Min Typ Max (D)VCC - 0.5 - (D)VCC - 0.5 IOH = -30 mA DVCC High current outputs 0.5 3.0 V DVCC  4.5 V 4.5 V (D)VCC  5.5 V VOH2 Normal and High Current outputs IOH = -2 mA 3.0 V (D)VCC  4.5 V IOH = -1.6 mA 4.5 V (D)VCC  5.5 V VOH5 Normal and High Current outputs IOH = -5 mA 3.0 V (D)VCC  4.5 V IOH = -3 mA Output H voltage 4.5 V DVCC 5.5 V VOH30 IOH = -20 mA 4.5 V VCC  5.5 V VOH3 3mA outputs IOH = -3 mA 3.0 V VCC  4.5 V VCC 0.5 IOH = -2 mA Document Number: 002-04582 Rev. *C Page 66 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition Value Unit Remarks 0.4 V Driving strength set to 2 mA - 0.4 V Driving strength set to 5 mA - - 0.5 V Driving strength set to 30 mA - - 0.4 V AVSS, AVRL < VI < AVCC, AVRH -1 - +1 A Single port pin Maximum leakage current of all LCD pins Min Typ Max - - - 4.5 V (D)VCC  5.5 V VOL2 Normal and High Current outputs IOL = +2 mA 3.0 V (D)VCC  4.5 V IOL = +1.6 mA 4.5 V (D)VCC  5.5 V VOL5 Normal and High Current outputs Output L voltage IOL = +5 mA 3.0 V (D)VCC  4.5 V IOL = +3 mA 4.5 V DVCC  5.5 V VOL30 IOL = +30 mA High current outputs 3.0 V DVCC  4.5 V IOL = +20 mA VOL3 3mA outputs 3.0 V VCC  5.5 V IOL = +3 mA VSS < VI < VCC IIL Pnn_m Total LCD leak current |IILCD| all SEG/COM pins VCC = 5.0 V - 0.5 10 A Internal LCD divide resistance RLCD Between V3 and VSS VCC = 5.0 V 25 40 65 k Pull-up resistance RUP Pnn_m, RSTX VCC  3.3 V  10 40 100 160 k VCC  5.0 V  10 25 50 100 k Input leak current Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC. Document Number: 002-04582 Rev. *C Page 67 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Value Condition (at TA) Symbol +25°C PLL Run mode with CLKS1/2 = 48 MHz, CLKB = CLKP1/2 = 24 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) PLL Run mode with CLKS1/2 = CLKB = CLKP1= 56 MHz, CLKP2 = 28 MHz Power supply current in Run modes* (CLKRC and CLKSC stopped. Core voltage at 1.9 V) ICCPLL PLL Run mode with CLKS1/2 = 72 MHz, CLKB = CLKP1 = 36 MHz, CLKP2 = 18 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) PLL Run mode with CLKS1/2 = 80 MHz, CLKB = CLKP1 = 40 MHz, CLKP2 = 20 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) PLL Run mode with CLKS1/2 = 96 MHz, CLKB = CLKP1= 48 MHz, CLKP2 = 24 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) Document Number: 002-04582 Rev. *C Typ Max 35 44 +125°C 36 47 +25°C 38 46 +125°C 39 49 +25°C 16 22 +125°C 17 23.5 +25°C 44 57 +125°C 45 60 +25°C 24 34 +125°C 25 35.5 +25°C 38 50 +125°C 39 53 +25°C 43 55 +125°C 44 57 +25°C 48 60 +125°C 49 63 +25°C 25 35 +125°C 26 36.5 Unit Remarks mA CY96F385/F386/F387 at 0 Flash wait states mA CY96F388/F389 at 0 Flash wait states mA CY96384/385 at 0 ROM wait states mA CY96F386/F387 at 2 Flash wait states mA CY96384/385 at 2 ROM wait states mA CY96F386/F387 at 1 Flash wait state mA CY96F385 at 1 Flash wait state mA CY96F388/F389 at 1 Flash wait state mA CY96384/385 at 1 ROM wait state Page 68 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Value Condition (at TA) Symbol +25°C Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4 MHz ICCMAIN (CLKPLL, CLKSC and CLKRC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2 MHz ICCRCH (CLKMC, CLKPLL and CLKSC stopped) Power supply current in Run modes* Typ Max 4.5 5.5 +125°C 5.1 7.5 +25°C 4.5 5.5 +125°C 5.1 8.5 +25°C 4.8 6 +125°C 5.4 8.5 +25°C 2.5 3.5 +125°C 3.1 5 +25°C 2.5 3.6 +125°C 3.1 5.1 +25°C 2.9 4 +125°C 3.5 6.5 +25°C 1.7 2.7 +125°C 2.3 4.2 +25°C 0.4 0.6 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100 kHz, SMCR:LPMS = 0 +125°C 0.9 3.5 +25°C 0.4 0.6 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) +125°C 0.9 2.9 +25°C 0.4 0.6 +125°C 0.9 2 +25°C 0.15 0.25 Unit Remarks mA CY96F385 at 1 Flash wait state mA CY96F386/F387 at 1 Flash wait state mA CY96F388/F389 at 1 Flash wait state mA CY96384/385 at 1 ROM wait state mA CY96F385 at 1 Flash wait state mA CY96F386/F387/F388/F 389 at 1 Flash wait state mA CY96384/385 at 1 ROM wait state mA CY96F386/F387 at 1 Flash wait state CY96F388/F389 at 1 Flash wait state CY96384/385/F385 at 1 ROM/Flash wait state ICCRCL RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100 kHz, SMCR:LPMS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode, no Flash programming/ erasing allowed) +125°C 0.65 3.2 +25°C 0.15 0.25 +125°C 0.65 2.6 +25°C 0.15 0.25 +125°C Document Number: 002-04582 Rev. *C 0.65 1.75 mA CY96F386/F387 at 1 Flash wait state mA CY96F388/F389 at 1 Flash wait state mA CY96384/385/F385 at 1 ROM/Flash wait state Page 69 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Value Condition (at TA) +25°C Power supply current in Run modes* Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32 kHz ICCSUB (CLKMC, CLKPLL and CLKRC stopped, no Flash programming/erasing allowed) Max 0.1 0.2 +125°C 0.6 3 +25°C 0.1 0.2 +125°C 0.6 2.4 +25°C 0.1 0.2 +125°C Document Number: 002-04582 Rev. *C Typ 0.6 1.7 Unit Remarks mA CY96F386/F387 at 1 Flash wait state mA CY96F388/F389 at 1 Flash wait state mA CY96384/385/F385 at 1 ROM/Flash wait state Page 70 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter PLL Sleep mode with CLKS1/2 = 48 MHz, CLKP1/2 = 24 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) Power supply current in Sleep modes* PLL Sleep mode with CLKS1/2 = CLKP1= 56 MHz, CLKP2 = 28 MHz ICCSPLL Value Condition (at TA) Symbol (CLKRC and CLKSC stopped. Core voltage at 1.9 V) PLL Sleep mode with CLKS1/2 = 72 MHz, CLKP1 = 36 MHz, CLKP2 = 18 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) PLL Sleep mode with CLKS1/2 = 80 MHz, CLKP1 = 40 MHz, CLKP2 = 20 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) PLL Sleep mode with CLKS1/2 = 96 MHz, CLKP1= 48 MHz, CLKP2 = 24 MHz (CLKRC and CLKSC stopped. Core voltage at 1.9 V) Document Number: 002-04582 Rev. *C Typ Max +25°C 7.5 9 +125°C 8.2 10.5 +25°C 9 10.5 +125°C 9.7 13 +25°C 11 13 +125°C 11.7 15.5 +25°C 7 8.5 +125°C 7.7 10 +25°C 14 15.5 +125°C 14.8 18 +25°C 12 13.5 +125°C 12.8 15 +25°C 10.5 12 +125°C 11.3 14.5 +25°C 14 17 +125°C 14.8 19.5 +25°C 13 14.5 +125°C 13.8 16 Unit Remarks mA CY96F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385 mA CY96F386/F387 mA CY96384/385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 Page 71 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter ICCSMAIN Typ Max +25°C 1.5 1.8 +125°C 2 4.5 Main Sleep mode with CLKS1/2 = CLKP1/2 = 4 MHz +25°C 1.6 2 (CLKPLL, CLKSC and CLKRC stopped) +125°C 2.1 4.2 +25°C 1.5 1.8 +125°C 2 3.3 +25°C 0.9 1.4 +125°C 1.5 4 RC Sleep mode with CLKS1/2 = CLKP1/2 = 2 MHz +25°C 0.9 1.4 (CLKMC, CLKPLL and CLKSC stopped) +125°C 1.5 3.5 +25°C 0.9 1.4 +125°C 1.5 2.8 Power supply current in Sleep modes* ICCSRCH Value Condition (at TA) Symbol Document Number: 002-04582 Rev. *C Unit Remarks mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 Page 72 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Value Condition (at TA) Symbol Typ Max +25°C 0.3 0.5 +125°C 0.8 3.4 +25°C 0.3 0.5 +125°C 0.8 2.8 +25°C 0.3 0.5 +125°C 0.8 2 +25°C 0.06 0.15 +125°C 0.56 3 +25°C 0.06 0.15 +125°C 0.56 2.4 +25°C 0.06 0.15 +125°C 0.56 1.6 +25°C 0.04 0.12 +125°C 0.54 2.9 Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32 kHz +25°C 0.04 0.12 (CLKMC, CLKPLL and CLKRC stopped) +125°C 0.54 2.3 +25°C 0.04 0.12 +125°C 0.54 1.55 +25°C 1.6 2 +125°C 2.1 4.8 PLL Timer mode with CLKMC = 4MHz, CLKPLL = 48 MHz +25°C 1.6 2 (CLKRC and CLKSC stopped. Core voltage at 1.9 V) +125°C 2.1 4.2 +25°C 1.6 2 +125°C 2.1 3.5 RC Sleep mode with CLKS1/2 = CLKP1/2 = 100 kHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) Unit Remarks mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 ICCSRCL RC Sleep mode with CLKS1/2 = CLKP1/2 = 100 kHz, SMCR:LPMSS = 1 Power supply current in Sleep modes* (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) ICCSSUB Power supply current in Timer modes* ICCTPLL Document Number: 002-04582 Rev. *C Page 73 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Value Condition (at TA) Symbol Main Timer mode with CLKMC = 4 MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode) Typ Max +25°C 0.35 0.5 +125°C 0.85 3.3 +25°C 0.35 0.5 +125°C 0.85 2.7 +25°C 0.35 0.5 +125°C 0.85 2 +25°C 0.1 0.15 +125°C 0.6 2.9 +25°C 0.1 0.15 +125°C 0.6 2.3 +25°C 0.1 0.18 +125°C 0.6 1.6 +25°C 0.35 0.5 +125°C 0.85 3.3 +25°C 0.35 0.5 +125°C 0.85 2.7 +25°C 0.35 0.5 +125°C 0.85 2 +25°C 0.1 0.15 +125°C 0.6 2.9 +25°C 0.1 0.15 +125°C 0.6 2.3 +25°C 0.1 0.15 +125°C 0.6 1.6 Unit Remarks mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 ICCTMAIN Main Timer mode with CLKMC = 4 MHz, SMCR:LPMSS = 1 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) CY96384/385/F385 Power supply current in Timer modes* RC Timer mode with CLKRC = 2 MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) mA CY9CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 ICCTRCH RC Timer mode with CLKRC = 2 MHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Document Number: 002-04582 Rev. *C Page 74 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Value Condition (at TA) Symbol Typ Max +25°C 0.3 0.45 +125°C 0.8 3.2 +25°C 0.3 0.45 +125°C 0.8 2.6 +25°C 0.3 0.45 +125°C 0.8 1.95 +25°C 0.05 0.1 +125°C 0.55 2.8 +25°C 0.05 0.1 +125°C 0.55 2.2 +25°C 0.05 0.1 +125°C 0.55 1.55 +25°C 0.03 0.1 +125°C 0.53 2.8 Sub Timer mode with CLKSC = 32 kHz +25°C 0.03 0.1 (CLKMC, CLKPLL and CLKRC stopped) +125°C 0.53 2.2 +25°C 0.03 0.1 +125°C 0.53 1.55 RC Timer mode with CLKRC = 100 kHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) Unit Remarks mA CY96F386/F387 mA CY96F386/F387 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 ICCTRCL RC Timer mode with CLKRC = 100 kHz, SMCR:LPMSS = 1 Power supply current in Timer modes* (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) ICCTSUB Document Number: 002-04582 Rev. *C Page 75 of 119 CY96380 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Power supply current in Stop Mode Power supply current for active Low Voltage detector Value Condition (at TA) Symbol Typ Max +25°C 0.02 0.08 +125°C 0.52 2.8 VRCR:LPMB[2:0] = 110B +25°C 0.02 0.08 (Core voltage at 1.8 V) +125°C 0.52 2.2 +25°C 0.02 0.08 +125°C 0.52 1.5 +25°C 0.015 0.06 +125°C 0.4 2.3 VRCR:LPMB[2:0] = 000B +25°C 0.015 0.06 (Core voltage at 1.2 V) +125°C 0.4 1.65 +25°C 0.015 0.06 +125°C 0.4 1.2 +25°C 90 140 Unit Remarks mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 mA CY96F386/F387 mA CY96F388/F389 mA CY96384/385/F385 A This current must be added to all Power supply currents above ICCH ICCLVD Low voltage detector enabled (RCR:LVDE = 1) +125°C 100 150 Power supply current for active Clock modulator ICCCLOMO Clock modulator enabled (CMCR:PDX = 1) - 3 4.5 mA Must be added to all current above Flash Write/Erase current ICCFLASH Current for one Flash module - 15 40 mA Must be added to all current above Input capacitance CIN - 15 30 pF High current outputs pF Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, High current outputs Input capacitance CIN - - 5 15 *: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32 kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Document Number: 002-04582 Rev. *C Page 76 of 119 CY96380 Series 15.4 AC Characteristics Source Clock Timing Parameter Clock frequency Clock frequency Clock frequency (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Symbol fC Pin X0, X1 fFCI fCL Value X0A Remarks Typ Max 3 - 16 MHz When using a crystal oscillator, PLL off 0 - 16 using an opposite phase external clock, MHz When PLL off 3.5 - 16 using a crystal oscillator or opposite MHz When phase external clock, PLL on 0 - 56 When using a single phase external clock in MHz “Fast Clock Input mode” (not available in CY96F386xxA and CY96F387xxA), PLL off 3.5 - 56 When using a single phase external clock in MHz “Fast Clock Input mode” (not available in CY96F386xxA and CY96F387xxA), PLL on 32 32.768 100 kHz When using an oscillation circuit 0 - 100 kHz When using an opposite phase external clock 0 - 50 kHz When using a single phase external clock 50 100 200 kHz When using slow frequency of RC oscillator 1 2 4 X0 X0A, X1A Unit Min fCR - PLL Clock frequency fCLKVCO - 64 - 200 PLL Phase Jitter TPSKEW - - - 5 ns For CLKMC (PLL input clock) MHz Input clock pulse width PWH, PWL X0,X1 8 - - ns Duty ratio is about 30% to 70% Input clock pulse width PWHL, PWLL X0A,X1A 5 - - s Clock frequency MHz When using fast frequency of RC oscillator VCO output frequency of PLL MHz Permitted (CLKVCO) tCYL VIH X0 VIL PWH PWL tCYLL VIH X0A VIL PWH Document Number: 002-04582 Rev. *C PWL Page 77 of 119 CY96380 Series Internal Clock Timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Core Voltage Settings Parameter Internal System clock frequency (CLKS1 and CLKS2) Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) Internal peripheral clock frequency (CLKP2) Symbol fCLKS1, fCLKS2 fCLKB, fCLKP1 fCLKP2 Document Number: 002-04582 Rev. *C 1.8 V 1.9 V Unit Remarks Min Max Min Max 0 92 0 96 MHz Others than below 0 72 0 80 MHz CY96F385/F388/F389 0 68 0 74 MHz CY96F386/F387 0 52 0 56 MHz Others than below 0 36 0 40 MHz CY96F385/F388/F389 0 28 0 32 MHz Others than below 0 26 0 28 MHz CY96F386/F387 Page 78 of 119 CY96380 Series External Reset Timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin tRSTL RSTX Reset input time Value Min Typ Max 500 - - Unit Remarks ns tRSTL RSTX 0.2 VCC Document Number: 002-04582 Rev. *C 0.2 VCC Page 79 of 119 CY96380 Series Power On Reset Timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Power on rise time Power off time Symbol Pin tR tOFF Value Unit Min Typ Max Vcc 0.05 - 30 ms Vcc 1 - - ms Remarks tR 2.7V VCC 0.2 V 0.2 V 0.2 V tOFF If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. VCC 3V Document Number: 002-04582 Rev. *C Rising edge of 50 mV/ms maximum is allowed Page 80 of 119 CY96380 Series External Input Timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition INTn(_R) NMI(_R) Input pulse width tINH tINL Value Min Max 200 — Unit ns Used Pin input function External Interrupt NMI Pnn_m General Purpose IO TINn(_R) Reload Timer — TTGn(_R) ADTG(_R) 2*tCLKP1 + 200 (tCLKP1=1/fCLK P1) PPG Trigger input — ns AD Converter Trigger FRCKn(_R) Free Running Timer external clock INn(_R) Input Capture Note : Relocated Resource Inputs have same characteristics External Pin input VIH VIH tINH Document Number: 002-04582 Rev. *C VIL VIL tINL Page 81 of 119 CY96380 Series Slew Rate High Current Outputs (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Output rise/fall time Symbol Pin Condition tR30 tF30 I/O circuit type M Output driving strength set to “30 mA” Value Min Max 15 — Unit Remarks ns Note : Relocated Resource Inputs have same characteristics Slew rate output timing VH VH VL VL tR30 Document Number: 002-04582 Rev. *C VH = VOL30 + 0.9  (VOH30 - VOL30) VL = VOL30 + 0.1  (VOH30 - VOL30) tF3 Page 82 of 119 CY96380 Series External Bus Timing Note: The values given below are for an I/O driving strength IOdrive = 5 mA. If IOdrive is 2 mA, all the maximum output timing described in the different tables must then be increased by 10 ns. Basic Timing Parameter (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Condition Min Max 25 — tCYC/2-5 tCYC/2+5 tCLCH tCYC/2-5 tCYC/2+5 tCHCBH -20 20 -20 20 -20 20 tCLCBL -20 20 tCHLH -10 10 -10 10 -10 10 -10 10 -15 15 -15 15 -15 15 -15 15 -15 15 -15 15 -10 10 -10 10 -10 10 -10 10 tCYC ECLK ECLK → UBX/ LBX / CSn time ECLK → ALE time tCHCL tCHCBL tCLCBH tCHLL tCLLH ECLK CSn, UBX, LBX, ECLK ALE, ECLK — — — tCLLL ECLK →address valid time (non-multiplexed) tCHAV tCLAV tCHAV ECLK →address valid time (multiplexed) tCLAV tCLADV tCHADV A[23:0], ECLK EBM:NMS=1 A[23:16], ECLK EBM:NMS=0 AD[15:0], ECLK EBM:NMS=0 tCHRWH ECLK → RDX /WRX time Value tCHRWL tCLRWH tCLRWL Document Number: 002-04582 Rev. *C RDX, WRX, WRLX,WRHX, ECLK — Unit Remarks ns ns ns ns ns ns ns Page 83 of 119 CY96380 Series (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition Min Max 30 — tCYC/2-8 tCYC/2+8 tCLCH tCYC/2-8 tCYC/2+8 tCHCBH -25 25 -25 25 -25 25 tCLCBL -25 25 tCHLH -15 15 -15 15 -15 15 -15 15 -20 20 -20 20 -20 20 -20 20 -20 20 -20 20 -15 15 -15 15 -15 15 -15 15 tCYC ECLK ECLK → UBX/ LBX / CSn time ECLK → ALE time tCHCL tCHCBL tCLCBH tCHLL tCLLH ECLK CSn, UBX, LBX, ECLK ALE, ECLK — — — tCLLL ECLK →address valid time (non-multiplexed) tCHAV tCLAV tCHAV ECLK →address valid time (multiplexed) tCLAV tCLADV tCHADV A[23:0], ECLK EBM:NMS=1 A[23:16], ECLK EBM:NMS=0 AD[15:0], ECLK EBM:NMS=0 tCHRWH ECLK → RDX /WRX time Value tCHRWL tCLRWH tCLRWL Document Number: 002-04582 Rev. *C RDX, WRX, WRLX, WRHX, ECLK — Unit Remarks ns ns ns ns ns ns ns Page 84 of 119 CY96380 Series tCYC tCHCL ECLK tCLCH 0.8*Vcc 0.2*Vcc tCLAV tCHAV A[23:0] tCHCBL tCLCBH tCLCBL tCHCBH tCHRWL tCLRWH tCLRWL tCHRWH CSn LBX UBX RDX WRX (WRLX, WRHX) tCLLH tCHLL tCHLH tCLLL ALE tCHADV tCLADV AD[15:0] Address Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04582 Rev. *C Page 85 of 119 CY96380 Series Bus Timing (Read) Parameter (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Conditions Min Max tCYC/2  5 — tCYC  5 — EACL:STS=0 and EACL:ACE=1 3tCYC/2  5 — EACL:STS=0 and EACL:ACE=0 tCYC  15 — EACL:STS=1 and EACL:ACE=0 3tCYC/2  15 — EACL:STS=0 and EACL:ACE=1 2tCYC  15 — EACL:STS=1 and EACL:ACE=1 5tCYC/2  15 — EACL:STS=0 and EACL:ACE=0 tCYC/2  15 — EACL:STS=1 and EACL:ACE=0 tCYC  15 — EACL:STS=0 and EACL:ACE=1 3tCYC/2  15 — EACL:STS=1 and EACL:ACE=1 2tCYC  15 — EACL:STS=0 tCYC/2  15 — EACL:STS=1 -15 — EBM:NMS= 1 tCYC/2  15 — EACL:ACE=0 EBM:NMS=0 3tCYC/2  15 — EACL:ACE=1 EBM:NMS=0 5tCYC/2  15 — EACL:ACE=0 EBM:NMS=0 tCYC  15 — EACL:ACE=1 EBM:NMS=0 2tCYC  15 — EBM:NMS= 1 — 2tCYC  55 EACL:STS=0 and EACL:ACE=0 ALE pulse width (multiplexed) tLHLL tAVLL ALE ALE, A[23:16], Valid address  ALE  time (multiplexed) tADVLL ALE,AD[15:0] ALE   Address valid time (multiplexed) tLLAX ALE, AD[15:0] Valid address  RDX  time (non-multiplexed) tAVRL RDX, A[23:0] tAVRL RDX, A[23:16] Valid address  RDX  time (multiplexed) tADVRL Valid address  Valid data input (non-multiplexed) tAVDV Document Number: 002-04582 Rev. *C RDX, AD[15:0] A[23:0], AD[15:0] Value EACL:STS=1 Unit Remarks ns ns EBM:NMS =0 ns ns ns ns ns ns w/o cycle extension Page 86 of 119 CY96380 Series (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol tAVDV Pin A[23:16], AD[15:0] Valid address  Valid data input (multiplexed) tADVDV AD[15:0] Conditions Value Min Max EACL:ACE=0 EBM:NMS=0 — 3tCYC  55 EACL:ACE=1 EBM:NMS=0 — 4tCYC  55 EACL:ACE=0 EBM:NMS=0 — 5tCYC/2  55 EACL:ACE=1 EBM:NMS=0 — 7tCYC/2  55 Unit Remarks ns w/o cycle extension ns w/o cycle extension RDX pulse width tRLRH RDX — 3 tCYC/2  5 — ns w/o cycle extension RDX   Valid data input tRLDV RDX, AD[15:0] — — 3 tCYC/2  50 ns w/o cycle extension RDX   Data hold time tRHDX RDX, AD[15:0] — 0 — ns Address valid  Data hold time tAXDX A[23:0], AD[15:0] — 0 — ns EACL:STS=1 and EACL:ACE=1 3tCYC/2  10 — other ECL:STS, EACL:ACE setting tCYC/2  10 — tCYC  15 — tCYC/2  15 — tCYC/2  10 — EACL:STS=0 tCYC/2  10 — EACL:STS=1  10 — — tCYC  50 RDX   ALE  time Valid address  ECLK  time tRHLH RDX, ALE tAVCH A[23:0], ECLK tADVCH AD[15:0], ECLK RDX   ECLK  time tRLCH RDX, ECLK ALE   RDX  time tLLRL ALE, RDX ECLK  Valid data input tCHDV AD[15:0], ECLK Document Number: 002-04582 Rev. *C — — — ns ns ns ns ns Page 87 of 119 CY96380 Series (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions Min Max tCYC/2  8 — tCYC  8 — EACL:STS=0 and EACL:ACE=1 3tCYC/2  8 — EACL:STS=0 and EACL:ACE=0 tCYC  20 — EACL:STS=1 and EACL:ACE=0 3tCYC/2  20 — EACL:STS=0 and EACL:ACE=1 2tCYC  20 — EACL:STS=1 and EACL:ACE=1 5tCYC/2  20 — EACL:STS=0 and EACL:ACE=0 tCYC/2  20 — EACL:STS=1 and EACL:ACE=0 tCYC  20 — EACL:STS=0 and EACL:ACE=1 3tCYC/2  20 — EACL:STS=1 and EACL:ACE=1 2tCYC  20 — EACL:STS=0 tCYC/2  20 — EACL:STS=1 -20 — EBM:NMS= 1 tCYC/2  20 — EACL:ACE=0 EBM:NMS=0 3tCYC/2  20 — EACL:ACE=1 EBM:NMS=0 5tCYC/2  20 — EACL:ACE=0 EBM:NMS=0 tCYC  20 — EACL:ACE=1 EBM:NMS=0 2tCYC  20 — EBM:NMS= 1 — 2tCYC  60 EACL:STS=0 and EACL:ACE=0 ALE pulse width (multiplexed) tLHLL tAVLL ALE ALE, A[23:16], Valid address  ALE  time (multiplexed) tADVLL ALE, AD[15:0] ALE   Address valid time (multiplexed) tLLAX Valid address  RDX  time (non-multiplexed) tAVRL RDX, A[23:0] tAVRL ALE, AD[15:0] RDX, A[23:16] Valid address  RDX  time (multiplexed) tADVRL RDX, AD[15:0] Valid address  Valid data input (non-multiplexed) tAVDV Document Number: 002-04582 Rev. *C A[23:0], AD[15:0] Value EACL:STS=1 Unit Remarks ns ns EBM:NMS =0 ns ns ns ns ns ns w/o cycle extension Page 88 of 119 CY96380 Series (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol tAVDV Pin A[23:16], AD[15:0] Valid address  Valid data input (multiplexed) tADVDV AD[15:0] Conditions Value Min Max EACL:ACE=0 EBM:NMS=0 — 3tCYC  60 EACL:ACE=1 EBM:NMS=0 — 4tCYC  60 EACL:ACE=0 EBM:NMS=0 — 5tCYC/2  60 EACL:ACE=1 EBM:NMS=0 — 7tCYC/2  60 Unit Remarks ns w/o cycle extension ns w/o cycle extension RDX pulse width tRLRH RDX — 3tCYC/2  8 — ns w/o cycle extension RDX   Valid data input tRLDV RDX, AD[15:0] — — 3tCYC/2  55 ns w/o cycle extension RDX   Data hold time tRHDX RDX, AD[15:0] — 0 — ns — 0 — ns EACL:STS=1 and EACL:ACE=1 3tCYC/2  15 — other ECL:STS, EACL:ACE setting tCYC/2  15 — tCYC  20 — tCYC/2  20 — tCYC/2  15 — EACL:STS=0 tCYC/2  15 — EACL:STS=1  15 — — tCYC  55 Address valid  Data hold time tAXDX A[23:0] RDX   ALE  time Valid address  ECLK  time tRHLH RDX, ALE tAVCH A[23:0], ECLK tADVCH AD[15:0], ECLK RDX   ECLK  time tRLCH RDX, ECLK ALE   RDX  time tLLRL ECLK  Valid data input tCHDV AD[15:0], ECLK Document Number: 002-04582 Rev. *C ALE, RDX — — — ns ns ns ns ns Page 89 of 119 CY96380 Series tAVCH tRLCH tADVCH ECLK . tCHDV 0.8*Vcc tAVLL tLLAX tADVLL ALE tRHLH 0.2*VC tLHLL tAVRL tADVRL tRLRH RDX tLLRL A[23:0] tRLDV tAVDV tAXD tRHDX tADVDV AD[15:0] Address VIH VIL Read data VIH VIL Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04582 Rev. *C Page 90 of 119 CY96380 Series Bus Timing (Write) Parameter Valid address  WRX  time (non-multiplexed) (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Symbol tAVWL tAVWL Pin WRX, WRLX, WRHX, A[23:0] WRX, WRLX, WRHX, A[23:16] Valid address  WRX  time (multiplexed) tADVWL Condition Value Min Max EACL:STS=0 EBM:NMS=1 tCYC/2  15 — EACL:STS=1 EBM:NMS=1 tCYC  15 — EACL:ACE=0 EBM:NMS=0 3tCYC/2  15 — EACL:ACE=1 EBM:NMS=0 5tCYC/2  15 — EACL:ACE=0 EBM:NMS=0 tCYC  15 — WRX, WRLX, WRHX, AD[15:0] EACL:ACE=1 EBM:NMS=0 Unit Remarks ns ns ns 2tCYC  15 — WRX pulse width tWLWH WRX, WRXL, WRHX — tCYC  5 — ns w/o cycle extension Valid data output  WRX  time tDVWH WRX, WRLX, WRHX, AD[15:0] — tCYC  20 — ns w/o cycle extension WRX   Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] — tCYC/2  15 — ns WRX   Address valid time (non-multiplexed) EACL:STS=1 EBM:NMS=1 EACL:STS=0 EBM:NMS=1  15 — ns tWHAX WRX, WRLX, WRHX, A[23:0] tCYC/2  15 — ns WRX   Address valid time (multiplexed) tWHAX WRX, WRLX, WRHX, A[23:16] EBM:NMS=0 tCYC/2  15 — ns EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting 2tCYC  10 — tCYC  10 — — tCYC/2  10 — EACL:STS=0 EBM:NMS=1 — tCYC/2  15 EACL:STS=1 EBM:NMS=1 — tCYC  15 EACL:ACE=0 EBM:NMS=0 — 3tCYC/2  15 EACL:ACE=1 EBM:NMS=0 — 5tCYC/2  15 WRX   ALE  time (multiplexed) tWHLH WRX, WRLX, WRHX, ALE WRX   ECLK  time tWLCH WRX, WRLX, WRHX, ECLK tCSLWL WRX, WRLX, WRHX, CSn CSn  WRX time (non-multiplexed) CSn  WRX time (multiplexed) tCSLWL WRX, WRLX, WRHX, CSn Document Number: 002-04582 Rev. *C ns EBM:NMS=0 ns ns ns Page 91 of 119 CY96380 Series (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter WRX  CSn time (non-multiplexed) WRX  CSn time (multiplexed) Symbol Pin Condition Value Min Max Unit EACL:STS=1 EBM:NMS=1 EACL:STS=0 EBM:NMS=1  15 — ns tWHCSH WRX, WRLX, WRHX, CSn tCYC/2  15 — ns tWHCSH WRX, WRLX, WRHX, CSn EBM:NMS=0 tCYC/2  15 — ns Remarks (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Valid address  WRX  time (non-multiplexed) Symbol tAVWL tAVWL Pin WRX, WRLX, WRHX, A[23:0] WRX, WRLX, WRHX, A[23:16] Valid address  WRX  time (multiplexed) tADVWL WRX, WRLX, WRHX, AD[15:0] Condition Value Min Max EACL:STS=0 EBM:NMS=1 tCYC/2  20 — EACL:STS=1 EBM:NMS=1 tCYC  20 — EACL:ACE=0 EBM:NMS=0 3tCYC/2  20 — EACL:ACE=1 EBM:NMS=0 5tCYC/2  20 — EACL:ACE=0 EBM:NMS=0 tCYC  20 — EACL:ACE=1 EBM:NMS=0 2tCYC  20 — Unit Remarks ns ns ns WRX pulse width tWLWH WRX, WRXL, WRHX — tCYC  8 — ns w/o cycle extension Valid data output  WRX  time tDVWH WRX, WRLX, WRHX, AD[15:0] — tCYC  25 — ns w/o cycle extension WRX   Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] — tCYC/2  20 — ns WRX   Address valid time (non-multiplexed) EACL:STS=1 EBM:NMS=1 EACL:STS=0 EBM:NMS=1  20 — ns tWHAX WRX, WRLX, WRHX, A[23:0] tCYC/2  20 — ns WRX   Address valid time (multiplexed) tWHAX WRX, WRLX, WRHX, A[23:16] EBM:NMS=0 tCYC/2  20 — ns EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting 2tCYC  15 — tCYC  15 — — tCYC/2  15 — WRX   ALE  time (multiplexed) tWHLH WRX, WRLX, WRHX, ALE WRX   ECLK  time tWLCH WRX, WRLX, WRHX, ECLK Document Number: 002-04582 Rev. *C ns EBM:NMS=0 ns Page 92 of 119 CY96380 Series (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter CSn  WRX time (non-multiplexed) CSn  WRX time (multiplexed) WRX  CSn time (non-multiplexed) WRX  CSn time (multiplexed) Symbol tCSLWL tCSLWL Pin Value Condition WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn Min Max EACL:STS=0 EBM:NMS=1 — tCYC/2  20 EACL:STS=1 EBM:NMS=1 — tCYC  20 EACL:ACE=0 EBM:NMS=0 — 3tCYC/2  20 EACL:ACE=1 EBM:NMS=0 — 5tCYC/2  20 Unit Remarks ns ns EACL:STS=1 EBM:NMS=1 EACL:STS=0 EBM:NMS=1  20 — ns tWHCSH WRX, WRLX, WRHX, CSn tCYC/2  20 — ns tWHCSH WRX, WRLX, WRHX, CSn EBM:NMS=0 tCYC/2  20 — ns tWLCH 0.8*VC ECLK tWHLH ALE . tAVWL tADVWL WRX (WRLX, WRHX) tWLWH 0.2*VCC tCSLWL tWHCSH CSn tWHAX A[23:0] tDVWH AD[15:0] Address tWHDX Write data Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04582 Rev. *C Page 93 of 119 CY96380 Series Ready Input Timing Parameter (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin RDY setup time tRYHS RDY RDY hold time tRYHH RDY Test Condition Rated Value Units Min Max 35 — ns 0 — ns — Remarks (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin RDY setup time tRYHS RDY RDY hold time tRYHH RDY Test Condition Rated Value Units Min Max 45 — ns 0 — ns — Remarks Note : If the RDY setup time is insufficient, use the auto-ready function. ECLK 0.8*VC tRYHS RDY When WAIT is not used. RDY When WAIT is used. VIH tRYHH VIH VIL Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04582 Rev. *C Page 94 of 119 CY96380 Series Hold Timing (TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Pin floating  HAKX  time tXHAL HAKX HAKX  time  Pin valid time tHAHV HAKX Value Condition — Units Min Max tCYC  20 tCYC + 20 ns tCYC  20 tCYC + 20 ns Remarks (TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Pin floating  HAKX  time tXHAL HAKX HAKX  time  Pin valid time tHAHV HAKX Value Condition — Max tCYC  25 tCYC + 25 ns tCYC  25 tCYC + 25 ns Remarks 0.8*VCC HAKX 0.2*VCC tHAHV tXHAL Each pin Units Min 0.8*VCC High-Z 0.2*VCC Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04582 Rev. *C Page 95 of 119 CY96380 Series USART Timing WARNING: The values given below are for an I/O driving strength IOdrive = 5 mA. If IOdrive is 2 mA, all the maximum output timing described in the different tables must then be increased by 10 ns. (TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition VCC = AVCC= 4.5 V VCC = AVCC= 3.0 V to to 5.5 V 4.5 V Min Max Min Max Unit Serial clock cycle time tSCYCI SCKn 4 tCLKP1 — 4 tCLKP1 — ns SCK ↓ → SOT delay time tSLOVI SCKn, SOTn -20 20 -30 30 ns SOT → SCK ↑ delay time tOVSHI SCKn, SOTn N*tCLKP1 - 20 *1 — N*tCLKP1 30 *1 — ns Valid SIN → SCK ↑ tIVSHI SCKn, SINn tCLKP1 + 45 — tCLKP1 + 55 — ns SCK ↑ → Valid SIN hold time tSHIXI SCKn, SINn 0 — 0 — ns Serial clock “L” pulse width tSLSHE SCKn tCLKP1 + 10 — tCLKP1 + 10 — ns Serial clock “H” pulse width tSHSLE SCKn tCLKP1 + 10 — tCLKP1 + 10 — ns SCK ↓ → SOT delay time tSLOVE SCKn, SOTn — 2 tCLKP1 + 45 — 2 tCLKP1 + 55 ns Valid SIN → SCK ↑ tIVSHE SCKn, SINn tCLKP1/2 + 10 — tCLKP1/2 + 10 — ns SCK ↑ → Valid SIN hold time tSHIXE SCKn, SINn tCLKP1 + 10 — tCLKP1 + 10 — ns SCK fall time tFE SCKn — 20 — 20 ns SCK rise time tRE SCKn — 20 — 20 ns Internal Shift Clock Mode External Shift Clock Mode Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “CY96300 Super series Hardware Manual” • tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns *1: Parameter N depends on tSCYCI and can be calculated as follows: • if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 • if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N 4*tCLKP1 2 5*tCLKP1, 6*tCLKP1 3 7*tCLKP1, 8*tCLKP1 4 ... ... Document Number: 002-04582 Rev. *C Page 96 of 119 CY96380 Series tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC SCK for ESCR:SCES = 1 0.8*VCC 0.8*VCC 0.2*VCC tSLOVI tOVSHI 0.8*VCC SOT 0.2*VCC tIVSHI SIN tSHIXI VIH VIH VIL VIL Internal Shift Clock Mode tSLSHE SCK for ESCR:SCES = 0 VIH SCK for ESCR:SCES = 1 VIL VIL VIH VIH VIL tFE SOT tSHSLE tSLOVE VIH VIL VIL tRE 0.8*VCC 0.2*VCC tIVSHE SIN VIH tSHIXE VIH VIH VIL VIL External Shift Clock Mode Document Number: 002-04582 Rev. *C Page 97 of 119 CY96380 Series I2C Timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Condition Standard-mode Fast-mode*4 Unit Min Max Min Max fSCL 0 100 0 400 kHz tHDSTA 4.0 — 0.6 — s “L” width of the SCL clock tLOW 4.7 — 1.3 — s “H” width of the SCL clock tHIGH 4.0 — 0.6 — s 4.7 — 0.6 — s 0 3.45*2 0 0.9*3 s SCL clock frequency Hold time (repeated) START condition SDA↓→SCL↓ Set-up time for a repeated START condition SCL↑→SDA↓ tSUSTA Data hold time SCL↓→SDA↓↑ tHDDAT Data set-up time SDA↓↑→SCL↑ tSUDAT 250 — 100 — ns Set-up time for STOP condition SCL↑→SDA↑ tSUSTO 4.0 — 0.6 — s tBUS 4.7 — 1.3 — s Bus free time between a STOP and START condition R  1.7 k, C  50 pF*1 *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. *4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. SDA tSUDAT tLOW tBUS tHDSTA SCL tHDSTA tHDDAT Document Number: 002-04582 Rev. *C tHIGH tSUSTA tSUSTO Page 98 of 119 CY96380 Series 15.5 Analog Digital Converter (TA = -40 °C to +125 °C, 3.0 V AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Resolution - Total error Value Unit Remarks Min Typ Max - - - 10 bit - - -3 - +3 LSB Nonlinearity error - - -2.5 - +2.5 LSB Differential nonlinearity error - - -1.9 - +1.9 LSB VOT ANn AVRL1.5 LSB AVRL+ 0.5 LSB AVRL+ 2.5 LSB V VFST ANn AVRH3.5 LSB AVRH1.5 LSB AVRH+ 0.5 LSB V Compare time - - 1.0 - 16,500 s 4.5 V AVCC  5.5 V 2.0 - - s 3.0 V AVCC  4.5 V Sampling time - - 0.5 - - s 4.5 V AVCC  5.5 V 1.2 - - s 3.0 V AVCC  4.5 V IAIN ANn -3 - +3 A AVSS, AVRL < VI < AVCC, AVRH -1 - +1 A TA = 25°C, AVSS, AVRL < VI < AVCC, AVRH -3 - +3 A TA = 125°C AVSS, AVRL < VI < AVCC, AVRH Zero reading voltage Full scale reading voltage Analog port input current Analog input leakage current (during conversion) Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels IAIN ANn VAIN ANn AVRL - AVRH V AVRH AVRH/AVRH2 0.75 AVcc - AVcc V AVRL AVRL AVSS - 0.25 AVCC V IA AVcc - 2.5 5 mA A/D Converter active IAH AVcc - - 5 A A/D Converter not operated IR AVRH/AVRL - 0.7 1 mA A/D Converter active IRH AVRH/AVRL - - 5 A A/D Converter not operated - ANn - - 4 LSB Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04582 Rev. *C Page 99 of 119 CY96380 Series Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error 3FF 3FE Actual conversion characteristics 1.5 LSB Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (Actually-measured value) 003 Actual conversion characteristics Ideal characteristics 002 001 0.5 LSB AVRL AVRH Analog input VNT  {1 LSB × (N  1) 1 LSB AVRH  AVRL (Ideal value) [V] 1024 Total error of digital output “N”  1 LSB   0.5 LSB} [LSB] N: A/D converter digital output value  AVRL  0.5 LSB [V] VFST (Ideal value)  AVRH  1.5 LSB [V] VOT (Ideal value) VNT : A voltage at which digital output transitions from (N  1) to N. Document Number: 002-04582 Rev. *C Page 100 of 119 CY96380 Series Nonlinearity error Differential nonlinearity error Ideal characteristics 3FF Digital output 3FD Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) 004 003 Actual conversion characteristics Digital output 3FE Actual conversion characteristics N V (N + 1) T (actual measurement value) VNT (actual measurement value) N−1 002 Ideal characteristics Actual conversion characteristics N−2 001 VOT (actual measurement value) AVRL AVRH AVRL AVRH Analog input Analog input Nonlinearity error of digital output N  Differential nonlinearity error of digital output N  VNT  {1 LSB × (N  1) 1 LSB V (N+1) T  VNT 1 LSB  1 LSB VFST  VOT 1022  VOT} [LSB] 1 LSB [LSB] [V] N : A/D converter digital output value VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” Notes on A/D Converter Section • ² About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit): If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. analog input circuit model: R Comparator Analog input C Sampling switch Reference value: • C = 8.5 pF (Max) Document Number: 002-04582 Rev. *C Page 101 of 119 CY96380 Series To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7where= RC. If the external input resistance (Rext) connected to the analog input is included, the sampling time is expressed as follows: Tsamp [min] = 7 × (Rext + 2.6 k) × C for 4.5 AVcc 5.5 Tsamp [min] = 7 × (Rext + 12.1 k) × C for 3.0 AVcc 4.5 If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. • ² About the error The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04582 Rev. *C Page 102 of 119 CY96380 Series 15.6 Alarm Comparator (TA = -40 °C to +125 °C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin IA5ALMF Power supply current IA5ALMS AVCC IA5ALMH Value Unit Remarks 45 A Alarm comparator enabled in fast mode (one channel) 7 13 A Alarm comparator enabled in slow mode (one channel) - - 5 A Alarm comparator disabled -1 - +1 A TA = 25 °C -3 - +3 A TA = 125 °C Min Typ Max - 25 - ALARM pin input current IALIN ALARM pin input voltage range VALIN 0 - AVCC V External low threshold high->low transition VEVTL(H->L) 0.36 * AVCC -0.25 0.36 * AVCC -0.1 - V External low threshold low->high transition VEVTL(L->H) - 0.36 * AVCC +0.1 0.36 * AVCC +0.25 V External high threshold high->low transition VEVTH(H->L) 0.78 * AVCC -0.25 0.78 * AVCC -0.1 - V External high threshold low->high transition VEVTH(L->H) 0.78 * AVCC +0.1 0.78 * AVCC +0.25 V Internal low threshold high->low transition VIVTL(H->L) 0.9 1.1 - V Internal low threshold low->high transition VIVTL(L->H) - 1.3 1.55 V Internal high threshold high->low transition VIVTH(H->L) 2.2 2.4 - V Internal high threshold low->high transition VIVTH(L->H) - 2.6 2.85 V VHYS 50 - 300 mV tCOMPF - 0.1 1 s CMD = 1 (fast) tCOMPS - 1 10 s CMD = 0 (slow) Power-up stabilization time after enabling alarm comparator tPD - 1 5 ms Slow/Fast mode transition time tCMD - 100 500 s Threshold levels specified above are not guaranteed within this time Switching hysteresis Comparison time ALARM0, ALARM1 INTREF = 0 INTREF = 1 Document Number: 002-04582 Rev. *C Page 103 of 119 CY96380 Series Comparator Output H L VxVTx(H->L) VHYS VALIN VxVTx(L->H) Document Number: 002-04582 Rev. *C Page 104 of 119 CY96380 Series 15.7 Low Voltage Detector Characteristics (TA = -40 °C to +125 °C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Symbol Value Unit Remarks 75 s After power-up or change of detection level 2.7 2.9 V CILCR:LVL[3:0]=”0000” VDL1 2.9 3.1 V CILCR:LVL[3:0]=”0001” Level 2 VDL2 3.1 3.3 V CILCR:LVL[3:0]=”0010” Level 3 VDL3 3.5 3.75 V CILCR:LVL[3:0]=”0011” Level 4 VDL4 3.6 3.85 V CILCR:LVL[3:0]=”0100” Level 5 VDL5 3.7 3.95 V CILCR:LVL[3:0]=”0101” Level 6 VDL6 3.8 4.05 V CILCR:LVL[3:0]=”0110” Level 7 VDL7 3.9 4.15 V CILCR:LVL[3:0]=”0111” Level 8 VDL8 4.0 4.25 V CILCR:LVL[3:0]=”1000” Level 9 VDL9 4.1 4.35 V CILCR:LVL[3:0]=”1001” Level 10 VDL10 not used Level 11 VDL11 not used Level 12 VDL12 not used Level 13 VDL13 not used Level 14 VDL14 not used Level 15 VDL15 not used Min Max TLVDSTAB - Level 0 VDL0 Level 1 Stabilization time CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register. Levels 10 to 15 are not used in this device. dV V For correct detection, the slope of the voltage level must satisfy dt ≤ 0.004 μs . Faster variations are regarded as noise and may not be detected. The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7 V. The electrical characteristics however are only valid in the specified range (usually down to 3.0 V). Document Number: 002-04582 Rev. *C Page 105 of 119 CY96380 Series Low Voltage Detector Operation In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC VDLx, Max VDLx, Min dV dt Time [s] Normal Operation Document Number: 002-04582 Rev. *C Low Voltage Reset Assertion Power Reset Extension Time Page 106 of 119 CY96380 Series 15.8 FLASH Memory Program/erase Characteristics (TA = -40°C to 105°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Value Unit Remarks 3.6 s Without erasure pre-programming time n*0.9 n*3.6 s Without erasure pre-programming time (n is the number of Flash sector of the device) - 23 370 us Without overhead time for submitting write command 10 000 - - cycle 20 - - year Min Typ Max Sector erase time - 0.9 Chip erase time - Word (16-bit width) programming time Program/Erase cycle Flash data retention time *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85°C) Document Number: 002-04582 Rev. *C Page 107 of 119 CY96380 Series 16. Example Characteristics The diagrams below show the characteristics of one measured sample with typical process parameters. Run Mode 100.00 PLL clock (56 MHz) 10.00 Icc [mA] Main osc. (4 MHz) RC clock (2 MHz) 1.00 RC clock (100 kHz) 0.10 Sub osc.(32 kHz) 0.01 -50.00 0.00 50.00 100.00 150.00 100.00 150.00 Ta [ºC] Sleep mode 100.00 PLL clock (56 MHz) Icc [mA] 10.00 Main osc. (4 MHz) 1.00 RC clock (2 MHz) RC clock (100 kHz) 0.10 Sub osc.(32 kHz) 0.01 -50.00 0.00 50.00 Ta [ºC] Document Number: 002-04582 Rev. *C Page 108 of 119 CY96380 Series Timer mode 10.00 PLL clock (56 MHz) Icc [mA] 1.00 Main osc. (4 MHz) RC clock (2 MHz) RC clock (100 kHz) 0.10 Sub osc. (32 kHz) 0.01 -50.00 0.00 50.00 100.00 150.00 100.00 150.00 Ta [ºC] Stop mode 1.00 Icc [mA] 0.10 0.01 0.00 -50.00 0.00 50.00 Ta [ºC] Document Number: 002-04582 Rev. *C Page 109 of 119 CY96380 Series Used Settings Mode Run mode Sleep mode Selected Source Clock Clock/Regulator Settings PLL CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz CLKP2 = 28 MHz Regulator in High Power Mode Core Voltage = 1.9 V Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz Regulator in High Power Mode Core Voltage = 1.8 V RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz Regulator in High Power Mode Core Voltage = 1.8 V RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz Regulator in High Power Mode Core Voltage = 1.8 V Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz Regulator in Low Power Mode A Core Voltage = 1.8 V PLL CLKS1 = CLKS2 = CLKP1 = 56 MHz CLKP2 = 28 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.9 V Main osc. CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V RC clock fast CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V RC clock slow CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V Sub osc. CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz (CLKB is stopped in this mode) Regulator in Low Power Mode A Core Voltage = 1.8 V Document Number: 002-04582 Rev. *C Page 110 of 119 CY96380 Series Used Settings Mode Timer mode Stop mode Selected Source Clock Clock/Regulator Settings PLL CLKMC = 4 MHz, CLKPLL = 56 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.9 V Main osc. CLKMC = 4 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock fast CLKRC = 2 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock slow CLKRC = 100 kHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V Sub osc. CLKSC = 100 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode A, Core Voltage = 1.8 V stopped (All clocks are stopped in this mode) Regulator in Low Power Mode B, Core Voltage = 1.8 V Document Number: 002-04582 Rev. *C Page 111 of 119 CY96380 Series 17. Package Dimension CY96(F)38x LQFP 120P Package Type Package Code LQFP 120 LQM120 002-16172 ** Document Number: 002-04582 Rev. *C Page 112 of 119 CY96380 Series 18. Ordering Information Part Number Flash/ROM Subclock CY96384RSBPMC-GSE2 No CY96384RWBPMC-GSE2 Yes CY96384RSCPMC-GSE2 ROM (128 KB) CY96384RWCPMC-GSE2 CY96385RSCPMC-GSE2 Yes ROM (160 KB) CY96F385RSAPMC-GS-UJE2 CY96F385RWAPMC-GS-UJE2 No No Flash A (160 KB) Yes No CY96F386RSBPMC-GS-UJE1 No CY96F386RWBPMC-GS-UJE2 Flash A (288 KB) No Yes CY96F386RSCPMC-GS-UJE2 No CY96F387RSBPMC-GS-UJE2 No CY96F387RWBPMC-G-UJE2 Package No 120-pin Plastic LQFP (LQM120) No 120-pin Plastic LQFP (LQM120) No 120-pin Plastic LQFP (LQM120) No 120-pin Plastic LQFP (LQM120) No 120-pin Plastic LQFP (LQM120) No 120-pin Plastic LQFP (LQM120) No CY96F385RSBPMC-GS-UJE2 CY96F386RSBPMC-GS-UJE2 Persistent Low Voltage Reset Flash A (416 KB) CY96F387RSCPMC-GS-UJE2 Yes No CY96F388HWBPMC-GS-UJE2 Flash A (544 KB) Flash B (32 KB) Yes No 120-pin Plastic LQFP (LQM120) CY96F389RSBPMC-GS-UJE2 Flash A (544 KB) Flash B (288 KB) No No 120-pin Plastic LQFP (LQM120) This datasheet is also valid for the following outdated devices: CY96F386RSA, CY96F386RWA, CY96F387RSA, CY96F387RWA Document Number: 002-04582 Rev. *C Page 113 of 119 CY96380 Series 19. Major Changes Page Section Change Result Rev *B - Marketing Part Numbers changed from an MB prefix to a CY prefix. 1 - Deleted the following comment. Note: MB96384/385/F385/F388/F389 devices are under development and specification is preliminary. These products under development may change its specification without notice. 6 1. Product Lineup Deleted the following comment. *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. 8 112 113 3. Pin Assignment 17. Package Dimension 18. Ordering Information Package description modified to JEDEC description. (before) FPT-120P-M21 (after) LQM120 113 18. Ordering Information Deleted the following comment. *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. Deleted the following parts number. - MB96384YSBPMC-GSE2 - MB96384YWBPMC-GSE2 - MB96385YSBPMC-GSE2 - MB96385RSBPMC-GSE2 - MB96385YWBPMC-GSE2 - MB96385RWBPMC-GSE2 - MB96F385YSAPMC-GSE2 - MB96F385YWAPMC-GSE2 - MB96F386YSBPMC-GSE2 - MB96F386YWBPMC-GSE2 - MB96F387YSBPMC-GSE2 - MB96F387YWBPMC-GSE2 - MB96F388TSAPMC-GSE2 - MB96F388HSAPMC-GSE2 - MB96F388TWAPMC-GSE2 - MB96F388HWAPMC-GSE2 - MB96F389YSAPMC-GSE2 - MB96F389RSAPMC-GSE2 - MB96F389YWAPMC-GSE2 - MB96F389RWAPMC-GSE2 - MB96V300BRB-ES (for evaluation) Document Number: 002-04582 Rev. *C Page 114 of 119 CY96380 Series Page 113 Section 18. Ordering Information Change Result Revised the following parts number. (before) - MB96384RSBPMC-GSE2 - MB96384RWBPMC-GSE2 - MB96F385RSAPMC-GSE2 - MB96F385RWAPMC-GSE2 - MB96F386RSBPMC-GSE2 - MB96F386RWBPMC-GSE2 - MB96F387RSBPMC-GSE2 - MB96F387RWBPMC-GSE2 (after) - CY96384RSBPMC-GSE2 - CY96384RWBPMC-GSE2 - CY96F385RSAPMC-GS-UJE2 - CY96F385RWAPMC-GS-UJE2 - CY96F386RSBPMC-GS-UJE2 - CY96F386RWBPMC-GS-UJE2 - CY96F387RSBPMC-GS-UJE2 - CY96F387RWBPMC-G-UJE2 Added the following parts number. - CY96384RSCPMC-GSE2 - CY96384RWCPMC-GSE2 - CY96385RSCPMC-GSE2 - CY96F385RSBPMC-GS-UJE2 - CY96F386RSBPMC-GS-UJE1 - CY96F386RSCPMC-GS-UJE1 - CY96F386RSCPMC-GS-UJE2 - CY96F387RSAPMC-GS-UJE2 - CY96F387RSCPMC-GS-UJE2 - CY96F388HSBPMC-GS-UJE1 - CY96F389RSBPMC-GS-UJE2 Changed and deleted the parts number in Note. (before) MB96F386YSA, MB96F386RSA, MB96F386YWA, MB96F386RWA, MB96F387YSA, MB96F387RSA, MB96F387YWA, MB96F387RWA (after) CY96F386RSA, CY96F386RWA, CY96F387RSA, CY96F387RWA Document Number: 002-04582 Rev. *C Page 115 of 119 CY96380 Series 20. Revision History Spansion Publication Number: DS07-13803-2E Revision Date Modification Prelim 1 2007-05-2 Creation Prelim 2 2007-05-24 Electrical characteristics and memory description updates Prelim 3 2007-08-09 Typo errors corrections, Flash memory programming interface update Prelim 4 2007-08-31 Update of DC characteristics. new MB96F388 and MB96F389 added. LVD chapter added as well as an example characteristics chapter Prelim 5 2007-09-06 Updates of the DC characteristics, interrupt vector table update, update of the LVD characteristics 2007-11-14 Memory map for external bus modified. Modifications of the drawing of the pin circuits. Electrical characteristics updates. Rephrasing and typos corrections. Add Slew rate high current outputs chapter. Modification of the block diagram. Memory map modified for Flash. RAM memory map added. Pin circuit type corrected. Type L IO is now included. 2007-12-12 Memory IO map modified New Flash/ROM configuration presentation Ordering information: MB96300B used as reference. Block diagram modified to included relocated pins. Main Flash becomes Flash memory A and Satellite flash becomes Flash memory B Prelim 6 Prelim 7 • • • • • • • • Prelim 8 2008-02-04 • • • • • • • • • • Devices under development added: MB96384/385/F385/F388/F389 Block diagram corrected (existing resource pins) Pin assignment: TTG8 -> TTG7 Pin function table corrected I/O circuit type diagrams corrected Memory map cleaned up "Flash sector configuration" replaced by corrected "User ROM Memory map for Flash devices", “ROM configuration” replaced by “User ROM Memory map for Mask ROM devices” IO map table regenerated: - Port register: Naming style corrected - Memory control registers renamed (Main/Sat -> A/B) - addresses after 000BFFh removed Absolute maximum ratings: Pd and Ta specified more precisely Run and Sleep mode currents: more conditions added (1WS settings) Run mode current spec in 48/24MHz mode corrected Maximum CLKP2 frequency for MB96F386/F387 corrected High current port input capacitance added External bus timings: missing conditions added and readability improved Alarm comparator spec updated (transition voltages defined) MB96V300A removed Ordering information updated Typos and formatting corrected Document Number: 002-04582 Rev. *C Page 116 of 119 CY96380 Series Revision 9 Date 2009-01-09 Modification • Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes and official notes and disclaimer added) • Numbering of Electrical Characteristics subchapters automated • Note about devices under development modified • I/O map: Note added about reserved addresses • Serial programming interface: Note about handshaking pins improved • ICCPLL for CLKS1/2=80MHz, CLKB=40MHz (F388/F389) increased by 5mA • ICCSPLL for CLKS1/2=80MHz, CLKB=40MHz (F388/F389) increased by 0.8mA (typ) and 1.3mA (max) • Updated ordering information: MB96384/385**A -> MB96384/385**B • Package code of MB96V300 corrected in ordering information • Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm, Max 50kOhm -> 65kOhm • Run and Sleep mode currents of ROM devices (MB96384/385) reduced • Added voltage condition to pull-up resistance and LCD divide resistance spec • Lineup: Term “Data Flash” replaced by “independent 32KB Flash” • Ordering information: column “Independent 32KB Data Flash” replaced by new column “Flash/ROM”, column “Remarks” removed • Official package dimension drawing with additional notes added • Empty pages removed • MB96384/385 and MB96F385/F388/F389 separated in DC spec and currents of these devices adjusted according to first evaluation results • Alarm comparator: Power supply current max values increased, comparison time reduced, mode transition time and power-up stabilization time newly added • Handling devices: Notes added about Serial communication and about using ceramic resonators. • Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor • AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz • VOL3 spec improved: spec valid for 3mA load for full Vcc range • C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted • “Preliminary” watermark removed NOTE: Please see “Document History” about later revised information. Document Number: 002-04582 Rev. *C Page 117 of 119 CY96380 Series Document History Document Title: CY96380 Series F2MC-16FX 16-bit Proprietary Microcontroller Document Number: 002-04582 Revision ECN **  05/02/2007 Migrated to Cypress and assigned document number 002-04582. No change to document contents or format. *A 5243006 04/28/2016 Updated to Cypress template 03/12/2018 Revised the following items: Marketing Part Numbers changed from an MB prefix to a CY prefix. 3.Pin Assignments 17.Package Dimension 18.Ordering Information Added 19. Major Changes For details, please see 19.Major Changes 01/22/2020 Added the following part number on 18. Ordering Information. CY96F388HWBPMC-GS-UJE2 Deleted the following parts number on 18. Ordering Information. CY96F386RSCPMC-GS-UJE1 CY96F387RSAPMC-GS-UJE2 CY96F388HSBPMC-GS-UJE1 *B *C 6094799 6777565 Submission Date Document Number: 002-04582 Rev. *C Description of Change Page 118 of 119 CY96380 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing Cypress Developer Community Community | Code Examples | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2009-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. 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Document Number: 002-04582 Rev. *C Revised January 22, 2020 Page 119 of 119