CYWUSB6935-48LFXI

CYWUSB6935 WirelessUSB LR™ 2.4-GHz DSSS Radio SoC 1.0 Features 2.0 Functional Description • 2.4-GHz radio transceiver • Operates in the unlicensed Industrial, Scientific, and Medical (ISM) band (2.4 GHz–2.483 GHz) • –95-dBm receive sensitivity • Up to 0dBm output power • Range of up to 50 meters or more • Data throughput of up to 62.5 kbits/sec • Highly integrated low cost, minimal number of external components required • Dual DSSS reconfigurable baseband correlators • SPI microcontroller interface (up to 2-MHz data rate) • 13-MHz input clock operation • Low standby current < 1 µA • Integrated 30-bit Manufacturing ID • Operating voltage from 2.7V to 3.6V • Operating temperature from –40° to 85°C • Offered in a small footprint 48 QFN The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct Sequence Spread Spectrum (DSSS) Gaussian Frequency Shift Keying (GFSK) baseband modem radio that connects directly to a microcontroller via a simple serial peripheral interface. The CYWUSB6935 is offered in an industrial temperature range 48-pin QFN and a commercial temperature range 48pin QFN. 3.0 Applications • Building/Home Automation — Climate Control — Lighting Control — Smart Appliances — On-Site Paging Systems — Alarm and Security • Industrial Control — Inventory Management — Factory Automation — Data Acquisition • Automatic Meter Reading (AMR) • Transportation — Diagnostics — Remote Keyless Entry • Consumer / PC — Locator Alarms — Presenter Tools — Remote Controls — Toys DIOV A L DIO SERDES A DSSS Baseband A GFSK Modulator RFOUT IRQ SS SCK MISO MOSI Digital SERDES B DSSS Baseband B GFSK Demodulator RFIN RESET PD Synthesizer Figure 3-1. CYWUSB6935 Simplified Block Diagram Cypress Semiconductor Corporation Document #: 38-16008 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 17, 2005 X13IN X13 X13OUT CYWUSB6935 3.1 Applications Support 4.2 GFSK Modem The CYWUSB6935 is supported by both the CY3632 WirelessUSB Development Kit and the CY3635 WirelessUSB N:1 Development Kit. The CY3635 development kit provides all of the materials and documents needed to cut the cord on multipoint to point and point-to-point low bandwidth, high node density applications including four small form-factor sensor boards and a hub board that connects to WirelessUSB LR RF module boards, a software application that graphically demonstrates the multipoint to point protocol, comprehensive WirelessUSB protocol code examples and all of the associated schematics, gerber files and bill of materials. The WirelessUSB N:1 Development Kit is also supported by the WirelessUSB Listener Tool. The transmitter uses a DSP-based vector modulator to convert the 1-MHz chips to an accurate GFSK carrier. The receiver uses a fully integrated Frequency Modulator (FM) detector with automatic data slicer to demodulate the GFSK signal. 4.3 Dual DSSS Baseband Data is converted to DSSS chips by a digital spreader. Despreading is performed by an oversampled correlator. The DSSS baseband cancels spurious noise and assembles properly correlated data bytes. The DSSS baseband has three operating modes: 64-chips/bit Single Channel, 32-chips/bit Single Channel, and 32-chips/bit Single Channel Dual Data Rate (DDR). 4.3.1 64 Chips/Bit Single Channel 4.0 Functional Overview The CYWUSB6935 provides a complete SPI-to-antenna radio modem. The CYWUSB6935 is designed to implement wireless devices operating in the worldwide 2.4-GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz–2.4835 GHz). It is intended for systems compliant with world-wide regulations covered by ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries); FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB STD-T66 (Japan). The CYWUSB6935 contains a 2.4-GHz radio transceiver, a GFSK modem, and a dual DSSS reconfigurable baseband. The radio and baseband are both code- and frequency-agile. Forty-nine spreading codes selected for optimal performance (Gold codes) are supported across 78 1-MHz channels yielding a theoretical spectral capacity of 3822 channels. The CYWUSB6935 supports a range of up to 50 meters or more. The baseband supports a single data stream operating at 15.625 kbits/sec. The advantage of selecting this mode is its ability to tolerate a noisy environment. This is because the 15.625 kbits/sec data stream utilizes the longest PN Code resulting in the highest probability for recovering packets over the air. This mode can also be selected for systems requiring data transmissions over longer ranges. 4.3.2 32 Chips/Bit Single Channel The baseband supports a single data stream operating at 31.25 kbits/sec. 4.3.3 32 Chips/Bit Single Channel Dual Data Rate (DDR) 4.1 2.4-GHz Radio The baseband spreads bits in pairs and supports a single data stream operating at 62.5 kbits/sec. The receiver and transmitter are a single-conversion, lowIntermediate Frequency (low-IF) architecture with fully integrated IF channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides an output power control range of 30 dB in seven steps. Table 4-1. Internal PA Output Power Step Table PA Setting 7 6 5 4 3 2 1 0 Typical Output Power (dBm) 0 –2.4 –5.6 –9.7 –16.4 –20.8 –24.8 –29.0 4.4 Serializer/Deserializer (SERDES) CYWUSB6935 provides a data Serializer/Deserializer (SERDES), which provides byte-level framing of transmit and receive data. Bytes for transmission are loaded into the SERDES and receive bytes are read from the SERDES via the SPI interface. The SERDES provides double buffering of transmit and receive data. While one byte is being transmitted by the radio the next byte can be written to the SERDES data register insuring there are no breaks in transmitted data. After a receive byte has been received it is loaded into the SERDES data register and can be read at any time until the next byte is received, at which time the old contents of the SERDES data register will be overwritten. 4.5 Application Interfaces CYWUSB6935 has a fully synchronous SPI slave interface for connectivity to the application MCU. Configuration and byteoriented data transfer can be performed over this interface. An interrupt is provided to trigger real time events. An optional SERDES Bypass mode (DIO) is provided for applications that require a synchronous serial bit-oriented data path. This interface is for data only. Both the receiver and transmitter integrated Voltage Controlled Oscillator (VCO) and synthesizer have the agility to cover the complete 2.4-GHz GFSK radio transmitter ISM band. The synthesizer provides the frequency-hopping local oscillator for the transmitter and receiver. The VCO loop filter is also integrated on-chip. Document #: 38-16008 Rev. *C Page 2 of 33 CYWUSB6935 4.6 Clocking and Power Management 5.0 5.1 Application Interfaces SPI Interface A 13-MHz crystal is directly connected to X13IN and X13 without the need for external capacitors. The CYWUSB6935 has a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. The Radio Frequency (RF) circuitry has on-chip decoupling capacitors. The CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The CYWUSB6935 can be shutdown to a fully static state using the PD pin. Below are the requirements for the crystal to be directly connected to X13IN and X13: • Nominal Frequency: 13 MHz • Operating Mode: Fundamental Mode • Resonance Mode: Parallel Resonant • Frequency Stability: ± 30 ppm • Series Resistance: ≤ 100 ohms • Load Capacitance: 10 pF • Drive Level: 10 µW–100 µW The CYWUSB6935 has a four-wire SPI communication interface between an application MCU and one or more slave devices. The SPI interface supports single-byte and multi-byte serial transfers. The four-wire SPI communications interface consists of Master Out-Slave In (MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS). The SPI receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active-low Slave Select (SS) pin must be asserted to initiate a SPI transfer. The application MCU can initiate a SPI data transfer via a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes as shown in Figure 5-1 through Figure 5-4. The SS signal should not be deasserted between bytes. The SPI communications interface is as follows: • Command Direction (bit 7) = “0” Enables SPI read transaction. A “1” enables SPI write transactions. • Command Increment (bit 6) = “1” Enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed. • Six bits of address. • Eight bits of data. The SPI communications interface has a burst mechanism, where the command byte can be followed by as many data bytes as desired. A burst transaction is terminated by deasserting the slave select (SS = 1). For burst read transactions, the application MCU must abide by the timing shown in Figure 12-2. The SPI communications interface single read and burst read sequences are shown in Figure 5-2 and Figure 5-3, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 5-4 and Figure 5-5, respectively. 4.7 Receive Signal Strength Indicator (RSSI) The RSSI register (Reg 0x22) returns the relative signal strength of the ON-channel signal power and can be used to: 1. Determine the connection quality 2. Determine the value of the noise floor 3. Check for a quiet channel before transmitting. The internal RSSI voltage is sampled through a 5-bit analogto-digital converter (ADC). A state machine controls the conversion process. Under normal conditions, the RSSI state machine initiates a conversion when an ON-channel carrier is detected and remains above the noise floor for over 50 µs. The conversion produces a 5-bit value in the RSSI register (Reg 0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22, bit 5). The state machine then remains in HALT mode and does not reset for a new conversion until the receive mode is toggled off and on. Once a connection has been established, the RSSI register can be read to determine the relative connection quality of the channel. A RSSI register value lower than 10 indicates that the received signal strength is low, a value greater than 28 indicates a strong signal level. To check for a quiet channel before transmitting, first set up receive mode properly and read the RSSI register (Reg 0x22). If the valid bit is zero, then force the Carrier Detect register (Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait greater than 50 µs and read the RSSI register again. Next, clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn the receiver OFF. Measuring the noise floor of a quiet channel is inherently a 'noisy' process so, for best results, this procedure should be repeated several times (~20) to compute an average noise floor level. A RSSI register value of 0-10 indicates a channel that is relatively quiet. A RSSI register value greater than 10 indicates the channel is probably being used. A RSSI register value greater than 28 indicates the presence of a strong signal. Document #: 38-16008 Rev. *C Page 3 of 33 CYWUSB6935 Byte 1 Bit # Bit Name 7 DIR 6 INC [5:0] Address Byte 1+N [7:0] Data Figure 5-1. SPI Transaction Format SCK SS cm d MOSI M IS O D IR addr A5 A4 A3 A2 A1 A0 0 IN C 0 d a ta t o m c u D7 D6 D5 D4 D3 D2 D1 D0 Figure 5-2. SPI Single Read Sequence SCK SS cm d MOSI M IS O D IR addr A5 A4 A3 A2 A1 A0 0 IN C 1 d a ta to m c u D7 D6 D5 D4 D3 D2 1 D1 D0 D7 d a ta to m c u D6 D5 D4 D3 D2 1+N D1 D0 Figure 5-3. SPI Burst Read Sequence SCK SS cm d M O SI M ISO DIR addr A5 A4 A3 A2 A1 A0 D7 data from m cu D6 D5 D4 D3 D2 D1 D0 1 INC 0 Figure 5-4. SPI Single Write Sequence SCK SS cm d MOSI M IS O D IR a dd r A5 A4 A3 A2 A1 A0 D7 d ata fro m m cu D6 D5 D4 D3 D2 1 D1 D0 D7 da ta from m cu D6 D5 D4 D3 D2 1+N D1 D0 1 IN C 1 Figure 5-5. SPI Burst Write Sequence Document #: 38-16008 Rev. *C Page 4 of 33 CYWUSB6935 5.2 DIO Interface 5.3.1 Wake Interrupt The DIO communications interface is an optional SERDES bypass data-only transfer interface. In receive mode, DIO and DIOVAL are valid after the falling edge of IRQ, which clocks the data as shown in Figure 5-6. In transmit mode, DIO and DIOVAL are sampled on the falling edge of the IRQ, which clocks the data as shown in Figure 5-7. The application MCU samples the DIO and DIOVAL on the rising edge of IRQ. When the PD pin is low, the oscillator is stopped. After PD is deasserted, the oscillator takes time to start, and until it has done so, it is not safe to use the SPI interface. The wake interrupt indicates that the oscillator has started, and that the device is ready to receive SPI transfers. The wake interrupt is enabled by setting bit 0 of the Wake Enable register (Reg 0x1C, bit 0=1). Whether or not a wake interrupt is pending is indicated by the state of bit 0 of the Wake Status register (Reg 0x1D, bit 0). Reading the Wake Status register (Reg 0x1D) clears the interrupt. 5.3.2 Transmit Interrupts 5.3 Interrupts The CYWUSB6935 features three sets of interrupts: transmit, received, and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. Interrupts are enabled and the status read through 6 registers: Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status (Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake Status (Reg 0x1D). If more than 1 interrupt is enabled at any time, it is necessary to read the relevant interrupt status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate interrupt status register. It is therefore possible to use the devices without making use of the IRQ pin at all. Firmware can poll the interrupt status register(s) to wait for an event, rather than using the IRQ pin. The polarity of all interrupts can be set by writing to the Configuration register (Reg 0x05), and it is possible to configure the IRQ pin to be open drain (if active low) or open source (if active high). Four interrupts are provided to flag the occurrence of transmit events. The interrupts are enabled by writing to the Transmit Interrupt Enable register (Reg 0x0D), and their status may be determined by reading the Transmit Interrupt Status register (Reg 0x0E). If more than 1 interrupt is enabled, it is necessary to read the Transmit Interrupt Status register (Reg 0x0E) to determine which event caused the IRQ pin to assert. The function and operation of these interrupts are described in detail in Section 7.0. 5.3.3 Receive Interrupts Eight interrupts are provided to flag the occurrence of receive events, four each for SERDES A and B. In 64 chips/bit and 32 chips/bit DDR modes, only the SERDES A interrupts are available, and the SERDES B interrupts will never trigger, even if enabled. The interrupts are enabled by writing to the Receive Interrupt Enable register (Reg 0x07), and their status may be determined by reading the Receive Interrupt Status register (Reg 0x08). If more than one interrupt is enabled, it is necessary to read the Receive Interrupt Status register (Reg 0x08) to determine which event caused the IRQ pin to assert. The function and operation of these interrupts are described in detail in Section 7.0. IRQ DIOVAL DIO v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v... data to mcu d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d... Figure 5-6. DIO Receive Sequence IRQ DIOVAL DIO v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v... data from mcu d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d... Figure 5-7. DIO Transmit Sequence Document #: 38-16008 Rev. *C Page 5 of 33 CYWUSB6935 6.0 Application Examples Figure 6-2 shows an application example of a WirelessUSB LR alarm system where a single hub node is connected to an alarm panel. The hub node wirelessly receives information from multiple sensor nodes in order to control the alarm panel. Figure 6-1 shows a block diagram example of a typical battery powered device using the CYWUSB6935 chip. LDO/ DC2DC + 3.3 V 0.1µF 2.0 pF 2.0 pF 3.3 nH RFIN PCB Trace Antenna Battery - 1.2 pF Vcc RESET PD IRQ Vcc Application Hardware PSoC 8-bit MCU RFOUT WirelessUSB LR 13MHz Crystal 2.2 nH 27 pF SPI 4 Figure 6-1. CYWUSB6935 Battery Powered Device W ir elessU S B LR ALAR M P AN E L W ir elessU S B LR R S P S oC + S MO K E D E TE C TO R P S oC + MO TIO N D E TE C TO R P S oC + D O O R SENSOR W ir elessU S B LR + P S oC Document #: 38-16008 Rev. *C 23 2 W ir elessU S B LR … W ir elessU S B LR Figure 6-2. WirelessUSB LR Alarm System P S oC + K E YP AD Page 6 of 33 CYWUSB6935 7.0 Register Descriptions Table 7-1 displays the list of registers inside the CYWUSB6935 that are addressable through the SPI interface. All registers are read and writable, except where noted. Table 7-1. CYWUSB6935 Register Map[1] Register Name Mnemonic CYWUSB6935 Address Page Default Access Revision ID Control Data Rate Configuration SERDES Control Receive SERDES Interrupt Status Receive SERDES Data A Receive SERDES Valid A Receive SERDES Data B Receive SERDES Valid B REG_ID REG_CONTROL REG_DATA_RATE REG_CONFIG REG_SERDES_CTL REG_RX_INT_STAT REG_RX_DATA_A REG_RX_VALID_A REG_RX_DATA_B REG_RX_VALID_B 0x00 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x18–0x11 0x19 0x1A 0x1C 0x1D 0x20 0x21 0x22 0x23 0x24 0x26 0x2E 0x2F 0x32 0x33 0x38 0x3C–0x3F 8 8 9 10 10 11 12 13 13 13 13 14 14 15 15 15 16 16 17 17 17 18 18 18 19 19 20 20 20 20 21 21 0x07 0x00 0x00 0x01 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1E8B6A3DE0E9B222 RO RW RW RW RW RW RO RO RO RO RO RW RO RW RW RW RW RW RW RO RW RW RO RW RW RW RW RW RW RW RW RO Receive SERDES Interrupt Enable REG_RX_INT_EN Transmit SERDES Interrupt Enable REG_TX_INT_EN Transmit SERDES Interrupt Status REG_TX_INT_STAT Transmit SERDES Data Transmit SERDES Valid PN Code Threshold Low Threshold High Wake Enable Wake Status Analog Control Channel Receive Signal Strength Indicator PA Bias Crystal Adjust VCO Calibration Reg Power Control Carrier Detect Clock Manual Clock Enable Synthesizer Lock Count Manufacturing ID Note: 1. All registers are accessed Little Endian. REG_TX_DATA REG_TX_VALID REG_PN_CODE REG_THRESHOLD_L REG_THRESHOLD_H REG_WAKE_EN REG_WAKE_STAT REG_ANALOG_CTL REG_CHANNEL REG_RSSI REG_PA REG_CRYSTAL_ADJ REG_VCO_CAL REG_PWR_CTL REG_CARRIER_DETECT REG_CLOCK_MANUAL REG_CLOCK_ENABLE REG_SYN_LOCK_CNT REG_MID 0x08 0x38 0x00 0x01 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x64 – Document #: 38-16008 Rev. *C Page 7 of 33 CYWUSB6935 Addr: 0x00 7 6 Silicon ID 5 4 REG_ID 3 2 Product ID 1 Default: 0x07 0 Figure 7-1. Revision ID Register Bit 7:4 3:0 Name Silicon ID Product ID Description These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only. These are the Product ID revision bits. Fixed at value 0111. These bits are read-only. Addr: 0x03 7 RX Enable 6 TX Enable 5 PN Code Select REG_CONTROL 4 3 2 Internal PA Enable 1 Bypass Internal Auto Internal PA Syn Lock Signal Disable Default: 0x00 0 Reserved Reserved Figure 7-2. Control Bit 7 Name RX Enable Description The Receive Enable bit is used to place the IC in receive mode. 1 = Receive Enabled 0 = Receive Disabled The Transmit Enable bit is used to place the IC in transmit mode. 1 = Transmit Enabled 0 = Transmit Disabled 6 TX Enable 5 PN Code Select The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code. 1 = 32 Most Significant Bits of PN code are used 0 = 32 Least Significant Bits of PN code are used This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1). Bypass Internal This bit controls whether the state machine waits for the internal Syn Lock Signal before waiting for the amount of Syn Lock Signal time specified in the Syn Lock Count register (Reg 0x38), in units of 2 µs. If the internal Syn Lock Signal is used then set Syn Lock Count to 25 to provide additional assurance that the synthesizer has settled. 1 = Bypass the Internal Syn Lock Signal and wait the amount of time in Syn Lock Count register (Reg 0x38) 0 = Wait for the Syn Lock Signal and then wait the amount of time specified in Syn Lock Count register (Reg 0x38) It is recommended that the application MCU sets this bit to 1 in order to guarantee a consistent settle time for the synthesizer. Auto Internal PA The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier. The Disable two options are automatic control by the baseband or by firmware through register writes. For external PA usage, please see the description of the REG_ANALOG_CTL register (Reg 0x20). 1 = Register controlled Internal PA Enable 0 = Auto controlled Internal PA Enable When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg 0x03, bit 2). It is recommended that this bit is set to 0, leaving the PA control to the baseband. Internal PA Enable The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier. 1 = Internal Power Amplifier Enabled 0 = Internal Power Amplifier Disabled This bit only applies when the Auto Internal PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t care. This bit is reserved and should be written with a zero. This bit is reserved and should be written with a zero. 4 3 2 1 0 Reserved Reserved Document #: 38-16008 Rev. *C Page 8 of 33 CYWUSB6935 Addr: 0x04 7 6 5 Reserved REG_DATA_RATE 4 3 2 Code Width 1 Default: 0x00 0 Sample Rate Data Rate Figure 7-3. Data Rate Bit 7:3 2[2] Name Reserved Code Width Description These bits are reserved and should be written with zeroes. The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes. 1 = 32 chips/bit PN codes 0 = 64 chips/bit PN codes The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample Rate (Reg 0x04, bit 0). The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of 62.5kbits/sec. 1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions) 0 = Normal Data Rate - 1 bit per PN code This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg 0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate capability. When using Normal Data Rate, the raw data throughput is 32 kbits/sec. Additionally, Normal Data Rate enables the user to potentially correlate data using two differing 32 chips/bit PN codes. 1[2] Data Rate 0[2] Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate. 1 = 12x Oversampling 0 = 6x Oversampling Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double Data Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN code is being used with Normal Data Rate. Note: 2. The following Reg 0x04, bits 2:0 values are not valid: • 001–Not Valid • 010–Not Valid • 011–Not Valid • 111–Not Valid Document #: 38-16008 Rev. *C Page 9 of 33 CYWUSB6935 Addr: 0x05 7 6 5 Reserved REG_CONFIG 4 3 2 1 Default: 0x01 0 IRQ Pin Select Figure 7-4. Configuration Bit 7:2 1:0 Name Reserved Description These bits are reserved and should be written with zeroes. 11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z) 10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z) 01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0) 00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1) IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin. Addr: 0x06 7 6 Reserved 5 REG_SERDES_CTL 4 3 SERDES Enable 2 1 Default: 0x03 0 EOF Length Figure 7-5. SERDES Control Bit 7:4 3 Name Reserved Description These bits are reserved and should be written with zeroes. SERDES Enable The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode. 1 = SERDES enabled 0 = SERDES disabled, bit-serial mode enabled When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to manage the timing required by the bit-serial mode. EOF Length The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without valid data before an EOF event will be generated. When in receive mode and a valid bit has been received the EOF event can then be identified by the number of bit times that expire without correlating any new data. The EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. 2:0 Document #: 38-16008 Rev. *C Page 10 of 33 CYWUSB6935 Addr: 0x07 7 Underflow B 6 Overflow B 5 EOF B REG_RX_INT_EN 4 Full B 3 Underflow A 2 Overflow A 1 Default: 0x00 0 Full A EOF A Figure 7-6. Receive SERDES Interrupt Enable Bit 7 Name Underflow B Description The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES Data B register (Reg 0x0B) 1 = Underflow B interrupt enabled for Receive SERDES Data B 0 = Underflow B interrupt disabled for Receive SERDES Data B An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is empty. The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data B register (Reg 0x0B) 1 = Overflow B interrupt enabled for Receive SERDES Data B 0 = Overflow B interrupt disabled for Receive SERDES Data B An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg 0x0B) before the prior data is read out. The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition. 1 = EOF B interrupt enabled for Channel B Receiver 0 = EOF B interrupt disabled for Channel B Receiver The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive status register The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having data placed in it. 1 = Full B interrupt enabled for Receive SERDES Data B 0 = Full B interrupt disabled for Receive SERDES Data B A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES Data A register (Reg 0x09) 1 = Underflow A interrupt enabled for Receive SERDES Data A 0 = Underflow A interrupt disabled for Receive SERDES Data A An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is empty. The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data A register (0x09) 1 = Overflow A interrupt enabled for Receive SERDES Data A 0 = Overflow A interrupt disabled for Receive SERDES Data A An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09) before the prior data is read out. The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel A Receiver. 1 = EOF A interrupt enabled for Channel A Receiver 0 = EOF A interrupt disabled for Channel A Receiver The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive status register. The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having data written into it. 1 = Full A interrupt enabled for Receive SERDES Data A 0 = Full A interrupt disabled for Receive SERDES Data A A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. 6 Overflow B 5 EOF B 4 Full B 3 Underflow A 2 Overflow A 1 EOF A 0 Full A Document #: 38-16008 Rev. *C Page 11 of 33 CYWUSB6935 Addr: 0x08 7 Valid B 6 Flow Violation B 5 EOF B REG_RX_INT_STAT 4 Full B 3 Valid A 2 Flow Violation A [3] Default: 0x00 1 EOF A 0 Full A Figure 7-7. Receive SERDES Interrupt Status Bit 7 Name Valid B Description The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. 1 = All bits are valid for Receive SERDES Data B 0 = Not all bits are valid for Receive SERDES Data B When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the byte that has been written are valid. This bit cannot generate an interrupt. 6 Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive SERDES Data B register (Reg 0x0B). 1 = Overflow/underflow interrupt pending for Receive SERDES Data B 0 = No overflow/underflow interrupt pending for Receive SERDES Data B Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) EOF B The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive. 1 = EOF interrupt pending for Channel B 0 = No EOF interrupt pending for Channel B An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data. 1 = Receive SERDES Data B full interrupt pending 0 = No Receive SERDES Data B full interrupt pending A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid. 1 = All bits are valid for Receive SERDES Data A 0 = Not all bits are valid for Receive SERDES Data A When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the byte that has been written are valid. This bit cannot generate an interrupt. 5 4 Full B 3 Valid A 2 Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive SERDES Data A register (Reg 0x09). 1 = Overflow/underflow interrupt pending for Receive SERDES Data A 0 = No overflow/underflow interrupt pending for Receive SERDES Data A Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) EOF A The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive. 1 = EOF interrupt pending for Channel A 0 = No EOF interrupt pending for Channel A An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08). The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data. 1 = Receive SERDES Data A full interrupt pending 0 = No Receive SERDES Data A full interrupt pending A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. 1 0 Full A Note: 3. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These registers are read-only. Document #: 38-16008 Rev. *C Page 12 of 33 CYWUSB6935 Addr: 0x09 7 6 5 REG_RX_DATA_A 4 Data 3 2 1 Default: 0x00 0 Figure 7-8. Receive SERDES Data A Bit 7:0 Name Data Description Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only. Addr: 0x0A 7 6 5 REG_RX_VALID_A 4 Valid 3 2 1 Default: 0x00 0 Figure 7-9. Receive SERDES Valid A Bit 7:0 Name Valid Description These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the corresponding data bit is valid for Channel A. If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0A). This register is read-only. Addr: 0x0B 7 6 5 REG_RX_DATA_B 4 Data 3 2 1 Default: 0x00 0 Figure 7-10. Receive SERDES Data B Bit 7:0 Name Data Description Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only. Addr: 0x0C 7 6 5 REG_RX_VALID_B 4 Valid 3 2 1 Default: 0x00 0 Figure 7-11. Receive SERDES Valid B Bit 7:0 Name Description Valid These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the corresponding data bit is valid for Channel B. If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register (Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is read-only. Document #: 38-16008 Rev. *C Page 13 of 33 CYWUSB6935 Addr: 0x0D 7 6 Reserved Bit 7:4 3 Name Reserved Underflow 5 REG_TX_INT_EN 4 3 Underflow 2 Overflow 1 Default: 0x00 0 Empty Done Figure 7-12. Transmit SERDES Interrupt Enable Description These bits are reserved and should be written with zeroes. The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit SERDES Data register (Reg 0x0F) 1 = Underflow interrupt enabled 0 = Underflow interrupt disabled An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does not have any data. The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data register (0x0F). 1 = Overflow interrupt enabled 0 = Overflow interrupt disabled An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F) before the preceding data has been transferred to the transmit shift register. The Done bit is used to enable the interrupt that signals the end of the transmission of data. 1 = Done interrupt enabled 0 = Done interrupt disabled The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and there is no more data for it to transmit. The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty. 1 = Empty interrupt enabled 0 = Empty interrupt disabled The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and it's safe to load the next byte 2 Overflow 1 Done 0 Empty Addr: 0x0E 7 6 Reserved 5 REG_TX_INT_STAT 4 3 Underflow 2 Overflow 1 Default: 0x00 0 Empty Done Figure 7-13. Transmit SERDES Interrupt Status[4] Bit Name Description 7:4 Reserved These bits are reserved. This register is read-only. 3 Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register (Reg 0x0F) has occurred. 1 = Underflow Interrupt pending 0 = No Underflow Interrupt pending This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E). 2 Overflow The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F) has occurred. 1 = Overflow Interrupt pending 0 = No Overflow Interrupt pending This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E). 1 Done The Done bit is used to signal the end of a data transmission. 1 = Done Interrupt pending 0 = No Done Interrupt pending This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E) 0 Empty The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied. 1 = Empty Interrupt pending 0 = No Empty Interrupt pending This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the data is loaded into the transmitter, and it is ok to write new data. Note: 4. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only. Document #: 38-16008 Rev. *C Page 14 of 33 CYWUSB6935 Addr: 0x0F 7 6 5 REG_TX_DATA 4 Data 3 2 1 Default: 0x00 0 Figure 7-14. Transmit SERDES Data Bit 7:0 Name Description Data Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. Addr: 0x10 7 6 5 REG_TX_VALID 4 Valid 3 2 1 Default: 0x00 0 Figure 7-15. Transmit SERDES Valid Bit 7:0 Name Description Valid[5] The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid. 1 = Valid transmit bit 0 = Invalid transmit bit Addr: 0x18-11 REG_PN_CODE Default: 0x1E8B6A3DE0E9B222 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 0x18 Address 0x17 Address 0x16 Address 0x15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address 0x14 Address 0x13 Address 0x12 9 8 7 6 5 4 3 2 1 0 Address 0x11 Figure 7-16. PN Code Bit 63:0 Name PN Codes Description The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value can be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by bit 1... followed by bit 62, followed by bit 63. Note: 5. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the Transmit SERDES Valid register (Reg 0x10) will send half a byte. Document #: 38-16008 Rev. *C Page 15 of 33 CYWUSB6935 Addr: 0x19 7 Reserved 6 5 REG_THRESHOLD_L 4 3 Threshold Low 2 1 Default: 0x08 0 Figure 7-17. Threshold Low Bit 7 6:0 Name Reserved Threshold Low Description This bit is reserved and should be written with zero. The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate a single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. Addr: 0x1A 7 Reserved 6 5 REG_THRESHOLD_H 4 3 Threshold High 2 1 Default: 0x38 0 Figure 7-18. Threshold High Bit 7 6:0 Name Reserved Threshold High Description This bit is reserved and should be written with zero. The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This value along with the Threshold Low value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. Document #: 38-16008 Rev. *C Page 16 of 33 CYWUSB6935 Addr: 0x1C 7 6 5 REG_WAKE_EN 4 Reserved 3 2 1 Default: 0x00 0 Wakeup Enable Figure 7-19. Wake Enable Bit 7:1 0 Name Reserved Description These bits are reserved and should be written with zeroes. Wakeup Enable Wakeup interrupt enable. 0 = disabled 1 = enabled A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications. Addr: 0x1D 7 6 5 REG_WAKE_STAT 4 Reserved 3 2 1 Default: 0x01 0 Wakeup Status Figure 7-20. Wake Status Bit 7:1 0 Name Reserved Wakeup Status Description These bits are reserved. This register is read-only. Wakeup status. 0 = Wake interrupt not pending 1 = Wake interrupt pending This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg 0x1D). This register is read-only. Addr: 0x20 7 Reserved 6 Reg Write Control 5 MID Read Enable REG_ANALOG_CTL 4 Reserved 3 Reserved 2 PA Output Enable 1 Default: 0x00 0 Reset PA Invert Figure 7-21. Analog Control Bit 7 6 Name Reserved Description This bit is reserved and should be written with zero. Reg Write Control Enables write access to Reg 0x2E and Reg 0x2F. 1 = Enables write access to Reg 0x2E and Reg 0x2F 0 = Reg 0x2E and Reg 0x2F are read-only MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). 1 = Enables read of MID registers 0 = Disables read of MID registers Reserved These bits are reserved and should be written with zeroes. PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier. 1 = PA Control Output Enabled on PACTL pin 0 = PA Control Output Disabled on PACTL pin PA Invert The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high. PA Output Enable and PA Invert cannot be simultaneously changed. 1 = PACTL active low 0 = PACTL active high The Reset bit is used to generate a self-clearing device reset. 1 = Device Reset. All registers are restored to their default values. 0 = No Device Reset. 5 4:3 2 1 0 Reset Document #: 38-16008 Rev. *C Page 17 of 33 CYWUSB6935 Addr: 0x21 7 Reserved 6 5 REG_CHANNEL 4 3 Channel 2 1 Default: 0x00 0 Figure 7-22. Channel Bit 7 6:0 Name Channel Description The Channel register (Reg 0x21) is used to determine the Synthesizer frequency. A value of 2 corresponds to a communication frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The channels are separated from each other by 1 MHz intervals. Limit application usage to channels 2–79 to adhere to FCC regulations. FCC regulations require that channels 0 and 1 and any channel greater than 79 be avoided. Use of other channels may be restricted by other regulatory agencies. The application MCU must ensure that this register is modified before transmitting data over the air for the first time. Reserved This bit is reserved and should be written with zero. Addr: 0x22 7 Reserved 6 5 Valid 4 REG_RSSI 3 2 RSSI 1 Default: 0x00 0 Figure 7-23. Receive Signal Strength Indicator (RSSI)[6] Bit 7:6 5 Name Reserved Valid Description These bits are reserved. This register is read-only. The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only. 1 = RSSI value is valid 0 = RSSI value is invalid The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only value with the higher values indicating stronger received signals meaning more reliable transmissions. 4:0 RSSI Addr: 0x23 7 6 5 Reserved 4 REG_PA 3 2 1 Default: 0x00 0 PA Bias Figure 7-24. PA Bias Bit 7:3 2:0 Name Reserved PA Bias Description These bits are reserved and should be written with zeroes. The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7) or decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the transmit power. By changing the PA Bias value signal strength management functions can be accomplished. For general purpose communication a value of 7 is recommended. See Table 4-1 for typical output power steps based on the PA Bias bit settings. Note: 6. The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See Section 4.7 for more details. Document #: 38-16008 Rev. *C Page 18 of 33 CYWUSB6935 Addr: 0x24 7 Reserved 6 Clock Output Disable 5 REG_CRYSTAL_ADJ 4 3 Crystal Adjust 2 1 Default: 0x00 0 Figure 7-25. Crystal Adjust Bit 7 6 Name Description Reserved This bit is reserved and should be written with zero. Clock Output Disable The Clock Output Disable bit disables the 13-MHz clock driven on the X13OUT pin. 1 = No 13-MHz clock driven externally 0 = 13-MHz clock driven externally If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on channels 5+13n. By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the 13-MHz clock, but it interfere with every 13th channel beginning with 2.405-GHz channel. Therefore, it is recommended that the 13-MHz clock output pin be disabled when not in use. The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5 pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1–2 pF. 5:0 Crystal Adjust Addr: 0x26 7 6 5 REG_VCO_CAL 4 3 Reserved 2 1 Default: 0x00 0 VCO Slope Enable Figure 7-26. VCO Calibration Bit 7:6 Name Description VCO Slope Enable The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automat(Write-Only) ically added to the VCO. 11 = –5/+5 VCO adjust. The application MCU must configure this option during initialization 10 = –2/+3 VCO adjust 01 = Reserved 00 = No VCO adjust These bits are undefined for read operations. Reserved These bits are reserved and should be written with zeroes. 5:0 Document #: 38-16008 Rev. *C Page 19 of 33 CYWUSB6935 Addr: 0x2E 7 Reg Power Control 6 5 REG_PWR_CTL 4 3 Reserved 2 1 Default: 0x00 0 Figure 7-27. Reg Power Control Bit 7 6:0 Name Reg Power Control Reserved Description When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable writes to Reg 0x2E. The application MCU must set this bit during initialization. These bits are reserved and should be written with zeroes. Addr: 0x2F 7 Carrier Detect Override 6 5 REG_CARRIER_DETECT 4 3 Reserved 2 1 Default: 0x00 0 Figure 7-28. Carrier Detect Bit 7 6:0 Name Carrier Detect Override Reserved Description When set, this bit overrides carrier detect. The user must set Reg 0x20, bit 6=1 to enable writes to Reg 0x2F. These bits are reserved and should be written with zeroes. Addr: 0x32 7 6 5 REG_CLOCK_MANUAL 4 3 2 1 Default: 0x00 0 Manual Clock Overrides Figure 7-29. Clock Manual Bit Name 7:0 Manual Clock Overrides Description This register must be written with 0x41 after reset for correct operation Addr: 0x33 7 6 5 REG_CLOCK_ENABLE 4 3 2 1 Default: 0x00 0 Manual Clock Enables Figure 7-30. Clock Enable Bit 7:0 Name Description Manual Clock Enables This register must be written with 0x41 after reset for correct operation Document #: 38-16008 Rev. *C Page 20 of 33 CYWUSB6935 Addr: 0x38 7 6 5 REG_SYN_LOCK_CNT 4 Count 3 2 1 Default: 0x64 0 Figure 7-31. Synthesizer Lock Count Bit 7:0 Name Count Description Determines the length of delay in 2-µs increments for the synthesizer to lock when auto synthesizer is enabled via Control register (0x03, bit 1=0) and not using the PLL lock signal. The default register setting is typically sufficient. Addr: 0x3C-3F Address 0x3F Address 0x3E REG_MID 9 8 7 6 5 4 3 2 1 0 Address 0x3D Address 0x3C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Figure 7-32. Manufacturing ID Bit Name Description 31:30 Address[31:30] These bits are read back as zeroes. 29:0 Address[29:0] These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only. Document #: 38-16008 Rev. *C Page 21 of 33 CYWUSB6935 8.0 Pin Descriptions Name Type Default Description RF Input. Modulated RF signal received. RF Output. Modulated RF signal to be transmitted. Crystal Input. (refer to Section 4.6). Crystal Input. (refer to Section 4.6). System Clock. Buffered 13-MHz system clock. Power Down. Asserting this input (low), will put the IC in the Suspend Mode (X13OUT is 0 when PD is Low). Active LOW Reset. Device reset. PACTL. External Power Amplifier control. Pull-down or make output. Data Input/Output. SERDES Bypass Mode Data Transmit/Receive. Data I/O Valid. SERDES Bypass Mode Data Transmit/Receive Valid. IRQ. Interrupt and SERDES Bypass Mode DIOCLK. Master-Output-Slave-Input Data. SPI data input pin. Master-Input-Slave-Output Data. SPI data output pin. SPI Input Clock. SPI clock. Slave Select Enable. SPI enable. Table 8-1. Pin Description Table Pin QFN Analog RF 46 5 38 35 26 33 14 34 20 19 21 23 24 25 22 RFIN RFOUT X13 X13IN X13OUT PD RESET PACTL DIO DIOVAL IRQ MOSI MISO SCK SS Input Output Input Input Output/Hi-Z Input Input I/O I/O I/O Output /Hi-Z Input Output/Hi-Z Input Input Input N/A N/A N/A Output N/A N/A Input Input Input Output N/A Hi-Z N/A N/A Crystal / Power Control SERDES Bypass Mode Communications/Interrupt SPI Communications Power and Ground 6, 9, 16, 28, 29, 32, VCC 41, 42, 44, 45 13 GND 1, 2, 3, 4, 7, 8, 10, 11, 12, 15, 17, 18, 27, 30, NC 31, 36, 37, 39, 40, 43, 47, 48 Exposed GND paddle VCC = 2.7V to 3.6V. VCC GND H L Ground = 0V. Must be tied to Ground. N/A N/A GND L Must be tied to Ground. Document #: 38-16008 Rev. *C Page 22 of 33 CYWUSB6935 CYWUSB6935 Top View* RFIN 46 X13 38 VCC 45 VCC 44 VCC 42 VCC 41 NC 48 NC 1 NC 2 NC 3 NC 4 RFOUT 5 V CC 6 NC 7 NC 8 V CC 9 NC 10 NC 11 NC 12 13 GND * E-PAD BOTTOM SIDE Figure 8-1. CYWUSB6935, 48 QFN – Top View NC 47 14 RESET CYWUSB6935 48 QFN NC 43 NC 40 NC 39 NC 37 36 NC 35 X13IN 34 PACTL 33 PD 32 V CC 31 NC 30 NC 29 V CC 28 V CC 27 NC 26 X13OUT 25 SCK 15 NC 16 VCC 17 NC 18 NC 19 DIOVAL 20 DIO 21 IRQ 22 SS 23 MOSI 24 MISO Document #: 38-16008 Rev. *C Page 23 of 33 CYWUSB6935 9.0 Absolute Maximum Ratings 10.0 Operating Conditions Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied .. –55°C to +125°C Supply Voltage on VCC relative to VSS.......... –0.3V to +3.9V DC Voltage to Logic Inputs[7] .................. –0.3V to VCC +0.3V DC Voltage applied to Outputs in High-Z State........................... –0.3V to VCC +0.3V Static Discharge Voltage (Digital)[8] ...........................>2000V Static Discharge Voltage (RF)[8].................................... 500V Latch-up Current ..................................... +200 mA, –200 mA VCC (Supply Voltage)..........................................2.7V to 3.6V TA (Ambient Temperature Under Bias) ....... -40°C to +85°C[9] TA (Ambient Temperature Under Bias) .........0°C to +70°C[10] Ground Voltage ................................................................. 0V FOSC (Oscillator or Crystal Frequency) ..................... 13 MHz 11.0 VCC VOH1 VOH2 VOL VIH VIL IIL CIN ISleep IDLE ICC DC Characteristics (Over the Operating Range) Description Conditions Min. Typ.[12] Max. Unit Parameter Supply Voltage Output High Voltage condition 1 Output High Voltage condition 2 Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Pin Input Capacitance (except X13, X13IN, RFIN) Current consumption during power-down mode PD = LOW Current consumption without synthesizer ICC from PD high to oscillator stable. Average transmitter current consumption[13] Current consumption during receive Current consumption during transmit Current consumption with Synthesizer on, No Transmit or Receive PD = HIGH 0 < VIN < VCC At IOH = –2.0 mA At IOL = 2.0 mA 2.7 At IOH = –100.0 µA VCC – 0.1 2.4 2.0 –0.3 –1 3.0 VCC 3.0 0.0 3.6 V V V 0.4 VCC [11] V V V µA pF µA mA mA µA mA mA mA 0.8 0.26 3.5 0.24 3 1.8 1.4 57.7 69.1 28.7 +1 10 15 STARTUP ICC TX AVG ICC RX ICC (PEAK) TX ICC (PEAK) SYNTH SETTLE ICC Notes: 7. It is permissible to connect voltages above VCC to inputs through a series resistor limiting input current to 1 mA. This can’t be done during power down mode. AC timing not guaranteed. 8. Human Body Model (HBM). 9. Industrial temperature operating range. 10. Commercial temperature operating range. 11. It is permissible to connect voltages above VCC to inputs through a series resistor limiting input current to 1 mA. 12. Typ. values measured with VCC = 3.0V @ 25°C 13. Average ICC when transmitting a 10-byte packet every 15 minutes using the WirelessUSB N:1 protocol. Document #: 38-16008 Rev. *C Page 24 of 33 CYWUSB6935 12.0 AC Characteristics [14] Parameter Description Min. Typ. Max. Unit Table 12-1. SPI Interface[16] tSCK_CYC tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tSS_SU tSS_HLD SPI Clock Period SPI Clock High Time SPI Clock Low Time SPI Input Data Set-up Time SPI Input Data Hold Time SPI Output Data Valid Time SPI Slave Select Set-up Time before first positive edge of SCK[17] SPI Slave Select Hold Time after last negative edge of SCK 476 238 158 158 10 97[16] 77 [16] ns ns ns ns ns ns 174 [16] tSCK_HI (BURST READ)[15] SPI Clock High Time ns ns ns 250 80 tSCK_CYC tSCK_HI SCK SS MOSI M IS O tSCK_LO D R IV E tSS_SU tDAT_SU SA M PL E tDAT_HLD d a ta fro m m c u tSS_HLD d a ta fro m m c u d a ta fro m m c u d a ta tD AT_VAL d a ta to m c u d a ta to m c u d a ta Figure 12-1. SPI Timing Diagram t SCK_CYC t SCK_HI SCK SS M ISO data to m cu every 8 S C K_HI D R th t SCK_LO IV E t SC K_HI (BU RST READ) every 9 th S C K_HI D R IV every 10 th S CK_HI D E R IV E data to m cu data to m cu data t DAT_VAL Figure 12-2. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram Notes: 14. AC values are not guaranteed if voltages on any pin exceed VCC. 15. This stretch only applies to every 9th SCK HI pulse for SPI Burst Reads only. 16. For FOSC = 13 MHz, 3.3v @ 25°C. 17. SCK must start low, otherwise the success of SPI transactions are not guaranteed. Document #: 38-16008 Rev. *C Page 25 of 33 CYWUSB6935 Table 12-2. DIO Interface Parameter Transmit Description Min. Typ. Max. Unit tTX_DIOVAL_SU tTX_DIO_SU tTX_DIOVAL_HLD tTX_DIO_HLD tTX_IRQ_HI DIOVAL Set-up Time DIO Set-up Time DIOVAL Hold Time DIO Hold Time Minimum IRQ High Time – 32 chips/bit DDR Minimum IRQ High Time – 32 chips/bit Minimum IRQ High Time – 64 chips/bit 2.1 2.1 0 0 8 16 32 8 16 32 –0.01 –0.01 –0.01 –0.01 –0.01 –0.01 1 1 1 8 16 32 6.1 8.2 16.1 6.1 8.2 16.1 µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs tTX_IRQ_LO Minimum IRQ Low Time – 32 chips/bit DDR Minimum IRQ Low Time – 32 chips/bit Minimum IRQ Low Time – 64 chips/bit Receive tRX_DIOVAL_VLD DIOVAL Valid Time – 32 chips/bit DDR DIOVAL Valid Time – 32 chips/bit DIOVAL Valid Time – 64 chips/bit tRX_DIO_VLD DIO Valid Time – 32 chips/bit DDR DIO Valid Time – 32 chips/bit DIO Valid Time – 64 chips/bit tRX_IRQ_HI Minimum IRQ High Time – 32 chips/bit DDR Minimum IRQ High Time – 32 chips/bit Minimum IRQ High Time – 64 chips/bit tRX_IRQ_LO Minimum IRQ Low Time – 32 chips/bit DDR Minimum IRQ Low Time – 32 chips/bit Minimum IRQ Low Time – 64 chips/bit t R X _ IR Q _ H I IR Q D IO / D IO V A L SA M PL E t R X _ IR Q _ L O SA M PL E d a ta d a ta d a ta t D IO t R XR_X _IO V A_LV_LVDL D D Figure 12-3. DIO Receive Timing Diagram t TX _IR Q _H I IR Q D IO / D IO V A L SA M PL E t T X _IR Q _LO SA M PL E data data t TX _D IO V A L_S U t T X _D IO _S U t T X _D IO V A L_H LD t T X _D IO _H LD Figure 12-4. DIO Transmit Timing Diagram Document #: 38-16008 Rev. *C Page 26 of 33 CYWUSB6935 12.1 Radio Parameters Parameter Description Conditions Min. Typ. Max. Unit Table 12-3. Radio Parameters RF Frequency Range Sensitivity Maximum Received Signal RSSI value for PWRin > –40 dBm RSSI value for PWRin < –95 dBm Interference Performance Note 19 2.400 –86 –20 –95 –7 28–31 0–10 6 -5 –33 –45 –35 –41 2.483 GHz dBm dBm Radio Receiver (T = 25°C, VCC = 3.3V, fosc = 13.000 MHz ± 2 ppm, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10–3) Co-channel Interference rejection Carrier-to-Interference (C/I) C = –60 dBm Adjacent (1 MHz) channel selectivity C/I 1 MHz Adjacent (2 MHz) channel selectivity C/I 2 MHz Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz Image[21] Frequency Interference, C/I Image C = –60 dBm C = –60 dBm C = –67 dBm C = –67 dBm dB dB dB dB dB dB Adjacent (1 MHz) interference to in-band image frequency, C/I C = –67 dBm image ±1 MHz Out-of-Band Blocking Interference Signal Frequency 30 MHz–2399 MHz except (FO/N & FO/N±1 MHz)[18] 2498 MHz–12.75 GHz, Intermodulation Spurious Emission [18] except (FO*N & FO*N±1 MHz) C = –67 dBm C = –67 dBm C = –64 dBm ∆f = 5,10 MHz –22 –21 –32 dBm dBm dBm 30 MHz–1 GHz 1 GHz–12.75 GHz except (4.8 GHz–5.0 GHz) 4.8 GHz–5.0 GHz Radio Transmitter (T = 25°C, VCC = 3.3V, fosc = 13.000 MHz ± 2 ppm) –57 –54 –4020] PA = 7 seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 100-kHz resolution bandwidth, –6 dBc 500 -5 –0.4 28.6 4.1 270 320 dBm dBm dBm dBm dB dB kHz kHz ns kHz kHz Maximum RF Transmit Power RF Power Control Range RF Power Range Control Step Size Frequency Deviation Frequency Deviation Zero Crossing Error Occupied Bandwidth Initial Frequency Offset In-band Spurious ±75 860 ±50 –45 –52 –30 –40 –54 –28 –25 –42 Second Channel Power (±2 MHz) > Third Channel Power (>3 MHz) Non-Harmonically Related Spurs dBm dBm dBm dBm dBm dBm 30 MHz–12.75 GHz Harmonic Spurs Second Harmonic Third Harmonic Fourth and Greater Harmonics Notes: 18. FO = Tuned Frequency, N = Integer. 19. Subject to regulation. 20. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements. 21. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection). Document #: 38-16008 Rev. *C Page 27 of 33 CYWUSB6935 12.2 Power Management Timing Table 12-4. Power Management Timing (The values below are dependent upon oscillator network component selection)[26] Parameter Description Conditions Min. Typ Max. Unit tPDN_X13 tSPI_RDY tPWR_RST tRST tPWR_PD tWAKE tPD tSLEEP tWAKE_INT tSTABLE tSTABLE2 Time from PD deassert to X13OUT Time from oscillator stable to start of SPI transactions Power On to RESET deasserted Minimum RESET asserted pulse width Power On to PD deasserted[22] PD deassert to clocks running PD assert to low power mode PD deassert to IRQ[24] assert (wake interrupt)[25] PD deassert to clock stable IRQ assert (wake interrupt) to clock stable to within ±10 ppm to within ±10 ppm [23] 2000 1 VCC @ 2.7V 1300 1 1300 2000 10 50 2000 2100 2100 µs µs µs µs µs µs µs ns µs µs µs Minimum PD asserted pulse width X13O U T VCC RESET PD tPDN_X13 S A T R T P U t S P I_ R D Y tPW R _R ST tPW R_PD tRST Figure 12-5. Power On Reset/Reset Timing X13OUT E SL tWAKE A W PD t PD tSLEEP IRQ Notes: 22. The PD pin must be asserted at power up to ensure proper crystal startup. 23. When X13OUT is enabled. 24. Both the polarity and the drive method of the IRQ pin are programmable. See page 10 for more details. Figure 12-6 illustrates default values for the Configuration register (Reg 0x05, bits 1:0). 25. A wakeup event is triggered when the PD pin is deasserted. Figure 12-6 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0=1). 26. Measured with CTS ATXN6077A crystal. Document #: 38-16008 Rev. *C EP t WAKE_INT Figure 12-6. Sleep / Wake Timing KE t STABLE tSTABLE2 Q IR Page 28 of 33 CYWUSB6935 12.3 Typical Operating Characteristics R eceiver Sensitivity 2.440G 3.3v Hz, -86 -88 Sensitivit y (dBm) -90 -92 -94 -96 -98 -100 -50 SM pec in S Typ pec Tem S c p pe Typical BER Sensitivity vs Temp GUID: 0x0ECC7E75 -93.5 -94.0 BER Rx Sens (dBm) -94.5 -95.0 -95.5 -96.0 -96.5 -97.0 -97.5 -98.0 -50 0 Temperature (°C) 50 100 3.3 3.7 2.6 -30 -10 10 30 T p(degC em ) 50 70 90 BER Sensitivity vs Tem @2.6v p -92.5 -93.0 BER Rx Sens ( dBm) -93.5 -94.0 -94.5 -95.0 -95.5 -96.0 -96.5 -50 -30 -10 10 30 50 70 90 LR06 0x0ECC7E75 BER Sensitivity vs Tem @3.3v p -94.0 BER Rx Sens (dBm) -94.5 -95.0 -95.5 -96.0 -96.5 -97.0 -97.5 -50 -30 -10 10 30 50 70 90 LR06 0x0ECC7E75 LR07 0x17D34AAD LR14 0x0DD2E9F8 LR07 0x17D34AAD LR14 0x0DD2E9F8 Tem perature (°C) Tem perature (°C) BER Sensitivity vs Tem @3.7v p -94.5 BER Rx Sens (dBm) -95.0 -95.5 -96.0 -96.5 -97.0 -97.5 -98.0 -50 -30 -10 10 30 50 70 90 LR06 0x0ECC7E75 LR14 0x0DD2E9F8 BER Sensitivity vs Vcc @-45°C -95.0 BER Rx Sens (dBm) LR07 0x17D 34AAD -95.5 -96.0 -96.5 -97.0 -97.5 -98.0 2.5 LR06 0x0ECC7E75 LR07 0x17D34AAD LR14 0x0DD2E9F8 Tem perature (°C) 2.7 2.9 3.1 Vcc 3.3 3.5 3.7 3.9 Document #: 38-16008 Rev. *C Page 29 of 33 CYWUSB6935 BER Sensitivity vs Vcc @25°C -94.0 LR06 0x0ECC7E75 LR14 0x0DD2E9F8 BER Sensitivity vs Vcc @90°C -93.0 LR06 0x0EC C7E75 BER Rx Sens (dBm) BER Rx Sens (dBm) -94.5 -95.0 -95.5 -96.0 -96.5 2.5 LR07 0x17D34AAD -93.5 -94.0 -94.5 -95.0 -95.5 2.5 LR07 0x17D34AAD LR14 0x0DD 2E9F8 2.7 2.9 3.1 Vcc 3.3 3.5 3.7 3.9 2.7 2.9 3.1 Vcc 3.3 3.5 3.7 3.9 M axim Trans it O um m utput Power 2.440G z, 3.3v H 0 0.4 Tx Ch40 Output Power LR18 0x17D34E2D -1 -2 -3 -4 -5 -6 -50 Spec M in Power (dBm) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -60 2.6 3.3 3.7 Power ( dBm) Spec T yp T pS em pec Average -30 -10 10 30 50 70 90 -40 -20 0 20 Temp (degC) 40 60 80 100 Temp (degC ) Tx Ch40 O utput Power LR20 0xDD2E6A 8 0 -1 Power (dBm) -2 -3 -4 -5 -6 -50 -30 -10 10 30 50 70 90 Tem (degC p ) 2.6 3.3 Power (dBm) 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -60 Tx Ch0 O utput Power LR21 0xECC7E71 3.7 Spec M in Spec Typ Temp Spec 2.6 3.3 3.7 -40 -20 0 20 Temp (degC ) 40 60 80 100 Document #: 38-16008 Rev. *C Page 30 of 33 CYWUSB6935 12.4 AC Test Loads and Waveforms for Digital Pins AC Test Loads OUTPUT 30 pF INCLUDING JIG AND SCOPE OUTPUT 5 pF INCLUDING JIG AND SCOPE DC Test Load VCC OUTPUT R2 R1 Max Typical ALL INPUT PULSES Parameter R1 R2 RTH VTH VCC 1071 937 500 1.4 3.00 Unit Ω Ω Ω V V VCC GND Rise time: 1 V/ns Equivalent to: 90% 10% 90% 10% Fall time: 1 V/ns THÉVENIN EQUIVALENT RTH VTH OUTPUT Figure 12-7. AC Test Loads and Waveforms for Digital Pins 13.0 Ordering Information Part Number Radio Package Name Package Type Operating Range CYWUSB6935-48LFXI CYWUSB6935-48LFXC Transceiver Transceiver 48 QFN 48 QFN 48 Quad Flat Package No Leads Lead-Free 48 Quad Flat Package No Leads Lead-Free Industrial Commercial Document #: 38-16008 Rev. *C Page 31 of 33 CYWUSB6935 14.0 Package Description 6.90 7.10 6.70 6.80 N 0.08 1.00 MAX. C 0.05 MAX. 0.80 MAX. 0.20 REF. X 0.23±0.05 N PIN1 ID 0.20 R. 1 2 0.45 1 2 0.80 DIA. 6.90 7.10 6.70 6.80 E-PAD Y 5.45 5.55 0.30-0.45 0°-12° C 5.45 5.55 0.50 SEATING PLANE 0.42±0.18 (4X) TOP VIEW SIDE VIEW E-PAD SIZE PADDLE SIZE (X, Y MAX.) BOTTOM VIEW DIMENSIONS IN mm MIN. MAX. REFERENCE JEDEC MO-220 PKG. WEIGHT 0.13 gms 5.1 X 5.1 3.8 X 3.8 5.3 X 5.3 4.0 X 4.0 51-85152-*B Figure 14-1. 48-pin Lead-Free QFN 7 × 7 mm LY48 The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 209 mils × 209 mils (width x length). This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or technical support regarding Cypress WirelessUSB products please contact Cypress at www.cypress.com. WirelessUSB, PSoC, and enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-16008 Rev. *C Page 32 of 33 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYWUSB6935 Document History Page Document Title: CYWUSB6935 WirelessUSB LR™ 2.4-GHz DSSS Radio SoC Document Number: 38-16008 REV. ECN NO. Issue Date Orig. of Change Description of Change ** *A 207428 275349 See ECN See ECN TGE ZTK New data sheet Updated REG_DATA_RATE (0x04), 111 - Not Valid Changed AVCC annotation to VCC Removed SOIC package option Corrected Figure 3-1, Figure 6-1 and Figure 6-2 Updated ordering information section Added Table 4-1 Internal PA Output Power Step Table Corrected Figure 14-1 caption Updated Radio Parameters Added commercial temperature operating range in section 10 Updated average transmitter current consumption number Added tSTABLE2 parameter to Table 12-4 and Figure 12-6 Removed Addr 0x01 and 0x02–unused Corrected Figure 6-1 - swap RFIN / RFOUT Corrected REG_CONTROL - bit 1 description Added Section 12.3 - Typical Operating Characteristics *B *C 291015 335774 See ECN See ECN ZTK TGE Document #: 38-16008 Rev. *C Page 33 of 33