MB88152APNF-G-111-JNERE1

CY88152A Spread Spectrum Clock Generator CY88152A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency. Features ■ Input frequency : 16.6 MHz to 134 MHz ■ Output frequency : 16.6 MHz to 134 MHz ■ Modulation rate : ■ Equipped with oscillation circuit: Range of oscillation 16.6 MHz to 48 MHz ■ Modulation clock output Duty : 40% to 60% ■ Modulation clock Cycle-Cycle Jitter : Less than 100 ps ■ Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load) ■ Power supply voltage : 3.3 V ± 0.3 V ■ Operating temperature : ■ Package : SOP 8-pin ± 0.5%, ± 1.5% (Center spread), − 1.0%, − 3.0% (Down spread) − 40° to +85 °C Cypress Semiconductor Corporation Document Number: 002-08308 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised Tuesday, July 31, 2018 CY88152A Contents Product Line-up ................................................................ 3 Output Clock Duty Cycle (tDCC = tb/ta) ......................... 15 Pin Assignment ................................................................ 3 Input Frequency (fin = 1/tin) ........................................... 15 Pin Description ................................................................. 3 Output Slew Rate (SR) .................................................. 15 I/O Circuit Type ................................................................. 4 Cycle-cycle Jitter (tJC = | tn − tn + 1 |) ............................ 15 Handling Devices .............................................................. 5 Modulation Waveform .................................................... 16 Block Diagram .................................................................. 6 Lock-up Time .................................................................. 17 Pin Setting ......................................................................... 7 Modulation enable setting ........................................... 7 SEL modulation rate setting ........................................ 7 Frequency setting ........................................................ 7 Oscillation Circuit ........................................................... 18 Absolute Maximum Ratings ........................................... 9 Recommended Operating Conditions .......................... 10 Electrical Characteristics ............................................... 12 DC Characteristics .................................................... 12 AC Characteristics ..................................................... 13 Document Number: 002-08308 Rev. *C Interconnection Circuit Example .................................. 19 Example Characteristics ................................................ 20 Ordering Information...................................................... 21 Package Dimension ........................................................ 22 Document History ........................................................... 23 Sales, Solutions, and Legal Information ...................... 24 Page 2 of 24 CY88152A 1. Product Line-up CY88152A has three kinds of input frequency, and two kinds of modulation type (center/down spread), total six line-ups. Product Input/Output Frequency CY88152A-100 16.6 MHz to 134 MHz CY88152A-101 16.6 MHz to 67 MHz CY88152A-111 16.6 MHz to 67 MHz CY88152A-112 40 MHz to 134 MHz Modulation Type Down spread Modulation Enable Pin No Yes Center spread Yes 2. Pin Assignment TOP VIEW XIN 1 8 XENS CY88152A-101 XOUT 2 CY88152A-111 CY88152A-112 XIN 1 7 FREQ 8 FREQ1 XOUT 2 CY88152A-100 7 FREQ0 VSS 3 6 VDD VSS 3 6 VDD SEL 4 5 CKOUT SEL 4 5 CKOUT SOB008 SOB008 3. Pin Description Pin Name I/O Pin No. Description XIN I 1 Crystal resonator connection pin/clock input pin XOUT O 2 Crystal resonator connection pin VSS − 3 GND pin SEL I 4 Modulation rate setting pin CKOUT O 5 Modulated clock output pin VDD − 6 Power supply voltage pin FREQ/FREQ0 I 7 Frequency setting pin XENS/FREQ1 I 8 Modulation enable setting pin/frequency setting pin Document Number: 002-08308 Rev. *C Page 3 of 24 CY88152A 4. I/O Circuit Type Pin Circuit Type Remarks SEL FREQ FREQ0 FREQ1 XENS CMOS hysteresis input CKOUT ■ CMOS output ■ IOL = 4 mA Note: For XIN and XOUT pins, refer to “Oscillation Circuit”. Document Number: 002-08308 Rev. *C Page 4 of 24 CY88152A 5. Handling Devices Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS pins. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling Unused Pins ■ Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. ■ Unused output pin should be opened. The Attention when the External Clock is Used ■ Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. ■ Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power Supply Pins ■ Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. ■ We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in parallel between VSS and VDD pins near the device, as a bypass capacitor. Oscillation Circuit ■ Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and resonator (or ceramic oscillator) do not intersect other wiring. ■ Design the printed circuit board that surrounds the XIN and XOUT pins with ground. Document Number: 002-08308 Rev. *C Page 5 of 24 CY88152A 6. Block Diagram VDD Modulation rate setting SEL Frequency setting FREQ/FREQ0 XENS/FREQ1 XOUT Modulation enable / Frequency setting PLL block Clock output CKOUT Reference clock Rf = 1 MΩ XIN VSS 1 − M Phase compare Reference clock 1 − N Charge pump V/I conversion IDAC Modulation clock output Loop filter 1 − L Modulation logic CY88152A PLL block ICO Modulation rate setting/ Modulation enable setting A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. Document Number: 002-08308 Rev. *C Page 6 of 24 CY88152A 7. Pin Setting When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock takes the maximum value of Lock-Up time in “AC Characteristics of Electrical Characteristics”. 7.1 Modulation Enable Setting XENS Modulation L Modulation H No modulation CY88152A-101, CY88152A-111, CY88152A-112 Note: CY88152A-100 and CY88152A-110 do not have XENS pin. 7.2 SEL Modulation Rate Setting SEL Modulation Rate ± 0.5% L − 1.0% ± 1.5% H − 3.0% Remarks CY88152A-111, CY88152A-112 Center spread CY88152A-100, CY88152A-101 Down spread CY88152A-111, CY88152A-112 Center spread CY88152A-100, CY88152A-101 Down spread Note: The modulation rate can be changed at the level of the terminal. 7.3 Frequency Setting FREQ Frequency L H 16.6 MHz to 40 MHz CY88152A-101, CY88152A-111 40 MHz to 80 MHz CY88152A-112 33 MHz to 67 MHz CY88152A-101, CY88152A-111 66 MHz to 134 MHz CY88152A-112 Note: CY88152A-100 and CY88152A-110 do not have FREQ pin. FREQ1 FREQ0 Frequency L L 16.6 MHz to 40 MHz L H 33 MHz to 67 MHz H L 40 MHz to 80 MHz H H 66 MHz to 134 MHz CY88152A-100 Note: CY88152A-101, CY88152A-111 and CY88152A-112 have neither FREQ0 pin nor FREQ1 pin. Document Number: 002-08308 Rev. *C Page 7 of 24 CY88152A 7.3.1 Center Spread Spectrum is spread (modulated) by centering on the input frequency. 3.0% modulation width Radiation level −3.0% Frequency Input frequency Center spread example of ± 1.5% Modulation rate 7.3.2 Down Spread Spectrum is spread (modulated) below the input frequency. 3.0% modulation width Radiation level −3.0% Frequency Input frequency Down spread example of Document Number: 002-08308 Rev. *C − 3.0% Modulation rate Page 8 of 24 CY88152A 8. Absolute Maximum Ratings Parameter Power supply voltagea Input voltage Output VDD a VI voltagea VO Storage temperature TST Operation junction temperature TJ Output current IO Overshoot VIOVER Undershoot VIUNDER a. The parameter is based on VSS WARNING: Rating Symbol Min − 0.5 VSS − 0.5 VSS − 0.5 − 55 − 40 − 14 − VSS − 1.0 (tUNDER ≤ 50 ns) Unit Max + 4.0 VDD + 0.5 VDD + 0.5 + 125 + 125 + 14 VDD + 1.0 (tOVER ≤ 50 ns) − V V V °C °C mA V V = 0.0 V. Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VDD Input pin VSS tOVER ≤ 50 ns Document Number: 002-08308 Rev. *C VIUNDER ≤ VSS − 1.0 V Page 9 of 24 CY88152A 9. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Pin Power supply voltage VDD VDD “H” level input voltage VIH SEL, FREQ/FREQ0, XENS/FREQ1 XIN “L” level input voltage VIL SEL, FREQ/FREQ0, XENS/FREQ1 XIN Input clock duty cycle tDCI Input clock slew rate SRIN Operating temperature WARNING: Ta Value Conditions XIN XIN − − − Min Typ Unit Max 3.0 3.3 3.6 V VDD x 0.8 − VDD + 0.3 V − − − VDD + 0.3 V 16.6 MHz to 100 MHz VDD x 0.8 100 MHz to 134 MHz VDD x 0.9 − VSS 16.6 MHz to 100 MHz VSS 100 MHz to 134 MHz VSS − − VDD + 0.3 V VDD x 0.2 V VDD x 0.2 V VDD x 0.1 V % 16.6 MHz to 100 MHz 40 50 60 100 MHz to 134 MHz 45 50 55 Input frequency 40 MHz to 100 MHz 0.0475 x fin − 1.75 − − Input frequency 100 MHz to 134 MHz 3 − − − −40 − + 85 V/ns ⋅C The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb XIN Document Number: 002-08308 Rev. *C 1.5 V Page 10 of 24 CY88152A Input clock slew rate (SRIN) VDD x 0.80 VDD x 0.20 XIN trin tfin Note: SRIN = (VDD x 0.80 - VDD x 0.20) /trin, SRIN = (VDD x 0.80 - VDD x 0.20) /tfin Document Number: 002-08308 Rev. *C Page 11 of 24 CY88152A 10. Electrical Characteristics 10.1 DC Characteristics Parameter (Ta = −40°C to Symbol Pin ICC VDD 24 MHz output No load capacitance Output voltage VOH CKOUT “H” level output IOH = − 4 mA “L” level output IOL = 4 mA VOL Output impedance ZO CKOUT Input capacitance CIN XIN, SEL, FREQ/ FREQ0, XENS/ FREQ1 Load capacitance CL CKOUT 16.6 MHz to 134 MHz Ta = + 25 °C VDD = VI = 0.0 V f = 1 MHz 16.6 MHz to 67 MHz 67 MHz to 100 MHz 100 MHz to 134 MHz Document Number: 002-08308 Rev. *C Value Conditions Power supply current + 85°C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Min Typ Unit Max − 5.0 7.0 mA VDD − 0.5 − VDD V VSS − 0.4 V 45 − Ω − 16 pF 15 pF − − − − − − − − 10 7 Page 12 of 24 CY88152A 10.2 AC Characteristics Parameter (Ta = −40°C to Symbol Pin + 85°C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Value Conditions Min Typ Output slew rate SR CKOUT 0.4 V to 2.4 V Load capacitance 15 pF 0.4 − − − − − − − − − Output clock duty cycle tDCC CKOUT 1.5 V 40 Modulation frequency (Number of input clocks per modulation) fMOD (nMOD) CKOUT CY88152A-100 FREQ[1 : 0] = (00) Oscillation frequency Input frequency Output frequency Lock-Up time fx fin fOUT tLK XIN, XOUT XIN CKOUT CKOUT Fundamental oscillation 16.6 3rd over tone 40 CY88152A-100 16.6 CY88152A-101/111 16.6 CY88152A-112 40 CY88152A-100 16.6 CY88152A-101/111 16.6 CY88152A-112 40 tJC Document Number: 002-08308 Rev. *C CKOUT 40 Unit MHz 48 134 MHz 67 134 134 MHz 67 134 4.0 V/ns − 60 % fin/2640 (2640) fin/2280 (2280) fin/1920 (1920) kHz (clks) CY88152A-100 FREQ[1 : 0] = (01) fin/4400 (4400) fin/3800 (3800) fin/3200 (3200) CY88152A-100 FREQ[1 : 0] = (10) fin/5280 (5280) fin/4560 (4560) fin/3840 (3840) CY88152A-100 FREQ[1 : 0] = (11) fin/8800 (8800) fin/7600 (7600) fin/6400 (6400) CY88152A-101/111 FREQ = 0 fin/2640 (2640) fin/2280 (2280) fin/1920 (1920) CY88152A-101/111 FREQ = 1 fin/4400 (4400) fin/3800 (3800) fin/3200 (3200) CY88152A-112 FREQ = 0 fin/5280 (5280) fin/4560 (4560) fin/3840 (3840) CY88152A-112 FREQ = 1 fin/8800 (8800) fin/7600 (7600) fin/6400 (6400) 2 5 3 8 − 100 16.6 MHz to 80 MHz 80 MHz to 134 MHz Cycle-cycle jitter Max No load capacitance, Ta = + 25 °C, VDD = 3.3 V − − − ms ps-rms Page 13 of 24 CY88152A fout (Output frequency) Modulation wave form t fMOD (Min) Clock count nMOD (Max) fMOD (Max) Clock count nMOD (Min) t ■ CY88152A contains the modulation period to realize the efficient EMI reduction. ■ The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) . ■ Furthermore, the average value of fMOD equals the typical value of the electrical characteristics. Document Number: 002-08308 Rev. *C Page 14 of 24 CY88152A 11. Output Clock Duty Cycle (tDCC = tb/ta) ta tb 1.5 V CKOUT 12. Input Frequency (fin = 1/tin) tin 0.8 VDD XIN 13. Output Slew Rate (SR) 2.4 V 0.4 V CKOUT tr tf Note: SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf 14. Cycle-cycle Jitter (tJC = | tn − tn + 1 |) CKOUT tn tn+1 Note: Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . Document Number: 002-08308 Rev. *C Page 15 of 24 CY88152A 15. Modulation Waveform ±1.5% modulation rate, Example of center spread CKOUT output frequency + 1.5 % Frequency at modulation OFF Time − 1.5 % fMOD −1.0% modulation rate, Example of down spread CKOUT output frequency Frequency at modulation OFF Time − 0.5 % − 1.0 % fMOD Document Number: 002-08308 Rev. *C Page 16 of 24 CY88152A 16. Lock-up Time 3.0 V VDD Internal clock stabilization wait time XIN Setting pin SEL FREQ1/XENS FREQ0/FREQ VIH tLK (lock-up time ) CKOUT If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. XIN VIH XENS tLK (lock-up time ) VIL tLK (lock-up time ) CKOUT For modulation enable control using the XENS pin during normal operation, the set clock signal is output from CKOUT pin at most the lock-up time (tLK) after the level at the XENS pin is determined. Note: When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. Document Number: 002-08308 Rev. *C Page 17 of 24 CY88152A 17. Oscillation Circuit The left side of figures below shows the connection example about general resonator. The oscillation circuit has the built-in feedback resistance (Rf). The value of capacity (C1 and C2) is required adjusting to the most suitable value of an individual resonator. The right side of figures below shows the example of connecting for the 3rd over-tone resonator. The value of capacity (C1, C2 and C3) and inductance (L1) is needed adjusting to the most suitable value of an individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. When an external clock is used (the resonator is not used), input the clock to XIN pin and do not connect anything with XOUT pin. When using the resonator CY88152A Internal Rf (1 MΩ) Rf (1 MΩ) XOUT Pin XIN Pin XOUT Pin XIN Pin CY88152A External L1 C1 C2 XIN Pin C1 C2 C3 Fundamental resonator 3rd over tone resonator When using an external clock CY88152A LSI Internal Rf (1 MΩ) XIN Pin External clock XOUT Pin CY88152A LSI External OPEN Note: A jitter characteristic of an input clock may cause an affect to a cycle-cycle jitter characteristic. Document Number: 002-08308 Rev. *C Page 18 of 24 CY88152A 18. Interconnection Circuit Example XENS/FREQ1 1 8 2 7 FREQ/FREQ0 CY88152A C1 C2 SEL 3 6 4 5 + C4 C3 R1 C1, C2 : Oscillation stabilization capacitance (refer to "Oscillation Circuit”.) C3 : Capacitor of 10 μF or higher C4 : Capacitor about 0.01 μF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) R1 : Impedance matching resistor for board pattern Document Number: 002-08308 Rev. *C Page 19 of 24 CY88152A 19. Example Characteristics The condition of the examples of the characteristics is shown as follows : Input frequency = 20 MHz (Output frequency = 20 MHz : Use for CY88152A-111) Power-supply voltage = 3.3 V, None load capacity, Modulation rate = ±1.5% (center spread) . Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with, RBW = 1 kHz (ATT use for CH B Spectrum −6 dB) . 10 dB /REF 0 dBm No modulation −7.44 dBm Avg 4 ±1.5% modulation −25.75 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 20 MHZ Document Number: 002-08308 Rev. *C ATT 6 dB SWP 2.505 s SPAN 4 MHZ Page 20 of 24 CY88152A 20. Ordering Information Input/Output Frequency Part Number Modulation Type Modulation Enable pin CY88152APNF-G-100-JNE1 16.6 MHz to 134 MHz Down spread No CY88152APNF-G-101-JNE1 16.6 MHz to 67 MHz Down spread Yes CY88152APNF-G-111-JNE1 16.6 MHz to 67 MHz Center spread Yes CY88152APNF-G-112-JNE1 40 MHz to 134 MHz Center spread Yes CY88152APNF-G-100-JNEFE1 16.6 MHz to 134 MHz Down spread No CY88152APNF-G-101-JNEFE1 16.6 MHz to 67 MHz Down spread Yes CY88152APNF-G-111-JNEFE1 16.6 MHz to 67 MHz Center spread Yes CY88152APNF-G-112-JNEFE1 40 MHz to 134 MHz Center spread Yes CY88152APNF-G-100-JNERE1 16.6 MHz to 134 MHz Down spread No CY88152APNF-G-101-JNERE1 16.6 MHz to 67 MHz Down spread Yes CY88152APNF-G-111-JNERE1 16.6 MHz to 67 MHz Center spread Yes CY88152APNF-G-112-JNERE1 40 MHz to 134 MHz Center spread Yes Package Remarks 8-pin plastic SOP (SOB008) 8-pin plastic SOP (SOB008) Emboss taping (EF type) 8-pin plastic SOP (SOB008) Emboss taping (ER type) Ordering Code Definitions CY88152APNF -G -101 -JN EF E1 Pb (lead)-free Package Tape and real: (EF: Forward, ER: Reverse) Tube (No Notation) Factory location: (JN: w/f=Japan, Assemble=China) Product line up Reliability Grade: G = 100 ppm Part number: CY88152APNF Document Number: 002-08308 Rev. *C Page 21 of 24 CY88152A 21. Package Dimension 0.36 L 0.45 0.44 0.52 0.60 0.75 0.25 BSC 1.27 BSC. h 0.40 BSC. 002-15856 Rev.** 11. JEDEC SPECIFICATION NO. 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