MB88154APNF-G-103-JNEFE1

CY88154A Spread Spectrum Clock Generator CY88154A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency. Features ■ Input frequency : 16.6 MHz to 67 MHz ■ Output frequency: 16.6 MHz to 67 MHz (One time input frequency) ■ Modulation rate can select from ± 0.5%, ± 1.0%, ■ Equipped with crystal oscillation circuit: Range of oscillation 16.6 MHz to 48 MHz ■ The external clock can be input: 16.6 MHz to 67 MHz ■ Modulation clock output duty : 40% to 60% ■ Modulation clock cycle-cycle jitter : Less than 100 ps ■ Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load) ■ Power supply voltage : 3.3 V ± 0.3 V ■ Operating temperature : ■ Package : SOP 8-pin ± 1.5% or − 1.0%, − 2.0%, − 3.0%. (For center spread / down spread.) − 40 °C to +85 °C Cypress Semiconductor Corporation Document Number: 002-08252 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 30, 2018 CY88154A Contents Product Lineup ....................................................................... 3 Pin Assignment ...................................................................... 3 Pin Description ....................................................................... 3 I/O Circuit Type ....................................................................... 4 DC Characteristics .......................................................... 10 AC Characteristics........................................................... 11 Output Clock Duty Cycle (tDCC, tDCR = tb/ta) ......................... 12 Input Frequency (fin = 1/tin) ................................................. 12 Handling Devices.................................................................... 4 Preventing Latch-up .......................................................... 4 Handling Unused Pins....................................................... 4 The Attention When the External Clock is Used ............... 4 Power Supply Pins ............................................................ 5 Oscillation Circuit............................................................... 5 Output Slew Rate (SR) ........................................................ 12 Block Diagram ........................................................................ 6 Interconnection Circuit Example ........................................ 17 Pin Setting............................................................................... 7 Example Characteristics...................................................... 18 Absolute Maximum Ratings ................................................. 9 Ordering Information............................................................ 19 Recommended Operating Conditions .................................. 9 Package Dimension.............................................................. 20 Document History................................................................. 21 Sales, Solutions, and Legal Information ............................ 22 Electrical Characteristics..................................................... 10 Document Number: 002-08252 Rev. *C Cycle-cycle Jitter (tJC = | tn − tn + 1 |) ................................... 13 Modulation Waveform .......................................................... 14 Lock-up Time ........................................................................ 15 Oscillation Circuit................................................................. 16 Page 2 of 22 CY88154A 1. Product Lineup CY88154A has two kinds of input frequency, and three kinds of modulation type (center/down spread), total six line-ups. Product Input/Output Frequency Modulation Type CY88154A-103 16.6 MHz to 40 MHz CY88154A-112 33 MHz to 67 MHz CY88154A-113 16.6 MHz to 40 MHz Down spread Center spread 2. Pin Assignment TOP VIEW CKOUT 1 8 SEL1 VDD 2 VSS 3 7 REFOUT CY88154A XIN 4 6 SEL0 5 XOUT SOB008 3. Pin Description Pin Name I/O Pin No. Description CKOUT O 1 Modulated clock output pin 2 Power supply voltage pin 3 GND pin VSS ⎯ ⎯ XIN I 4 Crystal resonator connection pin/clock input pin XOUT O 5 Crystal resonator connection pin SEL0 I 6 Modulation rate setting pin REFOUT O 7 Non-modulated clock output pin SEL1 I 8 Modulation rate setting pin VDD Document Number: 002-08252 Rev. *C Page 3 of 22 CY88154A 4. I/O Circuit Type Pin Circuit Type Remarks SEL0 SEL1 CMOS hysteresis input CKOUT REFOUT ■ CMOS output ■ IOL = 3 mA Note : For XIN and XOUT pins, refer to “Oscillation Circuit” 5. Handling Devices 5.1 Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. 5.2 Handling Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. 5.3 The Attention When the External Clock is Used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Document Number: 002-08252 Rev. *C Page 4 of 22 CY88154A 5.4 Power Supply Pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in parallel between VSS pin and VDD pin near the device, as a bypass capacitor. 5.5 Oscillation Circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. Document Number: 002-08252 Rev. *C Page 5 of 22 CY88154A 6. Block Diagram VDD 2 SEL1 8 Modulation rate setting SEL0 XOUT 1 CKOUT 7 REFOUT Modulation clock output 6 PLL block Reference clock 5 Reference clock output 4 XIN Rf = 1 MΩ 3 VSS 1 − M Phase compare Reference clock 1 − N Charge pump V/I conversion IDAC Modulation Clock output Loop filter 1 − L ICO Modulation logic Modulation rate setting/ Modulation enable setting CY88154A PLL block A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. Document Number: 002-08252 Rev. *C Page 6 of 22 CY88154A 7. Pin Setting SEL 0, SEL 1 Modulation Rate Setting Modulation Rate SEL1 SEL0 CY88154A-103 CY88154A-112, CY88154A-113 Down Spread Center Spread ± 0.5% ± 1.0% ± 1.5% No spread H L − 1.0% − 2.0% − 3.0% H H No spread L L L H Notes: ■ The modulation rate can be changed at the level of the pin. Spectrum does not spread when “H” level is set to SEL0 and SEL1 pins. The clock with low jitter can be obtained. ■ When changing the modulation rate setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock take the maximum value of “ Electrical Characteristics AC Characteristics Lock-Up time”. Center Spread Spectrum is spread (modulated) by centering on the input frequency. Modulation width 3.0% Radiation level −1.5% +1.5% Frequency Input frequency Modulation rate center spread example of Document Number: 002-08252 Rev. *C ± 1.5% Page 7 of 22 CY88154A Down Spread Spectrum is spread (modulated) below the input frequency. Modulation width 3.0% Radiation level −3.0% Frequency Frequency in modulation off Modulation width down spread example of Document Number: 002-08252 Rev. *C − 3.0% Page 8 of 22 CY88154A 8. Absolute Maximum Ratings Parameter Rating Symbol Power supply voltage* Max − 0.5 VSS − 0.5 VSS − 0.5 − 55 − 40 + 4.0 VDD + 0.5 VDD + 0.5 + 125 + 125 °C °C − 14 ⎯ + 14 mA VDD + 1.0 (tOVER ≤ 50 ns) V VSS − 1.0 (tUNDER ≤ 50 ns) ⎯ V VDD Input voltage* VI Output voltage* VO Storage temperature TST Operation junction temperature TJ Output current IO VIOVER VIUNDER Overshoot Undershoot Unit Min V V V * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VDD Input pin VSS tOVER ≤ 50 ns VIUNDER ≤ VSS − 1.0 V 9. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Pin Conditions Power supply voltage VDD VDD “H” level input voltage VIH “L” level input voltage VIL XIN, SEL0, SEL1 Input clock duty cycle tDCI Input clock through rate Operating temperature Value Unit Min Typ Max ⎯ 3.0 3.3 3.6 V ⎯ VDD × 0.80 ⎯ VDD + 0.3 V ⎯ VSS ⎯ VDD × 0.20 V XIN 16.6 MHz to 67 MHz 40 50 60 % SRIN XIN Input frequency 40 MHz to 67 MHz 0.0475 × fin − 1.75 ⎯ ⎯ V/ns Ta ⎯ ⎯ − 40 ⎯ + 85 °C Document Number: 002-08252 Rev. *C Page 9 of 22 CY88154A WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb 1.5 V XIN Input clock through rate (SRIN) VDD × 0.80 VDD × 0.20 XIN trin tfin Note : SRIN = (VDD × 0.80 − VDD × 0.20) /trin, SRIN = (VDD × 0.80 − VDD × 0.20) /tfin 10. Electrical Characteristics 10.1 DC Characteristics Parameter (Ta = −40 °C to Symbol Pin Conditions Power supply current ICC VDD Output voltage VOH CKOUT, REFOUT VOL Output impedance ZO CKOUT, REFOUT Input capacitance CIN XIN, SEL0, SEL1 Document Number: 002-08252 Rev. *C + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Value Unit Min Typ Max no load capacitance at 24 MHz output ⎯ 5.0 7.0 mA “H” level output IOH = − 3 mA VDD − 0.5 ⎯ VDD V “L” level output IOL = 3 mA VSS ⎯ 0.4 V 16.6 MHz to 67 MHz ⎯ 70 ⎯ Ω Ta = + 25 °C, VDD = VI = 0.0 V, f = 1 MHz ⎯ ⎯ 16 pF Page 10 of 22 CY88154A 10.2 AC Characteristics Parameter Oscillation frequency Input frequency Output frequency (Ta = −40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Value Symbol Pin Conditions fx XIN, XOUT Fundamental oscillation 16.6 3rd over-tone oscillation 40 CY88154A-103/113 16.6 CY88154A-112 33 CKOUT, REFOUT CY88154A-103/113 16.6 CY88154A-112 33 fin fOUT XIN Min Output slew rate SR CKOUT, REFOUT 0.4 V to 2.4 V load capacitance 15 pF 0.3 Output clock duty cycle tDCC CKOUT 1.5 V 40 tDCR REFOUT 1.5 V fMOD (nMOD) CKOUT Modulation frequency (Number of input clocks per modulation) Lock-Up time tLK CKOUT Cycle-cycle jitter tJC CKOUT Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit Max 40 MHz 48 40 MHz 67 40 MHz 67 2.0 V/ns 60 % tDCI − 10* ⎯ ⎯ tDCI + 10* % CY88154A-103/113 fin/2640 (2640) fin/2280 (2280) fin/1920 (1920) kHz (clks) CY88154A-112 fin/4400 (4400) fin/3800 (3800) fin/3200 (3200) ⎯ ⎯ ⎯ 2 5 ms ⎯ 100 ps-rms No load capacitance, Ta = +25 °C, VDD = 3.3 V * : Duty of the REFOUT output is guaranteed only for the following A and B because it depends on tDCI of input clock duty. A. Resonator : When resonator is connected with XIN and XOUT and oscillates normally. B. External clock input : The input level is Full - swing (VSS − VDD). fout (Output frequency) Modulation wave form t fMOD (Min) Clock count nMOD (Max) fMOD (Max) Clock count nMOD (Min) t CY88154A contains the modulation period to realize the efficient EMI reduction. The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) . Furthermore, the average value of fMOD equals the typical value of the electrical characteristics. Document Number: 002-08252 Rev. *C Page 11 of 22 CY88154A 11. Output Clock Duty Cycle (tDCC, tDCR = tb/ta) ta tb 1.5 V CKOUT, REFOUT 12. Input Frequency (fin = 1/tin) tin 0.8 VDD XIN 13. Output Slew Rate (SR) 2.4 V CKOUT, REFOUT 0.4 V tr tf Note : SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf Document Number: 002-08252 Rev. *C Page 12 of 22 CY88154A 14. Cycle-cycle Jitter (tJC = | tn − tn + 1 |) CKOUT tn tn+1 Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . Document Number: 002-08252 Rev. *C Page 13 of 22 CY88154A 15. Modulation Waveform ■ ±1.5% modulation rate, Example of center spread CKOUT output frequency + 1.5 % Frequency at modulation OFF Time − 1.5 % fMOD ■ −1.0% modulation rate, Example of down spread CKOUT output freFrequency at modulation OFF Time − 0.5 % − 1.0 % fMOD Document Number: 002-08252 Rev. *C Page 14 of 22 CY88154A 16. Lock-up Time VDD 3.0 V Internal clock stabilization wait time XIN Setting pin VIH SEL0, SEL1 tLK (lock-up time ) CKOUT If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. Document Number: 002-08252 Rev. *C Page 15 of 22 CY88154A 17. Oscillation Circuit The left side of figures below shows the connection example about general resonator. The oscillation circuit has the built-in feedback resistance (Rf) . The value of capacity (C1 and C2) is required adjusting to the most suitable value of an individual resonator. The right side of figures below shows the example of connecting for the 3rd over-tone resonator. The value of capacity (C1, C2 and C3) and inductance (L1) is needed adjusting to the most suitable value of an individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which use for the most suitable value. When an external clock is used (the resonator is not used) , input the clock to XIN pin and do not connect anything with XOUT. ■ When using a resonator CY88154A LSI Internal Rf (1 MΩ) Rf (1 MΩ) XIN Pin XOUT Pin XIN Pin XOUT Pin CY88154A LSI External L1 C2 C1 Normal resonator ■ C2 C1 C3 3rd over-tone resonator When using an external clock CY88154A LSI Internal Rf (1 MΩ) XIN Pin XOUT Pin CY88154A LSI External External clock OPEN Note : Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic. Document Number: 002-08252 Rev. *C Page 16 of 22 CY88154A 18. Interconnection Circuit Example SEL1 R2 1 8 7 2 CY88154A + R1 3 6 4 5 SEL0 C3 C4 ENS Xtal C1 C2 C1, C2 : Oscillation stabilization capacitance (refer to “ Oscillation Circuit”.) C3 : Capacitor of 10 μF or higher C4 : Capacitor about 0.01 μF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) R1, R2 : Impedance matching resistor for board pattern Document Number: 002-08252 Rev. *C Page 17 of 22 CY88154A 19. Example Characteristics The condition of the examples of the characteristic is shown as follows: Input frequency = 20 MHz (Output frequency = 20 MHz : Using CY88154A-113), Power - supply voltage = 3.3 V, None load capacity. Modulation rate = ± 1.5% (center spread) Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for − 6dB). CH B Spectrum 10 dB /REF 0 dBm No modulation −6.18 dBm Avg 4 modulation ± 1.5 % −26.03 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 20 MHZ Document Number: 002-08252 Rev. *C ATT 6 dB SWP 2.505 s SPAN 4 MHZ Page 18 of 22 CY88154A 20. Ordering Information Input/Output frequency Modulation type CY88154APNF-G-112-JNE1 33 MHz to 67 MHz Center CY88154APNF-G-113-JNE1 16.6 MHz to 40 MHz CY88154APNF-G-103-JNEFE1 16.6 MHz to 40 MHz Down CY88154APNF-G-112-JNEFE1 33 MHz to 67 MHz Center CY88154APNF-G-113-JNEFE1 16.6 MHz to 40 MHz CY88154APNF-G-103-JNERE1 16.6 MHz to 40 MHz Down CY88154APNF-G-112-JNERE1 33 MHz to 67 MHz Center CY88154APNF-G-113-JNERE1 16.6 MHz to 40 MHz Part number Package Remarks 8-pin plastic SOP (SOB008) Emboss taping (EF type) Emboss taping (ER type) Ordering Code Definitions CY88154APNF -G -103 -JN EF E1 Pb (lead)-free Package Tape and real: (EF: Forward, ER: Reverse) Tube (No Notation) Factory location: (JN: w/f=Japan, Assemble=China) Product line up Reliability Grade: G = 100 ppm Part number: CY88154APNF Document Number: 002-08252 Rev. *C Page 19 of 22 CY88154A 21. Package Dimension b 0.36 0.44 0.52 L 0.45 0.60 0.75 L 2 0.25 BSC 1.27 BSC. h 0.40 BSC. 002-15856 ** 11. JEDEC SPECIFICATION NO. REF : N/A Page 20 of 22 Document Number: 002-08252 Rev. *C 2  756 2  1 ( 2 1' , $17 /$$ 3 '5 , * /8 1 * ( , , 7+) $7 1 ( 2 6*& 1 , ( ( +'* 78$ /. 0 & 2 & ; 5($ 3 )