MB95F636HWQN-G-SNE1

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY95630H Series New 8FX 8-bit Microcontrollers The CY95630H Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral functions. Features ■ ■ ■ ❐ F2MC-8FX CPU core ❐ Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. Clock ❐ Selectable main clock source • Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) • External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) • Main CR clock (4 MHz 2%) • Main CR PLL clock - The main CR PLL clock frequency becomes 8 MHz 2% when the PLL multiplication rate is 2. - The main CR PLL clock frequency becomes 10 MHz 2% when the PLL multiplication rate is 2.5. - The main CR PLL clock frequency becomes 12 MHz 2% when the PLL multiplication rate is 3. - The main CR PLL clock frequency becomes 16 MHz 2% when the PLL multiplication rate is 4. ❐ Selectable subclock source • Suboscillation clock (32.768 kHz) • External clock (32.768 kHz) • Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) Timer ❐ 8/16-bit composite timer  2 channels ❐ 8/16-bit PPG  3 channels ❐ 16-bit PPG timer  1 channel (can work independently or together with the multi-pulse generator) ❐ 16-bit reload timer  1 channel (can work independently or together with the multi-pulse generator) ❐ Time-base timer  1 channel ❐ Watch prescaler  1 channel ■ UART/SIO  1 channel ❐ Full duplex double buffer ❐ Capable of clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer ■ I2C bus interface  1 channel ❐ Built-in wake-up function ■ Multi-pulse generator (MPG) (for DC motor control)  1 channel ❐ 16-bit reload timer  1 channel ❐ 16-bit PPG timer  1 channel ❐ Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function) ■ LIN-UART ❐ Full duplex double buffer Cypress Semiconductor Corporation Document Number: 002-04627 Rev. *G • Capable of clock asynchronous serial data transfer and clock synchronous serial data transfer ■ External interrupt  10 channels ❐ Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ❐ Can be used to wake up the device from different low power consumption (standby) modes ■ 8/10-bit A/D converter  8 channels ❐ 8-bit or 10-bit resolution can be selected. ■ Low power consumption (standby) modes ❐ There are four standby modes as follows: • Stop mode • Sleep mode • Watch mode • Time-base timer mode ❐ In standby mode, two further options can be selected: normal standby mode and deep standby mode. ■ I/O port ❐ CY95F632H/F633H/F634H/F636H (number of I/O ports: 28) • General-purpose I/O ports (CMOS I/O): 25 • General-purpose I/O ports (N-ch open drain): 3 ❐ CY95F632K/F633K/F634K/F636K (number of I/O ports: 29) • General-purpose I/O ports (CMOS I/O): 25 • General-purpose I/O ports (N-ch open drain): 4 ■ On-chip debug ❐ 1-wire serial control ❐ Serial writing supported (asynchronous mode) ■ Hardware/software watchdog timer ❐ Built-in hardware watchdog timer ❐ Built-in software watchdog timer ■ Power-on reset ❐ A power-on reset is generated when the power is switched on. ■ Low-voltage detection reset circuit (only available on CY95F632K/F633K/F634K/F636K) ❐ Built-in low-voltage detection function (The combination of detection voltage and release voltage can be selected from four options.) ■ Comparator ■ Clock supervisor counter ❐ Built-in clock supervisor counter ■ Dual operation Flash memory ❐ The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. ■ Flash memory security function ❐ Protects the content of the Flash memory. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 10, 2019 CY95630H Series Contents Features............................................................................. 1 1. Product Line-up ............................................................ 3 2. Packages And Corresponding Products.................... 5 3. Differences Among Products And Notes On Product Selection ............................................................. 5 4. Pin Assignment ............................................................ 6 5. Pin Functions................................................................ 8 6. I/O Circuit Type ........................................................... 12 7. Handling Precautions................................................. 7.1 Precautions for Product Design........................... 7.2 Precautions for Package Mounting ..................... 7.3 Precautions for Use Environment........................ 14 14 15 17 15. I/O Ports..................................................................... 15.1 Port 0................................................................. 15.2 Port 1................................................................. 15.3 Port 6................................................................. 15.4 Port F................................................................. 15.5 Port G ................................................................ 30 31 39 46 51 53 16. Interrupt Source Table ............................................. 56 17. Pin States In Each Mode .......................................... 57 18. Electrical Characteristics......................................... 18.1 Absolute Maximum Ratings............................... 18.2 Recommended Operating Conditions ............... 18.3 DC Characteristics ............................................ 18.4 AC Characteristics............................................. 18.5 A/D Converter................................................... 18.6 Flash Memory Program/Erase Characteristics.. 61 61 63 64 67 85 89 8. Notes On Device Handling......................................... 17 19. Sample Characteristics............................................ 90 9. Pin Connection ........................................................... 18 20. Mask Options ............................................................ 97 10. Block Diagram .......................................................... 19 21. Ordering Information................................................ 97 11. CPU Core................................................................... 20 22. Package Dimension.................................................. 98 12. Memory Space .......................................................... 21 23. Major Changes In This Edition .............................. 101 Document History Page ............................................... 101 Sales, Solutions, and Legal Information .................... 102 13. Areas For Specific Applications ............................. 23 14. I/O Map....................................................................... 24 Document Number: 002-04627 Rev. *G Page 2 of 103 CY95630H Series 1. Product Line-up Part number CY95F632H CY95F633H CY95F634H CY95F636H CY95F632K CY95F633K CY95F634K CY95F636K Parameter Type Clock supervisor counter Flash memory product It supervises the main clock oscillation and the subclock oscillation. Flash memory capacity RAM capacity 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte 256 bytes 512 bytes 1024 bytes 1024 bytes 256 bytes 512 bytes 1024 bytes 1024 bytes Power-on reset Yes Low-voltage detection reset Reset input • • • CPU functions • • • Generalpurpose I/O 8 Kbyte No Yes Dedicated Selected through software Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time • I/O port • CMOS I/O • N-ch open drain : 136 : 8 bits : 1 to 3 bytes : 1, 8 and 16 bits : 61.5 ns (machine clock frequency = 16.25 MHz) : 0.6 µs (machine clock frequency = 16.25 MHz) : 28 : 25 :3 • I/O port • CMOS I/O • N-ch open drain : 29 : 25 :4 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ software Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-CR clock can be used as the source clock of the software watchdog timer. Wild register It can be used to replace 3 bytes of data. LIN-UART • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. • Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled. • The LIN function can be used as a LIN master or a LIN slave. 8/10-bit A/D converter 8 channels 8-bit or 10-bit resolution can be selected. 2 channels • The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. 8/16-bit • It has the following functions: interval timer function, PWC function, PWM function and input composite timer capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. Document Number: 002-04627 Rev. *G Page 3 of 103 CY95630H Series Part number CY95F632H CY95F633H CY95F634H CY95F636H CY95F632K CY95F633K CY95F634K CY95F636K Parameter External interrupt On-chip debug 10 channels • Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.) • It can be used to wake up the device from different standby modes. • 1-wire serial control • It supports serial writing (asynchronous mode). 1 channel UART/SIO • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer are enabled. 1 channel I2C bus interface • Master/slave transmission and reception • It has the following functions: bus error function, arbitration function, transfer direction detection function, wake-up function, and functions of generating and detecting repeated START conditions. 3 channels 8/16-bit PPG • Each channel can be used as an “8-bit timer  2 channels” or a “16-bit timer  1 channel”. • The counter operating clock can be selected from eight clock sources. 1 channel 16-bit PPG timer • • • • PWM mode and one-shot mode are available to use. The counter operating clock can be selected from eight clock sources. It supports external trigger start. It can work independently or together with the multi-pulse generator. 1 channel 16-bit reload timer Multi-pulse generator (for DC motor control) • • • • • Two clock modes and two counter operating modes are available to use. It can output square wave. Count clock: it can be selected from internal clocks (seven types) and external clocks. Two counter operating modes: reload mode and one-shot mode It can work independently or together with the multi-pulse generator. • • • • 16-bit PPG timer: 1 channel 16-bit reload timer operations: toggle output, one-shot output Event counter: 1 channel Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function) Watch prescaler Eight different time intervals can be selected. Comparator 1 channel Document Number: 002-04627 Rev. *G Page 4 of 103 CY95630H Series Part number CY95F632H CY95F633H CY95F634H CY95F636H CY95F632K CY95F633K CY95F634K CY95F636K Parameter Flash memory • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years There are four standby modes as follows: • Stop mode • Sleep mode Standby mode • Watch mode • Time-base timer mode In standby mode, two further options can be selected: normal standby mode and deep standby mode. LQB032 PDS032 WNP032 Package 2. Packages And Corresponding Products Part number CY95F632H CY95F633H CY95F634H CY95F636H CY95F632K CY95F633K CY95F634K CY95F636K Package LQB032         PDS032         WNP032         : Available 3. Differences Among Products And Notes On Product Selection • Current consumption When using the on-chip debug function, take account of the current consumption of Flash memory program/erase. For details of current consumption, see “Electrical Characteristics”. • Package For details of information on each package, see “Packages And Corresponding Products” and “Package Dimension”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of operating voltage, see “Electrical Characteristics”. • On-chip debug function Document Number: 002-04627 Rev. *G Page 5 of 103 CY95630H Series The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection method, refer to “CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New 8FX CY95630H Series Hardware Manual”. 32 31 30 29 28 27 26 25 Vss PF1/X1 PF0/X0 PF2/RST P17/TO1/SNI0 P16/UI0/PPG21 P15/UO0/PPG20 P14/UCK0/PPG01 4. Pin Assignment P65/PPG11/OPT3 P64/EC1/PPG10/OPT2 7 8 Document Number: 002-04627 Rev. *G LQB032 16 5 6 P03/INT03/AN03/SOT P67/PPG21/TRG1/OPT5 P66/PPG20/PPG1/OPT4 (TOP VIEW) LQFP32 13 14 15 3 4 P00/INT00/AN00/CMP0_P P01/INT01/AN01/CMP0_N P02/INT02/AN02/SCK Vcc C 9 10 11 12 1 2 P63/TO11/PPG01/OPT1 P62/TO10/PPG00/OPT0 P61/INT09/SCL/TI1 P60/INT08/SDA/DTTI PG2/X1A/SNI2 PG1/X0A/SNI1 24 23 22 21 P13/PPG00 P12/DBG/EC0 P11/PPG11 P10/PPG10/CMP0_O 20 19 18 17 P07/INT07/AN07 P06/INT06/AN06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 Page 6 of 103 CY95630H Series PF2/RST PF0/X0 1 2 32 31 P17/TO1/SNI0 P16/UI0/PPG21 PF1/X1 Vss 3 4 30 29 P15/UO0/PPG20 P14/UCK0/PPG01 PG2/X1A/SNI2 PG1/X0A/SNI1 5 6 28 27 P13/PPG00 P12/DBG/EC0 Vcc C P67/PPG21/TRG1/OPT5 P66/PPG20/PPG1/OPT4 P65/PPG11/OPT3 P64/EC1/PPG10/OPT2 P63/TO11/PPG01/OPT1 P62/TO10/PPG00/OPT0 P61/INT09/SCL/TI1 7 26 P11/PPG11 8 25 P10/PPG10/CMP0_O 9 10 11 12 13 14 15 24 P07/INT07/AN07 23 P06/INT06/AN06/TO01 22 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P60/INT08/SDA/DTTI 16 21 20 19 18 17 (TOP VIEW) SH-DIP32 P02/INT02/AN02/SCK P01/INT01/AN01/CMP0_N P00/INT00/AN00/CMP0_P 32 31 30 29 28 27 26 25 Vss PF1/X1 PF0/X0 PF2/RST P17/TO1/SNI0 P16/UI0/PPG21 P15/UO0/PPG20 P14/UCK0/PPG01 PDS032 P67/PPG21/TRG1/OPT5 P66/PPG20/PPG1/OPT4 5 6 P65/PPG11/OPT3 P64/EC1/PPG10/OPT2 7 8 Document Number: 002-04627 Rev. *G (TOP VIEW) QFN32 WNP032 16 3 4 P03/INT03/AN03/SOT Vcc C 9 10 11 12 13 14 15 1 2 P63/TO11/PPG01/OPT1 P62/TO10/PPG00/OPT0 P61/INT09/SCL/TI1 P60/INT08/SDA/DTTI P00/INT00/AN00/CMP0_P P01/INT01/AN01/CMP0_N P02/INT02/AN02/SCK PG2/X1A/SNI2 PG1/X0A/SNI1 24 23 22 21 P13/PPG00 P12/DBG/EC0 P11/PPG11 P10/PPG10/CMP0_O 20 19 18 17 P07/INT07/AN07 P06/INT06/AN06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 Page 7 of 103 CY95630H Series 5. Pin Functions Pin no. I/O circuit Pin name LQFP32* , SH-DIP32*3 type*4 QFN32*2 1 PG2 2 5 C C — — PPG21 TRG1 D —  PPG20 PPG1 Hysteresis CMOS —  Hysteresis CMOS —  D 8/16-bit composite timer ch. 1 clock input pin Hysteresis CMOS 8/16-bit PPG ch. 1 output pin —  D Document Number: 002-04627 Rev. *G 16-bit PPG timer ch. 1 output pin 8/16-bit PPG ch. 1 output pin MPG waveform sequencer output pin General-purpose I/O port High-current pin P64 OPT2 8/16-bit PPG ch. 2 output pin General-purpose I/O port High-current pin OPT3 PPG10 16-bit PPG timer ch. 1 trigger input Hysteresis CMOS pin MPG waveform sequencer output pin P65 EC1 — — General-purpose I/O port High-current pin OPT4 PPG11 Decoupling capacitor connection pin — — MPG waveform sequencer output pin P66 12 — — Power supply pin 8/16-bit PPG ch. 2 output pin OPT5 8 — — Trigger input pin for the position detection function of the MPG waveform sequencer General-purpose I/O port High-current pin P67 11  Subclock input oscillation pin 8 7 — X0A 4 10 Hysteresis CMOS General-purpose I/O port VCC 6  PG1 7 9 — SNI2 SNI1 5 Hysteresis CMOS Trigger input pin for the position detection function of the MPG waveform sequencer 3 Output OD*5 PU*6 Subclock I/O oscillation pin C 6 Input General-purpose I/O port X1A 1 I/O type Function D MPG waveform sequencer output pin Page 8 of 103 CY95630H Series Pin no. I/O Pin name circuit LQFP32* , SH-DIP32*3 type*4 QFN32*2 1 13 TO11 D PPG01 TO10 D 13 16 17 18 I2C bus interface ch. 0 clock I/O pin TI1 16-bit reload timer ch. 1 input pin P60 General-purpose I/O port INT08 External interrupt input pin SDA I I2C bus interface ch. 0 data I/O pin DTTI MPG waveform sequencer input pin P00 General-purpose I/O port INT00 External interrupt input pin AN00 E 8/10-bit A/D converter analog input pin General-purpose I/O port INT01 External interrupt input pin CMP0_N Document Number: 002-04627 Rev. *G —  CMOS CMOS  — CMOS CMOS  — Hysteresis/ CMOS analog —  Hysteresis/ CMOS analog —  Comparator non-inverting analog input (positive input) pin P01 AN01 Hysteresis CMOS External interrupt input pin I CMP0_P 14 8/16-bit composite timer ch. 1 output pin General-purpose I/O port INT09 12  MPG waveform sequencer output pin P61 SCL — 8/16-bit PPG ch. 0 output pin OPT0 15 Hysteresis CMOS General-purpose I/O port High-current pin PPG00 11 8/16-bit composite timer ch. 1 output pin MPG waveform sequencer output pin P62 14 Output OD*5 PU*6 8/16-bit PPG ch. 0 output pin OPT1 10 Input General-purpose I/O port High-current pin P63 9 I/O type Function E 8/10-bit A/D converter analog input pin Comparator inverting analog input (negative input) pin Page 9 of 103 CY95630H Series Pin no. I/O Pin name circuit LQFP32* , SH-DIP32*3 type*4 QFN32*2 1 P02 19 AN02 External interrupt input pin E 17 18 20 21 22 LIN-UART clock I/O pin P03 General-purpose I/O port AN03 External interrupt input pin E 23 LIN-UART data output pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 F LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port INT05 External interrupt input pin AN05 E General-purpose I/O port INT06 External interrupt input pin E INT07 PPG10 CMP0_O Document Number: 002-04627 Rev. *G —  Hysteresis/ CMOS analog —  CMOS —  Hysteresis/ CMOS analog —  Hysteresis/ CMOS analog —  Hysteresis/ CMOS analog —  Hysteresis CMOS —  CMOS/ analog 8/10-bit A/D converter analog input pin General-purpose I/O port E P10 25 Hysteresis/ CMOS analog 8/16-bit composite timer ch. 0 output pin AN07 21 8/10-bit A/D converter analog input pin P06 AN06 Output OD*5 PU*6 8/16-bit composite timer ch. 0 output pin P07 24 8/10-bit A/D converter analog input pin SIN TO01 20 8/10-bit A/D converter analog input pin SOT TO00 19 8/10-bit A/D converter analog input pin SCK INT03 16 Input General-purpose I/O port INT02 15 I/O type Function External interrupt input pin 8/10-bit A/D converter analog input pin General-purpose I/O port G 8/16-bit PPG ch. 1 output pin Comparator digital output pin Page 10 of 103 CY95630H Series Pin no. I/O Pin name circuit LQFP32* , SH-DIP32*3 type*4 QFN32*2 1 22 26 P11 PPG11 G P12 23 27 DBG 28 P13 PPG00 H G P14 25 29 UCK0 G UO0 G UI0 1 30 2 31 3 32 4  — Hysteresis CMOS —  Hysteresis CMOS —  UART/SIO ch. 0 data output pin Hysteresis CMOS —  CMOS —  Hysteresis CMOS —  Hysteresis CMOS  — Hysteresis CMOS — — Hysteresis CMOS — — — — 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port 8/16-bit PPG ch. 0 output pin UART/SIO ch. 0 clock I/O pin J UART/SIO ch. 0 data input pin General-purpose I/O port TO1 16-bit reload timer ch. 1 output pin G SNI0 Trigger input pin for the position detection function of the MPG waveform sequencer PF2 General-purpose I/O port RST PF0 X0 PF1 X1 VSS : Available *1: LQB032 *2: WNP032 *3: PDS032 Document Number: 002-04627 Rev. *G CMOS 8/16-bit PPG ch. 2 output pin P17 32 29 Hysteresis CMOS DBG input pin General-purpose I/O port PPG21 28  8/16-bit PPG ch. 2 output pin P16 31 — General-purpose I/O port PPG20 27 Hysteresis CMOS 8/16-bit PPG ch. 1 output pin 8/16-bit PPG ch. 0 output pin P15 30 Output OD*5 PU*6 General-purpose I/O port PPG01 26 General-purpose I/O port Input General-purpose I/O port EC0 24 I/O type Function A B B — Reset pin Dedicated reset pin on CY95F632H/F633H/F634H/ F636H General-purpose I/O port Main clock input oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) — — *4: For the I/O circuit types, see “I/O Circuit Type”. *5: N-ch open drain *6: Pull-up Page 11 of 103 CY95630H Series 6. I/O Circuit Type Type Circuit A Remarks Reset input / Hysteresis input Reset output / Digital output • N-ch open drain output • Hysteresis input • Reset output N-ch B P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input • Oscillation circuit • High-speed side Feedback resistance: approx. 1 M • CMOS output • Hysteresis input Clock input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input C Port select R Pull-up control P-ch P-ch • Oscillation circuit • Low-speed side Feedback resistance: approx. 5 M Digital output N-ch Digital output Standby control • CMOS output • Hysteresis input • Pull-up control Hysteresis input Clock input X1A X0A Standby control / Port select Port select R Pull-up control Digital output P-ch Digital output N-ch Digital output Standby control Hysteresis input Document Number: 002-04627 Rev. *G Page 12 of 103 CY95630H Series Type Circuit Remarks D Pull-up control R P-ch Digital output P-ch • • • • CMOS output Hysteresis input Pull-up control High current output • • • • CMOS output Hysteresis input Pull-up control Analog input • • • • CMOS output CMOS input Pull-up control Analog input Digital output N-ch Standby control Hysteresis input E Pull-up control R P-ch Digital output P-ch Digital output N-ch Analog input A/D control Standby control Hysteresis input F Pull-up control R P-ch Digital output P-ch Digital output N-ch Analog input A/D control Standby control CMOS input G Pull-up control R P-ch • CMOS output • Hysteresis input • Pull-up control Digital output P-ch Digital output N-ch Standby control Hysteresis input H Standby control • N-ch open drain output • Hysteresis input Hysteresis input Digital output N-ch Document Number: 002-04627 Rev. *G Page 13 of 103 CY95630H Series Type Circuit Remarks I Digital output • N-ch open drain output • CMOS input N-ch Standby control CMOS input J Pull-up control R P-ch • CMOS output • CMOS input • Pull-up control Digital output P-ch Digital output N-ch Standby control CMOS input 7. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 7.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. Document Number: 002-04627 Rev. *G Page 14 of 103 CY95630H Series (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence.  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 7.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually Document Number: 002-04627 Rev. *G Page 15 of 103 CY95630H Series causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-04627 Rev. *G Page 16 of 103 CY95630H Series 7.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. 8. Notes On Device Handling • Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “18.1 Absolute Maximum Ratings” of “Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. Document Number: 002-04627 Rev. *G Page 17 of 103 CY95630H Series 9. Pin Connection • Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latchups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. • DBG pin Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. • RST pin Connect the RST pin to an external pull-up resistor of 2 k or above. To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general-purpose I/O function can be selected by the RSTEN bit in the SYSC register. • C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG/RST/C pins connection diagram DBG C RST Cs • Note on serial communication In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed Document Number: 002-04627 Rev. *G Page 18 of 103 CY95630H Series circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. If an error is detected, retransmit the data. 10. Block Diagram F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Dual operation Flash with security function (36/20/12/8 Kbyte) PF0/X0*2 PF1/X1*2 (PG1/X0A*2) Oscillator circuit CR oscillator (PG2/X1A*2) RAM (1024/512/256 bytes) Clock control (P05/TO00) 8/16-bit composite timer ch. 0 (P12*1/DBG) On-chip debug (P06/TO01) P12/EC0, (P04/EC0) Wild register 8/10-bit A/D converter P02/INT02 to P07/INT07 External interrupt P00/INT00, P01/INT01, P60/INT08, P61/INT09 External interrupt C Interrupt controller (P00/AN00 to P07/AN07) (P62*3/TO10) (P03/SOT) LIN-UART Internal bus (P02/SCK) 8/16-bit composite timer ch. 1 (P63*3/TO11) (P64*3/EC1) MPG 16-bit reload timer (P04/SIN) (P61/TI1) (P17/TO1) P62*3/OPT0 to P67*3/OPT5 Waveform sequencer (P14/UCK0) (P15/UO0) UART/SIO P17/SNI0, PG1/SNI1, PG2/SNI2 (P60/DTTI) (P61/TI1) (P16/UI0) (P60*1/SDA) (P61*1/SCL) (P62*3/PPG00), P13/PPG00 (P63*3/PPG01), P14/PPG01 16-bit PPG timer I2C bus interface ch. 0 8/16-bit PPG ch. 1 8/16-bit PPG ch. 0 (P67*3/TRG1) (P66*3/PPG1) P10/PPG10, (P64*3/PPG10) P11/PPG11, (P65*3/PPG11) (P00/CMP0_P) (P66*3/PPG20), P15/PPG20 (P67*3/PPG21), P16/PPG21 8/16-bit PPG ch. 2 Comparator (P01/CMP0_N) (P10/CMP0_O) Port Port Vcc Vss *1: P12, P60, P61 and PF2 are N-ch open drain pins. *2: Software select *3: P62 to P67 are high-current pins. Note: Pins in parentheses indicate that those pins are shared among different peripheral functions. Document Number: 002-04627 Rev. *G Page 19 of 103 CY95630H Series 11. CPU Core • Memory space The memory space of the CY95630H Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as generalpurpose registers and a vector table. The memory maps of the CY95630H Series are shown below. • Memory maps MB95F632H/F632K 0x0000 0x0080 0x0090 0x0100 0x0190 I/O area Access prohibited RAM 256 bytes Registers MB95F633H/F633K 0x0000 0x0080 0x0090 0x0100 0x0200 I/O area Access prohibited RAM 512 bytes Registers MB95F634H/F634K 0x0000 0x0080 0x0090 0x0100 0x0200 I/O area Access prohibited RAM 1024 bytes Registers MB95F636H/F636K 0x0000 0x0080 0x0090 0x0100 0x0200 I/O area Access prohibited RAM 1024 bytes Registers 0x0290 Access prohibited Access prohibited 0x0490 0x0490 Access prohibited 0x0F80 0x0F80 0x0F80 Flash memory 4 Kbyte Flash memory 4 Kbyte Flash memory 4 Kbyte Flash memory 4 Kbyte 0x2000 0x2000 0x2000 Extended I/O area 0x1000 0x1000 0x1000 0x2000 0x0F80 Extended I/O area Extended I/O area Extended I/O area 0x1000 Access prohibited Access prohibited Access prohibited 0x8000 Access prohibited Access prohibited 0xC000 Flash memory 32 Kbyte Flash memory 16 Kbyte 0xE000 Flash memory 8 Kbyte 0xF000 Flash memory 4 Kbyte 0xFFFF 0xFFFF Document Number: 002-04627 Rev. *G 0xFFFF 0xFFFF Page 20 of 103 CY95630H Series 12. Memory Space The memory space of the CY95630H Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table. • I/O area (addresses: 0x0000 to 0x007F) • This area contains the control registers and data registers for built-in peripheral functions. • As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also be accessed at high-speed by using direct addressing instructions. • Extended I/O area (addresses: 0x0F80 to 0x0FFF) • This area contains the control registers and data registers for built-in peripheral functions. • As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory. • Data area • Static RAM is incorporated in the data area as the internal data area. • The internal RAM size varies according to product. • The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions. • In CY95F636H/F636K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • In CY95F634H/F634K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • In CY95F633H/F633K, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • In CY95F632H/F632K, the area from 0x0090 to 0x018F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • In CY95F633H/F633K/F634H/F634K/F636H/F636K, the area from 0x0100 to 0x01FF can be used as a generalpurpose register area. • In CY95F632H/F632K, the area from 0x0100 to 0x018F can be used as a general-purpose register area. • Program area • The Flash memory is incorporated in the program area as the internal program area. • The Flash memory size varies according to product. • The area from 0xFFC0 to 0xFFFF is used as the vector table. • The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. Document Number: 002-04627 Rev. *G Page 21 of 103 CY95630H Series • Memory space map 0x0000 0x0080 0x0090 0x0100 I/O area Direct addressing area Access prohibited Registers (General-purpose register area) Extended direct addressing area 0x0200 Data area 0x047F 0x048F 0x0490 Access prohibited 0x0F80 0x0FFF 0x1000 Extended I/O area Program area 0xFFC0 0xFFFF Document Number: 002-04627 Rev. *G Vector table area Page 22 of 103 CY95630H Series 13. Areas For Specific Applications The general-purpose register area and vector table area are used for the specific applications. • General-purpose register area (Addresses: 0x0100 to 0x01FF*1) • This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc. • As this area forms part of the RAM area, it can also be used as conventional RAM. • When the area is used as general-purpose registers, general-purpose register addressing enables high-speed access with short instructions. • Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF) • The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX CY95630H Series Hardware Manual”. • Vector table area (Addresses: 0xFFC0 to 0xFFFF) • This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets. • The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set to an address in the vector table in the form of data. “Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets. For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS” and “A.2 Special Instruction ■ Special Instruction ● CALLV #vct” in “New 8FX CY95630H Series Hardware Manual”. • Direct bank pointer and access area Direct bank pointer (DP[2:0]) Operand-specified dir Access area 0bXXX (It does not affect mapping.) 0x0000 to 0x007F 0x0000 to 0x007F 0b000 (Initial value) 0x0090 to 0x00FF 0x0090 to 0x00FF 0b001 0x0100 to 0x017F 0b010 0x0180 to 0x01FF*1 0b011 0x0200 to 0x027F 0b100 0x0080 to 0x00FF 0x0280 to 0x02FF*2 0b101 0x0300 to 0x037F 0b110 0x0380 to 0x03FF 0b111 0x0400 to 0x047F *1: Due to the memory size limit, the available access area is up to “0x018F” in CY95F632H/F632K. *2: Due to the memory size limit, the available access area is up to “0x028F” in CY95F633H/F633K. Document Number: 002-04627 Rev. *G Page 23 of 103 CY95630H Series 14. I/O Map Address Register abbreviation 0x0000 PDR0 0x0001 Register name R/W Initial value Port 0 data register R/W 0b00000000 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E STBC2 Standby control register 2 R/W 0b00000000 0x000F to 0x0015 — — — 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 to 0x0027 — — — 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 0x002A PDRG Port G data register R/W 0b00000000 0x002B DDRG Port G direction register R/W 0b00000000 0x002C PUL0 Port 0 pull-up register R/W 0b00000000 0x002D PUL1 Port 1 pull-up register R/W 0b00000000 0x002E to 0x0032 — — — 0x0033 PUL6 R/W 0b00000000 0x0034 — — — 0x0035 PULG Port G pull-up register R/W 0b00000000 0x0036 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) Port 6 pull-up register (Disabled) Document Number: 002-04627 Rev. *G Page 24 of 103 CY95630H Series Address Register abbreviation 0x0037 T00CR1 0x0038 R/W Initial value 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000 0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000 0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000 0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000 0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000 0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000 0x003E PC21 8/16-bit PPG timer 21 control register R/W 0b00000000 0x003F PC20 8/16-bit PPG timer 20 control register R/W 0b00000000 0x0040 TMCSRH1 16-bit reload timer control status register (upper) R/W 0b00000000 0x0041 TMCSRL1 16-bit reload timer control status register (lower) R/W 0b00000000 0x0042 CMR0C Comparator control register R/W 0b00000101 0x0043 — — — 0x0044 PCNTH1 16-bit PPG status control register (upper) R/W 0b00000000 0x0045 PCNTL1 16-bit PPG status control register (lower) R/W 0b00000000 0x0046, 0x0047 — — — 0x0048 EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000 0x0049 EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000 0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000 0x004C EIC01 External interrupt circuit control register ch. 8/ch. 9 R/W 0b00000000 0x004D — — — 0x004E LVDR R/W 0b00000000 0x004F — — — 0x0050 SCR LIN-UART serial control register R/W 0b00000000 0x0051 SMR LIN-UART serial mode register R/W 0b00000000 0x0052 SSR LIN-UART serial status register R/W 0b00001000 RDR LIN-UART receive data register TDR LIN-UART transmit data register R/W 0b00000000 0x0053 Register name (Disabled) (Disabled) (Disabled) LVD reset voltage selection ID register (Disabled) 0x0054 ESCR LIN-UART extended status control register R/W 0b00000100 0x0055 ECCR LIN-UART extended communication control register R/W 0b000000XX 0x0056 SMC10 UART/SIO serial mode control register 1 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode control register 2 R/W 0b00100000 0x0058 SSR0 UART/SIO serial status and data register R/W 0b00000001 0x0059 TDR0 UART/SIO serial output data register R/W 0b00000000 Document Number: 002-04627 Rev. *G Page 25 of 103 CY95630H Series Address Register abbreviation 0x005A RDR0 0x005B to 0x005F — 0x0060 IBCR00 0x0061 IBCR10 0x0062 Register name R/W Initial value R 0b00000000 — — I2C bus control register 0 ch. 0 R/W 0b00000000 I C bus control register 1 ch. 0 R/W 0b00000000 IBSR0 I C bus status register ch. 0 R/W 0b00000000 0x0063 IDDR0 I C data register ch. 0 R/W 0b00000000 0x0064 IAAR0 I C address register ch. 0 R/W 0b00000000 0x0065 ICCR0 I C clock control register ch. 0 R/W 0b00000000 0x0066 OPCUR 16-bit MPG output control register (upper) R/W 0b00000000 0x0067 OPCLR 16-bit MPG output control register (lower) R/W 0b00000000 0x0068 IPCUR 16-bit MPG input control register (upper) R/W 0b00000000 0x0069 IPCLR 16-bit MPG input control register (lower) R/W 0b00000000 0x006A NCCR 16-bit MPG noise cancellation control register R/W 0b00000000 0x006B TCSR 16-bit MPG timer control status register R/W 0b00000000 0x006C ADC1 8/10-bit A/D converter control register 1 R/W 0b00000000 0x006D ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/10-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/10-bit A/D converter data register (lower) R/W 0b00000000 0x0070 — — — 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — — — UART/SIO serial input data register (Disabled) 2 2 2 2 2 (Disabled) Mirror of register bank pointer (RP) and direct bank pointer (DP) Document Number: 002-04627 Rev. *G (Disabled) Page 26 of 103 CY95630H Series Address Register abbreviation 0x0F80 WRARH0 0x0F81 Register name R/W Initial value Wild register address setting register (upper) ch. 0 R/W 0b00000000 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000 0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000 0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000 0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000 0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 0b00000000 0x0F9C PPS01 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111 0x0F9D PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111 0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111 0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111 0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111 0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111 0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111 0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111 0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000 0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000 0x0FA6 PPS21 8/16-bit PPG21 cycle setting buffer register R/W 0b11111111 0x0FA7 PPS20 8/16-bit PPG20 cycle setting buffer register R/W 0b11111111 (Disabled) Document Number: 002-04627 Rev. *G Page 27 of 103 CY95630H Series Address 0x0FA8 Register abbreviation Register name TMRH1 16-bit reload timer timer register (upper) TMRLRH1 16-bit reload timer reload register (upper) R/W Initial value R/W 0b00000000 R/W 0b00000000 TMRL1 16-bit reload timer timer register (lower) TMRLRL1 16-bit reload timer reload register (lower) 0x0FAA PDS21 8/16-bit PPG21 duty setting buffer register R/W 0b11111111 0x0FAB PDS20 8/16-bit PPG20 duty setting buffer register R/W 0b11111111 0x0FAC to 0x0FAF — — — 0x0FB0 PDCRH1 16-bit PPG downcounter register (upper) R 0b00000000 0x0FB1 PDCRL1 16-bit PPG downcounter register (lower) R 0b00000000 0x0FB2 PCSRH1 16-bit PPG cycle setting buffer register (upper) R/W 0b11111111 0x0FB3 PCSRL1 16-bit PPG cycle setting buffer register (lower) R/W 0b11111111 0x0FB4 PDUTH1 16-bit PPG duty setting buffer register (upper) R/W 0b11111111 0x0FB5 PDUTL1 16-bit PPG duty setting buffer register (lower) R/W 0b11111111 0x0FB6 to 0x0FBB — — — 0x0FBC BGR1 LIN-UART baud rate generator register 1 R/W 0b00000000 0x0FBD BGR0 LIN-UART baud rate generator register 0 R/W 0b00000000 0x0FBE PSSR0 UART/SIO dedicated baud rate generator prescaler select register R/W 0b00000000 0x0FBF BRSR0 UART/SIO dedicated baud rate generator baud rate setting register R/W 0b00000000 0x0FC0 to 0x0FC2 — — — 0x0FC3 AIDRL A/D input disable register (lower) R/W 0b00000000 0x0FC4 OPDBRH0 16-bit MPG output data buffer register (upper) ch. 0 R/W 0b00000000 0x0FC5 OPDBRL0 16-bit MPG output data buffer register (lower) ch. 0 R/W 0b00000000 0x0FC6 OPDBRH1 16-bit MPG output data buffer register (upper) ch. 1 R/W 0b00000000 0x0FC7 OPDBRL1 16-bit MPG output data buffer register (lower) ch. 1 R/W 0b00000000 0x0FC8 OPDBRH2 16-bit MPG output data buffer register (upper) ch. 2 R/W 0b00000000 0x0FC9 OPDBRL2 16-bit MPG output data buffer register (lower) ch. 2 R/W 0b00000000 0x0FCA OPDBRH3 16-bit MPG output data buffer register (upper) ch. 3 R/W 0b00000000 0x0FCB OPDBRL3 16-bit MPG output data buffer register (lower) ch. 3 R/W 0b00000000 0x0FCC OPDBRH4 16-bit MPG output data buffer register (upper) ch. 4 R/W 0b00000000 0x0FCD OPDBRL4 16-bit MPG output data buffer register (lower) ch. 4 R/W 0b00000000 0x0FA9 (Disabled) (Disabled) (Disabled) Document Number: 002-04627 Rev. *G Page 28 of 103 CY95630H Series Address Register abbreviation 0x0FCE OPDBRH5 0x0FCF Register name R/W Initial value 16-bit MPG output data buffer register (upper) ch. 5 R/W 0b00000000 OPDBRL5 16-bit MPG output data buffer register (lower) ch. 5 R/W 0b00000000 0x0FD0 OPDBRH6 16-bit MPG output data buffer register (upper) ch. 6 R/W 0b00000000 0x0FD1 OPDBRL6 16-bit MPG output data buffer register (lower) ch. 6 R/W 0b00000000 0x0FD2 OPDBRH7 16-bit MPG output data buffer register (upper) ch. 7 R/W 0b00000000 0x0FD3 OPDBRL7 16-bit MPG output data buffer register (lower) ch. 7 R/W 0b00000000 0x0FD4 OPDBRH8 16-bit MPG output data buffer register (upper) ch. 8 R/W 0b00000000 0x0FD5 OPDBRL8 16-bit MPG output data buffer register (lower) ch. 8 R/W 0b00000000 0x0FD6 OPDBRH9 16-bit MPG output data buffer register (upper) ch. 9 R/W 0b00000000 0x0FD7 OPDBRL9 16-bit MPG output data buffer register (lower) ch. 9 R/W 0b00000000 0x0FD8 OPDBRHA 16-bit MPG output data buffer register (upper) ch. A R/W 0b00000000 0x0FD9 OPDBRLA 16-bit MPG output data buffer register (lower) ch. A R/W 0b00000000 0x0FDA OPDBRHB 16-bit MPG output data buffer register (upper) ch. B R/W 0b00000000 0x0FDB OPDBRLB 16-bit MPG output data buffer register (lower) ch. B R/W 0b00000000 0x0FDC OPDUR 16-bit MPG output data register (upper) R 0b0000XXXX 0x0FDD OPDLR 16-bit MPG output data register (lower) R 0bXXXXXXXX 0x0FDE CPCUR 16-bit MPG compare clear register (upper) R/W 0bXXXXXXXX 0x0FDF CPCLR 16-bit MPG compare clear register (lower) R/W 0bXXXXXXXX 0x0FE0, 0x0FE1 — — — 0x0FE2 TMBUR 16-bit MPG timer buffer register (upper) R 0bXXXXXXXX 0x0FE3 TMBLR 16-bit MPG timer buffer register (lower) R 0bXXXXXXXX 0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 — — — 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b11000011 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX 0x0FEC WDTL Watchdog timer selection ID register (lower) R 0bXXXXXXXX 0x0FED, 0x0FEE — — — 0x0FEF WICR R/W 0b01000000 0x0FF0 to 0x0FFF — — — (Disabled) (Disabled) (Disabled) Interrupt pin selection circuit control register Document Number: 002-04627 Rev. *G (Disabled) Page 29 of 103 CY95630H Series • R/W access symbols R/W : Readable/Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 15. I/O Ports • List of port registers Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 0 pull-up register PUL0 R/W 0b00000000 Port 1 pull-up register PUL1 R/W 0b00000000 Port 6 pull-up register PUL6 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000 R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the readmodify-write (RMW) type of instruction.) Document Number: 002-04627 Rev. *G Page 30 of 103 CY95630H Series 15.1 Port 0 Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX CY95630H Series Hardware Manual”. 15.1.1 Port 0 configuration Port 0 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 0 data register (PDR0) • Port 0 direction register (DDR0) • Port 0 pull-up register (PUL0) • A/D input disable register (lower) (AIDRL) 15.1.2 Block diagrams of port 0 • P00/INT00/AN00/CMP0_P pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT00) • 8/10-bit A/D converter analog input pin (AN00) • Comparator non-inverting analog input (positive input) pin (CMP0_P) • P01/INT01/AN01/CMP0_N pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT01) • 8/10-bit A/D converter analog input pin (AN01) • Comparator inverting analog input (negative input) pin (CMP0_N) Document Number: 002-04627 Rev. *G Page 31 of 103 CY95630H Series • Block diagram of P00/INT00/AN00/CMP0_P and P01/INT01/AN01/CMP0_N Comparator analog input Comparator analog input disable Peripheral function input A/D analog input Peripheral function input enable (INT00 and INT01) Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write Document Number: 002-04627 Rev. *G Page 32 of 103 CY95630H Series • P02/INT02/AN02/SCK pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT02) • 8/10-bit A/D converter analog input pin (AN02) • LIN-UART clock I/O pin (SCK) • P03/INT03/AN03/SOT pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT03) • 8/10-bit A/D converter analog input pin (AN03) • LIN-UART data output pin (SOT) • P05/INT05/AN05/TO00 pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT05) • 8/10-bit A/D converter analog input pin (AN05) • 8/16-bit composite timer ch. 0 output pin (TO00) • P06/INT06/AN06/TO01 pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT06) • 8/10-bit A/D converter analog input pin (AN06) • 8/16-bit composite timer ch. 0 output pin (TO01) Document Number: 002-04627 Rev. *G Page 33 of 103 CY95630H Series • Block diagram of P02/INT02/AN02/SCK, P03/INT03/AN03/SOT, P05/INT05/AN05/TO00 and P06/INT06/AN06/TO01 Peripheral function input A/D analog input Peripheral function input enable (INT02, INT03, INT05 and INT06) Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write Document Number: 002-04627 Rev. *G Page 34 of 103 CY95630H Series • P04/INT04/AN04/SIN/EC0 pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT04) • 8/10-bit A/D converter analog input pin (AN04) • LIN-UART data input pin (SIN) • 8/16-bit composite timer ch. 0 clock input pin (EC0) • Block diagram of P04/INT04/AN04/SIN/EC0 Peripheral function input Peripheral function input enable (INT04) A/D analog input 0 1 Pull-up CMOS PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write Document Number: 002-04627 Rev. *G Page 35 of 103 CY95630H Series • P07/INT07/AN07 pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT07) • 8/10-bit A/D converter analog input pin (AN07) • Block diagram of P07/INT07/AN07 Peripheral function input Peripheral function input enable (INT07) A/D analog input Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write Document Number: 002-04627 Rev. *G Page 36 of 103 CY95630H Series 15.1.3 Port 0 registers • Port 0 register functions Register abbreviation PDR0 DDR0 PUL0 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Analog input enabled 1 Port input enabled • Correspondence between registers and pins for port 0 Correspondence between related register bits and pins Pin name P07 P06 P05 P04 P03 P02 P01 P00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PDR0 DDR0 PUL0 AIDRL 15.1.4 Port 0 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR0 register to external pins. • If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR0 register returns the PDR0 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input disable register (lower) (AIDRL) to “1”. • If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. Document Number: 002-04627 Rev. *G Page 37 of 103 CY95630H Series • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”. • When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”. • Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with analog input, its port input is disabled because the AIDRL register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the corresponding bit in the PUL0 register to “0”. • Operation as an external interrupt input pin • Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register. • Operation as a comparator input pin (only for P00 and P01) • Set the bit in the AIDRL register corresponding to the comparator input pin to “0”. • Regardless of the value of the PDR0 register and that of the DDR0 register, if the comparator analog input enable bit in the comparator control register (CMR0C:VCID) is set to “0”, the comparator input function is enabled. • To disable the comparator input function, set the VCID bit to “1”. • For details of the comparator, refer to “CHAPTER 27 COMPARATOR” in “New 8FX CY95630H Series Hardware Manual”. Document Number: 002-04627 Rev. *G Page 38 of 103 CY95630H Series 15.2 Port 1 Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX CY95630H Series Hardware Manual”. 15.2.1 Port 1 configuration Port 1 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 1 data register (PDR1) • Port 1 direction register (DDR1) • Port 1 pull-up register (PUL1) 15.2.2 Block diagrams of port 1 • P10/PPG10/CMP0_O pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 1 output pin (PPG10) • Comparator digital output pin (CMP0_O) • P11/PPG11 pin This pin has the following peripheral function: • 8/16-bit PPG ch. 1 output pin (PPG11) • P13/PPG00 pin This pin has the following peripheral function: • 8/16-bit PPG ch. 0 output pin (PPG00) • P15/UO0/PPG20 pin This pin has the following peripheral functions: • UART/SIO ch. 0 data output pin (UO0) • 8/16-bit PPG ch. 2 output pin (PPG20) Document Number: 002-04627 Rev. *G Page 39 of 103 CY95630H Series • Block diagram of P10/PPG10/CMP0_O, P11/PPG11, P13/PPG00 and P15/UO0/PPG20 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write Document Number: 002-04627 Rev. *G Page 40 of 103 CY95630H Series • P12/DBG/EC0 pin This pin has the following peripheral functions: • DBG input pin (DBG) • 8/16-bit composite timer ch. 0 clock input pin (EC0) • Block diagram of P12/DBG/EC0 Peripheral function input Hysteresis 0 1 PDR1 read Internal bus PDR1 Pin OD PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) • P14/UCK0/PPG01 pin This pin has the following peripheral functions: • UART/SIO ch. 0 clock I/O pin (UCK0) • 8/16-bit PPG ch. 0 output pin (PPG01) Document Number: 002-04627 Rev. *G Page 41 of 103 CY95630H Series • Block diagram of P14/UCK0/PPG01 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write Document Number: 002-04627 Rev. *G Page 42 of 103 CY95630H Series • P16/UI0/PPG21 pin This pin has the following peripheral functions: • UART/SIO ch. 0 data input pin (UI0) • 8/16-bit PPG ch. 2 output pin (PPG21) • Block diagram of P16/UI0/PPG21 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Pull-up 0 1 PDR1 read CMOS 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write • P17/TO1/SNI0 pin This pin has the following peripheral functions: • 16-bit reload timer ch. 1 output pin (TO1) • Trigger input pin for the position detection function of the MPG waveform sequencer (SNI0) Document Number: 002-04627 Rev. *G Page 43 of 103 CY95630H Series • Block diagram of P17/TO1/SNI0 Peripheral function input Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write Document Number: 002-04627 Rev. *G Page 44 of 103 CY95630H Series 15.2.3 Port 1 registers • Port 1 register functions Register abbreviation PDR1 DDR1 PUL1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 1 Correspondence between related register bits and pins Pin name P17 P16 P15 P14 P13 P12 P11 P10 bit7 bit6 bit5 bit4 bit3 bit2* bit1 bit0 PDR1 DDR1 PUL1 *: Though P12 has no pull-up function, bit2 in the PUL1 register can still be accessed. The operation of P12 is not affected by the setting of bit2 in the PUL1 register. 15.2.4 Port 1 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR1 register to external pins. • If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR1 register returns the PDR1 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function Document Number: 002-04627 Rev. *G Page 45 of 103 CY95630H Series to “0”. • Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P14/UCK0 and P16/UI0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register. 15.3 Port 6 Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX CY95630H Series Hardware Manual”. 15.3.1 Port 6 configuration Port 6 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 6 data register (PDR6) • Port 6 direction register (DDR6) • Port 6 pull-up register (PUL6) 15.3.2 Block diagrams of port 6 • P60/INT08/SDA/DTTI pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT08) • I2C bus interface ch. 0 data I/O pin (SDA) • MPG waveform sequencer input pin (DTTI) • P61/INT09/SCL/TI1 pin This pin has the following peripheral functions: • External interrupt circuit input pin (INT09) • I2C bus interface ch. 0 clock I/O pin (SCL) • 16-bit reload timer ch. 1 input pin (TI1) Document Number: 002-04627 Rev. *G Page 46 of 103 CY95630H Series • Block diagram of P60/INT08/SDA/DTTI and P61/INT09/SCL/TI1 Peripheral function input Peripheral function input enable (INT08 and INT09) Peripheral function output enable Peripheral function output CMOS 0 1 PDR6 read Internal bus Pin 1 PDR6 0 OD PDR6 write Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) • P62/TO10/PPG00/OPT0 pin This pin has the following peripheral functions: • 8/16-bit composite timer ch. 1 output pin (TO10) • 8/16-bit PPG ch. 0 output pin (PPG00) • MPG waveform sequencer output pin (OPT0) • P63/TO11/PPG01/OPT1 pin This pin has the following peripheral functions: • 8/16-bit composite timer ch. 1 output pin (TO11) • 8/16-bit PPG ch. 0 output pin (PPG01) • MPG waveform sequencer output pin (OPT1) • P65/PPG11/OPT3 pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 1 output pin (PPG11) • MPG waveform sequencer output pin (OPT3) • P66/PPG20/PPG1/OPT4 pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 2 output pin (PPG20) • 16-bit PPG timer ch. 1 output pin (PPG1) • MPG waveform sequencer output pin (OPT4) • Block diagram of P62/TO10/PPG00/OPT0, P63/TO11/PPG01/OPT1, P65/PPG11/OPT3 and Document Number: 002-04627 Rev. *G Page 47 of 103 CY95630H Series P66/PPG20/PPG1/OPT4 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR6 read 1 PDR6 0 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write • P64/EC1/PPG10/OPT2 pin This pin has the following peripheral functions: • 8/16-bit composite timer ch. 1 clock input pin (EC1) • 8/16-bit PPG ch. 1 output pin (PPG10) • MPG waveform sequencer output pin (OPT2) • P67/PPG21/TRG1/OPT5 pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 2 output pin (PPG21) • 16-bit PPG timer ch. 1 trigger input pin (TRG1) • MPG waveform sequencer output pin (OPT5) Document Number: 002-04627 Rev. *G Page 48 of 103 CY95630H Series • Block diagram of P64/EC1/PPG10/OPT2 and P67/PPG21/TRG1/OPT5 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR6 read 1 PDR6 Pin 0 PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write 15.3.3 Port 6 registers • Port 6 register functions Register abbreviation PDR6 DDR6 PUL6 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 6 Correspondence between related register bits and pins Pin name P67 P66 P65 P64 P63 P62 bit7 bit6 bit5 bit4 bit3 bit2 PDR6 DDR6 PUL6 Document Number: 002-04627 Rev. *G P61 P60 bit1 bit0 - - Page 49 of 103 CY95630H Series 15.3.4 Port 6 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. • If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR6 register returns the PDR6 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR6 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input from the external interrupt (INT08, INT09) is enabled, or if the interrupt input of P64/EC1 and P67/TRG1 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register. Document Number: 002-04627 Rev. *G Page 50 of 103 CY95630H Series 15.4 Port F Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX CY95630H Series Hardware Manual”. 15.4.1 Port F configuration Port F is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port F data register (PDRF) • Port F direction register (DDRF) 15.4.2 Block diagrams of port F • PF0/X0 pin This pin has the following peripheral function: • Main clock input oscillation pin (X0) • PF1/X1 pin This pin has the following peripheral function: • Main clock I/O oscillation pin (X1) • Block diagram of PF0/X0 and PF1/X1 Hysteresis 0 1 PDRF read Internal bus PDRF Pin PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) Document Number: 002-04627 Rev. *G Page 51 of 103 CY95630H Series • PF2/RST pin This pin has the following peripheral function: • Reset pin (RST) • Block diagram of PF2/RST Reset input Reset input enable Reset output enable Reset output Hysteresis 0 1 PDRF read Internal bus Pin 1 PDRF OD 0 PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) 15.4.3 Port F registers • Port F register functions Register abbreviation PDRF DDRF Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port F Correspondence between related register bits and pins Pin name PDRF DDRF - - - - - PF2* PF1 PF0 - - - - - bit2 bit1 bit0 *: PF2/RST is the dedicated reset pin on CY95F632H/F633H/F634H/F636H. 15.4.4 Port F operations • Operation as an output port • A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRF register to external pins. • If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRF register returns the PDRF register value. Document Number: 002-04627 Rev. *G Page 52 of 103 CY95630H Series • Operation as an input port • A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 15.5 Port G Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX CY95630H Series Hardware Manual”. 15.5.1 Port G configuration Port G is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port G data register (PDRG) • Port G direction register (DDRG) • Port G pull-up register (PULG) 15.5.2 Block diagram of port G • PG1/X0A/SNI1 pin This pin has the following peripheral functions: • Subclock input oscillation pin (X0A) • Trigger input pin for the position detection function of the MPG waveform sequencer (SNI1) • PG2/X1A/SNI2 pin This pin has the following peripheral functions: • Subclock I/O oscillation pin (X1A) • Trigger input pin for the position detection function of the MPG waveform sequencer (SNI2) Document Number: 002-04627 Rev. *G Page 53 of 103 CY95630H Series • Block diagram of PG1/X0A/SNI1 and PG2/X1A/SNI2 Peripheral function input Hysteresis 0 Pull-up 1 PDRG read PDRG Pin PDRG write Internal bus Executing bit manipulation instruction DDRG read DDRG DDRG write Stop mode, watch mode (SPL = 1) PULG read PULG PULG write 15.5.3 Port G registers • Port G register functions Register abbreviation PDRG DDRG PULG Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port G Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - - - - - - bit2 bit1 - PDRG DDRG PULG 15.5.4 Port G operations • Operation as an output port • A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRG register to external pins. Document Number: 002-04627 Rev. *G Page 54 of 103 CY95630H Series • If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRG register returns the PDRG register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDRG register corresponding to the input pin of a peripheral function to “0”. • Reading the PDRG register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register. Document Number: 002-04627 Rev. *G Page 55 of 103 CY95630H Series 16. Interrupt Source Table Interrupt source External interrupt ch. 0 External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 UART/SIO ch. 0 MPG (DTTI) 8/16-bit composite timer ch. 0 (lower) 8/16-bit composite timer ch. 0 (upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch. 1 (lower) 8/16-bit PPG ch. 1 (upper) 8/16-bit PPG ch. 2 (upper) 8/16-bit PPG ch. 0 (upper) 8/16-bit PPG ch. 0 (lower) 8/16-bit composite timer ch. 1 (upper) 8/16-bit PPG ch. 2 (lower) 16-bit reload timer ch. 1 MPG (write timing/compare clear) I2C bus interface 16-bit PPG timer ch. 1 MPG (position detection/compare interrupt) 8/10-bit A/D converter Time-base timer Watch prescaler Comparator External interrupt ch. 8 External interrupt ch. 9 8/16-bit composite timer ch. 1 (lower) Flash memory Document Number: 002-04627 Rev. *G Interrupt request number Vector table address Upper Lower Interrupt level setting register Register Bit IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0] IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0] IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0] IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0] IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0] IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0] IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 0xFFEC 0xFFEA 0xFFE8 0xFFE6 0xFFE4 0xFFE2 0xFFE0 0xFFED 0xFFEB 0xFFE9 0xFFE7 0xFFE5 0xFFE3 0xFFE1 ILR1 ILR2 ILR2 ILR2 ILR2 ILR3 ILR3 L07 [1:0] L08 [1:0] L09 [1:0] L10 [1:0] L11 [1:0] L12 [1:0] L13 [1:0] IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0] IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0] IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0] IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0] IRQ18 IRQ19 0xFFD6 0xFFD7 0xFFD4 0xFFD5 ILR4 ILR4 L18 [1:0] L19 [1:0] IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0] IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0] IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0] IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0] Priority order of interrupt sources of the same level (occurring simultaneously) High Low Page 56 of 103 CY95630H Series 17. Pin States In Each Mode Pin name Normal operation Sleep mode Oscillation input Oscillation input PF0/X0 I/O port* 4 I/O port* 4 Oscillation input Oscillation input PF1/X1 I/O port*4 I/O port*4 Oscillation input Oscillation input PG1/X0A/ SNI1 PF2/RST I/O port*4/ peripheral function I/O I/O port I/O port*4/ peripheral function I/O Reset input P62/TO10/ PPG00/ OPT0 P63/TO11/ PPG01/ OPT1 SPL=0 SPL=1 Hi-Z Hi-Z Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2*4 blocked*2*4 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2*4 2 4 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2*4 blocked*2*4 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2*4 2 4 blocked* * Hi-Z Hi-Z On reset — - Hi-Z - Input enabled*1 (However, it does not function.) — - Hi-Z - Input enabled*1 (However, it does not function.) — I/O port/ peripheral function I/O I/O port/ peripheral function I/O Hi-Z Hi-Z Hi-Z Hi-Z — - Hi-Z (However, - Hi-Z (However, - Hi-Z the setting of the setting of - Previous state - Input - Previous state the pull-up the pull-up kept enabled*1 kept control is control is - Input - Input (However, it effective.) effective.) blocked*2*4 blocked*2*4 does not - Input - Input function.) blocked*2*4 blocked*2*4 Reset input Reset input Reset input Reset input Reset input*3 I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z kept kept - Input blocked*2 - Input blocked*2 - Input blocked*2 - Input blocked*2 (However, an (However, an - Hi-Z (However, an (However, an - Input external external external external enabled*1 interrupt can interrupt can interrupt can interrupt can be input when be input when (However, it be input when be input when the external the external does not the external the external interrupt interrupt function.) interrupt interrupt request is request is request is request is enabled.) enabled.) enabled.) enabled.) I/O port/ peripheral function I/O - Hi-Z (However, the setting of - Previous state - Previous state the pull-up kept kept control is - Input blocked*2 - Input blocked*2 effective.) - Input blocked*2 - P60/INT08/ SDA/DTTI P61/INT09/ SCL/TI1 Watch mode SPL=1 - Hi-Z (However, - Hi-Z (However, - Hi-Z the setting of the setting of - Previous state - Input - Previous state I/O port*4/ I/O port*4/ the pull-up the pull-up kept enabled*1 kept control is control is peripheral func- peripheral func- Input - Input (However, it effective.) effective.) tion I/O tion I/O blocked*2*4 blocked*2*4 does not - Input - Input function.) blocked*2*4 blocked*2*4 Oscillation input Oscillation input PG2/X1A/ SNI2 Stop mode SPL=0 Document Number: 002-04627 Rev. *G Hi-Z (However, - Hi-Z the setting of - Input the pull-up enabled*1 control is (However, it effective.) does not Input blocked*2 function.) Page 57 of 103 CY95630H Series Pin name Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset I/O port/ peripheral function I/O - Hi-Z (However, - Hi-Z (However, the setting of the setting of - Previous state - Previous state the pull-up the pull-up kept kept control is control is 2 2 - Input blocked* - Input blocked* effective.) effective.) - Hi-Z (However, an (However, an - Input blocked*2 - Input blocked*2 - Input external external enabled*1 (However, an (However, an interrupt can interrupt can external external (However, it be input when be input when interrupt can interrupt can does not the external the external be input when be input when function.) interrupt interrupt the external the external request is request is interrupt interrupt enabled.) enabled.) request is request is enabled.) enabled.) I/O port/ peripheral function I/O - Hi-Z (However, the setting of - Previous state - Previous state the pull-up kept kept control is - Input blocked*2 - Input blocked*2 effective.) - Input blocked*2 - I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Hi-Z (However, - Hi-Z (However, the setting of the setting of - Previous state - Previous state the pull-up the pull-up kept kept control is control is 2 2 - Input blocked* - Input blocked* effective.) effective.) - Hi-Z (However, an (However, an - Input blocked*2 - Input blocked*2 - Input external external enabled*1 (However, an (However, an interrupt can interrupt can external external (However, it be input when be input when interrupt can interrupt can does not the external the external be input when be input when function.) interrupt interrupt the external the external request is request is interrupt interrupt enabled.) enabled.) request is request is enabled.) enabled.) P10/PPG10/ CMP0_O I/O port/ peripheral function I/O P11/PPG11 I/O port/ peripheral function I/O - Previous state kept - Input blocked*2 I/O port/ peripheral function I/O - Hi-Z - Input - Previous state - Previous state enabled*1 - Hi-Z - Hi-Z kept kept - Input blocked*2 - Input blocked*2 (However, it 2 2 - Input blocked* - Input blocked* does not function.) I/O port/ peripheral function I/O - Hi-Z (However, the setting of - Previous state - Previous state the pull-up kept kept control is - Input blocked*2 - Input blocked*2 effective.) - Input blocked*2 - P64/EC1/ PPG10/ OPT2 P65/PPG11/ OPT3 P66/PPG1/ PPG20/ OPT4 P67/TRG1/ PPG21/ OPT5 P12/DBG/ EC0 I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ P13/PPG00 peripheral function I/O Document Number: 002-04627 Rev. *G - Hi-Z (However, the setting of - Previous state the pull-up kept control is - Input blocked*2 effective.) - Input blocked*2 - Hi-Z (However, - Hi-Z the setting of - Input the pull-up enabled*1 control is (However, it effective.) does not Input blocked*2 function.) Hi-Z (However, - Hi-Z the setting of - Input the pull-up enabled*1 control is (However, it effective.) does not Input blocked*2 function.) Hi-Z (However, - Hi-Z the setting of - Input the pull-up enabled*1 control is (However, it effective.) does not Input blocked*2 function.) Page 58 of 103 CY95630H Series Pin name P14/UCK0/ PPG01 P15/UO0/ PPG20 P16/UI0/ PPG21 P17/TO1/ SNI0 Normal operation I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O Sleep mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset I/O port/ peripheral function I/O - Hi-Z (However, - Hi-Z (However, the setting of the setting of - Previous state - Previous state the pull-up the pull-up kept kept control is control is 2 2 - Input blocked* - Input blocked* effective.) effective.) - Hi-Z (However, an (However, an - Input blocked*2 - Input blocked*2 - Input external external enabled*1 (However, an (However, an interrupt can interrupt can external external (However, it be input when be input when interrupt can interrupt can does not the external the external be input when be input when function.) interrupt interrupt the external the external request is request is interrupt interrupt enabled.) enabled.) request is request is enabled.) enabled.) I/O port/ peripheral function I/O - Hi-Z (However, the setting of - Previous state - Previous state the pull-up kept kept control is - Input blocked*2 - Input blocked*2 effective.) - Input blocked*2 - I/O port/ peripheral function I/O - Hi-Z (However, - Hi-Z (However, the setting of the setting of - Previous state - Previous state the pull-up the pull-up kept kept control is control is 2 2 - Input blocked* - Input blocked* effective.) effective.) - Hi-Z (However, an (However, an - Input blocked*2 - Input blocked*2 - Input external external enabled*1 (However, an (However, an interrupt can interrupt can external external (However, it be input when be input when interrupt can interrupt can does not the external the external be input when be input when function.) interrupt interrupt the external the external request is request is interrupt interrupt enabled.) enabled.) request is request is enabled.) enabled.) I/O port/ peripheral function I/O - Hi-Z (However, the setting of - Previous state - Previous state the pull-up kept kept control is - Input blocked*2 - Input blocked*2 effective.) - Input blocked*2 - I/O port/ peripheral function I/O/ analog input - Hi-Z (However, - Hi-Z (However, the setting of the setting of - Previous state - Previous state the pull-up the pull-up kept kept control is control is 2 2 - Input blocked* - Input blocked* effective.) effective.) (However, an (However, an - Input blocked*2 - Input blocked*2 - Hi-Z external external (However, an (However, an - Input interrupt can interrupt can external external blocked*2 be input when be input when interrupt can interrupt can the external the external be input when be input when interrupt interrupt the external the external request is request is interrupt interrupt enabled.) enabled.) request is request is enabled.) enabled.) P00/INT00/ AN00/ CMP0_P P01/INT01/ AN01/ I/O port/ CMP0_N peripheral P02/INT02/ function I/O/ AN02/SCK analog input Stop mode P03/INT03/ AN03/SOT Document Number: 002-04627 Rev. *G Hi-Z (However, - Hi-Z the setting of - Input the pull-up enabled*1 control is (However, it effective.) does not Input blocked*2 function.) Hi-Z (However, - Hi-Z the setting of - Input the pull-up enabled*1 control is (However, it effective.) does not Input blocked*2 function.) Page 59 of 103 CY95630H Series Pin name Normal operation Sleep mode P04/INT04/ AN04/SIN/ EC0 P05/INT05/ AN05/TO00 I/O port/ P06/INT06/ peripheral AN06/TO01 function I/O/ analog input I/O port/ peripheral function I/O/ analog input P07/INT07/ AN07 Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset - Hi-Z (However, - Hi-Z (However, the setting of the setting of - Previous state - Previous state the pull-up the pull-up kept kept control is control is 2 2 - Input blocked* - Input blocked* effective.) effective.) (However, an (However, an - Input blocked*2 - Input blocked*2 - Hi-Z external external (However, an (However, an - Input interrupt can interrupt can external external blocked*2 be input when be input when interrupt can interrupt can the external the external be input when be input when interrupt interrupt the external the external request is request is interrupt interrupt enabled.) enabled.) request is request is enabled.) enabled.) SPL: Pin state setting bit in the standby control register (STBC:SPL) Hi-Z: High impedance *1: “Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or pull-down operation has to be performed in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports. *2: “Input blocked” means direct input gate operation from the pin is disabled. *3: The PF2/RST pin stays at the state shown when configured as a reset pin. *4: The pin stays at the state shown when configured as a general-purpose I/O port. Document Number: 002-04627 Rev. *G Page 60 of 103 CY95630H Series 18. Electrical Characteristics 18.1 Absolute Maximum Ratings Rating Parameter Symbol Power supply voltage*1 VCC VSS 0.3 VSS  6 V Input voltage*1 VI VSS 0.3 VSS  6 V *2 Output voltage*1 VO VSS 0.3 VSS  6 V *2 Maximum clamp current Total maximum clamp current “L” level maximum output current Min 2 mA Applicable to specific pins*3 |ICLAMP| — 20 mA Applicable to specific pins*3 IOL — 15 mA 4 — IOLAV2 “H” level maximum output current mA 12 Other than P62 to P67 Average output current = operating current  operating ratio (1 pin) P62 to P67 Average output current = operating current  operating ratio (1 pin) IOL — 100 mA IOLAV — 37 Total average output current = mA operating current  operating ratio (Total number of pins) IOH — 15 mA 4 IOHAV1 “H” level average current — mA 8 IOHAV2 “H” level total maximum output current Remarks 2 “L” level average current “L” level total average output current Unit ICLAMP IOLAV1 “L” level total maximum output current Max Other than P62 to P67 Average output current = operating current  operating ratio (1 pin) P62 to P67 Average output current = operating current  operating ratio (1 pin) IOH — 100 mA IOHAV — 47 Total average output current = mA operating current  operating ratio (Total number of pins) Power consumption Pd — 320 mW Operating temperature TA 40 85 Storage temperature Tstg 55 150 C C “H” level total average output current *1: These parameters are based on the condition that VSS is 0.0 V. *2: V1 and V0 must not exceed VCC  0.3 V. V1 must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Specific pins: P00 to P07, P10, P11, P13 to P17, P62 to P67, PF0, PF1, PG1, PG2 Document Number: 002-04627 Rev. *G Page 61 of 103 CY95630H Series • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit: • Input/Output equivalent circuit Protective diode VCC P-ch Limiting resistor HV(High Voltage) input (0 V to 16 V) N-ch R WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-04627 Rev. *G Page 62 of 103 CY95630H Series 18.2 Recommended Operating Conditions Parameter Symbol Power supply voltage VCC Decoupling capacitor CS Operating temperature TA (VSS = 0.0 V) Value Min Max 2.4*1 5.5 2.3 5.5 0.022 1  40 85 5 35 Unit V µF C Remarks In normal operation Hold condition in stop mode *2 Other than on-chip debug mode On-chip debug mode *1: The minimum power supply voltage becomes 2.88 V when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram * DBG C RST Cs *: Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-04627 Rev. *G Page 63 of 103 CY95630H Series 18.3 DC Characteristics Parameter Symbol “H” level input voltage “L” level input voltage Open-drain output application voltage “H” level output voltage “L” level output voltage Input leak current (Hi-Z output leak current) Internal pull-up resistor Input capacitance (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85°C) Pin name Condition VIHI P04, P16, P60, P61 Value Unit Remarks VCC  0.3 V CMOS input level — VCC  0.3 V Hysteresis input 0.8 VCC — VCC  0.3 V Hysteresis input — VSS 0.3 — 0.3 VCC V CMOS input level VILS P00 to P07, P10 to P17, P60 to P67, PF0, PF1, PG1, PG2 — VSS 0.3 — 0.2 VCC V Hysteresis input VILM PF2 — VSS 0.3 — 0.2 VCC V Hysteresis input P12, P60, P61, PF2 — VSS 0.3 — Vss  5.5 V VOH1 Output pins other than P12, IOH = 4 mA P62 to P67, PF2 VCC 0.5 — — V VOH2 P62 to P67 IOH = 8 mA VCC 0.5 — — V VOL1 Output pins other than P62 IOL = 4 mA to P67 — — 0.4 V VOL2 P62 to P67 IOL = 12 mA — — 0.4 V All input pins 0.0 V < VI < VCC 5 — 5 When the internal µA pull-up resistor is disabled P00 to P07, P10, P11, P13 to P17, P62 to P67, PG1, PG2 VI = 0 V 25 50 100 When the internal k pull-up resistor is enabled — 5 15 pF Min Typ Max — 0.7 VCC — VIHS P00 to P07, P10 to P17, P60 to P67, PF0, PF1, PG1, PG2 — 0.8 VCC VIHM PF2 — VILI P04, P16, P60, P61 VD ILI RPULL CIN Other than VCC f = 1 MHz and VSS Document Number: 002-04627 Rev. *G Page 64 of 103 CY95630H Series (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85°C) Parameter Symbol Pin name Condition Value Min Typ*1 Max*2 Unit Remarks — 3.6 5.8 Except during Flash mA memory programming and erasing — 7.5 13.8 During Flash memory mA programming and erasing — 4.1 9.1 mA At A/D conversion — 1.3 3 mA ICCL VCC FCL = 32 kHz (External clock FMPL = 16 kHz operation) Subclock mode (divided by 2) TA = 25°C — 49 145 µA ICCLS FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = 25°C — 10 15 µA ICCT FCL = 32 kHz Watch mode Main stop mode TA = 25°C — 7 13 µA In deep standby mode FMCRPLL = 16 MHz FMP = 16 MHz Main CR PLL clock mode (multiplied by 4) TA = 25°C — 4.7 6.8 mA ICCMCR FCRH = 4 MHz FMP = 4 MHz Main CR clock mode — 1.1 4.6 mA ICCSCR Sub-CR clock mode (divided by 2) TA = 25°C — 58.1 230 µA — 345 395 µA In deep standby mode — 6 10 µA In deep standby mode FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ICC FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) ICCS Power supply current*3 ICCMPLL VCC ICCTS ICCH FCH = 32 MHz Time-base timer mode VCC T A = 25°C (External clock operation) Substop mode TA = 25°C Document Number: 002-04627 Rev. *G In deep standby mode Page 65 of 103 CY95630H Series (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85°C) Parameter Power supply current*3 Symbol Pin name Condition Value Min Typ*1 Max*2 Unit IV Current consumption of the comparator — 60 160 µA ILVD Current consumption of the low-voltage detection circuit — 4 7 µA ICRH Current consumption of the main CR oscillator — 240 320 µA ICRL Current consumption of the sub-CR oscillator oscillating at 100 kHz — 7 20 µA INSTBY Current consumption difference between normal standby mode and deep standby mode TA = 25°C — 20 30 µA VCC Remarks *1: VCC = 5.0 V, TA = 25°C *2: VCC = 5.5 V, TA = 85°C (unless otherwise specified) *3: • The power supply current is determined by the external clock. When the low-voltage detection circuit is selected, the power supply current is the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the values from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current is the sum of adding up the current consumption of the low-voltage detection circuit (ILVD), the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always in operation, and current consumption therefore increases accordingly. • See “4. AC Characteristics Clock Timing” for FCH, FCL, FCRH and FMCRPLL. • See “4. AC Characteristics Source Clock/Machine Clock” for FMP and FMPL. • The power supply current value in standby mode is measured in deep standby mode. The current consumption in normal standby is higher than that in deep standby mode. The power supply current value in normal standby can be found by adding the current consumption difference between normal standby mode and deep standby mode (INSTBY) to the power supply current value in deep standby mode. For details of normal standby and deep standby mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in “New 8FX CY95630H Series Hardware Manual”. Document Number: 002-04627 Rev. *G Page 66 of 103 CY95630H Series 18.4 AC Characteristics 18.4.1 Clock Timing Parameter Clock frequency (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C) Value Symbol Pin name Condition Unit Remarks Min Typ Max When the main oscillation X0, X1 — 1 — 16.25 MHz circuit is used FCH X0 X1: open 1 — 12 MHz When the main external clock X0, X1 * 1 — 32.5 MHz is used Operating conditions 3.92 4 4.08 MHz • The main CR clock is used. • 0C TA 70C FCRH — — Operating conditions • The main CR clock is used. 3.8 4 4.2 MHz •  40 C  TA  0 C,  70 C  TA   85 C Operating conditions 7.84 8 8.16 MHz • PLL multiplication rate: 2 • 0C TA 70C Operating conditions • PLL multiplication rate: 2 7.6 8 8.4 MHz •  40 C  TA  0 C,  70 C  TA   85 C Operating conditions 9.8 10 10.2 MHz • PLL multiplication rate: 2.5 • 0C TA 70C Operating conditions • PLL multiplication rate: 2.5 9.5 10 10.5 MHz •  40 C  TA  0 C,  70 C  TA   85 C — — FMCRPLL Operating conditions 11.76 12 12.24 MHz • PLL multiplication rate: 3 • 0C TA 70C Operating conditions • PLL multiplication rate: 3 11.4 12 12.6 MHz •  40 C  TA  0 C,  70 C  TA   85 C Operating conditions 15.68 16 16.32 MHz • PLL multiplication rate: 4 • 0C TA 70C Operating conditions • PLL multiplication rate: 4 15.2 16 16.8 MHz •  40 C  TA  0 C,  70 C  TA   85 C When the suboscillation — 32.768 — kHz circuit is used FCL X0A, X1A — When the sub-external clock — 32.768 — kHz is used When the sub-CR clock is FCRL — — 50 100 150 kHz used Document Number: 002-04627 Rev. *G Page 67 of 103 CY95630H Series (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C) Parameter Symbol Pin name Condition  X0, X1 Clock cycle time tHCYL X0 tLCYL Input clock pulse width X0A, X1A tWH1, tWL1 X0 tWH2, tWL2 X0A Typ Max 61.5  1000 ns 83.4 1000 ns 1000 ns * 30.8   30.5 33.4 * 12.4    — 15.2     —  5 ns — — 5 ns X1: open X0, X1 X0, X0A X1: open Input clock rising time and tCR, tCF X0, X1, * falling time X0A, X1A CR oscillation start time Unit Min   X1: open X0, X1 Value Remarks When the main oscillation circuit is used When an external clock is used µs When the subclock is used ns ns µs When an external clock is used, the duty ratio should range between 40% and 60%. When an external clock is used tCRHWK — — — — 50 µs When the main CR clock is used tCRLWK — — — — 30 µs When the sub-CR clock is used — — — — 100 µs When the main CR PLL clock is used PLL oscillation tMCRPLLWK start time *: The external clock signal is input to X0 and the inverted external clock signal to X1. • Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tCR tWL1 tCF 0.8 VCC 0.8 VCC X0, X1 0.2 VCC 0.2 VCC 0.2 VCC • Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used X0 When an external clock is used When an external clock (X1 is open) is used X0 X1 FCH X1 X1 Open FCH Document Number: 002-04627 Rev. *G X0 FCH Page 68 of 103 CY95630H Series • Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR tWL2 tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC • Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used X0A X1A When an external clock is used X0A X1A Open FCL FCL • Input waveform generated when an internal clock (main CR clock) is used tCRHWK 1/FCRH Main CR clock Oscillation starts Oscillation stabilizes • Input waveform generated when an internal clock (sub-CR clock) is used tCRLWK 1/FCRL Sub-CR clock Oscillation starts Document Number: 002-04627 Rev. *G Oscillation stabilizes Page 69 of 103 CY95630H Series • Input waveform generated when an internal clock (main CR PLL clock) is used 1/FMCRPLL tMCRPLLWK Main CR PLL clock Oscillation starts Oscillation stabilizes 18.4.2 Source Clock/Machine Clock Parameter Source clock cycle time*1 Symbol tSCLK (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Pin name — FSP Source clock frequency Machine clock cycle time*2 (minimum instruction execution time) — FSPL tMCLK Value Unit Typ Max 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 62.5 — 250 ns When the main CR clock is used Min: FCRH = 4 MHz, multiplied by 4 Max: FCRH = 4 MHz, no division — 61 — µs When the suboscillation clock is used FCL = 32.768 kHz, divided by 2 — 20 — µs When the sub-CR clock is used FCL = 100 kHz, divided by 2 0.5 — 16.25 — 4 — MHz When the main CR clock is used — 16.384 — kHz When the suboscillation clock is used — 50 — kHz 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 250 — 4000 ns When the main CR clock is used Min: FSP = 4 MHz, no division Max: FSP = 4 MHz, divided by 16 61 — 976.5 µs When the suboscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 MHz When the main oscillation clock is used — Document Number: 002-04627 Rev. *G Remarks Min When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Page 70 of 103 CY95630H Series Parameter Symbol Pin name FMP Machine clock frequency — FMPL Value Unit Min Typ Max 0.031 — 16.25 0.25 — 16 1.024 — 16.384 3.125 — 50 Remarks MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the suboscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following. • Main clock divided by 2 • Main CR clock • PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.) • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 • Schematic diagram of the clock generation block FCH (Main oscillation clock) Divided by 2 FCRH (Main CR clock) SCLK (Source clock) FMCRPLL (Main CR PLL clock) FCL (Suboscillation clock) Division circuit × 1 × 1/4 × 1/8 × 1/16 MCLK (Machine clock) Divided by 2 Machine clock divide ratio select bits (SYCC:DIV[1:0]) FCRL (Sub-CR clock) Divided by 2 Clock mode select bits (SYCC:SCS[2:0]) Document Number: 002-04627 Rev. *G Page 71 of 103 CY95630H Series • Operating voltage - Operating frequency (TA = 40°C to 85°C) 5.5 Operating voltage (V) 5.0 A/D converter operation range 4.0 3.5 3.0 2.7 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) 18.4.3 External Reset Parameter RST “L” level pulse width (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Symbol tRSTL Value Min Max 2 tMCLK*  Unit Remarks ns *: See “Source Clock/Machine Clock” for tMCLK. tRSTL RST 0.2 VCC Document Number: 002-04627 Rev. *G 0.2 VCC Page 72 of 103 CY95630H Series 18.4.4 Power-on Reset (VSS = 0.0 V, TA = 40°C to 85°C) Parameter Symbol Condition Power supply rising time tR Power supply cutoff time tOFF   Value Unit Min Max  50 ms 1  ms Remarks Wait time until power-on tOFF tR 2.5 V VCC 0.2 V 0.2 V 0.2 V Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below. VCC 2.3 V Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode VSS 18.4.5 Peripheral Input Timing Parameter (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Symbol Peripheral input “H” pulse width tILIH Peripheral input “L” pulse width tIHIL Value Pin name INT00 to INT09, EC0, EC1, TI1, TRG1 Min Max 2 tMCLK*   2 tMCLK* Unit ns ns *: See “Source Clock/Machine Clock” for tMCLK. tILIH INT00 to INT09, EC0, EC1, TI1, TRG1 Document Number: 002-04627 Rev. *G 0.8 VCC tIHIL 0.8 VCC 0.2 VCC 0.2 VCC Page 73 of 103 CY95630H Series 18.4.6 LIN-UART Timing Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Parameter Serial clock cycle time Symbol Pin name Condition Value Unit Min Max 5 tMCLK*3 — ns tSCYC SCK SCK  SOT delay time tSLOVI 50 50 ns Valid SIN  SCK tIVSHI tMCLK*3  80 — ns SCK  valid SIN hold time tSHIXI SCK, SOT Internal clock operation output pin: SCK, SIN CL = 80 pF  1 TTL SCK, SIN 0 — ns Serial clock “L” pulse width tSLSH SCK 3 tMCLK*3tR — ns Serial clock “H” pulse width tSHSL SCK tMCLK*3  10 — ns SCK  SOT delay time tSLOVE Valid SIN  SCK tIVSHE SCK  valid SIN hold time tSHIXE SCK, SOT External clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF  1 TTL — 2 tMCLK*3  60 ns 30 — ns tMCLK*3  30 — ns SCK falling time tF SCK — 10 ns SCK rising time tR SCK — 10 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC 0.8 VCC SCK 0.2 VCC 0.2 VCC tSLOVI 0.8 VCC SOT 0.2 VCC tIVSHI tSHIXI 0.7 VCC 0.7 VCC SIN 0.3 VCC 0.3 VCC Document Number: 002-04627 Rev. *G Page 74 of 103 CY95630H Series • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.8 VCC SCK 0.2 VCC tF 0.2 VCC tR tSLOVE 0.8 VCC SOT 0.2 VCC tIVSHE tSHIXE 0.7 VCC 0.7 VCC SIN 0.3 VCC 0.3 VCC Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Parameter Serial clock cycle time Symbol Pin name Value Condition Max 5 tMCLK*3 — ns 50 tSCYC SCK SCK  SOT delay time tSHOVI Valid SIN  SCK tIVSLI t SCK valid SIN hold time tSLIXI SCK, SOT Internal clock operation output pin: SCK, SIN CL = 80 pF  1 TTL SCK, SIN Serial clock “H” pulse width tSHSL SCK 3t Serial clock “L” pulse width tSLSH SCK t SCK  SOT delay time tSHOVE Valid SIN  SCK tIVSLE SCK valid SIN hold time tSLIXE SCK, SOT External clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF  1 TTL 50 ns MCLK 3 *  80 — ns 0 — ns * tR — ns *  10 — ns MCLK 3 MCLK 3 — t Unit Min 2t *  60 ns MCLK 3 30 — ns MCLK 3 *  30 — ns SCK falling time tF SCK — 10 ns SCK rising time tR SCK — 10 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “Source Clock/Machine Clock” for tMCLK. Document Number: 002-04627 Rev. *G Page 75 of 103 CY95630H Series • Internal shift clock mode tSCYC 0.8 VCC 0.8 VCC SCK 0.2 VCC tSHOVI 0.8 VCC SOT 0.2 VCC tIVSLI tSLIXI 0.7 VCC 0.7 VCC SIN 0.3 VCC 0.3 VCC • External shift clock mode tSHSL 0.8 VCC tSLSH 0.8 VCC SCK 0.2 VCC tR tF 0.2 VCC 0.2 VCC tSHOVE 0.8 VCC SOT 0.2 VCC tIVSLE tSLIXE 0.7 VCC 0.7 VCC SIN 0.3 VCC 0.3 VCC Document Number: 002-04627 Rev. *G Page 76 of 103 CY95630H Series Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Parameter Symbol Pin name Value Condition Serial clock cycle time tSCYC SCK SCK SOT delay time tSHOVI Valid SIN  SCK tIVSLI t SCK valid SIN hold time tSLIXI SCK, SOT Internal clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF  1 TTL SOT  SCKdelay time tSOVLI SCK, SOT 3t Unit Min Max 5 tMCLK*3 — ns 50 50 ns MCLK 3 *  80 — ns 0 — ns * 70 — ns MCLK 3 *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “Source Clock/Machine Clock” for tMCLK. tSCYC 0.8 VCC SCK 0.2 VCC SOT 0.2 VCC tSHOVI tSOVLI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tIVSLI SIN tSLIXI 0.7 VCC 0.7 VCC 0.3 VCC 0.3 VCC Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Parameter Symbol Pin name Value Condition Serial clock cycle time tSCYC SCK SCK  SOT delay time tSLOVI Valid SIN  SCK tIVSHI t SCK  valid SIN hold time tSHIXI SCK, SOT Internal clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF  1 TTL SOT  SCKdelay time tSOVHI SCK, SOT 3t Unit Min Max 5 tMCLK*3 — ns 50 50 ns MCLK 3 *  80 — ns 0 — ns * 70 — ns MCLK 3 *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “Source Clock/Machine Clock” for tMCLK. Document Number: 002-04627 Rev. *G Page 77 of 103 CY95630H Series tSCYC 0.8 VCC SCK 0.8 VCC 0.2 VCC tSOVHI SOT tSLOVI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tIVSHI SIN tSHIXI 0.7 VCC 0.7 VCC 0.3 VCC 0.3 VCC 18.4.7 Low-voltage Detection Parameter (VSS = 0.0 V, TA = 40°C to 85°C) Symbol Value Unit Remarks Min Typ Max 2.52 2.7 2.88 2.61 2.8 2.99 2.89 3.1 3.31 3.08 3.3 3.52 2.43 2.6 2.77 2.52 2.7 2.88 2.80 3 3.20 2.99 3.2 3.41 VHYS — — 100 mV Power supply start voltage Voff — — 2.3 V Power supply end voltage Von 4.9 — — V Power supply voltage change time (at power supply rise) tr 650 — — µs Slope of power supply that the reset release signal generates within the rating (VDL+) Power supply voltage change time (at power supply fall) tf 650 — — µs Slope of power supply that the reset detection signal generates within the rating (VDL-) Reset release delay time td1 — — 30 µs Reset detection delay time td2 — — 30 µs LVD reset threshold voltage transition stabilization time tstb 10 — — µs Release voltage* Detection voltage* Hysteresis width VDL VDL V At power supply rise V At power supply fall *: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID register (LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to “CHAPTER 16 LOWVOLTAGE DETECTION RESET CIRCUIT” in “New 8FX CY95630H Series Hardware Manual”. Document Number: 002-04627 Rev. *G Page 78 of 103 CY95630H Series VCC Von Voff time tf tr VDL+ VHYS VDL- Internal reset signal time td2 Document Number: 002-04627 Rev. *G td1 Page 79 of 103 CY95630H Series 18.4.8 I2C Bus Interface Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Value Parameter Standardmode Fast-mode Min Max Min Max 0 100 0 400 kHz SCL, SDA 4.0 — 0.6 — µs Symbol Pin name Condition SCL clock frequency fSCL (Repeated) START condition hold time SDA  SCL  tHD;STA SCL Unit SCL clock “L” width tLOW SCL 4.7 — 1.3 — µs SCL clock “H” width tHIGH SCL 4.0 — 0.6 — µs 4.7 — 0.6 — µs (Repeated) START condition setup time SCL  SDA  tSU;STA SCL, SDA Data hold time SCL  SDA  tHD;DAT SCL, SDA 0 3.45*2 0 0.9*3 µs Data setup time SDA  SCL  tSU;DAT SCL, SDA 0.25 — 0.1 — µs STOP condition setup time SCL   SDA  tSU;STO SCL, SDA 4 — 0.6 — µs tBUF SCL, SDA 4.7 — 1.3 — µs Bus free time between STOP condition and START condition R = 1.7 k, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT  250 ns is fulfilled. tWAKEUP SDA tLOW tHD;DAT tHIGH tHD;STA tBUF SCL tHD;STA Document Number: 002-04627 Rev. *G tSU;DAT fSCL tSU;STA tSU;STO Page 80 of 103 CY95630H Series (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Value*2 Pin Unit Remarks Parameter Symbol Condition name Min Max SCL clock tLOW SCL (2  nm/2)tMCLK  20 — ns Master mode “L” width SCL clock tHIGH SCL (nm/2)tMCLK  20 (nm/2)tMCLK  20 ns Master mode “H” width Master mode Maximum value is applied when START SCL, (-1  nm/2)tMCLK  20 (-1  nm)tMCLK  20 ns m, n = 1, 8. condition tHD;STA SDA Otherwise, the hold time minimum value is applied. STOP SCL, condition tSU;STO (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode SDA setup time START SCL, condition tSU;STA (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode SDA setup time Bus free time between STOP SCL, tBUF (2 nm  4) tMCLK  20 — ns condition SDA and START condition R = 1.7 k, SCL, Data hold C = 50 pF*1 3 tMCLK  20 — ns Master mode tHD;DAT SDA time Master mode It is assumed that “L” of SCL is not extended. The minimum value is Data setup SCL, tSU;DAT (-2  nm/2) tMCLK  20 (-1  nm/2) tMCLK  20 ns applied to the first time SDA bit of continuous data. Otherwise, the maximum value is applied. The minimum value is applied Setup time to the interrupt at between the ninth SCL. clearing tSU;INT SCL (nm/2) tMCLK  20 (1  nm/2) tMCLK  20 ns The maximum interrupt and value is applied SCL rising to the interrupt at the eighth SCL. SCL clock tLOW SCL 4 tMCLK  20 — ns At reception “L” width SCL clock tHIGH SCL 4 tMCLK  20 — ns At reception “H” width Document Number: 002-04627 Rev. *G Page 81 of 103 CY95630H Series (Continued) Parameter Symbol Pin Condition name START condition detection tHD;STA SCL, SDA STOP condition detection tSU;STO SCL, SDA RESTART condition detection condition tSU;STA SCL, SDA Bus free time tBUF Data hold time tHD;DAT Data setup time tSU;DAT Data hold time tHD;DAT Data setup time tSU;DAT SDA  SCL (with wakeup function in use) tWAKEUP SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA R = 1.7 k, C = 50 pF*1 (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Value*2 Unit Remarks Min Max No START condition is 2 tMCLK  20 — ns detected when 1 tMCLK is used at reception. No STOP condition is detected when 1 2 tMCLK  20 — ns tMCLK is used at reception. No RESTART condition is 2 tMCLK  20 — ns detected when 1 tMCLK is used at reception. 2 tMCLK  20 — ns At reception 2 tMCLK  20 — ns tLOW  3 tMCLK  20 — 0 — ns At reception tMCLK  20 — ns At reception Oscillation stabilization wait time 2 tMCLK  20 — ns At slave transmission mode At slave ns transmission mode *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: • See “Source Clock/Machine Clock” for tMCLK. • m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0). • n represents the CS[2:0] bits in the I2C clock control register ch. 0 (ICCR0). • The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK) and the CS[4:0] bits in the ICCR0 register. • Standard-mode: m and n can be set to values in the following range: 0.9 MHz  tMCLK (machine clock)  16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK  1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK  2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK  4 MHz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < tMCLK  10 MHz (m, n) = (8, 22) : 0.9 MHz < tMCLK  16.25 MHz • Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK  4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK  8 MHz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < tMCLK  10 MHz (m, n) = (5, 8) : 3.3 MHz < tMCLK  16.25 MHz Document Number: 002-04627 Rev. *G Page 82 of 103 CY95630H Series 18.4.9 UART/SIO, Serial I/O Timing Parameter (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Symbol Pin name Value Condition Unit Min Max 4 tMCLK* — ns 190 190 ns 2 tMCLK* — ns Serial clock cycle time tSCYC UCK0 UCK  UO time tSLOV UCK0, UO0 Valid UI  UCK  tIVSH UCK0, UI0 UCK  valid UI hold time tSHIX UCK0, UI0 2 tMCLK* — ns Serial clock “H” pulse width tSHSL UCK0 4 tMCLK* — ns Serial clock “L” pulse width tSLSH UCK0 4 tMCLK* — ns UCK  UO time tSLOV UCK0, UO0 — 190 ns Valid UI  UCK  tIVSH UCK0, UI0 2 tMCLK* — ns UCK  valid UI hold time tSHIX UCK0, UI0 2 tMCLK* — ns Internal clock operation External clock operation *: See “Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0, UCK1 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UO0, UO1 0.8 VCC 0.2 VCC tIVSH UI0, UI1 Document Number: 002-04627 Rev. *G tSHIX 0.7 VCC 0.7 VCC 0.3 VCC 0.3 VCC Page 83 of 103 CY95630H Series • External shift clock mode tSLSH tSHSL 0.8 VCC UCK0, UCK1 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 0.8 VCC UO0, UO1 0.2 VCC tIVSH tSHIX 0.7 VCC 0.7 VCC UI0, UI1 0.3 VCC 0.3 VCC 18.4.10 MPG Input Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C) Parameter Symbol Pin name Condition tTIWH, tTIWL SNI0 to SNI2, DTTI — Input pulse width Value Min Max 4 tMCLK — Unit Remarks ns 0.8 VCC 0.8 VCC SNI0 to SNI2, DTTI 0.2 VCC tTIWH 18.4.11 Comparator Timing Parameter 0.2 VCC tTIWL (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C) Pin name Value Min Typ Max Unit Remarks Voltage range CMP0_P, CMP0_N 0 — VCC  1.3 V Offset voltage CMP0_P, CMP0_N 15 — 15 mV Delay time CMP0_O — 650 1200 ns Overdrive 5 mV — 140 420 ns Overdrive 50 mV Power down delay CMP0_O — — 1200 ns Power down recovery PD: 1  0 Power up stabilization time CMP0_O — — 1200 ns Output stabilization time at power up Document Number: 002-04627 Rev. *G Page 84 of 103 CY95630H Series 18.5 A/D Converter 18.5.1 A/D Converter Electrical Characteristics Parameter (VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C) Value Symbol Unit Min Typ Max Resolution — — 10 bit Total error 3 — 3 LSB 2.5 — 2.5 LSB 1.9 — 1.9 LSB — Linearity error Differential linearity error Remarks Zero transition voltage V0T VSS 1.5 LSB VSS  0.5 LSB VSS  2.5 LSB V Full-scale transition voltage VFST VCC 4.5 LSB VCC 2 LSB VCC  0.5 LSB V — 3 — 10 µs 2.7 V  VCC  5.5 V 2.7 V  VCC  5.5 V, with external impedance  3.3 k and external capacitance = 10 pF Compare time Sampling time — 0.941 —  µs Analog input current IAIN 0.3 — 0.3 µA Analog input voltage VAIN VSS — VCC V 18.5.2 Notes on Using A/D Converter • External impedance of analog input and its sampling time The A/D converter of the CY95630H Series has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit Analog input Comparator R C During sampling: ON VCC 4.5 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 4.5 V R C 1.45 kΩ (Max) 2.7 kΩ (Max) 14.89 pF (Max) 14.89 pF (Max) Note: The values are reference values. Document Number: 002-04627 Rev. *G Page 85 of 103 CY95630H Series • Relationship between external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ] 100 External impedance [kΩ] 80 60 40 20 0 0 2 4 6 8 10 12 14 16 18 20 Minimum sampling time [μs] [External impedance = 0 kΩ to 20 kΩ] External impedance [kΩ] 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Minimum sampling time [μs] Note: External capacitance = 10 pF • A/D conversion error As |VCC  VSS| decreases, the A/D conversion error increases proportionately. Document Number: 002-04627 Rev. *G Page 86 of 103 CY95630H Series 18.5.3 Definitions of A/D Converter Terms • Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“0000000000”   “0000000001”) of a device to the full-scale transition point (“1111111111”   “1111111110”) of the same device. • Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. • Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. Ideal I/O characteristics Total error VFST 0x3FF 0x3FF 0x3FE 2 LSB 0x3FD Digital output Digital output 0x3FD 0x004 0x003 Actual conversion characteristic 0x3FE V0T {1 LSB × (N − 1) + 0.5 LSB} 0x004 VNT 0x003 1 LSB 0x002 0x002 0x001 Actual conversion characteristic Ideal characteristic 0x001 0.5 LSB VSS Analog input 1 LSB = VCC VCC − VSS V 1024 N VSS Analog input Total error of digital output N = VCC VNT − {1 LSB × (N − 1) + 0.5 LSB} LSB 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN Document Number: 002-04627 Rev. *G Page 87 of 103 CY95630H Series Zero transition error Full-scale transition error 0x004 Ideal characteristic Actual conversion characteristic 0x3FF Actual conversion characteristic 0x002 Ideal characteristic Digital output Digital output 0x003 Actual conversion characteristic 0x3FE VFST (measurement value) 0x3FD Actual conversion characteristic 0x001 0x3FC V0T (measurement value) VSS Analog input VCC VSS Linearity error 0x3FF 0x3FE Ideal characteristic 0x(N+1) Actual conversion characteristic {1 LSB × N + V0T} VFST Digital output Digital output 0x3FD (measurement value) VNT 0x004 0x002 VCC Differential linearity error Actual conversion characteristic V(N+1)T 0xN VNT 0x(N−1) Actual conversion characteristic 0x003 Analog input Ideal characteristic Actual conversion characteristic 0x(N−2) 0x001 V0T (measurement value) VSS Analog input VCC Linearity error of digital output N = VSS VCC VNT − {1 LSB × N + V0T} 1 LSB Differential linearity error of digital output N = N Analog input V(N+1)T − VNT − 1 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN V0T (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC − 2 LSB [V] Document Number: 002-04627 Rev. *G Page 88 of 103 CY95630H Series 18.6 Flash Memory Program/Erase Characteristics Parameter Value Unit Remarks 1.6*2 s The time of writing “0x00” prior to erasure is excluded. 0.6*1 3.1*2 s The time of writing “0x00” prior to erasure is excluded. 17 272 µs System-level overhead is excluded. Program/erase cycle 100000 — — cycle Power supply voltage at program/erase 2.4 — 5.5 V 20*3 — — Average TA = 85°C Number of program/erase cycles: 1000 or below 10*3 — — Average TA = 85°C year Number of program/erase cycles: 1001 to 10000 inclusive 5*3 — — Min Typ Max Sector erase time (2 Kbyte sector) — 0.3*1 Sector erase time (32 Kbyte sector) — Byte writing time — Flash memory data retention time Average TA = 85°C Number of program/erase cycles: 10001 or above *1: VCC = 5.5 V, TA = 25°C, 0 cycle *2: VCC = 2.4 V, TA = 85°C, 100000 cycles *3: These values were converted from the result of a technology reliability assessment. (These values were converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being 85°C.) Document Number: 002-04627 Rev. *G Page 89 of 103 CY95630H Series 19. Sample Characteristics • Power supply current temperature characteristics ICC  VCC TA  25C, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating ICC  TA VCC  5.5 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating 15 15 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 10 ICC[mA] ICC[mA] 10 5 5 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] ICCS  VCC TA  25C, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating +150 6 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 5 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 5 4 4 ICCS[mA] ICCS[mA] +100 ICCS  TA VCC  5.5 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating 6 3 3 2 2 1 1 0 0 1 2 3 4 5 6 7 −50 0 VCC[V] −50 +100 +150 TA[°C] ICCL  VCC TA  25C, FMPL  16 kHz (divided by 2) Subclock mode with the external clock operating ICCL  TA VCC  5.5 V, FMPL  16 kHz (divided by 2) Subclock mode with the external clock operating 140 140 120 120 100 100 80 80 ICCL[μA] ICCL[μA] +50 TA[°C] 60 60 40 40 20 20 0 0 1 2 3 4 5 VCC[V] Document Number: 002-04627 Rev. *G 6 7 −50 0 +50 +100 +150 TA[°C] Page 90 of 103 CY95630H Series ICCLS  VCC TA  25C, FMPL  16 kHz (divided by 2) Subsleep mode with the external clock operating ICCLS  TA VCC  5.5 V, FMPL  16 kHz (divided by 2) Subsleep mode with the external clock operating 30 20 20 ICCLS[μA] ICCLS[μA] 30 10 10 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +100 +150 ICCT  TA VCC  5.5 V, FMPL  16 kHz (divided by 2) Watch mode with the external clock operating 20 20 18 18 16 16 14 14 12 12 ICCT[μA] ICCT[μA] ICCT  VCC TA  25C, FMPL  16 kHz (divided by 2) Watch mode with the external clock operating 10 10 8 8 6 6 4 4 2 2 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +50 +100 +150 TA[°C] ICCTS  VCC TA  25C, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating ICCTS  TA VCC  5.5 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating 600 600 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 500 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 500 400 400 ICCTS[μA] ICCTS[μA] +50 TA[°C] 300 300 200 200 100 100 0 0 1 2 3 4 5 VCC[V] Document Number: 002-04627 Rev. *G 6 7 −50 0 +50 +100 +150 TA[°C] Page 91 of 103 CY95630H Series ICCH  VCC TA  25C, FMPL  (stop) Substop mode with the external clock stopping ICCH  TA VCC  5.5 V, FMPL  (stop) Substop mode with the external clock stopping 20 16 16 12 12 ICCH[μA] ICCH[μA] 20 8 8 4 4 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] ICCMCR  VCC TA  25C, FMP  4 MHz (no division) Main CR clock mode +100 +150 ICCMCR  TA VCC  5.5 V, FMP  4 MHz (no division) Main CR clock mode 10 10 8 8 6 6 ICCMCR[mA] ICCMCR[mA] +50 TA[°C] 4 2 4 2 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +50 +100 +150 TA[°C] 10 10 8 8 6 6 ICCMPLL[mA] ICCMPLL[mA] ICCMPLL  VCC ICCMPLL  TA TA  25C, FMP  16 MHz (PLL multiplication rate: 4) VCC  5.5 V, FMP  16 MHz (PLL multiplication rate: 4) Main CR PLL clock mode Main CR PLL clock mode 4 2 4 2 0 0 1 2 3 4 5 VCC[V] Document Number: 002-04627 Rev. *G 6 7 −50 0 +50 +100 +150 TA[°C] Page 92 of 103 CY95630H Series ICCSCR  TA VCC  5.5 V, FMPL  50 kHz (divided by 2) Sub-CR clock mode 200 200 150 150 ICCSCR[μA] ICCSCR[μA] ICCSCR  VCC TA  25C, FMPL  50 kHz (divided by 2) Sub-CR clock mode 100 100 50 50 0 0 1 2 3 4 5 VCC[V] Document Number: 002-04627 Rev. *G 6 7 −50 0 +50 +100 +150 TA[°C] Page 93 of 103 CY95630H Series • Input voltage characteristics VIHI  VCC and VILI  VCC TA  25C VIHS  VCC and VILS  VCC TA  25C 5 5 VIHI VILI VIHS VILS 4 3 3 VIHI/VILI[V] VIHS/VILS[V] 4 2 1 2 1 0 0 2 3 4 5 6 7 2 3 4 VCC[V] 5 6 7 VCC[V] VIHM  VCC and VILM  VCC TA  25C 5 VIHM VILM VIHM/VILM[V] 4 3 2 1 0 2 3 4 5 6 7 VCC[V] Document Number: 002-04627 Rev. *G Page 94 of 103 CY95630H Series • Output voltage characteristics (VCC  VOH2)  IOH TA  25C 1.4 1.4 1.2 1.2 1.0 1.0 VCC − VOH2[V] VCC − VOH1[V] (VCC  VOH1)  IOH TA  25C 0.8 0.6 0.8 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 IOH[mA] IOH[mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VOL1  IOL TA  25C VOL2  IOL TA  25C 1.4 1.0 1.2 0.8 0.6 0.8 VOL2[V] VOL1[V] 1.0 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IOL[mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V Document Number: 002-04627 Rev. *G 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IOL[mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V Page 95 of 103 CY95630H Series • Pull-up characteristics RPULL  VCC TA  25C 200 RPULL[kΩ] 150 100 50 0 1 2 3 4 5 6 VCC[V] Document Number: 002-04627 Rev. *G Page 96 of 103 CY95630H Series 20. Mask Options No. Part number Selectable/Fixed 1 2 Low-voltage detection reset Reset CY95F632K CY95F633K CY95F634K CY95F636K CY95F632H CY95F633H CY95F634H CY95F636H Fixed Without low-voltage detection reset With low-voltage detection reset With dedicated reset input Without dedicated reset input 21. Ordering Information Part number CY95F632KPMC-G-UNE2 CY95F633KPMC-G-UNE2 CY95F634HPMC-G-UNE2 CY95F634KPMC-G-UNE2 CY95F636KPMC-G-UNE2 CY95F633HPMC-G-UNERE2 Document Number: 002-04627 Rev. *G Package Packing 32-pin plastic LQFP (LQB032) Tray Reel Page 97 of 103 CY95630H Series 22. Package Dimension Package Type Package Code LQFP 32 LQB032 4 D D1 24 5 7 17 17 25 16 E1 6 32 8 e 0.20 C A-B D b 0.20 C A-B TOP VIEW 9 32 8 2 5 7 1 BOTTOM VIEW 0.10 C A-B D 3 25 4 9 1 16 E 5 7 3 24 D 8 2 9 θ A A' 0.10 C SEATING PLANE c b SECTION A-A' 0.25 10 SIDE VIEW SYMBOL DIMENSIONS MIN. NOM. MAX. 0.05 0.15 1.60 A A1 b 0.32 c 0.13 0.35 0.43 0.18 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 32 LEAD LQFP 7.0X7.0X1.6 MM LQB032 REV*.* 002-13879 ** Document Number: 002-04627 Rev. *G Page 98 of 103 CY95630H Series Package Type Package Code SDIP 32 PDS032 002-16908 ** Document Number: 002-04627 Rev. *G Page 99 of 103 CY95630H Series Package Type Package Code QFN 32 WNP032 002-15160 ** Document Number: 002-04627 Rev. *G Page 100 of 103 CY95630H Series 23. Major Changes In This Edition Spansion Publication Number: DS702-00009 Page Section Details 22 ■ PIN CONNECTION • C pin 66 ■ ELECTRICAL CHARACTERISTICS Corrected the following statement in remark *2. 2. Recommended Operating Conditions The bypass capacitor for the VCC pin must have a capacitance larger than CS.  The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. 71 4. AC Characteristics (1) Clock Timing Corrected the following statement. The bypass capacitor for the VCC pin must have a capacitance larger than CS.  The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. Corrected the pin names of the parameter “Input clock rising time and falling time”. X0  X0, X0A X0, X1  X0, X1, X0A, X1A NOTE: Please see “Document History” about later revised information. Document Number: 002-04627 Rev. *G Page 101 of 103 CY95630H Series Document History Page Document Title: CY95630H Series, New 8FX 8-bit Microcontrollers Document Number: 002-04627 Revision ECN Submission Date ** – 06/07/2013 Migrated to Cypress and assigned document number 002-04627. No change to document contents or format. *A 5193921 03/29/2016 Updated Ordering Information: Updated part numbers. Updated to Cypress template. *B 5443796 02/06/2017 Replaced “FPT-32P-M30” with “LQB032” in all instances across the document. Replaced “LCC-32P-M19” with “WNP032” in all instances across the document. Replaced “DIP-32P-M06” with “PDS032” in all instances across the document. Updated Ordering Information: Updated part numbers. *C 5746267 05/23/2017 Updated Cypress Logo and Copyright. *D 5895915 09/27/2017 Updated Ordering Information: Updated part numbers. Added a column “Packing” and added details in that column. *E 6599271 06/19/2019 Updated Ordering Information: Updated part numbers. Updated to new template. Description of Change *F 6730588 11/13/2019 Updated series name and part number from prefix MB to prefix CY. *G 6748761 12/10/2019 Added ordering part numbers: CY95F632KPMC-G-UNE2 CY95F633KPMC-G-UNE2 CY95F634KPMC-G-UNE2 CY95F636KPMC-G-UNE2 Document Number: 002-04627 Rev. *G Page 102 of 103 CY95630H Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2011–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). 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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04627 Rev. *G Revised December 10, 2019 Page 103 of 103