PALCE22V10-5JC

22V10 PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL® Device Features • Low power — 90 mA max. commercial (10 ns) — 130 mA max. commercial (5 ns) • CMOS Flash EPROM technology for electrical erasability and reprogrammability • Variable product terms — 2 x(8 through 16) product terms • User-programmable macrocell — Output polarity control — Individually selectable for registered or combinatorial operation • Up to 22 input terms and 10 outputs • DIP, LCC, and PLCC available — 5 ns commercial version 4 ns tCO 3 ns tS 5 ns tPD 181-MHz state machine — 10 ns military and industrial versions 7 ns tCO 6 ns tS 10 ns tPD 110-MHz state machine — 15-ns commercial, industrial, and military versions — 25-ns commercial, industrial, and military versions • High reliability — Proven Flash EPROM technology — 100% programming and functional testing Functional Description The Cypress PALCE22V10 is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell. Logic Block Diagram (PDIP/CDIP) V SS 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 CP/I 1 PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 16 16 14 12 10 8 Reset Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Preset 13 I 14 I/O9 15 I/O8 16 I/O 7 17 I/O6 18 I/O5 19 I/O4 20 I/O3 21 I/O2 22 I/O1 23 I/O0 24 V CC CE22V10–1 Pin Configuration I I CP/I NC V CC I/O0 I/O1 4 3 2 1 282726 I I I NC I I I 5 6 7 8 9 10 11 12131415161718 V SS NC I/O9 I/O8 CE22V10–2 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 I I I NC I I I 5 6 7 8 9 10 11 I I CP/I NC V CC I/O0 I/O1 4 3 2 1 2827 26 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 CE22V10–3 121314 1516 1718 V SS NC LCC Top View PLCC Top View PAL is a registered trademark of Advanced Micro Devices. Cypress Semiconductor Corporation Document #: 38-03027 Rev. ** • 3901 North First Street • San Jose I/O9 I/O8 I I I I I I • CA 95134 • 408-943-2600 Revised September 1996 PALCE22V10 Selection Guide tPD ns Generic Part Number PALCE22V10-5 PALCE22V10-7 PALCE22V10-10 PALCE22V10-15 PALCE22V10-25 Com’l 5 7.5 10 15 25 10 15 25 Mil/Ind 3 5 6 10 15 6 10 15 tS ns Com’l Mil/Ind 4 5 7 8 15 7 8 15 tCO ns Com’l Mil/Ind ICC mA Com’l 130 130 90 90 90 150 120 120 Mil/Ind Functional Description (continued) The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The PALCE22V10 can be electrically erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as “registered” or “combinatorial.” Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through “array” configurable “output enable” for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array. PALCE22V10 features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PALCE 22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity. Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, func- tions requiring up to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALCE22V10 provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Configuration Table Registered/Combinatorial C1 0 0 1 1 C0 0 1 0 1 Configuration Registered/Active LOW Registered/Active HIGH Combinatorial/Active LOW Combinatorial/Active HIGH Document #: 38-03027 Rev. ** Page 2 of 13 PALCE22V10 Macrocell AR OUTPUT SELECT MUX D Q CP Q S1 S0 SP INPUT/ FEEDBACK MUX S1 C1 C0 MACROCELL CE22V10–4 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Output Current into Outputs (LOW) .............................16 mA Note: 1. TA is the “instant on” case temperature. DC Programming Voltage............................................. 12.5V Latch-Up Current..................................................... >200 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2001V Operating Range Range Commercial Industrial Military[1] Ambient Temperature 0°C to +75°C –40°C to +85°C –55°C to +125°C VCC 5V ±5% 5V ±10% 5V ±10% Document #: 38-03027 Rev. ** Page 3 of 13 PALCE22V10 ] Electrical Characteristics Over the Operating Range[2] Parameter VOH VOL VIH VIL[4] IIX IOZ ISC ICC1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Standby Power Supply Current VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL Test Conditions IOH = –3.2 mA IOH = –2 mA IOL = 16 mA IOL = 12 mA Com’l Mil/Ind Com’l Mil/Ind 2.0 –0.5 –10 –40 –30 Com’l Mil/Ind Com’l Com’l Mil/Ind Mil/Ind 0.8 10 40 –130 90 130 120 120 110 140 130 130 V V µA µA mA mA mA mA mA mA mA mA mA 0.5 V Min. 2.4 Max. Unit V Guaranteed Input Logical HIGH Voltage for All Inputs[3] Guaranteed Input Logical LOW Voltage for All Inputs[3] VSS < VIN < VCC, VCC = Max. VCC = Max., VSS < VOUT < VCC VCC = Max., VIN = GND, Outputs Open in Unprogrammed Device VCC = Max., VIL = 0V, VIH = 3V, Output Open, Device Programmed as a 10-Bit Counter, f = 25 MHz 10, 15, 25 ns 5, 7.5 ns 15, 25 ns 10 ns 10, 15, 25 ns 5, 7.5 ns 15, 25 ns 10 ns Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,6] ICC2[6] Operating Power Supply Current Capacitance[6] Parameter CIN COUT ] Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz Min. Max. 10 10 Unit pF pF Endurance Characteristics[6] Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions Min. 100 Max. Unit Cycles Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03027 Rev. ** Page 4 of 13 PALCE22V10 AC Test Loads and Waveforms R1238 Ω (319Ω MIL) R1238 Ω (319Ω MIL) OUTPUT CL 750Ω (1.2KΩ MIL) 5V OUTPUT 5V R2170 Ω (236Ω MIL) OUTPUT CL INCLUDING JIG AND SCOPE 5 pF INCLUDING JIG AND SCOPE R2170 Ω (236Ω MIL) (a) (b) ALL INPUT PULSES 3.0V 90% GND < 2 ns 10% 90% 10% < 2 ns CE22V10–5 (c) (d) Equivalent to: OUTPUT THÉ VENIN EQUIVALENT (Commercial) 99Ω 2.08V=V thc CE22V10–6 Equivalent to: OUTPUT THÉ VENIN EQUIVALENT (Military) 136Ω 2.13V=V thm CE22V10–7 Load Speed 5, 7.5, 10, 15, 25 ns CL 50 pF Package PDIP, CDIP, PLCC, LCC Parameter t ER () VX 1.5V 2.6V 0V V thc V OH V OL VX VX Output W aveform Measurement Level 0.5V 0.5V 1.5V VX VX V OH t ER (+) t EA t EA (+) (- ) 0.5V (e) Test Waveforms V OL Document #: 38-03027 Rev. ** Page 5 of 13 PALCE22V10 ] Commercial Switching Characteristics PALCE22V10[2,7] 22V10-5 Parameter tPD tEA tER tCO tS1 tS2 tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tAW tAR tAP tSPR tPR Description Input to Output Propagation Delay[8] Input to Output Enable Delay[9] Input to Output Disable Delay[10] Clock to Output Delay[8] Input or Feedback Set-Up Time Synchronous Preset Set-Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH Clock Width LOW [6] [6] 22V10-7 Min. 3 Max. 7.5 8 8 2 5 6 0 10 3 3 100 166 133 5 22V10-10 Min. 3 Max. 10 10 10 2 6 7 0 12 3 3 76.9 142 111 7 22V10-15 Min. 3 Max. 15 15 15 2 10 10 0 20 6 6 55.5 83.3 68.9 8 22V10-25 Min. 3 Max. 25 25 25 2 15 15 0 30 13 13 33.3 35.7 38.5 15 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 13 25 25 ns ns ns 25 15 1 ns ns µs Min. 3 Max. 5 6 6 2 3 4 0 7 2.5 2.5 143 200 181 4 External Maximum Frequency (1/(tCO + tS))[11] Data Path Maximum Frequency (1/(tWH + tWL))[6, 12] Internal Feedback Maximum Frequency (1/(tCF + tS))[6,13] Register Clock to Feedback Input[6,14] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Delay Synchronous Preset Recovery Time Power-Up Reset Time[6,15] 2.5 8 4 7.5 4 1 6 1 8 5 2.5 10 6 12 8 1 3 15 10 13 10 1 4.5 20 Notes: 7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test Loads and Waveforms is used for tEA(+). 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS. 15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied Document #: 38-03027 Rev. ** Page 6 of 13 PALCE22V10 Military and Industrial Switching Characteristics PALCE22V10[2,7] 22V10-10 Parameter tPD tEA tER tCO tS1 tS2 tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tAW tAR tAP tSPR tPR Description Input to Output Propagation Delay[8] Input to Output Enable Delay[9] Input to Output Disable Delay Clock to Output Delay[8] Input or Feedback Set-Up Time Synchronous Preset Set-Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH Clock Width LOW [6] [6] [10] 22V10-15 Min. 3 Max. 15 15 15 2 10 10 0 20 6 6 50.0 83.3 68.9 8 22V10-25 Min. 3 Max. 25 25 25 2 18 18 0 33 14 14 30.3 35.7 32.2 15 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 13 25 25 ns ns ns 25 25 1 ns ns µs Min. 3 Max. 10 10 10 2 6 7 0 12 3 3 76.9 142 111 7 External Maximum Frequency (1/(tCO + tS))11] Data Path Maximum Frequency (1/(tWH + tWL))[6,12 ] Internal Feedback Maximum Frequency (1/(tCF + tS))[6,13] Register Clock to Feedback Input[6,14] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Delay Synchronous Preset Recovery Time Power-Up Reset Time[6,15] 3 10 6 12 8 1 20 1 15 12 4.5 20 Document #: 38-03027 Rev. ** Page 7 of 13 PALCE22V10 Switching Waveforms INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET CP t SPR t AW ASYNCHRONOUS RESET REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS tER [10] tS tH t WH t WL tP t AR t CO t AP tER [10] tEA [9] tEA [9] CE22V10–8 Power-Up Reset Waveform[15] POWER SUPPLY VOLTAGE REGISTERED ACTIVE LOW OUTPUTS CLOCK tPR MAX = 1 µs t WL CE22V10–9 10% 90% t PR VCC tS Document #: 38-03027 Rev. ** Page 8 of 13 PALCE22V10 Functional Logic Diagram for PALCE22V10 1 0 AR OE 0 4 8 12 16 20 24 28 32 36 40 S S S 7 OE 0 Macro– cell 23 S S S 2 9 OE 0 Macro– cell 22 S S S 3 11 OE 0 Macro– cell 21 S S S 4 13 OE 0 Macro– cell 20 S S S 15 OE 0 Macro– cell 19 5 S S S 15 OE 0 Macro– cell 18 6 S S S 7 13 OE 0 Macro– cell 17 S S S 11 Macro– cell 16 8 OE 0 S S S 9 Macro– cell 15 9 OE 0 S S S 7 Macro– cell 14 10 SP 11 CE22V10–10 13 Document #: 38-03027 Rev. ** Page 9 of 13 PALCE22V10 Ordering Information ICC (mA) 130 130 90 150 150 tPD (ns) 5 7.5 10 10 10 tS (ns) 3 5 6 6 6 tCO (ns) 4 5 7 7 7 Ordering Code PALCE22V10-5PC PALCE22V10-5JC PALCE22V10-7JC PALCE22V10-7PC PALCE22V10-10JC PALCE22V10-10PC PALCE22V10-10JI PALCE22V10-10PI PALCE22V10-10DMB PALCE22V10-10KMB PALCE22V10-10LMB 90 120 120 15 15 15 7.5 7.5 7.5 10 10 10 PALCE22V10-15JC PALCE22V10-15PC PALCE22V10-15JI PALCE22V10-15PI PALCE22V10-15DMB PALCE22V10-15KMB PALCE22V10-15LMB 90 120 120 25 25 25 15 15 15 15 15 15 PALCE22V10-25JC PALCE22V10-25PC PALCE22V10-25JI PALCE22V10-25PI PALCE22V10-25DMB PALCE22V10-25KMB PALCE22V10-25LMB Package Name P13 J64 J64 P13 J64 P13 J64 P13 D14 K73 L64 J64 P13 J64 P13 D14 K73 L64 J64 P13 J64 P13 D14 K73 L64 Package Type 24-Lead (300 MIL) Molded DIP 28-Lead Plastic Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier Military Industrial Commercial Military Industrial Commercial Military Industrial Commercial Commercial Operating Range Commercial MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter tPD tCO tS tH Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38-03027 Rev. ** Page 10 of 13 PALCE22V10 Package Diagrams 24–Lead (300–Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 28–Lead Plastic Leaded Chip Carrier J64 24–Lead Rectangular Cerpack K73 MIL-STD-1835 F- 6 Config.A 28–Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 Document #: 38-03027 Rev. ** Page 11 of 13 PALCE22V10 Package Diagrams (continued) 24–Lead (300–Mil) Molded DIP P13/P13A Document #: 38-03027 Rev. ** Page 12 of 13 © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PALCE22V10 Document Title: PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL® Device Document Number: 38-03027 REV. ** ECN NO. 106372 Issue Date 07/11/01 Orig. of Change SZV Description of Change Change from Spec Number: 38-00447 to 38-03027 Document #: 38-03027 Rev. ** Page 13 of 13