S6E1C12D0AGV20000

S6E1C1 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller The S6E1C1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of 2 2 peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I C, I S, and Smart Card). The products which are described in this data sheet are placed into TYPE3-M0+ product categories in "FM0+ Family Peripheral Manual". Features  CSIO (also known as SPI) 32-bit ARM Cortex-M0+ Core  Full duplex double buffer dedicated baud rate generator  Overrun error detection function  Serial chip select function (ch1 and ch6 only)  Data length: 5 to 16 bits  Built-in  Processor version: r0p1  Maximum operating frequency: 40.8 MHz  Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels  I2 C  Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400 kbps) supported.  24-bit System timer (Sys Tick): System timer for OS task management  I2S (MFS-I2S) CSIO (Max 2 ch: ch.4, ch.6) and I S clock generator  Supports two transfer protocol 2 • IS • MSB-justified  Master mode only Compatible with Cortex-M3 bit band operation. On-Chip Memory  Flash memory I2C Slave  Up to 128 Kbytes cycle: 0 wait-cycle  Security function for code protection  Read  I2C Slave supports the slave function of I2C and wake-up function from Standby mode.  SRAM The on-chip SRAM of this series has one independent SRAM .  Up to 16 Kbytes  4Kbytes: can retain value in Deep standby Mode Descriptor System Data Transfer Controller (DSTC) (64 Channels)  The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor that has already been constructed on the memory, can access directly the memory / peripheral device and performs the data transfer operation. Multi-Function Serial Interface (Max 6channels)  3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels without FIFO (Ch.0, 1 and 3)  The operation mode of each channel can be selected from one of the following.  UART  CSIO (CSIO is known to many customers as SPI) 2 I C  It supports the software activation, the hardware activation, and the chain activation functions A/D Converter (Max: 8 Channels)  12-bit A/D Converter  UART duplex double buffer  Parity can be enabled or disabled.  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4)  * : S6E1C12B0A/S6E1C11B0A and S6E1C12C0A/S6E1C11C0A do not support Hardware Flow control.  Various error detection functions (parity errors, framing errors, and overrun errors)  Successive approximation type time: 2.0 μs @ 2.7 V to 3.6 V  Priority conversion available (2 levels of priority)  Scan conversion mode  Built-in FIFO for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4 steps)  Full Cypress Semiconductor Corporation Document Number: 002-00234 Rev.*A 2  Using Bit Band Operation •  Conversion Base Timer (Max: 8 Channels) The operation mode of each channel can be selected from one of the following. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 9, 2015 S6E1C1 Series  16-bit PWM timer External Interrupt Controller Unit  16-bit PPG timer  Up to 12 external interrupt input pins  16/32-bit reload timer  Non-maskable interrupt (NMI) input pin: 1  16/32-bit PWC timer General-Purpose I/O Port This series can use its pin as a general-purpose I/O port when it is not used for an external bus or a peripheral function. All ports can be set to fast general-purpose I/O ports or slow general-purpose I/O ports. In addition, this series has a port relocate function that can set to which I/O port a peripheral function can be allocated.  All ports are Fast GPIO which can be accessed by 1cycle  Capable of controlling the pull-up of each pin  Capable of reading pin level directly  Port relocate function  Up to 54 fast general-purpose I/O ports @64-pin package  Certain ports are 5 V tolerant. See 4.List of Pin Functions and 5.I/O Circuit Type for the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. The operation mode of each timer channel can be selected from one of the following.  Free-running mode  Periodic mode (= Reload mode)  One-shot mode Real-Time Clock The Real-time Clock counts year/month/day/hour/minute/second/day of the week from year 00 to year 99.  The RTC can generate an interrupt at a specific time (year/month/day/hour/minute/second/day of the week) and can also generate an interrupt in a specific year, in a specific month, on a specific day, at a specific hour or at a specific minute.  It has a timer interrupt function generating an interrupt upon a specific time or at specific intervals.  It can keep counting while rewriting the time.  It can count leap years automatically. Watch Counter The Watch Counter wakes up the microcontroller from the low power consumption mode. The clock source can be selected from the main clock, the sub clock, the built-in high-speed CR clock or the built-in low-speed CR clock. Interval timer: up to 64 s (sub clock: 32.768 kHz) Document Number: 002-00234 Rev.*A Watchdog Timer (2 Channels) The watchdog timer generates an interrupt or a reset when the counter reaches a time-out value. This series consists of two different watchdogs, hardware watchdog and software watchdog. The hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep standby RTC and Deep standby Stop mode. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage.  CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021 CRC32 Generator Polynomial: 0x04C11DB7  IEEE-802.3 HDMI-CEC/Remote Control Receiver (Up to 2 Channels)  HDMI-CEC transmitter  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  HDMI-CEC receiver  Automatic  Line ACK reply function available error detection function available  Remote control receiver 4 bytes reception buffer code detection function available  Repeat Smart Card Interface (Max 1 Channel)  Compliant with ISO7816-3 specification  Card Reader only/B class card only  Available protocols  Transmitter: 8E2, 8O2, 8N2 8E1, 8O1, 8N2, 8N1, 9N1  Inverse mode  Receiver:  TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes) Clock and Reset  Clocks A clock can be selected from five clock sources (two external oscillators, two built-in CR oscillator, and main PLL).  Main clock: 8 MHz to 48 MHz Page 2 of 100 S6E1C1 Series  Sub clock: high-speed CR clock:  Built-in low-speed CR clock:  Main PLL clock  Built-in 32.768 kHz 8 MHz 100 kHz 8MHz to 16MHz (Input), 75MHz to 150MHz (Output)  Resets  Reset request from the INITX pin  Power on reset  Software reset  Watchdog timer reset  Low-voltage detection reset  Clock supervisor reset Clock Supervisor (CSV) The Clock Supervisor monitors the failure of external clocks with a clock generated by a built-in CR oscillator. Low Power Consumption Mode This series has six low power consumption modes.  Sleep  Timer  RTC  Stop  Deep standby RTC (selectable between keeping the value of RAM and not)  Deep standby Stop (selectable between keeping the value of RAM and not) Peripheral Clock Gating  If an external clock failure (clock stop) is detected, a reset is The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used.  If an external frequency anomaly is detected, an interrupt or Debug asserted. a reset is asserted. Low-Voltage Detector (LVD) This series monitors the voltage on the VCC pin with a 2-stage mechanism. When the voltage falls below a designated voltage, the Low-voltage Detector generates an interrupt or a reset.  LVD1: monitor VCC and error reporting via an interrupt  LVD2: auto-reset operation Document Number: 002-00234 Rev.*A  Serial Wire Debug Port (SW-DP)  Micro Trace Buffer (MTB) Unique ID A 41-bit unique value of the device has been set. Power Supply  Wide voltage range: VCC = 1.65V to 3.6 V Page 3 of 100 S6E1C1 Series Table of Contents Features................................................................................................................................................................................... 1 1. Product Lineup .................................................................................................................................................................. 5 2. Packages ........................................................................................................................................................................... 6 3. Pin Assignment ................................................................................................................................................................. 7 4. List of Pin Functions....................................................................................................................................................... 13 5. I/O Circuit Type................................................................................................................................................................ 26 6. Handling Precautions ..................................................................................................................................................... 31 6.1 Precautions for Product Design ................................................................................................................................... 31 6.2 Precautions for Package Mounting .............................................................................................................................. 32 6.3 Precautions for Use Environment ................................................................................................................................ 34 7. Handling Devices ............................................................................................................................................................ 35 8. Block Diagram ................................................................................................................................................................. 38 9. Memory Map .................................................................................................................................................................... 39 10. Pin Status in Each CPU State ........................................................................................................................................ 42 11. Electrical Characteristics ............................................................................................................................................... 45 11.1 Absolute Maximum Ratings ......................................................................................................................................... 45 11.2 Recommended Operating Conditions.......................................................................................................................... 46 11.3 DC Characteristics....................................................................................................................................................... 47 11.3.1 Current Rating .............................................................................................................................................................. 47 11.3.2 Pin Characteristics ....................................................................................................................................................... 52 11.4 AC Characteristics ....................................................................................................................................................... 53 11.4.1 Main Clock Input Characteristics .................................................................................................................................. 53 11.4.2 Sub Clock Input Characteristics ................................................................................................................................... 54 11.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 55 11.4.4 Operating Conditions of Main PLL (In the Case of Using the Main Clock as the Input Clock of the PLL) .................... 56 11.4.5 Operating Conditions of Main PLL (In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL) ........................................................................................................................................................... 56 11.4.6 Reset Input Characteristics .......................................................................................................................................... 57 11.4.7 Power-on Reset Timing................................................................................................................................................ 57 11.4.8 Base Timer Input Timing .............................................................................................................................................. 58 11.4.9 CSIO/SPI/UART Timing ............................................................................................................................................... 59 11.4.10 External Input Timing ................................................................................................................................................ 76 2 11.4.11 I C Timing / I2C Slave Timing ................................................................................................................................... 77 2 11.4.12 I S Timing (MFS-I2S Timing) .................................................................................................................................... 78 11.4.13 Smart Card Interface Characteristics ........................................................................................................................ 80 11.4.14 SW-DP Timing .......................................................................................................................................................... 81 11.5 12-bit A/D Converter .................................................................................................................................................... 82 11.6 Low-Voltage Detection Characteristics ........................................................................................................................ 85 11.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 85 11.6.2 Low-Voltage Detection Interrupt ................................................................................................................................... 86 11.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 87 11.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 88 11.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 88 11.8.2 Return Factor: Reset .................................................................................................................................................... 90 12. Ordering Information ...................................................................................................................................................... 92 13. Package Dimensions ...................................................................................................................................................... 93 Document History ................................................................................................................................................................. 99 Sales, Solutions, and Legal Information........................................................................................................................... 100 Document Number: 002-00234 Rev.*A Page 4 of 100 S6E1C1 Series 1. Product Lineup Memory Size Product name On-chip Flash memory On-chip SRAM Function Product name Pin count S6E1C11B0A/ S6E1C11C0A/ S6E1C11D0A 64 Kbytes 12 Kbytes S6E1C12B0A/ S6E1C12C0A/ S6E1C12D0A 128 Kbytes 16 Kbytes S6E1C12B0A/ S6E1C11B0A 32 S6E1C12C0A/ S6E1C12C0A 48 Cortex-M0+ 40.8 MHz 1.65 V to 3.6 V 64 ch. 6 ch. (Max) Ch.0/1/3 without FIFO Ch.4/6/7 with FIFO I2S : 1 ch (Max) Ch. 6 with FIFO CPU Frequency Power supply voltage range DSTC Multi-function Serial Interface 2 (UART/CSIO/I C/I2S) Base Timer (PWC/Reload timer/PWM/PPG) Dual Timer HDMI-CEC/ Remote Control Receiver I2C Slave Smart Card Interface Real-time Clock Watch Counter CRC Accelerator Watchdog timer External Interrupt 4 ch. (Max) Ch.0/1/3 without FIFO Ch. 6 with FIFO I2S : No S6E1C11D0A/ S6E1C12D0A 64 6 ch. (Max) Ch.0/1/3 without FIFO Ch.4/6/7 with FIFO I2S : 2 ch (Max) Ch. 4/6 with FIFO 8 ch. (Max) 1 unit 1 ch.(Max) Ch.1 2 ch (Max) Ch.0/1 1 ch (Max) No 7 pins (Max), NMI x 1 24 pins (Max) 6 ch. (1 unit) 1 unit 1 unit Yes 1 ch. (SW) + 1 ch. (HW) 9 pins (Max), NMI x 1 38 pins (Max) 8 ch. (1 unit) Yes 2 ch. 8 MHz (Typ) 100 kHz (Typ) SW-DP Yes 1 ch (Max) 12 pins (Max), NMI x 1 54 pins (Max) 8 ch. (1 unit) I/O port 12-bit A/D converter CSV (Clock Supervisor) LVD (Low-voltage Detection) High-speed Built-in CR Low-speed Debug Function Unique ID Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See "11. Electrical Characteristics 11.4 AC Characteristics 11.4.3 Built-in CR Oscillation Characteristics" for accuracy of built-in CR. Document Number: 002-00234 Rev.*A Page 5 of 100 S6E1C1 Series 2. Packages Product name Package LQFP: FPT-32P-M30 (0.80 mm pitch) QFN: LCC-32P-M73 (0.50 mm pitch) LQFP: FPT-48P-M49 (0.50 mm pitch) QFN: LCC-48P-M74 (0.50 mm pitch) LQFP: FPT-64P-M38 (0.50 mm pitch) QFN: LCC-64P-M25 (0.50 mm pitch) : Available S6E1C12B0A/ S6E1C11B0A S6E1C12C0A/ S6E1C11C0A  - S6E1C12D0A/ S6E1C11D0A -  -  - -  - - -  - -  Note: See "13. Package Dimensions" for detailed information on each package. − Document Number: 002-00234 Rev.*A Page 6 of 100 S6E1C1 Series 3. Pin Assignment FPT-64P-M38 (TOP VIEW) Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00234 Rev.*A Page 7 of 100 S6E1C1 Series LCC-64P-M25 (TOP VIEW) Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00234 Rev.*A Page 8 of 100 S6E1C1 Series FPT-48P-M49 (TOP VIEW) Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00234 Rev.*A Page 9 of 100 S6E1C1 Series LCC-48P-M74 (TOP VIEW) Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00234 Rev.*A Page 10 of 100 S6E1C1 Series FPT-32P-M30 (TOP VIEW) Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00234 Rev.*A Page 11 of 100 S6E1C1 Series LCC-32P-M73 (TOP VIEW) Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00234 Rev.*A Page 12 of 100 S6E1C1 Series 4. List of Pin Functions List of Pin Numbers The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Pin no. LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 1 1 2 Pin Function P50 SIN3_1 I/O circuit type Pin state type D K D K D K D K D K H K H K H K H K INT00_0 P51 2 2 3 3 3 4 SOT3_1 INT01_0 P52 SCK3_1 INT02_0 P53 4 4 - TIOA1_2 INT07_2 P30 SCS60_1 5 5 - TIOB0_1 INT03_2 MI2SWS6_1 P31 6 6 - SCK6_1 SI2CSCL6_1 INT04_2 MI2SCK6_1 - - 5 P31 SCK6_1 SI2CSCL6_1 INT04_2 P32 SOT6_1 7 7 - SI2CSDA6_1 TIOB2_1 INT05_2 MI2SDO6_1 P32 SOT6_1 - - 6 SI2CSDA6_1 TIOB2_1 INT05_2 Document Number: 002-00234 Rev.*A Page 13 of 100 S6E1C1 Series Pin no. LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 Pin Function I/O circuit type Pin state type H K H K D K D K D K D K D K D K D K D K D K D K P33 ADTG_6 8 8 - SIN6_1 INT04_0 MI2SDI6_1 P33 - - 7 ADTG_6 SIN6_1 INT04_0 P34 9 - - SCS61_1 TIOB4_1 MI2SMCK6_1 P34 - 10 9 - - - SCS61_1 MI2SMCK6_1 P35 SCS62_1 TIOB5_1 INT08_1 P3A TIOA0_1 11 - - INT03_0 RTCCO_2 SUBOUT_2 IC1_CIN_0 P3A TIOA0_1 - 10 - INT03_0 RTCCO_2 SUBOUT_2 P3B 12 - - - 11 - 13 - - - 12 - 14 - - Document Number: 002-00234 Rev.*A TIOA1_1 IC1_DATA_0 P3B TIOA1_1 P3C TIOA2_1 IC1_RST_0 P3C TIOA2_1 P3D TIOA3_1 IC1_VPEN_0 Page 14 of 100 S6E1C1 Series Pin no. LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 15 - - Pin Function P3E TIOA4_1 I/O circuit type Pin state type D K IC1_VCC_0 P3F 16 - - TIOA5_1 IC1_CLK_0 D K 17 13 8 I F 18 14 9 MD0 PE2 A A 19 15 10 A B 20 - - D K 21 - - D K D K D K D K D K D K 22 - - 23 - - 24 - - X0 PE3 X1 P40 TIOA0_0 INT12_1 P41 TIOA1_0 INT13_1 P42 TIOA2_0 P43 ADTG_7 TIOA3_0 P4C SCK7_1 TIOB3_0 P4C - 16 - 25 17 - 26 18 - SIN7_1 INT06_2 D K 27 28 19 20 11 12 VCC C - - 29 21 13 - - 30 22 14 VSS P46 C C 31 23 15 C D 32 24 16 B E H K 33 25 17 Document Number: 002-00234 Rev.*A SCK7_1 P4D SOT7_1 P4E X0A P47 X1A INITX P60 TIOA2_2 INT15_1 CEC1_0 Page 15 of 100 S6E1C1 Series Pin no. LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 34 - - Pin Function P1E RTS4_1 I/O circuit type Pin state type D K D K D K D K D K H K H K D K F J G J F J F J F J MI2SMCK4_1 P1D 35 - - 36 - - CTS4_1 MI2SWS4_1 P1C SCK4_1 MI2SCK4_1 P1B 37 - - - 26 - SOT4_1 MI2SDO4_1 P1B SOT4_1 P1A SIN4_1 38 - - INT05_1 CEC0_0 MI2SDI4_1 P1A - 27 - 39 - - 40 28 18 41 29 19 SIN4_1 INT05_1 CEC0_0 P1F ADTG_5 P10 AN00 P11 AN01 SIN1_1 INT02_1 WKUP1 42 30 20 P12 AN02 SOT1_1 P13 43 31 21 AN03 SCK1_1 RTCCO_1 SUBOUT_1 P14 AN04 44 32 - SIN0_1 SCS10_1 INT03_1 Document Number: 002-00234 Rev.*A Page 16 of 100 S6E1C1 Series Pin no. LQFP-64 QFN-64 45 LQFP-48 QFN-48 33 LQFP-32 QFN-32 - Pin Function P15 AN05 SOT0_1 SCS11_1 P23 AN06 I/O circuit type Pin state type F J F J 46 34 22 47 35 23 P22 AN07 F J 48 36 24 TIOB7_1 VCC - - 49 50 37 38 25 AVRH * AVRL - - 51 39 26 P21 INT06_1 E K E K D K E K D K E K 52 - - 53 40 27 54 - - 55 41 28 SCK0_0 TIOA7_1 WKUP2 P00 WKUP4 P01 SWCLK SOT0_0 P02 WKUP5 P03 SWDIO SIN0_0 TIOB7_0 P05 MD1 56 42 29 TIOA5_2 INT00_1 57 43 - WKUP3 VCC - - 58 59 44 45 30 31 P80 P81 J J G G 60 46 32 - - 61 47 - VSS P61 H K 62 - - E K 63 - - E K TIOB2_2 P0B TIOB6_1 WKUP6 P0C TIOA6_1 WKUP7 Document Number: 002-00234 Rev.*A Page 17 of 100 S6E1C1 Series Pin no. LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 Pin Function I/O circuit type Pin state type E I P0F NMIX 64 48 1 WKUP0 RTCCO_0 SUBOUT_0 CROUT_1 *: In case of 32-pin package, AVRH pin is internally connected to VCC pin. Document Number: 002-00234 Rev.*A Page 18 of 100 S6E1C1 Series List of Pin Functions The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Pin no. Pin function Pin name ADC ADTG_5 ADTG_6 ADC Base Timer 0 Base Timer 1 Function description LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 39 8 8 7 ADTG_7 AN00 23 40 28 18 AN01 AN02 41 42 29 30 19 20 43 44 31 32 21 - AN05 AN06 45 46 33 34 22 AN07 TIOA0_0 47 20 35 - 23 - Base timer ch.0 TIOB pin 11 5 10 5 - Base timer ch.1 TIOA pin 21 12 11 - 4 22 4 - - 13 33 12 25 17 AN03 AN04 TIOA0_1 TIOB0_1 TIOA1_0 TIOA1_1 A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin TIOA1_2 TIOA2_0 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 TIOA2_1 TIOA2_2 Base timer ch.2 TIOA pin TIOB2_1 TIOB2_2 Base timer ch.2 TIOB pin 7 61 7 47 6 - TIOA3_0 TIOA3_1 Base timer ch.3 TIOA pin 23 14 - - TIOB3_0 TIOA4_1 Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin 24 15 - - TIOB4_1 TIOA5_1 Base timer ch.4 TIOB pin 9 16 - - Base timer ch.5 TIOB pin 56 10 42 - 29 - TIOA6_1 TIOB6_1 Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin 63 62 - - TIOA7_1 TIOB7_0 Base timer ch.7 TIOA pin 46 55 34 41 22 28 47 35 23 53 40 27 55 41 28 TIOA5_2 TIOB5_1 TIOB7_1 SWCLK Debugger SWDIO Document Number: 002-00234 Rev.*A Base timer ch.5 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Page 19 of 100 S6E1C1 Series Pin no. Pin function Pin name Function description INT00_0 INT00_1 External interrupt request 00 input pin INT01_0 INT02_0 INT02_1 INT03_0 INT03_1 INT03_2 External Interrupt GPIO GPIO GPIO External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 1 56 1 42 2 29 2 3 2 3 3 4 41 11 29 10 19 - 44 5 32 5 - INT04_0 INT04_2 External interrupt request 04 input pin 8 6 8 6 7 5 INT05_1 INT05_2 External interrupt request 05 input pin 38 7 27 7 6 INT06_1 INT06_2 External interrupt request 06 input pin 51 26 39 18 26 - INT07_2 INT08_1 External interrupt request 07 input pin External interrupt request 08 input pin 4 10 4 - - INT12_1 INT13_1 External interrupt request 12 input pin External interrupt request 13 input pin 20 21 - - INT15_1 NMIX External interrupt request 15 input pin Non-Maskable Interrupt input pin 33 64 25 48 17 1 P00 P01 52 53 40 27 P02 P03 54 55 41 28 56 62 42 - 29 - P0C P0F 63 64 48 1 P10 P11 40 41 28 29 18 19 P12 P13 42 43 30 31 20 21 P14 P15 44 45 32 33 - 38 37 27 26 - P1C P1D 36 35 - - P1E P1F 34 39 - - 51 47 39 35 26 23 46 34 22 P05 P0B P1A P1B P21 P22 P23 Document Number: 002-00234 Rev.*A General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Page 20 of 100 S6E1C1 Series Pin no. Pin function GPIO GPIO GPIO GPIO GPIO GPIO Pin name LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 P30 P31 5 6 5 6 5 P32 P33 7 8 7 8 6 7 P34 P35 9 10 9 - - 11 12 10 11 - P3C P3D 13 14 12 - - P3E P3F 15 16 - - P40 P41 20 21 - - P42 P43 22 23 - - 30 31 22 23 14 15 P4C P4D 24 25 16 17 - P4E P50 26 1 18 1 2 2 3 2 3 3 4 4 33 4 25 17 61 58 47 44 30 59 18 45 14 31 9 19 55 15 41 10 28 44 32 - 53 40 27 45 33 - 46 34 22 P3A P3B P46 P47 P51 P52 P53 P60 P61 P80 P81 PE2 PE3 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) Multi-function Serial 0 Function description SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Document Number: 002-00234 Rev.*A General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA0 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when used as a CSIO pin (operation mode 2) and as SCL0 when used as an I2C pin (operation mode 4). Page 21 of 100 S6E1C1 Series Pin no. Pin function Pin name LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 41 29 19 42 30 20 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when used as a CSIO pin (operation mode 2) and as SCL1 when used as an I2C pin (operation mode 4). 43 31 21 SCS10_1 Multi-function serial interface ch.1 serial chip select 0 input/output pin. 44 32 - 45 33 - 1 1 2 2 2 3 3 3 4 SIN1_1 SOT1_1 (SDA1_1) Multi-function Serial 1 SCS11_1 SIN3_1 Multi-function Serial 3 Function description SOT3_1 (SDA3_1) SCK3_1 (SCL3_1) Document Number: 002-00234 Rev.*A Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA1 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.1 serial chip select 1 output pin. Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA3 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when used as a CSIO (operation mode 2) and as SCL3 when used as an I2C pin (operation mode 4). Page 22 of 100 S6E1C1 Series Pin no. Pin function Pin name SIN4_1 SOT4_1 (SDA4_1) Multi-function Serial 4 SCK4_1 (SCL4_1) CTS4_1 RTS4_1 SIN6_1 SOT6_1 (SDA6_1) Multi-function Serial 6 SCK6_1 (SCL6_1) SCS60_1 SCS61_1 SCS62_1 SIN7_1 Multi-function Serial 7 SOT7_1 (SDA7_1) SCK7_1 (SCL7_1) Document Number: 002-00234 Rev.*A Function description Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA4 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when used as a CSIO (operation mode 2) and as SCL4 when used as an I2C pin (operation mode 4). Multi-function serial interface ch4 CTS input pin Multi-function serial interface ch4 RTS output pin Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA6 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when used as a CSIO (operation mode 2) and as SCL6 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.6 serial chip select 0 input/output pin. Multi-function serial interface ch.6 serial chip select 1 output pin. Multi-function serial interface ch.6 serial chip select 2 output pin. Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA7 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when used as a CSIO (operation mode 2) and as SCL7 when used as an I2C pin (operation mode 4). LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 38 27 - 37 26 - 36 - - 35 - - 34 - - 8 8 7 7 7 6 6 6 5 5 5 - 9 9 - 10 - - 26 18 - 25 17 - 24 16 - Page 23 of 100 S6E1C1 Series Pin no. Pin function Pin name MI2SDI4_1 MI2SDO4_1 MI2SCK4_1 MI2SWS4_1 I2S(MFS) MI2SMCK4_ 1 MI2SDI6_1 MI2SDO6_1 MI2SCK6_1 MI2SWS6_1 MI2SMCK6_ 1 IC1_CIN_0 IC1_CLK_0 Smart Card Interface IC1_DATA_0 IC1_RST_0 IC1_VCC_0 IC1_VPEN_0 RTCCO_0 RTCCO_1 Real-time Clock RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 HDMI-CEC/Re mote Control Reception CEC0_0 CEC1_0 Document Number: 002-00234 Rev.*A Function description LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 38 - - 37 - - 36 - - 35 - - I2S Master Clock Input/output pin (operation mode 2). 34 - - I2S Serial Data Input pin (operation mode 2). 8 8 - 7 7 - 6 6 - 5 5 - 9 9 - 11 - - 16 - - 12 - - 13 - - 15 14 - - 64 43 48 31 1 21 11 64 10 48 1 43 11 31 10 21 - 38 27 - 33 25 17 I2S Serial Data Input pin (operation mode 2). I2S Serial Data Output pin (operation mode 2). I2S Serial Clock Output pin (operation mode 2). I2S Word Select Output pin (operation mode 2). I2S Serial Data Output pin (operation mode 2). I2S Serial Clock Output pin (operation mode 2). I2S Word Select Output pin (operation mode 2). I2S Master Clock Input/output pin (operation mode 2). Smart Card insert detection output pin Smart Card serial interface clock output pin Smart Card serial interface data input pin Smart Card reset output pin Smart Card power enable output pin Smart Card programming output pin 0.5 seconds pulse output pin of real-time clock Sub clock output pin HDMI-CEC/Remote Control Reception ch.0 input/output pin HDMI-CEC/Remote Control Reception ch.1 input/output pin Page 24 of 100 S6E1C1 Series Pin no. Pin function Pin name WKUP0 WKUP1 WKUP2 Low Power Consumption Mode WKUP3 WKUP4 WKUP5 WKUP6 WKUP7 Function description Deep Standby mode return signal input pin 0 Deep Standby mode return signal input pin 1 Deep Standby mode return signal input pin 2 Deep Standby mode return signal input pin 3 Deep Standby mode return signal input pin 4 Deep Standby mode return signal input pin 5 Deep Standby mode return signal input pin 6 Deep Standby mode return signal input pin 7 I2C Clock Pin I2C Data Pin LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 64 48 1 41 29 19 51 39 26 56 42 29 52 - - 54 - - 62 - - 63 - - 6 7 6 7 5 6 I2C Slave SI2CSCL6_1 SI2CSDA6_1 RESET INITX External Reset Input pin. A reset is valid when INITX="L". 32 24 16 MD0 Mode 0 pin. During normal operation, input MD0="L". During serial programming to Flash memory, input MD0="H". 17 13 8 56 42 29 18 30 14 22 9 14 MODE X0 X0A Mode 1 pin. During normal operation, input is not needed. During serial programming to Flash memory, MD1 = "L" must be input. Main clock (oscillation) input pin Sub clock (oscillation) input pin X1 X1A Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin 19 31 15 23 10 15 Built-in high-speed CR oscillation clock output port 64 48 1 27 48 19 36 11 24 57 29 43 21 13 60 46 32 49 37 - 50 38 25 28 20 12 MD1 CLOCK CROUT_1 POWER GND VCC VCC VCC VSS VSS Power supply pin GND pin A/D converter analog reference voltage AVRH * Analog input pin A/D converter analog reference voltage Reference AVRL input pin Power supply stabilization capacitance C pin C pin *: In case of 32-pin package, AVRH pin is internally connected to VCC pin. Document Number: 002-00234 Rev.*A Page 25 of 100 S6E1C1 Series 5. I/O Circuit Type Type Circuit P-ch P-ch Digital output N-ch Digital output Remarks X1 R Pull-up resistor control Digital input Standby mode Control Clock input It is possible to select the main oscillation / GPIO function When the main oscillation is selected. ・Oscillation feedback resistor : Approximately 1MΩ ・With standby mode control A Standby mode Control Digital input Standby mode Control R P-ch P-ch Digital output N-ch Digital output X0 When the GPIO is selected. ・CMOS level output. ・CMOS level hysteresis input ・With pull-up resistor control ・With standby mode control ・Pull-up resistor : Approximately 33kΩ ・IOH= -4mA, IOL= 4mA Pull-up resistor control B Pull-up resistor Digital input Document Number: 002-00234 Rev.*A CMOS level hysteresis input Pull-up resistor : Approximately 33kΩ Page 26 of 100 S6E1C1 Series Type Circuit P-ch P-ch Digital output N-ch Digital output Remarks X1A R Pull-up resistor control Digital input Standby mode Control It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5MΩ  With Standby mode control Clock input C Standby mode Control Digital input Standby mode Control R P-ch P-ch Digital output N-ch Digital output When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 33kΩ IOH= -4mA, IOL= 4mA X0A Pull-up resistor control Document Number: 002-00234 Rev.*A Page 27 of 100 S6E1C1 Series Type Circuit P-ch D P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Remarks ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 33kΩ ・ IOH= -4mA, IOL= 4mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Standby mode Control P-ch E P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode Control ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 33kΩ ・ IOH= -4mA, IOL= 4mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Wake up request Wake up control Document Number: 002-00234 Rev.*A Page 28 of 100 S6E1C1 Series Type Circuit P-ch P-ch Digital output N-ch Digital output R F Pull-up resistor control Digital input Standby mode Control Analog input Remarks ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 33kΩ ・ IOH= -4mA, IOL= 4mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Input control P-ch P-ch Digital output N-ch Digital output R G Pull-up resistor control Digital input Standby mode Control Wake up request Wake up Control ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 33kΩ ・ IOH= -4mA, IOL= 4mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Analog input Input control Document Number: 002-00234 Rev.*A Page 29 of 100 S6E1C1 Series Type Circuit P-ch H P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode Control I Mode input P-ch J N-ch Remarks ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 33kΩ ・ IOH= -4mA, IOL= 4mA ・ Available to control PZR registers ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off ・ CMOS level hysteresis input Digital output Digital output R  CMOS level output  CMOS level hysteresis input  With standby mode control Digital input Standby mode Control Document Number: 002-00234 Rev.*A Page 30 of 100 S6E1C1 Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: 002-00234 Rev.*A Page 31 of 100 S6E1C1 Series Latch-Up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Document Number: 002-00234 Rev.*A Page 32 of 100 S6E1C1 Series Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C and 30 ˚C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-00234 Rev.*A Page 33 of 100 S6E1C1 Series 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf Document Number: 002-00234 Rev.*A Page 34 of 100 S6E1C1 Series 7. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVRH pin and AVRL pin near this device. Stabilizing Supply Voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF Document Number: 002-00234 Rev.*A Page 35 of 100 S6E1C1 Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. However in the Deep Standby mode, an external clock as an input of the sub clock cannot be used. Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Set as External clock input X1(PE3), X1A (P47) 2 Handling when Using Multi-Function Serial Pin as I C Pin 2 2 If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled. However, I C pins need to 2 keep the electrical characteristic like other pins and not to connect to the external I C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. Incidentally, the C pin becomes floating in Deep standby mode. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Document Number: 002-00234 Rev.*A Page 36 of 100 S6E1C1 Series Notes on Power-on Turn power on/off in the following order or at the same time. Turning on : VCC →AVRH Turning off : AVRH →VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise; perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features Among the Products with Different Memory Sizes and Between Flash Memory Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Handling when Using Debug Pins When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, set them as output only; do not set them as input. Document Number: 002-00234 Rev.*A Page 37 of 100 S6E1C1 Series 8. Block Diagram SWCLK SWDIO SW-DP Fast GPIO Cortex-M0+Core On-Chip SRAM 12/16Kbyte Flash I/F On-Chip FLASH 64/128Kbyte Bit Band Wrapper NVIC Dual-Timer WatchDog Timer (Software) Clock Reset Generator Security Multi-layer AHB AHB-APB Bridge APB0 System ROM table INITX MTB WatchDog Timer (Hardware) DSTC 64ch. WatchDog Timer (CVS) Main Osc Sub Osc AHB-AHB Bridge Source Clock X0 X1 X0A X1A PLL CR 8MHz CR 100KHz CROUT AVRH AVRL ANxx ADTG Power-On LVD Ctrl 12-bit A/D Converter IRQ-Monitor Unit 0 LVD Regulator C Watch Counter Base Timer 16-bit 8 ch. 32-bit 4 ch. CRC Accelarator Real-Time Clock AHB-APB Bridge : APB1 TIOAx TIOBx External Interrupt Controller 12 pin(Max) + NMI NMIX MODE-Ctrl MD0, MD1 Deep Standby Ctrl Peripheral Clock Gating GPIO Smart Card I/F PIN-Function-Ctrl P0x, P1x, : PEx SCKx SINx SOTx SCSx MI2SCKx MI2SDIx MI2SDOx MI2SMCKx MI2SWSx IC1_CLKx IC1_VCCx IC1_VPENx IC1_CINx IC1_DATAx I2C Slave Document Number: 002-00234 Rev.*A INTx Low-Speed CR Multi-function Serial I/F 6 ch. (Max) WKUPx RTCCO SI2CSCLx SI2CSDAx Page 38 of 100 S6E1C1 Series 9. Memory Map Memory Map (1) See "Memory map (2)" for the memory size details. Document Number: 002-00234 Rev.*A Page 39 of 100 S6E1C1 Series Memory Map (2) S6E1C11B0A S6E1C11C0A S6E1C11D0A 0x2008_0000 S6E1C12B0A S6E1C12C0A S6E1C12D0A 0x2008_0000 Reserved 0x2000_4000 0x2000_3000 0x2000_1000 Reserved 0x2000_4000 SRAM 4K byte 0x2000_3000 SRAM 8K byte SRAM 4K byte SRAM 12K byte 0x2000_0000 Reserved 0x0010_0004 0x0010_0000 CR trimming Security Reserved 0x0010_0004 0x0010_0000 CR trimming Security Reserved Reserved 0x0001_FFF0 0x0000_FFF0 Flash 131056 Byte (128Kbyte - 16Byte)* Flash 65520 Byte (64Kbyte - 16Byte) * 0x0000_0000 0x0000_0000 *: See "S6E1C1/C3 Series Flash Programming Manual" to check details of the Flash memory. Document Number: 002-00234 Rev.*A Page 40 of 100 S6E1C1 Series Peripheral Address Map Start address End address 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog Timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Reserved 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF Reserved 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Reserved 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_5000 0x4003_6000 0x4003_7000 0x4003_4FFF 0x4003_5FFF 0x4003_6FFF 0x4003_77FF 0x4003_7800 0x4003_79FF I2C Slave 0x4003_7A00 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function Serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C800 0x4003_C900 0x4003_CA00 0x4003_CB00 0x4004_0000 0x4005_0000 0x4006_1000 0x4006_2000 0x4003_C7FF 0x4003_C8FF 0x4003_C9FF 0x4003_CAFF 0x4003_FFFF 0x4004_FFFF 0x4006_0FFF 0x4006_1FFF 0x41FF_FFFF Peripheral Clock Gating Reserved Smart Card Interface MFS-I2S Clock Generator Reserved Reserved Reserved DSTC Reserved Document Number: 002-00234 Rev.*A Bus AHB APB0 APB1 AHB Peripheral Flash memory I/F register Reserved Software Watchdog Timer Reserved HDMI-CEC/Remote Control Receiver Low-Voltage Detection / DS mode / Vref Calibration Reserved Reserved Page 41 of 100 S6E1C1 Series 10. Pin Status in Each CPU State The following table shows pin status in each CPU state. CPU state Type Selected Pin function Main osillation circuit Main osillation circuit selected *1 selected A Main clock external Digital I/O slected *2 input selected GPIO selected B Main osillation circuit Main osillation circuit selected *1 selected Digital I/O slected *2 GPIO selected Sub osillation circuit Sub osillation circuit selected *1 selected C Sub clock external Digital I/O slected *2 input selected GPIO selected Sub osillation circuit Sub osillation circuit selected *1 selected Digital I/O slected *2 GPIO selected E Digital I/O slected INITX input F Digital I/O slected MD0 input G Digital I/O slected *6 GPIO selected D H Digital I/O slected Digital I/O slected (7) (8) OS OS OE OE OE OS OS OS - - IE/IS IE/IS IE/IS IS IS IS - - PC HC IS HS IS HS OS OS OE OE OE OS OS OS - - PC HC IS GS IS GS OS OE OE OE OE OE OE OE - - IE/IS IE/IS IE/IS IS IS IS - - PC HC IS HS IS HS OS OE OE OE OE OE OE OE HS IS HS HC IS PC This pin is digital input pin, pull up register is on, and digital input is not shut off in all CPU state.. This pin is digital input pin, pull up register is none, digital input is not shut off in all CPU state.. IS IE IP CP HC IS HS IS HS PC IP IP IP IP IP - PC HC IS HS IS HS - - IP IP IP - - - - - IP IP IP IP IP IP IS IE PC HC IS - - - input selected Analog input selected Exterrnal interrupt enable and input selected Resource other than above selected CEC pin selected WKUP enable and input selected I2CSLAVE enable selected Digital I/O slected (6) - GPIO selected K (5) NMI selected input selected Digital I/O slected *4 (4) GPIO selected WKUP enable and J (3) IS GPIO selected Analog input selected *3 (2) SW selected WKUP0 enable and I (1) Exterrnal interrupt enable and input selected GPIO selected Resource other than above selected *5 Analog input is enalbe in all CPU state - - IP IP IP IP IP IP - - IP IP IP GS IS GS - - PC HC IS HS IS HS - - PC HC IS GS IS GS - - CP CP CP CP CP CP - - IP IP IP IP IP IP - - PC HC IP GS IS GS - - PC HC IP GS IS GS IS IE PC HC IS HS IS HS - - PC HC IS GS IS GS Each term in above table have the following meanings. Document Number: 002-00234 Rev.*A Page 42 of 100 S6E1C1 Series Type This indicates a pin status type that is shown in “pin list table” in “4. List of Pin Functions” Selected Pin function This indicates a pin function that is selected by user program. CPU state This indicates a state of the CPU that is shown below. (1) (2) (3) (4) (5) (6) (7) (8) Reset state. CPU is initialized by Power-on reset or a reset due to low Power voltage supply. Reset state. CPU is initialized by INITX input signal or system initialization after power on reset. Run mode or SLEEP mode state. Timer mode, RTC mode or STOP mode state. The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0". Timer mode, RTC mode or STOP mode state. The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1". Deep standby STOP mode or Deep standby RTC mode state, The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0" Deep standby STOP mode or Deep standby RTC mode state, The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1" Run mode state after returning from Deep Standby mode. (I/O state hold function(CONTX) is fixed at 1) Each pin status The meaning of the symbols in the pin status table is as follows. IS Digital output is disabled. (Hi-Z) Pull up register is off. Digital input is shut off by fixed 0. IE Digital output is disabled. (Hi-Z) Pull up register is off. Digital input is not shut off. IP Digital output is disabled. (Hi-Z) Pull up register is defined by the value of the PCR register. Digital input is not shut off. IE/IS Digital output is disabled. (Hi-Z) Pull up register is off. Digital input is shut off in case of the OSC stop. Digital input is not shut off in case of the OSC operation. OE The OSC is in operation state. However, it may be stopped in some operation mode of the CPU. For detail, see chapter “Low Power Consumption Mode” in peripheral manual. OS The OSC is in stop state. (Hi-Z) PC Digital output and pull up register is controlled by the register in the GPIO or peripheral function. Digital input is not shut off CP Digital output is controlled by the register in the GPIO or peripheral function. Pull up register is off． Digital input is not shut off. HC Digital output and pull up register is maintained the status that is immediately prior to entering the current CPU state. Digital input is not shut off HS Digital output and pull up register is maintained the status that is immediately prior to entering the current CPU state. Digital input is shut off GS Digital output and pull up register is copied the GPIO status that is immediately prior to entering the current CPU state and the status is maintained. Digital input is shut off Document Number: 002-00234 Rev.*A Page 43 of 100 S6E1C1 Series Additional note Additional note is described below. *1 In this type, when internal oscillation function is selected, digital output is disabled. (Hi-Z) pull up register is off, digital input is shut off by fixed 0. *2 In this type, when Digital I/O function is selected, internal oscillation function is disabled. *3 In this type, when analog input function is selected, digital output is disabled, (Hi-Z). pull up register is off, digital input is shut off by fixed 0. *4 In this type, when Digital I/O function is selected, analog input function is not available. *5 In this case, PCR register is initialized to “1”. Pull up register is on. *6 This pin does not have pull up register. Document Number: 002-00234 Rev.*A Page 44 of 100 S6E1C1 Series 11. Electrical Characteristics 11.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage* * 1, 3 Analog reference voltage* * 1, 2 VCC AVRH 1 VI Input voltage* 1 Analog pin input voltage* 1 Output voltage* Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VIA VSS - 0.5 VO VSS - 0.5 4 L level maximum output current* IOL 5 L level average output current* IOLAV L level total maximum output current ∑IOL 6 L level total average output current* ∑IOLAV 4 H level maximum output current* IOH 5 H level average output current* IOHAV H level total maximum output current ∑IOH 6 H level total average output current* ∑IOHAV Power consumption PD Storage temperature TSTG *1: These parameters are based on the condition that VSS= 0 V. Rating - 55 Max VSS + 4.6 VSS + 4.6 VCC + 0.5 (≤ 4.6 V) VSS + 6.5 VCC + 0.5 (≤ 4.6 V) Vcc + 0.5 (≤ 4.6 V) 10 4 100 50 - 10 -4 - 100 - 50 200 + 150 Unit Remarks V V V V 5 V tolerant V V mA mA mA mA mA mA mA mA mW °C 4 mA type 4 mA type 4 mA type 4 mA type *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not to exceed VCC + 0.5 V at power-on. *4: The maximum output current is the peak value for a single pin. *5: The average output is the average current for a single pin over a period of 100 ms. *6: The total average output current is the average current for all pins over a period of 100 ms. Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. − Document Number: 002-00234 Rev.*A Page 45 of 100 S6E1C1 Series 11.2 Recommended Operating Conditions (VSS= 0.0 V) Parameter Power supply voltage Analog reference voltage Symbol Conditions VCC - AVRH - Min 2 1.65 * 2.7 Value Max 3.6 VCC VCC VCC AVRL VSS VSS Smoothing capacitor CS 1 10 Operating temperature Ta - 40 + 105 *1: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor. Unit Remarks V V VCC ≥ 2.7 V V V μF °C VCC < 2.7 V 1 For regulator* *2: In between less than the minimum power supply voltage reset / interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-00234 Rev.*A Page 46 of 100 S6E1C1 Series 11.3 DC Characteristics 11.3.1 Current Rating Symbol *8 8 MHz external clock input, PLL ON Run mode, code executed from Flash Run mode, code executed from RAM Icc (VCC) Run mode, code executed from Flash Value HCLK Conditions (Pin Name) Frequency*4 8 MHZ Typ*1 Max*2 1.4 2.7 4.1 Unit Remarks 8 MHz external clock input, PLL ON*8 8 MHZ NOP code executed 20 MHZ Built-in high speed CR stopped 40 MHZ 2.6 3.9 1.3 2.3 3.4 1.6 2.8 4.1 1.0 1.7 2.7 40 MHZ 1.6 3.1 mA *3,*6,*7 8 MHZ 1.1 2.4 mA *3 32 kHZ 240 1264 μA *3 100 kHZ 246 1271 μA *3 8 MHZ 0.8 1.9 20 MHZ 2.4 mA *3 40 MHZ 1.3 1.8 8 MHZ 0.6 1.7 mA *3 32 kHZ 237 1261 μA *3 100 kHZ 238 1262 μA *3 NOP code executed 20 MHZ Built-in high speed CR stopped 40 MHZ 8 MHz external clock input, PLL ON*8 8 MHZ Benchmark code executed 20 MHZ Built-in high speed CR stopped 40 MHZ 8 MHz crystal oscillation, PLL ON*8 8 MHZ NOP code executed 20 MHZ Built-in high speed CR stopped 40 MHZ mA *3 mA *3 mA *3 mA *3 5.6 2.6 3.8 5.1 3.0 4.4 5.9 2.1 2.9 4.0 8 MHz external clock input, PLL ON NOP code executed Built-in high speed CR stopped PCLK1 stopped Built-in high speed CR*5 NOP code executed All peripheral clock stopped by CKENx Run mode, code executed from Flash 32 kHz crystal oscillation NOP code executed All peripheral clock stopped by CKENx Built-in low speed CR NOP code executed All peripheral clock stopped by CKENx 8 MHz external clock input, PLL ON*8 All peripheral clock stopped by CKENx Iccs (VCC) Sleep operation Built-in high speed CR*5 All peripheral clock stopped by CKENx 32 kHz crystal oscillation All peripheral clock stopped by CKENx Built-in low speed CR All peripheral clock stopped by CKENx 3.0 *1 : TA=+25°C,VCC=3.3 V *2 : TA=+105°C,VCC=3.6 V *3 : All ports are fixed *4 : PCLK0 is set to divided rate 8 *5 : The frequency is set to 8 MHz by trimming *6 : Flash sync down is set to FRWTR.RWT=111 and FSYNDN.SD=1111 *7 : VCC=1.65 V *8 : When HCLK=8 MHz, PLL OFF Document Number: 002-00234 Rev.*A Page 47 of 100 S6E1C1 Series Parameter Symbol (Pin Name) Conditions ICCH (VCC) Power supply current ICCT (VCC) Stop mode Sub timer mode ICCR (VCC) RTC mode *1: All ports are fixed. LVD off. Flash off. Value Unit Remarks Typ Max Ta=25℃ Vcc=3.3 V 12.4 52.4 μA *1, *2 Ta=25℃ Vcc=1.65 V 12.0 52.0 μA *1, *2 Ta= 105℃ Vcc=3.6 V - 597 μA *1, *2 15.6 55.6 μA *1, *2 15.0 55.0 μA *1, *2 - 601 μA *1, *2 13.2 53.2 μA *1, *2 12.7 52.7 μA *1, *2 - 598 μA *1, *2 Ta=25℃ Vcc=3.3 V 32 kHz Crystal oscillation Ta=25℃ Vcc=1.65 V 32 kHz Crystal oscillation Ta= 105℃ Vcc=3.6 V 32 kHz Crystal oscillation Ta=25℃ Vcc=3.3 V 32 kHz Crystal oscillation Ta=25℃ Vcc=1.65 V 32 kHz Crystal oscillation Ta= 105℃ Vcc=3.6 V 32 kHz Crystal oscillation *2: When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added. Document Number: 002-00234 Rev.*A Page 48 of 100 S6E1C1 Series Parameter Symbol (Pin Name) RAM off ICCHD (VCC) Deep standby Stop mode RAM on Power supply current RAM off ICCRD (VCC) Value Conditions Deep standby RTC mode RAM on *1: All ports are fixed. LVD off. Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta= 105°C Vcc=3.6 V Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta= 105°C Vcc=3.6 V Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta= 105°C Vcc=3.6 V Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta= 105°C Vcc=3.6 V Unit Remarks 1.85 μA *1, *2 0.56 1.83 μA *1, *2 - 46 μA *1, *2 0.78 6.6 μA *1, *2 0.76 6.6 μA *1, *2 - 88 μA *1, *2 1.16 2.4 μA *1, *2 1.15 2.4 μA *1, *2 - 46 μA *1, *2 1.37 7.2 μA *1, *2 1.35 7.2 μA *1, *2 - 88 μA *1, *2 Typ Max 0.58 *2: When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added. Document Number: 002-00234 Rev.*A Page 49 of 100 S6E1C1 Series LVD Current Parameter Low-Voltage detection circuit (LVD) power supply current (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol ICCLVD Pin Name Conditions VCC At operation Typ 0.15 0.10 Bipolar Vref Current Parameter Bipolar Vref Current Flash memory write/erase current Symbol Pin Name Conditions ICCBGR VCC At operation Typ Unit Remarks μA For occurrence of reset μA For occurrence of interrupt Value Max 200 Unit Remarks μA (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin Name Conditions ICCFLASH VCC At Write/Erase Typ Value 4.4 Max 5.6 Unit Remarks mA (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Power supply current Pin Name ICCAD VCC Reference power supply current (AVRH) ICCAVRH AVRH Document Number: 002-00234 Rev.*A 0.3 100 A/D converter Current Parameter Max 0.3 (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Flash Memory Current Parameter Value Value Conditions At operation 0.5 0.75 mA At operation 0.69 1.3 mA At stop 0.1 1.3 μA Typ Max Unit Remarks AVRH=3.6 V Page 50 of 100 S6E1C1 Series Peripheral Current Dissipation Clock System Peripheral Conditions GPIO At all ports operation 0.05 0.12 0.23 DSTC At 2ch operation 0.02 0.06 0.10 Base timer At 4ch operation 0.02 0.05 0.10 ADC At 1 unit operation 0.04 0.10 0.21 Multi-function serial At 1ch operation 0.01 0.03 0.06 MFS-I2S At 1ch operation 0.02 0.05 0.08 Smart Card I/F At 1ch operation 0.04 0.08 0.18 HCLK PCLK1 (VCC=1.65 V to 3.6 V, VSS=0 V, TA=- 40°C to +105°C) Frequency (MHz) 20 Document Number: 002-00234 Rev.*A 8 40 Unit Remarks mA mA Page 51 of 100 S6E1C1 Series 11.3.2 Pin Characteristics Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) H level output voltage L level output voltage Input leak current Pull-up resistance value Input capacitance (VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Value Typ Max - VCC +0.3 V VCC × 0.8 VCC × 0.7 - VSS +5.5 V VSS - 0.3 - Symbol Pin Name Conditions VCC ≥ 2.7 V VIHS CMOS hysteresis input pin, MD0 VCC < 2.7 V VCC × 0.7 5 V tolerant input pin VCC ≥ 2.7 V VCC < 2.7 V CMOS hysteresis input pin, MD0 VCC ≥ 2.7 V VILS 5 V tolerant input pin VOH 4 mA type Min VCC < 2.7 V VCC × 0.2 V VCC × 0.3 VSS - 0.3 - VCC × 0.2 - VCC × 0.3 - VCC V V VCC ≥ 2.7 V, IOH = - 4 mA VCC - 0.5 VCC < 2.7 V, IOH = - 2 mA VCC - 0.45 VSS - 0.4 V μA VOL 4 mA type VCC ≥ 2.7 V, IOL 4 mA VCC < 2.7 V, IOL=2 mA IIL - - -5 - +5 RPU Pull-up pin VCC ≥ 2.7 V 21 33 48 VCC < 2.7 V - - 88 CIN Other than VCC, VSS, AVRH - - 5 15 Document Number: 002-00234 Rev.*A Remarks VCC × 0.8 VCC < 2.7 V VCC ≥ 2.7 V Unit kΩ pF Page 52 of 100 S6E1C1 Series 11.4 AC Characteristics 11.4.1 Main Clock Input Characteristics Parameter Symbol Input frequency FCH Input clock cycle tCYLH Input clock pulse width Input clock rising time and falling time Internal operating *1 clock frequency Pin name X0, X1 (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Conditions Value Unit Remarks Min Max VCC ≥ 2.7V VCC < 2.7V 8 8 48 20 MHz When the crystal oscillator is connected - 8 48 MHz When the external clock is used - 20.83 125 ns PWH/tCYLH, PWL/tCYLH 45 55 % - - 5 ns tCF, tCR FCM - - - 40.8 MHz When the external clock is used When the external clock is used When the external clock is used Master clock FCC FCP0 FCP1 - - - 40.8 40.8 40.8 MHz MHz MHz Base clock (HCLK/FCLK) 2 APB0 bus clock* 2 APB1 bus clock* tCYCCM tCYCC tCYCP0 tCYCP1 - - 24.5 - ns - Master clock 24.5 ns Base clock (HCLK/FCLK) Internal operating *1 2 clock cycle time 24.5 ns APB0 bus clock* 2 24.5 ns APB1 bus clock* *1: For details of each internal operating clock, refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual". *2: For details of the APB bus to which a peripheral is connected, see "8. Block Diagram". tCYLH X0 0.8 × Vcc 0.8 × Vcc 0.2 × Vcc PWH PWL tCF Document Number: 002-00234 Rev.*A 0.8 × Vcc 0.2 × Vcc tCR Page 53 of 100 S6E1C1 Series 11.4.2 Sub Clock Input Characteristics Parameter Input frequency Input clock cycle Symbol (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Pin Name fCL tCYLL X0A, X1A Conditions Value Unit Min Typ Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs 55 % Input clock pulse PWH/tCYLL, 45 width PWL/tCYLL *: See "Sub crystal oscillator" in "7. Handling Devices" for the crystal oscillator used. Remarks When the crystal oscillator is connected When the external clock is used When the external clock is used When the external clock is used tCYLL 0.8 × Vcc 0.8 × Vcc 0.2 × Vcc X0A PWH Document Number: 002-00234 Rev.*A 0.8 × Vcc 0.2 × Vcc PWL Page 54 of 100 S6E1C1 Series 11.4.3 Built-in CR Oscillation Characteristics Built-in High-Speed CR Parameter (VCC= 1.65 V to 3.6 V, VSS = 0 V, TA=- 40°C to +105°C) Symbol Conditions FCRH Ta = - 40°C to + 105°C, Clock frequency Value Min Typ Max 7.84 8 8.16 Unit MHz Frequency tCRWT 300 μs stabilization time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming. Remarks After trimming *1 *2 *2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in Low-Speed CR Parameter Clock frequency (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Conditions fCRL - Document Number: 002-00234 Rev.*A Value Min Typ Max 50 100 150 Unit Remarks kHz Page 55 of 100 S6E1C1 Series 11.4.4 Operating Conditions of Main PLL (In the Case of Using the Main Clock as the Input Clock of the PLL) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol 1 PLL oscillation stabilization wait time* (LOCK UP time) tLOCK Value Unit Min Typ Max 50 - - μs - 16 18 150 40 MHz multiple MHz MHz PLL input clock frequency FPLLI 8 PLL multiple rate 5 PLL macro oscillation clock frequency FPLLO 75 2 Main PLL clock frequency* FCLKPLL *1: The wait time is the time it takes for PLL oscillation to stabilize. Remarks *2: For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual". Main PLL connection Main clock (CLKMO) K divider High-speed CR clock (CLKHC) PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider 11.4.5 Operating Conditions of Main PLL (In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol 1 PLL oscillation stabilization wait time* (LOCK UP time) tLOCK Value Unit Min Typ Max 50 - - μs 8 - 8.16 18 150 40.8 MHz multiple MHz MHz PLL input clock frequency FPLLI 7.84 PLL multiple rate 9 PLL macro oscillation clock frequency FPLLO 75 2 Main PLL clock frequency* FCLKPLL *1: The wait time is the time it takes for PLL oscillation to stabilize. Remarks *2: For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual". Note: For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency and temperature have been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. − Document Number: 002-00234 Rev.*A Page 56 of 100 S6E1C1 Series 11.4.6 Reset Input Characteristics Parameter (VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin Name Conditions tINITX INITX - Reset input time 11.4.7 Power-on Reset Timing Parameter Value Min Max 500 - Unit Remarks ns (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Power supply rising time tVCCR Power supply shut down time Time until releasing Power-on reset tOFF Pin Name VCC tPRT Value Unit Min Max 0 - ms 1 - ms 0.43 3.4 ms Remarks VCC_minimum VDH_minimum VCC 0.2V 0.2V tVCCR tOFF tPRT Internal reset Reset active CPU Operation 0.2V Release start Glossary  VCC_minimum : Minimum VCC of recommended operating conditions.  VDH_minimum : Minimum detection voltage of Low-Voltage detection reset. See "11.6 Low-Voltage Detection Characteristics". Document Number: 002-00234 Rev.*A Page 57 of 100 S6E1C1 Series 11.4.8 Base Timer Input Timing Timer Input Timing Parameter Input pulse width (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin Name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - Min Value 2 tCYCP Max - Unit Remarks ns tTIWL tTIWH ECK VIHS VIHS TIN VILS VILS Trigger Input Timing Parameter Input pulse width (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin Name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - VIHS Value 2 tCYCP Max - Unit Remarks ns tTRGL tTRGH TGIN Min VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see "8. Block Diagram". Document Number: 002-00234 Rev.*A Page 58 of 100 S6E1C1 Series 11.4.9 CSIO/SPI/UART Timing CSIO (SPI=0, SCINV=0) Parameter (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock "L" pulse width tSLSH Serial clock "H" pulse width tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Conditions VCC < 2.7 V Min Max 4 tCYCP - VCC ≥ 2.7 V Min Max 4 tCYCP - Unit ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns SCKx 2 tCYCP 10 - - ns SCKx tCYCP + 10 - - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Master mode Slave mode 2 tCYCP 10 tCYCP + 10 Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram". − The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00234 Rev.*A Page 59 of 100 S6E1C1 Series tSCYC VOH SCK VOL VOL tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Master mode tSLSH SCK VIH tF tSHSL VIL VIL tSLOVE SOT VIH tR VOH VOL tIVSHE SIN VIH VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-00234 Rev.*A Page 60 of 100 S6E1C1 Series CSIO (SPI=0, SCINV=1) Parameter (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK falling time SCK rising time tF tR Conditions Master mode VCC < 2.7V Min Max 4 tCYCP - Unit ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns - ns - ns 2 tCYCP 10 tCYCP + 10 Slave mode VCC ≥ 2.7V Min Max 4 tCYCP - - 2 tCYCP 10 tCYCP + 10 - 50 - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns - Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram". − The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00234 Rev.*A Page 61 of 100 S6E1C1 Series tSCYC SCK VOH VOH VOL tSHOVI VOH SOT VOL tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF tSHOVE SOT VOH VOL tIVSLE SIN VIL VIL VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-00234 Rev.*A Page 62 of 100 S6E1C1 Series SPI (SPI=1, SCINV=0) Parameter (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓→ SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓→ SIN hold time tSLIXE SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK falling time SCK rising time tF tR Conditions Master mode VCC < 2.7 V Min Max 4 tCYCP - Unit ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns - ns - ns - ns 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 Slave mode VCC ≥ 2.7 V Min Max 4 tCYCP - - 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 - 50 - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns - Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram". − The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00234 Rev.*A Page 63 of 100 S6E1C1 Series tSCYC SCK tSOVLI SOT VOH VOL VOH VOL VOH VOL VIH VIL SIN VOL tSHOVI tIVSLI tSLIXI VIH VIL Master mode tSLSH VIH SCK * SOT VIL tSHSL VIL tF tR VOH VOL SIN VIH VIL tIVSLE *: Changes when writing to TDR register Document Number: 002-00234 Rev.*A tSLIXE VIH VIH tSHOVE VOH VOL VIH VIL Slave mode Page 64 of 100 S6E1C1 Series SPI (SPI=1, SCINV=1) Parameter (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin name SCKx Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK falling time SCK rising time tF tR Conditions SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Master mode VCC < 2.7 V Min Max 4 tCYCP - Unit ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns - ns - ns - ns 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 Slave mode VCC ≥ 2.7 V Min Max 4 tCYCP - - 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 - 50 - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns - Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram". − The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00234 Rev.*A Page 65 of 100 S6E1C1 Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tR SCK SOT VIL VIH VIH tSLSH VIL tSLOVE VOH VOL tIVSHE SIN tF tSHSL VIL VOH VOL tSHIXE VIH VIL VIH VIL Slave mode Document Number: 002-00234 Rev.*A Page 66 of 100 S6E1C1 Series When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=1) Parameter Symbol Conditions (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) VCC < 2.7 V Min VCC ≥ 2.7 V Max Unit Max Min (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns (*3)+50 (*3)-50 (*3)+50 ns SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI (*3)-50 SCS↓→SCK↓ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 55 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns Master mode Slave mode *1: CSSU bit value × serial chip select timing operating clock cycle. *2: CSHD bit value × serial chip select timing operating clock cycle. *3: CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. Notes: − tCYCP indicates the APB bus clock cycle time. For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram". − − For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − When the external load capacitance CL=30 pF. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. Document Number: 002-00234 Rev.*A Page 67 of 100 S6E1C1 Series SCSO tCSSI tCSHI tCSDI tCSHE tCSDE SCK SOT (SPI=0) SOT (SPI=1) Master mode SCSI tCSSE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00234 Rev.*A Page 68 of 100 S6E1C1 Series When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=1) Parameter Symbol SCS↓→SCK↑ setup time tCSSI SCK↓→SCS↑ hold time tCSHI Conditions Master mode (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) VCC < 2.7 V VCC ≥ 2.7 V Unit Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 (*3)+50 (*3)-50 (*3)+50 ns SCS↓→SCK↑ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 55 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns Slave mode *1: CSSU bit value × serial chip select timing operating clock cycle. *2: CSHD bit value × serial chip select timing operating clock cycle. *3: CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. Notes: − tCYCP indicates the APB bus clock cycle time. For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram". − − For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − When the external load capacitance CL=30 pF. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. Document Number: 002-00234 Rev.*A Page 69 of 100 S6E1C1 Series SCSO tCSSI tCSHI tCSDI tCSHE tCSDE SCK SOT (SPI=0) SOT (SPI=1) Master mode SCSI tCSSE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00234 Rev.*A Page 70 of 100 S6E1C1 Series When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=0) Parameter SCS↑→SCK↓ setup time Symbol Conditions tCSSI Master mode (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) VCC < 2.7 V VCC ≥ 2.7 V Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 Unit ns SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 (*3)+50 (*3)-50 (*3)+50 ns SCS↑→SCK↓ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time SCS↓→SOT delay time 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns tDSE - 55 - 40 ns tDEE 0 - 0 - ns Slave mode *1: CSSU bit value × serial chip select timing operating clock cycle. *2: CSHD bit value × serial chip select timing operating clock cycle. *3: CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. Notes: − tCYCP indicates the APB bus clock cycle time. For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram". − For information About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. − When the external load capacitance CL=30 pF. Document Number: 002-00234 Rev.*A Page 71 of 100 S6E1C1 Series tCSDI SCSO tCSSI tCSHI SCK SOT (SPI=0) SOT (SPI=1) Master mode tCSDE SCSI tCSSE tCSHE SCK tDEE SOT (SPI=0) SOT tDSE (SPI=1) Slave mode Document Number: 002-00234 Rev.*A Page 72 of 100 S6E1C1 Series When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=0) Parameter SCS↑→SCK↑ setup time Symbol Conditions tCSSI Master mode (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) VCC < 2.7 V VCC ≥ 2.7 V Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 Unit ns SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 (*3)+50 (*3)-50 (*3)+50 ns SCS↑→SCK↑ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time SCS↓→SOT delay time 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns tDSE - 55 - 40 ns tDEE 0 - 0 - ns Slave mode *1: CSSU bit value × serial chip select timing operating clock cycle. *2: CSHD bit value × serial chip select timing operating clock cycle. *3: CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. Notes: − tCYCP indicates the APB bus clock cycle time. For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram". − For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. − When the external load capacitance CL=30 pF. Document Number: 002-00234 Rev.*A Page 73 of 100 S6E1C1 Series tCSDI SCSO tCSSI tCSHI SCK SOT (SPI=0) SOT (SPI=1) Master mode tCSDE SCSI tCSSE tCSHE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00234 Rev.*A Page 74 of 100 S6E1C1 Series UART external clock input (EXT=1) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol tSLSH tSHSL tF tR Document Number: 002-00234 Rev.*A VIL Min tCYCP +10 tCYCP +10 - CL=30 pF tR SCK Value Conditions tF tSHSL VIH VIH VIL Max 5 5 Unit Remarks ns ns ns ns tSLSH VIL Page 75 of 100 S6E1C1 Series 11.4.10 External Input Timing Parameter Input pulse width (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Value Min Pin Name Conditions ADTGx - 2 tCYCP* INT00 to INT08, INT12, INT13, INT15, NMIX *2 WKUPx 1 Max Unit - ns 2 tCYCP +100* - ns *3 500 - ns *4 500 - ns Remarks A/D converter trigger input tINH, tINL 1 External interrupt, NMI Deep standby wake up *1: tCYCP represents the APB bus clock cycle time. For the number of the APB bus to which the Multi-function Timer is connected and that of the APB bus to which the External Interrupt Controller is connected, see "8. Block Diagram". *2: In Run mode and Sleep mode *3: In Timer mode, RTC mode and Stop mode *4: In Deep Standby RTC mode and Deep Standby Stop mode tINH VILS Document Number: 002-00234 Rev.*A tINL VILS VIHS VIHS Page 76 of 100 S6E1C1 Series 2 11.4.11 I C Timing / I2C Slave Timing Parameter SCL(SI2CSCL) clock frequency (Repeated) Start condition hold time SDA(SI2CSDA) ↓ → SCL(SI2CSCL) ↓ SCL(SI2CSCL) clock L width SCL(SI2CSCL) clock H width (Repeated) Start setup time SCL(SI2CSCL) ↑ → SDA (SI2CSDA)↓ Data hold time SCL(SI2CSCL) ↓ → SDA(SI2CSDA) ↓↑ Data setup time SDA (SI2CSDA)↓ ↑ → SCL(SI2CSCL) ↑ Stop condition setup time SCL(SI2CSCL) ↑ → SDA (SI2CSDA)↑ Bus free time between Stop condition and Start condition (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbo l FSCL Conditions Standard-Mode Min Max 0 100 Fast-Mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs tSUSTA 4.7 - 0.6 - μs 0 3.45* 0 0.9* μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs tHDDAT CL=30 pF, 1 R=(Vp/IOL)* 2 3 Remarks except I2C 2 2 ns 4 4 tCYCP* tCYCP* Slave *1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. VP represents the power supply voltage of the pull-up resistance, and IOL the VOL guaranteed current. Noise filter tSP - *2: The maximum tHDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at L (tLOW) does not extend. 2 2 *3: A Fast-mode I C bus device can be used in a Standard-mode I C bus system, provided that the condition of tSUDAT ≥ 250 ns is fulfilled. *4: tCYCP represents the APB bus clock cycle time. 2 For the number of the APB bus to which the I C is connected, see "8. Block Diagram". To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA tSUDAT tLOW tSUSTA tBUF SCL tHDSTA Document Number: 002-00234 Rev.*A tHDDAT tHIGH tHDSTA tSP tSUSTO Page 77 of 100 S6E1C1 Series 2 11.4.12 I S Timing (MFS-I2S Timing) Master Mode Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter MI2SCK max frequency (*1) 2 I S clock cycle time (*1) 2 I S clock Duty cycle Symbo l FMI2SCK tICYC ∆ MI2SCK↓ → MI2SWS delay time tSWDT MI2SCK↓ → MI2SDO delay time tSDDT MI2SDI → MI2SCK ↑ setup time tDSST MI2SCK ↑ → MI2SDI hold time tSDHT MI2SCK falling time MI2SCK rising time tF tR Pin Name MI2SCKx MI2SCKx MI2SCKx MI2SCKx , MI2SWS x MI2SCKx , MI2SDO x MI2SCKx , MI2SDIx MI2SCKx , MI2SDIx MI2SCKx MI2SCKx Conditions CL=30 pF VCC < 2.7 V Min Max 6.144 4 tCYCP 45% 55% VCC ≥ 2.7 V Min Max 6.144 4 tCYCP 45% 55% Unit MHz ns -30 +30 -20 +20 ns -30 +30 -20 +20 ns 50 - 36 - ns 0 - 0 - ns - 5 5 - 5 5 ns ns *1: I2S clock should meet the multiple of PCLK(tICYC) and the frequency less than FMI2SCK meantime. The detail information please refer to Chapter I2S of Communication Macro Part of Peripheral Manual. VIH MI2SCK tF VIH VIL VIL tSWDT, tSDDT MI2SWS and MI2SDO MI2SDI Document Number: 002-00234 Rev.*A tR VOH VOL tDSST tSDHT VIH VIH VIL VIL Page 78 of 100 S6E1C1 Series MI2SMCK Input Characteristics Parameter (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Value Unit Symbol Pin Name Conditions Input frequency fCHS MI2SMCK - - 12.288 MHz Input clock cycle tCYLHS - 81.3 - ns - - 45 55 % tCFS tCRS PWHS/tCYLHS PWLS/tCYLHS - - - 5 ns Input clock pulse width Input clock rise time and fall time MI2SMCK Output Characteristics Parameter Output frequency Max Remarks When using external clock When using external clock (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin Name Conditions fCHS MI2SMCK - Document Number: 002-00234 Rev.*A Min Min Value Max Unit Remarks - 25 MHz VCC ≥ 2.7 V - 20 MHz VCC < 2.7 V Page 79 of 100 S6E1C1 Series 11.4.13 Smart Card Interface Characteristics (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Output rising time tR Output falling time tF Output clock frequency Duty cycle fCLK ∆ Pin Name Conditions ICx_VCC, ICx_RST, ICx_CLK, ICx_DATA ICx_CLK CL=30 pF Value Unit Min Max 4 20 ns 4 20 ns - 20 MHz 45% 55% Remarks  External pull-up resistor (20 kΩ to 50 kΩ) must be applied to ICx_CIN pin when it’s used as smart card reader function. Document Number: 002-00234 Rev.*A Page 80 of 100 S6E1C1 Series 11.4.14 SW-DP Timing Parameter (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Value Unit Symbol Pin Name Conditions SWDIO setup time tSWS SWCLK, SWDIO - 15 - ns SWDIO hold time tSWH SWCLK, SWDIO - 15 - ns SWDIO delay time tSWD SWCLK, SWDIO - - 45 ns Min Max Remarks Note: − External load capacitance CL=30 pF SWCLK VOH VOL tJTAGS VOH VOL SWDIO (When input) tJTAGH VOH VOL tSWD JTAGD SWDIO (When output) Document Number: 002-00234 Rev.*A VOH VOL Page 81 of 100 S6E1C1 Series 11.5 12-bit A/D Converter Electrical Characteristics of A/D Converter (Preliminary Values) Parameter ANxx Min - 4.5 - 2.5 - 15 Value Typ - Max 12 4.5 + 2.5 + 15 ANxx AVRH - 15 - AVRH + 15 1.0 - - 4.0 - - 10 - - 0.3 - 1.2 - 3.0 - 1.65 ≤ VCC < 1.8 V 50 - VCC ≥ 2.7 V 200 - 500 - Symbol Pin Name Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage VZT Full-scale transition voltage VFST 1 Conversion time* Sampling time - *2 Ts 3 Compare clock cycle * Tcck (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) - - - Unit bit LSB LSB mV mV VCC ≥ 2.7 V μs 1.8 ≤ VCC < 2.7 V 1.65 ≤ VCC < 1.8 V VCC ≥ 2.7 V 10 1000 μs ns 1.8 ≤ VCC < 2.7 V 1.8 ≤ VCC < 2.7 V 1.65 ≤ VCC < 1.8 V State transition time to operation permission Analog input capacity Tstt - - - 1.0 μs CAIN - - - pF Analog input resistance RAIN - - - - - - - 7.5 2.2 5.5 10.5 4 LSB - ANxx - - 5 μA - ANxx Interchannel disparity Analog port input leak current Analog input voltage Remarks kΩ VCC ≥ 2.7 V 1.8 ≤ VCC < 2.7 V 1.65 ≤ VCC < 1.8 V VSS AVRH V 2.7 VCC ≥ 2.7V VCC V AVRH Reference voltage VCC VCC < 2.7V AVRL VSS VSS V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The minimum conversion time is computed according to the following conditions: sampling time=0.3 μs, compare time=0.7 μs VCC ≥ 2.7 V sampling time=1.2 μs, compare time=2.8 μs 1.8 ≤ VCC < 2.7 V sampling time=3.0 μs, compare time=7.0 μs 1.65 ≤ VCC < 1.8 V Ensure that the conversion time satisfies the specifications of the sampling time (tS) and compare clock cycle (tCCK). For details of the settings of the sampling time and compare clock cycle, refer to "Chapter: A/D Converter" in "FM0+ Family Peripheral Manual Analog Macro Part". The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram". The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: The required sampling time varies according to the external impedance. Set a sampling time that satisfies (Equation 1). *3: The compare time (tC) is the result of (Equation 2). Document Number: 002-00234 Rev.*A Page 82 of 100 S6E1C1 Series ANxx Analog input pins Analog signal source REXT Comparator RAIN CAIN (Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D Converter = 2.2 kΩ with 2.7 < VCC < 3.6 Input resistance of A/D Converter = 5.5 kΩ with 1.8 < VCC < 2.7 Input resistance of A/D Converter = 10.5 kΩ with 1.65 < VCC < 1.8 CAIN: REXT: Input capacitance of A/D Converter = 7.5 pF with 1.65 < VCC < 3.6 Output impedance of external circuit (Equation 2) tC=tCCK × 14 tC: Compare time tCCK : Compare clock cycle Document Number: 002-00234 Rev.*A Page 83 of 100 S6E1C1 Series Definitions of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} 0xFFD VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output Differential Nonlinearity 0x001 Analog input : : : : (Actually-measured value) 0x(N-2) AVRH Differential Nonlinearity of digital output N = N VZT VFST VNT (Actually-measured value) Actual conversion characteristics Integral Nonlinearity of digital output N = 1LSB = V(N+1)T VNT VZT (Actually-measured value) VSS Ideal characteristics 0x(N-1) Actual conversion characteristics Ideal characteristics 0x002 0xN Actual conversion characteristics VSS Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB AVRH [LSB] - 1 [LSB] VFST – VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-00234 Rev.*A Page 84 of 100 S6E1C1 Series 11.6 Low-Voltage Detection Characteristics 11.6.1 Low-Voltage Detection Reset Parameter Symbol (TA=-40°C to +105°C) Conditions Min 1.38 1.43 Value Typ 1.50 1.55 Max 1.60 1.65 Unit Detected voltage Released voltage VDL VDH LVD stabilization wait time TLVDW - - - 8160× *2 tCYCP μs LVD detection delay time TLVDDL - - - 200 μs Fixed *1 V V Remarks When voltage drops When voltage rises *1: The value of low voltage detection reset is always fixed. *2: tCYCP indicates the APB1 bus clock cycle time. Document Number: 002-00234 Rev.*A Page 85 of 100 S6E1C1 Series 11.6.2 Low-Voltage Detection Interrupt (TA=-40°C to +105°C) Min 1.56 1.61 1.61 1.66 1.66 1.70 1.70 1.75 1.75 1.79 1.79 1.84 1.84 1.89 1.89 1.93 2.30 2.39 2.39 2.48 2.48 2.58 2.58 2.67 2.67 2.76 2.76 2.85 2.85 2.94 2.94 3.04 Value Typ 1.70 1.75 1.75 1.80 1.80 1.85 1.85 1.90 1.90 1.95 1.95 2.00 2.00 2.05 2.05 2.10 2.50 2.60 2.60 2.70 2.70 2.80 2.80 2.90 2.90 3.00 3.00 3.10 3.10 3.20 3.20 3.30 - - - - - - Symbo l Conditions Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH SVHI=00100 LVD stabilization wait time TLVDW LVD detection delay time TLVDDL Parameter *: SVHI=00101 SVHI=00110 SVHI=00111 SVHI=01000 SVHI=01001 SVHI=01010 SVHI=01011 SVHI=01100 SVHI=01101 SVHI=01110 SVHI=01111 SVHI=10000 SVHI=10001 SVHI=10010 SVHI=10011 Max 1.84 1.89 1.89 1.94 1.94 2.00 2.00 2.05 2.05 2.11 2.11 2.16 2.16 2.21 2.21 2.27 2.70 2.81 2.81 2.92 2.92 3.02 3.02 3.13 3.13 3.24 3.24 3.35 3.35 3.46 3.46 3.56 8160 × tCYCP* 200 Uni t V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs μs tCYCP represents the APB1 bus clock cycle time. Document Number: 002-00234 Rev.*A Page 86 of 100 S6E1C1 Series 11.7 Flash Memory Write/Erase Characteristics Parameter Sector erase time Large sector Small sector (VCC=1.65 V to 3.6 V, TA=- 40°C to +105°C) Min Value Typ Max - 1.1 2.7 - 0.3 0.9 Unit s Remarks The sector erase time includes the time of writing prior to internal erase. The halfword (16-bit) write time excludes the system-level overhead. The chip erase time includes the time of Chip erase time 4.5 11.7 s writing prior to internal erase. *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write. Halfword (16-bit) write time - 30 528 μs Write/Erase Cycle and Data Hold Time Write/Erase Cycle Data Hold Time (Year) 1,000 20* Remarks 10,000 10* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C). Document Number: 002-00234 Rev.*A Page 87 of 100 S6E1C1 Series 11.8 Return Time from Low-Power Consumption Mode 11.8.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time Current Mode (VCC=1.65 V to 3.6 V, TA=-40°C to +105°C) Parameter Sleep mode Mode to return Symbol each Run Modes High-speed CR Run mode Main Run mode PLL Run mode Low-speed CR Run mode Sub Run mode High-speed CR Run mode Low-speed CR Run mode Main Run mode Sub Run mode PLL Run mode High-speed CR Run mode Low-speed CR Run mode Sub Run mode Main Run mode PLL Run mode Timer mode Stop Mode RTC mode Value Typ Max *1 4*HCLK tICNT Deep Standby RTC mode High-speed CR Run mode Deep Standby Stop mode *1: The maximum value depends on the condition of environment. Unit Remarks When High-speed CR is enabled When High-speed CR is enabled μs 12*HCLK 13*HCLK μs 34+12*HCLK 72+13*HCLK μs 34+12*HCLK 72+13*HCLK μs 34+12*HCLK +tOSCWT 72+13*HCLK +tOSCWT μs 34+12*HCLK 72+13*HCLK μs 34+12*HCLK +tOSCWT 72+13*HCLK +tOSCWT μs 43 281 μs *2 *2 *2: tOSCWT : Oscillator stabilization time. Operation Example of Return from Low-Power Consumption Mode (by External Interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-00234 Rev.*A Page 88 of 100 S6E1C1 Series Operation Example of Return from Low-Power Consumption Mode (by Internal Resource Interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual". Document Number: 002-00234 Rev.*A Page 89 of 100 S6E1C1 Series 11.8.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC=1.65 V to 3.6 V, TA=-40°C to +105°C) Parameter Current Mode High-speed CR Sleep mode Main Sleep mode PLL Sleep mode Mode to return Symbol Typ Value Max* Unit 20 22 μs Low-speed CR Sleep mode 50 106 μs Sub Sleep mode 112 137 μs 20 22 μs Low-speed CR Timer mode 87 159 μs Sub Timer mode 148 209 μs 45 68 μs 43 281 μs High-speed CR Timer mode Main Timer mode PLL Timer mode High-speed CR Run mode Stop mode RTC mode Deep Standby RTC mode Deep Standby Stop mode *: The maximum value depends on the accuracy of built-in CR. tRCNT Remarks When High-speed CR is enabled When High-speed CR is enabled When High-speed CR is enabled When High-speed CR is enabled Operation Example of Return from Low-Power Consumption Mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation Document Number: 002-00234 Rev.*A Start Page 90 of 100 S6E1C1 Series Operation Example of Return from Low Power Consumption Mode (by Internal Resource Reset*) Internal resource reset Internal reset Release Reset active tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual". − The time during the power-on reset/low-voltage detection reset is excluded. See "11.4.7 Power-on Reset Timing in 11.4 AC Characteristics in 11. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-00234 Rev.*A Page 91 of 100 S6E1C1 Series 12. Ordering Information Part number On-chip Flash memory On-Chip SRAM S6E1C12D0AGV20000 S6E1C11D0AGV20000 S6E1C12C0AGV20000 S6E1C11C0AGV20000 S6E1C12B0AGP20000 S6E1C11B0AGP20000 S6E1C12D0AGN20000 S6E1C11D0AGN20000 S6E1C12C0AGN20000 S6E1C11C0AGN20000 S6E1C12B0AGN20000 S6E1C11B0AGN20000 [Kbyte] 128 64 128 64 128 64 128 64 128 64 128 64 [Kbyte] 16 12 16 12 16 12 16 12 16 12 16 12 Document Number: 002-00234 Rev.*A Package Plastic  LQFP (0.50 mm pitch), 64 pins (FPT-64P-M38) Plastic  LQFP (0.50 mm pitch), 48 pins (FPT-48P-M49) Plastic  LQFP (0.80 mm pitch), 32 pins (FPT-32P-M30) Plastic  QFN64 (0.50 mm pitch), 64 pins (LCC-64P-M25) Plastic  QFN48 (0.50 mm pitch), 48 pins (LCC-48P-M74) Plastic  QFN32 (0.50 mm pitch), 32 pins (LCC-32P-M73) Packing Tray Tray Tray Tray Tray Tray Page 92 of 100 S6E1C1 Series 13. Package Dimensions 32-pin plastic LQFP Lead pitch 0.80 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.60 mm MAX (FPT-32P-M30) 32-pin plastic LQFP (FPT-32P-M30) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ +0.05 * 7.00±0.10(.276±.004)SQ 24 0.13 –0.00 +.002 .005 –.000 17 16 25 0.10(.004) Details of "A" part 1.60 MAX (Mounting height) (.063) MAX INDEX 0.25(.010) 9 32 0~7° 1 0.80(.031) C 0.35 .014 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2 Document Number: 002-00234 Rev.*A "A" 8 +0.08 –0.03 +.003 –.001 0.20(.008) M 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 93 of 100 S6E1C1 Series 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00 ± 0.20(.354 ± .008)SQ *7.00± 0.10(.276 ± .004)SQ 36 0.145± 0.055 (.006 ± .002) 25 37 24 0.08(.003) INDEX 48 +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 13 "A" 1 0.50(.020) C Details of "A" part 0.10 ± 0.10 (.004 ± .004) (Stand off) 12 0.22 ± 0.05 (.008 ± .002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 Document Number: 002-00234 Rev.*A 0°~8° 0.25(.010) M 0.60 ± 0.15 (.024 ± .006) Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 94 of 100 S6E1C1 Series 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ 0.145 ± 0.055 (.006 ± .002) *10.00±0.10(.394±.004)SQ 48 33 Details of "A" part 32 49 0.08(.003) +0.20 1.50 –0.10 (Mounting height) –.004 .059 +.008 0.25(.010) 0~8° INDEX 17 64 1 0.22±0.05 (.009±.002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 Document Number: 002-00234 Rev.*A 0.10 ± 0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60 ± 0.15 (.024±.006) M Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 95 of 100 S6E1C1 Series 32-pin plastic QFN Lead pitch 0.50 mm Package width × package length 5.00 mm × 5.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.06 g (LCC-32P-M73) 32-pin plastic QFN (LCC-32P-M73) 5.00±0.10 (.197±.004) 3.20±0.10 (.068±.004) 0.25±0.05 (.010±.002) INDEX AREA 5.00±0.10 (.197±.004) 3.20±0.10 (.068±.004) 0.75±0.05 (.030±.002) (0.20) ((.008)) C 0.50(.020) (TYP) 0.40±0.05 (.016±.002) 1PIN CORNER C0.25(C.010) 0.02 +0.03 -0.02 (.0008 +.0012 -.0008 ) 2013 FUJITSU SEMICONDUCTOR LIMITED HMbC32-73Sc-1-1 Document Number: 002-00234 Rev.*A Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 96 of 100 S6E1C1 Series 48-pin plastic QFN Lead pitch 0.50 mm Package width× package length 7.00 mm × 7.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.12 g (LCC-48P-M74) 48-pin plastic QFN (LCC-48P-M74) 7.00±0.10 (.276±.004) INDEX AREA 4.65±0.15 (.183±.006) 7.00±0.10 (.276±.004) 4.65±0.15 (.183±.006) +0.05 0.25 -0.07 (.010 +.002 ) -.003 1PIN CORNER C0.30(C.020) 0.50(.020) (TYP) 0.75±0.05 (.030±.002) (0.20) ((.008)) C 0.50±0.05 (.020±.002) +0.03 0.02 -0.02 (.0008 +.0012 ) -.0008 2013 FUJITSU SEMICONDUCTOR LIMITED HMbC48-74Sc-1-1 Document Number: 002-00234 Rev.*A Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 97 of 100 S6E1C1 Series 64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.21 g (LCC-64P-M25) 64-pin plastic QFN (LCC-64P-M25) 9.00±0.10 (.354±.004) INDEX AREA 7.20±0.15 (.283±.006) 9.00±0.10 (.354±.004) 7.20±0.15 (.283±.006) 0.25±0.05 (.010±.002) 1PIN CORNER C0.50(C.020) 0.50(.020) (TYP) 0.75±0.05 (.030±.002) (0.20) ((.008)) C 0.40±0.05 (.016±.002) +0.03 0.02 -0.02 (.0008 +.0012 -.0008 ) 2013 FUJITSU SEMICONDUCTOR LIMITED HMbC64-25Sc-1-1 Document Number: 002-00234 Rev.*A Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 98 of 100 S6E1C1 Series Document History Document Title: S6E1C1 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller Document Number: 002-00234 Revision ECN Orig. of Submission Change Date Description of Change ** 4896074 TEKA 08/31/2015 New Spec. *A 4955136 TEKA 10/9/2015 AC/DC characteristics updated. Typo fixed in “List of Pin Functions”. Document Number: 002-00234 Rev.*A Page 99 of 100 S6E1C1 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF Spansion Products PSoC® Solutions cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless spansion.com/products Cypress, the Cypress logo, Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. 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Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 002-00234 Rev.*A October 9, 2015 Page 100 of 100