S6E2C58H0AGV2000A

S6E2C5 Series 32-bit ARM® Cortex®-M4F FM4 Microcontroller Devices in the S6E2C5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part (002-04856)." Features 32-bit ARM Cortex-M4F Core External Bus Interface  Supports SRAM, NOR, NAND flash and SDRAM device  Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)  8-/16-/32-bit data width  Up to 25-bit address bus  Processor version: r0p1  Up to 200 MHz frequency operation  FPU built-in  Support DSP instructions  Memory protection unit (MPU): improves the reliability of an embedded system  Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels  Maximum Access size: 256M byte  Supports address/data multiplexing  Supports external RDY function  Supports scramble function  Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units.  24-bit system timer (Sys Tick): system timer for OS task management  Possible to set two kinds of the scramble key Note: It is necessary to use the Cypress provided software library to use the scramble function. On-chip Memories  Flash memory This series is based on two independent on-chip flash memories.  Up to 2048 Kbytes flash accelerator system with 16 Kbytes trace buffer memory  Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent single cycle access to flash memory can be obtained by the flash accelerator system.  Security function for code protection USB Interface (Max two Channels) The USB interface is composed of a device and a host.  USB device  USB 2.0 Full-speed supported 6 EndPoint supported • EndPoint 0 is control transfer • EndPoint 1, 2 can be selected bulk-transfer, interrupt-transfer or isochronous-transfer • EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer • EndPoint 1 to 5 comprise double buffer  The size of each endpoint is as follows. • Endpoint 0, 2 to 5: 64 byte • EndPoint 1: 256 byte  Built-in  Max  SRAM This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to the I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to system bus of Cortex-M4F core.  USB host  SRAM0: up to 192 Kbytes  SRAM1: 32 Kbytes  SRAM2: 32 Kbytes Cypress Semiconductor Corporation Document Number: 002-04984 Rev.*B  USB2.0 Full-Speed/Low-Speed supported interrupt-transfer, and isochronous-transfer  Bulk-transfer, support Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet length supported  Wake-up function supported  USB • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 20, 2017 S6E2C5 Series CAN Interface (Max two Channels)  Compatible with CAN specification 2.0A/B  Maximum transfer rate: 1 Mbps  Built-in 32-message buffer  I2 C CAN-FD Interface (One Channel)  Compatible with CAN Specification 2.0A/B DMA Controller (Eight channels)  Maximum transfer rate: 5 Mbps  Message buffer for receiver: up to 192 messages  Message buffer for transmitter: up to 32 messages  Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported DMA controller has an independent bus, so the CPU and DMA controller can process simultaneously.  Eight independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  CAN with flexible data rate (non-ISO CAN FD)  Transfer address area: 32-bit (4 GB)  Notes:  Transfer mode: Block transfer/Burst transfer/Demand  CAN FD cannot communicate between non-ISO CAN FD and ISO CAN FD, because non-ISO CAN FD and ISO CAN FD are different frame format.  About the problem of "non-ISO CAN FD", see the White Paper from CiA(CAN in Automation). http://www.can-newsletter.org/engineering/standardization/ 141222_can-fd-and-crc-issued_white-paper_bosch Multi-function Serial Interface (Max 16 channels)  Separate 64 byte receive and transmit FIFO buffers for channels 0 to 7.  Operation mode is selectable for each channel from the following:  UART  CSIO (SPI)  LIN  I2 C  UART  Full-duplex double buffer with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detect functions available (parity errors, framing errors, and overrun errors) transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 DSTC (Descriptor System data Transfer Controller; 256 Channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed on the memory, can access directly the memory/peripheral device and perform the data-transfer operation. It supports the software activation, the hardware activation, and the chain activation functions.  Selection  CSIO (SPI)  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch 6 and ch 7 only)  Supports high-speed SPI (ch 4 and ch 6 only)  Data length 5 to 16-bit A/D Converter (Max 32 channels)  12-bit A/D Converter  Successive approximation type three units  Conversion time: 0.5 μs at 5 V  Priority conversion available (priority at two levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: 4 steps)  Built-in  LIN  LIN protocol Rev.2.1 supported double buffer  Master/slave mode supported  LIN break field generation (can change to 13- to 16-bit length)  LIN break delimiter generation (can change to 1- to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  Full-duplex Document Number: 002-04984 Rev.*B D/A Converter (Max 2 Channels)  R-2R type  12-bit resolution Page 2 of 201 S6E2C5 Series Base Timer (Max 16 Channels) Real-Time Clock (RTC) Operation mode is selected from the following for each channel: The real-time clock can count year, month, day, hour, minute, second, or day of the week from 00 to 99.  16-bit PWM timer  Interrupt function with specifying date and time  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer (year/month/day/hour/minute) is available. This function is also available by specifying only year, month, day, hour, or minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count. General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals; moreover, the port relocate function is built in. It can set the I/O port to which the peripheral function can be allocated.  Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC; Max four Channels)  Capable of reading pin level directly The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. It is also possible to use up/down counter.  Built-in port-relocate function  The detection edge of the three external event input pins AIN,  Capable of pull-up control per pin  Up to 120 high-speed general-purpose I/O ports in 144 pin package  Some pins 5V tolerant I/O. See 4. Pin Descriptions and 5. I/O Circuit Type for the corresponding pins. Multi-function Timer (Max three Units) BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter)  16-bit free-run timer × 3 ch/unit The dual timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the following for each channel:  Input capture × 4 ch/unit  Free-running  Output compare × 6 ch/unit  Periodic (= Reload)  A/D activation compare × 6 ch/unit  One shot The multi-function timer is composed of the following blocks: Minimum resolution: 5.00 ns  Waveform generator × 3 ch/unit  16-bit PPG timer × 3 ch/unit Watch Counter  PWM signal output function The watch counter is used for wake up from low-power consumption mode. It is possible to select the main clock, sub clock, built-in High-speed CR clock, or built-in low-speed CR clock as the clock source.  DC chopper waveform output function  Interval timer: up to 64 s (max) with a sub clock of 32.768 The following functions can be used to achieve the motor control:  Dead time function kHz  Input capture function  A/D convertor activate function External Interrupt Controller Unit  DTIF (motor emergency stop) interrupt function  External interrupt input pin: Max 32 pins  Include one non-maskable interrupt (NMI) Document Number: 002-04984 Rev.*B Page 3 of 201 S6E2C5 Series Watchdog Timer (2 Channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs: a "hardware" watchdog and a "software" watchdog. The hardware watchdog timer is clocked by low-speed internal CR oscillator. The hardware watchdog is thus active in any power saving mode except RTC mode and Stop mode. I2S (Inter-IC Sound Bus) Interface (TX x 1 channel, RX x 1 channel)  Supports three transfer protocols  I2 S  Left justified mode  Separate clock generation block for flexible system integration options  DSP  Master/slave mode selectable  RX Only, TX Only or TX and RX simultaneous operation selectable Cyclic Redundancy Check (CRC) Accelerator  Word length is programmable from 7-bits to 32 bits The CRC accelerator helps to verify data transmission or storage integrity.  RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 CCITT CRC16 and IEEE-802.3 CRC32 are supported.  DMA, interrupts, or polling based data transfer supported words x 32-bits)  CCITT CRC16 generator polynomial: 0x1021  IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7 Clock and Reset  Clocks Programmable Cyclic Redundancy Check (PRGCRC) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16, IEEE-802.3 CRC32 and generating polynomial are supported.  CCITT CRC16 generator polynomial: 0x1021  IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7  Generating polynomial SD Card Interface It is possible to use the SD card that conforms to the following standards. Five clock sources (two external oscillators, two internal CR oscillators, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz clock: 32.768 kHz  High-speed internal CR clock: 4 MHz  Low-speed internal CR clock: 100 kHz  Main PLL Clock  Sub  Resets  Reset requests from INITX pin on reset  Software reset  Watchdog timer reset  Low-voltage detector reset  Clock supervisor reset  Power Clock Supervisor (CSV)  Part 1 Physical Layer Specification version 3.01 Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  Part E1 SDIO Specification version 3.00  External OSC clock failure (clock stop) is detected, reset is  Part A2 SD Host Controller Standard Specification version 3.00  1-bit or 4-bit data bus asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include two-stage monitoring of voltage on the VCC pins. when the voltage falls below the voltage that has been set, the low-voltage detector function generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Document Number: 002-04984 Rev.*B Page 4 of 201 S6E2C5 Series Low-power Consumption Mode Debug Six low power consumption modes are supported.  Serial wire JTAG debug port (SWJ-DP)  Sleep  Embedded trace macrocells (ETM) provide comprehensive  Timer debug and trace facilities.  RTC  AHB trace macrocells (HTM)  Stop  Deep standby RTC (selectable from with/without RAM retention) Unique ID Unique value of the device (41-bit) is set.  Deep standby stop (selectable from with/without RAM retention) Power Supply Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used.  Four power supplies  Wide range voltage: VCC = 2.7 V to 5.5 V  Power supply for USB ch 0 I/O: USBVCC0 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for USB ch 1 I/O: USBVCC1 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for VBAT: VBAT = 1.65 V to 5.5 V  RTC  32-kHz oscillation circuit  Power-on circuit  Back up register: 32 bytes  Port circuit Document Number: 002-04984 Rev.*B Page 5 of 201 S6E2C5 Series Table of Contents Features ........................................................................................................................................................................... 1 1. Product Lineup ............................................................................................................................................................ 8 2. Packages .................................................................................................................................................................... 10 3. Pin Assignments ....................................................................................................................................................... 11 4. Pin Descriptions ........................................................................................................................................................ 15 5. I/O Circuit Type .......................................................................................................................................................... 64 6. Handling Precautions................................................................................................................................................ 72 6.1 Precautions for Product Design ................................................................................................................................ 72 6.2 Precautions for Package Mounting ........................................................................................................................... 73 6.3 Precautions for Use Environment ............................................................................................................................. 75 7. Handling Devices....................................................................................................................................................... 76 8. Block Diagram ........................................................................................................................................................... 79 9. Memory Size .............................................................................................................................................................. 80 10. Memory Map .............................................................................................................................................................. 80 11. Pin Status in Each CPU State ................................................................................................................................... 86 12. Electrical Characteristics.......................................................................................................................................... 95 12.1 Absolute Maximum Ratings ...................................................................................................................................... 95 12.2 Recommended Operating Conditions ....................................................................................................................... 97 12.3 DC Characteristics .................................................................................................................................................. 101 12.3.1 Current Rating ..................................................................................................................................................... 101 12.3.2 Pin Characteristics ............................................................................................................................................... 111 12.4 AC Characteristics .................................................................................................................................................. 113 12.4.1 Main Clock Input Characteristics ......................................................................................................................... 113 12.4.2 Sub Clock Input Characteristics ........................................................................................................................... 114 12.4.3 Built-In CR Oscillation Characteristics ................................................................................................................. 114 12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL) .............................. 115 12.4.5 Operating Conditions of USB PLL・I2S PLL (in the Case of Using Main Clock for Input Clock of PLL) .............. 115 12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) .......................................................................................................................................................................... 116 12.4.7 Reset Input Characteristics .................................................................................................................................. 116 12.4.8 Power-On Reset Timing....................................................................................................................................... 117 12.4.9 GPIO Output Characteristics ............................................................................................................................... 117 12.4.10 External Bus Timing ............................................................................................................................................. 118 12.4.11 Base Timer Input Timing ...................................................................................................................................... 129 12.4.12 CSIO (SPI) Timing ............................................................................................................................................... 130 12.4.13 External Input Timing ........................................................................................................................................... 163 12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................. 164 12.4.15 I2C Timing ............................................................................................................................................................ 167 12.4.16 SD Card Interface Timing .................................................................................................................................... 169 12.4.17 ETM/ HTM Timing ................................................................................................................................................ 171 12.4.18 JTAG Timing ........................................................................................................................................................ 172 12.4.19 I2S Timing ............................................................................................................................................................ 173 12.4.20 High-Speed Quad SPI Timing.............................................................................................................................. 178 12.5 12-bit A/D Converter ............................................................................................................................................... 180 12.6 12-bit D/A Converter ............................................................................................................................................... 183 12.7 USB Characteristics................................................................................................................................................ 184 Document Number: 002-04984 Rev.*B Page 6 of 201 S6E2C5 Series 12.8 Low-Voltage Detection Characteristics ................................................................................................................... 188 12.8.1 Low-Voltage Detection Reset .............................................................................................................................. 188 12.8.2 Interrupt of Low-Voltage Detection ...................................................................................................................... 188 12.9 MainFlash Memory Write/Erase Characteristics ..................................................................................................... 189 12.10 Dual Flash Memory Write/Erase Characteristics .................................................................................................... 189 12.11 Standby Recovery Time ......................................................................................................................................... 190 12.11.1 Recovery cause: Interrupt/WKUP ........................................................................................................................ 190 12.11.2 Recovery Cause: Reset ....................................................................................................................................... 192 13. Ordering Information............................................................................................................................................... 194 14. Package Dimensions............................................................................................................................................... 195 15. Major Changes ......................................................................................................................................................... 195 Document History ............................................................................................................................................................... 200 Sales, Solutions, and Legal Information ........................................................................................................................... 201 Document Number: 002-04984 Rev.*B Page 7 of 201 S6E2C5 Series 1. Product Lineup Memory Size Product Name On-chip flash memory On-chip SRAM SRAM0 SRAM1 SRAM2 S6E2C58H/J/L S6E2C59H/J/L S6E2C5AH/J/L 1024 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes 32 Kbytes 1536 Kbytes 192 Kbytes 128 Kbytes 32 Kbytes 32 Kbytes 2048 Kbytes 256 Kbytes 192 Kbytes 32 Kbytes 32 Kbytes Function S6E2C58H0A S6E2C58J0A S6E2C58L0A S6E2C59H0A S6E2C59J0A S6E2C59L0A S6E2C5AH0A S6E2C5AJ0A S6E2C5AL0A 144 176/192 216 Cortex-M4F, MPU, NVIC 128 ch 200 MHz 2.7V to 5.5V 2 ch 2 ch (Max) 1 ch 8ch 256 ch Product Name Pin count CPU Freq. Power supply voltage range USB2.0 (device/host) CAN CAN-FD (non-ISO CAN FD) DMAC DSTC Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash NAND flash External bus interface Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash , NAND flash Addr: 25-bit (Max), Data: 8-/16-/32-bit CS: 9 (Max), SRAM, NOR flash , NAND flash, SDRAM SDRAM MF timer Multi-function serial interface (UART/CSIO/LIN/I2C) Base timer (PWC/Reload timer/PWM/PPG) A/D activation compare Input capture Free-run timer Output compare Waveform generator PPG SD card interface I2 S High-speed quad SPI QPRC Dual timer Real-time clock Watch counter CRC accelerator Watchdog timer External interrupts I/O ports 12-bit A/D converter 12-bit D/A converter CSV (clock supervisor) LVD (low-voltage detector) Document Number: 002-04984 Rev.*B 16ch (Max) ch 0 to ch 7：FIFO, ch 8 to ch 15：No FIFO 16 ch (Max) 6 ch 4 ch 3 ch 6 ch 3 ch 3 ch 3 units (Max) 1 unit - 120 pins (Max) 24 ch (3 units) 1 unit 1 unit 4 ch (Max) 1 unit 1 unit 1 unit Yes (fixed, programmable) 1 ch (SW) + 1 ch (HW) 32 pins (Max)+ NMI × 1 152 pins (Max) 190 pins (Max) 32 ch (3 units) 2 units (Max) Yes 2 ch Page 8 of 201 S6E2C5 Series Product Name Built-in CR High-speed Low-speed S6E2C58H0A S6E2C59H0A S6E2C5AH0A S6E2C58J0A S6E2C59J0A S6E2C5AJ0A 4 MHz 100 kHz SWJ-DP/ETM/HTM Yes S6E2C58L0A S6E2C59L0A S6E2C5AL0A Debug function Unique ID Notes: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. − See 12.4.3 Built-In CR Oscillation Characteristics for the accuracy of the built-in CR. Document Number: 002-04984 Rev.*B Page 9 of 201 S6E2C5 Series 2. Packages Product Name Package LQFP: LQS144 (0.5-mm pitch) LQFP: LQP176 (0.5-mm pitch) BGA : LBE192 (0.8-mm pitch) LQFP: LQQ216 (0.4-mm pitch) : Supported S6E2C58H0A S6E2C59H0A S6E2C5AH0A  - - S6E2C58J0A S6E2C59J0A S6E2C5AJ0A -   - S6E2C58L0A S6E2C59L0A S6E2C5AL0A  Note: − See 14. Package Dimensions for detailed information on each package. Document Number: 002-04984 Rev.*B Page 10 of 201 S6E2C5 Series 3. Pin Assignments LQS144 VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 (Top View) VCC 1 108 VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 107 P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 106 P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 105 USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_0 5 104 P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_0 6 103 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 102 P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 101 P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_0 9 100 P24/AN29/TIOA13_1/MAD18_0 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 10 99 P25/AN28/RX1_0/INT25_0/MAD17_0 PA9/SOT7_0/IC22_0/MADATA09_0 11 98 P26/TX1_0/MAD16_0 PAA/SCK7_0/IC23_0/MADATA10_0 12 97 P27/AN27/SIN5_0/INT24_0/MAD15_0 PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0 13 96 P28/AN26/SOT5_0/MAD14_0 PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0 14 95 P29/AN25/SCK5_0/MAD13_0 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 15 94 P2A/AN24/CTS5_0/MAD12_0 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 16 93 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 17 92 P1E/AN14/TIOA8_1/INT26_1/MAD10_0 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 18 91 P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 19 90 P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 20 89 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P32/BIN2_1/INT19_0/S_DATA1_0 21 88 P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P33/FRCK0_0/ZIN2_1/S_DATA0_0 22 87 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P34/IC03_0/INT00_1/S_CLK_0 23 86 P18/AN08/SIN2_0/TIOA3_2/INT10_0 VCC 24 85 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 VSS 25 84 P16/AN06/SOT11_0/TIOA2_2/BIN1_2 P35/IC02_0/INT01_1/S_CMD_0 26 83 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P36/IC01_0/INT02_1/S_DATA3_0 27 82 P14/AN04/SOT6_1/TX1_1 P37/IC00_0/INT03_1/S_DATA2_0 28 81 P13/AN03/SIN6_1/RX1_1/INT25_1 P38/ADTG_2/DTTI0X_0/S_WP_0 29 80 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 30 79 P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 31 78 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 32 77 AVRH P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 33 76 AVRL P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 34 75 AVSS P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 35 74 AVCC VSS 36 73 VCC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P7D/SCK1_1/RX2_0/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/TX2_0/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 144 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04984 Rev.*B Page 11 of 201 S6E2C5 Series LQP176 VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P64/CTS4_0/RTO25_1/INT29_1 P65/RTO24_1/INT28_1 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P95/RTS5_1/Q_CS0_0 P94/CTS5_1/Q_SCK_0 P93/SCK5_1/INT15_1/Q_IO0_0 P92/SOT5_1/INT14_1/Q_IO1_0 P91/SIN5_1/INT13_1/Q_IO2_0 P90/INT12_1/Q_IO3_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 (Top View) VCC 1 132 VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 131 P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 130 P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 129 USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_0 5 128 P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_0 6 127 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 126 P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 125 P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_0 9 124 P24/AN29/TIOA13_1/MAD18_0 P50/SCS72_0/RTO00_1/TIOA8_2 10 123 P25/AN28/RX1_0/INT25_0/MAD17_0 P51/SCS73_0/RTO01_1/TIOB8_2 11 122 P26/TX1_0/MAD16_0 P52/RTO02_1/TIOA9_2 12 121 P27/AN27/SIN5_0/INT24_0/MAD15_0 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 13 120 P28/AN26/SOT5_0/MAD14_0 PA9/SOT7_0/IC22_0/MADATA09_0 14 119 P29/AN25/SCK5_0/MAD13_0 PAA/SCK7_0/IC23_0/MADATA10_0 15 118 P2A/AN24/CTS5_0/MAD12_0 PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0 16 117 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0 17 116 P1E/AN14/TIOA8_1/INT26_1/MAD10_0 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 18 115 PB7/AN23/TIOB12_1/TRACED7 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 19 114 PB6/AN22/SCK8_1/TIOA12_1/TRACED6 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 20 113 PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 21 112 PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 22 111 P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 23 110 P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P30/RX0_1/TIOA13_2/INT03_2/I2SDI0_0 24 109 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P31/TX0_1/TIOB13_2/I2SCK0_0 25 108 P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P32/BIN2_1/INT19_0/S_DATA1_0 26 107 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P33/FRCK0_0/ZIN2_1/S_DATA0_0 27 106 P18/AN08/SIN2_0/TIOA3_2/INT10_0 P34/IC03_0/INT00_1/S_CLK_0 28 105 PB3/AN19/SCS62_1/TIOB10_1 VCC 29 104 PB2/AN18/SCS61_1/TIOA10_1/INT09_1 VSS 30 103 PB1/AN17/SCS60_1/TIOB9_1/INT08_1 P35/IC02_0/INT01_1/S_CMD_0 31 102 PB0/AN16/SCK6_1/TIOA9_1 P36/IC01_0/INT02_1/S_DATA3_0 32 101 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 P37/IC00_0/INT03_1/S_DATA2_0 33 100 P16/AN06/SOT11_0/TIOA2_2/BIN1_2 P38/ADTG_2/DTTI0X_0/S_WP_0 34 99 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 35 98 P14/AN04/SOT6_1/TX1_1 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 36 97 P13/AN03/SIN6_1/RX1_1/INT25_1 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 37 96 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 38 95 P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 39 94 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 40 93 AVRH P5D/SIN10_1/TIOB11_2/INT01_2/I2SMCLK0_0 41 92 AVRL P5E/SOT10_1/TIOA12_2/I2SDO0_0 42 91 AVSS P5F/SCK10_1/TIOB12_2/I2SWS0_0 43 90 AVCC VSS 44 89 VCC 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P7D/SCK1_1/RX2_0/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/TX2_0/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP PF0/SCS63_0/RX2_1/FRCK1_1/TIOA15_1/INT22_1 PF1/SCS62_0/TX2_1/TIOB15_1/INT23_1 P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 PF2/RTO10_1/TIOA6_1/MRASX_0 PF3/RTO11_1/TIOB6_1/INT05_1/MCASX_0 PF4/RTO12_1/TIOA7_1/INT06_1/MSDWEX_0 PF5/RTO13_1/TIOB7_1/INT07_1/MCSX8_0 PF6/RTO14_1/TIOA14_1/INT20_1/MSDCKE_0 PF7/RTO15_1/TIOB14_1/INT21_1/MSDCLK_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 176 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04984 Rev.*B Page 12 of 201 S6E2C5 Series LQQ216 VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P64/CTS4_0/RTO25_1/INT29_1 P65/RTO24_1/INT28_1 P66/SIN13_1/RTO23_1/TIOA15_2/INT15_2 P67/SOT13_1/RTO22_1/TIOB15_2 P68/SCK13_1/RTO21_1/TIOA14_2 P69/RTO20_1/TIOB14_2 P6A/DTTI2X_1/TIOA7_2 P6B/SIN14_1/IC20_1/TIOB7_2/INT14_2 P6C/SOT14_1/IC21_1/TIOA6_2 P6D/SCK14_1/IC22_1/TIOB6_2 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P97/TX0_2/INT13_2/Q_CS2_0 P96/RX0_2/INT12_2/Q_CS1_0 P95/RTS5_1/Q_CS0_0 P94/CTS5_1/Q_SCK_0 P93/SCK5_1/INT15_1/Q_IO0_0 P92/SOT5_1/INT14_1/Q_IO1_0 P91/SIN5_1/INT13_1/Q_IO2_0 P90/INT12_1/Q_IO3_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 (Top View) VCC 1 162 VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 161 P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 160 P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 159 USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_0 5 158 P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_0 6 157 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 156 P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 155 P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_0 9 154 P24/AN29/TIOA13_1/MAD18_0 P50/SCS72_0/RTO00_1/TIOA8_2/MADATA16_0 10 153 P25/AN28/RX1_0/INT25_0/MAD17_0 P51/SCS73_0/RTO01_1/TIOB8_2/MADATA17_0 11 152 P26/TX1_0/MAD16_0 P52/RTO02_1/TIOA9_2/MADATA18_0 12 151 PBF/SIN0_1/ZIN3_2/INT11_2/TRACED15 P53/RTO03_1/TIOB9_2/MADATA19_0 13 150 PBE/SOT0_1/BIN3_2/TRACED14 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 14 149 PBD/SCK0_1/RX1_2/AIN3_2/INT10_2/TRACED13 PA9/SOT7_0/IC22_0/MADATA09_0 15 148 PBC/TX1_2/TRACED12 PAA/SCK7_0/IC23_0/MADATA10_0 16 147 P27/AN27/SIN5_0/INT24_0/MAD15_0 PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0 17 146 P28/AN26/SOT5_0/MAD14_0 PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0 18 145 P29/AN25/SCK5_0/MAD13_0 P54/SIN15_1/RTO04_1/TIOA10_2/INT00_2/MADATA20_0 19 144 P2A/AN24/CTS5_0/MAD12_0 P55/SOT15_1/RTO05_1/TIOB10_2/MADATA21_0 20 143 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 P56/SCK15_1/DTTI0X_1/TIOB0_1/MADATA22_0 21 142 P1E/AN14/TIOA8_1/INT26_1/MAD10_0 P57/IC00_1/TIOB1_1/MADATA23_0 22 141 PB7/AN23/TIOB12_1/TRACED7 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 23 140 PB6/AN22/SCK8_1/TIOA12_1/TRACED6 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 24 139 PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 25 138 PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4 P58/SIN11_1/IC01_1/TIOB2_1/INT02_2/MADATA24_0 26 137 VCC P59/SOT11_1/IC02_1/TIOB3_1/MADATA25_0 27 136 VSS P5A/SCK11_1/IC03_1/TIOB4_1/MADATA26_0 28 135 P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P5B/FRCK0_1/TIOB5_1/MADATA27_0 29 134 P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 30 133 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 LQFP - 216 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 31 132 P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 32 131 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P5C/TIOA11_2/MADATA28_0/RTCCO_1/SUBOUT_1 33 130 P18/AN08/SIN2_0/TIOA3_2/INT10_0 P30/RX0_1/TIOA13_2/INT03_2/MDQM2_0/I2SDI0_0 34 129 PB3/AN19/SCS62_1/TIOB10_1 P31/TX0_1/TIOB13_2/MDQM3_0/I2SCK0_0 35 128 PB2/AN18/SCS61_1/TIOA10_1/INT09_1 P32/BIN2_1/INT19_0/S_DATA1_0 36 127 PB1/AN17/SCS60_1/TIOB9_1/INT08_1 P33/FRCK0_0/ZIN2_1/S_DATA0_0 37 126 PB0/AN16/SCK6_1/TIOA9_1 P34/IC03_0/INT00_1/S_CLK_0 38 125 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 VCC 39 124 P16/AN06/SOT11_0/TIOA2_2/BIN1_2 VSS 40 123 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P35/IC02_0/INT01_1/S_CMD_0 41 122 PBB/SCK9_1/ZIN2_2/TRACED11 P36/IC01_0/INT02_1/S_DATA3_0 42 121 PBA/SOT9_1/BIN2_2/TRACED10 P37/IC00_0/INT03_1/S_DATA2_0 43 120 PB9/SIN9_1/AIN2_2/INT09_2/TRACED9 P38/ADTG_2/DTTI0X_0/S_WP_0 44 119 PB8/ADTG_6/SCS63_1/INT08_2/TRACED8 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 45 118 P14/AN04/SOT6_1/TX1_1 107 108 PE3/X1 VSS 96 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 106 95 PF9/SCS71_1/IC10_1/BIN1_1 105 94 PF8/SCS70_1/DTTI1X_1/AIN1_1 MD0 93 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 PE2/X0 92 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 104 91 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 PE0/MD1 90 103 89 PF6/RTO14_1/TIOA14_1/INT20_1/MSDCKE_0 PF7/RTO15_1/TIOB14_1/INT21_1/MSDCLK_0 PFC/SIN7_1/IC13_1/INT06_2 88 PF5/RTO13_1/TIOB7_1/INT07_1/MCSX8_0 102 87 PF4/RTO12_1/TIOA7_1/INT06_1/MSDWEX_0 101 86 PFA/SCK7_1/IC11_1/ZIN1_1 85 PF2/RTO10_1/TIOA6_1/MRASX_0 PF3/RTO11_1/TIOB6_1/INT05_1/MCASX_0 PFB/SOT7_1/IC12_1/INT07_2 84 P74/SCK9_0/TIOB2_0/MAD03_0 100 83 P73/SOT9_0/TIOB1_0/MAD02_0 P7C/DA0/SCS61_0/INT04_1 82 99 81 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 80 P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 98 79 PF1/SCS62_0/TX2_1/TIOB15_1/INT23_1 97 78 PF0/SCS63_0/RX2_1/FRCK1_1/TIOA15_1/INT22_1 P79/SOT6_0/IC11_0/MAD08_0 77 P7A/SCK6_0/IC12_0/MAD09_0 76 P48/VREGCTL 75 VBAT P49/VWAKEUP 74 71 P7E/ADTG_7/TX2_0/FRCK1_0/MCSX0_0 P47/X1A 70 P7D/SCK1_1/RX2_0/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 73 69 P4E/SCS73_1/TX2_2 72 68 P4D/SCS72_1/RX2_2/INT05_2 INITX 67 P4C/SCK12_1/ZIN0_1 P46/X0A 66 VCC P4B/SOT12_1/BIN0_1 109 65 54 64 AVCC VSS VCC 110 P4A/SIN12_1/AIN0_1/INT04_2 53 63 AVSS P5F/SCK10_1/TIOB12_2/MADATA31_0/I2SWS0_0 VSS AVRL 111 62 112 52 C 51 P5E/SOT10_1/TIOA12_2/MADATA30_0/I2SDO0_0 61 AVRH P5D/SIN10_1/TIOB11_2/INT01_2/MADATA29_0/I2SMCLK0_0 60 113 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 50 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 59 114 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 49 58 P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 115 57 48 56 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 55 P13/AN03/SIN6_1/RX1_1/INT25_1 116 VCC 117 47 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 46 P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04984 Rev.*B Page 13 of 201 S6E2C5 Series LBE192 (Top View) 1 A 2 3 UDP0 UDM0 4 5 6 7 8 9 10 11 12 13 14 USBV VSS PCD PCB VSS VCC PC8 VSS TCK VCC CC0 B VSS PA0 P60 P62 P64 PD1 PCA PC1 P95 P92 TDO TMS C VCC PA1 PA2 P61 P63 PD2 PCC PC5 PC0 P93 P90 D PA5 PA4 PA6 PA7 PA3 P6E PCE PC6 PC2 P94 P91 P22 P21 UDM1 E VSS P50 P51 P52 PA8 P65 PCF PC7 PC3 P26 P25 P24 P23 F PA9 PAA PAB PAC PAD PAE PD0 PC9 PC4 P2A P29 P28 P27 PB5 G VSS PAF P08 P09 P0A P30 VSS VSS P1F P1E PB7 PB6 PB4 P1B H VCC P32 P34 P31 VSS P35 VSS VSS P18 PB2 P1D P19 P1C P1A J P33 P39 P38 P37 P36 P71 VSS P74 PB1 PB0 P17 P16 P15 PB3 K P3A P3B P3C P3D PF0 PF1 VSS P73 P75 P79 P14 P12 P11 P13 L P3E P5D P5E P43 P7D P70 VSS P72 PF7 P78 P10 AVRH AVRL VSS M VSS P5F P42 P44 P7E P49 VSS PF3 PF6 P7A P7C AVSS AVCC VCC N VCC P40 P41 P45 INITX P48 VSS PF2 PF4 P77 P7B MD0 MD1 VSS P C VSS VCC X0A X1A VSS VBAT PF5 P76 VSS TRSTX VSS TDI P20 UDP1 X0 USBV CC1 X1 PFBGA-192 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04984 Rev.*B Page 14 of 201 S6E2C5 Series 4. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQQ216 LQP176 LQS144 LBE192 1 1 1 C1 2 2 2 B2 3 3 3 C2 4 4 4 C3 5 5 5 D5 6 6 6 D2 7 7 7 D1 Document Number: 002-04984 Rev.*B Pin Name VCC PA0 RTO20_0 (PPG20_0) TIOA8_0 AIN2_0 INT00_0 MADATA00_0 PA1 RTO21_0 (PPG20_0) TIOA9_0 BIN2_0 MADATA01_0 PA2 RTO22_0 (PPG22_0) TIOA10_0 ZIN2_0 MADATA02_0 PA3 RTO23_0 (PPG22_0) TIOA11_0 MADATA03_0 PA4 RTO24_0 (PPG24_0) TIOA12_0 MADATA04_0 PA5 SIN1_0 RTO25_0 (PPG24_0) TIOA13_0 INT01_0 MADATA05_0 I/O circuit type - Pin state type - G K G I G I G I G I G K Page 15 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 8 8 8 D3 9 9 9 D4 10 10 - E2 11 11 - E3 12 12 - E4 13 - - - 14 13 10 E5 15 14 11 F1 16 15 12 F2 17 16 13 F3 Document Number: 002-04984 Rev.*B Pin Name PA6 SOT1_0 (SDA1_0)) DTTI2X_0 MADATA06_0 PA7 SCK1_0 (SCL1_0) IC20_0 MADATA07_0 P50 SCS72_0 RTO00_1 (PPG00_1) TIOA8_2 MADATA16_0 P51 SCS73_0 RTO01_1 (PPG00_1) TIOB8_2 MADATA17_0 P52 RTO02_1 (PPG02_1) TIOA9_2 MADATA18_0 P53 RTO03_1 (PPG02_1) TIOB9_2 MADATA19_0 PA8 SIN7_0 IC21_0 INT02_0 WKUP1 MADATA08_0 PA9 SOT7_0 (SDA7_0) IC22_0 MADATA09_0 PAA SCK7_0 (SCL7_0) IC23_0 MADATA10_0 PAB SCS70_0 RX0_0 FRCK2_0 INT03_0 MADATA11_0 I/O circuit type Pin state type E I E I E I E I E I E I I Q N I N I E K Page 16 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 18 17 14 F4 19 - - - 20 - - - 21 - - - 22 - - - 23 18 15 F5 24 19 16 F6 25 20 17 G2 26 - - - Pin Name PAC SCS71_0 TX0_0 TIOB8_0 AIN3_0 MADATA12_0 P54 SIN15_1 RTO04_1 (PPG04_1) TIOA10_2 INT00_2 MADATA20_0 P55 SOT15_1 (SDA15_1) RTO05_1 (PPG04_1) TIOB10_2 MADATA21_0 P56 SCK15_1 (SCL15_1) DTTI0X_1 TIOB0_1 MADATA22_0 P57 IC00_1 TIOB1_1 MADATA23_0 PAD SCK3_0 (SCL3_0) TIOB9_0 BIN3_0 MADATA13_0 PAE ADTG_0 SOT3_0 (SDA3_0) TIOB10_0 ZIN3_0 MADATA14_0 PAF SIN3_0 TIOB11_0 INT16_0 MADATA15_0 P58 SIN11_1 IC01_1 TIOB2_1 I/O circuit type Pin state type E I E K E I E I E I N I N I I K E K INT02_2 MADATA24_0 Document Number: 002-04984 Rev.*B Page 17 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 27 - - - 28 - - - 29 - - - 30 21 18 G3 31 22 19 G4 32 23 20 G5 33 - - - 34 24 - G6 35 25 - H4 36 26 21 H2 Document Number: 002-04984 Rev.*B Pin Name P59 SOT11_1 (SDA11_1) IC02_1 TIOB3_1 MADATA25_0 P5A SCK11_1 (SCL11_1) IC03_1 TIOB4_1 MADATA26_0 P5B FRCK0_1 TIOB5_1 MADATA27_0 P08 SIN14_0 TIOB12_0 INT17_0 MDQM0_0 P09 SOT14_0 (SDA14_0) TIOB13_0 INT18_0 MDQM1_0 P0A ADTG_1 SCK14_0 (SCL14_0) AIN2_1 MCLKOUT_0 P5C TIOA11_2 MADATA28_0 RTCCO_1 SUBOUT_1 P30 RX0_1 TIOA13_2 INT03_2 MDQM2_0 I2SDI0_0 P31 TX0_1 TIOB13_2 MDQM3_0 I2SCK0_0 P32 BIN2_1 INT19_0 S_DATA1_0 I/O circuit type Pin state type E I E I E I E K E K L I E I E K E I L K Page 18 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 37 27 22 J1 38 28 23 H3 39 40 29 30 24 25 H1 H5 41 31 26 H6 42 32 27 J5 43 33 28 J4 44 34 29 J3 45 35 30 J2 46 36 31 K1 47 37 32 K2 Document Number: 002-04984 Rev.*B Pin Name P33 FRCK0_0 ZIN2_1 S_DATA0_0 P34 IC03_0 INT00_1 S_CLK_0 VCC VSS P35 IC02_0 INT01_1 S_CMD_0 P36 IC01_0 INT02_1 S_DATA3_0 P37 IC00_0 INT03_1 S_DATA2_0 P38 ADTG_2 DTTI0X_0 S_WP_0 P39 SIN2_1 RTO00_0 (PPG00_0) TIOA0_1 AIN3_1 INT16_1 S_CD_0 MAD24_0 P3A SOT2_1 (SDA2_1) RTO01_0 (PPG00_0) TIOA1_1 BIN3_1 INT17_1 MAD23_0 P3B SCK2_1 (SCL2_1) RTO02_0 (PPG02_0) TIOA2_1 ZIN3_1 INT18_1 MAD22_0 MNALE_0 I/O circuit type Pin state type L I L K - - L K L K L K E I G K G K G K Page 19 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 48 38 33 K3 49 39 34 K4 50 40 35 L1 51 41 - L2 52 42 - L3 53 43 - M2 54 55 44 45 36 37 M1 N1 56 46 38 N2 Document Number: 002-04984 Rev.*B Pin Name P3C SIN13_0 RTO03_0 (PPG02_0) TIOA3_1 INT19_1 MAD21_0 MNCLE_0 P3D SOT13_0 (SDA13_0) RTO04_0 (PPG04_0) TIOA4_1 MAD20_0 MNWEX_0 P3E SCK13_0 (SCL13_0) RTO05_0 (PPG04_0) TIOA5_1 MAD19_0 MNREX_0 P5D SIN10_1 TIOB11_2 INT01_2 MADATA29_0 I2SMCLK0_0 P5E SOT10_1 (SDA10_1) TIOA12_2 MADATA30_0 I2SDO0_0 P5F SCK10_1 (SCL10_1) TIOB12_2 MADATA31_0 I2SWS0_0 VSS VCC P40 SIN3_1 RTO10_0 (PPG10_0) TIOA0_0 AIN0_0 INT23_0 MCSX7_0 I/O circuit type Pin state type G K G I G I E K E I E I - - G K Page 20 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 57 47 39 N3 58 48 40 M3 59 49 41 L4 60 50 42 M4 61 51 43 N4 62 63 64 52 53 54 44 45 46 P2 P3 P4 65 - - - 66 - - - 67 - - - 68 - - - Document Number: 002-04984 Rev.*B Pin Name P41 SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) TIOA1_0 BIN0_0 MCSX6_0 P42 SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) TIOA2_0 ZIN0_0 MCSX5_0 P43 SIN15_0 RTO13_0 (PPG12_0) TIOA3_0 INT04_0 MCSX4_0 P44 SOT15_0 (SDA15_0) RTO14_0 (PPG14_0) TIOA4_0 MCSX3_0 P45 SCK15_0 (SCL15_0) RTO15_0 (PPG14_0) TIOA5_0 MCSX2_0 C VSS VCC P4A SIN12_1 AIN0_1 INT04_2 P4B SOT12_1 (SDA12_1) BIN0_1 P4C SCK12_1 (SCL12_1) ZIN0_1 P4D SCS72_1 RX2_2 INT05_2 I/O circuit type Pin state type G I G I G K G I G I - - E K E I E I E K Page 21 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 69 - - - 70 55 47 L5 71 56 48 M5 72 57 49 N5 73 58 50 P5 74 59 51 P6 75 60 52 P8 76 61 53 N6 77 62 54 M6 78 63 - K5 79 64 - K6 80 65 55 L6 81 66 56 J6 82 67 57 L8 83 68 58 K8 Document Number: 002-04984 Rev.*B Pin Name P4E SCS73_1 TX2_2 P7D SCK1_1 (SCL1_1) RX2_0 DTTI1X_0 INT05_0 WKUP2 MCSX1_0 P7E ADTG_7 TX2_0 FRCK1_0 MCSX0_0 INITX P46 X0A P47 X1A VBAT P48 VREGCTL P49 VWAKEUP PF0 SCS63_0 RX2_1 FRCK1_1 TIOA15_1 INT22_1 PF1 SCS62_0 TX2_1 TIOB15_1 INT23_1 P70 ADTG_8 SIN1_1 INT06_0 MRDY_0 P71 SOT1_1 (SDA1_1) MAD00_0 P72 SIN9_0 TIOB0_0 INT07_0 MAD01_0 P73 SOT9_0 (SDA9_0) TIOB1_0 MAD02_0 I/O circuit type Pin state type E I L Q L I B C P S Q T - - O U O U E K E K I K E I E K E I Page 22 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 84 69 59 J8 85 70 - N8 86 71 - M8 87 72 - N9 88 73 - P9 89 74 - M9 90 75 - L9 91 76 60 K9 92 77 61 P10 Document Number: 002-04984 Rev.*B Pin Name P74 SCK9_0 (SCL9_0) TIOB2_0 MAD03_0 PF2 RTO10_1 (PPG10_1) TIOA6_1 MRASX_0 PF3 RTO11_1 (PPG10_1) TIOB6_1 INT05_1 MCASX_0 PF4 RTO12_1 (PPG12_1) TIOA7_1 INT06_1 MSDWEX_0 PF5 RTO13_1 (PPG12_1) TIOB7_1 INT07_1 MCSX8_0 PF6 RTO14_1 (PPG14_1) TIOA14_1 INT20_1 MSDCKE_0 PF7 RTO15_1 (PPG14_1) TIOB14_1 INT21_1 MSDCLK_0 P75 SIN8_0 TIOB3_0 AIN1_0 INT20_0 MAD04_0 P76 SOT8_0 (SDA8_0) TIOB4_0 BIN1_0 MAD05_0 I/O circuit type Pin state type E I L I L K L K L K L K L K E K E I Page 23 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 93 78 62 N10 94 - - - 95 - - - 96 79 63 L10 97 80 64 K10 98 81 65 M10 99 82 66 N11 100 83 67 M11 101 - - - 102 - - - 103 - - - 104 84 68 N13 105 85 69 N12 Document Number: 002-04984 Rev.*B Pin Name P77 SCK8_0 (SCL8_0) TIOB5_0 ZIN1_0 MAD06_0 PF8 SCS70_1 DTTI1X_1 AIN1_1 PF9 SCS71_1 IC10_1 BIN1_1 P78 SIN6_0 IC10_0 INT21_0 MAD07_0 P79 SOT6_0 (SDA6_0) IC11_0 MAD08_0 P7A SCK6_0 (SCL6_0) IC12_0 MAD09_0 P7B DA1 SCS60_0 IC13_0 INT22_0 P7C DA0 SCS61_0 INT04_1 PFA SCK7_1 (SCL7_1) IC11_1 ZIN1_1 PFB SOT7_1 (SDA7_1) IC12_1 INT07_2 PFC SIN7_1 IC13_1 INT06_2 PE0 MD1 MD0 I/O circuit type Pin state type E I E I E I E K L I L I R J R J E I E K E K C E J D Page 24 of 201 S6E2C5 Series Pin No Pin Name I/O circuit type Pin state type A A A B LQQ216 LQP176 LQS144 LBE192 106 86 70 P12 107 87 71 P13 108 88 72 N14 VSS - - 109 89 73 M14 VCC - - 110 90 74 M13 AVCC - - 111 91 75 M12 AVSS - - 112 92 76 L13 AVRL - - 113 93 77 L12 AVRH - - F M F L F L F M F L E O E O E N 114 94 78 L11 115 95 79 K13 116 96 80 K12 117 97 81 K14 118 98 82 K11 119 - - - 120 - - - 121 - - - Document Number: 002-04984 Rev.*B PE2 X0 PE3 X1 P10 AN00 SIN10_0 TIOA0_2 AIN0_2 INT08_0 P11 AN01 SOT10_0 (SDA10_0) TIOB0_2 BIN0_2 P12 AN02 SCK10_0 (SCL10_0) TIOA1_2 ZIN0_2 P13 AN03 SIN6_1 RX1_1 INT25_1 P14 AN04 SOT6_1 (SDA6_1) TX1_1 PB8 ADTG_6 SCS63_1 INT08_2 TRACED8 PB9 SIN9_1 AIN2_2 INT09_2 TRACED9 PBA SOT9_1 (SDA9_1) BIN2_2 TRACED10 Page 25 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type E N F M F L F L F L F M F M F L F M F O PBB 122 - - - 123 99 83 J13 124 100 84 J12 125 101 85 J11 126 102 - J10 127 103 - J9 128 104 - H10 129 105 - J14 130 106 86 H9 131 107 87 H12 Document Number: 002-04984 Rev.*B SCK9_1 (SCL9_1) ZIN2_2 TRACED11 P15 AN05 SIN11_0 TIOB1_2 AIN1_2 INT09_0 P16 AN06 SOT11_0 (SDA11_0) TIOA2_2 BIN1_2 P17 AN07 SCK11_0 (SCL11_0) TIOB2_2 ZIN1_2 PB0 AN16 SCK6_1 (SCL6_1) TIOA9_1 PB1 AN17 SCS60_1 TIOB9_1 INT08_1 PB2 AN18 SCS61_1 TIOA10_1 INT09_1 PB3 AN19 SCS62_1 TIOB10_1 P18 AN08 SIN2_0 TIOA3_2 INT10_0 P19 AN09 SOT2_0 (SDA2_0) TIOB3_2 INT24_1 TRACECLK Page 26 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name P1A AN10 SCK2_0 (SCL2_0) TIOA4_2 TRACED0 P1B AN11 SIN12_0 TIOB4_2 INT11_0 TRACED1 P1C AN12 SOT12_0 (SDA12_0) TIOA5_2 TRACED2 P1D AN13 SCK12_0 (SCL12_0) TIOB5_2 TRACED3 I/O circuit type Pin state type F N F O F N F N 132 108 88 H14 133 109 89 G14 134 110 90 H13 135 111 91 H11 136 - - - VSS - - 137 - - - VCC - - F O F O F N F N F M 138 112 - G13 139 113 - F14 140 114 - G12 141 115 - G11 142 116 92 G10 Document Number: 002-04984 Rev.*B PB4 AN20 SIN8_1 TIOA11_1 INT10_1 TRACED4 PB5 AN21 SOT8_1 (SDA8_1) TIOB11_1 INT11_1 TRACED5 PB6 AN22 SCK8_1 (SCL8_1) TIOA12_1 TRACED6 PB7 AN23 TIOB12_1 TRACED7 P1E AN14 TIOA8_1 INT26_1 MAD10_0 Page 27 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 143 117 93 G9 144 118 94 F10 145 119 95 F11 146 120 96 F12 147 121 97 F13 148 - - - 149 - - - 150 - - - 151 - - - 152 122 98 E10 153 123 99 E11 Document Number: 002-04984 Rev.*B Pin Name P1F AN15 RTS5_0 TIOB8_1 INT27_1 MAD11_0 P2A AN24 CTS5_0 MAD12_0 P29 AN25 SCK5_0 (SCL5_0) MAD13_0 P28 AN26 SOT5_0 (SDA5_0) MAD14_0 P27 AN27 SIN5_0 INT24_0 MAD15_0 PBC TX1_2 TRACED12 PBD SCK0_1 (SCL0_1) RX1_2 AIN3_2 INT10_2 TRACED13 PBE SOT0_1 (SDA0_1) BIN3_2 TRACED14 PBF SIN0_1 ZIN3_2 INT11_2 TRACED15 P26 TX1_0 MAD16_0 P25 AN28 RX1_0 INT25_0 MAD17_0 I/O circuit type Pin state type F M F L F L F L F M E N E O E N E O E I F M Page 28 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 154 124 100 E12 155 125 101 E13 156 126 102 D12 157 127 103 D13 158 128 104 C13 159 129 105 E14 Pin Name P24 AN29 TIOA13_1 MAD18_0 P23 UHCONX1 AN30 SCK0_0 (SCL0_0) TIOB13_1 P22 AN31 SOT0_0 (SDA0_0) INT26_0 P21 ADTG_4 SIN0_0 INT27_0 CROUT_0 P20 NMIX WKUP0 USBVCC1 160 130 106 D14 161 131 107 C14 162 132 108 B14 P82 UDM1 P83 UDP1 VSS 163 133 109 A13 VCC 164 134 110 B13 165 135 111 A12 166 136 112 C12 167 137 113 B12 168 138 114 B11 169 139 - C11 170 140 - D11 171 141 - B10 Document Number: 002-04984 Rev.*B P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P90 INT12_1 Q_IO3_0 P91 SIN5_1 INT13_1 Q_IO2_0 P92 SOT5_1 (SDA5_1) INT14_1 Q_IO1_0 I/O circuit type Pin state type F L F L F M I K I F - - H R H R - - - - E G E G E G E G E G S K S K S K Page 29 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type S K S I S I S K S K K I K I 172 142 - C10 173 143 - D10 174 144 - B9 175 - - - 176 - - - 177 145 115 C9 178 146 116 B8 P93 SCK5_1 (SCL5_1) INT15_1 Q_IO0_0 P94 CTS5_1 Q_SCK_0 P95 RTS5_1 Q_CS0_0 P96 RX0_2 INT12_2 Q_CS1_0 P97 TX0_2 INT13_2 Q_CS2_0 PC0 PC1 TIOB6_0 179 147 117 D9 PC2 TIOA6_0 K I 180 148 118 E9 PC3 TIOB7_0 K I 181 149 119 F9 PC4 TIOA7_0 K I 182 150 120 C8 PC5 TIOB14_0 K I 183 151 121 D8 PC6 TIOA14_0 K I E K K I K I 184 152 122 E8 PC7 INT13_0 CROUT_1 185 153 123 A10 186 154 124 F8 PC8 PC9 TIOB15_0 187 155 125 B7 PCA TIOA15_0 K I 188 156 126 A9 VCC - - 189 157 127 A8 VSS - - L K K I L K 190 158 128 A7 191 159 129 C7 192 160 130 A6 Document Number: 002-04984 Rev.*B PCB INT28_0 PCC PCD SOT4_1 (SDA4_1) INT14_0 Page 30 of 201 S6E2C5 Series Pin No Pin Name I/O circuit type Pin state type PCE SIN4_1 INT15_0 L K L K L K L K L I E K E I E I E K E I E I E I E I LQQ216 LQP176 LQS144 LBE192 193 161 131 D7 194 162 132 E7 195 163 133 F7 PCF RTS4_1 INT12_0 PD0 INT30_1 196 164 134 B6 PD1 INT31_1 197 165 135 C6 198 166 136 D6 199 - - - 200 - - - 201 - - - 202 - - - 203 - - - 204 - - - 205 - - - Document Number: 002-04984 Rev.*B PD2 CTS4_1 FRCK2_1 P6E ADTG_5 SCK4_1 (SCL4_1) IC23_1 INT29_0 P6D SCK14_1 (SCL14_1) IC22_1 TIOB6_2 P6C SOT14_1 (SDA14_1) IC21_1 TIOA6_2 P6B SIN14_1 IC20_1 TIOB7_2 INT14_2 P6A DTTI2X_1 TIOA7_2 P69 RTO20_1 (PPG20_1) TIOB14_2 P68 SCK13_1 (SCL13_0) RTO21_1 (PPG20_1) TIOA14_2 P67 SOT13_1 (SDA13_1) RTO22_1 (PPG22_1) TIOB15_2 Page 31 of 201 S6E2C5 Series Pin No LQQ216 LQP176 LQS144 LBE192 206 - - - 207 167 - E6 208 168 - B5 209 169 137 C5 210 170 138 B4 211 171 139 C4 212 172 140 B3 213 173 141 A4 214 174 142 A3 215 175 143 A2 Document Number: 002-04984 Rev.*B Pin Name P66 SIN13_1 RTO23_1 (PPG22_1) TIOA15_2 INT15_2 P65 RTO24_1 (PPG24_1) INT28_1 P64 CTS4_0 RTO25_1 (PPG24_1) INT29_1 P63 ADTG_3 RTS4_0 INT30_0 MOEX_0 P62 SCK4_0 (SCL4_0) MWEX_0 P61 UHCONX0 SOT4_0 (SDA4_0) MALE_0 RTCCO_0 SUBOUT_0 P60 SIN4_0 INT31_0 WKUP3 USBVCC0 P80 UDM0 P81 UDP0 I/O circuit type Pin state type E K E K I K L K L I L I I Q - - H R H R Page 32 of 201 S6E2C5 Series Pin No Pin Name I/O circuit type Pin state type LQQ216 LQP176 LQS144 LBE192 216 176 144 B1 - - - - - E1 - - - - - G1 - - - - - P7 - - - - - P11 - - - - - L14 - - - - - A11 - - - - - A5 - - - - - N7 - - - - - M7 - - - - - L7 - - - - - K7 - - - - - J7 - - -- - - G7 - - - - - H7 - - - - - H8 - - - - - G8 - - Document Number: 002-04984 Rev.*B VSS Page 33 of 201 S6E2C5 Series Signal Descriptions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin name ADC ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 Function A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Document Number: 002-04984 Rev.*B LQQ 216 24 32 44 209 157 198 119 71 80 114 115 116 117 118 123 124 125 130 131 132 133 134 135 142 143 126 127 128 129 138 139 140 141 144 145 146 147 153 154 155 156 Pin No LQP LQS 176 144 19 16 23 20 34 29 169 137 127 103 166 136 56 48 65 55 94 78 95 79 96 80 97 81 98 82 99 83 100 84 101 85 106 86 107 87 108 88 109 89 110 90 111 91 116 92 117 93 102 103 104 105 112 113 114 115 118 94 119 95 120 96 121 97 123 99 124 100 125 101 126 102 LBE 192 F6 G5 J3 C5 D13 D6 M5 L6 L11 K13 K12 K14 K11 J13 J12 J11 H9 H12 H14 G14 H13 H11 G10 G9 J10 J9 H10 J14 G13 F14 G12 G11 F10 F11 F12 F13 E11 E12 E13 D12 Page 34 of 201 S6E2C5 Series Module Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Pin name TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 Base Timer 4 Base Timer ch.0 TIOB Pin Base Timer ch.1 TIOA Pin Base Timer ch.1 TIOB Pin Base Timer ch.2 TIOA Pin Base Timer ch.2 TIOB Pin Base Timer ch.3 TIOA Pin Base Timer ch.3 TIOB Pin Base Timer ch.4 TIOA Pin Pin No LQP LQS 176 144 46 38 35 30 94 78 67 57 95 79 47 39 36 31 96 80 68 58 99 83 48 40 37 32 100 84 69 59 101 85 49 41 38 33 106 86 76 60 107 87 50 42 LBE 192 N2 J2 L11 L8 K13 N3 K1 K12 K8 J13 M3 K2 J12 J8 J11 L4 K3 H9 K9 H12 M4 39 34 K4 TIOA4_2 132 108 88 H14 TIOB4_0 92 77 61 P10 28 - - - TIOB4_2 133 109 89 G14 TIOA5_0 61 51 43 N4 50 40 35 L1 TIOA5_2 134 110 90 H13 TIOB5_0 93 78 62 N10 29 - - - TIOB5_2 135 111 91 H11 TIOA6_0 179 147 117 D9 85 70 - N8 TIOA6_2 200 - - - TIOB6_0 178 146 116 B8 86 71 - M8 199 - - - TIOA5_1 TIOB5_1 TIOA6_1 Base Timer 6 Base Timer ch.0 TIOA Pin LQQ 216 56 45 114 82 21 115 57 46 116 83 22 123 58 47 124 84 26 125 59 48 130 91 27 131 60 49 TIOB4_1 Base Timer 5 Function TIOB6_1 TIOB6_2 Document Number: 002-04984 Rev.*B Base Timer ch.4 TIOB Pin Base Timer ch.5 TIOA Pin Base Timer ch.5 TIOB Pin Base Timer ch.6 TIOA Pin Base Timer ch.6 TIOB Pin Page 35 of 201 S6E2C5 Series Module LQQ 216 Pin No LQP LQS 176 144 181 149 119 LBE 192 F9 87 72 - N9 TIOA7_2 202 - - - TIOB7_0 180 148 118 E9 88 73 - P9 Pin name Function TIOA7_0 TIOA7_1 Base Timer 7 TIOB7_1 201 - - - TIOA8_0 2 2 2 B2 142 116 92 G10 TIOA8_2 10 10 - E2 TIOB8_0 18 17 14 F4 143 117 93 G9 TIOB8_2 11 11 - E3 TIOA9_0 3 3 3 C2 TIOB8_1 TIOA9_1 Base Timer 9 Base Timer ch.8 TIOB Pin Base Timer ch.9 TIOA Pin 126 102 - J10 12 12 - E4 TIOB9_0 23 18 15 F5 127 103 - J9 TIOB9_2 13 - - - TIOA10_0 4 4 4 C3 128 104 - H10 19 - - - 24 19 16 F6 TIOA10_1 Base Timer ch.9 TIOB Pin Base Timer ch.10 TIOA Pin TIOA10_2 TIOB10_0 TIOB10_1 Base Timer ch.10 TIOB Pin 129 105 - J14 TIOB10_2 20 - - - TIOA11_0 5 5 5 D5 138 112 - G13 TIOA11_2 33 - - - TIOB11_0 25 20 17 G2 139 113 - F14 51 41 - L2 TIOA11_1 Base Timer 11 Base Timer ch.8 TIOA Pin TIOA9_2 TIOB9_1 Base Timer 10 Base Timer ch.7 TIOB Pin TIOB7_2 TIOA8_1 Base Timer 8 Base Timer ch.7 TIOA Pin TIOB11_1 Base Timer ch.11 の TIOA Pin Base Timer ch.11 TIOB Pin TIOB11_2 TIOA12_0 6 6 6 D2 140 114 - G12 TIOA12_2 52 42 - L3 TIOB12_0 30 21 18 G3 141 115 - G11 53 43 - M2 TIOA12_1 Base Timer 12 TIOB12_1 TIOB12_2 Document Number: 002-04984 Rev.*B Base Timer ch.12 TIOA Pin Base Timer ch.12 TIOB Pin Page 36 of 201 S6E2C5 Series Module Pin name Function 7 7 7 154 124 100 E12 TIOA13_2 34 24 - G6 TIOB13_0 31 22 19 G4 155 125 101 E13 TIOA13_1 TIOB13_1 35 25 - H4 183 151 121 D8 89 74 - M9 TIOA14_2 204 - - - TIOB14_0 182 150 120 C8 90 75 - L9 TIOB14_2 203 - - - TIOA15_0 187 155 125 B7 TIOA15_1 Base Timer ch.14 TIOB Pin Base Timer ch.15 TIOA Pin 78 63 - K5 206 - - - TIOB15_0 186 154 124 F8 79 64 - K6 TIOB15_2 205 - - - TX0_0 18 17 14 F4 35 25 - H4 176 - - - 17 16 13 F3 TX0_1 Base Timer ch.15 TIOB Pin CAN interface ch.0 TX output pin TX0_2 RX0_0 RX0_1 CAN interface ch.0 RX output pin 34 24 - G6 RX0_2 175 - - - TX1_0 152 122 98 E10 118 98 82 K11 TX1_2 148 - - - RX1_0 153 123 99 E11 117 97 81 K14 149 - - - 71 56 48 M5 79 64 - K6 TX2_2 69 - - - RX2_0 70 55 47 L5 78 63 - K5 68 - - - TX1_1 CAN 1 Base Timer ch.14 TIOA Pin TIOA15_2 TIOB15_1 CAN 0 Base Timer ch.13 TIOB Pin TIOA14_0 TIOB14_1 Base Timer 15 Base Timer ch.13 TIOA Pin TIOB13_2 TIOA14_1 Base Timer 14 RX1_1 CAN interface ch.1 TX output pin CAN interface ch.1 RX output pin RX1_2 TX2_0 TX2_1 CAN 2 (CAN-FD) Pin No LQP LQS 176 144 LBE 192 D1 TIOA13_0 Base Timer 13 LQQ 216 RX2_1 RX2_2 Document Number: 002-04984 Rev.*B CAN-FD interface ch.2 TX output pin CAN-FD interface ch.2 RX input pin Page 37 of 201 S6E2C5 Series Module Pin name Function Pin No LQP LQS 176 144 LBE 192 165 135 111 A12 167 137 113 B12 168 138 114 B11 SWO Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin TCK JTAG test clock input pin 165 135 111 A12 TDI JTAG test data input pin 166 136 112 C12 TDO JTAG debug data output pin 168 138 114 B11 TMS JTAG test mode state input/output pin 167 137 113 B12 Trace CLK output pin of ETM/HTM 131 107 87 H12 132 108 88 H14 133 109 89 G14 134 110 90 H13 TRACED3 135 111 91 H11 TRACED4 138 112 - G13 TRACED5 139 113 - F14 TRACED6 140 114 - G12 TRACED7 141 115 - G11 TRACED8 119 - - - 120 - - - 121 - - - TRACED11 122 - - - TRACED12 148 - - - TRACED13 149 - - - TRACED14 150 - - - TRACED15 151 - - - 164 134 110 B13 SWCLK SWDIO TRACECLK TRACED0 TRACED1 TRACED2 Debugger LQQ 216 TRACED9 TRACED10 TRSTX Document Number: 002-04984 Rev.*B Trace data output pin of ETM/ Trace data output pin of HTM Trace data output pin of HTM JTAG test reset Input pin Page 38 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 LBE 192 J6 MAD00_0 81 66 56 MAD01_0 82 67 57 L8 MAD02_0 83 68 58 K8 MAD03_0 84 69 59 J8 MAD04_0 91 76 60 K9 MAD05_0 92 77 61 P10 MAD06_0 93 78 62 N10 MAD07_0 96 79 63 L10 MAD08_0 97 80 64 K10 MAD09_0 98 81 65 M10 MAD10_0 142 116 92 G10 MAD11_0 143 117 93 G9 144 118 94 F10 MAD13_0 145 119 95 F11 MAD14_0 146 120 96 F12 MAD15_0 147 121 97 F13 MAD16_0 152 122 98 E10 MAD17_0 153 123 99 E11 MAD12_0 External Bus Function External bus interface address bus MAD18_0 154 124 100 E12 MAD19_0 50 40 35 L1 MAD20_0 49 39 34 K4 MAD21_0 48 38 33 K3 MAD22_0 47 37 32 K2 MAD23_0 46 36 31 K1 MAD24_0 45 35 30 J2 MCSX0_0 71 56 48 M5 MCSX1_0 70 55 47 L5 MCSX2_0 61 51 43 N4 60 50 42 M4 59 49 41 L4 MCSX5_0 58 48 40 M3 MCSX6_0 57 47 39 N3 MCSX7_0 56 46 38 N2 MCSX8_0 88 73 - P9 MCSX3_0 MCSX4_0 Document Number: 002-04984 Rev.*B External bus interface chip select output pin Page 39 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 MADATA00_0 2 2 2 LBE 192 B2 MADATA01_0 3 3 3 C2 MADATA02_0 4 4 4 C3 MADATA03_0 5 5 5 D5 MADATA04_0 6 6 6 D2 MADATA05_0 7 7 7 D1 MADATA06_0 8 8 8 D3 MADATA07_0 9 9 9 D4 MADATA08_0 14 13 10 E5 MADATA09_0 15 14 11 F1 MADATA10_0 16 15 12 F2 MADATA11_0 17 16 13 F3 MADATA12_0 18 17 14 F4 MADATA13_0 23 18 15 F5 MADATA14_0 24 19 16 F6 25 20 17 G2 10 - - - MADATA17_0 11 - - - MADATA18_0 12 - - - MADATA19_0 13 - - - MADATA20_0 19 - - - MADATA21_0 20 - - - MADATA22_0 21 - - - MADATA23_0 22 - - - MADATA24_0 26 - - - MADATA25_0 27 - - - MADATA26_0 28 - - - MADATA27_0 29 - - - MADATA28_0 33 - - - MADATA29_0 51 - - - MADATA30_0 52 - - - MADATA31_0 53 - - - MDQM0_0 30 21 18 G3 31 22 19 G4 34 - - - 35 - - - 211 171 139 C4 80 65 55 L6 32 23 20 G5 MADATA15_0 MADATA16_0 External Bus Function MDQM1_0 MDQM2_0 External bus interface data bus (Address / data multiplex bus) External bus interface byte mask signal output pin MDQM3_0 MALE_0 MRDY_0 MCLKOUT_0 Document Number: 002-04984 Rev.*B External bus interface Address Latch enable output signal for multiplex External bus interface external RDY input signal External bus clock signal Page 40 of 201 S6E2C5 Series Module Pin name MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 External Bus MWEX_0 MSDCLK_0 MSDCKE_0 MRASX_0 MCASX_0 MSDWEX_0 Function External bus interface ALE signal to control NAND Flash output pin External bus interface CLE signal to control NAND Flash output pin External bus interface read enable signal to control NAND Flash External bus interface write enable signal to control NAND Flash External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM SDRAM interface SDRAM clock output pin SDRAM interface SDRAM clock enable output pin SDRAM interface SDRAM row active output pin SDRAM interface SDRAM column active output pin SDRAM interface SDRAM write enable output pin INT00_0 Pin No LQP LQS 176 144 LBE 192 47 37 32 K2 48 38 33 K3 50 40 35 L1 49 39 34 K4 209 169 137 C5 210 170 138 B4 90 75 - L9 89 74 - M9 85 70 - N8 86 71 - M8 87 72 - N9 2 2 2 B2 38 28 23 H3 INT00_2 19 - - - INT01_0 7 7 7 D1 41 31 26 H6 INT01_2 51 41 - L2 INT02_0 14 13 10 E5 42 32 27 J5 26 - - - 17 16 13 F3 43 33 28 J4 INT03_2 34 24 - G6 INT04_0 59 49 41 L4 100 83 67 M11 INT04_2 65 - - - INT05_0 70 55 47 L5 86 71 - M8 68 - - - INT00_1 INT01_1 INT02_1 External Interrupt LQQ 216 External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin INT02_2 INT03_0 INT03_1 INT04_1 INT05_1 INT05_2 Document Number: 002-04984 Rev.*B External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin Page 41 of 201 S6E2C5 Series Module Pin name Function Pin No LQP LQS 176 144 80 65 55 LBE 192 L6 87 72 - N9 INT06_2 103 - - - INT07_0 82 67 57 L8 88 73 - P9 INT06_0 INT06_1 INT07_1 External interrupt request 06 input pin External interrupt request 07 input pin INT07_2 102 - - - INT08_0 114 94 78 L11 127 103 - J9 INT08_2 119 - - - INT09_0 123 99 83 J13 128 104 - H10 INT09_2 120 - - - INT10_0 130 106 86 H9 INT08_1 INT09_1 INT10_1 External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin 138 112 - G13 INT10_2 149 - - - INT11_0 133 109 89 G14 139 113 - F14 INT11_2 151 - - - INT12_0 194 162 132 E7 169 139 - C11 175 - - - 184 152 122 E8 INT11_1 External Interrupt LQQ 216 INT12_1 External interrupt request 11 input pin External interrupt request 12 input pin INT12_2 INT13_0 INT13_1 External interrupt request 13 input pin 170 140 - D11 INT13_2 176 - - - INT14_0 192 160 130 A6 171 141 - B10 INT14_2 201 - - - INT15_0 193 161 131 D7 172 142 - C10 206 - - - 25 20 17 G2 45 35 30 J2 30 21 18 G3 46 36 31 K1 31 22 19 G4 47 37 32 K2 36 48 91 26 38 76 21 33 60 H2 K3 K9 INT14_1 INT15_1 External interrupt request 14 input pin External interrupt request 15 input pin INT15_2 INT16_0 INT16_1 INT17_0 INT17_1 INT18_0 INT18_1 INT19_0 INT19_1 INT20_0 Document Number: 002-04984 Rev.*B External interrupt request 16 input pin External interrupt request 17 input pin External interrupt request 18 input pin External interrupt request 19 input pin External interrupt request 20 input pin Page 42 of 201 S6E2C5 Series Module Pin name Function INT20_1 INT21_0 INT21_1 INT22_0 INT22_1 INT23_0 INT23_1 INT24_0 INT24_1 INT25_0 INT25_1 INT26_0 External Interrupt INT26_1 INT27_0 INT27_1 INT28_0 INT28_1 INT29_0 INT29_1 INT30_0 INT30_1 INT31_0 INT31_1 NMIX Document Number: 002-04984 Rev.*B External interrupt request 21 input pin External interrupt request 22 input pin External interrupt request 23 input pin External interrupt request 24 input pin External interrupt request 25 input pin External interrupt request 26 input pin External interrupt request 27 input pin External interrupt request 28 input pin External interrupt request 29 input pin External interrupt request 30 input pin External interrupt request 31 input pin Non-Maskable Interrupt input pin LQQ 216 Pin No LQP LQS 176 144 89 74 - LBE 192 M9 96 79 63 L10 90 75 - L9 99 82 66 N11 78 63 - K5 56 46 38 N2 79 64 - K6 147 121 97 F13 131 107 87 H12 153 123 99 E11 117 97 81 K14 156 126 102 D12 142 116 92 G10 157 127 103 D13 143 117 93 G9 190 158 128 A7 207 167 - E6 198 166 136 D6 208 168 - B5 209 169 137 C5 195 163 133 F7 212 172 140 B3 196 164 134 B6 158 128 104 C13 Page 43 of 201 S6E2C5 Series Module LQQ 216 Pin No LQP LQS 176 144 P00 164 134 110 LBE 192 B13 P01 165 135 111 A12 P02 166 136 112 C12 167 137 113 B12 168 138 114 B11 P08 30 21 18 G3 P09 31 22 19 G4 P0A 32 23 20 G5 P10 114 94 78 L11 P11 115 95 79 K13 P12 116 96 80 K12 P13 117 97 81 K14 P14 118 98 82 K11 P15 123 99 83 J13 P16 124 100 84 J12 125 101 85 J11 130 106 86 H9 P19 131 107 87 H12 P1A 132 108 88 H14 P1B 133 109 89 G14 P1C 134 110 90 H13 P1D 135 111 91 H11 P1E 142 116 92 G10 P1F 143 117 93 G9 P20 158 128 104 C13 P21 157 127 103 D13 P22 156 126 102 D12 P23 155 125 101 E13 P24 154 124 100 E12 153 123 99 E11 P26 152 122 98 E10 P27 147 121 97 F13 P28 146 120 96 F12 P29 145 119 95 F11 P2A 144 118 94 F10 Pin name P03 P04 P17 P18 GPIO P25 Document Number: 002-04984 Rev.*B Function General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Page 44 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 P30 34 24 - LBE 192 G6 P31 35 25 - H4 P32 36 26 21 H2 P33 37 27 22 J1 P34 38 28 23 H3 P35 41 31 26 H6 P36 42 32 27 J5 43 33 28 J4 P38 44 34 29 J3 P39 45 35 30 J2 P3A 46 36 31 K1 P3B 47 37 32 K2 P3C 48 38 33 K3 P3D 49 39 34 K4 P3E 50 40 35 L1 P40 56 46 38 N2 P41 57 47 39 N3 P42 58 48 40 M3 P43 59 49 41 L4 P44 60 50 42 M4 P45 61 51 43 N4 73 58 50 P5 P37 GPIO Function General-purpose I/O port 3 P46 P47 General-purpose I/O port 4 74 59 51 P6 P48 76 61 53 N6 P49 77 62 54 M6 P4A 65 - - - P4B 66 - - - P4C 67 - - - P4D 68 - - - P4E 69 - - - Document Number: 002-04984 Rev.*B Page 45 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 P50 10 10 - LBE 192 E2 P51 11 11 - E3 P52 12 12 - E4 P53 13 - - - P54 19 - - - P55 20 - - - P56 21 - - - 22 - - - 26 - - - P59 27 - - - P5A 28 - - - P5B 29 - - - P5C 33 - - - P5D 51 41 - L2 P5E 52 42 - L3 P5F 53 43 - M2 P60 212 172 140 B3 P61 211 171 139 C4 P62 210 170 138 B4 P63 209 169 137 C5 P64 208 168 - B5 P65 207 167 - E6 206 - - - 205 - - - P68 204 - - - P69 203 - - - P6A 202 - - - P6B 201 - - - P6C 200 - - - P6D 199 - - - P6E 198 166 136 D6 P57 P58 GPIO Function General-purpose I/O port 5 P66 P67 Document Number: 002-04984 Rev.*B General-purpose I/O port 6 Page 46 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 P70 80 65 55 LBE 192 L6 P71 81 66 56 J6 P72 82 67 57 L8 P73 83 68 58 K8 P74 84 69 59 J8 P75 91 76 60 K9 P76 92 77 61 P10 93 78 62 N10 P78 96 79 63 L10 P79 97 80 64 K10 P7A 98 81 65 M10 P7B 99 82 66 N11 P7C 100 83 67 M11 P7D 70 55 47 L5 P7E 71 56 48 M5 P80 214 174 142 A3 215 175 143 A2 160 130 106 D14 P83 161 131 107 C14 P90 169 139 - C11 P91 170 140 - D11 P92 171 141 - B10 172 142 - C10 173 143 - D10 P95 174 144 - B9 P96 175 - - - P97 176 - - - P77 GPIO Function P81 P82 P93 P94 Document Number: 002-04984 Rev.*B General-purpose I/O port General-purpose I/O port 8 General-purpose I/O port 9 7 Page 47 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 PA0 2 2 2 LBE 192 B2 PA1 3 3 3 C2 PA2 4 4 4 C3 PA3 5 5 5 D5 PA4 6 6 6 D2 PA5 7 7 7 D1 PA6 8 8 8 D3 9 9 9 D4 14 13 10 E5 PA9 15 14 11 F1 PAA 16 15 12 F2 PAB 17 16 13 F3 PAC 18 17 14 F4 PAD 23 18 15 F5 PAE 24 19 16 F6 PAF 25 20 17 G2 PB0 126 102 - J10 PB1 127 103 - J9 PB2 128 104 - H10 PB3 129 105 - J14 PB4 138 112 - G13 PB5 139 113 - F14 PB6 140 114 - G12 PB7 141 115 - G11 119 - - - PB9 120 - - - PBA 121 - - - PBB 122 - - - PBC 148 - - - PBD 149 - - - PBE 150 - - - PBF 151 - - - PA7 PA8 GPIO Function PB8 Document Number: 002-04984 Rev.*B General-purpose I/O port A General-purpose I/O port B Page 48 of 201 S6E2C5 Series Module LQQ 216 Pin No LQP LQS 176 144 PC0 177 145 115 LBE 192 C9 PC1 178 146 116 B8 PC2 179 147 117 D9 PC3 180 148 118 E9 PC4 181 149 119 F9 PC5 182 150 120 C8 PC6 183 151 121 D8 184 152 122 E8 185 153 123 A10 PC9 186 154 124 F8 PCA 187 155 125 B7 PCB 190 158 128 A7 PCC 191 159 129 C7 PCD 192 160 130 A6 PCE 193 161 131 D7 PCF 194 162 132 E7 PD0 195 163 133 F7 196 164 134 B6 PD2 197 165 135 C6 PE0 104 84 68 N13 106 86 70 P12 PE3 107 87 71 P13 PF0 78 63 - K5 PF1 79 64 - K6 PF2 85 70 - N8 PF3 86 71 - M8 PF4 87 72 - N9 PF5 88 73 - P9 89 74 - M9 PF7 90 75 - L9 PF8 94 - - - PF9 95 - - - PFA 101 - - - PFB 102 - - - PFC 103 - - - Pin name PC7 PC8 GPIO PD1 PE2 PF6 Document Number: 002-04984 Rev.*B Function General-purpose I/O port C General-purpose I/O port D General-purpose I/O port E General-purpose I/O port F Page 49 of 201 S6E2C5 Series Module Pin name Function LQQ 216 Pin No LQP LQS 176 144 SIN0_0 Multi-function serial interface ch.0 input pin 157 127 103 LBE 192 D13 151 - - - 156 126 102 D12 150 - - - 155 125 101 E13 149 - - - SIN0_1 SOT0_0 (SDA0_0) Multifunction serial 0 SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) Multi-function serial interface ch.0 output pin This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4) Multi-function serial interface ch.1 input pin 7 7 7 D1 80 65 55 L6 Multi-function serial interface ch.1 output pin 8 8 8 D3 81 66 56 J6 9 9 9 D4 70 55 47 L5 130 106 86 H9 45 35 30 J2 131 107 87 H12 46 36 31 K1 132 108 88 H14 47 37 32 K2 This pin operates as SOT1 when it is used in Multifunction serial 1 SOT1_1 (SDA1_1) and as SDA1 when it is used in an I2C (operation mode 4). SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SIN2_0 SIN2_1 SOT2_0 (SDA2_0) Multifunction serial 2 a UART/CSIO/LIN(operation modes 0 to 3) SOT2_1 (SDA2_1) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) Document Number: 002-04984 Rev.*B Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O Pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). Page 50 of 201 S6E2C5 Series Module Function LQQ 216 SIN3_0 Multi-function serial interface ch.3 input pin 25 20 17 LBE 192 G2 56 46 38 N2 24 19 16 F6 57 47 39 N3 23 18 15 F5 58 48 40 M3 212 172 140 B3 193 161 131 D7 211 171 139 C4 192 160 130 A6 210 170 138 B4 198 166 136 D6 Multi-function serial interface ch.4 CTS input pin 208 168 - B5 197 165 135 C6 Multi-function serial interface ch.4 RTS output pin 209 169 137 C5 194 162 132 E7 SIN3_1 SOT3_0 (SDA3_0) Multifunction serial 3 SOT3_1 (SDA3_1) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SIN4_0 SIN4_1 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) Multifunction serial 4 Pin No LQP LQS 176 144 Pin name SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) CTS4_0 CTS4_1 RTS4_0 RTS4_1 Document Number: 002-04984 Rev.*B Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Page 51 of 201 S6E2C5 Series Module Pin name Function LQQ 216 Pin No LQP LQS 176 144 SIN5_0 Multi-function serial interface ch.5 input pin 147 121 97 LBE 192 F13 170 140 - D11 146 120 96 F12 171 141 - B10 145 119 95 F11 172 142 - C10 Multi-function serial interface ch.5 CTS input pin 144 118 94 F10 173 143 - D10 Multi-function serial interface ch.5 RTS output pin 143 117 93 G9 174 144 - B9 Multi-function serial interface ch.6 input pin 96 79 63 L10 117 97 81 K14 97 80 64 K10 118 98 82 K11 98 81 65 M10 126 102 - J10 99 127 82 103 66 - N11 J9 Multi-function serial interface ch.6 chip select1 input/output pin 100 83 67 M11 128 104 - H10 64 - K6 SCS62_1 Multi-function serial interface ch.6 chip select2 input/output pin 79 129 105 - J14 SCS63_0 SCS63_1 Multi-function serial interface ch.6 chip select3 input/output pin 78 119 63 - - K5 - SIN5_1 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) Multifunction serial 5 SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) CTS5_0 CTS5_1 RTS5_0 RTS5_1 SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) Multifunction serial 6 SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) SCS60_0 SCS60_1 SCS61_0 SCS61_1 SCS62_0 Document Number: 002-04984 Rev.*B Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 chip select 0 input/output pin Page 52 of 201 S6E2C5 Series Module Function LQQ 216 SIN7_0 SIN7_1 SOT7_0 (SDA7_0) Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 chip select 0 input/output pin 14 103 13 - 10 - LBE 192 E5 - 15 14 11 F1 102 - - - 16 15 12 F2 101 - - - 17 94 18 95 10 68 11 69 91 138 16 17 10 11 76 112 13 14 60 - F3 F4 E2 E3 K9 G13 92 77 61 P10 139 113 - F14 93 78 62 N10 140 114 - G12 82 120 67 - 57 - L8 - 83 68 58 K8 121 - - - 84 69 59 J8 122 - - - SOT7_1 (SDA7_1) Multifunction serial 7 SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) SCS70_0 SCS70_1 SCS71_0 SCS71_1 SCS72_0 SCS72_1 SCS73_0 SCS73_1 SIN8_0 SIN8_1 SOT8_0 (SDA8_0) Multifunction serial 8 SOT8_1 (SDA8_1) SCK8_0 (SCL8_0) SCK8_1 (SCL8_1) SIN9_0 SIN9_1 SOT9_0 (SDA9_0) Multifunction serial 9 Pin No LQP LQS 176 144 Pin name SOT9_1 (SDA9_1) SCK9_0 (SCL9_0) SCK9_1 (SCL9_1) Document Number: 002-04984 Rev.*B Multi-function serial interface ch.7 chip select1 input/output pin Multi-function serial interface ch.7 chip select 2 input/output pin Multi-function serial interface ch.7 chip select 3 input/output pin Multi-function serial interface ch.8 input pin Multi-function serial interface ch.8 output pin. This pin operates as SOT8 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA8 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.8 clock I/O pin. This pin operates as SCK8 when it is used in a CSIO (operation modes 2) and as SCL8 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.9 input pin Multi-function serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA9 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a CSIO (operation modes 2) and as SCL9 when it is used in an I2C (operation mode 4). Page 53 of 201 S6E2C5 Series Module Multifunction serial 10 Function LQQ 216 SIN10_0 SIN10_1 SOT10_0 (SDA10_0) Multi-function serial interface ch.10 input pin Multi-function serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA10 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a CSIO (operation modes 2) and as SCL10 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.11 input pin Multi-function serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA11 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a CSIO (operation modes 2) and as SCL11 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.12 input pin Multi-function serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA12 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a CSIO (operation modes 2) and as SCL12 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.13 input pin Multi-function serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA13 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a CSIO (operation modes 2) and as SCL13 when it is used in an I2C (operation mode 4). 114 51 94 41 78 - LBE 192 L11 L2 115 95 79 K13 52 42 - L3 116 96 80 K12 53 43 - M2 123 26 99 - 83 - J13 - 124 100 84 J12 27 - - - 125 101 85 J11 28 - - - 133 65 109 - 89 - G14 - 134 110 90 H13 66 - - - 135 111 91 H11 67 - - - 48 206 38 - 33 - K3 - 49 39 34 K4 205 - - - 50 40 35 L1 204 - - - SOT10_1 (SDA10_1) SCK10_0 (SCL10_0) SCK10_1 (SCL10_1) SIN11_0 SIN11_1 SOT11_0 (SDA11_0) Multifunction serial 11 SOT11_1 (SDA11_1) SCK11_0 (SCL11_0) SCK11_1 (SCL11_1) SIN12_0 SIN12_1 SOT12_0 (SDA12_0) Multifunction serial 12 SOT12_1 (SDA12_1) SCK12_0 (SCL12_0) SCK12_1 (SCL12_1) SIN13_0 SIN13_1 SOT13_0 (SDA13_0) Multifunction serial 13 Pin No LQP LQS 176 144 Pin name SOT13_1 (SDA13_1) SCK13_0 (SCL13_0) SCK13_1 (SCL13_1) Document Number: 002-04984 Rev.*B Page 54 of 201 S6E2C5 Series Module Multifunction serial 14 Function LQQ 216 SIN14_0 SIN14_1 SOT14_0 (SDA14_0) Multi-function serial interface ch.14 input pin Multi-function serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA14 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a CSIO (operation modes 2) and as SCL14 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.15 input pin Multi-function serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA15 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a CSIO (operation modes 2) and as SCL15 when it is used in an I2C (operation mode 4). 30 201 21 - 18 - LBE 192 G3 - 31 22 19 G4 200 - - - 32 23 20 G5 199 - - - 59 19 49 - 41 - L4 - 60 50 42 M4 20 - - - 61 51 43 N4 21 - - - SOT14_1 (SDA14_1) SCK14_0 (SCL14_0) SCK14_1 (SCL14_1) SIN15_0 SIN15_1 SOT15_0 (SDA15_0) Multifunction serial 15 Pin No LQP LQS 176 144 Pin name SOT15_1 (SDA15_1) SCK15_0 (SCL15_0) SCK15_1 (SCL15_1) Document Number: 002-04984 Rev.*B Page 55 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 44 34 29 LBE 192 J3 21 - - - 16-bit free-run timer ch.0 external clock input pin 37 27 22 J1 29 - - - IC00_0 43 33 28 J4 IC00_1 22 - - - IC01_0 42 32 27 J5 26 - - - 41 31 26 H6 IC02_1 27 - - - IC03_0 38 28 23 H3 IC03_1 28 - - - Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 45 35 30 J2 10 10 - E2 Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 46 36 31 K1 11 11 - E3 Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 47 37 32 K2 12 12 - E4 Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 48 38 33 K3 13 - - - Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 49 39 34 K4 19 - - - Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 50 40 35 L1 20 - - - DTTI0X_0 DTTI0X_1 FRCK0_0 FRCK0_1 IC01_1 IC02_0 RTO00_0 (PPG00_0) Multifunction Timer Timer 0 Function RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Document Number: 002-04984 Rev.*B 16-bit input capture input pin of Multi-function timer 0. ICxx describes channel number. Page 56 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 70 55 47 LBE 192 L5 94 - - - 16-bit free-run timer ch.1 external clock input pin 71 56 48 M5 78 63 - K5 IC10_0 96 79 63 L10 IC10_1 95 - - - IC11_0 97 80 64 K10 101 - - - 98 81 65 M10 IC12_1 102 - - - IC13_0 99 82 66 N11 IC13_1 103 - - - Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 56 46 38 N2 85 70 - N8 Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 57 47 39 N3 86 71 - M8 Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 58 48 40 M3 87 72 - N9 Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 59 49 41 L4 88 73 - P9 Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 60 50 42 M4 89 74 - M9 Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 61 51 43 N4 90 75 - L9 DTTI1X_0 DTTI1X_1 FRCK1_0 FRCK1_1 IC11_1 IC12_0 RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) Multifunction Timer 1 Function RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) Document Number: 002-04984 Rev.*B 16-bit input capture input pin of Multi-function timer 1. ICxx describes channel number. Page 57 of 201 S6E2C5 Series Module Pin name LQQ 216 Pin No LQP LQS 176 144 8 8 8 LBE 192 D3 202 - - - 17 16 13 F3 197 165 135 C6 IC20_0 9 9 9 D4 IC20_1 201 - - - IC21_0 14 13 10 E5 200 - - - 15 14 11 F1 IC22_1 199 - - - IC23_0 16 15 12 F2 IC23_1 198 166 136 D6 2 2 2 B2 203 - - - 3 3 3 C2 204 - - - 4 4 4 C3 205 - - - 5 5 5 D5 206 - - - 6 6 6 D2 207 167 - E6 7 7 7 D1 208 168 - B5 DTTI2X_0 DTTI2X_1 FRCK2_0 FRCK2_1 IC21_1 IC22_0 RTO20_0 (PPG20_0) RTO20_1 (PPG20_1) Multifunction Timer 2 Function RTO21_0 (PPG20_0) RTO21_1 (PPG20_1) RTO22_0 (PPG22_0) RTO22_1 (PPG22_1) RTO23_0 (PPG22_0) RTO23_1 (PPG22_1) RTO24_0 (PPG24_0) RTO24_1 (PPG24_1) RTO25_0 (PPG24_0) RTO25_1 (PPG24_1) Document Number: 002-04984 Rev.*B Input signal controlling wave form generator outputs RTO20 to RTO25 of Multi-function timer 2. 16-bit free-run timer ch.2 external clock input pin 16-bit input capture input pin of Multi-function timer 2. ICxx describes channel number. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Page 58 of 201 S6E2C5 Series Module Pin name Function 56 46 38 65 - - - AIN0_2 114 94 78 L11 BIN0_0 57 47 39 N3 66 - - - BIN0_2 115 95 79 K13 ZIN0_0 58 48 40 M3 67 - - - ZIN0_2 116 96 80 K12 AIN1_0 91 76 60 K9 94 - - - AIN1_2 123 99 83 J13 BIN1_0 92 77 61 P10 AIN0_1 BIN0_1 ZIN0_1 AIN1_1 Quadrature Position/ Revolution Counter 1 BIN1_1 QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin 95 - - - BIN1_2 124 100 84 J12 ZIN1_0 93 78 62 N10 101 - - - ZIN1_2 125 101 85 J11 AIN2_0 2 2 2 B2 32 23 20 G5 120 - - - 3 3 3 C2 ZIN1_1 AIN2_1 QPRC ch.1 ZIN input pin QPRC ch.2 AIN input pin AIN2_2 Quadrature Position/ Revolution Counter 2 Pin No LQP LQS 176 144 LBE 192 N2 AIN0_0 Quadrature Position/ Revolution Counter 0 LQQ 216 BIN2_0 BIN2_1 QPRC ch.2 BIN input pin 36 26 21 H2 BIN2_2 121 - - - ZIN2_0 4 4 4 C3 37 27 22 J1 122 - - - ZIN2_1 ZIN2_2 Document Number: 002-04984 Rev.*B QPRC ch.2 ZIN input pin Page 59 of 201 S6E2C5 Series Module Pin name Function 18 17 14 45 35 30 J2 AIN3_2 149 - - - BIN3_0 23 18 15 F5 46 36 31 K1 AIN3_1 BIN3_1 QPRC ch.3 AIN input pin QPRC ch.3 BIN input pin BIN3_2 150 - - - ZIN3_0 24 19 16 F6 47 37 32 K2 151 - - - 211 171 139 C4 33 - - - 211 171 139 C4 33 - - - ZIN3_1 QPRC ch.3 ZIN input pin ZIN3_2 RTCCO_0 Real-time clock RTCCO_1 SUBOUT_0 SUBOUT_1 USB0 USB ch.0 device/host D – pin 214 174 142 A3 USB ch.0 device/host D + pin 215 175 143 A2 USB ch.0 external pull-up control pin 211 171 139 C4 UDM1 USB ch.1 device/host D – pin 160 130 106 D14 UDP1 USB ch.1 device/host D + pin 161 131 107 C14 155 125 101 E13 158 128 104 C13 14 13 10 E5 70 55 47 L5 212 172 140 B3 DA0 USB ch.1 external pull-up control pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 D/A converter ch.0 analog output pin 100 83 67 M11 DA1 D/A converter ch.1 analog output pin 99 82 66 N11 On-board regulator control pin The return signal input pin from a hibernation state 76 61 53 N6 77 62 54 M6 WKUP0 WKUP1 WKUP2 WKUP3 DAC VREGCTL VBAT Sub clock output pin UDP0 UHCONX1 Low-Power Consumption Mode 0.5 seconds pulse output pin of Real-time clock UDM0 UHCONX0 USB1 Pin No LQP LQS 176 144 LBE 192 F4 AIN3_0 Quadrature Position/ Revolution Counter 3 LQQ 216 VWAKEUP Document Number: 002-04984 Rev.*B Page 60 of 201 S6E2C5 Series Module Pin name S_CLK_0 S_CMD_0 Function SD memory card interface SD memory card clock output pin SD memory card interface SD memory card command output S_DATA1_0 SD I/F S_DATA0_0 S_DATA3_0 SD memory card interface SD memory card data bus S_DATA2_0 S_CD_0 S_WP_0 I2SMCLK0_0 I2 S SD memory card interface SD memory card detection pin SD memory card interface SD memory card write protection I2S external clock pin LBE 192 38 28 23 H3 41 31 26 H6 36 26 21 H2 37 27 22 J1 42 32 27 J5 43 33 28 J4 45 35 30 J2 44 34 29 J3 51 41 - L2 I2SDO0_0 serial transition data output pin 52 42 - L3 I2SWS0_0 I2S frame synchronization signal pin 53 43 - M2 I2SDI0_0 I2 S serial received data input pin 34 24 - G6 I2SCK0_0 I2 S bit clock pin 35 25 - H4 Q_SCK_0 SPI clock output pin 173 143 - D10 172 142 - C10 171 141 - B10 Q_IO1_0 Q_IO2_0 SPI data input/output pin 170 140 - D11 Q_IO3_0 169 139 - C11 Q_CS0_0 174 144 - B9 175 - - - 176 - - - 72 57 49 N5 Q_CS1_0 SPI chip select output pin Q_CS2_0 Reset Pin No LQP LQS 176 144 I2 S Q_IO0_0 High-Speed Quad SPI LQQ 216 INITX Document Number: 002-04984 Rev.*B External Reset Input pin. A reset is valid when INITX=L. Page 61 of 201 S6E2C5 Series Module Pin name MD1 Mode MD0 VCC Function Mode 1 pin. During serial programming to Flash memory, MD1=L must be input. Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash memory, MD0=H must be input. Power supply Pin Power USBVCC0 USBVCC1 GND VSS Document Number: 002-04984 Rev.*B 3.3V Power supply port for USB I/O GND Pin LQQ 216 Pin No LQP LQS 176 144 LBE 192 104 84 68 N13 105 85 69 N12 1 1 1 C1 39 29 24 H1 55 45 37 N1 64 54 46 P4 109 89 73 M14 137 - - - 163 133 109 A13 188 156 126 A9 213 173 141 A4 159 129 105 E14 40 30 25 H5 54 44 36 M1 63 53 45 P3 108 88 72 N14 136 - - - 162 132 108 B14 189 157 127 A8 216 176 144 B1 - - - E1 - - - G1 - - - P7 - - - P11 - - - L14 - - - A11 - - - A5 - - - N7 - - - M7 - - - K7 - - - J7 - - - G7 - - - H7 - - - H8 - - - G8 Page 62 of 201 S6E2C5 Series Module Clock Pin name Main clock (oscillation) input pin 106 86 70 X1 Main clock (oscillation) I/O pin 107 87 71 P13 X0A Sub clock (oscillation) input pin 73 58 50 P5 X1A Sub clock (oscillation) I/O pin 74 59 51 P6 Built-in High-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter analog reference voltage input pin VBAT power supply pin. Backup power supply (battery etc.) and system power supply. A/D converter and D/A converter GND pin Power supply stabilization capacity pin 157 184 127 152 103 122 D13 E8 110 90 74 M13 112 92 76 L13 113 93 77 L12 75 60 52 P8 111 91 75 M12 62 52 44 P2 AVRL AVRH Analog GND C Pin Pin No LQP LQS 176 144 X0 AVCC VBAT Power LQQ 216 LBE 192 P12 CROUT_0 CROUT_1 Analog Power Function VBAT AVSS C Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-04984 Rev.*B Page 63 of 201 S6E2C5 Series 5. I/O Circuit Type Type A Circuit Remarks Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R It is possible to select the main oscillation/GPIO function. Pull-up resistor control Digital input Standby mode control Clock input When the main oscillation is selected: ・ Oscillation feedback resistor: approximately 1 MΩ ・ Standby mode control Feedback resistor Standby mode control Digital input Standby mode control Pull-up When the GPIO is selected: ・ CMOS level output. ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control B Pull-up resistor Digital input Document Number: 002-04984 Rev.*B ・ CMOS level hysteresis input ・ Pull-up resistor: approximately 50 kΩ Page 64 of 201 S6E2C5 Series Type C Circuit Remarks Digital input Digital output N-ch ・ Open drain output ・ CMOS level hysteresis input E P-ch P-ch N-ch Digital output Digital output R Pull-up resistor control ・ ・ ・ ・ ・ CMOS level output CMOS level hysteresis input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Digital input Standby mode control F P-ch P-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control ・ ・ ・ ・ ・ ・ ・ CMOS level output CMOS level hysteresis input Input control Analog input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Analog input Input control Document Number: 002-04984 Rev.*B Page 65 of 201 S6E2C5 Series Type Circuit Remarks G P-ch P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input ・ ・ ・ ・ ・ CMOS level output CMOS level hysteresis input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -12 mA, IOL = 12 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Standby mode control H GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output UDP/Pxx USB Full-speed/Low-speed control UDP input Differential UDM/Pxx It is possible to select either USB I/O or GPIO function. When the USB I/O is selected: ・ Full-speed, low-speed control Differential input USB/GPIO select UDM input UDM output When the GPIO is selected: ・ CMOS level output ・ CMOS level hysteresis input ・ Standby mode control ・ IOH = -20.5 mA, IOL = 18.5 mA USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: 002-04984 Rev.*B Page 66 of 201 S6E2C5 Series Type I Circuit P-ch Remarks P-ch N-ch Digital output Digital output ・ ・ ・ ・ ・ ・ ・ ・ R ・ Pull-up resistor control Digital input CMOS level output CMOS level hysteresis input 5V tolerant Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ IOH = -4 mA, IOL = 4 mA Available to control of PZR registers (pseudo-open drain control) For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. Standby mode control J Mode input CMOS level hysteresis input K P-ch P-ch N-ch Digital output Digital output R ・ CMOS level output ・ TTL level hysteresis input ・ Pull-up resistor control ・Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4mA, IOL = 4mA Pull-up resistor control Digital input Standby mode control Document Number: 002-04984 Rev.*B Page 67 of 201 S6E2C5 Series Type Circuit Remarks L P-ch P-ch N-ch Digital output Digital output Pull-up resistor control R ・ ・ ・ ・ ・ CMOS level output CMOS level hysteresis input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -8 mA, IOL = 8 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Digital input Standby mode control N Pull-up resistor control P-ch P-ch N-ch R N-ch Digital output Digital output Fast mode control Digital input Standby mode control Document Number: 002-04984 Rev.*B ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA (GPIO) ・ IOL = 20mA (Fast mode Plus) ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Page 68 of 201 S6E2C5 Series Type Circuit Remarks O Pull-up resistor control P-ch P-ch N-ch Digital output Digital output R Digital input ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. ・ For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part (002-04856).” P P-ch P-ch X0A N-ch Pull-up resistor control Digital output Digital output R ・ CMOS level output ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part (002-04856).” Digital input Standby mode control OSC Document Number: 002-04984 Rev.*B Page 69 of 201 S6E2C5 Series Type Q Circuit Pull-up resistor control Digital output P-ch P-ch X1A Remarks Digital output N-ch R Digital input Standby mode control OSC RX It is possible to select the sub oscillation/GPIO function. When the sub oscillation is selected: ・ Oscillation feedback resistor: approximately 10 MΩ When the GPIO is selected: ・ CMOS level output. ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part (002-04856).” Standby mode control Clock input R P-ch P-ch N-ch Pull-up resistor control Digital output Digital output R Digital input ・ CMOS level output ・ CMOS level hysteresis input ・ Analog output ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA (4.5V to 5.5V) ・ IOH = -2 mA, IOL = 2 mA (2.7V to 4.5V) Standby mode control Analog output Document Number: 002-04984 Rev.*B Page 70 of 201 S6E2C5 Series Type S Circuit P-ch Remarks Pull-up resistor control P-ch Digital output N-ch Port Drive Select R Digital input ・ CMOS level output ・ (It is possible to select by port drive capability. Select register [PDSR]) ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -10 mA, IOL = 10 mA (PDSR = 1) ・ IOH = -4 mA, IOL = 4 mA (PDSR = 0) ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Standby mode Control Document Number: 002-04984 Rev.*B Page 71 of 201 S6E2C5 Series 6. Handling Precautions Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power-supply pin or ground pin. Document Number: 002-04984 Rev.*B Page 72 of 201 S6E2C5 Series Latch-Up Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Document Number: 002-04984 Rev.*B Page 73 of 201 S6E2C5 Series Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent this, do the following: 1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. 3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%. 4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in these aluminum laminate bags for storage. 5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-04984 Rev.*B Page 74 of 201 S6E2C5 Series 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of static electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive gases, dust, or oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, including cosmic radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, flame CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04984 Rev.*B Page 75 of 201 S6E2C5 Series 7. Handling Devices Power-Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines, however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane, as this is expected to produce stable operation. Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board. Sub Crystal Oscillator The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress recommends a crystal oscillator that meets the following conditions:  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF Document Number: 002-04984 Rev.*B Page 76 of 201 S6E2C5 Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.  Example of Using an External Clock Device X0(X0A) Set as external clock input Can be used as general-purpose I/O ports. X1(PE3), X1A (P47) Handling When Using Multi-Function Serial Pin as I2C Pin If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output must be disabled. I2C pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU power off. C Pin Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance is low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important to prevent the device from erroneously switching to test mode as a result of noise. Document Number: 002-04984 Rev.*B Page 77 of 201 S6E2C5 Series Notes on Power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part(002-04856). Turning on: Turning off: VBAT → VCC → USBVCC0 VBAT → VCC → USBVCC1 VCC → AVCC → AVRH AVRH → AVCC → VCC USBVCC1 → VCC → VBAT USBVCC0 → VCC → VBAT Serial Communication There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take care to design the printed circuit board to minimize noise. Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Characteristics within the Product Line The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If you are switching to a different product of the same series, please make sure to evaluate the electric characteristics. Pull-up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Pin Doubled as Debug Function The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as input. Document Number: 002-04984 Rev.*B Page 78 of 201 S6E2C5 Series 8. Block Diagram S6E2C5AH/J/L, S6E2C59H/J/L, S6E2C58H/J/L TRSTX,TCK, TDI,TMS TDO SWJ-DP ETM/HTM* TRACEDx, TRACECLK TPIU/ETB* ROM Table SRAM0 96/144/192 Kbytes SRAM1 32 Kbytes Cortex-M4　Core I @200 MHz(Max) D FPU SRAM2 32 Kbytes MPU NVIC Multi-layer AHB (Max 200 MHz) Sys AHB-APB Bridge: APB0(Max 100 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) CSV MainFlash I/F MainFlash/DualFlash 2 Mbytes(1M+1M)/ 1.5 Mbytes(1M+0.5M)/ 1 Mbytes(MainOnly) Trace Buffer (16 Kbytes) Security DualFlash I/F USB2.0 (Host/ Func) PHY USB2.0 (Host/ Func) PHY USBVCC0 UDP0,UDM0 UHCONX0 USBVCC1 UDP1,UDM1 UHCONX1 DMAC 8ch. CLK DSTC CR 100 kHz CR 4 MHz PLL TX1,RX1 CAN ch.2 TX2,RX2 VBAT Domain Sub Osc I2S 1unit AHB-AHB Bridge (Slave) X0A X1A Main Osc TX0,RX0 CAN ch.1 PRG-CRC Accelerator Source Clock X0 X1 CAN ch.0 GPIO MODE-Ctrl Unit 2 TIOBx AINx BINx ZINx FRCK0 QPRC 4ch. 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. DTTI0X Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer × 3 VBAT VWAKEUP VREGCTL RTCCO, SUBOUT DAx Document Number: 002-04984 Rev.*B S_DATAx S_CD,S_WP Q_IOx 16-bit Output Compare 6ch. RTO0x S_CLK,S_CMD SD-CARD I/F Hi-Speed Quad SPI A/D Activation Compare 6ch. IC0x . . . PFx MD0, MD1 Q_SCK, Q_CSx Base Timer 16-bit 32ch./ 32-bit 16ch. VBAT Domain Real-Time Clock Port Ctrl. 12-bit D/A Converter 2units MADx External Bus I/F MADATAx MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX CAN Prescaler AHB-APB Bridge : APB2 (Max 100 MHz) Unit 1 AHB-APB Bridge : APB1 (Max 200 MHz) ANxx AHB-AHB Bridge (Master) 12-bit A/D Converter Unit 0 ADTGx TIOAx P0x, P1x, PIN-Function-Ctrl CROUT AVCC, AVSS, AVRH, AVRL I2SMCLK, I2SWS, I2SCK I2SDI I2SDO USB Clock Ctrl PLL I2S Clock Ctrl PLL Power-On Reset LVD Ctrl LVD IRQ-Monitor Regulator C CRC Accelerator Watch Counter Deep Standby Ctrl WKUPx Peripheral Clock Gating Low-speed CR Prescaler External Interrupt Controller 32-pin + NMI INTx NMIX Multi-function Serial I/F 16ch. (with FIFO ch.0 to ch.7) HW flow control(ch.4,5) SCKx SINx SOTx CTSx RTSx Page 79 of 201 S6E2C5 Series 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4008_1000 0x4008_0000 0x4007_0000 0x4006_F000 0x4006_E000 0xFFFF_FFFF 0x4006_D000 Reserved 0x4006_C000 Programmable-CRC CAN-FD (CAN ch.2) GPIO SD-Card I/F Reserved I2S 0xE010_0000 0xE000_0000 0xD000_0000 Cortex-M4 Private Peripherals Reserved Reg. Area 0x4006_4000 0x4006_3000 External Device Area 0x4006_2000 0x4006_1000 0x4006_0000 0x6000_0000 0x4005_0000 0x4004_0000 Reserved 0x4400_0000 0x4200_0000 0x4003_F000 0x4003_E000 32 Mbytes Bit band alias 0x4003_D000 0x4003_C800 CAN ch.1 CAN ch.0 DSTC DMAC USB ch.1 USB ch.0 EXT-bus I/F Reserved I2S prescaler Reserved Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x4003_C100 Peripherals 0x4000_0000 0x4003_B000 0x4003_A000 Reserved 0x2400_0000 0x2200_0000 0x4003_9000 0x4003_8000 32 Mbytes Bit band alias 0x4003_7000 0x4003_6000 0x4003_5000 DualFlash 0x200F_0000 0x4003_4000 0x4003_3000 0x4003_2000 Reserved See "Memory Map (2) and (3)" for メモリサイズの 詳細は 次項の「●メモリマップ(2)」 memory size を参照してください。 details. 0x2004_8000 0x2004_0000 0x2003_8000 0x2000_0000 0x1FFF_0000 0x0050_0000 0x0040_0000 0x4003_0000 0x4002_F000 SRAM2 SRAM1 Reserved SRAM0 Reserved Security/CR Trim MainFlash 0x0000_0000 0x4003_1000 0x4002_E000 Reserved 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_3000 0x4002_2000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-04984 Rev.*B RTC/Port Ctrl Watch Counter CRC MFS CAN prescaler USB Clock ctrl LVD/DS mode Reserved D/AC Reserved Int-Req.Read EXTI Reserved CR Trim A/DC QPRC Base Timer PPG Reserved MFT Unit2 MFT Unit1 MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F Page 80 of 201 S6E2C5 Series Memory Map (2) S6E2C5AH/J/L S6E2C59H/J/L 0x2020_0000 0x2020_0000 Reserved 0x2003_8000 0x2020_0000 Reserved 0x2004_8000 0x2004_0000 S6E2C58H/J/L Reserved 0x2004_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes 0x2004_0000 0x2003_8000 Reserved 0x2004_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes 0x2004_0000 0x2003_8000 Reserved 0x2000_0000 Reserved 0x2000_0000 0x2000_0000 SRAM0 128 Kbytes SRAM0 192 Kbytes SRAM2 32 Kbytes SRAM1 32 Kbytes 0x1FFF_0000 SRAM0 64 Kbytes 0x1FFE_0000 0x1FFD_0000 0x0041_0000 0x0040_2000 0x0040_0000 SA3(#0) (8KB) General purpose CR trimming Security 0x0040_8000 0x0040_6000 0x0040_4000 0x0040_2000 0x0040_0000 SA0-3(#1) (8KBx4) SA3(#0) (8KB) General purpose CR trimming Security 0x0040_8000 0x0040_6000 0x0040_4000 0x0040_2000 0x0040_0000 SA0-3(#1) (8KBx4) SA3(#0) (8KB) General purpose CR trimming Security MainFlash 40 Kbytes 0x0040_4000 SA0-3(#1) (8KBx4) 0x0041_0000 MainFlash 40 Kbytes 0x0040_6000 0x0041_0000 MainFlash 40 Kbytes 0x0040_8000 Reserved Reserved Reserved Reserved Reserved 0x0020_0000 Reserved SA9-23(#1) (64KBx15) SA9-15(#1) (64KBx7) SA8(#1) (32KB) SA4-7(#1) (8KBx4) 0x0010_0000 0x0000_0000 SA8(#0) (32KB) SA4-7(#0) (8KBx4) SA9-23(#0) (64KBx15) 0x0000_0000 SA8(#0) (32KB) SA4-7(#0) (8KBx4) 0x0010_0000 SA9-23(#0) (64KBx15) 0x0000_0000 SA8(#0) (32KB) SA4-7(#0) (8KBx4) MainFlash 1 Mbytes SA9-23(#0) (64KBx15) MainFlash 1.5 Mbytes MainFlash 2 Mbytes 0x0010_0000 SA8(#1) (32KB) SA4-7(#1) (8KBx4) 0x0018_0000 * See S6E2CC/S6E2C5/S6E2C4/S6E2C3/S6E2C2/S6E2C1 Series Flash Programming Manual to confirm the detail of flash Memory. Document Number: 002-04984 Rev.*B Page 81 of 201 S6E2C5 Series Memory Map (2) during Dual Flash Mode S6E2C5AH/J/L 0x200F_8000 SA8(#1) (32KB) SA4-7(#1) (8KBx4) SA0-3(#1) (8KBx4) 0x2018_0000 0x2010_0000 0x200F_8000 Reserved 0x2003_8000 SA9-15(#1) (64KBx7) SA8(#1) (32KB) SA4-7(#1) (8KBx4) SA0-3(#1) (8KBx4) 0x2020_0000 Reserved 0x2010_0000 0x200F_8000 Reserved 0x2004_8000 0x2004_0000 Reserved 0x2004_0000 0x2003_8000 Reserved 0x2004_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes 0x2004_0000 0x2003_8000 Reserved 0x2000_0000 SRAM2 32 Kbytes SRAM1 32 Kbytes Reserved 0x2000_0000 0x2000_0000 SRAM0 128 Kbytes SRAM0 192 Kbytes SA0-3(#1) (8KBx4) Reserved 0x2004_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes DualFlash 32 Kbytes 0x2010_0000 0x2020_0000 S6E2C58H/J/L DualFlash 512 Kbytes +32 Kbytes SA9-23(#1) (64KBx15) DualFlash 1 Mbytes +32 Kbytes 0x2020_0000 S6E2C59H/J/L 0x1FFF_0000 SRAM0 64 Kbytes 0x1FFE_0000 0x1FFD_0000 0x0041_0000 0x0040_2000 0x0040_0000 SA3(#0) (8KB) General purpose CR trimming / HTM Security 0x0040_6000 0x0040_4000 0x0040_2000 0x0040_0000 Reserved 0x0040_0000 SA3(#0) (8KB) General purpose CR trimming / HTM Security 0x0010_0000 SA8(#0) (32KB) SA4-7(#0) (8KBx4) SA9-23(#0) (64KBx15) 0x0000_0000 SA8(#0) (32KB) SA4-7(#0) (8KBx4) MainFlash 1 Mbytes SA9-23(#0) (64KBx15) 0x0000_0000 Reserved Reserved MainFlash 1 Mbytes Document Number: 002-04984 Rev.*B MainFlash 1 Mbytes SA8(#0) (32KB) SA4-7(#0) (8KBx4) 0x0040_4000 0x0040_2000 0x0010_0000 SA9-23(#0) (64KBx15) 0x0040_6000 Reserved 0x0010_0000 0x0000_0000 SA3(#0) (8KB) General purpose CR trimming / HTM Security 0x0040_8000 MainFlash 8 Kbytes 0x0040_4000 0x0040_8000 0x0041_0000 Reserved MainFlash 8 Kbytes 0x0040_6000 0x0041_0000 Reserved MainFlash 8 Kbytes 0x0040_8000 Reserved Reserved Reserved Page 82 of 201 S6E2C5 Series Memory Map (3) S6E2C5AH 0xD000_0000 S6E2C5AJ 0xD000_0000 S6E2C5AL 0xD000_0000 Hi-Speed Quad SPI 256 Mbytes 0xC000_0000 0xC000_0000 Reserved 0x8000_0000 Hi-Speed Quad SPI 256 Mbytes 0xC000_0000 Reserved 0x8000_0000 Reserved 0x8000_0000 SDRAM 256 Mbytes 0x7000_0000 0x7000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 Document Number: 002-04984 Rev.*B SDRAM 256 Mbytes 0x7000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 Page 83 of 201 S6E2C5 Series Peripheral Address Map Start Address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_3000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_C100 0x4003_C800 0x4003_D000 0x4003_E000 0x4003_F000 End Address 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_1FFF 0x4002_2FFF 0x4002_3FFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_2FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_C0FF 0x4003_C7FF 0x4003_CFFF 0x4003_DFFF 0x4003_EFFF 0x4003_FFFF Document Number: 002-04984 Rev.*B Bus AHB APB0 APB1 APB2 Peripherals MainFlash I/F register Reserved Clock/reset control Hardware watchdog timer Software watchdog timer Reserved Dual-timer Reserved Multi-Function Timer unit 0 Multi-Function Timer unit 1 Multi-Function Timer unit 2 Reserved PPG Base timer Quadrature position/revolution counter A/D converter Reserved Internal CR trimming Reserved External interrupt controller Interrupt request batch-read function Reserved D/A converter Reserved Low voltage detector Deep standby mode Controller USB clock generator CAN prescaler Multi-function serial interface CRC Watch counter RTC/port control Low-speed CR prescaler Peripheral clock gating Reserved I2S prescaler Reserved External memory interface Page 84 of 201 S6E2C5 Series Start Address 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_3000 0x4006_4000 0x4006_C000 0x4006_D000 0x4006_E000 0x4006_F000 0x4007_0000 0x4008_0000 0x4008_1000 0x200E_0000 0xD000_0000 End Address 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_2FFF 0x4006_3FFF 0x4006_BFFF 0x4006_CFFF 0x4006_DFFF 0x4006_EFFF 0x4006_FFFF 0x4007_FFFF 0x4008_0FFF 0x41FF_FFFF 0x200E_FFFF 0xDFFF_FFFF Document Number: 002-04984 Rev.*B Bus AHB Peripherals USB ch 0 USB ch 1 DMAC register DSTC register CAN ch 0 CAN ch 1 Reserved I2 S Reserved SD card I/F GPIO CAN-FD (CAN ch 2) Programmable-CRC Reserved Workflash I/F register High-speed quad SPI control register Page 85 of 201 S6E2C5 Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings:  INITX = 0 This is the period when the INITX pin is at the L level.  INITX = 1 This is the period when the INITX pin is at the H level.  SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.  Setting prohibition Prohibition of a setting by specification limitation Document Number: 002-04984 Rev.*B Page 86 of 201 S6E2C5 Series Pin Status Type List of Pin Behavior by Mode State Function Group INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Power Supply Stable INITX=1 ‐ Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Main crystal oscillator input pin/ Input external enabled main clock input selected Input enabled Input enabled Input enabled Input enabled Maintain previous state GPIO Hi-Z/intern Hi-Z/intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 GPIO selected Maintain previous state Hi-Z/intern al input fixed at 0 Maintain previous State GPIO selected A Power-On Reset or LowVoltage Detection State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 GPIO Hi-Z/intern Hi-Z/intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 Input enabled Input enabled Input enabled Power Supply Stable INITX=1 GPIO selected Input Enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Main crystal oscillator output pin Hi-Z/ internal input fixed at 0/ or input enable Hi-Z/ internal input fixed at 0 Hi-Z/ internal input fixed at 0 C INITX input pin Pull-up/ input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input enabled Input enabled Setting disabled Setting disabled Input enabled Hi-Z/ input enabled Input enabled Hi-Z/ input enabled Input enabled Setting disabled Input enabled Maintain previous state Input enabled GPIO selected Input enabled Maintain previous state B E Document Number: 002-04984 Rev.*B Maintain previous state Hi-Z/intern al input fixed at 0 Maintain previous state while oscillator active/ When oscillation stops*1, it will be Hi-Z/ Internal input fixed at 0 GPIO selected GPIO selected Page 87 of 201 Pin Status Type S6E2C5 Series Function Group INITX Input State Device Internal Reset State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ NMIX selected F Power-On Reset or LowVoltage Detection State Setting disabled Setting disabled Resource other than above selected GPIO selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled JTAG selected Hi-Z Pull-up/ input enabled Pull-up/ input enabled I GPIO selected Setting disabled Setting disabled Setting disabled JTAG selected Hi-Z Pull-up/ input enabled Pull-up/ input enabled Resource other than above selected GPIO selected Resource selected GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Document Number: 002-04984 Rev.*B Power Supply Stable INITX=1 ‐ Setting disabled G H Run mode or Sleep mode State Maintain previous state Maintain previous state Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 Maintain previous state Maintain previous Hi-Z/ state internal input fixed at 0 INITX=1 SPL=0 SPL=1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z/ WKUP input enabled Maintain previous state Maintain previous state GPIO Hi-Z/ Hi-Z/ selected, internal internal internal input fixed input fixed input fixed at 0 at 0 at 0 Maintain previous state Maintain previous state WKUP input enabled Maintain previous state Maintain previous state Power Supply Stable INITX=1 Maintain previous state GPIO selected Maintain previous state GPIO selected Maintain previous state GPIO Hi-Z/Intern Hi-Z/Intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 GPIO selected GPIO Hi-Z/Intern Hi-Z/intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 GPIO selected Page 88 of 201 Pin Status Type S6E2C5 Series Function Group Power-On Reset or LowVoltage Detection State INITX Input State Device Internal Reset State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Run mode or Sleep mode State Power Supply Stable INITX=1 ‐ Analog output selected J K External interrupt enable selected Resource other than above selected GPIO selected External interrupt enable selected Resource other than above selected GPIO selected Analog input selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Maintain previous state Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Setting disabled Maintain previous state Setting disabled Document Number: 002-04984 Rev.*B *3 Maintain previous state Maintain previous state Power Supply Stable INITX=1 - GPIO Hi-Z/intern selected, al input internal fixed input fixed at 0 at 0 Hi-Z/intern al input fixed at 0 GPIO selected Maintain previous state Hi-Z Setting disabled Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Supply Stable *2 L Resource other than above selected GPIO selected Timer mode, RTC mode, or Stop mode State Maintain previous state GPIO Hi-Z/intern selected, al input internal fixed Hi-Z/intern input fixed at 0 al input at 0 fixed at 0 Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ internal internal internal internal input fixed input fixed input fixed input fixed at 0/ at 0/ at 0/ at 0/ analog analog analog analog input input input input enabled enabled enabled enabled Maintain previous state GPIO Hi-Z/intern Hi-Z/intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 GPIO selected Hi-Z/ internal input fixed at 0/ analog input enabled GPIO selected Page 89 of 201 Pin Status Type S6E2C5 Series Function Group Analog input selected M External interrupt enable selected Resource other than above selected GPIO selected Analog input selected N Trace selected Resource other than above selected GPIO selected Power-On Reset or LowVoltage Detection State INITX Input State Device Internal Reset State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Hi-Z/ Hi-Z/ internal internal input input fixed fixed Hi-Z at 0/ at 0/ analog analog input input enabled enabled Run mode or Sleep mode State Power Supply Stable INITX=1 ‐ Hi-Z/ internal input fixed at 0/ analog input enabled Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ internal internal internal internal input fixed input fixed input fixed input fixed at 0/ at 0/ at 0/ at 0/ analog analog analog analog input input input input enabled enabled enabled enabled Power Supply Stable INITX=1 Hi-Z/ internal input fixed at 0/ analog input enabled Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z Hi-Z/ internal input fixed at0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Maintain previous state GPIO Hi-Z/intern selected, al input internal fixed Hi-Z/intern input fixed at 0 al input at 0 fixed at 0 Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ internal internal internal internal input fixed input fixed input fixed input fixed at 0/ at 0/ at 0/ at 0/ analog analog analog analog input input input input enabled enabled enabled enabled GPIO selected Hi-Z/ internal input fixed at 0/ analog input enabled Trace output Setting disabled Setting disabled Document Number: 002-04984 Rev.*B Setting disabled Maintain previous state Maintain previous state GPIO Hi-Z/intern selected, al input Hi-Z/intern internal fixed al input input fixed at 0 fixed at 0 at 0 GPIO selected Page 90 of 201 Pin Status Type S6E2C5 Series Function Group Analog input selected O Trace selected External interrupt enable selected Resource other than above selected GPIO selected Analog input selected P Power-On Reset or LowVoltage Detection State INITX Input State Device Internal Reset State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Hi-Z/ Hi-Z/ internal internal input input fixed fixed Hi-Z at 0/ at 0/ analog analog input input enabled enabled Run mode or Sleep mode State Power Supply Stable INITX=1 ‐ Hi-Z/ internal input fixed at 0/ analog input enabled Timer mode, RTC mode, or Stop mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ internal internal internal internal input fixed input fixed input fixed input fixed at 0/ at 0/ at 0/ at 0/ analog analog analog analog input input input input enabled enabled enabled enabled Power Supply Stable INITX=1 Hi-Z/ internal input fixed at 0/ analog input enabled Trace output Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Maintain previous state Maintain previous state GPIO Hi-Z/intern selected, al input internal fixed input fixed at 0 Hi-Z/intern at 0 al input fixed at 0 Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ internal internal internal internal input fixed input fixed input fixed input fixed at 0/ at 0/ at 0/ at 0/ analog analog analog analog input input input input enabled enabled enabled enabled Maintain previous state WKUP enabled Resource other than above selected GPIO selected Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Setting disabled Setting disabled Document Number: 002-04984 Rev.*B Setting disabled Maintain previous state Maintain previous state WKUP input enabled GPIO selected Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ WKUP input enabled GPIO Hi-Z/intern Hi-Z/intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 GPIO selected Page 91 of 201 Pin Status Type S6E2C5 Series Function Group Power-On Reset or LowVoltage Detection State INITX Input State Device Internal Reset State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Run mode or Sleep mode State Power Supply Stable INITX=1 ‐ Timer mode, RTC mode, or Stop mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Hi-Z/ WKUP WKUP input input enabled enabled WKUP enabled Q External interrupt enable selected Resource other than above selected Setting disabled Setting disabled Maintain previous state Setting disabled Maintain previous state Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Maintain previous state Hi-Z at transmission/ input enabled/ internal input fixed at 0 at reception Maintain previous state GPIO selected GPIO selected R Setting disabled Setting disabled Setting disabled Ethernet I/O Setting selected disabled *4 Setting disabled Setting disabled USB I/O pin V Resource other than above selected Hi-Z Hi-Z/ input enabled GPIO selected Document Number: 002-04984 Rev.*B Hi-Z/ input enabled Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State GPIO Hi-Z/intern selected, al input internal fixed Hi-Z/intern input fixed at 0 al input at 0 fixed at 0 GPIO Hi-Z/intern Hi-Z/intern selected, al input al input internal fixed fixed input fixed at 0 at 0 at 0 Hi-Z at Hi-Z at transtransmission/ mission/ input input Hi-Z/ Hi-Z/ enabled/ enabled/ input input internal internal enabled enabled input fixed input fixed at 0 at at 0 at reception reception Maintain previous state Power Supply Stable INITX=1 WKUP input enabled GPIO selected GPIO selected Hi-Z/ input enabled Maintain previous state Maintain previous state Maintain previous state GPIO Hi-Z/intern selected, al input internal fixed Hi-Z/intern input fixed at "0 al input at 0 fixed at 0 GPIO selected Page 92 of 201 Pin Status Type S6E2C5 Series Function Group Power-On Reset or LowVoltage Detection State INITX Input State Device Internal Reset State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Power Supply Stable INITX=1 ‐ Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Ethernet input/output selected*4 W External interrupt enable selected Resource other than above selected GPIO selected Setting disabled Setting disabled Maintain previous state Setting disabled Maintain previous state Hi-Z Hi-Z/ input enabled Maintain previous state Hi-Z/ input enabled Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Hi-Z/intern al input fixed at 0 GPIO Hi-Z/intern selected, al input internal fixed input fixed at 0 at 0 Power Supply Stable INITX=1 - GPIO selected *1: Oscillation is stopped at sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Maintain previous state at Timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at Timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode. *4: It shows the case selected by EPFR14.E_SPLC register. Document Number: 002-04984 Rev.*B Page 93 of 201 S6E2C5 Series VBAT Pin Status Type List of VBAT Domain Pin Status INITX Input State Power Supply Unstabl e Power Supply Stable Function Group ‐ ‐ INITX=0 ‐ Maintain GPIO Setting previous selected disabled state Sub crystal S oscillator input pin/ Input Input external enabled enabled sub clock input selected Maintain GPIO Setting previous selected disabled state External Maintain sub clock Setting previous input disabled state selected T Hi-Z/ Sub internal crystal input Maintain oscillator fixed at previous output 0/ state pin or input enable Resource selected U Hi-Z GPIO selected Run Device mode Internal or Reset Sleep State mode State Poweron reset*1 INITX=1 ‐ Timer Mode, RTC mode, or Stop mode State Return Deep Standby From RTC mode or Deep Deep Standby Stop Standby mode State Mode State VBAT RTC Mode State Return From VBAT RTC Mode State Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable INITX=1 ‐ INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 INITX=1 - - - Maintain Maintain Maintain Maintain Maintain Maintain Maintain Setting previous previous previous previous previous previous previous prohibition state state state state state state state Input Input Input enabled enabled enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain Maintain Maintain Maintain Maintain Maintain Maintain Setting previous previous previous previous previous previous previous prohibition state state state state state state state - Maintain previous state - Maintain Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous previous state state state state state state state Maintain previous state Maintain previous state Maintain Maintain Maintain Maintain previous previous previous previous Maintain Maintain state/ state/ state/ state/ Maintain previous previous When When When When previous state state oscillation oscillation oscillation oscillation state stops, stops, stops, stops, Hi-Z*2 Hi-Z*2 Hi-Z*2 Hi-Z*2 Maintain previous state Maintain previous state Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous previous previous state state state state state state state state Maintain previous state Maintain previous state *1: When VBAT and VCC power on. *2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop mode Document Number: 002-04984 Rev.*B Page 94 of 201 S6E2C5 Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Rating Remarks VCC USB) *1,*3 USBVCC0 VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB) *1,*3 USBVCC1 VSS - 0.5 VSS + 6.5 V VBAT AVCC AVRH VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5 V) USBVCC0 + 0.5 (≤ 6.5 V) USBVCC1 + 0.5 (≤ 6.5 V) VSS + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) 10 20 20 20 22.4 4 8 10 12 20 100 50 - 10 V V V mA mA mA mA mA mA mA mA mA mA mA mA mA 4 mA type 8 mA type 10 mA type 12 mA type I2C Fm+ 4 mA type 8 mA type 10 mA type 12 mA type I2C Fm+ -20 mA 8 mA type - 20 - 20 -4 -8 - 10 - 12 - 100 - 50 200 + 150 mA mA mA mA mA mA mA mA mW °C 10 mA type 12 mA type 4 mA type 8 mA type 10 mA type 12 mA type Power supply voltage*1,*2 Power supply voltage (for *1 ,*4 Power supply voltage (VBAT) Analog power supply voltage *1 ,*5 Analog reference voltage *1 ,*5 VSS - 0.5 Input voltage *1 VI VSS - 0.5 VSS - 0.5 VSS - 0.5 Analog pin input voltage Output voltage *1 *1 L level maximum output current *6 L level average output current *7 L level total maximum output current L level total maximum output current H level maximum output current *8 *6 H level average output current *7 H level total maximum output current H level total average output current *8 Power consumption Storage temperature VIA VSS - 0.5 VO VSS - 0.5 IOL - IOLAV - ∑IOL ∑IOLAV - IOH Max VSS + 6.5 Unit Min VSS - 0.5 - IOHAV - ∑IOH ∑IOHAV PD TSTG - 55 V V Except for USB pin V USB ch 0 pin V USB ch 1 pin V 5V tolerant V V 4 mA type *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: USBVCC0, USBVCC1 must not drop below VSS - 0.5 V. *4: VBAT must not drop below VSS - 0.5 V. *5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100-ms period. Document Number: 002-04984 Rev.*B Page 95 of 201 S6E2C5 Series *8: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100-ms period. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-04984 Rev.*B Page 96 of 201 S6E2C5 Series 12.2 Recommended Operating Conditions Parameter Power supply voltage Power supply voltage (for USB ch 0) Power supply voltage (for USB ch 1) Power supply voltage (VBAT) Analog power supply voltage Analog reference voltage Operating temperature Junction temperature Ambient temperature Symbol Conditions VCC - USBVCC0 USBVCC1 VBAT AVCC AVRH AVRL TJ TA Value Remarks Max 5.5 3.0 3.6 ( ≤VCC) 2.7 5.5 ( ≤VCC) *2 3.0 3.6 ( ≤VCC) *3 2.7 5.5 ( ≤VCC) 1.65 2.7 *6 AVSS - 40 -40 5.5 5.5 AVCC AVSS + 125 *5 - V *1 V - - Unit Min 2.7 *7 V *4 V V V V °C °C AVCC = VCC *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0) *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80) *3: When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1) *4: When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82) *5: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is: TA (Max) = TJ(Max) - Pd(Max) × θJA Pd: Power dissipation (W) θJA: Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage *6: The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5. 12-bit A/D Converter for the details. *7: For the voltage range between Vcc(min) and the low voltage detection reset (VDH), the MCU must be clocked from either the High-speed CR or the low-speed CR.” Document Number: 002-04984 Rev.*B Page 97 of 201 S6E2C5 Series Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for Package Thermal Resistance and Maximum Permissible Power Package LQS144 (0.5-mm pitch) LQP176 (0.5-mm pitch) LQQ216 (0.4-mm pitch) LBE192 (0.8-mm pitch) Printed Circuit Board Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Maximum Permissible Power (mW) Thermal Resistance θja (°C/W) TA = +85°C TA = +105°C 48 833 417 33 1212 606 45 889 444 31 1290 645 46 870 435 32 1250 625 - - - 35 1143 571 WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04984 Rev.*B Page 98 of 201 S6E2C5 Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage ICC is the current drawn by the device. It can be analyzed as follows. ICC = ICC (INT) + ΣICC (IO) ICC (INT): Current drawn by internal logic and memory, etc. through the regulator ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin For ICC (INT), it can be anticipated by (1) Current Rating in 12.3. DC Characteristics (This rating value does not include ICC (IO) for a value at pin fixed). For ICC (IO), it depends on system used by customers. The calculation formula is shown below. ICC (IO) = (CINT + CEXT) × VCC × fSW CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Pin internal load capacitance CINT Conditions Capacitance Value 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself: Measure current value ICC (Typ) at normal temperature (+25°C). Add maximum leakage current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC (Typ) + ICC (leak_max) Parameter Symbol Maximum leakage current at operating ICC (leak_max) Document Number: 002-04984 Rev.*B Conditions Current Value TJ = +125°C 79.2 mA TJ = +105°C 39.4 mA TJ = +85°C 26.5 mA Page 99 of 201 S6E2C5 Series Current Explanation Diagram Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC=ICC (INT)＋ΣICC (IO) VCC A ICC Chip ICC (INT) ΣICC (IO) A Regulator VOL V A ・・・ V IOL Flash VOH ・・・ Logic IOH RAM ICC (IO) CEXT ・・・ Document Number: 002-04984 Rev.*B Page 100 of 201 S6E2C5 Series 12.3 DC Characteristics 12.3.1 Current Rating Table 12-1 Typical and Maximum Current Consumption in Normal Operation(PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Value Pin Parameter Symbol Conditions Frequency*4 Unit Remarks 1 Name Typ* Max*2 200 MHz 117 224 mA *5 192 MHz 113 219 mA 180 MHz 106 211 mA 160 MHz 95 197 mA 144 MHz 86 186 mA 120 MHz 73 169 mA *3 When all 100 MHz 61 155 mA peripheral clocks 80 MHz 50 140 mA are on *6 60 MHz 39 126 mA 40 MHz 27 112 mA 20 MHz 16 97 mA 8 MHz 8.7 88.9 mA Normal Power 4 MHz 6.4 86.1 mA operation supply ICC VCC *7,*8 200 MHz 71 168 mA current (PLL) *5 192 MHz 68 165 mA 180 MHz 64 159 mA 160 MHz 58 151 mA 144 MHz 52 144 mA 120 MHz 44 134 mA *3 When all 100 MHz 38 126 mA peripheral clocks 80 MHz 31 117 mA are off *6 60 MHz 24 109 mA 40 MHz 17 100 mA 20 MHz 10 91 mA 8 MHz 6.3 86.1 mA 4 MHz 5.0 84.5 mA *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1) *6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *7: Firmware being executed during data collection for this table is not being accessed from the MainFlash memory.” *8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 101 of 201 S6E2C5 Series Table 12-2 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Parameter Symbol Pin Name Frequency*4 Conditions *5 *6 Power supply current ICC VCC Normal operation *7,*8 (PLL) *5 *6 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz Value Typ* Max*2 Unit 128 123 116 102 93 79 67 54 42 30 17 9.2 6.7 74 71 67 59 53 45 39 32 25 18 11 6.5 5.1 236 230 221 205 193 175 161 145 130 115 99 90.0 86.9 170 167 162 152 145 135 127 118 110 101 92 86.8 85.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0) *6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *7: With data access to a MainFlash memory. *8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 102 of 201 S6E2C5 Series Table 12-3 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Frequency*4 Conditions *5 Power supply current ICC VCC Normal operation *6,*7 (PLL) *5 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz Value Typ* Max*2 Unit 71 62 51 40 29 17 13 8.4 46 41 34 27 20 12 9.4 6.5 161 150 138 125 112 98 93 88.5 132 125 118 110 102 93 89.7 86.4 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) *6: With data access to a MainFlash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 103 of 201 S6E2C5 Series Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other Than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Normal operation *6, *7 (main oscillation) Power supply current ICC Frequency*4 Conditions Normal operation *6 (built-in High-speed CR) VCC Normal operation *6, *8 (sub oscillation) Normal operation *6 (built-in low-speed CR) *5 *5 *5 *5 Value Unit Typ*1 Max*2 4.7 84.9 mA 3.9 83.8 mA 3.0 83.2 mA 2.1 82.0 mA 0.78 80.37 mA 0.77 80.36 mA 0.81 80.39 mA 0.78 80.38 mA 4 MHz 4 MHz 32 kHz 100 kHz Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) *6: With data access to a MainFlash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *8: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 104 of 201 S6E2C5 Series Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol ICCS Pin Name VCC Conditions Frequency*4 Sleep operation*5 (PLL) 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz Value Typ*1 Max*2 88 85 80 72 65 55 47 38 30 21 12 7.4 5.8 44 42 40 36 33 28 24 20 16 12 7.6 5.2 4.4 188 184 178 164 156 144 134 124 114 104 93 87.2 85.2 134 132 129 123 119 113 108 103 98 93 87.6 84.7 83.7 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 105 of 201 S6E2C5 Series Table 12-6 Typical and Maximum Current Consumption in Sleep Operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Power supply current Symbol ICCS Pin Name VCC Conditions Frequency*4 Sleep operation*5 (PLL) 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz Value Typ*1 Max*2 45 38 31 24 18 11 8.6 6.3 20 18 15 12 9.1 6.5 5.5 4.6 130 122 114 106 99 91 88.3 85.7 103 99 96 93 89.3 86.1 84.9 83.8 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 106 of 201 S6E2C5 Series Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other Than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Value Pin Parameter Symbol Conditions Frequency*4 Unit Remarks Name Typ*1 Max*2 Sleep operation*5 (main oscillation) Power supply current Sleep operation (built-in High-speed CR) ICCS 3.4 82.6 mA 2.5 81.7 mA 2.5 81.7 mA 1.7 80.9 mA 0.75 79.97 mA 0.74 79.96 mA 0.79 80.01 mA 0.76 79.98 mA 4 MHz 4 MHz VCC Sleep operation*6 (sub oscillation) Sleep operation (built-in low-speed CR) 32 kHz 100 kHz *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 107 of 201 S6E2C5 Series Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode Value Pin Parameter Symbol Conditions Frequency Unit Name Typ*1 Max*2 Stop mode ICCH Timer mode*5 (main oscillation) Timer mode (built-in High-speed CR) Power supply current ICCT - 4 MHz 4 MHz VCC Timer mode*6 (sub oscillation) Timer mode (built-in low-speed CR) ICCR RTC mode*6 (sub oscillation) 32 kHz 100 kHz 32 kHz Remarks 0.56 3.01 mA *3, *4 TA = +25°C - 27.03 mA *3, *4 TA = +85°C - 39.92 mA *3, *4 TA = +105°C 1.40 3.85 mA *3, *4 TA = +25°C - 27.87 mA *3, *4 TA = +85°C - 40.76 mA *3, *4 TA = +105°C 0.95 3.40 mA *3, *4 TA = +25°C - 27.42 mA *3, *4 TA = +85°C - 40.31 mA *3, *4 TA = +105°C 0.57 3.02 mA *3, *4 TA = +25°C - 27.04 mA *3, *4 TA = +85°C - 39.93 mA *3, *4 TA = +105°C 0.58 3.03 mA *3, *4 TA = +25°C - 27.05 mA *3, *4 TA = +85°C - 39.94 mA *3, *4 TA = +105°C 0.57 3.02 mA *3, *4 TA = +25°C - 27.04 mA *3, *4 TA = +85°C - 39.93 mA *3, *4 TA = +105°C *1: VCC = 3.3V *2: VCC = 5.5V *3: When all ports are fixed *4: When LVD is off *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) Document Number: 002-04984 Rev.*B Page 108 of 201 S6E2C5 Series Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Value Pin Parameter Symbol Conditions Frequency Unit Remarks Name Typ*1 Max*2 Deep standby Stop mode (When RAM is off) - 96 248 μA *3, *4 TA = +25°C - 3009 μA *3, *4 TA = +85°C - 3889 μA *3, *4 TA = +105°C 106 259 μA *3, *4 TA = +25°C - 3020 μA *3, *4 TA = +85°C - 3900 μA *3, *4 TA = +105°C 96 248 μA *3, *4 TA = +25°C - 3009 μA *3, *4 TA = +85°C - 3889 μA *3, *4 TA = +105°C 106 259 μA *3, *4 TA = +25°C - 3020 μA *3, *4 TA = +85°C - 3900 μA *3, *4 TA = +105°C 0.0058 0.1 μA *3, *4, *5 TA = +25°C - 1.4 μA *3, *4, *5 TA = +85°C - 3.3 μA *3, *4, *5 TA = +105°C 1.0 1.8 μA *3, *4 TA = +25°C - 3.2 μA *3, *4 TA = +85°C - 5.1 μA *3, *4 TA = +105°C ICCHD Deep standby Stop mode (When RAM is on) - VCC Deep Standby RTC mode (When RAM is off) Power supply current 32 kHz ICCRD Deep Standby RTC mode (When RAM is on) RTC stop*6 ICCVBAT VBAT - RTC operation*6 *1: VCC = 3.3 V *2: VCC = 5.5 V *3: When all ports are fixed *4: When LVD is off *5: When sub oscillation is off *6: In the case of setting RTC after VCC power on Document Number: 002-04984 Rev.*B Page 109 of 201 S6E2C5 Series Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase Value Pin Parameter Symbol Conditions Unit Remarks Name Min Typ Max Low-voltage detection circuit (LVD) power supply current MainFlash memory write/erase current ICCLVD At operation - 4 7 μA For occurrence of interrupt At write/erase - 13.4 15.9 mA *1 VCC ICCFLASH *1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply current (ICC). Peripheral Current Dissipation Clock system HCLK PCLK1 PCLK2 Frequency (MHz) 50 100 200 Peripheral Unit GPIO All ports 0.39 0.81 1.56 DMAC - 0.99 1.97 3.82 DSTC - 0.73 1.49 2.86 External bus I/F - 0.25 0.48 0.97 SD card I/F - 0.74 1.47 2.90 CAN 1 ch 0.06 0.08 0.16 CAN-FD 1 ch 0.77 1.50 2.95 USB 1 ch 0.48 0.95 1.89 I2 S - 0.51 1.02 1.99 High-Speed Quad SPI - 0.48 0.97 1.49 Programmable CRC - 0.05 0.10 0.22 Base timer 4 ch 0.21 0.42 0.83 1 unit/4 ch 0.83 1.65 3.25 1 unit 0.07 0.13 0.27 A/D converter 1 unit 0.31 0.60 1.17 Multi-function serial 1 ch 0.41 0.81 - Multi-functional timer/PPG Quadrature position/revolution counter Document Number: 002-04984 Rev.*B Unit Remarks mA mA mA Page 110 of 201 S6E2C5 Series 12.3.2 Pin Characteristics (VCC = USBVCC0 = USBVCC1 = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter H level input voltage (hysteresis input) Symbol VIHS VILS Value Typ Max - VCC×0.8 - VCC + 0.3 V VCC > 3.0 V, VCC ≤ 3.6 V, 2.4 - VCC + 0.3 V - VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - 2.0 - VCC+0.3 V VSS - 0.3 - VCC×0.2 V VSS - 0.3 - VCC×0.2 V - VSS - 0.3 - VCC×0.2 V - VSS - VCC×0.3 V - VSS - 0.3 - 0.8 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V USBVCC 0.4 - USBVCC V *1 VCC - 0.5 - VCC V At GPIO Conditions CMOS hysteresis input pin, MD0, MD1 MADATAxx 5 V tolerant input pin Input pin doubled as I2C Fm+ TTL Schmitt input pin CMOS hysteresis input pin, MD0, MD1 L level input voltage (hysteresis input) Min Pin Name 5 V tolerant input pin Input pin doubled as I2C Fm+ TTL Schmitt input pin - Unit Remarks At External Bus VCC ≥ 4.5 V, IOH = - 4 mA 4 mA type VCC < 4.5 V, IOH = - 2 mA VCC ≥ 4.5 V, IOH = - 8 mA 8 mA type H level output voltage VOH 10 mA type 12 mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Document Number: 002-04984 Rev.*B VCC < 4.5 V, IOH = - 4 mA VCC ≥ 4.5 V, IOH = - 10 mA VCC < 4.5 V, IOH = - 8 mA VCC ≥ 4.5 V, IOH = - 12 mA VCC < 4.5 V, IOH = - 8 mA USBVCC ≥ 4.5 V, IOH = - 20.5 mA USBVCC < 4.5 V, IOH = - 13.0 mA VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 3 mA Page 111 of 201 S6E2C5 Series Parameter Symbol Pin Name Conditions Value Unit Min Typ Max VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V Remarks VCC ≥ 4.5 V, IOL = 4 mA 4 mA type VCC < 4.5 V, IOL = 2 mA VCC ≥ 4.5 V, IOL = 8 mA 8 mA type 10 mA type L level output voltage VOL 12 mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Input leak current Pull-up resistor value Input capacitance IIL - RPU Pull-up pin CIN Other than VCC, USBVCC0, USBVCC1, VBAT, VSS, AVCC, AVSS, AVRH VCC < 4.5 V, IOL = 4 mA VCC ≥ 4.5 V, IOL = 10 mA VCC < 4.5 V, IOL = 8 mA VCC ≥ 4.5 V, IOL = 12 mA VCC < 4.5 V, IOL = 8 mA USBVCC ≥ 4.5 V, IOL = 18.5 mA USBVCC < 4.5 V, IOL = 10.5 mA VCC ≥ 4.5 V, IOL = 4 mA VCC < 4.5 V, IOL = 3 mA VCC ≤ 4.5 V, IOL = 20 mA *1 At GPIO At I2C Fm+ - -5 - +5 VCC ≥ 4.5 V 25 50 100 VCC < 4.5 V 30 80 200 - - 5 15 μA kΩ pF *1: USBVcc0 and USBVcc1 are described as USBVcc. Document Number: 002-04984 Rev.*B Page 112 of 201 S6E2C5 Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40C to +105C) Parameter Input frequency Symbol Pin Name fCH Input clock cycle tCYLH Input clock pulse width Input clock rise time and fall time X0, X1 tCF, tCR fCC - Conditions Value Min Max VCC ≥4.5 V VCC < 4.5 V VCC ≥4.5 V VCC < 4.5 V VCC ≥4.5 V VCC < 4.5 V PWH/tCYLH, PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 - Unit Remarks MHz When crystal oscillator is connected MHz When using external clock ns When using external clock 55 % When using external clock - 5 ns When using external clock - 200 MHz Base clock (HCLK/FCLK) APB0bus clock *2 100 MHz APB1bus clock *2 200 MHz APB2bus clock *2 100 MHz Base clock (HCLK/FCLK) tCYCC 5 ns Internal operating clock *1 APB0bus clock *2 tCYCP0 10 ns cycle time APB1bus clock *2 tCYCP1 5 ns APB2bus clock *2 tCYCP2 10 ns *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). *2: For more about each APB bus to which each peripheral is connected, see 8. Block Diagram in this data sheet. Internal operating frequency clock *1 fCP0 fCP1 fCP2 X0 Document Number: 002-04984 Rev.*B Page 113 of 201 S6E2C5 Series 12.4.2 Sub Clock Input Characteristics (VBAT = 1.65V to 5.5V, VSS = 0V) Parameter Symbol Input frequency Pin Name Value Conditions Unit Min Typ Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs 1/tCYLL X0A, X1A Input clock cycle tCYLL PWH/tCYLL, 45 55 % PWL/tCYLL *: For more information about crystal oscillator, see Sub crystal oscillator in 7. Handling Devices. Input clock pulse width - Remarks When crystal oscillator is connected * When using external clock When using external clock When using external clock tCYLL 0.8 × VBAT 0.8 × VBAT 0.8 × VBAT 0.2 × VBAT 0.2 × VBAT X0A PWH PWL 12.4.3 Built-In CR Oscillation Characteristics Built-In High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Conditions TJ = - 20°C to + 105°C Min Typ Max 3.92 4 4.08 Unit Remarks When trimming Clock frequency fCRH TJ = - 40°C to + 125°C 3.88 4 4.12 TJ = - 40°C to + 125°C 3 4 5 *1 MHz When not trimming Frequency stabilization *2 tCRWT 30 μs time *1: In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming *2: This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is able to use the High-speed CR clock as a source clock. Built-In Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Clock frequency fCRL - Document Number: 002-04984 Rev.*B Value Min Typ Max 50 100 150 Unit Remarks kHz Page 114 of 201 S6E2C5 Series 12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Min PLL oscillation stabilization wait time*1 tLOCK 100 (lock up time) PLL input clock frequency fPLLI 4 PLL multiplication rate 13 PLL macro oscillation clock frequency fPLLO 200 Main PLL clock frequency*2 fCLKPLL *1: Time from when the PLL starts operating until the oscillation stabilizes Unit Typ Max - - μs - 16 100 400 200 MHz multiplier MHz MHz Remarks *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). 12.4.5 Operating Conditions of USB PLL・I2S PLL (in the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter PLL oscillation stabilization wait (lock up time) PLL input clock frequency PLL multiplication rate time*1 PLL macro oscillation clock frequency USB clock frequency Min Value Typ Max tLOCK 100 - - μs fPLLI - 4 13 - fPLLO 200 - 16 100 400 384 MHz multiplier MHz MHz fCLKPLL - - 50 MHz fCLKPLL - - 12.288 MHz Symbol *2 I2S clock frequency *3 Unit Remarks USB I2 S After the M frequency division After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes *2: For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862). *3: For more information about I2S clock, see Chapter 7-1: I2S Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862). Document Number: 002-04984 Rev.*B Page 115 of 201 S6E2C5 Series 12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Min Value Typ Max tLOCK 100 - - μs fPLLI fPLLO 3.8 50 190 4 - 4.2 95 400 MHz multiplier MHz fCLKPLL - - 200 MHz Symbol time*1 PLL oscillation stabilization wait (lock up time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency *2 Unit Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). Note: − The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main PLL. 12.4.7 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Reset input time Symbol Pin Name Conditions tINITX INITX - Document Number: 002-04984 Rev.*B Value Min Typ 500 - Unit Remarks ns Page 116 of 201 S6E2C5 Series 12.4.8 Power-On Reset Timing (VSS = 0V) Parameter Symbol Power supply shut down time Power ramp rate Pin Name Min Typ Max - 1 - - VCC: 0.2V to 2.70V 0.6 - 1000 - 0.33 - 0.60 tOFF dV/dt Time until releasing Power-on reset Value Conditions VCC tPRT Unit ms Remarks *1 mV/µs *2 ms *1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 7. 2.7V VCC VDH 0.2V 0.2V dV/dt tPRT Internal RST 0.2V tOFF release RST Active CPU Operation start Glossary  VDH: detection voltage of Low Voltage detection reset. See “12.8. Low-Voltage Detection Characteristics”. 12.4.9 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol Pin Name tPCYCLE Pxx* Conditions Value Unit Min Typ VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz Remarks *: GPIO is a target. Pxx tPCYCLE Document Number: 002-04984 Rev.*B Page 117 of 201 S6E2C5 Series 12.4.10 External Bus Timing External Bus Clock Output Characteristics Parameter Symbol Pin Name tCYCLE MCLKOUT *1 Output frequency Value Conditions Min Typ - 50 *2 Unit Remarks MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main Part (002-04856). *2: Generate MCLKOUT at setting more than four divisions when the AHB bus clock exceeds 100 MHz. 0.8 × Vcc 0.8 × Vcc MCLK tCYCLE External Bus Signal I/O characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VIH Value Unit 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Remarks Signal input characteristics VIL - VOH Signal output characteristics VOL Input signal Document Number: 002-04984 Rev.*B VIH VIL VIH VIL VOH VOL VOH VOL Page 118 of 201 S6E2C5 Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions tOEW MOEX MCSX↓→Address output delay time tCSL – AV MOEX↑→Address hold time tOEH - AX MCSX↓→ MOEX↓delay time tCSL - OEL MOEX↑→ MCSX↑time tOEH - CSH MOEX Minimum pulse width MCSX↓→ MDQM↓delay time tCSL - RDQML Data set up→MOEX↑ time tDS - OE MOEX↑→ Data hold time tDH - OE Value Unit Min Max - MCLK×n-3 - ns MCSX[7: 0], MAD[24: 0] - -9 +9 ns MOEX, MAD[24: 0] - 0 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns - 0 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns - 20 - ns - 0 - ns MOEX, MCSX[7: 0] MCSX, MDQM[3: 0] MOEX, MADATA[31: 0] MOEX, MADATA[31: 0] MWEX Minimum pulse width tWEW MWEX - MCLK×n-3 - ns MWEX↑→Address output delay time tWEH - AX MWEX, MAD[24: 0] - 0 MCLK×m+9 ns MCSX↓→ MWEX↓delay time tCSL - WEL - MCLK×n-9 MCLK×n+9 ns MWEX↑→ MCSX↑delay time tWEH - CSH - 0 MCLK×m+9 ns MCSX↓→ MDQM↓delay time tCSL-WDQML - MCLK×n-9 MCLK×n+9 ns - MCLK-9 MCLK+9 ns - 0 MCLK×m+9 ns MCSX↓→ Data output time MWEX↑→ Data hold time tCSL-DX tWEH - DX MWEX, MCSX[7: 0] MCSX, MDQM[3: 0] MCSX, MADATA[31: 0] MWEX, MADATA[31: 0] Remarks Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) Document Number: 002-04984 Rev.*B Page 119 of 201 S6E2C5 Series tCYCLE MCLK tOEH-CSH tWEH-CSH MCSX[7: 0] tCSL-AV MAD[24: 0] tOEH-AX Address tWEH-AX tCSL-AV Address tCSL-OEL MOEX tOEW tCSL-WDQML tCSL-RDQML MDQM[1: 0] tCSL-WEL tWEW MWEX tDS-OE MADATA[15: 0] tDH-OE RD tWEH-DX WD Invalid tCSL-DX Document Number: 002-04984 Rev.*B Page 120 of 201 S6E2C5 Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Pin Name Condition s Min Max tAV MCLK, MAD[24: 0] - 1 9 ns MCLK, MCSX[7: 0] - 1 9 ns - 1 9 ns MCLK, MOEX - 1 9 ns - 1 9 ns - 19 - ns - 0 - ns MCLK, MWEX - 1 9 ns - 1 9 ns MCLK, MDQM[3: 0] - 1 9 ns - 1 9 ns - MCLK+1 MCLK+18 ns - 1 18 ns Address delay time tCSL MCSX delay time tCSH tREL MOEX delay time tREH Data set up →MCLK↑ time tDS MCLK↑→ Data hold time tDH MCLK, MADATA[31: 0] MCLK, MADATA[31: 0] tWEL MWEX delay time MDQM[1: 0] delay time Value Symbol tWEH tDQML tDQMH MCLK↑→ Data output time tODS MCLK↑→ Data hold time tOD MCLK, MADATA[31: 0] MCLK, MADATA[31: 0] Unit Remark s Note: − When the external load capacitance CL = 30 pF tCYCLE MCLK tCSL tCSH MCSX[7: 0] tAV tAV Address MAD[24: 0] Address tREL tREH tDQML tDQMH MOEX tDQML tDQMH tWEL tWEH MDQM[3: 0] MWEX tDS tDH RD tOD WD Invalid MADATA[31: 0] tODS Document Number: 002-04984 Rev.*B Page 121 of 201 S6E2C5 Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Multiplexed address delay time tALE-CHMADV Multiplexed address hold time tCHMADH Pin Name MALE, MAD[24: 0] Conditions Value Unit Min Max - 0 10 ns - MCLK×n+0 MCLK×n+10 ns Remarks Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) MCLK MCSX[7: 0] MALE MAD [24: 0] MOEX MDQM [3: 0] MWEX MADATA[31: 0] Document Number: 002-04984 Rev.*B Page 122 of 201 S6E2C5 Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MALE delay time Symbol Pin Name Conditions tCHAL MCLK, MALE MCLK, MADATA[31: 0] tCHAH MCLK↑→Multiplexed address delay time MCLK↑→Multiplexed data output time tCHMADV tCHMADX Value Unit Min Max - 1 9 - 1 9 - 1 tOD ns - 1 tOD ns Remarks Note: − When the external load capacitance CL = 30 pF MCLK MCSX[7: 0] MALE MAD [24: 0] MOEX MDQM [3: 0] MWEX MADATA[31: 0] Document Number: 002-04984 Rev.*B Page 123 of 201 S6E2C5 Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MNREX Min pulse width Data set up →MNREX↑time Symbol Pin Name Conditions tNREW MNREX tDS – NRE MNREX, MADATA[31: 0] MNREX, MADATA[31: 0] MNALE, MNWEX MNALE, MNWEX MNCLE, MNWEX Value Unit Min Max - MCLK×n-3 - ns - 20 - ns - 0 - ns - MCLK×m-9 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns MNREX↑→ Data hold time MNALE↑→ MNWEX delay time MNALE↓→ MNWEX delay time MNCLE↑→ MNWEX delay time tCLEH - NWEL MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX - 0 MCLK×m+9 ns tNWEW MNWEX - MCLK×n-3 - ns - -9 9 ns - 0 MCLK×m+9 ns MNWEX Min pulse width MNWEX↓→ Data output time MNWEX↑→ Data hold time tDH – NRE tALEH - NWEL tALEL - NWEL tNWEL – DV tNWEH – DX MNWEX, MADATA[31: 0] MNWEX, MADATA[31: 0] Remarks Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) NAND Flash Read MCLK MNREX MADATA[31: 0] Read Document Number: 002-04984 Rev.*B Page 124 of 201 S6E2C5 Series NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[31: 0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[31: 0] Write Document Number: 002-04984 Rev.*B Page 125 of 201 S6E2C5 Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MCLK↑ MRDY input setup time Symbol Pin Name Conditions tRDYI MCLK, MRDY - Value Min Max 19 - Unit Remarks ns  When RDY is input ··· MCLK Over 2cycle Original MOEX MWEX tRDYI MRDY  When RDY is released MCLK ··· ··· 2 cycles Extended MOEX MWEX tRDYI 0.5×VCC MRDY Document Number: 002-04984 Rev.*B Page 126 of 201 S6E2C5 Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Output frequency tCYCSD MSDCLK Address delay time tAOSD MSDCLK↑→ Data output delay time MSDCLK↑→ Data output Hi-Z time tDOSD tDOZSD MDQM[3: 0] delay time tWROSD MCSX delay time tMCSSD MRASX delay time tRASSD MCASX delay time tCASSD MSDWEX delay time tMWESD MSDCKE delay time tCKESD Data set up time tDSSD Data hold time tDHSD MSDCLK, MAD[15: 0] MSDCLK, MADATA[31: 0] MSDCLK, MADATA[31: 0] MSDCLK, MDQM[1: 0] MSDCLK, MCSX8 MSDCLK, MRASX MSDCLK, MCASX MSDCLK, MSDWEX MSDCLK, MSDCKE MSDCLK, MADATA[31: 0] MSDCLK, MADATA[31: 0] Unit Unit Min Max - - 50 MHz - 2 12 ns - 2 12 ns - 2 19.5 ns - 1 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 19 - ns - 0 - ns Remarks Note: − When the external load capacitance CL = 30 pF Document Number: 002-04984 Rev.*B Page 127 of 201 S6E2C5 Series tCYCSD SDRAM Access MSDCLK tAOSD MAD[24:0] MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE Address tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDSSD MADATA[15:0] RD tDOSD MADATA[15:0] Document Number: 002-04984 Rev.*B tDHSD tDOZSD WD Page 128 of 201 S6E2C5 Series 12.4.11 Base Timer Input Timing Timer Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin Name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin Name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is connected, see 8. Block Diagram in this data sheet. Document Number: 002-04984 Rev.*B Page 129 of 201 S6E2C5 Series 12.4.12 CSIO (SPI) Timing Synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time Notes: tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Conditions Unit Min Max Min Max 4tCYCP 8 - 4tCYCP 8 - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 130 of 201 S6E2C5 Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04984 Rev.*B Page 131 of 201 S6E2C5 Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Baud rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width tSLSH Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx Serial clock H pulse width tSHSL SCKx Parameter Symbol SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns tCYCP + 10 - tCYCP + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 132 of 201 S6E2C5 Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK tSLSH VIH VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04984 Rev.*B Page 133 of 201 S6E2C5 Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 134 of 201 S6E2C5 Series tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK VIH VIH VIL tF * SOT VIL tSHSL tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL MS bit = 1 * Changes when writing to TDR register Document Number: 002-04984 Rev.*B Page 135 of 201 S6E2C5 Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 136 of 201 S6E2C5 Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04984 Rev.*B Page 137 of 201 S6E2C5 Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Min Max Unit Max Min (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 138 of 201 S6E2C5 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 139 of 201 S6E2C5 Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Min Max Unit Max Min (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 140 of 201 S6E2C5 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 141 of 201 S6E2C5 Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↓ setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↓ setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 142 of 201 S6E2C5 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 143 of 201 S6E2C5 Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCK↓→SCS↓hold time tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↑setup time tCSSE tCSHE tCSDE tDSE tDEE SCS↑→SCK↑setup time SCK↓→SCS↓hold time SCS deselect time SCS↑→SOT delay time SCS↓→SOT delay time Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Units Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ( *2)+0 (*3)-50 +5tCYCP 3tCYCP+30 ( *2)+50 (*3)+50 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 144 of 201 S6E2C5 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 145 of 201 S6E2C5 Series High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 4tCYCP - 10 VCC ≥4.5 V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns 14 12.5* Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04984 Rev.*B Page 146 of 201 S6E2C5 Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04984 Rev.*B Page 147 of 201 S6E2C5 Series High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions VCC < 4.5 V Min Max 4tCYCP - 10 Internal shift clock operation External shift clock operation VCC ≥ 4.5 V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns 14 12.5* Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04984 Rev.*B Page 148 of 201 S6E2C5 Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK tSLSH VIH VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04984 Rev.*B Page 149 of 201 S6E2C5 Series High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx Conditions SCKx, SINx Internal shift clock operation SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5 V Min Max 4tCYCP - 10 VCC ≥ 4.5 V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns 14 12.5* External shift clock operation Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF) Document Number: 002-04984 Rev.*B Page 150 of 201 S6E2C5 Series tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK VIH VIH VIL tF * SOT VIL tSHSL tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL MS bit = 1 * Changes when writing to TDR register Document Number: 002-04984 Rev.*B Page 151 of 201 S6E2C5 Series High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx Conditions SCKx, SINx Internal shift clock operation SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5 V Min Max 4tCYCP - 10 VCC ≥ 4.5 V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns 14 12.5* External shift clock operation Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF) Document Number: 002-04984 Rev.*B Page 152 of 201 S6E2C5 Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04984 Rev.*B Page 153 of 201 S6E2C5 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Min Max Unit Max Min (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 154 of 201 S6E2C5 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 155 of 201 S6E2C5 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↑ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Min Max Unit Min Min (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 156 of 201 S6E2C5 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 157 of 201 S6E2C5 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↓ setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↓ setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 158 of 201 S6E2C5 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 159 of 201 S6E2C5 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↑ setup time tCSSE SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ( *2)+0 (*3)-20 +5tCYCP 3tCYCP+15 ( *2)+20 (*3)+20 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 40 - 40 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04984 Rev.*B Page 160 of 201 S6E2C5 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04984 Rev.*B Page 161 of 201 S6E2C5 Series External clock (EXT = 1): When in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Serial clock L pulse width Serial clock H pulse width SCK fall time SCK rise time Symbol tSLSH tSHSL tF tR Condition CL = 30 pF tR SCK VIL Document Number: 002-04984 Rev.*B Value Min tCYCP + 10 tCYCP + 10 - tSHSL VIH Max 5 5 VIL Remarks ns ns ns ns tF tSLSH VIH Unit VIL VIH Page 162 of 201 S6E2C5 Series 12.4.13 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Min Max Unit A/D converter trigger input ADTGx FRCKx Input pulse width tINH, tINL ICxx DTTIxX Remarks - 2tCYCP*1 - ns - 2tCYCP*1 2tCYCP + 100*1 - ns - ns 500*2 - ns 500*3 - ns INT00 to INT31, NMIX - WKUPx - Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see 8. Block Diagram in this data sheet. *2: When in Stop mode, in Timer mode *3: When in Deep Standby RTC mode, in Deep Standby Stop mode Document Number: 002-04984 Rev.*B Page 163 of 201 S6E2C5 Series 12.4.14 Quadrature Position/Revolution Counter Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40°C to +105°C) Value Parameter Symbol Conditions Min Max Unit AIN pin H width tAHL AIN pin L width tALL BIN pin H width tBHL BIN pin L width tBLL BIN rise time from PC_Mode2 or tAUBU AIN pin H level PC_Mode3 AIN fall time from PC_Mode2 or tBUAD BIN pin H level PC_Mode3 BIN fall time from PC_Mode2 or tADBD AIN pin L level PC_Mode3 AIN rise time from PC_Mode2 or tBDAU BIN pin L level PC_Mode3 AIN rise time from PC_Mode2 or ns 2tCYCP* tBUAU BIN pin H level PC_Mode3 BIN fall time from PC_Mode2 or tAUBD AIN pin H level PC_Mode3 AIN fall time from PC_Mode2 or tBDAD BIN pin L level PC_Mode3 BIN rise time from PC_Mode2 or tADBU AIN pin L level PC_Mode3 ZIN pin H width tZHL QCR: CGSC = 0 ZIN pin L width tZLL QCR: CGSC = 0 AIN/BIN rise and fall time tZABE QCR: CGSC = 1 from determined ZIN level Determined ZIN level from tABEZ QCR: CGSC = 1 AIN/BIN rise and fall time *: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the APB bus number to which the quadrature position/revolution counter is connected, see "8. Block Diagram" in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-04984 Rev.*B tBLL Page 164 of 201 S6E2C5 Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN Document Number: 002-04984 Rev.*B Page 165 of 201 S6E2C5 Series ZIN AIN/BIN Document Number: 002-04984 Rev.*B Page 166 of 201 S6E2C5 Series 12.4.15 I2C Timing Standard-mode, Fast-mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between "Stop condition" and "START condition" Symbol Conditions Standard-mode Min Max Fast-mode Min Max Unit fSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs tSUSTA tHDDAT CL = 30 pF, R = (Vp/IOL)*1 Remarks 2 MHz ≤ ns 2 tCYCP*4 2 tCYCP*4 tCYCP＜40 MHz 40 MHz ≤ ns 4 tCYCP*4 4 tCYCP*4 tCYCP ＜60 MHz Noise filter tSP *5 60 MHz ≤ ns 6 tCYCP*4 6 tCYCP*4 tCYCP ＜80 MHz 80 MHz ≤ ns 8 tCYCP*4 8 tCYCP*4 tCYCP ≤100 MHz *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. V p indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal. *3: Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns.” *4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see "8.Block Diagram" in this data sheet. When using Standard-mode, the peripheral bus clock must be set more than 2 MHz. When using Fast-mode, the peripheral bus clock must be set more than 8 MHz. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. Document Number: 002-04984 Rev.*B Page 167 of 201 S6E2C5 Series Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between "Stop condition" and "START condition" Symbol Conditions Fast Mode Plus (Fm+)*6 Min Max Unit fSCL 0 1000 kHz tHDSTA 0.26 - μs tLOW tHIGH tSUSTA 0.5 0.26 0.26 - μs μs μs 0 0.45*2, *3 μs tSUDAT 50 - ns tSUSTO 0.26 - μs tBUF 0.5 - μs tHDDAT CL = 30 pF, R = (Vp/IOL)*1 Remarks 60 MHz ≤ ns 6 tCYCP*4 tCYCP＜80 MHz Noise filter tSP *5 80 MHz ≤ ns 8 tCYCP*4 tCYCP ≤100 MHz *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. V p indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal. *3: The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns.” *4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see "8.Block Diagram" in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See Chapter12: I/O PORT in FM4 Family Peripheral Manual Main Part (002-04856) for the details. Document Number: 002-04984 Rev.*B Page 168 of 201 S6E2C5 Series 12.4.16 SD Card Interface Timing Default-Speed Mode  Clock CLK (All values are referenced to VIH and VIL transition points) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Clock frequency Data Transfer Mode Clock frequency Identification Mode Clock low time Clock high time Clock rise time Clock fall time Symbol Pin Name fPP S_CLK fOD S_CLK tWL tWH tTLH tTHL S_CLK S_CLK S_CLK S_CLK Value Conditions CCARD ≤ 10 pF (1card) Remarks Min Max 0 25 MHz 0/100 400 kHz 10 10 - 10 10 ns ns ns ns *: 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.  Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Input set-up time tISU Input hold time tIH Value Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD ≤ 10 pF (1card) Remarks Min Max 5 - ns 5 - ns  Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Output Delay time during Data Transfer Mode Output Delay time during Identification Mode tODLY tODLY Value Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD ≤ 40 pF (1card) Max 0 14 ns 0 50 ns tWH tWL S_CLK (SD Clock) VIH VIH VIH VIL VIL tTLH tTHL tIH tISU S_CMD, S_DATA3: 0 (Card Input) VIH VIH VIL VIL tODLY(Min) tODLY(Max) S_CMD, S_DATA3: 0 (Card Output) Remarks Min VOH VOH VOL VOL Default-Speed Mode Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. − For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part (002-04856). Document Number: 002-04984 Rev.*B Page 169 of 201 S6E2C5 Series High-Speed Mode  Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name fPP S_CLK Clock frequency Data Transfer Mode Clock low time Clock high time Clock rise time Clock fall time tWL tWH tTLH tTHL Value Conditions Max 0 50 MHz 7 7 - 3 3 ns ns ns ns CCARD ≤ 10 pF (1 card) S_CLK S_CLK S_CLK S_CLK Remarks Min  Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Input set-up time tISU Input hold time tIH Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD ≤ 10 pF (1 card) Value Remarks Min Max 6 - ns 2 - ns  Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Output delay time during data transfer mode tODLY Output hold time tOH Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CL ≤ 40 pF (1 card) CL ≥ 15 pF (1 card) Value Max 0 14 ns 2.5 - ns - 40 pF Total system capacitance CL 1 card for each line* *: In order to satisfy severe timing, host shall drive only one card. tWH tWL S_CLK (SD Clock) 50%VCC VIH VIH VIL VIL 50%VCC tODLY(Max) S_CMD, S_DATA3: 0 (Card Output) VIH tTLH tTHL tIH tISU S_CMD, S_DATA3: 0 (Card Input) Remarks Min VIH VIH VIL VIL tOH(Min) VOH VOH VOL VOL High-Speed Mode Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. − For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part (002-04856). Document Number: 002-04984 Rev.*B Page 170 of 201 S6E2C5 Series 12.4.17 ETM/ HTM Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Data hold Symbol Pin Name Conditions tETMH TRACECLK, TRACED[15: 0] VCC ≥ 4.5 V TRACECLK frequency 1/tTRACE TRACECLK clock cycle tTRACE TRACECLK VCC ＜4.5 V VCC ≥ 4.5 V VCC ＜4.5 V Value Unit Min 2 Max 9 2 15 50 32 MHz MHz Remarks ns VCC ≥ 4.5 V 20 - ns VCC ＜4.5 V 31.25 - ns Note: − When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[15: 0] Document Number: 002-04984 Rev.*B Page 171 of 201 S6E2C5 Series 12.4.18 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V VCC ＜4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V VCC ＜4.5 V VCC ≥ 4.5 V VCC ＜4.5 V Value Unit Min Max 15 - ns 15 - ns - 25 45 ns Remarks Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO Document Number: 002-04984 Rev.*B Page 172 of 201 S6E2C5 Series 12.4.19 I2S Timing Master Mode Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Output clock pulse width I2SCK→I2SWS delay time I2SCK→I2SDO delay time* I2SDI→I2SCK setup time I2SDI→I2SCK hold time Input signal rise time Symbol Pin Name Conditions fMCYC tMHW I2SCK - I2SCK - tMLW tDFS tDDO tHSDI Input signal fall time tHDI tFI tFI I2SCK, I2SWS I2SCK, I2SDO I2SCK, I2SDI I2SDI Value Unit Min 45 Max 12.288 55 MHz % 45 55 % - 0 24.0 ns - 0 24.0 ns - 25.0 - ns - 0 - ns - - 5 ns - - 5 ns Remarks *: Except for the first bit of transmission frame Notes: − When the external load capacitance CL = 20 pF − When I2SWS = 48 kHz, I2MCLK = 256 × I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details. Document Number: 002-04984 Rev.*B Page 173 of 201 S6E2C5 Series tmcyc tmhw tmlw I2SCK (CPOL=0) I2SCK (CPOL=1) tdfs I2SWS (FSPH=0, FSLN=0) tdfs tdfs tdfs I2SWS (FSPH=1, FSLN=0) tdfs tdfs I2SWS (FSPH=0, FSLN=1) tdfs tdfs I2SWS (FSPH=1, FSLN=1) tddo I2SDO tsdi thdi tsdi thdi I2SDI (SMPL=0) tsdi thdi I2SDI (SMPL=1) Note: − See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details of CPOL, FSPH, FSLIN, and SMPL. I2SDI 0.8×VCC 0.8×VCC 0.2×VCC tfi Document Number: 002-04984 Rev.*B 0.8×VCC 0.2×VCC tri Page 174 of 201 S6E2C5 Series Slave Mode Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input frequency Input clock pulse width I2SWS→I2SCK Setup time I2SWS→I2SCK Hole time I2SCK↑→I2SDO Delay time*1 I2SCK↑→I2SDO Delay time*2 I2SDI→I2SCK↓ Setup time I2SDI→I2SCK↓ Hole time Input signal rise time Symbol Pin Name Conditions fSCYC tSHW I2SCK - I2SCK - tSLW I2SCK, I2SWS I2SCK, I2SWS tSFI tHFI tDDO Value Unit Min 45 Max 12.288 55 MHz % 45 55 % - 8 - ns - 0 - ns - 0 32 ns - 0 32 ns - 8 - ns - 0 - ns - - 5 ns - - 5 ns Remarks I2SCK, I2SDO tDFB1 tSDI I2SCK, I2SDI tHDI Input signal fall time tFI tFI I2SCK, I2SWS, I2SDI *1: Except for the first bit of transmission frame *2: When FSPH bit = 1. Notes: − When the external load capacitance CL = 20 pF − When I2SWS = 48 kHz, I2MCLK = 256×I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details. Document Number: 002-04984 Rev.*B Page 175 of 201 S6E2C5 Series tscyc tshw tslw I2SCK (CPOL=0) I2SCK (CPOL=1) tsfi thfi I2SWS (FSPH=0, FSLN=0) tsfi thfi I2SWS (FSPH=1, FSLN=0) tsfi I2SWS (FSPH=0, FSLN=1) tsfi I2SWS (FSPH=1, FSLN=1) tddo tdfb1 I2SDO tsdi thdi tsdi thdi I2SDI (SMPL=0) tsdi thdi I2SDI (SMPL=1) Notes: − See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details of FSPH, FSLN, SMPL − I2SCK input is selectable polarity by CPOL bit of CNTREG register I2SCK I2SWS I2SDI 0.8×VCC 0.8×VCC 0.2×VCC tfi Document Number: 002-04984 Rev.*B 0.8×VCC 0.2×VCC tri Page 176 of 201 S6E2C5 Series I2SMCLK Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Symbol Pin Name Conditions Input frequency fCHS I2SMCK Input clock cycle tCYLHS - - - tCFS tCRS - Parameter Input clock pulse width Input clock rise time and fall time Value Unit Min Max - - 25 MHz PWHS/tCYLHS PWLS/tCYLHS 40 - ns 45 55 % - - 5 ns Remarks When using external clock When using external clock tCYLHS I2SMCLK 0.8×VCC 0.8×VCC 0.8×VCC 0.2×VCC PWHS 0.2×VCC PWLS tCFS tCRS I2SMCLK Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol Pin Name Conditions fCHS I2SMCK - Document Number: 002-04984 Rev.*B Value Min Max - 12.288 Unit Remarks MHz Page 177 of 201 S6E2C5 Series 12.4.20 High-Speed Quad SPI Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Serial clock frequency Enabled CS→ CLK Starting Time (mode0/mode2) Enabled CS→ CLK Starting Time (mode1/mode3) CLK Last→ Disabled CS Time (mode0/mode2) CLK Last→ Disabled CS Time (mode1/mode3) SIO Data output time SIO Setup Symbol tSCYCM Pin Name Q_SCK_0 Unit Remarks 66 MHz *1 - 50 MHz *2 1.5×tSCYCM - 5 - ns tSCYCM - 5 - ns tSCYCM - ns 1.5×tSCYCM - ns CL = 15 pF, VCC = 3.0 to 3.6V 0 5 ns CL = 30 pF 0 5 3 10 0.5×tSCYCM - Min Max CL = 15 pF, VCC = 3.0 to 3.6V - CL = 30 pF tOSLSK02 tOSLSK13 tOSKSL02 Q_SCK_0, Q_CS0_0, Q_CS1_0, Q_CS2_0 CL = 30 pF tOSKSL13 tOSDAT tDSSET Q_SCK_0, Q_IO0_0, Q_IO1_0, Q_IO2_0, Q_IO3_0 Value Conditions CL = 30 pF SIO Hold tSDHOLD CL = 30 pF *1: When RTM = 1 and mode = 0, 1, 3 *2: When RTM = 1 and mode = 2 or RTM = 0 and mode = 0, 1, 2, 3 ns *1 *2 ns Notes: − See Chapter8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the detail of RTM mode. − When using High-Speed Quad SPI, please set PDSR register to set the pin drive capability for VCC = 3V. See Chapter12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details. Document Number: 002-04984 Rev.*B Page 178 of 201 S6E2C5 Series Q_CS0, Q_CS1, Q_CS2 tSCYCM mode0 mode2 tOSLSK02 Q_SCK tOSKSL02 mode1 mode3 tOSKSL13 tOSLSK13 input Q_IO0, Q_IO1, Q_IO2, Q_IO3 tDSSET tSDHOLD output tOSDAT Document Number: 002-04984 Rev.*B Page 179 of 201 S6E2C5 Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Min - 4.5 - 2.5 - 15 AVRH – 15 AVCC - 15 Value Typ - Max 12 + 4.5 + 2.5 + 15 AVRH + 15 AVCC + 15 - 0.5*1 - - μs tS - 0.15 0.3 - 10 μs Compare clock cycle*3 tCCK - 25 - 1000 50 - 1000 State transition time to operation permission tSTT - - - 1.0 μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA A/D 1 unit operation - 1.3 22 μA When A/D stop Reference power supply current (AVRH) - AVRH - 1.1 1.97 mA A/D 1 unit operation AVRH = 5.5 V - 0.3 6.3 μA When A/D stop Analog input capacity CAIN - - - pF Analog input resistance RAIN - - - - - - - 12.05 1.2 1.8 4 LSB - ANxx - - 5 μA Parameter Symbol Resolution Integral nonlinearity Differential nonlinearity Zero transition voltage Full-scale transition voltage VZT Pin Name ANxx VFST ANxx Conversion time - Sampling time *2 Interchannel disparity Analog port input leak current Unit bit LSB LSB mV mV mV ns kΩ Remarks AVRH = 2.7 V to 5.5 V AVCC ≥ 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVRH V AVSS V AVSS AVCC Tcck ＜ 50 ns 4.5 AVCC AVRH V Tcck ≥ 50 ns Reference voltage 2.7 AVCC AVRL V AVSS AVSS *1: The conversion time is the value of sampling time (TS) + compare time (TC). The condition of the minimum conversion time is when the value of TS = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (TS) and compare clock cycle (TCCK). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus number to which the A/D converter is connected, see 8. Block Diagram in this data sheet. The sampling and compare clock are set at base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (TC) is the value of (Equation 2). Analog input voltage - Document Number: 002-04984 Rev.*B ANxx Page 180 of 201 S6E2C5 Series ANxx Analog input pin Rext Comparator R AIN Rin Analog signal source Cin CAIN (Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D = 1.2 kΩ at 4.5V ≤ AVCC ≤ 5.5V Input resistance of A/D = 1.8 kΩ at 2.7V ≤ AVCC < 4.5V CAIN: Input capacity of A/D = 12.05 pF at 2.7V ≤ AVCC ≤ 5.5V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-04984 Rev.*B Page 181 of 201 S6E2C5 Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVss Actual conversion characteristics AVRH AVss AVRH Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-04984 Rev.*B Page 182 of 201 S6E2C5 Series 12.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Resolution Conversion time Integral nonlinearity* Differential nonlinearity* Output voltage offset Analog output impedance - Min - Value Typ - Max 12 tC20 0.56 0.69 0.81 tC100 2.79 3.42 INL - 16 - - 0.98 - + 1.5 LSB - 20.0 3.10 2.0 3.80 - + 10 + 1.4 4.50 - mV mV kΩ MΩ 260 330 410 μs When setting 0x000 When setting 0xFFF D/A operation When D/A stop D/A 1ch operation AVCC = 3.3 V 400 510 620 μs D/A 1ch operation AVCC = 5.0 V - - 14 μs When D/A stop Symbol DNL Pin Name DAx VOFF RO IDDA Power supply current* AVCC IDSA Unit Remarks bit μs Load 20 pF 4.06 μs Load 100 pF + 16 LSB *: During no load Document Number: 002-04984 Rev.*B Page 183 of 201 S6E2C5 Series 12.7 USB Characteristics (VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V) Parameter Input characteristics Symbol Value Conditions Min Max Unit Remarks V *1 V *1 Input H level voltage VIH - 2.0 Input L level voltage Differential input sensitivity Different common mode range VIL - VSS - 0.3 USBVCC + 0.3 0.8 VDI - 0.2 - V *2 VCM - 0.8 2.5 V *2 2.8 3.6 V *3 0.0 0.3 V *3 1.3 4 4 90 28 2.0 20 20 111.11 44 V ns ns % Ω *4 *5 *5 *5 *6 Output H level voltage Output characteristics Pin Name VOH Output L level voltage VOL Crossover voltage Rise time Fall time Rise/fall time matching Output impedance VCRS tFR tFF tFRFM ZDRV UDP0/ UDM0, UDP1/ UDM1 External pull-down resistance = 15 kΩ External pull-up resistance = 1.5 kΩ Full-Speed Full-Speed Full-Speed Full-Speed Minimum differential input sensitivity [V] Rise time tLR Low-Speed 75 300 ns *7 Fall time tLF Low-Speed 75 300 ns *7 Rise/fall time matching tLRFM Low-Speed 80 125 % *7 *1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There is some hysteresis applied to lower noise sensitivity. *2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8V to 2.5V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Document Number: 002-04984 Rev.*B Page 184 of 201 S6E2C5 Series *3: The output drive capability of the driver is below 0.3 V at low state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at high state (VOH). *4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rise time (TRISE) and fall time (TFALL) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, TR/TF ratio is regulated as within ± 10% to minimize RFI emission. Rise time Document Number: 002-04984 Rev.*B Falling time Page 185 of 201 S6E2C5 Series *6: USB Full-speed connection is performed via twisted-pair cable shield with 90 Ω ± 15% characteristic impedance (differential mode). USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence.” *7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rise time Falling time Note: − See Low-Speed Load (Compliance Load) for conditions of external load. Document Number: 002-04984 Rev.*B Page 186 of 201 S6E2C5 Series Low-Speed Load (Upstream Port Load) - Reference 1 CL=50pF to 150pF CL=50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL= 200pF to 600pF CL= 200pF to 600pF Low-Speed Load (Compliance Load) CL=200pF to 450pF CL=200pF to 450pF Document Number: 002-04984 Rev.*B Page 187 of 201 S6E2C5 Series 12.8 Low-Voltage Detection Characteristics 12.8.1 Low-Voltage Detection Reset Parameter Min Value Typ Max - 2.46 2.55 2.64 V - 2.51 2.60 2.69 V Min Value Typ Max Symbol Conditions Detected voltage VDL Released voltage VDH Unit Remarks When voltage drops When voltage rises 12.8.2 Interrupt of Low-Voltage Detection Parameter Detected voltage Symbol Conditions VDL Unit 2.80 2.90 3.00 V 2.90 3.00 3.11 V 2.99 3.10 3.21 V 3.09 3.20 3.31 V 3.18 3.30 3.42 V 3.28 3.40 3.52 V 3.67 3.80 3.93 V 3.76 3.90 4.04 V 3.76 3.90 4.04 V 3.86 4.00 4.14 V 4.05 4.20 4.35 V 4.15 4.30 4.45 V 4.15 4.30 4.45 V 4.25 4.40 4.55 V 4.25 4.40 4.55 V 4.34 4.50 4.66 V - - 6000×tCYCP μs SVHI = 00111 Released voltage VDH Detected voltage VDL SVHI = 00100 Released voltage VDH Detected voltage VDL SVHI = 01100 Released voltage VDH Detected voltage VDL SVHI = 01111 Released voltage VDH Detected voltage VDL SVHI = 01110 Released voltage VDH Detected voltage VDL SVHI = 01001 Released voltage VDH Detected voltage VDL SVHI = 01000 Released voltage VDH Detected voltage VDL SVHI = 11000 Released voltage VDH LVD stabilization wait time tLVDW - * Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-04984 Rev.*B Page 188 of 201 S6E2C5 Series 12.9 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V) Parameter Large Sector Min - Value Typ Max 0.7 3.7 Unit s Includes write time prior to internal erase Sector erase time Half word (16-bit) write time Remarks Small Sector - 0.3 1.1 s Write cycles < 100 times Write cycles > 100 times - 12 100 200 μs Not including system-level overhead time - 13.6 68 s Includes write time prior to internal erase Chip erase time* *: It indicates the chip erase time of 1MB MainFlash memory For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required. See 3.2.2 Command Operating Explanations and 3.3.3 Flash Erase Operation in this product's Flash Programming Manual for the detail. Write Cycles and Data Retention Time Erase/Write Cycles (Cycle) Data Retention Time (Year) 1,000 20* 10,000 10* 100,000 5* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C). 12.10 Dual Flash Memory Write/Erase Characteristics It is the same write/erase characteristics as the MainFlash memory. See 3.6 Dual flash mode in this product's Flash Programming Manual for the detail of dual flash mode. Document Number: 002-04984 Rev.*B Page 189 of 201 S6E2C5 Series 12.11 Standby Recovery Time 12.11.1 Recovery cause: Interrupt/WKUP The time from the interrupt occurring to the time of program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Sleep mode High-speed CR Timer mode Main Timer mode PLL Timer mode Unit Max* Typ μs HCLK×1 40 80 μs Low-speed CR Timer mode 450 900 μs Sub Timer mode 896 1136 μs 316 581 μs 270 540 μs 365 667 μs 365 667 μs RTC mode Stop mode (High-speed CR/Main/PLL Run mode return) RTC mode Stop mode (Low-speed CR/sub Run mode return) tICNT Deep Standby RTC mode with RAM retention Deep Standby Stop mode with RAM retention Remarks without RAM retention with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in External Interrupt Recovery*) Ext.INT Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-04984 Rev.*B Page 190 of 201 S6E2C5 Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each low-power consumption mode. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main Part (002-04856). Document Number: 002-04984 Rev.*B Page 191 of 201 S6E2C5 Series 12.11.2 Recovery Cause: Reset The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Unit Typ Max* Sleep mode High-speed CR Timer mode Main Timer mode PLL Timer mode 155 266 μs 155 266 μs Low-speed CR Timer mode 315 567 μs 315 567 μs 315 567 μs 336 667 μs 336 667 μs Sub Timer mode tRCNT RTC mode Stop mode Deep Standby RTC mode with RAM retention Deep Standby Stop mode with RAM retention Remarks without RAM retention with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX Internal RST RST Active Release tRCNT CPU Operation Document Number: 002-04984 Rev.*B Start Page 192 of 201 S6E2C5 Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST Internal RST RST Active Release tRCNT CPU Operation Start *: Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each low power consumption mode. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main Part (002-04856). − When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-On Reset Timing. − In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock, they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock. − Internal resource reset indicates Watchdog reset and CSV reset. Document Number: 002-04984 Rev.*B Page 193 of 201 S6E2C5 Series 13. Ordering Information Part number Flash RAM Crypto S6E2C58H0AGV2000A 1 MB 128 KB N/A S6E2C59H0AGV2000A 1.5 MB 192 KB N/A S6E2C5AH0AGV2000A 2 MB 256 KB N/A S6E2C58J0AGV2000A 1 MB 128 KB N/A S6E2C59J0AGV2000A 1.5 MB 192 KB N/A S6E2C5AJ0AGV2000A 2 MB 256 KB N/A S6E2C58J0AGB1000A 1 MB 128 KB N/A S6E2C59J0AGB1000A 1.5 MB 192 KB N/A S6E2C5AJ0AGB1000A 2 MB 256 KB N/A S6E2C58L0AGL2000A 1 MB 128 KB N/A S6E2C59L0AGL2000A 1.5 MB 192 KB N/A S6E2C5AL0AGL2000A 2 MB 256 KB N/A Document Number: 002-04984 Rev.*B Package Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Page 194 of 201 S6E2C5 Series 14. Package Dimensions Package Type Package Code LQFP 144 LQS 144 4 D D1 108 4 5 7 7 5 73 109 73 72 D D1 108 109 72 E1 E 5 7 E 4 4 E1 5 7 3 3 6 144 37 1 144 37 36 1 36 BOTTOM VIEW 2 5 7 e 3 0.10 C A-B D 0.20 C A-B D b 0.08 TOP VIEW C A-B D 8 2 A 9 c A A' 0.08 C SEATING PLANE L1 0.25 L A1 10 b SECTION A-A' SIDE VIEW SYMBOL DIMENSIONS MIN. NOM. MAX. 1.70 A A1 0.00 0.20 b 0.17 c 0.09 0.22 0.27 0.20 D 22.00 BSC D1 20.00 BSC e 0.50 BSC E 22.00 BSC 20.00 BSC E1 L 0.45 0.60 0.75 L1 0.30 0.50 0.70 002-13015 ** PACKAGE OUTLINE, 144 LEAD LQFP 20.0X20.0X1.7 MM LQS144 Rev** Document Number: 002-04984 Rev.*B Page 195 of 201 S6E2C5 Series Package Type Package Code LQFP 176 LQP 176 D D1 132 4 5 7 89 133 89 88 132 133 88 E1 E 5 7 4 3 6 176 45 1 176 45 44 44 1 2 5 7 e 3 BOTTOM VIEW 0.10 C A-B D 0.20 C A-B D b 0.08 C A-B D 8 TOP VIEW 2 A 9 c A A' 0.08 C SIDE VIEW SYMBOL L1 0.25 A1 10 L b SECTION A-A' DIMENSIONS MIN. NOM. MAX. 0.05 0.15 1.70 A A1 SEATING PLANE b 0.17 c 0.09 0.22 0.20 D 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 0.27 24.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 0 8 002-15150 ** PACKAGE OUTLINE, 176 LEAD LQFP 24.0X24.0X1.7 MM LQP176 REV** Document Number: 002-04984 Rev.*B Page 196 of 201 S6E2C5 Series Package Type Package Code LQFP 216 LQQ 216 4 D 5 7 D1 162 109 1 09 108 163 1 62 108 163 E1 E 5 4 7 3 6 55 216 1 55 216 54 1 54 e 2 5 7 3 0.10 C A-B D 0.20 C A-B D b 0.07 C A-B D BOTTOM VIEW 8 TOP VIEW 2 A 9 c A A' SEATING PLANE L1 0.08 C 0.25 L A1 10 b SECTION A-A' SIDE VIEW SYMBOL DIMENSIONS MIN. NOM. MAX. 1.70 A A1 0.05 b 0.13 c 0.09 0.15 0.18 0.23 0.20 D 26.00 BSC. D1 24.00 BSC. e 0.40 BSC E 26.00 BSC. 24.00 BSC. E1 L 0.45 0.60 0.75 L1 0.30 0.50 0.70 0 8 002-15153 ** PACKAGE OUTLINE, 216 LEAD LQFP 24.0X24.0X1.7 MM LQQ216 REV** Document Number: 002-04984 Rev.*B Page 197 of 201 S6E2C5 Series Package Type Package Code PFBGA 192 LBE 192 A 0.20 C 14 2X 13 12 7 11 10 9 8 7 6 5 4 3 2 1 P PIN A1 CORNER INDEX MARK 8 N M L K J H G F E B D C B A 7 0.20 C 192xφ b 0.08 C A B 6 2X TOP VIEW BOTTOM VIEW DETAIL A 0.10 C C SIDE VIEW DETAIL A NOTES DIMENSIONS SYMBOL MIN. NOM. A A1 0.25 D 0.35 1. ALL DIMENSIONS ARE IN MILLIMETERS. 1.45 2. DIMENSIONS AND TOLERANCES METHODS PER ASME Y14.5-2009. THIS OUTLINE CONFORMS TO JEP95, SECTION 4.5. 0.45 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010. 4. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 12.00 BSC E 12.00 BSC D1 10.40 BSC E1 10.40 BSC MD 14 ME 14 n 192 b MAX. 0.35 0.45 eD 0.80 BSC eE 0.80 BSC SD / SE 0.40 BSC 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 0.55 7. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" =0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK. METALLIZED MARK INDENTATION OR OTHER MEANS. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 002-13493 ** PACKAGE OUTLINE, 192 BALL FBGA 12.00X12.00X1.45 MM LBE192 REV** Document Number: 002-04984 Rev.*B Page 198 of 201 S6E2C5 Series 15. Major Changes Spansion Publication Number: DS709-00010 Page Section Revision 0.1 Revision 1.0 7 2. Features 15 3. Product Lineup 12 2. Features 15 3. Product Lineup 90 10. Block Diagram 91 12. Memory Map 18-20 5. Pin Assignments 22-74 6. Pin Descriptions 75-82 7. I/O Circuit Type - 97-105 106-107 13. Pin Status In Each CPU State 14.1. Absolute Maximum Ratings 108-111 14.2. Recommended Operating Conditions 112-121 14.3.1. Current Rating 122-123 14.3.2. Pin Characteristics 126 14.4.5. Operating Conditions of USB PLL・ I2S PLL (in the case of using main clock for input clock of PLL) 190 14.5.12-bit A/D Converter Change Results Initial release Added that CAN-FD Interface supported non-CAN FD. Deleted HDM-CEC/Remote Control Receiver. Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1) Revised the pin name of I2S. (MI2S*_0→MI2S*0_0) Deleted the pin of IGTRG0_0. Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1) Revised the pin name of I2S. (MI2S*_0→MI2S*0_0) Revised the pin number of PF7 in LQFP216.(91→90) Revised the pin number of X1. (73, 58, 50, P5→107, 87, 71, P13) Revised the pin number of X0A. (107, 87, 71, P13→73, 58, 50, P5) Revised IOH/IOL of Type S.(IOH=-12mA→-10mA, IOL=12mA→ 10mA) Added the case of using I2C in Type E, F, G, L, N, S. Deleted X and Y in Pin Status Type. Added 10 mA type. Added AVRL in Analog reference voltage. Revised the leakage current in Maximum leakage current at operating Revised the maximum current of each category. Added the characteristic of external bus in H level input voltage (hysteresis input). Added the characteristic of 10 mA type. Revised the maximum of I2S PLL macro oscillation clock frequency. (307.2 MHz→384 MHz) Revised the minimum of Sampling time. Revised the characteristic of State transition time to operation permission Added AVRL in Analog reference voltage. Revised the SVHI values in Conditions 198 14.8.2. Interrupt of Low-Voltage Detection NOTE: Please see “Document History” about later revised information. Document Number: 002-04984 Rev.*B Page 199 of 201 S6E2C5 Series Document History Document Title: S6E2C5 Series 32-bit ARM® Cortex®-M4F, FM4 Microcontroller Document Number: 002-04984 Revision ECN ** - Orig. of Submission Change Date AKIH 04/22/2015 Description of Change New Spec. Company name and layout design change. *A 5126421 HITK 02/08/2016 Added the note of TAP pin. Updated Package Code and Dimensions (LQFP-144, LQFP-176, LQFP-216). Updated 12.4.8 Power-On Reset Timing. Changed parameter from “Power Supply rise time(tVCCR)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and add some comments. (Page 117) Modified CSIO timing typo (12.4.12 CSIO(SPI) Timing) Deleted “SPI=1, MS=0” in the titles and added MS=0,1 in the schematic (Page 138-145, 154-161) Modified RTC description(Features, Real-Time Clock (RTC) ) Deleted “second , or day of the week” in the Interrupt function.(Page.3) Modifications related to the VBAT in the following chapter. “7. Handling Devices” Notes on Power-on (Page. 78) “11. Pin Status in Each CPU State” List of VBAT Domain Pin Status (Page. 94) “12.3.1 Current Rating” Table12-9. Typical and Maximum Current Consumption in Deep Standby STOP Mode, Deep Standby RTC Mode and VBAT (Page. 109) Change the name from “USB Function” to “USB Device” (Page 1, 8, 60) Updated “14. Package dimensions “(Page 195-198)” Deleted MPNs below from “13. Ordering Information” (Page 194) *B 5634625 YSKA 02/20/2017 S6E2C58H0AGV20000, S6E2C59H0AGV20000, S6E2C5AH0AGV20000, S6E2C58J0AGV20000, S6E2C59J0AGV20000, S6E2C5AJ0AGV20000, S6E2C58J0AGB10000, S6E2C59J0AGB10000, S6E2C5AJ0AGB10000, S6E2C58L0AGL20000, S6E2C59L0AGL20000, S6E2C5AL0AGL20000 Added MPNs below to “13. Ordering Information” (Page 194) S6E2C58H0AGV2000A, S6E2C59H0AGV2000A, S6E2C5AH0AGV2000A, S6E2C58J0AGV2000A, S6E2C59J0AGV2000A, S6E2C5AJ0AGV2000A, S6E2C58J0AGB1000A, S6E2C59J0AGB1000A, S6E2C5AJ0AGB1000A, S6E2C58L0AGL2000A, S6E2C59L0AGL2000A, S6E2C5AL0AGL2000A Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12 CSIO(SPI) Timing”(Page 146-152) Modified the expression of the “Built-in CR” and add Note in the “1. Product Lineup”(Page 9) Modified typo(SCLKx_0 -> SCKx_0)(Page 130, 132, 134, 136) Added Maximum Access size in “Features”(Page 1) Updated IO circuit (type A) (Page 64) Document Number: 002-04984 Rev.*B Page 200 of 201 S6E2C5 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). 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