W144

W144 440BX AGPset Spread Spectrum Frequency Synthesizer Features • Maximized electromagnetic interference (EMI) suppression using Cypress’ Spread Spectrum technology • Single chip system frequency synthesizer for Intel® 440BX AGPset • Two copies of CPU output • Six copies of PCI output 1 • One 48-MHz output for USB • One 24-MHz output for SIO • Two buffered reference outputs • One IOAPIC output • Thirteen SDRAM outputs provide support for three DIMMs • Supports frequencies up to 150 MHz • I2C interface for programming • Power management control inputs Table 1. Pin Selectable Frequency FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Input Address CPU_F, CPU1 FS2 FS1 FS0 (MHz) PCI_F, 1:5 (MHz) 1 1 1 133.6 33.4 (CPU/4) 1 1 0 124 31 (CPU/4) 1 0 1 150 37.5 (CPU/4) 1 0 0 140 35 (CPU/4) 0 1 1 105 35 (CPU/3) 0 1 0 110 36.7 (CPU/3) 0 0 1 115 38.3 (CPU/3) 0 0 0 120 40 (CPU/3) 1 1 1 100.2 33.4 (CPU/3) 1 1 0 133.3 44.43 (CPU/3) 1 0 1 112 37.3 (CPU/3) 1 0 0 103 34.3 (CPU/3) 0 1 1 66.8 33.4 (CPU/2) 0 1 0 83.3 41.7 (CPU/2) 0 0 1 75 37.5 (CPU/2) 0 0 0 124 41.3 (CPU/3) Logic Block Diagram VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC PLL Ref Freq Pin Configuration [1] REF1/FS2 VDDQ2 IOAPIC VDDQ2 I/O Pin Control Stop Clock Control CLK_STOP# PLL 1 ÷2,3,4 Stop Clock Control CPU1 CPU_F VDDQ3 PCI_F/MODE PCI1/FS3 PCI2 PCI3 PCI4 PCI5 VDDQ3 48MHz/FS0 ÷2 Stop Clock Control SDATA SCLK I2C Logic PLL2 VDDQ3 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE **PCI1/FS3 GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDATA I2C SCLK { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC REF1/FS2* GND CPU_F CPU1 VDDQ2 CLK_STOP# SDRAM_F GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS0* 24MHz/FS1* W144 SDRAMIN Stop Clock Control 24MHz/FS1 VDDQ3 SDRAM0:11 12 SDRAM_F Note: 1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping while ** has an internal pull down resistor. Cypress Semiconductor Corporation Document #: 38-07153 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 16, 2004 W144 Pin Description Pin Name CPU_F CPU1 PCI2:5 PCI1/FS3 No. 44 43 10, 11, 12, 13 8 Type Description O Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to VDDQ2. See Tables 1 and 6 for detailed frequency information. O CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. O PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. I/O Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through serial input interface, see Tables 1 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. I/O Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 1 and 6. This output is not affected by the PCI_STOP# input. When an input, sets function of pin 2. I CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected clock outputs start, beginning with a full clock cycle (2–3 CPU clock latency). O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW. I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will be latched, which will set clock frequencies as described in Table 1. I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be latched, which will set clock frequencies as described in Table 1. I/O I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which will set clock frequencies as described in Table 1. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:11, SDRAM_F). O Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. O I I/O I Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN input which is not affected by the CLK_STOP# input Clock pin for I2C Circuitry Data pin for I2C Circuitry Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply. Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. PCI_F/MODE 7 CLK_STOP# 41 IOAPIC 48MHz/FS0 47 26 24MHz/FS1 25 REF1/FS2 46 REF0/ (PCI_STOP#) 2 SDRAMIN SDRAM0:11 15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 40 24 23 4 SDRAM_F SCLK SDATA X1 X2 VDDQ3 5 1, 6, 14, 19, 27, 30, 36 42, 48 3, 9, 16, 22, 33, 39, 45 I P VDDQ2 GND P G Document #: 38-07153 Rev. *B Page 2 of 14 W144 Key Specifications CPU Cycle-to-Cycle Jitter: ......................................... 250 ps CPU to CPU Output Skew: ........................................ 175 ps PCI to PCI Output Skew: ............................................ 500 ps VDDQ3:..................................................................... 3.3V±5% VDDQ2:..................................................................... 2.5V±5% SDRAMIN to SDRAM0:11 Delay: ......................... 3.7 ns typ. SDRAM0:11 (leads) to SDRAM_F Skew: ............. 0.4 ns typ. Table 2. Mode Input Table Mode 0 1 PCI_STOP# REF0 Pin2 nation of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-kΩ “strapping” resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W144 power up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pin and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs are