W211B

PRELIMINARY W211B FTG for 440BX, VIA Apollo Pro-133, and ProMedia Features • Maximized EMI Suppression using Cypress’s Spread Spectrum technology • Single-chip system frequency synthesizer for 440BX, VIA Apollo Pro-133, and ProMedia • Supports Intel® Pentium® II and Cyrix class processors • Two copies of CPU output • Six copies of PCI output • One 48-MHz output for USB • One 24-MHz or 48-MHz output for SIO • Two buffered reference outputs • One IOAPIC output • Thirteen SDRAM outputs provide support for 3 DIMMs • Supports frequencies up to 200 MHz • SMBus interface for programming • Power management control inputs • Available in 48-pin SSOP • SDRAM Range = 66 MHz to 133 MHz SDRAMIN to SDRAM0:12 Delay:........................4.5 – 6.0 ns Table 1. Mode Input Table Mode Pin 2 0 CPU_STOP# 1 REF0 Table 2. Pin Selectable Frequency Input Address CPU_F, PCI_F, Spread FS3 FS2 FS1 FS0 CPU1 (MHz) 1:5 (MHz) Spectrum 1 1 1 1 133.3 33.3 ±0.5% 1 1 1 0 75 37.5 OFF 1 1 0 1 100.2 33.3 ±0.5% 1 1 0 0 66.8 33.4 ±0.5% 1 0 1 1 79 39.5 OFF 1 0 1 0 110 36.7 OFF 1 0 0 1 115 38.3 OFF 1 0 0 0 120 30 OFF 0 1 1 1 133.3 33.3 –0.5% 0 1 1 0 83 27.7 OFF 0 1 0 1 100.2 33.3 –0.5% 0 1 0 0 66.8 33.4 –0.5% 0 0 1 1 122 30.5 –0.5% 0 0 1 0 129 32.3 OFF 0 0 0 1 138 34.5 OFF 0 0 0 0 95 31.7 –0.5% Key Specifications CPU Cycle-to-Cycle Jitter: .......................................... 250 ps CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew: ............................................ 500 ps VDDQ3: .................................................................... 3.3V±5% VDDQ2: .................................................................... 2.5V±5% Block Diagram X1 X2 XTAL OSC VDDQ3 REF0/(CPU_STOP#) REF1/FS0 Pin Configuration[1] VDDQ3 REF0/(CPU_STOP#) GND X1 X2 VDDQ3 PCI0/MODE PCI1/FS1* GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SMBus SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC REF1/FS0* GND CPU_F CPU1 VDDQ2 PWRDWN# SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS2* 24_48MHz/FS3^ PLL Ref Freq I/O Pin Control PWRDWN# CPU_F Stop Clock Control ÷2,3,4 W211B CPU1 PLL 1 VDDQ3 PCI0/MODE PCI1/FS1 PCI2 PCI3 PCI4 PCI5 VDDQ3 48MHz/FS2 ÷2 SDATA SCLK SMBus Logic PLL2 { SDRAMIN 13 24_48MHz/FS3 VDDQ3 SDRAM0:12 Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor. Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07174 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 25, 2001 PRELIMINARY Pin Definitions Pin Name CPU_F CPU1 PCI2:5 Pin No. 44 43 10, 11, 12, 13 Pin Type O O O Pin Description W211B Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to VDDQ2. See Table 2 and Table 6 for detailed frequency information. CPU Clock Output 1: This CPU clock output is controlled by the CPU_STOP# and PWRDWN# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial input interface, see Tables 2 and 6 for details. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs or through serial input interface. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine the function of pin 2, see Table 1 for details. PWRDWN# input: LVTTL-compatible input that places the device in power-down mode when held LOW. IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. This output is disabled when PWRDWN# is set LOW. 48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. 24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 48 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Upon power-up, FS0 input will be latched which will set clock frequencies as described in Table 2. Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined by the MODE pin. When CPU_STOP# input is asserted LOW, it will disable CPU1 output and drive it to logic 0. When this pin is configured as an output, this pin becomes a 3.3V 14.318-MHz output clock. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when PWRDWN# input is set LOW. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply. Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers, connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. Page 2 of 16 PCI1/FS1 8 I/O PCI0/MODE 7 I/O PWRDWN# IOAPIC 48MHz/FS2 41 47 26 I O I/O 24_48MHz/ FS3 25 I/O REF1/FS0 46 I/O REF0/ CPU_STOP# 2 I/O SDRAMIN SDRAM0:12 15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 I O SCLK SDATA X1 24 23 4 I I/O I X2 VDDQ3 VDDQ2 GND 5 1, 6, 14, 19, 27, 30, 36 42, 48 3, 9, 16, 22, 33, 39, 45 I P P G Document #: 38-07174 Rev. ** PRELIMINARY Overview The W211B was developed as a single-chip device to meet the clocking needs of both Intel 440BX and VIA Apollo Pro-133 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W211B adds a thirteenth output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress’s proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. W211B Upon W211B power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs is