W234

1 W234 Dual Direct Rambus™ Clock Generator Features • Differential clock source for Direct Rambus™ memory subsystem for up to 1.6-Gb/s serial data transfer rate • Provide synchronization flexibility: the Rambus® Channel can optionally be synchronous to an external system or processor clock • Power managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications • Works with Cypress CY2210-2, CY2210-3, CY2215, W133, W158, W159, W161, and W167B to support Intel® architecture platforms • Low-power CMOS design packaged in a 28-pin, 173-mil TSSOP package Overview The Cypress W234 provides dual channel differential clock signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock but can also be used in systems that do not require synchronization of the Rambus clock. Key Specifications Supply Voltage:.................................... VDD = 3.3V ± 0.165V Operating Temperature:.................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: .......................................VDD + 0.5V Maximum Input Frequency: ..................................... 100 MHz Output Duty Cycle: .................................. 40/60% worst case Output Type: ............................Rambus signaling level (RSL) Block Diagram PCLKM0 SYNCLKN0 Pin Configuration Phase Alignment Output Logic CLK0 CLK0# VDDIR REFCLK VDD SYNCLKN0 PCLKM0 GND VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 S0 S1 S2 GND CLK0# CLK0 VDD VDD CLK1 CLK1# GND MULT0 MULT1 MULT2 REFCLK MULT0:2 PLL GND SYNCLKN1 PCLKM1 VDD S0:2 Test Logic VDDIPD STOP# PWR_DWN# PCLKM1 SYNCLKN1 Phase Alignment Output Logic CLK1 CLK1# PWR_DWN# STOP# Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 7, 2001, Rev. ** W234 Pin Definitions Pin Name REFCLK PCLKM0:1 Pin No. 2 5, 10 Pin Type I I Pin Description Reference Clock Input: Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133). Phase Detector Input 0:1: The phase difference between this signal and SYNCLKN is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If the Gear Ratio Logic is not used, this pin would be connected to ground. Phase Detector Input 0:1: The phase difference between this signal and PCLKM is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If the Gear Ratio Logic is not used, this pin would be connected to ground. Clock Output Enable: When this input is driven to active LOW, it disables the differential Rambus Channel clocks. Active LOW Power-Down: When this input is driven to active LOW, it disables the differential Rambus Channel clocks and places the W234 in Power-Down mode. PLL Multiplier Select: These inputs select the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL for the input REFCLK. MULT0 0 0 0 0 1 1 1 1 MULT1 0 0 1 1 0 0 1 1 MULT2 0 1 0 1 0 1 0 1 A 4 9 6 TBD 8 16 8 TBD B 1 2 1 TBD 3 3 1 TBD SYNCLKN0:1 4, 9 I STOP# PWR_DWN# MULT 0:2 13 14 17, 16, 15 I I I CLK0, CLK0#, CLK1, CLK1# S0, S1, S2 23, 24, 20, 19 28, 27, 26 O I Complementary Output Clock: Differential Rambus Channel clock outputs. Mode Control Input: These inputs control the operating mode of the W234. S0 0 1 1 0 1 1 0 S1 0 0 1 0 0 1 1 S2 0 0 0 1 1 1 X MODE Normal Bypass Test Vendor Test A Vendor Test B Reserved Output Test (OE) VDDIR VDDIPD VDD GND 1 12 3, 7, 11, 21, 22 6, 8, 18, 25 RefV RefV P G Reference for Refclk: Voltage reference for input reference clock. Reference for Phase Detector: Voltage reference for phase detector inputs and STOP#. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. 2 W234 CY2210-2 CY2210-3 CY2215 W133 W158 W159 W161 W167B W234 Refclk PLL Phase Align D Busclk Pclk/M RMC RAC Synclk/N M Pclk N Synclk 4 DLL Gear Ratio Logic Figure 1. DDLL System Architecture DDLL System Architecture and Gear Ratio Logic Figure 1 shows the Distributed Delay Lock Loop (DDLL) system architecture, including the main system clock source, the Direct Rambus clock generator (DRCG), and the core logic that contains the Rambus Access Cell (RAC), the Rambus Memory Controller (RMC), and the Gear Ratio Logic. (This diagram abstractly represents the differential clocks as a single Busclk wire.) The purpose of the DDLL is to frequency-lock and phase-align the core logic and Rambus clocks (PCLK and SYNCLK) at the RMC/RAC boundary in order to allow data transfers without incurring additional latency. In the DDLL architecture, a PLL is used to generate the desired Busclk frequency, while a distributed loop forms a DLL to align the phase of Pclk and Synclk at the RMC/RAC boundary. The main clock source drives the system clock (Pclk) to the core logic, and also drives the reference clock (Refclk) to the DRCG. For typical Intel architecture platforms, Refclk will be half the CPU front side bus frequency. A PLL inside the DRCG multiplies Refclk to generate the desired frequency for Busclk, and Busclk is driven through a terminated transmission line (Rambus Channel). At the mid-point of the channel, the RAC senses Busclk using its own DLL for clock alignment, followed by a fixed divide-by-4 that generates Synclk. Pclk is the clock used in the memory controller (RMC) in the core logic, and Synclk is the clock used at the core logic interface of the RAC. The DDLL together with the Gear Ratio Logic enables users to exchange data directly from the Pclk domain to the Synclk domain without incurring additional latency for synchronization. In general, Pclk and Synclk can be of different frequencies, so the Gear Ratio Logic must select the appropriate M and N dividers such that the frequencies of Pclk/M and Synclk/N are equal. In one interesting example, Pclk=133 MHz, Synclk=100 MHz, and M=4 while N=3, giving Pclk/M=Synclk/N=33 MHz. This example of the clock waveforms with the Gear Ratio Logic is shown in Figure 2. The output clocks from the Gear Ratio Logic, Pclk/M, and Synclk/N, are output from the core logic and routed to the DRCG Phase Detector (φD) inputs. The routing of Pclk/M and Synclk/N must be matched in the core logic as well as on the board. After comparing the phase of Pclk/M vs. Synclk/N, the DRCG Phase Detector (φD) drives a phase aligner that adjusts the phase of the DRCG output clock, Busclk. Since everything else in the distributed loop is fixed delay, adjusting Busclk adjusts the phase of Synclk and thus the phase of Synclk/N. In this manner the distributed loop adjusts the phase of Synclk/N to match that of Pclk/M, nulling the phase error at the input of the DRCG Phase Detector (φD). When the clocks are aligned, data can be exchanged directly from the Pclk domain to the Synclk domain. Pclk Synclk Pclk/M = Synclk/N Figure 2. Gear Ratio Timing Diagram 3 W234 CY2210-2 CY2210-3 CY2215 W133 Refclk W158 W159 W161 W167B S0/S1/S2 STOP# W234 PLL Phase Align D Busclk Pclk/M RMC RAC Synclk/N M Pclk N Synclk 4 DLL Gear Ratio Logic Figure 3. DDLL Including Details of DRCG Phase Detector Signals The DRCG Phase Detector (φD) receives two inputs from the core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M and N dividers in the core logic are chosen so that the frequencies of PCLKM and SYNCLKN are identical. The Phase Detector (φD) detects the phase difference between the two input clocks, and drives the DRCG Phase Aligner to null the input phase error through the distributed loop. When the loop is locked, the input phase error between PCLKM and SYNCLKN is within the specification tERR,PD given in Table 13 after the lock time given in the State Transition Section. The Phase Detector (φD) aligns the rising edge of PCLKM to the rising edge of SYNCLKN. The duty cycle of the phase detector input clocks will be within the specification DCIN,PD given in Table 12. Because the duty cycles of the two phase detector input clocks will not necessarily be identical, the falling edges of PCLKM and SYNCLKN may not be aligned when the rising edges are aligned. The voltage levels of the PCLKM and SYNCLKN signals are determined by the controller. The pin VDDIPD is used as the voltage reference for the phase detector inputs and should be connected to the output voltage supply of the controller. In some applications, the DRCG PLL output clock will be used directly, by bypassing the Phase Aligner. If PCLKM and SYNCLKN are not used, those inputs must be grounded. Selection Logic Table 1 shows the logic for selecting the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL from the input Refclk. Divider A sets the feedback and divider B sets the prescaler, so the PLL output clock frequency is set by: PLLClk=Refclk*A/B. Table 1. PLL Divider Selection MULT0 0 0 0 0 1 1 1 1 MULT1 0 0 1 1 0 0 1 1 MULT2 0 1 0 1 0 1 0 1 8 16 8 TBD A 4 9 6 TBD 3 3 1 B 1 2 1 Table 2 shows the logic for enabling the clock outputs, using the STOP# input signal. When STOP# is HIGH, the DRCG is in its normal mode, and CLK and CLK# are complementary outputs following the Phase Aligner output (PAclk). When STOP# is LOW, the DRCG is in the Clk Stop mode, the output clock drivers are disabled (set to Hi-Z), and the CLK and CLK# settle to the DC voltage VX,STOP as given in Table 13. The level of VX,STOP is set by an external resistor network. Table 2. Clk Stop Mode Selection Mode Normal Clk Stop STOP# 1 0 CLK PACLK VX,STOP CLK# PACLK# VX,STOP Table 3 shows the logic for selecting the Bypass and Test modes. The select bits, S0, S1, and S2 control the selection of these modes. The Bypass mode brings out the full-speed PLL output clock, bypassing the Phase Aligner. The Test mode brings the REFCLK input all the way to the output, bypassing both the PLL and the Phase Aligner. In the Output Test mode (OE), both the CLK and CLK# outputs are put into a highimpedance state (Hi-Z). This can be used for component testing and for board-level testing. 4 W234 Table 3. Bypass and Test Mode Selection Mode Normal Bypass Test Vendor Test A Vendor Test B Reserved Output Test (OE) S0 S1 S2 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 X By Pclk (int.) Gnd PLLClk RefClk CLK PAClk PLLClk RefClk Hi-Z CLK# PAClk# PLLClk# RefClk# RefClk# and the corresponding M and N dividers in the gear ratio logic. The column Ratio gives the Gear Ratio as defined Pclk/Synclk (same as M and N). The column F@PD gives the divided down frequency (in MHz) at the Phase Detector (φD), where F@PD=PCLK/M=SYNCLK/N. State Transitions The clock source has three fundamental operating states. Figure 4 shows the state diagram with each transition labelled A through H. Note that the clock source output may NOT be glitch-free during state transitions. Upon powering up the device, the device can enter any state, depending on the settings of the control signals, PWR_DWN# and STOP#. In Power-Down mode, the clock source is powered down with the control signal, PWR_DWN#, equal to 0. The control signals S0, S1 and S2 must be stable before power is applied to the device, and can only be changed in Power-Down mode (PWR_DWN#=0). The reference inputs, VDDIR and VDDIPD, may remain on or may be grounded during the Power-Down mode. The control signals MULT0, MULT1, and MULT2 can be used in two ways. If they are changed during Power-Down mode, then the Power-Down transition timings determine the settling time of the DRCG. However, the MULT0, MULT1, and MULT2 control signals can also be changed during Normal mode. When the MULT control signals are “hot swapped” in this manner, the MULT transition timings determine the settling time of the DRCG. Table 4 shows the logic for selecting the Power-Down mode, using the PWR_DWN# input signal. PWR_DWN# is active LOW (enabled when 0). When PWR_DWN# is disabled, the DRCG is in its normal mode. When PWR_DWN# is enabled, the DRCG is put into a powered-off state, and the CLK and CLK# outputs are three-stated. Table 4. PWR_DWN# Mode Selection Mode Normal Power-Down PWR_DWN# 1 0 CLK PAClk GND CLK# PAClk# GND Table of Frequencies and Gear Ratios Table 5 shows several supported Pclk and Busclk frequencies, the corresponding A and B dividers required in the DRCG PLL, Table 5. Frequencies, Dividers, and Gear Ratios Pclk 67 100 100 133 133 Refclk 33 50 50 67 67 Busclk 267 300 400 267 400 Synclk 67 75 100 67 100 A 8 6 8 4 6 B 1 1 1 1 1 M 2 8 4 4 8 N 2 6 4 2 6 Ratio 1.0 1.33 1.0 2.0 1.33 F@PD 33 12.5 25 33 16.7 VDD Turn-On M L VDD Turn-On G J Test N B K Normal F A D E VDD Turn-On Clk Stop C H VDD Turn-On Power-Down Figure 4. Clock Source State Diagram 5 W234 In Clk Stop mode, the clock source is on, but the output is disabled (STOP# asserted). The VDDIPD reference input may remain on or may be grounded during the Clk Stop mode. The VDDIR reference input must remain on during the Clk Stop mode. In Normal mode, the clock source is on, and the output is enabled. Table 6 lists the control signals for each state. Table 6. Control Signals for Clock Source States State Power-Down Clk Stop Normal PWR_DWN# 0 1 1 STOP# X 0 1 Clock Source OFF ON ON Output Buffer Ground Disabled Enabled Figure 5 shows the timing diagrams for the various transitions between states, and Table 7 specifies the latencies of each state transition. Note that these transition latencies assume the following: • REFCLK input has settled and meets specification shown in Table 12. • MULT0, MULT1, MULT2, S0, S1, and S2 control signals are stable. Timing Diagrams Power-Down Exit and Entry PWR_DWN# tPOWERUP tPOWERDN CLK0/CLK0# CLK1/CLK1# Output Enable Control tON tSTOP STOP# tCLKON tCLKOFF tCLKSETL CLK0/CLK0# CLK1/CLK1# output clock clock enabled not specified and glitch free glitches may occur. clock output settled within 50 ps of the phase before disabled Figure 5. State Transition Timing Diagrams MULT0 and/or MULT1 and/or MULT2 tMULT CLK0/CLK0# CLK1/CLK1# Figure 6. Multiply Transition Timing 6 W234 Table 7. State Transition Latency Specifications Transition Latency Transition A From Power-Down To Normal Symbol tPOWERUP Max. 3 ms Description Time from PWR_DWN# to rising edge CLK/CLK# output settled (excluding tDISTLOCK) Time from PWR_DWN# rising edge until the internal PLL and clock has turned ON and settled. Time from PWR_DWN# rising edge to CLK/CLK# output settled (excluding tDISTLOCK). Time from VDD is applied and settled until CLK/CLK# output settled (excluding tDISTLOCK). Time from VDD is applied and settled until internal PLL and clock has turned ON and settled. Time from VDD is applied and settled until internal PLL and clock has turned ON and settled. Time from when MULT0, MULT1, or MULT2 changed until CLK/CLK# output resettled (excluding tDISTLOCK). Time from STOP# rising edge until CLK/CLK# provides glitch-free clock edges. Time from STOP# rising edge to CLK/CLK# output settled to within 50 ps of the phase before CLK/CLK# was disabled. Time from STOP# falling edge to CLK/CLK# output disabled. Time from when S0, S1, or S2 is changed until CLK/CLK# output has resettled (excluding tDISTLOCK). Time from when S0, S1, or S2 is changed until CLK/CLK# output has resettled (excluding tDISTLOCK). Time from PWR_DWN# falling edge to the device in PWR_DWN#. C Power-Down Clk Stop tPOWERUP 3 ms K Power-Down Test tPOWERUP 3 ms G VDD ON Normal tPOWERUP 3 ms H VDD ON Clk Stop tPOWERUP 3 ms M VDD ON Test tPOWERUP 3 ms J Normal Normal tMULT 1 ms E E Clk Stop Clk Stop Normal Normal tCLKON tCLKSETL 10 ns 20 cycles F L Normal Test Clk Stop Normal tCLKOFF tCTL 5 ns 3 ms N Normal Test tCTL 3 ms B,D Normal or Clk Stop PWR_DWN# tPOWERDN 1 ms Figure 5 shows that the CLK Stop to Normal transition goes through three phases. During tCLKON, the clock output is not specified and can have glitches. For tCLKON