19-5359; Rev 11/10
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
GENERAL DESCRIPTION
FEATURES
The 71M6511 is a highly integrated SOC with an MPU core, RTC, flash,
and LCD driver. Our Single Converter Technology® with a 22-bit deltasigma ADC, three analog inputs, digital temperature compensation,
precision voltage reference, and 32-bit computation engine (CE) supports a
wide range of single-phase metering applications with very few low cost
external components. A 32kHz crystal time base for the entire system and
internal battery backup support for RAM and RTC further reduce system
cost.
Wh accuracy < 0.1% over 2000:1
range
Exceeds IEC 62053/ANSIC 12.20
Voltage reference
< 10ppm/°C -- 71M6511H,
< 50ppm/°C -- 71M6511
Three sensor inputs - VDD referenced
Low jitter Wh/VARh pulse outputs
Pulse count for pulse outputs
Four-quadrant metering
Voltage/current angle
Line frequency count for RTC
Digital temperature compensation
Sag detection
Independent 32-bit compute engine
40-70Hz line frequency range with
same calibration
Phase compensation (±7°)
Battery backup for RAM and RTC
22mW at 3.3V, 7.2µW backup
Flash memory option with security
22-bit delta-sigma ADC
8-bit MPU (80515) - 1 clock cycle per
instruction
LCD driver (≤ 128 pixels)
High speed SSI serial output
RTC for time-of-use functions
Hardware watchdog timer
Up to 12 general-purpose I/O pins
64KB flash, 7KB RAM
Two UARTs for IR and AMR
64-lead LQFP package
2
Maximum design flexibility is supported with multiple UARTs, I C, a power
fail comparator, a 5V LCD charge pump, up to 12 DIO pins and an insystem programmable flash. The device is offered in high (0.1%) and
standard
(0.5%)
accuracy
versions
for
multifunction
residential/commercial
meter
applications
requiring
multiple
voltage/current inputs and complex LCD or DIO configurations.
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of meters that
meet most demanding worldwide electricity metering standards.
LIVE
CT/SHUNT
POWER SUPPLY
LOAD
NEUT
CONVERTER
V3.3A V3.3D GNDA GNDD
IA
5V BOOST
VA
V or I
TERIDIAN
71M6511
IB
VDRV
REGULATOR
VBAT
BATTERY
V2.5
VOLTAGE REF
TEMP
SENSOR
VREF
RAM
VBIAS
SERIAL PORTS
AMR
IR
TX
VLCD
COM0..3
3V/5V LCD
FLASH
SEG0..19
SEG 24..32
DIO 0..11
88.88.8888
COMPUTE
ENGINE
SEG 32..41
DIO 12..21
EEPROM
RX
SENSE
DRIVE
RX
TX
COMPARATOR
POWER
FAULT
LCD DRIVER
DIO, PULSE
V1
OSC/PLL
XIN
32 kHz
XOUT
MPU
TEST PULSES
RTC
TIMERS
ICE
7/20/2007
Single Converter Technology is a registered trademark of
Maxim Integrated Products, Inc.
Page: 1 of 98
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
Table of Contents
GENERAL DESCRIPTION..................................................................................................................................... 1
FEATURES ............................................................................................................................................. 1
HARDWARE DESCRIPTION ................................................................................................................................. 8
Hardware Overview .................................................................................................................................. 8
Analog Front End (AFE) ........................................................................................................................... 8
Multiplexer.................................................................................................................................. 8
ADC ........................................................................................................................................... 9
FIR Filter .................................................................................................................................... 9
Voltage Reference ...................................................................................................................... 9
Temperature Sensor ................................................................................................................... 10
Functional Description ................................................................................................................ 10
Computation Engine (CE) ......................................................................................................................... 11
Meter Equations ......................................................................................................................... 12
Pulse Generator ......................................................................................................................... 12
Real-Time Monitor ...................................................................................................................... 13
CE Functional Overview ............................................................................................................. 13
80515 MPU Core ..................................................................................................................................... 15
80515 Overview ......................................................................................................................... 15
Memory Organization ................................................................................................................. 15
Special Function Registers (SFRs) .............................................................................................. 17
Special Function Registers (Generic 80515 SFRs) ...................................................................... 18
Special Function Registers Specific to the 71M6511 .................................................................... 20
Instruction Set ............................................................................................................................ 21
UART ......................................................................................................................................... 21
Timers and Counters .................................................................................................................. 24
WD Timer (Software Watchdog Timer) ........................................................................................ 26
Interrupts.................................................................................................................................... 29
External Interrupts ...................................................................................................................... 32
Interrupt Priority Level Structure .................................................................................................. 34
Interrupt Sources and Vectors..................................................................................................... 35
On-Chip Resources.................................................................................................................................. 37
DIO Ports ................................................................................................................................... 37
Physical Memory ........................................................................................................................ 38
Oscillator .................................................................................................................................... 39
Real-Time Clock (RTC)............................................................................................................... 40
LCD Drivers ............................................................................................................................... 40
LCD Voltage Boost Circuitry........................................................................................................ 41
UART (UART0) and Optical Port (UART1)................................................................................... 41
Hardware Reset Mechanisms ..................................................................................................... 42
Reset Pin (RESETZ)................................................................................................................... 42
Hardware Watchdog Timer ......................................................................................................... 42
Crystal Frequency Monitor .......................................................................................................... 42
V1 Pin ........................................................................................................................................ 42
I2C Interface (EEPROM) ............................................................................................................ 43
Internal Clocks and Clock Dividers .............................................................................................. 44
Battery ....................................................................................................................................... 44
Internal Voltages (VBIAS, VBAT, V2P5) ...................................................................................... 44
Test Ports .................................................................................................................................. 44
Page: 2 of 98
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
FUNCTIONAL DESCRIPTION ............................................................................................................................... 47
Theory of Operation ................................................................................................................................. 47
System Timing Summary.......................................................................................................................... 47
Data Flow ................................................................................................................................................ 50
CE/MPU Communication.......................................................................................................................... 50
Fault, Reset, Power-Up ............................................................................................................................ 51
Battery Operation ..................................................................................................................................... 52
Power Save Modes .................................................................................................................................. 52
Temperature Compensation ..................................................................................................................... 53
Chopping Circuitry.................................................................................................................................... 53
Internal/External Pulse Generation and Pulse Counting ............................................................................. 55
Program Security ..................................................................................................................................... 56
FIRMWARE INTERFACE ...................................................................................................................................... 57
I/O RAM MAP – In Numerical Order .......................................................................................................... 57
SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order ........................................................ 58
I/O RAM (Configuration RAM) – Alphabetical Order................................................................................... 59
CE Program and Environment .................................................................................................................. 65
CE Program ............................................................................................................................... 65
Formats...................................................................................................................................... 65
Constants................................................................................................................................... 65
Environment ............................................................................................................................... 66
CE Calculations.......................................................................................................................... 66
CE RAM Locations ................................................................................................................................... 67
CE Front End Data (Raw Data) ................................................................................................... 67
CE Status Word.......................................................................................................................... 67
CE Transfer Variables ................................................................................................................ 68
TYPICAL PERFORMANCE DATA.......................................................................................................................... 75
Wh Accuracy at Room Temperature ......................................................................................................... 75
VARh Accuracy at Room Temperature ..................................................................................................... 75
Harmonic Performance............................................................................................................................. 76
Meter Accuracy over Temperature (71M6511H) ........................................................................................ 76
APPLICATION INFORMATION .............................................................................................................................. 77
Connection of Sensors (CT, Resistive Shunt, Rogowski Coil) .................................................................... 77
Distinction between 71M6511 and 71M6511H Parts.................................................................................. 77
Temperature Compensation and Mains Frequency Stabilization for the RTC.............................................. 78
External Temperature Compensation........................................................................................................ 79
Temperature Measurement ...................................................................................................................... 79
Connecting LCDs ..................................................................................................................................... 80
Connecting I2C EEPROMs....................................................................................................................... 82
Connecting 5V Devices ............................................................................................................................ 82
Optical Interface ....................................................................................................................................... 83
Connecting V1 and Reset Pins ................................................................................................................. 83
Flash Programming .................................................................................................................................. 84
MPU Firmware Library.............................................................................................................................. 84
SPECIFICATIONS ................................................................................................................................................. 85
Electrical Specifications ............................................................................................................................ 85
LOGIC LEVELS.......................................................................................................................... 86
VREF, VBIAS ............................................................................................................................. 88
CRYSTAL OSCILLATOR............................................................................................................ 88
LCD BOOST .............................................................................................................................. 90
LCD DRIVERS ........................................................................................................................... 90
RTC ........................................................................................................................................... 90
Page: 3 of 98
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
RESETZ..................................................................................................................................... 90
COMPARATORS ....................................................................................................................... 90
RAM AND FLASH MEMORY ...................................................................................................... 91
FLASH MEMORY TIMING .......................................................................................................... 91
EEPROM INTERFACE ............................................................................................................... 91
Recommended External Components ....................................................................................................... 91
Packaging Information.............................................................................................................................. 92
Pinout (Top View) ....................................................................................................................... 93
Pin Descriptions ......................................................................................................................... 94
I/O Equivalent Circuits: ............................................................................................................... 96
ORDERING INFORMATION .................................................................................................................... 97
Figures
Figure 1: IC Functional Block Diagram .......................................................................................................................... 7
Figure 2: General Topology of a Chopped Amplifier ..................................................................................................... 10
Figure 3: AFE Block Diagram...................................................................................................................................... 11
Figure 4: Samples in Multiplexer Cycle ....................................................................................................................... 13
Figure 5: Accumulation Interval.................................................................................................................................. 13
Figure 6: Memory Map .............................................................................................................................................. 15
Figure 7: Interrupt Structure ...................................................................................................................................... 36
Figure 8: DIO Ports Block Diagram ............................................................................................................................. 37
Figure 9: Oscillator Circuit ......................................................................................................................................... 40
Figure 10: LCD Voltage Boost Circuitry....................................................................................................................... 41
Figure 11: Voltage Range for V1 ................................................................................................................................ 43
Figure 12: Voltage. Current, Momentary and Accumulated Energy................................................................................ 47
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers ................................................................ 48
Figure 14: RTM Output Format .................................................................................................................................. 49
Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ............................................................................................ 49
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY) ................................................................. 49
Figure 17: MPU/CE Data Flow .................................................................................................................................... 50
Figure 18: MPU/CE Communication (Functional)......................................................................................................... 51
Figure 19: MPU/CE Communication (Processing Sequence) ........................................................................................ 51
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up................................................. 52
Figure 21: Chop Polarity w/ Automatic Chopping ........................................................................................................ 54
Figure 22: Sequence with Alternate Multiplexer Cycles ................................................................................................ 54
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping........................................................... 55
Figure 24: Wh Accuracy, 0.3A - 200A/240V ................................................................................................................ 75
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance ................................................................................... 75
Figure 27: Meter Accuracy over Harmonics at 240V, 30A ............................................................................................ 76
Figure 29: Resistive Voltage Divider (left), Current Transformer (right) ......................................................................... 77
Figure 30: Resistive Shunt (left), Rogowski Coil (right) ............................................................................................... 77
Figure 31: Crystal Frequency over Temperature .......................................................................................................... 78
Figure 32: Crystal Compensation ............................................................................................................................... 79
Figure 33: Connecting LCDs ...................................................................................................................................... 80
Figure 34: LCD Boost Circuit...................................................................................................................................... 81
Figure 35: EEPROM Connection ................................................................................................................................. 82
Figure 36: Interfacing RX to a 0-5V Signal .................................................................................................................. 82
Figure 37: Connection for Optical Components ........................................................................................................... 83
Figure 38: Voltage Divider for V1 ............................................................................................................................... 83
Figure 39: External Components for RESETZ .............................................................................................................. 84
Page: 4 of 98
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles .............................................................................. 8
Table 2: Channel control based on MUX_DIV and FIR_LEN ........................................................................................ 9
Table 3: CE DRAM Locations for ADC Results............................................................................................................. 12
Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation) .................................. 12
Table 5: Stretch Memory Cycle Width......................................................................................................................... 16
Table 6: Internal Data Memory Map ........................................................................................................................... 17
Table 7: Special Function Registers Locations............................................................................................................. 17
Table 8: Special Function Registers Reset Values ........................................................................................................ 18
Table 9: PSW Register Flags ...................................................................................................................................... 19
Table 10: PSW bit functions ...................................................................................................................................... 19
Table 11: Port Registers ............................................................................................................................................ 20
Table 12: Special Function Registers .......................................................................................................................... 21
Table 13: Baud Rate Generation ................................................................................................................................. 22
Table 14: UART Modes.............................................................................................................................................. 22
Table 15: The S0CON Register ................................................................................................................................... 22
Table 16: The S1CON register .................................................................................................................................... 23
Table 17: The S0CON Bit Functions ............................................................................................................................ 23
Table 18: The S1CON Bit Functions ............................................................................................................................ 24
Table 19: The TMOD Register .................................................................................................................................... 24
Table 20: TMOD Register Bit Description .................................................................................................................... 25
Table 21: Timers/Counters Mode Description ............................................................................................................. 25
Table 22: The TCON Register ..................................................................................................................................... 25
Table 23: The TCON Register Bit Functions ................................................................................................................. 26
Table 24: Timer Modes.............................................................................................................................................. 26
Table 25: The PCON Register ..................................................................................................................................... 26
Table 26: The IEN0 Register (see also Table 34) ......................................................................................................... 27
Table 27: The IEN0 Bit Functions (see also Table 34)................................................................................................... 27
Table 28: The IEN1 Register (see also Tables 35/36) ................................................................................................... 27
Table 29: The IEN1 Bit Functions (see also Tables 35/36) ............................................................................................ 27
Table 30: The IP0 Register (see also Table 46)............................................................................................................ 28
Table 31: The IP0 bit Functions (see also Table 46) ..................................................................................................... 28
Table 32: The WDTREL Register ................................................................................................................................ 28
Table 33: The WDTREL Bit Functions ......................................................................................................................... 28
Table 34: The IEN0 Register ...................................................................................................................................... 29
Table 35: The IEN0 Bit Functions ............................................................................................................................... 30
Table 36: The IEN1 Register ...................................................................................................................................... 31
Table 37: The IEN1 Bit Functions ............................................................................................................................... 31
Table 38: The IEN2 Register ...................................................................................................................................... 31
Table 39: The IEN2 Bit Functions ............................................................................................................................... 31
Table 40: The TCON Register ..................................................................................................................................... 32
Table 41: The TCON Bit Functions .............................................................................................................................. 32
Table 42: The IRCON Register.................................................................................................................................... 32
Table 43: The IRCON Bit Functions............................................................................................................................. 32
Table 44: External MPU Interrupts ............................................................................................................................. 33
Table 45: Control Bits for External Interrupts .............................................................................................................. 33
Table 46: Priority Level Groups .................................................................................................................................. 34
Table 47: The IP0 Register:........................................................................................................................................ 34
Table 48: The IP1 Register:........................................................................................................................................ 34
Page: 5 of 98
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V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
Table 49: Priority Levels ............................................................................................................................................ 34
Table 50: Interrupt Polling Sequence .......................................................................................................................... 35
Table 51: Interrupt Vectors ........................................................................................................................................ 35
Table 52: Data/Direction Registers and Internal Resources for DIO Pin Groups ............................................................. 37
Table 53: DIO_DIR Control Bit.................................................................................................................................. 38
Table 54: Selectable Controls using the DIO_DIR Bits................................................................................................ 38
Table 55: MPU Data Memory Map.............................................................................................................................. 38
Table 56: Liquid Crystal Display Segment Table (Typical) ............................................................................................ 41
Table 57: EECTRL Status Bits................................................................................................................................... 44
Table 58: TMUX[3:0] Selections ............................................................................................................................... 45
Table 59: SSI Pin Assignment .................................................................................................................................... 46
Table 60: Power Saving Measures ............................................................................................................................. 52
Table 61: CHOP_EN Bits.......................................................................................................................................... 53
Table 62: Frequency over Temperature ....................................................................................................................... 78
Page: 6 of 98
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
VREF VBIAS
IA
VA
IB
V3P3A
GNDA
GNDA
∆Σ ADC
CONVERTER
VBIAS
VOLTAGE
BOOST
MUX
VDRV
-
V3P3A
FIR
FILTER
+
LCD_IBST
LCD_BSTEN
VREF
TEMP
VREF
CHOP_EN
VREF_DIS
MUX
GNDD
FIR_LEN
MUX
CTRL
CK32
VOLT
REG
EQU
MUX_ALT
MUX_DIV
V3P3D
VBAT
XIN
XOUT
0.1V
MCK
PLL
RTCLK (32KHz)
OSC
(32KHz)
GNDD
OSC_DIS
V2P5
CK_EN
CKTEST
4.9MHz
V2P5
2.5V to logic
CKFIR
4.9MHz
VLCD
CKOUT_EN
CK_GEN
CE RAM
(1KB)
CK_2X
ECK_DIS
MPU_DIV
SSI
CKMPU_2X
MUX_SYNC
WPULSE
VARPULSE
STRT
CKCE
CE
LCD DISPLAY
DRIVER
DATA
00-FF
32-bit Compute
Engine
TEST
MUX
RTM
=1
TI0
IEN1.4
EEPROM/
I2C
IP1.3/
IP0.3
INT5
IP1.4/
IP0.4
IRCON.4
IEN1.5
INT6
IRCON.5
IP1.5/
IP0.5
XFER_BUSY
>=1
RTC_1S
Figure 7: Interrupt Structure
Page: 36 of 98
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
On-Chip Resources
DIO Ports
The 71M6511/6511H includes up to 12 pins of general purpose digital I/O. These pins are dual function and can alternatively
be used as LCD drivers. Figure 8 shows a block diagram of the DIO section.
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction. The pins are configured and
controlled by the DIO and DIO_DIR registers (SFRs) and by the five bits of the I/O register LCD_NUM (0x2020[4:0]). See the
description for LCD_NUM in the I/O RAM Section for a table listing the available segment pins versus DIO pins, depending on
the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general
purpose pins to be LCD segment pins, starting at the higher pin numbers.
LCD DISPLAY
DRIVER
COM0..3
SEG0..SEG2
SEG8..SEG19
LCD_NUM
LCD_MODE
LCD_CLK
LCD_EN
DIGITAL I/O
DIO_EEX
PULSEV/W
DIO_IN
DIO_OUT
LCD_NUM
DIO_GP
SEG24/DIO4 ...
SEG31/DIO11
SEG34/DIO14 ...
SEG37/DIO17
SEG3/SCLK
SEG4/SSDATA
SEG5/SFR
SEG6/SRDY
SEG7/
MUX_SYNC
Figure 8: DIO Ports Block Diagram
Each pin declared as DIO can be configured independently as an input or output with the bits of the DIO_DIRn registers. Table
52 lists the direction registers and configurability associated with each group of DIO pins. Table 53 shows the configuration for
a DIO pin through its associated bit in its DIO_DIR register.
DIO
Pin number
Data Register bit
Direction Register
bit
Internal Resources
Configurable
DIO
Pin number
Data Register bit
Direction Register
bit
Internal Resources
Configurable
16
22
0
0
N
0
-----
1
---
2
3
4
5
6
--37 38 39
--4
5
6
DIO0=P0 (SFR 0x80)
---4
5
6
DIO_DIR0 (SFR 0xA2)
7
40
7
8
41
0
9
42
1
7
0
1
--
Y
Y
Y
--
--
Y
Y
17
12
1
Y
18 19 20 21 22
----------DIO2=P2 (SFR 0xA0)
1
-----DIO_DIR2 (SFR 0xA1)
23
---
N
--
--
--
--
--
--
10 11 12 13 14
43 44
--20
2
3
--6
DIO1=P1 (SFR 0x90)
2
3
--6
DIO_DIR1 (SFR 0x91)
Y
Y
--
--
N
15
21
7
7
N
--
Table 52: Data/Direction Registers and Internal Resources for DIO Pin Groups
Page: 37 of 98
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V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
DIO_DIR bit
0
1
DIO Pin Function
input
output
Table 53: DIO_DIR Control Bit
Values read from and written into the DIO ports use the data registers P0, P1 and P2.
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when
configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 52 for DIO pins
available for this option). This way, DIO pins can be tracked even if they are configured as outputs. This feature is useful for
pulse counting. The control resources selectable for the DIO pins are listed in Table 54. If more than one input is connected to
the same resource, the resources are combined using a logical OR.
DIO_R
Value
Resource Selected for DIO Pin
0
NONE
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0 rising)
5
Low priority I/O interrupt (INT1 rising)
6
High priority I/O interrupt (INT0 falling)
7
Low priority I/O interrupt (INT1 falling)
Table 54: Selectable Controls using the DIO_DIR Bits
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6,
VARPULSE = DIO7) using the I/O RAM registers DIO_PW (0x2008[2]) and DIO_PV (0x2008[3]). In this case, DIO6 and DIO7
are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface by setting the I/O RAM register
DIO_EEX (0x2008[4]).
Physical Memory
Data bus address space is allocated to on-chip memory as shown in Table 55.
Address
(hex)
Memory
Technology
Memory Type
0000-FFFF
Flash Memory
Non-volatile
0000-07FF
1000-13FF
Static RAM
Static RAM
Battery-buffered
Volatile
2000-20FF
Static RAM
Volatile
3000-3FFF
Static RAM
Volatile
Typical Usage
Program and non-volatile
data
MPU data
CE data
Configuration RAM
(I/O RAM)
CE Program code
Wait States
(at 5MHz)
Memory Size
(bytes)
0
64KB
0
5
2KB
1KB
0
256
5
4KB
Table 55: MPU Data Memory Map
Flash Memory: The 71M6511 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU
program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations.
Page: 38 of 98
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Single-Phase Energy Meter IC
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The I/O RAM bit register FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw,
this bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
1.
2.
Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
Write pattern 0xAA to FLSH_ERASE (SFR address 0x94)
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1.
2.
Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]
Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)
Writing to flash memory:
The MPU may write to the flash memory for non-volatile data storage or when implementing a boot-loader. The I/O RAM
register FLSH_PWE (flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A)
between flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL =1. After the write
operation, FLSH_PWE must be cleared.
The original state of a flash byte is 0xFF (all bits are 1). Overwriting programmed flash cells with a different value usually requires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a
page erase. After this, the page can be updated in RAM and then written back to the flash memory.
Writing to flash locations will affect the corresponding XRAM cells, i.e. 0x2000 to 0x20FF (I/O RAM), 0x0000 to
0x07FF (MPU RAM), plus CE DRAM and CE PRAM. It is critical to maintain the integrity of the cells 0x2000…0x2007
as a minimum (where important system settings are stored) during the flash-write operation. This can be achieved by
excluding the critical addresses from the write operation.
MPU RAM: The 71M6511 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256bytes of internal RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.
CE DRAM: The CE DRAM is the data memory of the CE. The MPU can read and write the CE DRAM as the primary means of
data communication between the two processors.
CE PRAM: The CE PRAM is the program memory of the CE. The CE PRAM has to be loaded with CE code before the CE
starts operating. CE PRAM cannot be accessed by the MPU when the CE is running.
Oscillator
The oscillator drives a standard 32.768kHz watch crystal (see Figure 9). Crystals of this type are accurate and do not require a
high current oscillator circuit. The oscillator in the TERIDIAN 71M6511 Power Meter IC has been designed specifically to
handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power
dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT pin.
Page: 39 of 98
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71M651X
XIN
crystal
XOUT
Figure 9: Oscillator Circuit
The oscillator should be placed as close as possible to the IC, and vias should be avoided. An external resistor
across the crystal must not be added.
Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. In the absence of the 3.3V supply, the RTC is powered by the external
battery (VBAT pin). The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes,
hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own
output register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the
RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the
same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU
clock speed, RTC reads require one wait state.
The RTC interrupt must be enabled using the I/O RAM register EX_RTC (address 0x2002[1]). RTC time is set by writing to the
I/O RAM registers RTC_SEC, RTC_MIN, through RTC_YR. Each byte written to RTC must be delayed at least 3 CK32 cycles
from any previous byte written to RTC.
Two time correction bits, the I/O RAM registers RTC_DEC_SEC (0x201C[1]) and RTC_INC_SEC (0x201C[0]) are provided to
adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second
at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can
integrate temperature and correct the RTC time as necessary as discussed in temperature compensation.
LCD Drivers
The 71M6511 contains 15 dedicated LCD segment pins, 5 LCD segment pins that rare shared with the SSI port and/or other
functions, and an additional 12 multi-purpose pins (LCD/DIO) that may be configured as LCD segment drivers (see I/O RAM
register LCD_NUM). Thus, the 71M6511/6511H is capable of driving between 80 to 128 pixels of LCD display with 25% duty
cycle. At seven segments per digit, the LCD can be designed for 11 to 18 digits for display. Since each pixel is addressed
individually, the LCD display can be a combination of alphanumeric digits and enunciator symbols. The information to be
displayed is written into the lower four bits of I/O RAM registers LCD_SEG0 through LCD_SEG37. Bit 0 corresponds to the
segment selected when COM0 pin is active while bit 1 is allocated to COM1.
The LCD driver circuitry is grouped into four common outputs (COM0 to COM3) and up to 32 segment outputs (see Table 56).
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Dedicated Segment Pins
Shared w/ DIO4-DIO11
Shared w/ DIO14-DIO17
SEG0
SEG1
…
SEG19
SEG24
…
SEG31
SEG34
…
SEG37
COM0
P0
P4
…
P76
P80
…
P108
P112
…
P124
COM1
P1
P5
…
P77
P81
…
P109
P113
...
P125
COM2
P2
P6
…
P78
P82
…
P110
P114
…
P126
COM3
P3
P7
…
P79
P83
…
P111
P115
…
P127
Table 56: Liquid Crystal Display Segment Table (Typical)
Note: P0, P1, … Represent the pixel/segment numbers on the LCD.
A charge pump suitable for driving VLCD is included on-chip. This circuit creates 5V from the 3.3V supply. A contrast DAC is
provided that permits the LCD full-scale voltage to be adjusted between VLCD and 70% of VLCD. The LCD_NUM register
defines the number of dual purpose pins used for LCD segment interface.
LCD Voltage Boost Circuitry
A voltage boost circuit may be used to generate 5V from the 3.3V supply to support low-power 5V devices, such as LCDs.
Figure 10 shows a block diagram of the voltage boost circuitry including the voltage regulators for V2P5 and V2P5NV. When
activated using the I/O RAM register LCD_BSTEN (0x2020[7]), the boost circuitry provides an AC voltage at the VDRV output
pin (see the Applications section for details).
VOLTAGE
BOOST
VDRV
LCD_IBST
LCD_BSTEN
GNDD
V2P5NV
GNDD
V3P3D
VOLT
REG
V3P3D
VBAT
0.1V
GNDD
GNDD
V2P5
V2P5
VLCD
Figure 10: LCD Voltage Boost Circuitry
UART (UART0) and Optical Port (UART1)
The 71M6511/6511H includes an interface to implement an IR or optical port. The pin OPT_TX is designed to directly drive an
external LED for transmitting data on an optical link (low-active). The pin OPT_RX, also low-active, is designed to sense the
input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated
UART port. OPT_TX can be tristated if it is desired to multiplex another I/O pin to the OPT_TX output. The control bit for the
OPT_TX output is the I/O RAM register OPT_TXDIS (0x2008[5]).
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Hardware Reset Mechanisms
Several conditions will cause a hardware reset of the 71M6511/6511H:
•
•
•
•
•
Voltage at the RESETZ pin low
Voltage at the E_RST pin low
Voltage at the V1 pin below reset threshold (VBIAS)
The crystal frequency monitor detected a crystal malfunction
Hardware Watchdog timer
Reset Pin (RESETZ)
When the RESETZ pin is pulled low (or when V1 < VBIAS), all digital activity in the chip stops while analog circuits are still
active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared.
Hardware Watchdog Timer
In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware
watchdog timer (WDT) is included in the 71M6511/6511H. This timer will reset the MPU if it is not refreshed periodically, and
can be used to recover the MPU in situations where program control is lost.
The watchdog timer uses the RTC crystal oscillator as its time base and requires a reset under MPU program control at least
every 1.5 seconds. When the WDT overflow occurs, the MPU is momentarily reset as if RESETZ were pulled low for half of a
crystal oscillator cycle. Thus, after 4100 cycles of the CK32 (32768Hz clock), the MPU program will be launched from address
00.
An I/O RAM register status bit, WD_OVF (0x2002[2]), is set when WDT overflow occurs. This bit is powered by the VBAT
pin and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power up. After
reading this bit, MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESETZ pin.
The watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, WD_OVF is set and a
system reset will be performed when the crystal oscillator resumes.
There is no internal digital state that deactivates the WDT. For debug purposes, however, the WDT can be disabled by tying
the V1 pin to V3P3 (see Figure 11 and WD Disable Threshold [V1-V3P3A] in the Comparator Section of the Electrical
Specifications). Of course, this also deactivates the power fault detection implemented with V1. Since there is no way in firmware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the MPU might find itself in, it will be
reset to a known state upon watchdog timer overflow.
In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when
WAKE=0 and, during development, when a 0x14 command is received from the ICE port.
Crystal Frequency Monitor
The hardware watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, the I/O RAM
register WD_OVF is set and a system reset will be performed when the crystal oscillator resumes.
V1 Pin
The comparator at the V1 pin controls the state of the digital circuitry on the chip. When V1 < VBIAS (or when the RESTZ pin
is pulled low), all digital activity in the chip stops while analog circuits including the oscillator and RTC module are still active.
Additionally, when V1 < VBIAS, all I/O RAM bits are cleared. As long as V1 is greater than VBIAS, the internal 2.5V regulator
will continue to provide power to the digital section.
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V1
V3P3
V3P3-10mV
WDT disabled
V3P3 400mV
Normal
operation,
WDT
enabled
when
(V1 < VBIAS)
the battery is
enabled
VBIAS
Battery or
reset
mode
0V
Figure 11: Voltage Range for V1
I2C Interface (EEPROM)
A dedicated 2-pin serial interface implements an I2C driver that can be used to communicate with external EEPROM devices.
The interface can be multiplexed onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM register DIO_EEX
(0x2008[4]). The MPU communicates with the interface through two SFR registers: EEDATA (0x9E) and EECTRL (0x9F). If the
MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL.
The write to EECTRL initiates the transmit sequence. By observing the BUSY bit in EECTRL the MPU can determine when the
transmit operation is finished (i.e. when the BUSY bit transitions from 1 to 0). INT5 is also asserted when BUSY falls. The MPU
can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the ‘Receive’ command to EECTRL and waiting for BUSY to fall. Upon completion, the received data
will appear in EEDATA.
The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state until the next
transmission. The bits in EECTRL are shown in Table 57.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. However, controlling DIO4 and
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process
interrupts.
2
Note: Clock stretching and multi-master operation is not supported for the I C interface.
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Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7
ERROR
R
0
Positive
1 when an illegal command is received.
6
BUSY
R
0
Positive
1 when serial data bus is busy.
5
RX_ACK
R
1
Negative
0 indicates that the EEPROM sent an ACK bit.
4
TX_ACK
R
1
Negative
0 indicates when an ACK bit has been sent to the EEPROM
CMD
3-0
CMD[3:0
]
W
Positive,
see CMD
Table
0
Operation
0
No-op. Applying the no-op command will stop the I2C clock
(SCK, DIO4). Failure to issue the no-op command will keep
the SCK signal toggling.
2
Receive a byte from EEPROM and send ACK.
3
Transmit a byte to EEPROM.
5
Issue a ‘STOP’ sequence.
6
Receive the last byte from EEPROM and do not send ACK.
9
Issue a ‘START’ sequence.
Others
No Operation, set the ERROR bit.
Table 57: EECTRL Status Bits
Internal Clocks and Clock Dividers
All internal clocks are based on the watch crystal frequency (CK32 = 32,768Hz) applied to the XIN and XOUT pins. The PLL
multiplies this frequency by 150 to 4.9152MHz. This frequency is supplied to the ADC, the FIR filter (CKFIR), the clock test
output pin (CKTEST), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU
(CKMPU) and one for the CE (CKCE).
-MPU_DIV
Hz where
The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2
MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to
38.4kHz.
The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register
ECK_DIS (0x2005[5]) is asserted by the MPU.
Battery
The VBAT pin provides an input for an external battery that can be used to support the crystal oscillator, RTC, the WD_OVF bit
and XRAM in the absence of the main power supply. If the battery is not used, the VBAT pin should be connected to V3P3.
Internal Voltages (VBIAS, VBAT, V2P5)
The 71M6511 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages
can be tied together outside the chip. The internal supply voltage V2P5 is generated by a regulator from the 3.3V supplies.
The battery voltage, VBAT, is required when crystal oscillator, RTC and XRAM are required to keep operating while V3P3D is
removed (battery mode). VBAT, usually supplied by an external battery, powers crystal oscillator, RTC and XRAM (and the
WD_OVF bit).
VBIAS (1.5V) is generated internally and used for the V1 comparator and for the reference of the temperature sensor.
Test Ports
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TMUXOUT Pin: One out of 16 digital or 4 analog signals can be selected to be output on the TMUXOUT pin. The function of
the multiplexer is controlled with the I/O RAM register TMUX (0x2000[3:0]), as shown in Table 58.
TMUX[3:0]
Mode
Function
0
analog
DGND
1
analog
IBIAS
2
analog
PLL_2.5V
3
analog
VBIAS
4
digital
RTM (Real time output from CE)
5
digital
WDTR_EN (Comparator 1 Output AND V1LT3)
6
digital
reserved
7
digital
reserved
8
digital
RXD (from Optical interface)
9
digital
MUX_SYNC
A
digital
CK_10M
B
digital
CK_MPU
C
--
reserved for production test
D
digital
RTCLK
E
digital
CE_BUSY
F
digital
XFER_BUSY
Table 58: TMUX[3:0] Selections
Emulator Port: The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX provides control of the MPU through
an external in-circuit emulator. The emulator port is compatible with the ADM51 emulators manufactured by Signum Systems.
The signals of the emulator port have weak pull-ups. Adding 1kΩ pull-up resistors on the PCB is recommended.
Real-Time Monitor: The RTM output of the CE is available as one of the digital multiplexer options. RTM data is read from the
CE DRAM locations specified by I/O RAM registers RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC. The RTM can
be enabled and disabled with I/O RAM register RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked
out in 35 cycles and contains a leading flag bit. Figure 13 in the System Timing Section illustrates the RTM output format. RTM
is low when not in use.
SSI Interface: A high-speed serial interface with handshake capability is available to send a contiguous block of CE data to an
external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycle of 32kHz before
each CE code pass begins. If the block of data is big enough that transmission has not completed when the code pass begins,
it will complete during the CE code pass with no timing impact to the CE or the serial data. In this case, care must be taken
that the transmitted data is not modified unexpectedly by the CE. The SSI interface is enabled by the SSI_EN bit and consists
of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit
processors. The operation of each pin is as follows:
SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls
whether SCLK runs continuously or is gated off when no SSI activity is occurring. If SCLK is gated, it will begin 3 cycles before
SFR rises and will persist 3 cycles after the last data bit is output.
The pins used for the SSI are multiplexed with the LCD segment outputs, as shown in Table 59. Thus, the LCD should be
disabled when the SSI is in use.
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SSI Signal
LCD Segment
Output Pin
SCLK
SEG3
SSDATA
SEG4
SFR
SEG5
SRDY
SEG6
Table 59: SSI Pin Assignment
SRDY is an optional handshake input that indicates that the DSP or data-logging device is ready to receive data. SRDY must
be high to enable SFR to rise and initiate the transfer of the next field. It is expected that SRDY changes state on the rising
edges of SCLK. If SRDY is not high when the SSI port is ready to transmit the next field, transmission will be delayed until it is.
SRDY is ignored except at the beginning of a field transmission. If SRDY is not enabled (by SSI_RDYEN), the SSI port will
behave as if SRDY is always one.
SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the contents of a block of CE
RAM words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first.
The field size is set with the SSI_FSIZE register: 0 entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of
the SFR pulse can be inverted with SSI_FPOL. If SRDY does not delay it, the first SFR pulse in a frame will rise on the third
SCLK after MUX_SYNC (fourth SCLK if 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger
or DSP.
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FUNCTIONAL DESCRIPTION
Theory of Operation
The energy delivered by a power source into a load can be expressed as:
t
E = ∫ V (t ) I (t )dt
0
Assuming phase angles are constant, the following formulae apply:
P = Real Energy [Wh] = V * A * cos φ* t
Q = Reactive Energy [VARh] = V * A * sin φ * t
S = Apparent Energy [VAh] =
P2 + Q2
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change
constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the
71M6511/6511H functions by emulating the integral operation above, i.e. it processes current and voltage samples through an
ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic
range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for
the momentary energy. Summing up the momentary energy quantities over time will result in accumulated energy.
500
400
V [V], I [A], P [Ws]
300
200
100
0
-100
-200
Current [A]
-300
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
0
5
10
15
time [ms]
20
Figure 12: Voltage. Current, Momentary and Accumulated Energy
Figure 12 shows the shapes of V(t), I(t), the momentary and the accumulated energy, resulting from 50 samples of the voltage
and current signals over a period of 20ms. The application of 240VAC and 100A results in an accumulation of 480Ws over the
20ms period, as indicated by the Accumulated Power curve.
The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion.
System Timing Summary
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Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV = 1 (four mux states) and FIR_LEN = 1 (3 CK32 cycles). Since FIR filter conversions
require two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1
+ 3 * states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into
DRAM is shown in Figure 13.
Figure 13 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
ADC, CE and SERIAL TIMING
ADC MUX Frame
ADC TIMING
Settle
MUX_DIV Conversions (MUX_DIV=4 is shown)
CK32
150
MUX_SYNC
MUX STATE
S
1
0
2
3
S
ADC EXECUTION
ADC0
CE TIMING
0
ADC1
450
ADC2
900
ADC3
1350
1800
CE_EXECUTION
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM and SSI TIMING
140
RTM
SSI
LAST SSI TRANSFER
BEGIN SSI TRANSFER
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respectively.
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CK32
MUX_SYNC
CKTEST
0
31
FLAG
1
30
31
0
FLAG
1
30
31
SIG
N
30
LSB
FLAG
1
SIG
N
0
LSB
31
SIG
N
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
30
LSB
FLAG
1
LSB
0
SIG
N
TMUXOUT/RTM
Figure 14: RTM Output Format
If SSI_CKGATE =1
If 16bit fields
If SSI_CKGATE =1
If 32bit fields
SFR (Output)
SRDY (Input)
SCLK (Output)
31
SSDATA (Output)
30
16
1
15
0
31
30
16
1
15
0
1
31
0
SSI_END
SSI_BEG+1
SSI_BEG
MUX_SYNC
Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0)
Next field is delayed while SRDY is low
SFR (Output)
SRDY (Input)
SCLK (Output)
SSDATA (Output)
31
30
29
18
17
16
16
16
16
15
14
13
12
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY)
SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single
field, as multiple 16-bit fields, or as multiple 32-bit fields. The SFR pulse is one SCLK clock cycle wide, changes state on the
rising edge of SCLK and precedes the first bit of each field.
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Data Flow
The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)
sequentially processes the samples from the voltage inputs on pins IA, VA, and IB, performing calculations to measure active
2
2
power (Wh), reactive power (VARh), A h, and V h for four-quadrant metering. These measurements are then accessed by the
MPU, processed further and output using the peripheral devices available to the MPU.
Pulses
IRQ
Samples
CE
Data
PreProcessor
MPU
PostProcessor
Processed
Metering
Data
I/O RAM (Configuration RAM)
Figure 17: MPU/CE Data Flow
CE/MPU Communication
Figure 18 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the
I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY,
which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the
output region of the CE RAM. This will occur whenever the CE has finished generating a sum by completing an accumulation
interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the
XFER_BUSY and CE_BUSY signals.
Figure 19 shows the sequence of events between CE and MPU upon reset or power-up. In a typical application, the sequence
of events is as follows:
1)
2)
3)
4)
5)
Upon power-up, the MPU initializes the hardware, including disabling the CE
The MPU loads the code for the CE into the CE PRAM
The MPU loads CE data into the CE DRAM.
The MPU starts the CE by setting the CE_EN bit in the I/O RAM.
The CE then repetitively executes its code, generating results and storing them in the CE DRAM
It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and
PRE_SAMPS is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting
accumulation interval is:
τ=
N ACC
2520
60 ⋅ 42
=
=
= 999.75ms
32768Hz 2520.62 Hz
fS
13
This means that accurate time measurements should be based on the RTC, not the accumulation interval.
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PULSES
W (DIO6)
WSUM
VARSUM
VAR (DIO7)
DISPLAY (memory-mapped
LCD segments)
APULSEW
SERIAL
(UART0/1)
APULSER
EXT_PULSE
DATA
ADC
MPU
EEPROM
(I2C)
SAMPLES
CE_BUSY
CE
Mux Ctrl.
DIO
XFER_BUSY
INTERRUPTS
I/O RAM (CONFIGURATION RAM)
Figure 18: MPU/CE Communication (Functional)
The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional
processing such as energy accumulation.
CE PRAM
FLASH
CE_EN
XFER Interrupt
COMPUTATION
ENGINE
CE DRAM
MPU
Figure 19: MPU/CE Communication (Processing Sequence)
Fault, Reset, Power-Up
Reset Mode: When the RESETZ pin is pulled low or when V1 < VBIAS, all digital activity in the chip stops while analog circuits
are still active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared. As long as V1, the
input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100
cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot
sequences from address 00. See the security section for more description of preboot and boot.
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Power-Up: After power-up, the 71M6511/6511H is in reset as long as V1 < VBIAS. As soon as V1 exceeds VBIAS, the reset
timer is started which takes the MPU out of reset after 4100 oscillator cycles (see Figure 20). The MPU then initiates its preboot phase lasting 32 cycles. The supply current will be low but not zero during power-up. It will increase, once V1 exceeds
VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under
firmware control, following the steps specified in Battery Operation and Power Save Modes.
V3P3
3.3V
V2P5
V1
1.5V
0V
POWER
DOWN
PWR
UP
PREBOOT
RESET TIMER
FIRMWARE HAS CONTROL OVER CHIP...
V1 > VBIAS
SUPPLY CURRENT
nominal
1ms
125ms
0mA
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up
Battery Operation
When V1 is lower than VBIAS, the external battery will power the following parts of the 71M6511/6511H:
•
•
•
•
RTC
Crystal oscillator circuitry
MPU XRAM
WD_OVF bit
Power Save Modes
In normal mode of operation, running on 3.3V supply, various resources of the 71M6511/6511H may be shut down by the
MPU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active.
Table 60 outlines these resources and their typical current consumption (based on initial condition MPU_DIV = 0).
Power Saving Measure
Software Control
Disable the CE
Typical
Savings
CE_EN = 0
0.16mA
ADC_DIS = 1
1.8mA
Disable clock test output CKTEST
CKOUTDIS = 1
0.6mA
Disable emulator clock
ECK_DIS = 1 *)
0.1mA
Disable the ADC
Set flash read pulse timing to 33 ns
Disable the LCD voltage boost circuitry
Disable RTM outputs
FLASH66Z =1
0.04mA
LCD_BSTEN = 0
0.9mA
RTM_EN = 0
0.01mA
Increase the clock divider for the MPU
MPU_DIV = X
0.4mA/MHz
*) This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus
preclude flash erase and programming operations.
Table 60: Power Saving Measures
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Temperature Compensation
Internal Compensation: The internal voltage reference is calibrated during device manufacture. Trim data is stored in on-chip
fuses.
For the 71M6511, the temperature coefficients TC1 and TC2 are given as constants that represent typical component
behavior.
For the 71M6511H, the temperature characteristics of the chip are measured during production and then stored in the fuse
registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be derived from the fuses by using the relations given in the
Electrical Specifications section. TC1 and TC2 can be further processed to generate the coefficients PPMC and PPMC2.
TRIMM[2:0], TRIMBGA and TRIMBGB are read by first writing either 4, 5 or 6 to TRIMSEL (0x20FD) and then reading the value
of TRIM (0x20FF).
When the EXT_TEMP register in CE DRAM (address 0x38) is set to 0, the CE automatically compensates for temperature
errors by controlling the GAIN_ADJ register (address 0x2E) based on the PPMC, PPMC2, and TEMP_X register values. In the
case of internal compensation, GAIN_ADJ is an output of the CE.
External Compensation: Rather than internally compensating for the temperature variation, the bandgap temperature is
provided to the embedded MPU, which then may digitally compensate the power outputs. This permits a system-wide
temperature correction over the entire system rather than local to the chip. The incorporated thermal coefficients may include
the current sensors, the voltage sensors, and other influences. Since the band gap is chopper stabilized via the CHOP_EN bits,
the most significant long-term drift mechanism in the voltage reference is removed.
When the EXT_TEMP register in CE DRAM is set to 15, the CE ignores the PPMC, PPMC2, and TEMP_X register values and
applies the gain supplied by the MPU in GAIN_ADJ. External compensation enables the MPU to control the CE gain based on
any variable, and when EXT_TEMP = 15, GAIN_ADJ is an input to the CE.
Chopping Circuitry
As explained in the hardware section, the bits of the I/O RAM register CHOP_ENA[1:0] have to be toggled in between
multiplexer cycles to achieve the desired elimination of DC offset.
The amplifier within the reference is auto-zeroed by means of an internal signal that is controlled by the CHOP_EN bits. When
this signal is HIGH, the connection of the amplifier inputs is reversed. This preserves the overall polarity of the amplifier gain
but inverts the input offset. By alternately reversing the connection, the offset of the amplifier is averaged to zero. The two bits
of the CHOP_EN register have the function specified in Table 61.
CHOP_EN[1]
Function
CHOP_EN[0]
0
0
Toggle chop signal
0
1
Reference connection positive
1
0
Reference connection reversed
1
Toggle chop signal
1
Table 61: CHOP_EN Bits
For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the
reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 21. With an even number of
multiplexer cycles in each accumulation interval, the number of cycles with positive reference connection will equal the number
of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is
acceptable when only the primary signals (meter voltage, meter current) are of interest.
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MUX
cycle 2
MUX
cycle 1
MUX
cycle 3
Accumulation Interval m+2
Accumulation Interval m+1
Accumulation Interval m
MUX
cycle n
MUX
cycle 1
Reversed
Positive
MUX
cycle n
MUX
cycle 1
Reversed
Positive
Chop Polarity
Reversed
Positive
Positive
Reversed
Positive
Reversed
Positive
CE_BUSY interrupt
(falling edge)
XFER_BUSY interrupt
(falling edge)
Figure 21: Chop Polarity w/ Automatic Chopping
If temperature compensation or accurate reading of the die temperature is required, alternate multiplexer cycles have to be
inserted in between the regular cycles. This is done under MPU firmware control by asserting the MUX_ALT bit whenever
necessary. Since die temperature usually changes very slowly, alternate multiplexer cycles have to be inserted very
infrequently. Usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each
XFER_BUSY interrupt. This sequence is shown in Figure 22.
Accumulation Interval m
MUX
alt. MUX MUX
cycle 2 cycle 3
cycle
Accumulation Interval m+1
MUX alt. MUX
cycle n cycle
Accumulation Interval m+2
MUX alt. MUX
cycle n cycle
Chop Polarity
Positive
RePositive
versed
RePositive
versed
Re- Positive
versed
Reversed
Positive
Reversed
Positive
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
Figure 22: Sequence with Alternate Multiplexer Cycles
This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.
Consequently, DC offset will appear on the temperature measurement, which will decrease the accuracy of this measurement
and thus cause temperature reading and compensation to be less accurate.
The sequence shown in Figure 23 uses the CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.
CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each
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XFER_BUSY interrupt. After these first two cycles, CHOP_EN returns to 11 (automatic toggle). The value of CHOP_EN, when
set after the XFER_BUSY interrupt, is in force for the entire following multiplexer cycle.
When using this sequence, the alternate multiplexer cycle is toggled between positive and reversed connection resulting in
accurate temperature measurement.
An example for proper application of the CHOP_EN bits can be found in the Demo Code shipped with the 6511 and 6511
Demo Kits. Firmware implementations should closely follow this example.
Accumulation Interval m
alt. MUX MUX
cycle 2
cycle
MUX
cycle 3
Accumulation Interval m+1
Accumulation Interval m+2
MUX
cycle n
alt. MUX MUX
cycle 2
cycle
MUX
cycle 3
MUX
cycle n
alt. MUX MUX
cycle 2
cycle
MUX
cycle 3
MUX
cycle n
Positive
reversed
Positive
reversed
Positive Positive
reversed
Positive
Chop Polarity
rePositive Positive versed
reversed
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
CHOP_EN
01
11
(11)
(11)
(11)
10
11
(11)
(11)
(11)
01
11
(11)
(11)
(11)
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping
Internal/External Pulse Generation and Pulse Counting
The CE is the source for pulses. It can generate pulses directly based on the voltage and current inputs and the configured
pulse generation parameters. This is called “internal pulse generation”, and applies when the CE RAM register EXT_PULSE
(address 0x37) equals 0. Alternatively, the CE can be configured to generate pulses based on registers that are controlled by
the MPU (“external pulse generation”), i.e. when the register EXT_PULSE equals 15. In the case of external pulse generation,
the MPU writes values to the CE registers APULSEW (0x26) and APULSER (0x27).
The pulse rate, usually inversely expressed as “Kh” (and measured in Wh per pulse), is determined by the CE RAM registers
WRATE, PULSE_SLOW, PULSE_FAST, In_8, as well as by the sensor scaling VMAX and IMAX per the equation:
Kh =
VMAX ⋅ IMAX ⋅ 47.1132
[Wh / pulse]
In _ 8 ⋅ WRATE ⋅ N ACC ⋅ X
where
In_8 is the gain factor (1 or 8) controlled by the CE variable In_SHUNT,
X is the pulse gain factor controlled by the CE variables PULSE_SLOW and PULSE_FAST
NACC is the accumulation count (PRE_SAMPS * SUM_CYCLES)
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Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked.
This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a
32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to
perform a global erase of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM.
The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A readonly status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the
ICE can be enabled and is permitted to take control of the MPU.
SECURE (SFR 0xB2[6]), the security enable bit, is reset whenever the MPU is reset. Hardware associated with the bit permits
only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once
SECURE is set, the preboot code is protected and no external read of program code is possible.
Specifically, when SECURE is set:
•
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or
ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases CE program RAM whether
SECURE is set or not.
Writes to page zero, whether by MPU or ICE, are inhibited.
The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE
interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE
Interface description).
Additionally, by setting the I/O RAM register ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with
the emulator. See the cautionary note in the I/O RAM Register description!
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FIRMWARE INTERFACE
I/O RAM MAP – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed.
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0
CE1
CE2
COMP0
CONFIG0
CONFIG1
VERSION
EQU[2:0]
2000
PRE_SAMPS[1:0]
2001
MUX_DIV[1:0]
2002
2003
2004 VREF_CAL
2005 RESERVED
2006
TMUX[3:0]
SUM_CYCLES[5:0]
CHOP_EN[1:0]
RTM_EN
WD_OVF
EX_RTC
RESERVED
RESERVED
VREF_DIS
MPU_DIV
RESERVED CKOUT_DIS
ECK_DIS
FIR_LEN
ADC_DIS
MUX_ALT
FLASH66Z
VERSION[7:0]
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
2008
2009
200A
200B
200C
200D
200E
OPT_TXDIS
RESERVED
RESERVED
DIO_R5[2:0]
DIO_R7[2:0]
DIO_R9[2:0]
DIO_R11[2:0]
RTC0
RTC1
RTC2
RTC3
RTC4
RTC5
RTC6
RTC7
2015
2016
2017
2018
2019
201A
201B
201C
CE_EN
EX_XFR
COMP_STAT[0]
MUX_E
Digital I/O:
DIO_EEX
DIO_PW
DIO_PV
RESERVED
RESERVED
DIO_R4[2:0]
DIO_R6[2:0]
DIO_R8[2:0]
DIO_R10[2:0]
Real Time Clock:
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
RTC_DEC_SEC RTC_INC_SEC
LCD Display Interface:
LCDX
LCDY
LCDZ
LCD0
LCD1
…
LCD19
LCD20
…
LCD23
LCD24
…
LCD31
LCD32
LCD33
LCD34
LCD35
LCD36
LCD37
2020 LCD_BSTEN
2021
2022
2030
2031
…
2043
2044
…
2047
2048
…
204F
2050
2051
2052
2053
2054
2055
Page: 57 of 98
LCD_EN
LCD_NUM[4:0]
LCD_MODE[2:0]
LCD_CLK[1:0]
LCD_FS[4:0]
LCD_SEG0[3:0]
LCD_SEG1[3:0]
…
LCD_SEG19[3:0]
RESERVED
…
RESERVED
LCD_SEG24[3:0]
…
LCD_SEG31[3:0]
LCD_SEG32[3:0]
LCD_SEG33[3:0]
LCD_SEG34[3:0]
LCD_SEG35[3:0]
LCD_SEG36[3:0]
LCD_SEG37[3:0]
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LCD38
LCD39
LCD40
LCD41
2056
2057
2058
2059
RTM0
RTM1
RTM2
RTM3
2060
2061
2062
2063
RESERVED
RESERVED
RESERVED
RESERVED
RTM Probes:
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
Synchronous Serial Interface:
SSI
2070
S S I _ B E G 2071
SSI_END 2072
SSI_EN
SSI_10M
SSI_CKGATE
SSI_FSIZE[1:0]
SSI_BEG[7:0]
SSI_END[7:0]
SSI_FPOL
SSI_RDYEN
SSI_RDYPOL
Fuse Selection Registers:
TRIMSEL 20FD
TRIM
20FF
TRIMSEL[7:0]
TRIM[7:0]
SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers.
Name
SFR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Digital I/O:
P0
DIR0
P1
DIR1
P2
DIR2
80
A2
90
91
A0
A1
DIO_0[7:4] (Port 0)
DIO_DIR0[7:4]
DIO_1[7:6] (Port 1)
DIO_DIR1[7:6]
INTBITS
WDI
F8
E8
INT6
ERASE
FLSHCTL
PGADR
94
B2
B7
RESERVED
1111
RESERVED
1111
DIO_1[3:0] (Port 1)
DIO_DIR1[3:0]
DIO_2[1:0] (Port 2)
DIO_DIR2[1:0]
Interrupts and WD Timer:
INT5
INT4
INT3
INT2
WD_RST
INT1
IE_RTC
INT0
IE_XFER
FLSH_MEEN
FLSH_PWE
Flash:
FLSH_ERASE[7:0]
PREBOOT
SECURE
FLSH_PGADR[6:0]
Serial EEPROM:
9E
EEDATA[7:0]
9F
EECTRL[7:0]
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I/O RAM (Configuration RAM) – Alphabetical Order
Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its parameters from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and
copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory
space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all
bits are cleared to zero unless otherwise stated. Generic SFR registers are not listed.
Name
Location
[Bit(s)]
Dir
Description
ADC_DIS
2005[3]
R/W
Disables ADC and removes bias current
CE_EN
2000[4]
R/W
CE enable.
CHOP_EN[1:0]
2002[5:4]
R/W
Chop enable for the reference band gap circuit.
00: enabled 01: disabled 10: disabled 11: enabled
RESERVED
2004[5]
R/W
Must be 0.
CKOUT_DIS
2004[4]
R/W
CKOUT Disable. When zero, CKTEST is an active output.
RESERVED
2003[4:3]
R/W
Must be 0.
RESERVED
2003[2:0]
R
Reserved
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Connects dedicated I/O pins 4 to 11 to selectable internal resources. If
more than one input is connected to the same resource, the ‘Multiple’
column below specifies how they are combined. See Software User’s
Guide for details).
DIO_DIR0[7:4]
SFR A2
R/W
Programs the direction of DIO pins 7 through 4. 1 indicates output.
Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW
for special option for DIO6 and DIO7 outputs. See DIO_EEX for special
option for DIO4 and DIO5.
Note: Bit 0, Bit 1, Bit 2 and Bit 3 must be set to 1.
Page: 59 of 98
DIO_GP
0
1
2
3
4
5
6
7
Resource
NONE
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (int0 rising)
Low priority I/O interrupt (int1 rising)
High priority I/O interrupt (int0 falling)
Low priority I/O interrupt (int1 falling)
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-OR
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DIO_DIR1[7:6]
DIO_DIR1[3:0]
SFR91
R/W
Programs the direction of DIO pins 15, 14 and 11 through 8. 1
indicates output. Ignored if the pin is not configured as I/O.
Note: Bit 4 and Bit 5 must be set to 1.
DIO_DIR2[1:0]
SFRA1[5:0]
R/W
Programs the direction of DIO pins 17 and 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
Note: Bit 2, Bit 3, Bit 4 and Bit 5 must be set to 1.
DIO_0[7:4]
DIO_1[7:6],
DIO_1[3:0]
DIO_2[1:0]
SFR80
SFR90
SFR90
SFRA0[1:0]
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 1
Port 2
DIO_EEX
2008[4]
R/W
When set, converts DIO4 and DIO5 to interface with external
EEPROM. DIO4 becomes SCK and DIO5 becomes bi-directional SDA.
LCD_NUM must be less than 18.
DIO_PV
2008[2]
R/W
Causes VARPULSE to be output on DIO7, if DIO7 is configured as
output. LCD_NUM must be less than 15.
DIO_PW
2008[3]
R/W
Causes WPULSE to be output on DIO6, if DIO6 is configured as
output. LCD_NUM must be less than 17.
EEDATA[7:0]
SFR 9E
R/W
Serial EEPROM interface data
EECTRL[7:0]
SFR 9F
R/W
Serial EEPROM interface control
ECK_DIS
2005[5]
R/W
Emulator clock disable. When one, the emulator clock is disabled.
This bit is to be used with caution! Inadvertently setting
this bit will inhibit access to the part with the ICE
interface and thus preclude flash erase and programming
operations. If ECK_DIS is set, it should be done at least 1000ms after
power-up to give emulators and programming devices enough time to
complete an erase operation.
EQU[2:0]
2000[7:5]
R/W
Specifies the power equation to the CE.
EX_XFR
EX_RTC
2002[0]
2002[1]
R/W
Interrupt enable bits. These bits enable the XFER_BUSY and the
RTC_1SEC interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
FIR_LEN
2005[4]
R/W
The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),
0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)
FLASH66Z
2005[1]
R/W
Should be set to 1 to minimize supply current.
Page: 60 of 98
The value on the DIO pins. Pins configured as LCD will read
zero. When written, changes data on pins configured as
outputs. Pins configured as LCD or input will ignore writes.
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FLSH_ERASE
SFR 94
W
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write
to FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write
to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must
be enabled.
Any other pattern written to FLSH_ERASE will have no effect.
FLSH_MEEN
SFR B2[1]
W
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
FLSH_PGADR
SFR B7[7:1]
W
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be
erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
FLSH_PWE
SFR B2[0]
R/W
Program Write Enable
0 – MOVX commands refer to XRAM Space, normal operation
(default).
1 – MOVX @DPTR,A moves A to Program Space (flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
IE_XFER
IE_RTC
SFR E8[0]
SFR E8[1]
R/W
Interrupt flags. These flags are part of the WDI SFR register and monitor the XFER_BUSY interrupt and the RTC_1SEC interrupt. The
flags are set by hardware and must be cleared by the interrupt handler.
See also WD_RST.
INTBITS
SFR F8[6:0]
R
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have any
memory and are primarily intended for debug use.
LCD_BSTEN
2020[7]
R/W
Enables the LCD voltage boost circuit.
LCD_CLK[1:0]
2021[1:0]
R/W
Sets the LCD clock frequency for COM/SEG pins (not the frame rate.
Note: fw = CKFIR/128
9
8
7
6
00: f w/2 , 01: fw/2 , 10: fw/2 , 11: fw/2
LCD_EN
2021[5]
R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs.
LCD_FS[4:0]
2022[4:0]
R/W
Controls the LCD full scale voltage, VLC2:
VLC 2 = VLCD ⋅ (0.7 + 0.3
Page: 61 of 98
LCD _ FS
)
31
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Single-Phase Energy Meter IC
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LCD_MODE[2:0
]
2021[4:2]
R/
W
The LCD bias mode.
000: 4 states, 1/3 bias
001: 3 states, 1/3 bias
010: 2 states, ½ bias
011: 3 states, ½ bias
100: static display
LCD_NUM[4:0]
2020[4:0]
R/
W
Controls the number of dual-purpose LCD/DIO pins to be configured
as LCD. LCD_NUM will be between 0 and 18. The first dual-purpose
pin to be allocated as LCD is SEG37/DIO17. The table below lists
which SEG and DIO functions are selected for each LCD_NUM value.
SEG
LCD_NUM
1-4
DIO
None
DIO4-11, DIO14-17
5
SEG37
DIO4-11, DIO14-16
6
SEG36-37
DIO4-11, DIO14-15
7
SEG35-37
DIO4-11, DIO14
8-10
SEG34-37
DIO4-11
11
SEG34-37, SEG31
DIO4-10
12
SEG34-37, SEG30-31
DIO4-9
13
SEG34-37, SEG29-31
DIO4-8
14
SEG34-37, SEG28-31
DIO4-7
15
SEG34-37, SEG27-31
DIO4-6
16
SEG34-37, SEG26-31
DIO4-5
17
SEG34-37, SEG25-31
DIO4
18
SEG34-37, SEG24-31
None
LCD_SEG0[3:0]LCD_SEG19[3:0],
LCD_SEG24[3:0]LCD_SEG31[3:0],
LCD_SEG34[3:0]LCD_SEG37[3:0],
2030[3:0]
2043[3:0]
,
2048[3:0]
204f[3:0],
2052[3:0]
2055[3:0]
R/
W
LCD Segment Data. Each word contains information for from 1 to 4
time divisions of each segment. In each word, bit 0 corresponds to
COM0, on up to bit 3 for COM3.
MPU_DIV[2:0]
2004[2:0]
R/
W
The MPU clock divider (from CKCE). These bits may be programmed
by the MPU without risk of losing control.
000 - CKCE, 001 - CKCE/2, …, 111 - CKCE/27
MPU_DIV is 000 on power-up.
MUX_ALT
2005[2]
R/
W
The MPU asserts this bit when it wishes the MUX to perform ADC
conversions on an alternate set of inputs.
MUX_DIV[1:0]
2002[7:6]
R/
W
The number of states in the input multiplexer.
00 - 6 states 01 - 4 states 10 - 3 states 11 - 2 states
MUX_E
2005[0]
R/
MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC
Page: 62 of 98
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W
output.
OPT_TXDIS
2008[5]
R/
W
Tristates the OPT_TX output.
PREBOOT
SFR
B2[7]
R
Indicates that the preboot sequence is active.
PRE_SAMPS[1:0]
2001[7:6]
R/
W
Together w/ SUM_CYCLES, this value determines the number of
samples in one sum cycle between XFER interrupts for the CE.
Number of samples = PRE_SAMPS*SUM_CYCLES.
00-42, 01-50, 10-84, 11-100
RTC_SEC[5:0]
RTC_MINI[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2015
2016
2017
2018
2019
201A
201B
RTC_DEC_SEC
RTC_INC_SEC
R/W
The RTC interface. These are the ‘year’, ‘month’, ‘day’, ‘hour’,
‘minute’ and ‘second’ parameters for the RTC. The RTC is set by
writing to these registers. Year 00 is defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR
00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR
00 to 256
201C[1]
201C[0]
W
RTC time correction bits. Only one bit may be pulsed at a time. When
pulsed, causes the RTC time value to be incremented (or
decremented) by an additional second the next time the RTC_SEC
register is clocked. The pulse width may be any value. If an additional
correction is desired, the MPU must wait 2 seconds before pulsing
one of the bits again.
RTM_EN
2002[3]
R/W
Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2060
2061
2062
2063
R/W
R/W
R/W
R/W
Four RTM probes. Before each CE code pass, the values of these
registers are serially output on the RTM pin. The RTM registers are
ignored when RTM_EN=0.
SECURE
SFR
B2[6]
R/W
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
SSI_EN
2070[7]
R/W
Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take
on the new functions SCLK, SSDATA, SFR, and SRDY, respectively.
When SSI_EN is high and LCD_EN is low, these pins are converted to
the SSI function, regardless of LCDEN and LCD_NUM. For proper
LCD operation, SSI_EN must not be high when LCD_EN is high.
SSI_10M
2070[6]
R/W
SSI clock speed: 0: 5MHz, 1: 10MHz
SSI_CKGATE
2070[5]
R/W
SSI gated clock enable. When low, the SCLK is continuous. When
high, the clock is held low when data is not being transferred.
SSI_FSIZE[1:0]
2070[4:3]
R/W
SSI frame pulse format:
0: once at beginning of SSI sequence (whole block of data),
1: every 8 bits, 2: every 16 bits, 3: every 32 bits.
SSI_FPOL
2070[2]
R/W
SFR pulse polarity: 0: positive, 1: negative
Page: 63 of 98
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SSI_RDYEN
2070[1]
R/W
SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SSI_RDYPOL
2070[0]
R/W
SRDY polarity: 0: positive, 1: negative
SSI_BEG[7:0]
SSI_END[7:0]
2071[7:0]
2072[7:0]
R/W
The beginning and ending address of the transfer region of the CE
data memory. If the SSI is enabled, a block of words starting with
SSI_BEG and ending with SSI_END will be sent. SSI_END must be
larger than SSI_BEG. The maximum number of output words is limited
by the number of SSI clocks in a CE code pass—see FIR_LEN,
MUX_DIV, and SSI_10M.
SUM_CYCLES
[5:0]
2001[5:0]
R/W
TMUX[3:0]
2000[3:0]
R/W
Selects one of 16 inputs for TMUXOUT.
0 – DGND (analog)
1 – IBIAS (analog)
2 – PLL_2.5V (analog)
3 – VBIAS (analog)
4 – RTM (Real time output from CE)
5 – WDTR_EN (Comparator 1 Output AND V1LT3)
6 – reserved
7 – reserved
8 – RXD (from Optical interface)
9 – MUX_SYNC (from MUX_CTRL)
A – CK_10M
B – CK_MPU
C – reserved for production test
D – RTCLK
E – CE_BUSY
F – XFER_BUSY
RESERVED
2005[7]
R/W
Must be zero.
TRIMSEL
20FD
W
Selects the temperature trim fuse to be read with the TRIM register
(TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6)
TRIM
20FF
R
Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depending on the
value written to TRIMSEL. If TRIMBGB = 0 then the IC is a 6511 else
the IC is a 6511H.
VERSION[7:0]
2006
R
The silicon revision number. This data sheet does not apply to
revisions < 000 0100.
VREF_CAL
2004[7]
R/W
Brings VREF out to the VREF pin. This feature is disabled when
VREF_DIS=1.
VREF_DIS
2004[3]
R/W
Disables the internal voltage reference.
WD_RST
SFR
E8[7]
WD_OVF
2002[2]
Page: 64 of 98
Together w/ PRE_SAMPS, this value determines (for the CE) the
number of samples in one sum cycle between XFER interrupts.
Number of samples = PRE_SAMPS*SUM_CYCLES.
W
Resets the WD timer. The WDT is reset when a 1 is written to this bit.
Only byte operations on the whole WDI register should be used.
R/W
The WD overflow status bit. This bit is set when the WD timer
overflows. It is powered by the VBAT pin and at boot-up will indicate if
the part is recovering from a WD overflow or a power fault. This bit
should be cleared by the MPU on boot-up. It is also automatically
cleared when RESETZ is low.
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
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CE Program and Environment
CE Program
The CE program is supplied by TERIDIAN as a data image that can be merged with the MPU operational code for meter
applications. Typically, the CE program covers most applications and does not need to be modified. The description in this
section applies to CE code revision CE11B05.
Formats
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement (-1 = 0xFFFFFFFF). ‘Calibration’
parameters are defined in flash memory (or external EEPROM) and must be copied to CE memory by the MPU before
enabling the CE. ‘Internal’ variables are used in internal CE calculations. ‘Input’ variables allow the MPU to control the
behavior of the CE code. ‘Output’ variables are outputs of the CE calculations. The corresponding MPU address for the most
significant byte is given by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_address for the least significant byte.
Constants
Constants used in the CE Data Memory tables are:
Sampling frequency: FS = 32768Hz/13 = 2520.62Hz (MUX_DIV = 1) or 32786/10 = 3276.8Hz (MUX_DIV = 2)
F0 is the fundamental signal frequency, typically 50 or 60Hz.
IMAX is the external rms current corresponding to 250mV peak at the inputs IA or IB.
VMAX is the external rms voltage corresponding to 250mV peak at the input VA.
NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES. This value resides in
SUM_PRE (CE address 36).
Accumulation count time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS.
In_8 is a gain constant of current channel n. Its value is 8 or 1 and is controlled by In_SHUNT.
X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW.
-9
Voltage LSB = VMAX * 3.3243*10 V (peak).
The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as used by the CE) to
external, i.e. metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an
actual meter. The LSB values used in this document relate digital quantities at the CE or MPU interface to external meter input
quantities. For example, if a SAG threshold of 80V peak is desired at the meter input, the digital value that should be programmed into SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR.
The parameters EQU, CE_EN, PRE_SAMPS, and SUM_CYCLES are essential to the function of the CE and are stored in I/O
RAM (see I/O RAM section).
Page: 65 of 98
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Environment
Before starting the CE using the CE_EN bit, the MPU has to establish the proper environment for the CE by implementing the
following steps:
•
Loading the image for the CE code into CE PRAM.
•
Loading the CE data into CE DRAM.
•
Establishing the equation to be applied in EQU.
•
Establishing the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.
•
Establishing the number of cycles per ADC mux cycle.
The default configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV = 1 (4 conversions per mux cycle). There
must be thirteen CK32 cycles (see System Timing Diagram, Figure 13). This means that the product of the number of cycles
per ADC conversion and the number of conversions per cycle must be 12 (allowing for one settling cycle).
Alternatively, the 71M6511 can be operated at ten CK32 cycles per ADC mux cycle (MUX_DIV = 2). CE quantities are stated
in this section for MUX_DIV = 2, if they differ from those associated with the default setting.
During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer
sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of CHOP must be altered
for each sample. It must also alternate for each alternate multiplexer reading.
The MPU must program CHOP_EN alternately between 01 and 10 on every CE_BUSY interrupt except for the first CE_BUSY
after an XFER_BUSY interrupt. Note that when XFER_BUSY occurs, it will always be at the same time as a CE_BUSY
interrupt.
Operating CE codes with environment parameters deviating from the values specified by Teridian will lead to
unpredictable results.
CE Calculations
The CE performs the precision computations necessary to accurately measure power. These computations include offset
cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag
detection, peak detection, and voltage phase measurement. All data computed by the CE is dependent on the selected meter
equation as given by EQU (in I/O RAM). As a function of EQU, the element components V0 through I2 take on different
meanings.
•
EQU
Watt & VAR Formula
(WSUM/VARSUM)
Element Input Mapping
W0SUM/
VAR0SUM
0
VA IA (1 element, 2W 1φ)
1
VA*(IA-IB)/2
(1 element, 3W 1φ)
Page: 66 of 98
W1SUM/
VAR1SUM
I0SQSUM
I1SQSUM
VA*IA
VA*IB
IA
IB
VA*(IA-IB)/2
VA*IB
IA-IB
IB
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Single-Phase Energy Meter IC
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CE RAM Locations
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through 7, as listed below.
Address (HEX)
Name
Description
00
01
02
03
04
05
06
07
IA
VA
IB
TEMP
--
Phase A current
Phase A voltage
Phase B current
Reserved
Reserved
Reserved
Temperature
Reserved
CE Status Word
Since the CE_BUSY interrupt occurs at 2520.6Hz (or at 3276.8Hz when MUX_DIV = 2), it is desirable to minimize the
computation required in the interrupt handler of the MPU. The MPU can read CESTATUS at every CE_BUSY interrupt.
CE
Address
Name
0x51
CESTATUS
Description
See description of CE status word below
The CE Status Word is useful for generating early warnings to the MPU. It contains sag warnings for phase A, as well as F0,
the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of voltage
and input AC signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage.
CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt).
Note: The CE does not store sag alarms from one code pass to the next. CESTATUS is refreshed at every CE_BUSY
interrupt and remains valid for up to 100µs after the CE_BUSY interrupt occurs. Unsynchronized read operations of
CESTATUS will yield unreliable results.
The significance of the bits in CESTATUS is shown in the table below:
CESTATUS
[bit]
Name
31-29
Not Used
28
F0
27
RESERVED
26
RESERVED
25
SAG_A
24-0
Not Used
Page: 67 of 98
Description
These unused bits will always be zero.
F0 is a square wave at the exact fundamental input frequency.
Normally zero. Becomes one when VA remains below SAG_THR for SAG_CNT
samples. Will not return to zero until VA rises above SAG_THR.
These unused bits will always be zero.
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For generating proper status information, the CE is initialized by the MPU using SAG_THR (default of 80V RMS at the meter
input if VMAX=600V) and SAG_CNT (default 80 samples). Using the default value for SAG_CNT, the peak-to-peak signal has to
be below SAG_THR value for 32 milliseconds to activate the SAG_X status bits.
CE
Address
Name
Default
Description
Meter voltage inputs must be above this threshold to prevent sag alarms.
LSB = VMAX * 3.3243*10-9 V peak.
0x31
+56,722,300
(0x361837C)
SAG_THR
For example, if a sag threshold of 80V RMS is desired,
2
SAG _ THR = VMAX ⋅803.3243
⋅10 −9
0x32
SA
G_
C
NT
Number of consecutive voltage samples below SAG_THR before a sag alarm
is declared. 80*397µs = 31.8ms (for MUX_DIV = 1).
80
CE Transfer Variables
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer
variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout
each accumulation interval. In this data sheet, the names of CE transfer variables always end with _X.
Fundamental Power Measurement Variables
The table below describes each transfer variable for fundamental power measurement. All variables are signed 32 bit integers.
Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the
integration time is 1 second. Additionally, the hardware will not permit output values to ‘fold back’ upon overflow.
CE
Address
Name
42
RESERVED
43
W0SUM_X
44
W1SUM_X
45
RESERVED
46
RESERVED
47
VAR0SUM_X
48
VAR1SUM_X
49
RESERVED
Description
The sum of Watt samples from each wattmeter element (In_8 is the gain
configured by IA_SHUNT or IB_SHUNT).
LSB = 6.6952*10-13 VMAX IMAX / In_8 Wh (for MUX_DIV = 1)
-13
LSB = 5.1501*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 2)
The sum of VAR samples from each wattmeter element (In_8 is the gain
configured by IA_SHUNT or IB_SHUNT).
-13
LSB = 6.6952*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 1)
-13
LSB = 5.1501*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 2)
WxSUM_X is the Wh value accumulated for element ‘X’ in the last accumulation interval and can be computed based on the
specified LSB value.
For example with VMAX = 600V and IMAX = 208A, LSB (for WxSUM_X ) is 0.08356 µWh (MUX_DIV = 1).
Page: 68 of 98
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Instantaneous Power Measurement Variables
The FREQSEL Register selects the input phase used for frequency measurement and for the MAIN_EDGE counter. The
frequency measurement is implemented using the frequency locked loop of the CE for the selected phase.
IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval.
INSQSUM_X can be used for computing the neutral current.
CE
Address
Name
Description
33
RESERVED
Fundamental frequency.
LSB
41
FREQ_X
or
4A
I0SQSUM_X
4B
I1SQSUM_X
4C
RESERVED
4D
RESERVED
4E
V0SQSUM_X
4F
RESERVED
50
RESERVED
≡
FS
≈ 0.587 ⋅ 10 −6 Hz for MUX_DIV = 1
32
2
FS
≈ 0.763 ⋅ 10 −6 Hz for MUX_DIV = 2
2 32
The sum of squared current samples from each element.
LSB = 6.6952*10-13 IMAX2 / In_82 A2h (for MUX_DIV = 1)
-13
2
2 2
LSB = 5.1501*10 IMAX / In_8 A h (for MUX_DIV = 2)
The sum of squared voltage samples from each element.
LSB= 6.6952*10-13 VMAX2 V2h (for MUX_DIV = 1)
-13
2 2
LSB = 5.1501*10 VMAX V h (for MUX_DIV = 2)
The RMS values can be computed by the MPU from the squared current and voltage samples as per the formulae:
IxRMS =
IxSQSUM ⋅ LSB ⋅ 3600 ⋅ FS
N ACC
VxRMS =
VxSQSUM ⋅ LSB ⋅ 3600 ⋅ FS
N ACC
Note: FS = 2520.6Hz (MUX_DIV = 1) or 3276.8Hz (MUX_DIV = 2)
Other Measurement Parameters
MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X is the number of halfcycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQSEL register.
CE
Address
Name
52
RESERVED
53
RESERVED
55
MAINEDGE_X
Page: 69 of 98
Description
The number of edge crossings of the selected voltage in the previous
accumulation interval. Edge crossings are either direction and are debounced.
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
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Temperature Measurement and Temperature Compensation
Input variables: TEMP_NOM is the reference value for temperature measurement, i.e. when this value is set with
TEMP_RAW_X at known temperature. The 71M6511/6511H measures temperature with reference to this value.
DEGSCALE is the slope or rate of temperature increase or decrease from the TEMP_NOM for TEMP_X measurement.
PPMC and PPMC2 are temperature compensation coefficients. Their values should reflect the characteristics of the band gap
voltage reference of the chip. PPMC and PPMC2 follow the square law characteristics to compensate for nonlinear temperature
behaviors, when the 71M6511/6511H is in internal temperature compensation mode.
CE
Addres
s
Name
Defaul
t
0x11
TEMP_NOM
0
0x30
DEGSCALE
9585
Description
During calibration, the value of TEMP_RAW_X should be placed in
TEMP_NOM.
Scale factor for TEMP_X.
TEMP_X = -DEGSCALE*2-22*(TEMP_RAW_X-TEMP_NOM).
Should be 15 or 0. When 15, causes the CE to ignore internal temperature compensation and permits the MPU to control GAIN_ADJ.
When internal temperature compensation is selected, GAIN_ADJ will be:
0x38
0x39
0x3A
0
EXT_TEMP
PPMC
PPMC
2
0
0
TEMP _ X ⋅ PPMC TEMP _ X 2 ⋅ PPMC 2
GAIN _ ADJ = 16384 + floor 1 +
+
214
2 23
Default is 0 (internal compensation).
Linear temperature compensation factor. Equals the linear temperature
coefficient (PPM/°C) of VREF multiplied by 26.84, or TC1 (expressed in
µV/°C, see Electrical Specifications) multiplied by 22.46. A positive
value will cause the meter to run faster when hot. The compensation
factor affects both V and I and will therefore have a double effect on
products.
Square-law temperature compensation factor. Equals the square-law
temperature coefficient (PPM/°C2) of VREF multiplied by 1374, or TC2
2
(expressed in µV/°C , see Electrical Specifications) multiplied by
1150.1. A positive value will cause the meter to run faster when hot. The
compensation factor affects both V and I and will therefore have a
double effect on products.
EXT_TEMP allows the MPU to select between direct control of GAIN_ADJ or management of GAIN_ADJ by the CE, based on
TEMP_X and the temperature correction coefficients PPMC and PPMC2.
Output variables: TEMP_X is the temperature measurement from reference temperature of TEMP_NOM. TEMP_X is
computed using TEMP_RAW_X and DEGSCALE. This quantity is positive when the temperature is above the reference and is
negative for cold temperatures.
TEMP_RAW_X is the raw processed value from ADC output and is the fundamental quantity for temperature measurement.
TEMP_RAW_X is less than TEMP_NOM at higher temperatures. TEMP_RAW_X is more than TEMP_NOM for cooler
temperatures than reference temperature.
Page: 70 of 98
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NOVEMBER 2010
GAIN_ADJ is a scaling factor for power measurements based on temperature (when in internal temperature compensation
mode). In general, for higher temperatures it is lower than 16384 and higher than 16384 for lower temperatures. GAIN_ADJ is
mainly dependent on the PPMC, PPMC2 and TEMP_X register values. This parameter is automatically computed by the CE
and is used by the CE for temperature compensation.
CE
Address
Name
Description
0x40
TEMP_X
0x54
TEMP_RAW_X
0x2E
GAIN_ADJ
0
Deviation from Calibration temperature. LSB = 0.1 C.
Filtered, unscaled reading from temperature sensor. This
value should be written to TEMP_NOM during meter
calibration.
Scales all voltage and current inputs. 16384 provides
unity gain. Default is 16384. If EXT_TMP = 0, GAIN_ADJ
is updated by the CE.
Pulse Generation
Input variables: The combination of the PULSE_SLOW and PULSE_FAST parameters control the speed of the pulse rate. The
default values of 1 and 1 will maintain the original pulse rate given by the Kh equation.
WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The lower WRATE it is the
slower is the pulse rate for measured power quantity. The metering constant Kh is derived from WRATE as the amount of
energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120V and 30A results in one
pulse per second. If the load is 240V at 150A, ten pulses per second will be generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE > 0. In this case, the pulse rate is determined by
APULSEW and APULSER. The MPU has to load the source for pulse generation in APULSEW and APULSER to generate pulses.
Irrespective of the EXT_PULSE, status the output pulse rate controlled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE > 0, the MPU is providing the source for pulse generation. If EXT_PULSE is negative, W0SUM_X
and VAR0SUM_X are the default pulse generation sources. In this case, creep cannot be controlled since it is an MPU function.
The maximum pulse rate is FS /2= 1260.3Hz (MUX_DIV = 1).
PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. When
MUX_DIV = 1, the minimum pulse width possible is 397µs.
The maximum time jitter is 397µs (for MUX_DIV = 1) and is independent of the number of pulses measured. Thus, if the pulse
generator is monitored for 1 second, the peak jitter is 397PPM. After 10 seconds, the peak jitter is 39.7PPM. The average jitter
is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its
maximum rate without exhibiting any roll-over characteristics. The actual pulse rate, using WSUM as an example, is:
RATE =
X ⋅ WRATE ⋅ WSUM ⋅ FS
Hz
2 46
Where FS = 2520.6Hz (sampling frequency for MUX_DIV = 1) or 3276.8Hz (sampling frequency for MUX_DIV = 2) and X is the
pulse gain factor derived from CE variables PULSE_SLOW and PULSE_FAST (see table below).
Page: 71 of 98
© 2005–2010 Teridian Semiconductor Corporation
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71M6511/71M6511H
Single-Phase Energy Meter IC
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DATA SHEET
NOVEMBER 2010
CE
Address
0x28
0x29
Name
PULSE_SLOW
PULSE_FAST
Default
1
1
Description
When PULSE_SLOW > 0, the pulse generator input is reduced 64x.
When PULSE_FAST > 0, the pulse generator input is increased 16x.
These two parameters control the pulse gain factor X (see table below).
Allowed values are either 1 or –1.
X
PULSE_SLOW
PULSE_FAST
1.5 * 22 = 6
-1
-1
6
-1
1
-4
1.5 * 2 = 0.09375
1
-1
1.5
1 (default)
1 (default)
1.5 * 2 = 96
0x2D
WRATE
1556
Kh =
VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse (for MUX_DIV = 1).
VMAX*IMAX*36.2409 / (In_8*WRATE*NACC*X) Wh/pulse (for MUX_DIV = 2).
0x36
SUM_PRE
2520
PRE_SAMPS * SUM_CYCLES. This variable is also called NACC.
0x37
EXT_PULSE
15
Should be 15 or 0. When zero, causes the pulse generators to respond to
WSUM_X and VARSUM_X. Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
50
The maximum pulse width (low-going pulse) is:
(2 * PULSE_WIDTH + 1) * 397µs (for MUX_DIV = 1)
(2 * PULSE_WIDTH + 1) * 305µs (for MUX_DIV = 2)
0 is a legitimate value.
0
Wh pulse generator input, to be updated by the MPU when using external pulse
generation (see DIO_PW bit). The output pulse rate is:
-32
-14
APULSEW * FS * 2 * WRATE * 2
This input is buffered and can be updated by the MPU during a computation interval. The change will take effect at the beginning of the next interval.
0
VARh pulse generator input to be updated by the MPU when using external
pulse generation (see DIO_PV bit). The output pulse rate is:
-32
-14
APULSER * FS*2 * WRATE * 2
This input is buffered and can be updated by the MPU during a computation interval. The change will take effect at the beginning of the next interval.
0x3C
0x26
0x27
Page: 72 of 98
PULSE_WIDTH
APULSEW
APULSER
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V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
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Current Shunt Variables
Input variables: IA_SHUNT and IB_SHUNT can configure the current inputs to accept shunt resistor sensors. In this case the
CE provides an additional gain of 8 to the current inputs. This will enable the pulse rate to change by 8 times. In order to
maintain a normal pulse rate WRATE may have to be decreased by 8 times. Whenever IA_SHUNT or IB_SHUNT are set to 1 or
a positive number, In_8 is assigned a value of 8 in the equation for Kh.
CE
Address
Name
Default
2A
IA_SHUNT
-1
2B
IB_SHUNT
-1
2C
RESERVED
Description
When +1, these variables increase the respective current gain by 8. The
gain factor controlled by In_SHUNT is referred to as In_8 throughout this
document. Allowed values are 1 or –1. For example, if IB_SHUNT=-1, IB_8
= 1, if IB_SHUNT = 1, IB_8 = 8.
IA_SHUNT corresponds to IA_8, IB_SHUNT corresponds to IB_8.
CE Calibration Parameters
The table below lists the parameters that are typically entered to affect calibration of meter accuracy.
CE
Address
Name
Default
8
CAL_IA
16384
9
CAL_VA
16384
A
CAL_IB
16384
B
RESERVED
C
RESERVED
D
RESERVED
E
PHADJ_A
0
Description
These constants control the gain of their respective channels. The nominal
14
value for each parameters is 2 = 16384. The gain of each channel is directly
proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow,
CAL should be scaled by 1/(1 – 0.01).
These two constants control the CT phase compensation. No compensation
occurs when PHADJ_X = 0. As PHADJ_X is increased, more compensation
15
(lag) is introduced. Range: ±2 – 1. If it is desired to delay the current by the
angle Φ:
PHADJ _ X = 2 20
F
0
a ⋅ TANΦ
b − c ⋅ TANΦ
a = 1 + (1 − 2 −9 ) 2 − 2(1 − 2 −9 ) cos(2πF0T )
F0T =
F0
FS
b = (1 − 2 −9 ) sin( 2πF0T )
c = 1 − (1 − 2 −9 ) cos(2πF0T )
10
Page: 73 of 98
0
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V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
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DATA SHEET
NOVEMBER 2010
Other CE Parameters
The table below shows CE parameters used for suppression of noise due to scaling and truncation effects as well as scaling
factors.
CE
Address
Name
Default
2F
22
QUANTA
QUANTB
0
0
These parameters are added to the Watt calculation to compensate for input
noise and truncation.
-10
LSB=(VMAX*IMAX / IA_8) *7.4162*10 W for phase A, and
-10
LSB=(VMAX*IMAX / IB_8) *7.4162*10 W for phase B
34
24
QUANT_VARA
QUANT_VARB
0
0
These parameters are added to the VAR calculation to compensate for input
noise and truncation.
-10
LSB = (VMAX*IMAX / IA_8) * 7.4162*10 W for phase A, and
-10
LSB = (VMAX*IMAX / IB_8) * 7.4162*10 W for phase B
0
0
These parameters are added to compensate for input noise and truncation in
2
2
the squaring calculations for I and V .
2
-10 2
LSB=VMAX *7.4162*10 V ,
LSB= (IMAX2/IA_82)*7.4162*10-10 A2 for phase A and
2
2
-10 2
LSB= (IMAX /IB_8 )*7.4162*10 A for phase B.
35
23
3B
Page: 74 of 98
QUANT_IA
QUANT_IB
KVAR
6448
12880
Description
Scale factor for the VAR calculation. The default value of KVAR should never
need to be changed.
for MUX_DIV = 1
for MUX_DIV = 2
© 2005–2010 Teridian Semiconductor Corporation
V2.7
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
TYPICAL PERFORMANCE DATA
Wh Accuracy at Room Temperature
Figure 24: Wh Accuracy, 0.3A - 200A/240V
VARh Accuracy at Room Temperature
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance
Page: 75 of 98
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Harmonic Performance
2
1
0
Error [%]
-1
-2
-3
50Hz Harmonic Data
60Hz Harmonic Data
-4
-5
-6
-7
-8
1
3
5
7
9
11
13
15
17
19
21
23
25
Harmonic
Test performed at current distortion amplitude of 40% and voltage distortion amplitude of 10% as per IEC 62053, part 22.
Figure 26: Meter Accuracy over Harmonics at 240V, 30A
Page: 76 of 98
© 2005–2010 Teridian Semiconductor Corporation
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Single-Phase Energy Meter IC
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DATA SHEET
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APPLICATION INFORMATION
Connection of Sensors (CT, Resistive Shunt, Rogowski Coil)
Figure 27 and Figure 28 show how resistive dividers, current transformers, restive shunts, and Rogowski coils are connected
to the voltage and current inputs of the 71M6511.
The analog input pins of the 71M6511 are designed for sensors with low source impedance. RC filters with resistance
values higher than those implemented in the Teridian Demo Boards should be avoided.
VA = Vin * Rout/(Rout + Rin)
VA
Rin
Vin
Rout
Figure 27: Resistive Voltage Divider (left), Current
Transformer
(right)
Vout = dIin /dt
R
Vout
Iin
1/N
Vout = dIin /dt
IA
R
Vout
VC
V3P3
Figure 28: Resistive Shunt (left), Rogowski Coil (right)
Distinction between 71M6511 and 71M6511H Parts
71M6511H parts go through a process of trimming and characterization during production that make them suitable to highaccuracy applications.
The first process applied to the 71M6511H is the trimming of the reference voltage, which is guaranteed to have accuracy over
temperature of better that ±10PPM/°C.
The second process applied to the 71M6511H is the characterization of the reference voltage over temperature. The
coefficients for the reference voltage are stored in so-called trim fuses (I/O RAM registers TRIMBGA, TRIMBGB, TRIMM[2:0].
The MPU program can read these trim fuses and calculate the correction coefficients PPM1 and PPM2 per the formulae given
in the Performance Specifications section (VREF, VBIAS). See the Temperature Compensation section for details.
The fuse TRIMBGB is non-zero for the 71M6511H part and zero for the 71M6511 part.
Trim fuse information is not available for non-H parts. Thus, the standard are to be applied. These settings are:
•
PPMC = TC1 * 22.46 = –149
•
PPMC2 = TC2 * 1150.1 = –392
Page: 77 of 98
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Single-Phase Energy Meter IC
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NOVEMBER 2010
Temperature Compensation and Mains Frequency Stabilization for the RTC
The accuracy of the RTC depends on the stability of the external crystal. Crystals vary in terms of initial accuracy as well as in
terms of behavior over temperature. The flexibility provided by the MPU allows for compensation of the RTC using the substrate temperature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL,
Y_CALC, and Y_CAL_C2 have to be calculated. Provided the IC substrate temperatures tracks the crystal temperature, the
coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count, using the
RTC_DEC_SEC or RTC_INC_SEC registers in I/O RAM.
It is not recommended to measure crystal frequency directly due to the error introduced by the measurement probes. A
practical method to measure the crystal frequency (when installed on the PCB with the 71M6511) is to have a DIO pin toggle
every second, based on the RTC interrupt, with all other interrupts disabled. When this signal is measured with a precision
timer, the crystal frequency can be obtained from the measured time period t (in µs):
f = 32768
10 6 µs
t
Example: Let us assume a crystal characterized by the measurements shown in Table 62. The values show that even at
nominal temperature (the temperature at which the chip was calibrated for energy), the deviation from the ideal crystal
frequency is 11.6 PPM, resulting in about one second inaccuracy per day, i.e. more than some standards allow.
Deviation from
Nominal
Temperature [°C]
Measured
Frequency [Hz]
Deviation from
Nominal
Frequency [PPM]
+50
32767.98
-0.61
+25
32768.28
8.545
0
32768.38
11.597
-25
32768.08
2.441
-50
32767.58
-12.817
Table 62: Frequency over Temperature
As Figure 29 shows, even a constant compensation would not bring much improvement, since the temperature characteristics
of the crystal are a mix of constant, linear, and quadratic effects (in commercially available crystals, the constant and quadratic
effects are dominant).
32768.5
32768.4
32768.3
32768.2
32768.1
32768
32767.9
32767.8
32767.7
32767.6
32767.5
-50
-25
0
25
50
Figure 29: Crystal Frequency over Temperature
The temperature characteristics of the crystal are obtained from the curve in Figure 29 by curve-fitting the PPM deviations. A
fairly close curve fit is achieved with the coefficients a = 10.89, b = 0.122, and c = –0.00714 (see Figure 30).
Page: 78 of 98
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71M6511/71M6511H
Single-Phase Energy Meter IC
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DATA SHEET
NOVEMBER 2010
When applying the inverted coefficients, a curve (see Figure 30) will result that effectively neutralizes the original crystal
characteristics. The frequencies were calculated using the fit coefficients as follows:
a
b
c
f = f nom ⋅ 1 + 6 + T 6 + T 2 6
10
10
10
32768.5
32768.4
32768.3
32768.2
32768.1
32768
32767.9
32767.8
crystal
32767.7
curve fit
32767.6
inverse curve
32767.5
-50
-25
0
25
50
Figure 30: Crystal Compensation
The MPU Demo Code supplied with the TERIDIAN Demo Kits has a direct interface for these coefficients and it directly controls the RTC_DEC_SEC or RTC_INC_SEC registers. The Demo Code uses the coefficients in the following form:
CORRECTION ( ppm) =
Y _ CAL
Y _ CALC
Y _ CALC 2
+T ⋅
+T2 ⋅
10
100
1000
Note that the coefficients are scaled by 10, 100, and 1000 to provide more resolution. For our example case, the coefficients
would then become (after rounding, since the Demo Code accepts only integers):
Y_CAL = 109, Y_CALC = 12, Y_CALC2 = 7
Alternatively, the mains frequency may be used to stabilize or check the function of the RTC. For this purpose, the CE
provides a count of the zero crossings detected for the selected line voltage in the MAIN_EDGE_X address. This count is
equivalent to twice the line frequency, and can be used to synchronize and/or correct the RTC.
External Temperature Compensation
In a production electricity meter, the 71M6511 or 71M6511H is not the only component contributing to temperature dependency. In fact, a whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors)
will exhibit slight or pronounced temperature effects. Since the output of the on-chip temperature sensor is accessible to the
MPU, temperature-compensation mechanisms with great flexibility, i.e. beyond the capabilities implemented in the CE, are
possible.
Temperature Measurement
Temperature measurement can be implemented with the following steps:
1)
At a known temperature TN, read the TEMP_RAW register of the CE and write the value into TEMP_NOM.
2)
Read the TEMP_X register at the known temperature. The obtained value should be
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