71M6515H-IGTR/F

19-5361; Rev 7/11 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 FEATURES The 71M6515H is a high-accuracy analog front-end (AFE) IC that provides measurements for 3-quadrant 3-phase metering. The combination of a 21-bit sigma-delta A/D converter with a six-input analog front-end, a thermally compensated high-precision reference, and a compute engine results in high accuracy and wide dynamic range. Our Single Converter Technology® reduces cross talk and cost. This IC also provides RTC and battery backup for time-of-use (TOU) metering. High Accuracy  < 0.1% Wh accuracy over 2000:1 range  Exceeds IEC 62053/ANSIC 12.20 specifications  Up to 10ppm/C precision ultra-stable voltage reference  Single Converter Technology reduces cross talk and power consumption  Six sensor inputs—referenced to V3P3  Compatible with CTs, resistive shunts and Rogowski Coil sensors  Digital temperature compensation  Sag detection  Measures Wh, VARh, VAh, Vrms, Irms, V-to-V phase and load angle on each phase  Four-quadrant metering.  Four low-jitter pulse outputs from selectable measurements  Four pulse count registers  Selectable default status for pulse pins  Same calibration data for 46Hz to 64Hz line frequency  Broad CT phase compensation (±7deg) VOLTAGE CURRENT GENERAL DESCRIPTION Battery UART, IRQZ RTC COMPUTE ENGINE HOST PROCESSOR RAM SSI VOLTAGE REFERENCE CONTROL DIO TERIDIAN 71M6515H Figure 1: Meter Block Diagram As shown in the block diagram (Figure 1), the host processor communicates with the 71M6515H through a UART interface using the programmable IRQZ interrupt. The 71M6515H calculates and accumulates meter measurements for each accumulation interval. A high-speed synchronous serial port (SSI) is provided to facilitate high-end metering. Integrated rectifying functions on the battery-backup circuit enable minimal external component usage and minimum back-up current. Also, eight multipurpose pins are provided for control of peripherals. Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc. Page: 1 of 60 Battery Backup  Powers real-time clock during power supply outage  Compatible with Li-ion, NiCd, or super capacitor  Battery backup current 2µA typical at 25°C External Data Interface  UART control interface, two selectable data rates  8 general-purpose I/O pins with alarm capability  5 or 10MHz selectable high-speed synchronous serial output for DSP interface  IRQ output signal for alarms and end of measurement intervals  Alarms on voltage sag, overvoltage, overcurrent Low System Cost  Power consumption 30mW at 3.3V typical  Real-time clock with temperature compensation  Built-in power-fault detection  Single 32kHz crystal time base  Single-supply operation (3.3V)  64-lead LQFP package © 20052011 Teridian Semiconductor Corporation 1.6 VREF PULSEW PULSER V3P3A GNDA GNDA ∆Σ ADC CONVERTER IA VA IB VB IC VC GNDD MUX VOLT REG V3P3A + V3P3D 21 GNDD VREF VX TEMP VREF GNDD V2P5 MUXSYNC 2.5V to logic VBIAS (1.5V) CALCULATIONS SSI INTERFACE SSCLK SSDATA OUTPUT VALUES: Whr (A, B, C) VARhr (A, B, C) VAhr (A, B, C) Vrms (A, B, C) Irms (A, B, C) Iphase (A, B, C) Frequency (Selected Phase) Temperature SFR SRDY SYSTEM CLOCKS CK_GEN CKTEST ALARMS: Voltage Sag (A, B, C) Zero Cross (Selected Phase) Over-Voltage (All) Over-Current (All) D0-D7 State Change BATTERY BACKUP OSC (32KHz) XIN XOUT RTC VBAT PULSE4 PULSE3 PULSE_INIT BAUDRATE DATA RAM CONTROL MISC TX IRQZ UART RX I/O CONTROL D0 D4 D1 D5 D6 D2 Change of State (D0...D7) D3 D7 TEST VFLT FAULT DETECT VBIAS (1.5V) GNDD V3P3 TMUXOUT VX RESERVED 64 PINS -- 64 TQFP RESETZ March 3, 2008 Figure 2: IC Functional Block Diagram ELECTRICAL SPECIFICATIONS Page: 2 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3D, V3P3A |V3P3D – V3P3A| VBAT GNDD Analog Output Pins: −0.5V to 4.6V 0V to 0.5V -0.5V to 4.6V -0.5V to +0.5V -1mA to 1mA, -0.5V to V3P3A+0.5V -1mA to 1mA, -0.5 to 3.0V VREF V2P5 Analog Input Pins: IA, VA, IB, VB, IC, VC VFLT, VX XIN, XOUT Digital Input Pins: RX D0…D7 All other pins -0.5V to V3P3A+1.0V -0.5V to V3P3A+0.5V -0.5V to 3.0V -0.5V to 3.6V -0.5V to 6V -0.5V to V3P3D+0.5V Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature – 10 second duration ESD Stress Pins IA, VA, IB, VB, IC, VC, RX, TX All other pins 140 °C 125 °C −45 °C to 165 °C 250 °C 6kV 2kV Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. RECOMMENDED OPERATING CONDITIONS PARAMETER CONDITION MIN 3.3V Supply Voltage (V3P3A, V3P3D)+ Normal Operation Battery Backup No Battery Battery Backup 3.0 3.3 3.6 V 0 3.8 V Externally Connect to V3P3D 2.0 3.8 V -40 85 ºC VBAT Operating Temperature + TYP MAX UNIT V3P3A and V3P3D should be shorted together on the circuit board. GNDD and GNDA should also be shorted on the circuit board. Page: 3 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 LOGIC LEVELS PARAMETER CONDITION Digital high-level input voltage, VIH Digital low-level input voltage, VIL ILOAD = 1mA ILOAD = 15mA ILOAD = 1mA ILOAD = 15mA VIN=0V Input pull-up current, IIL RESETZ E_RXTX, E_ISYNC/BRKRQ E_RST Other digital inputs Input pull down current, IIH TEST Other digital inputs 1 TYP 2 −0.3 V3P3D –0.4 V3P3D0.61 0 Digital high-level output voltage VOH Digital low-level output voltage VOL MIN MAX UNIT V3P3D 0.8 V V V3P3D V V 0.4 0.81 V V 10 10 10 -1 100 100 100 +1 µA µA µA µA 10 -1 100 +1 µA µA VIN=V3P3D Guaranteed by design; not production tested. SUPPLY CURRENT PARAMETER V3P3A + V3P3D V3P3A current V3P3D current VBAT current VBAT current, VBAT=3.6V 1 CONDITION MIN Normal Operation, V3P3A=V3P3D=3.3V VBAT=3.6V TYP MAX UNIT 8.8 3.7 5.1 2 11.5 4.7 6.8 300 4 mA mA mA nA µA 4 12 -300 Battery backup, ≤25°C V3P3A=V3P3D=0V 85°C fOSC = 32kHz 1 µA Guaranteed by design; not production tested. VREF Page: 4 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 PARAMETER CONDITION MIN MAX VREF output voltage, VNOM(25) VREF output impedance VNOM definition 2 Ta = 25ºC 1.193 1.195 1.197 ILOAD = 10µA, -10µA 2.5 VNOM(T) = VREF(22) + (T-22)TC1 + (T-22)2TC2 VREF(T) deviation from VNOM(T) Ta = -40ºC to +85ºC, for 71M6515H-IGT/F VREF (T ) − VNOM (T ) 10 VNOM max(| T − 22 |,40) 6 Ta = -40ºC to +85ºC, for 71M6515H-IGTW/F 1 +10 1 +40 -10 -40 ±25 VREF aging 1 TYP UNIT V kΩ V 1 PPM/ºC 1 PPM/ºC PPM/year Guaranteed by design; not production tested. 2 This relationship describes the nominal behavior of VREF at different temperatures. The values of TC1 and TC2 are device specific in general and are programmed into the device at manufacturing. Page: 5 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 2.5V VOLTAGE REGULATOR PARAMETER CONDITION Reduce V3P3 until V2P5 drops 200mV RESETZ=1, ILOAD=0 Voltage Overhead V3P3D-V2P5 PSRR MIN ΔV2P5/ΔV3P3D TYP -3 MAX UNIT 440 mV +3 mV/V RTC PARAMETER CONDITION Range for date MIN TYP MAX UNIT 2000 -- 2255 year MIN TYP MAX UNIT 11 µs µs RESETZ PARAMETER CONDITION Reset pulse width Reset pulse fall time 1 5 Guaranteed by design; not production tested. CRYSTAL OSCILLATOR PARAMETER Maximum Output Power to Crystal4 Xin to Xout Capacitance Capacitance to DGND Xin Xout Watchdog RTC_OK threshold CONDITION MIN TYP MAX 1 3 5 5 UNIT µW pF 25 pF pF kHz MAX UNIT TEMPERATURE SENSOR PARAMETER CONDITION Nominal Sensitivity (Sn) Nominal Offset (Nn) 4 MIN TA=25ºC, TA=85ºC Nominal relationship: N(T)= Sn*T+Nn 4 TYP -900 LSB/ºC 40000 0 LSB Temperature Error, relative to 25ºC error ERR = (T − 25) − 1 ( N (T ) − N (25)) Sn TA = -40ºC to +85ºC -31 +31 ºC Guaranteed by design; not production tested. Page: 6 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 PULSE GENERATOR TIMING SPECIFICATIONS PARAMETER CONDITION MIN TYP MAX UNIT 7.56 kHz 0.15 kHz 0.15 kHz CONDITION VALUE UNIT Air velocity 0 m/s. Part soldered to PCB. 63.7 °C/W APULSE=231-1, WRATE=215-1 PULSE3=231-1, WRATE=215-1 PULSEW, PULSER maximum rate PULSE3, PULSE4 maximum rate Pulse count frequency all pulse outputs THERMAL CHARACTERISTICS PARAMETER Thermal resistance, junction to ambient (RθJA ) UART HOST INTERFACE PARAMETER CONDITION Baud Rate Character set Data Format Byte-to-byte delay (6515H times out after maximum delay) Byte-to-byte delay Response time to read command Response time to read command when 71M6515H is post-processing data Host sending data to 6515H 6515H sending data to host 6515H has data ready Data not ready CE_ONLY = 1 CE_ONLY = 0 and VAH_SELECT = 0 CE_ONLY = 0 and VAH_SELECT = 1 MIN TYP MAX UNIT 19.2 binary 8N1 38.4 kBaud 10 20 ms 0 0.1 ms 0.5 2 ms 40 ms 80 ms 350 ms MAX UNIT -250 250 mV peak -101 +101 µV/V 90 dB dB kΩ ADC CONVERTER, V3P3 REFERENCED PARAMETER CONDITION Usable Input Range (Vin-V3P3A) Voltage to Current cross talk: Page: 7 of 60 TYP Vin = 200mV peak, 65Hz, on VA, VB, or VC 10 6 *Vcrosstalk cos(∠Vin − ∠Vcrosstalk ) Vcrosstalk = largest Vin measurement on IA, IB, or THD (First 10 harmonics) 250mV-pk 20mV-pk Input Impedance MIN IC Vin=65Hz, 64kpts FFT, BlackmanHarris window Vin=65Hz -75 -90 40 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 Temperature Coefficient of Input Impedance LSB size Digital Full Scale ADC Gain Error vs. %Power Supply Variation Vin=65Hz Ω/°C 355 +884736 nV/LSB LSB Vin=200mV pk, 65Hz V3P3A=3.0V, 3.6V 10 6 ∆Nout PK 357nV / VIN 100 ∆V 3P3 A / 3.3 Input Offset (Vin-V3P3A) 1 1.7 -10 50 PPM/ % +10 mV Guaranteed by design; not production tested. RECOMMENDED EXTERNAL COMPONENTS NAME C1 C2 FROM V3P3A V3P3D TO AGND DGND XTAL XIN XOUT CXS CXL C2P5 XIN XOUT V2P5 AGND AGND DGND FUNCTION Bypass capacitor for 3.3V supply Bypass capacitor for 3.3V supply 32.768kHz crystal – electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.5pF Load capacitor for crystal (depends on crystal specs and board parasitics). Bypass capacitor for V2P5 VALUE ≥0.1±20% ≥0.1±20% UNIT µF µF 32.768 kHz 27±10% 27±10% ≥0.1±20% pF pF µF FOOTNOTES: 1 This spec is guaranteed, has been verified in production samples, but is not measured in production. 2 This spec is guaranteed, has been verified in production samples, but is measured in production only at DC. 3 This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference Page: 8 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 VB V3P3A GNDA 50 49 53 VC VA 54 51 IC 55 52 IA IB 56 VX VREF 57 VFLT 59 58 XIN GNDA 61 60 XOUT GNDD 62 RESERVED 64 63 PIN CONFIGURATION AND PIN FUNCTION GNDD 1 48 GNDD RESERVED TMUXOUT /RTM TX 2 47 RESETZ 3 46 V2P5 45 VBAT 44 RX SSCLK 5 CKTEST 6 V3P3D 7 SSDATA SFR TERIDIAN 4 71M6515H-IGT Or 71M6515H-IGTW 8 9 43 RESERVED 42 D0 41 IRQZ 40 PULSE_INIT 39 D6 10 RESERVED 11 38 D5 RESERVED 12 37 D4 RESERVED 13 36 PULSER PULSE3 14 35 PULSEW PULSE4 15 34 UARTCSZ 33 D7 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESERVED RESERVED D1 D2 D3 SRDY MUX_SYNC RESERVED GNDD RESERVED RESERVED RESERVED RESERVED RESERVED 18 17 16 RESERVED BAUD_RATE 32 RESERVED Pins marked RESERVED should be left unconnected during normal use. Page: 9 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 Analog Pin Description IA, IB, IC VA, VB, VC VFLT VX VREF Pin No. 56 55 54 53 52 51 59 58 57 XIN, XOUT 61 63 Name Type Circuit I 6 I 6 I I I/O 7 6 9 I 8 Description Line Current Sense Inputs: Voltage inputs to the internal A/D converter. Typically, they are connected to the output of a current transformer. The input is referenced to V3P3A. Unused pins must be tied to V3P3A. Line Voltage Sense Inputs: Voltage inputs to the internal A/D converter. Typically, they are connected to the output of a resistor divider. The input is referenced to V3P3A. Unused pins must be tied to V3P3A. Power Fault Input. This pin must be tied to V3P3A. Auxiliary input (not used). This pin should be tied to VREF. Voltage Reference for the ADC. Crystal Inputs: A 32768Hz crystal should be connected across these pins. Typically, a 15pF capacitor is also connected from each pin to GNDA. See the datasheet of the crystal manufacturer for details. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”. Digital Pin Description Unless otherwise indicated, all inputs and outputs are standard CMOS. Inputs do NOT have internal pull-ups or pull-downs. Pin No. Type Circuit CKTEST 6 I/O 4 D0 D1 D2 D3 D4 D5 D6 D7 PULSE4 PULSE3 42 21 22 23 37 38 39 33 15 14 PULSE_INIT Name I/O 3, 4 O O 4 4 40 I 3 BAUD_RATE 16 I 3 IRQZ 41 O 4 MUXSYNC 25 O 4 RESETZ 47 I 1 Page: 10 of 60 Description Clock PLL output. Can be enabled and disabled by CKOUT_DSB (see Status Mask). Input/output pins 0 through 7. These pins must be terminated to V3P3D or ground if configured as input pins. D0 through D7 are high impedance after reset or power-up and are configured as outputs and driven low 140ms after RESETZ goes high. The fourth pulse generator output The third pulse generator output The pulse output initial power-up voltage (0: 0V, 1: 3.3V), default is 1. This pin must be terminated to V3P3D or ground. The UART baud rate (1: 38.4kbd, 0: 19.2kbd). This pin must be terminated to V3P3D or ground. Interrupt output, low active. A falling edge indicates the end of a measurement frame, as well as alarms. Rises when status word is read. Internal signal. MUXSYNC falls at the beginning of each conversion cycle (multiplexer frame). Chip reset: Input pin with internal pull-up resistor, used to reset the chip into a known state. For normal operation, this pin is set to 1. To reset the chip, this pin is driven to 0 for 5 microseconds. No external reset circuitry is necessary for power-up reset. © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 Name Pin No. Type Circuit UARTCSZ 34 I 3 SRDY SFR SSCLK SSDATA 24 9 5 8 I O O O 3 4 4 4 RX 44 I 3 TX TMUXOUT PULSER PULSEW 4 3 36 35 O O O O 4 4 4 4 Description Enables the UART when 0. The UART is disabled when this pin is set to 1. A positive pulse on this pin will reset the UART. This pin must be terminated to ground. High-Speed Synchronous Interface (SSI). The SRDY input should be tied to ground. SSI frame pulse output, one SSCLK wide. SSI clock output (5MHz or 10MHz selectable). SSI data output, changes on the rising edge of SSCLK. UART serial Interface receiver input. The voltage at this pin must not exceed 3.6V. This pin must be terminated to V3P3D or ground. UART serial Interface transmitter output. Digital output test multiplexer. Controlled by TMUX[2:0]. Selectable pulse output (default: VARh pulse). Selectable pulse output (default: Wh pulse). Power/Ground Pin Description Name Pin No. Type GNDA P Analog ground: This pin should be connected directly to the ground plane. P Digital ground: These pins must be connected directly to the ground plane. V3P3A 49,60 1,27, 48,62 50 P Analog power: A 3.3V analog power supply should be connected to this pin. V3P3D 7 P Digital power supply: A 3.3V digital power supply should be connected to this pin. VBAT 45 P V2P5 46 O GNDD Description Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D. Output of the 2.5V regulator. A 0.1µF capacitor should be connected from this pin to GND. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”. Reserved Pins Pins labeled RESERVED are not to be connected. Name RESERVED Page: 11 of 60 Pin No. 2,10,11,12, 13,17,18,19, 20,26,28,29, 30,31,32,43, 64 Description DO NOT CONNECT THESE PINS! © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 I/O Equivalent Circuits V3P3D V3P3A V3P3D V3P3D 110K Digital Input Pin CMOS Input Analog Input Pin To MUX from internal reference V2P5 Pin GNDD GNDA Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up GNDD Analog Input Equivalent Circuit Type 6: ADC Input V2P5 Equivalent Circuit Type 10: V2P5 V3P3D V3P3A Digital Input Pin CMOS Input 110K GNDD Comparator Input Pin To Comparator GNDD GNDD GNDA Comparator Input Equivalent Circuit Type 7: Comparator Input Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down V3P3D Digital Input Pin Power Down Circuits VBAT Pin VBAT Equivalent Circuit Type 12: VBAT Power V3P3D CMOS Input Oscillator Pin GNDD To Oscillator GNDD Digital Input Type 3: Standard Digital Input or pin configured as DIO Input Oscillator Equivalent Circuit Type 8: Oscillator I/O V3P3D V3P3D V3P3A Digital Output Pin CMOS Output GNDD GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output Page: 12 of 60 from internal reference VREF Pin GNDA VREF Equivalent Circuit Type 9: VREF © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 %Error TYPICAL PERFORMANCE CHARACTERISTICS 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 Deg 60 Deg -60 Deg 180 Deg 1 3 0.3 200 10 0.1 1 25 30 10 100 100 A 1000 Figure 3: Wh Accuracy, 0.3A - 200A/240V 0.2 90 Deg 0.15 150 Deg 0.1 % Error 0.05 3 0 270 Deg 10 25 1 30 0.3 100 -0.05 200 -0.1 -0.15 -0.2 0.1 1 10 A 100 1000 Figure 4: VARh Accuracy for 0.3A to 200A/240V Performance Page: 13 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 2 1 0 Error [%] -1 -2 -3 50Hz Harmonic Data 60Hz Harmonic Data -4 -5 -6 -7 -8 1 3 5 7 9 11 13 15 17 19 21 23 25 Harmonic Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Figure 5: Meter Accuracy over Harmonics at 240V, 30A Error [%] Performance for Apparent Energy (VAh) 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0.1 1 10 100 1000 Current [A] Figure 6: Typical VAh Accuracy for VAh Using Vector Method Page: 14 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 FUNCTIONAL DESCRIPTION THEORY OF OPERATION The 71M6515H integrates the primary functional blocks required to implement a solid-state electricity meter front end. Included on-chip are an analog front end (AFE), a digital computation engine (CE), a voltage reference, a real time clock, and I/O pins. Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils. In a typical application, the 71M6515H sequentially digitizes the voltage inputs on pins IA, VA, IB, VB, IC, VC and performs calculations to measure active energy (Wh), reactive energy (VARh), and apparent energy (VAh). In addition to these measurement functions, the real time clock function allows the device to record time of use (TOU) metering information for multi-rate applications. The 71M6515H contains a temperature-trimmed ultra-precise voltage reference, and the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement. RTC accuracy can be greatly improved by supplying correction coefficients derived from crystal characterization. The combination of both features enables designers to produce electricity meters with exceptional accuracy over the industrial temperature range. Meter Equations The 71M6515H implements the equations in Table 1. Register EQU specifies the equation to be used. In one sample time, each of the six inputs is converted and the selected equation updated. In a typical application, IA, IB, IC are connected to current transformers that sense the current on each phase of the line voltage. VA, VB, and VC are typically connected to voltage sensors (resistor dividers) with respect to NEUTRAL. NEUTRAL is to be connected to V3P3A, the analog supply voltage. NEUTRAL is the zero reference for all analog measurements. EQU Watt & VAR Formula Application Channels used from MUX sequence Mux State: 0 1 2 3 4 5 0 VA IA 1 element, 2W 1ø IA VA - - - - 1* VA(IA-IB)/2 1 element, 3W 1ø IA VA IB - - - 2 VA IA + VB IB 2 element, 3W 3 øDelta IA VA IB VB - - 3* VA (IA - IB)/2 + VC IC 2 element, 4W 3ø Delta IA VA IB - IC VC 4* VA(IA-IB)/2 + VB(IC-IB)/2) 2 element, 4W 3ø Wye IA VA IB VB IC - 5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye IA VA IB VB IC VC Note: Equations 1*, 3*, 4* available only when IMAGE = 00 (CT mode). Table 1: Meter Equations Table 2 shows how the elements of the meter are mapped for the six possible equations. Page: 15 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 EQU Element Output Mapping Watt & VAR Formula (WSUM/VARSUM) W0SUM/ VAR0SUM W1SUM/ VAR1SUM W2SUM/ VAR2SUM I0SQ SUM I1SQ SUM I2SQ SUM VA*IA - - IA - - VA*(IA-IB)/2 VA*IB - IA-IB IB - 0 VA IA (1 element, 2W 1φ) 1 VA*(IA-IB)/2 (1 element, 3W 1φ) 2 VA*IA + VB*IB (2 element, 3W 3φ Delta) VA*IA VB*IB - IA IB - 3 VA*(IA-IB)/2 + VC*IC (2 element, 4W 3φ Delta) VA*(IA-IB)/2 - VC*IC IA-IB IB IC 4 VA*(IA-IB)/2 + VB*(IC-IB)/2 (2 element, 4W 3φ Wye) VA*(IA-IB)/2 VB*(IC-IB)/2 IA-IB IC-IB IC 5 VA*IA + VB*IB + VC*IC (3 element, 4W 3φ Wye) VA*IA VB*IB IA IB IC VC*IC Table 2: Meter Element Output Mapping ANALOG FRONT END A/D Converter (ADC) A single delta-sigma A/D converter (ADC) digitizes the inputs to the device. The resolution of the ADC is 21 bits. The ADC operates at 5MHz oversampling rate and places the digital results in CE memory. Each analog input is sampled at 2520Hz. Once each accumulation interval, it refreshes the temperature value that is placed in the TEMP_RAW register. The analog reference for all inputs is V3P3A, i.e. the ADC processes voltages between the input pins and V3P3A. Voltage Reference The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques as well as production trims to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The CE compensates for temperature characteristics of the voltage reference by modifying the gain applied to the V and I channels based on the coefficients PPMC and PPMC2. See the section “TEMPERATURE COMPENSATION” for details. DIGITAL COMPUTATION The six ADC outputs are processed and accumulated digitally. The default product summation is based on 42*60 (if the SUM_CYCLES register is set to 60) samples per accumulation interval. At the end of each accumulation interval, a ready interrupt (IRQZ) is signaled (if enabled with the READY bit in STMASK), indicating that fresh data is available to the host. For instance, if SUM_CYCLES =30, the IRQZ rate will be 2Hz (500ms). A dedicated 32-bit Computation Engine (CE) performs the precision computations necessary to accurately measure energy. Internal CE calculations include frequency-insensitive offset cancellation on all six channels and a frequency insensitive 90° phase shifter for VAR calculations. The CE also includes LPF smoothing filters after each product and squaring circuit to attenuate ripple and eliminate beat frequencies between the power line fundamental and the accumulation time. The CE 2 2 directly calculates Watts, VARs, V , and I and accumulates them for one interval. At the end of each CE computation cycle, the accumulated data are post-processed to calculate RMS amplitudes, phase angles, and VAh. When post-processing is complete, the IRQZ signal is activated. Page: 16 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 The minimum combined cycle time for CE and post-processor is 400ms, which makes the maximum frequency for the IRQZ signal 2.5Hz. If the 71M6515H is interfacing to an external DSP (typically, but not necessarily through the SSI interface), the host may turn off post-processing by setting the CE_ONLY bit in the CONFIG word. This will permit setting SUM_CYCLES below its recommended lower limit of 24. SUM_CYCLES may then be reduced to 1, creating an accumulation interval of only 42 samples. The outputs available in CE only mode are limited to temperature, frequency, voltage phases, input signal zero crossings, plus WSUM and VARSUM for each phase and VSQSUM, ISQSUM, and ISQFRACT for each phase. Pulse Generators The chip contains four pulse generators connected to the pins PULSEW, PULSER, PULSE3, and PULSE4 that create low jitter pulses from 32-bit data. The peak time jitter for PULSEW and PULSER is the 397µs MUX frame period, and is independent of the rate of the generator or the length of time the generator is monitored. Thus, if the pulse generator is monitored for 1 second, the peak jitter is 400PPM. After 10 seconds, the peak jitter is 40PPM. PULSE3 and PULSE4 are updated at a slower rate and have four times higher jitter, i.e. 160PPM after 10 seconds. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any roll-over characteristics. Pulse generator inputs may be from three sources: • Internal (directly from the CE), PULSEW and PULSER only • External (controlled by the host writing to registers APULSEW, APULSER, APULSE3, APULSE4) • Post-processed values The source is selected individually for each pulse output with the PULSEW_SRC, PULSER_SRC, PULSE3_SRC, and PULSE4_SRC registers. Figure 7 shows internal pulse generation for the PULSEW output selected by writing the value 35 into the PULSEW_SRC register. 35: WSUM CE 2: WBSUM 35 PULSEW_SRC 3: WCSUM 4: VARSUM POST PROCESSOR 0: WSUM 1: WASUM PULSEW OUTPUT 34: VAR2SUM_E 36: APULSEW HOST Figure 7: Internal Pulse Generation Selected in the PULSEW_SRC Register Page: 17 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 Internal data is pulsed out during the accumulation interval immediately following its accumulation interval. Post-processed values are pulsed out one accumulation interval after that. The pulse generator output rate depends on its input value, WRATE, PULSE_SLOW, and PULSE_FAST. Additionally, its maximum pulse width (negative going pulse) is controlled by PULSEWIDTH. High frequency pulses will have 50% duty cycle until their rate slows enough that their pulse width is limited by PULSEWIDTH. In internal and post-processed modes, the pulse rate, expressed as Kh (Wh per pulse) is given by the formula: Kh = VMAX IMAX 1.5757 Wh / Pulse In _ 8 ⋅ SUM _ CYCLES ⋅ WRATE ⋅ X where VMAX is the meter voltage corresponding to an input voltage of 176mV (rms) at the VA, VB, and VC input pins , IMAX is the meter current corresponding to an input voltage of 176mV (rms) at the IA, IB, and IC input pins, In_8 is the additional ADC gain (1 or 8), as controlled by the IA_X, IB_X and IC_X bits in the CONFIG register. X is the pulse speed factor determined from Table 3. PULSE_SLOW 0 0 1 1 (default) PULSE_FAST 0 1 0 1 (default) X 2 1.5*2 =6 1.5*26=96 1.5*2-4=0.09375 1.5 Table 3: Pulse Speed Factor X In external pulse mode, the pulse rate is given by the formula: Rate(Hz) = WRATE * X * input * 35.82*10-12, where input is the value in registers APULSER, APULSEW. APULSE3 or APULSE4, X is the pulse speed factor determined from Table 3. External pulse generation can be seen as providing the raw voltage and current readings equivalent to Vin*Iin / LSB directly to the pulse generator. The maximum pulse rate is 7.56kHz for PULSEW and PULSER, and 150Hz for PULSE3 and PULSE4. In external pulse mode, the pulse generators load their data at the beginning of each CE accumulation interval, preserving any partially implemented pulses from the previous interval. The source of data is controlled by the entries in the PULSE_SRCS register. PULSER_SRCS contains 8-bit entries for each pulse source, PULSEW, PULSER, PULSE3, and PULSE4. See the register description for details. The procedure for accurate external pulse generation controlled by the host is: 1) Respond to a READY interrupt by reading the accumulated values. 2) Process the accumulated values. 3) Write the processed value(s) to APULSER, APULSEW, APULSE3, or APULSE4. The host must write to APULSER, APULSEW, APULSE3, and APULSE4 before the next READY interrupt for the pulse generation to be beginning in the following accumulation interval. Figure 8 illustrates pulse generator timing. Regardless of the source, the pulse generators should receive new data during each accumulation interval. If this does not occur and if the corresponding bit in the STMASK register is set, an APULSE_ERR interrupt will be issued. The PULSEW, PULSER, PULSE3 and PULSE4 pins are suitable for driving LEDs through a current limiting resistor. The LED should be connected so it is on when the pulse pin is low. Page: 18 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 The pin PULSE_INIT determines the logic level applied to the pulse pins on power-up, i.e. with PULSE_INIT low, the pulse pins will be initialized to low (default = 1). The pulse width PW is controlled with the PULSEWIDTH register for the PULSER and PULSEW output pins per the following formula: PW = 2 ⋅ PULSEWIDTH + 1 2520.6 The PULSE3 and PULSE4 output pins will always generate pulses with 50% duty cycle. Internal Data (Directly by CE) Accumulation Interval CE Operations Post Processing Accumulation 2 Accumulation 1 XFER XFER Post 0 Pulse Generator Accumulation 3 XFER Post 2 Post 1 READY READY READY Pulse 0 Pulse 1 Pulse 2 Post-Processed Data Accumulation Interval CE Operations Post Processing Accumulation 2 Accumulation 1 XFER XFER Post 0 Post 2 Post 1 READY READY APULSE write Pulse 0 APULSE write Pulse 1 READY Pulse Generator APULSE write Pulse -1 Accumulation 3 XFER External (Host data is transferred to the pulse generator in the first accumulation interval after the next READY) Accumulation Interval CE Operations Post Processing XFER Post 0 Pulse Generator Host 0 APULSE write Pulse -2 Accumulation 3 XFER Post 2 Post 1 READY Host Processing Accumulation 2 Accumulation 1 XFER READY Host 1 APULSE write Pulse -1 READY Host 2 APULSE write Pulse 0 Figure 8: Pulse Generator Timing Page: 19 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 Internal Resources Oscillator The oscillator drives a standard 32.768kHz watch crystal. Crystals of this type are accurate and do not require a high current oscillator circuit. The 71M6515H oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Using PLL techniques, all internal clocks, such as the 4.915MHz clock for the ADC and the post-processor, are derived from the watch crystal frequency. Real-Time Clock (RTC) The RTC is driven directly by the crystal oscillator. In the absence of V3P3, it is powered by the battery-backed up supply. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year. The nominal quadratic temperature coefficient of the crystal is automatically compensated in the RTC. The RTC is capable of processing leap years. I/O Peripherals The 71M6515H includes several I/O peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. The I/O peripherals include a UART and digital I/O. Digital I/O The device includes eight pins of general purpose digital I/O (D0…D7). Each pin can be configured independently as an input or output with the D_DIR bits. Inputs are standard CMOS with no pull-ups or pull-downs. Outputs are standard CMOS. The DIO pins are controlled by the D_CONFIG register. Immediately after reset or power-up, D0 through D7 are in tri-state mode. 140 ms after reset, D0 through D7 are configured as outputs and driven low. UART Host Interface The UART is a dedicated 2-wire serial interface, which can communicate with the host processor. The operation of each pin is as follows: RX: Is the pin accepting the serial input data. It inputs data to internal registers. The bytes are input LSB first. The voltage applied to this pin must be restricted to 0 to 3.6V. TX: Is the pin used for serial output data. It outputs the contents of a block of internal registers. The bytes are output LSB first. BAUD_RATE: The baud rate can be selected with the BAUD_RATE pin (38.4bps when high, 19.2bps when low). UARTCSZ: This pin enables the UART when low. The UART can be reset by taking UARTCSZ briefly to the high state and then low again. The 71M6515H has several on-chip registers, which can be read and written. All transfers start with a stream of 8-bit bytes (LSB first) from the host on the RX input, followed by a (possibly null) stream of 8-bit bytes (LSB first) to the host on the TX output (see Figure 9 and Figure 10). The UART is configured as 8N1 (8 bits, no parity, 1 stop bit). If the READY bit in STMASK is enabled, the IRQZ pin can be used to signal data availability to the host. If data read cycles exceeding 1 second are used, care should be taken to prevent data overflow. UART Write Register Operation The registers are written by sending a byte, consisting of a starting register address in the seven MSBs and ‘0’ in the LSB indicating this is a write operation. It is followed by a one byte length of bytes to write. If more bytes arrive than fit in the addressed register, subsequent registers will be written. The bytes are processed in “big-endian” order (i.e. most significant byte first). See Figure 9 (read bits and bytes from left to right). Page: 20 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 L W S B M S B L S B M S B L S B M S B L S B M S B RX register address most significant data byte length least significant data byte time TX Figure 9: UART Write Operation UART Read Register Operation The registers are read by sending a byte, consisting of a start register address in the seven MSBs and ‘1’ in the LSB indicating this is a read operation. It is followed by a one byte length of bytes to read. If more bytes are asked for than the size of the addressed register, subsequent registers will be read. The bytes are in “big-endian” order (i.e. most significant byte first). See Figure 10. L R S B M S B L S B M S B RX register address length time L S B TX M S B most significant data byte L S B M S B least significant data byte Figure 10: UART Read Operation Note: In both register read and write operations, the register address can be 0 through 127 (0x7F). The register address byte is obtained by left-shifting the register address by one bit and setting bit 0 to 1 for read or setting bit 0 to 0 for write. Synchronous Serial Interface (SSI) A high speed, handshake, serial interface is available to send a contiguous block of CE data to an external data logger or DSP. The block of data, configurable as to location and size, is sent at the beginning of each ADC multiplex cycle. The SSI interface is enabled by the SSI_EN bit and consists of the outputs SSCLK, SSDATA, and SFR and of the SRDY input pin. The interface is compatible with 16-bit and 32-bit processors. The operation of each pin is as follows: SSCLK: This pin provides the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls whether SSCLK runs continuously or is gated off when no SSI activity is occurring. If SSCLK is gated, it will begin three cycles before SFR rises and will persist three cycles after the last data bit is output. SSDATA: This pin provides the serial output data. SSDATA changes on the rising edge of SSCLK and outputs the contents of a block of CE words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first. SSDATA is stable with the falling edge of SSCLK. SFR: This pin provides the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single field, as multiple 16 bit fields, or as multiple 32 bit fields. The SFR pulse is one clock cycle wide, changes state on the rising edge of SSCLK and precedes the first bit of each field. The field size is set with SSI_FSIZE: 0-entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of the SFR pulse can be inverted with SSI_FPOL. The first SFR pulse in a frame will rise on the third SSCLK clock period after MUX_SYNC (fourth SSCLK period, if SSCLK is 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP. SRDY: The SRDY input should always be tied to GND. Page: 21 of 60 © 2005−2011 Teridian Semiconductor Corporation 1.6 71M6515H Energy Meter IC A Maxim Integrated Products Brand DATA SHEET JULY 2011 The SSI timing is shown in Figure 11. If 16bit fields If SSI_CKGATE =1 If 32bit fields If SSI_CKGATE =1 SFR (Output) SCLK (Output) 31 SSDATA (Output) 30 16 15 1 0 31 30 SSI_BEG 16 15 1 SSI_BEG+1 0 1 31 0 SSI_END MUX_STATE Figure 11: SSI Timing (SSI_FPOL = SSI_RDYPOL = 0) Fault and Reset Behavior Reset Mode When RESETZ is pulled low or when VFLT < V3P3/2, all activity (i.e. sampling of analog signals, CE, generation of digital outputs) in the chip stops while the analog circuits are active. The exceptions are the oscillator and RTC module, which continue to run. Additionally, all I/O Register bits are cleared. As long as VFLT > V3P3/2, the internal 2.5V regulator will continue to provide power to the digital section. Once initiated, the reset mode will persist until the reset timer times out. This will occur in 4100 cycles of the real time clock after RESETZ goes high, at which time the 71M6515H will begin executing its preboot and boot sequences. Power Fault Circuit The power fault comparator compares the voltage at the VFLT pin to V3P3/2. The comparator output internally enables the battery backup protection for oscillator, RTC and RAM during the power fail mode. Temperature Compensation Voltage Reference The internal voltage reference of the 71M6515H is calibrated at 25°C during device manufacture. The 71M6515H is given additional temperature-related calibrations which further compensate its ADC gain and allow it to achieve 10PPM/°C over ±60°C temperature range. Temperature Sensor The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset thermal drift in the system. The temperature sensor is read once per accumulation interval. Temperature measurement can be implemented with the following steps: 1) At a known temperature TN, read the TEMP_RAW register and write the value into TEMP_NOM register. 2) Read the DELTA_T register at the known temperature. The obtained value should be