Simplifying System IntegrationTM
73S1217F
Evaluation Board User Guide
August 17, 2009
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User Guide
UG_1217F_040
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Microsoft, Windows and Vista are registered trademarks of Microsoft Corporation.
Signum is a trademark of Signum Systems Corporation.
®
Keil is a trademark of ARM Ltd.
Linux is a registered trademark of Linus Torvalds.
Slackware is a registered trademark of Patrick Volkerding and Slackware Linux, Inc.
Fedora is a registered trademark of RedHat, Inc.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
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Table of Contents
1
Introduction ................................................................................................................................... 4
1.1
Evaluation Kit Contents......................................................................................................... 5
1.2
Evaluation Board Features .................................................................................................... 5
1.3
Recommended Equipment and Test Tools ............................................................................ 5
2
Evaluation Board Basic Setup ...................................................................................................... 6
2.1
Connecting the Evaluation Board with an Emulation Tool ...................................................... 7
2.2
Loading User Code into the Evaluation Board ....................................................................... 8
3
Using the USB CCID Application ................................................................................................ 10
3.1
Driver and Host Demonstration Software Installation ........................................................... 10
3.1.1 Driver and Software Installation on a Linux System.................................................... 11
3.2
Frequently Asked Questions ............................................................................................... 11
4
Evaluation Board Hardware Description .................................................................................... 13
4.1
Jumpers, Switches and Modules ......................................................................................... 13
4.2
Test Points ......................................................................................................................... 18
4.3
Schematic........................................................................................................................... 19
4.4
PCB Layouts....................................................................................................................... 20
4.5
Bill of Materials ................................................................................................................... 26
4.6
Schematic Information ........................................................................................................ 29
4.6.1 Reset Circuit.............................................................................................................. 29
4.6.2 Oscillators ................................................................................................................. 29
4.6.3 LCD .......................................................................................................................... 30
4.6.4 USB Interface ............................................................................................................ 30
4.6.5 Smart Card Interface ................................................................................................. 31
5
Ordering Information ................................................................................................................... 32
6
Related Documentation ............................................................................................................... 32
7
Contact Information..................................................................................................................... 32
Revision History .................................................................................................................................. 33
Figures
Figure 1: 73S1217F / 1210F Evaluation Board ......................................................................................... 4
Figure 2: 73S1217F Evaluation Board Basic Connections ........................................................................ 6
Figure 3: 73S1217F Evaluation Board Basic Connections with ADM-51 ICE ............................................ 7
Figure 4: Emulator Window Showing RESET and ERASE Buttons........................................................... 9
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu ..................................... 9
Figure 11: 73S1217F Evaluation Board Jumper, Switch and Module Locations ...................................... 17
Figure 12: 73S1217F Evaluation Board Electrical Schematic ................................................................. 19
Figure 13: 73S1217F Evaluation Board Top View (Silkscreen) ............................................................... 20
Figure 14: 73S1217F Evaluation Board Bottom View (Silkscreen) .......................................................... 21
Figure 15: 73S1217F Evaluation Board Top Signal Layer ...................................................................... 22
Figure 16: 73S1217F Evaluation Board Middle Layer 1 – Ground Plane................................................. 23
Figure 17: 73S1217F Evaluation Board Middle Layer 2 – Supply Plane ................................................. 24
Figure 18: 73S1217F Evaluation Board Bottom Signal Layer ................................................................. 25
Figure 6: External Components for RESET ............................................................................................ 29
Figure 7: Oscillator Circuit...................................................................................................................... 29
Figure 8: LCD Connections.................................................................................................................... 30
Figure 9: USB Connections ................................................................................................................... 30
Figure 10: Smart Card Connections ....................................................................................................... 31
Tables
Table 1: Flash Programming Interface Signals ......................................................................................... 8
Table 2: Evaluation Board Jumper, Switch and Module Description ....................................................... 13
Table 3: Evaluation Board Test Point Description................................................................................... 18
Table 4: 73S1217F Evaluation Board Bill of Materials ............................................................................ 26
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73S1217F Evaluation Board User Guide
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1 Introduction
The Teridian Semiconductor Corporation (TSC) 73S1217F Evaluation Board is used as a platform to
demonstrate the capabilities of the 73S1217F Smart Card Controller devices. It has been designed to
operate either as a standalone or a development platform.
The 73S1217F Evaluation Board can be programmed to run any of the Teridian turnkey applications or a
user-developed custom application. Teridian provides its USB CCID application preloaded on the board
and an EMV testing application on the CD.
Applications can be downloaded through the In-Circuit-Emulator (ICE) or through the TSC Flash
Programmer Model TFP2. As a development tool, the evaluation board has been designed to operate in
conjunction with an ICE to develop and debug 73S1217F based embedded applications.
Figure 1: 73S1217F / 1210F Evaluation Board
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1.1
73S1217F Evaluation Board User Guide
Evaluation Kit Contents
The 73S1217F Evaluation Kit contains the following:
•
73S1217F Evaluation Board: 4-layer, rectangular PWB as shown in Figure 1 (identification number
E1217FN12B1 Rev B), containing the 73S1217F with the preloaded USB CCID application.
•
USB cable, A-B, male/male, 2 meters (Digi-key AE9932-ND).
•
5 V DC power supply.
•
CD containing documentation (data sheet, and user guides), Software API libraries, evaluation code
and utilities.
1.2
Evaluation Board Features
The 73S1217F Evaluation Board (see Figure 1) includes the following:
•
USB 2.0 full speed interface
•
RS-232 interface
•
Dual smart card interface
•
ICE/Programmer interface
•
2 line x 16 character LCD module
•
6 x 5 keypad
•
Real Time Clock (RTC) capability
•
1 LED
1.3
Recommended Equipment and Test Tools
The following equipment and tools (not provided) are recommended for use with the 73S1217F
Evaluation Kit:
•
For functional evaluation: PC with Microsoft® Windows® XP or Vista®, or a workstation with Linux®,
equipped with a USB and or serial (RS-232) port.
•
For software development (MPU code)
Signum™ ICE (In Circuit Emulator): ADM-51. Refer to
http://signum.temp.veriohosting.com/Signum.htm .
Keil™ 8051 C Compiler Kit: CA51. Refer to http://www.keil.com/c51/ca51kit.htm and
http://www.keil.com/product/sales.htm.
Rev. 2.4
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2 Evaluation Board Basic Setup
Figure 2 shows the basic connections of the evaluation board with the external equipment.
The power supply can come from three sources:
•
A regulated lab power supply connected to the banana plugs J2, J3 and J5.
•
•
Any AC-DC converter block, able to generate a DC power supply of 2.7 V min / 6.5 V max / 400 mA.
The +5 V coming from the USB bus when connected to a computer or hub, able to support USB-powered
devices. In this case the ON/OFF switch, S33, has no effect and power is always on. When the
board is powered from the USB bus, the application is bus-powered and the embedded application
must be designed for this.
The communication with an external host can be accommodated by either:
•
•
A standard USB2.0 full speed interface or
A standard RS-232 serial interface (TX/RX only).
The board is loaded by default with the USB CCID application. Refer to Section 3 for information on
setting up and running this application.
Figure 2: 73S1217F Evaluation Board Basic Connections
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2.1
73S1217F Evaluation Board User Guide
Connecting the Evaluation Board with an Emulation Tool
The 73S1217F Evaluation Board has been designed to operate with an In-Circuit-Emulator (ICE) from
Signum Systems (model ADM-51). Figure 3 shows the connections between the ICE and the evaluation
board. The Signum System pod has a ribbon cable that must be directly attached to connector J11.
Signum Systems offers different pod options depending on user needs. The standard pod allows users to
perform typical emulator functions such as symbolic debugging, in-line breakpoints, memory
examination/modification, etc. Other pod options enable code trace capability and/or complex
breakpoints at an additional cost.
Figure 3: 73S1217F Evaluation Board Basic Connections with ADM-51 ICE
Rev. 2.4
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2.2
UG_1217F_040
Loading User Code into the Evaluation Board
Hardware Interface for Programming
The signals listed in Table 1 are necessary for communication between the TFP2 or ICE and the
73S1217F.
Table 1: Flash Programming Interface Signals
Signal
Direction
Function
E_TCLK
Output from 73S1217F
Data clock
E_RXTX
Bi-directional
Data input/output
Bi-directional
Flash Downloader Reset (active low)
1
E_RST
1
The E_RST signal should only be driven by the TFP2 when enabling these
interface signals. The TFP2 must release E_RST at all other times.
The signals in Table 1, along with 3.3 V and GND, are available on the emulator header J11. Production
modules may be equipped with much simpler programming connectors, e.g. a 5x1 header.
Programming of the flash memory requires either the Signum Systems ADM51 in-circuit emulator or the
TSC Flash Programmer Model TFP2 provided by Teridian.
Loading Code with the In-Circuit Emulator
If firmware exists in the 73S1217F flash memory, the memory must be erased before loading a new file
into memory. In order to erase the flash memory, the RESET button in the emulator software must be
clicked followed by the ERASE button (see Figure 4).
Once the flash memory is erased, a new file can be loaded using the Load command in the File menu.
The dialog box shown in Figure 5 makes it possible to select the file to be loaded by clicking the Browse
button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC.
At this point, the emulator probe (cable) can be removed. Once the 73S1217F device is reset using the
reset button on the evaluation board, the new code starts executing.
Loading Code with the TSC Flash Programmer Model TFP2
Follow the instructions given in the TSC Flash Programmer Model TFP2 User’s Manual.
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RESET
BUTTON
ERASE
BUTTON
Figure 4: Emulator Window Showing RESET and ERASE Buttons
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu
Rev. 2.4
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3 Using the USB CCID Application
The USB CCID firmware is pre-installed on the 73S1217F Evaluation Board. To operate correctly, it
requires a PC with the appropriate driver to be connected through its USB port. When powered-up, the
board is able to run the CCID-USB demonstration host application which allows:
•
•
•
3.1
Smart card activation and deactivation, in ISO or EMV mode.
Smart card APDU commands to be exchanged with the smart card inserted in the board.
Starting a test sequence in order to test and evaluate the board performance against an EMV test
environment.
Driver and Host Demonstration Software Installation
Installation on Windows XP
Two drivers are available for use with Windows XP:
•
•
The standard Microsoft Windows XP driver and
The Teridian provided driver that adds additional features beyond the capabilities of the Microsoft
driver.
See the 73S1215F, 73S1217F CCID Application Note for further details on the differences between the
two drivers.
When using the 73S1217F transparent reader – dual slot with keypad and LCD evaluation board, the
Microsoft provided driver should not be used as this driver does not support the second slot nor the LCD
display and keypad.
The Microsoft CCID driver included in the CD is used by Teridian for testing. Check with
Microsoft for the latest driver upgrades.
Follow these steps to install the drivers and software on a PC running Windows XP:
•
•
•
•
•
Extract “12xxF CCID+DFU Vy.yy Release.zip” (where y.yy is the latest version of the firmware
release).
o Create an install directory. For example: “C:\TSC\”.
o Unzip “12xxF CCID+DFU Vy.yy Release.zip” to the just created folder. All applications and
documentation needed to run the board with a Windows PC will be loaded to this folder.
Connect the USB cable between the host system and the 73S1217F Evaluation Board. The power
LED light should now come on.
The host system should recognize the board and start the Add New Hardware Installation Wizard.
When the wizard prompts, select the Teridian driver file.
o To use the Teridian supplied driver, select the ccidtsc-xp.inf file located in the “C:\TSC\12xxF
CCID+DFU Vy.yy Release\USB-CCID Firmware\CCID USB\CCID+DFU USB Drivers\XP 32 CCID” subdirectory. The ccistsc-xp.inf and ccidtsc-xp.sys files must be in the same directory on
the host.
Follow the prompts until the process is completed.
Run “CCID-DFU_USB_vy.yy.exe” (located in the path - C:\TSC\12xxF CCID+DFU C:\TSC\12xxF
CCID+DFU V2.00 Release\Host Applications\Windows App\Bin\Release Release\Host
Applications\Windows App\Bin\Release) on the host system to execute the host demonstration
application.
At this point the application window should appear. For additional information regarding the use of the
Teridian Host application, refer to the 73S12xxF USB-CCID Host GUI Users Guide (UG_12xxF_037).
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To use the Windows standard driver, select the usbccid.inf file located in the “CCID USB
XPDriver” subdirectory. The uscccid.inf and usbccid.sys files must be in the same directory on
the host.
3.1.1 Driver and Software Installation on a Linux System
Teridian has tested the 73S1217F Evaluation Board with Linux CCID driver v1.3.2 and PCSC-Lite v.1.4.4
®
®
(middleware) on two distributions of Linux: Slackware 6 with kernel 2.4.16, and Fedora 7 with kernel
2.6.23. Refer to the 73S1215F, 73S1217F CCID USB Linux Driver Installation Guide (UG_12xxF_041)
for details on installation and usage on a Linux system.
3.2
Frequently Asked Questions
Windows
Q The PC/SC application starts but it shows a “No Reader Found” message.
A: Follow these steps to make sure:
1. The board has powered up properly (USB is securely connected and there is power applied to the
board).
2. Control Panel – System – Hardware – Device Manager – Smart Card Readers shows: “Teridian
Semiconductors USB CCID Smart Card Reader...” And there is no yellow “!” or red “X”.
3. Smart Card Service has started by going to ‘Control Panel – Administrative Tools – Services –
Smart Card’. Look under the “status” column and if it shows “stopped”, hit the restart or start
button to start it.
4. If all of the above look ok, hit the refresh button on the CCIDUSB.exe application.
Q: There is a yellow “!” on the Teridian driver shown on the Device Manager menu.
A: This usually means the driver did not complete the driver enumeration process. Push the reset button
on the evaluation board a few times. If the board is connected to the host via a USB HUB, remove the
HUB and try connecting the board directly to the PC USB port to make sure the driver and the board
can enumerate with the USB host. If the problem persists, check the driver on the PC to make sure it
is at least version 6.0.0.2. Contact your Teridian Sales Representative for the latest version of the
driver. Sometimes, rebooting the PC Host to clear up any previous USB problem will help.
Q: There is a red “X” on the Teridian driver shown on the Device Manager menu.
A: This usually means the smart card driver has been disabled. Highlight and right click on the driver to
re-enable.
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Q: The Teridian Smart Reader is nowhere to be found on the Device Manager menu and there is an
“unknown USB device” found where the Teridian evaluation board should be.
A: This usually means the demo board is properly powered up but there is no enumeration taking place.
If the board is connected to a USB HUB, remove the HUB and connect the board directly to the PC
USB port. Or move it to a different USB port on the system. If the problem persists and it is
absolutely sure that the evaluation board is properly powered up, it is possible that there is no
firmware in the part. Contact a Sales Representative for reprogramming of Flash.
Q: The Teridian driver is loaded. What to do to replace it with the Microsoft Generic USB CCID driver?
A: Right click on the Teridian Driver in the Device Manager Menu, select “Update Driver..”. Select “No,
Not this time” on the next menu, “Install from a list or specific location”, “Don’t Search, I will choose the
driver to install”. If the next menu does not show the Microsoft Generic USB CCID driver, select
“Have Disk” and browse to where the driver file resides (usually in the “CCID USB XPDriver” folder)
and select the file. Follow through with the installation wizard.
Linux
Q: How can I see debug messages from PCSC-Lite when I run pcscd from the command line?
A: Before invoking pcscd, open the file /usr/local/pcsc/drivers/ifd-ccid.bundle/Contents/Info.plist in an
editor, and set ifdLogLevel to 7. Save the change. Then run the command “pcscd –f –d” in a console.
Now pcscd runs in foreground and should display many messages in the console. These messages
show information about the smart card readers that have been detected, and whether or not a smart
card is present in the reader. Also shown in the messages are the data exchanges between the host
(Linux) and the smart card reader. The most important messages are the error messages that pcscd
displays when a critical error has occurred. If fewer messages are desired, set IfdLogLevel to 3 or 1.
Q: When I run command “pcscd –f –d”, I get an error message that says “file /var/run/pcscd.pub already
exists. Another pcscd seems to be running”.
A: Only one instance of pcscd (PCSC-Lite Daemon) should be running at any time. If you receive this
error message when invoking the pcscd program, pcscd is probably running already. If your intention
is to restart pcscd, first terminate the pcscd that is currently running. Run the command “ps aux | grep
pcscd” to obtain the PID (Process ID) of the currently running pcscd. For example, you may see
output similar to the following:
[root@localhost ~]# ps aux | grep pcscd
root 3380 0.1 0.0 74588 1752 pts/2
[root@localhost ~]#
Sl+
16:06
0:02 pcscd –f –d
The PID of the currently running pcscd in this case is 3380. Next run the command “kill 3380” to stop
pcscd. Now start pcscd again by entering the command “pcscd –f –d”.
Q: When I start the program pcsc_scan, I receive an error message saying “PCSC Not Running”.
A: The pcsc_scan program requires the services provided by pcscd. Hence the PCSC-Lite daemon
pcscd should be already running before pcsc_scan can start. Run pcscd first, and then invoke
pcsc_scan.
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4 Evaluation Board Hardware Description
4.1
Jumpers, Switches and Modules
Table 2 describes the 73S1217F Evaluation Board jumpers, switches and modules. The Item # in Table 2
references Figure 11.
Table 2: Evaluation Board Jumper, Switch and Module Description
Schematic
and
Item
Default
setting
Silkscreen
#
Reference
1
J2, J3, J5
No
Connect
Name
Use
Banana plugs for
external regulated
power supply
Must be used to connect an external power
supply. These inputs are intended to allow
control of the input supply voltage of the board.
JP5 must be in position “EXT VPC” when using
VPC and JP8 must be in position “EXT” when
using the VBAT power supply inputs.
The evaluation board is sensitive to the polarity:
One red plug is +2.7/6.5 V for external VPC and the other red plug is +4.0/6.5 V for VBAT. The
black plug is ground.
2
JP2
VP
73S8010R VPC select
Selects VPC power supply source for the
73S8010R device between VP on the
73S1217F and +5 V from JP1 pin 2.
3
J11
No
Connect
In-Circuit Emulator
connector
This connector must be used when using an
external
In-Circuit Emulator (SIGNUM 8052 ADM51
ICE). Refer to the electrical schematic for pin
assignment.
4
PJ1
No
Connect
DC jack
Plug to connect an external DC block. Must be
used in conjunction with appropriate settings of
S1, JP1 and JP6 (see details above).
Power supply features are:
Voltage: 2.7 V min / 6.5 V Max
Current: 400 mA
5
J6
Connect
USB connector
Standard USB socket. Requires a standard
USB 1.1 or 2.0 device cable to connect to a
computer.
6
JP23
Inserted
USB interrupt jumper
Jumper allows the VBUS (after level conversion)
to connect to USR7 (configured for interrupt).
Remove this jumper if not needed and USR7
can be used for another purpose.
7
JP6
Shutdown RS-232 Xcvr enable
jumper
Selects between VDD (always enabled) and a
test point (with pull down) to allow the RS232
transceiver chip to be shut down.
8
P1
No
Connect
This socket allows connection of an RS232
cable to a computer. Use a crossed wired
(RX/TX) cable. The evaluation board has an
on-board level shifter (U7) to allow direct
connection to a computer.
Connection to an RS232 link is required when
using the pre-downloaded USB CCID
application.
Rev. 2.4
DB9 RS232 female
socket
13
73S1217F Evaluation Board User Guide
Schematic
Item
and
Default
setting
#
Silkscreen
Reference
9
JP3
Not
Inserted
UG_1217F_040
Name
Use
RS-232 Xcvr power
Power supply jumper for the RS232 transceiver
chip. Can be removed to obtain accurate power
measurements.
10
D2, D3
LEDs:
Serial link activity
These LEDs (D2, D3) reflect the activity on the
serial link (RS232 or serial).
D2 reflects the activity on the RX line (Data
going TO the 73S1217F)
D3 reflects the activity on the TX line (Data
coming FROM the 73S1217F)
11
U5
LCD Module
On-board LCD module:
• 2 lines of 16 characters, each character dot
matrix is 5x7.
• Includes an embedded Hitachi HD44780
LCD driver, controlled from the on-board
73S1217F USR interface.
12
RV1
Adjustable resistor to
adjust LCD brightness
Can be used to adjust the brightness of the onboard LCD module.
13
S2 to S26,
S27 to S32
On-board keypad
5x6 keyboard directly connected to the on-board
73S1217F IC (68-pin only). The assignment of
the keys, as silk-printed on the PCB, is the one
supported by the TSC Application Programming
Interface.
14
–
Board reference and
serial number
Should be mentioned in any communication with
Teridian when requesting support.
15
D8
VDD power indicator
Indicates when the 73S1217F is turned on (VDD
= 3.3 V).
16
S33
ON/OFF switch
Switch used to turn on and off the 73S1217F.
The switch is overridden when VBUS is applied
(VDD is always on).
When VDD is on and the switch is pressed, the
73S1217F will activate the OFF_REQ signal
and the 73S1217F must set the SCPWRDN or
PWRDN bits to shutoff VDD.
17
JP7
Power ON/OFF select
jumper
This jumper will select between the ON/OFF
switch and ground. When the switch is
selected, the VDD power will toggle between on
and off (see item #16). When ground is
selected, the VDD will turn on automatically
upon application of VPC to the 73S1217F.
18
–
Breadboard area
This breadboard area allows engineers to add
their own circuitry / connection of peripherals
when prototyping and developing a 73S1217F
based application. User I/Os, GPIOs, interrupt
pins and power supply pins are located close to
this area to allow easy connection.
19
JP9
14
ON/OFF
OFF_REQ INT3 select
Selects the source for INT3 between the
73S8010R and the OFF_REQ pin on the
73S1217F. Should be set opposite of JP21.
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User Guide
Schematic
Item
and
Default
setting
#
Silkscreen
Reference
20
JP21
8010R
INT
Name
Use
INT2 select
Selects the source for INT2 between the
73S8010R and the OFF_REQ pin on the
73S1217F. Should be set opposite of JP9.
21
JP13
Not
Inserted
Jumper: USR7/SDA
select
This jumper selects which signal is connected to
the daughter board connector pin USR7:
• In position “USR7”, the 73S1217F USR7
signal is connected to the daughter card pin
USR7.
• In position “SDA”, the I2C SDA signal is
connected to the daughter card pin USR7.
This allows the SDA line to connect to an
SDA pin on a 73S8010R daughter card.
22
JP14
Not
Inserted
Jumper: USR7/SDA
select
This jumper allows the on board 73S8010R
AUX2 pin to be connected to USR5 if needed. If
not needed, the jumper should be removed.
23
U4
On board 73S8010R
The board contains a built-in 73S8010R that is
connected to the external smart card interface of
the 73S1217F. This device can be
disconnected from the 73S1217F if not used, by
removing jumpers JP12 and JP21.
24
J7,J8
Optional 73S80xxX
Daughter Board
interface
When developing applications that require more
than 2 smart card interfaces, an optional
daughter board can be populated to use the
73S1217F external smart card interface (lines
SCIO and SCK), in conjunction with the
USR(0:7) port and the INT2 interrupt input of the
73S1217F). Refer to the electrical schematic for
pin assignment.
25
J9, J10
SIM / SAM and Smart
Card connectors –
external interface (#2)
Allows the evaluation board to communicate
with a smart card using either the standard
(credit card size) or SIM/SAM format. This slot
is connected to the 73S1217F external card
interface # 2.
Note that J10 is wired is parallel to the smart
card connector J9 (underneath the PCB). Both
connectors cannot be populated at the same
time.
26
JP11
Not
Inserted
Jumper: USR6/SCL
select
This jumper selects which signal is connected to
the daughter board connector pin USR6:
• In position “USR6”, the 73S1217F USR6
signal is connected to the daughter card pin
USR6.
• In position “SCL”, the I2C SCL signal is
connected to the daughter card pin USR6.
This allows the SCL line to connect to an SCL
pin on a 73S8010R daughter card.
27
JP10
Not
Inserted
Jumper: USR6/AUX1
select
This jumper allows the on board 73S8010R
AUX1 pin to be connected to USR6 if needed. If
not needed the jumper should be removed.
Rev. 2.4
15
73S1217F Evaluation Board User Guide
Schematic
Item
and
#
Silkscreen
Reference
28
S27
Default
setting
UG_1217F_040
Name
Use
Reset button
Evaluation board main reset: Asserts a
hardware reset to the on-board 73S1217F IC.
29
JP12
Inserted
LED0 jumper
In normal use, a jumper must be inserted in this
header to connect the LEDs to the LED pins of
the 73S1217F. This jumper can be replaced by
a µA / mA-meter to measure the actual current
drawn by the LED output of the 73S1217F.
30
JP15
GND
Jumper: security fuse
control
This jumper should be removed at all times.
Connecting the jumper will allow the security
fuses to be blown under firmware control. Refer
to the 73S1217F Data Sheet for further
information about the security fuse.
31
JP20
Not
Inserted
Analog select
Selects the analog input between TP32 and the
VBAT input voltage (via resistor divider).
32
JP8
Not
Inserted
VBAT select
Selects the VBAT input between an external
supply on J3 or the unregulated 5 V on PJ1.
33
J1, J4
SIM / SAM and Smart
Card connectors –
internal interface (#1)
Allows the evaluation board to communicate
with a smart card using either the standard
(credit card size) or SIM/SAM format: This slot
is connected to the 73S1217F built-in card
interface # 1.
J1 is wired in parallel to the smart card
connector J4 (underneath the PCB). Both
connectors cannot be used at the same time.
34
JP4
Inserted
VDD jumper
The VDD supply jumper can be replaced with a
current meter to measure the power
consumption on VDD.
35
JP1
VBUS
Jumper:
5V power supply
selection
This jumper selects the 5.0 V power supply. It
selects either the unregulated 5 V supply from
PJ1 or the 5.0 V from the USB VBUS:
• In position “5V UNREG”, the evaluation
board 5.0 V is powered from the PJ1
connector.
• In position “VBUS”, the evaluation board is
powered from the USB VBUS.
36
JP5
Not
Inserted
Jumper:
VPC power supply
selection
This jumper selects the VPC power supply. It
selects either the power supply connected to
plug J2 or the 5 V unregulated supply on the
PJ1 connector.
• In position “5V UNREG”, the evaluation
board VPC is connected to 5 V coming in on
PJ1.
• In position “EXT VPC”, the evaluation board
VPC is powered from the voltage applied on
the plug J2.
16
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User’s Guide
7
1
2
3
4
5
8
6
9
10
11
36
35
34
33
12
32
31
30
29
28
13
27
26
25
24
23
22
20
21
18
17
16
15
14
19
Figure 6: 73S1217F Evaluation Board Jumper, Switch and Module Locations
Rev. 2.4
17
73S1217F Evaluation Board User’s Guide
4.2
UG_1217F_040
Test Points
The test point numbers listed in Table 3 refer to the test point numbers shown in the electrical schematic
and in the silkscreen of the PCB (see Section 5 73S1217F Evaluation Board Schematics, PCB Layouts
and Bill of Materials).
Table 3: Evaluation Board Test Point Description
Test
Point #
Name
Use
TP1
LIN
Test point to monitor Inductor operation.
TP2
Shutdown
Test point to control the enable input on the RX-232 transceiver chip.
TP4
VPC
Single-pin test point. VPC signal directly connected to the 73S1217F and its
decoupling capacitors. Can be used to measure integrity of the power
supply of the DC-DC converters of the 73S1217F.
TP6
VDD
2-pin test point, with one ground and one VDD signal directly connected to
the 73S1217F and its decoupling capacitors. Can be used to measure the
integrity of the digital power supply of the 73S1217F, or to add a decoupling
capacitor.
TP10
Smart Card
Contacts –
Interface #1
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC1, RST1, CLK1, C81 and C41. Each contact
has its own ground pin on the header.
TP11 to
TP17
GND
Ground test points. Can be used for grounding of lab equipment probes.
TP18
Card Detect – Card detect signal coming directly from the card connectors.
Interface #1
TP21
USR(7:0)
Standard 9/8-bit user I/O port of the 73S1217F.
Some of the user I/Os are shared by the extension 73S80xx
daughter board when using an external smart card interface, and
the LCD interface. Only one should be used at a time.
TP22
USB
TP22 has 4 pins, connected to the USB D+ and D- wires, as well as 2
grounds.
TP24
VBUS
+5 V USB bus. Can be used as a test point for USB voltage presence.
TP25
Smart Card
Contacts –
Interface #2
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC2, RST2, CLK2, C42 and C82. Each contact
has its own ground pin on the header.
TP27
ROW[0:5]
The row pins used for the keypad interface.
TP29
COL[0:4]
The column pins used for the keypad interface.
TP30
INT2
INT3
Interrupt input #2 and #3 of the 73S1217F. This header is close to the
breadboard area for easy wiring.
TP31
RX, TX
The TX and RX serial UART I/O signals (3.3 V digital logic level).
18
Rev. 2.4
UG_1217F_040
Schematic
These test pins should be located between two rows (4
pads each) of SC connector and signal pins locate within
5mm from pads.
CLK track should be routed away from RST and C4.
+5V SOURCE
SELECT
JP1
VPC
5V
+ C1
10uF
LED
RXD
+5VDC
+5VDC
VPC
J2
Banana
TXD
+ C7
1
HEADER 2X2
R2
24
DPLUS
R3
24
DMINUS
100k VBUS_MON
R4
JP23
R5
1
C17
0.1uF
VBUS
AUX1
USR6
Y2
OSC_OUT_12
1
2
3
SCL
OSC_OUT_32
OSC_IN_32
C24
C25
22pF
22pF
SDA
1M
22pF
USR0
USR1
USR2
USR3
USR4
USR5
JP11
32.768kHz
R34
C22
5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SC I/F EXPANSION
GND
VDD
3
2
1
USR7
C23
1
2
3
4
5
6
7
8
9
10
C26
J8
SCLK
SIO
AUX1
AUX2
INT2
GND
GND
GND
5V
5V
USR0
USR1
USR2
USR3
USR4
USR5
USR6/SCL
USR7/SDA
GND
+3.3V
TSM_110_01_L_SV
JP13
SCLK
SIO
SC4
SC8
INT2
GND
GND
GND
+5V
+5V
1
2
3
4
5
6
7
8
9
10
0.1uF
0.47uF
27p
27p
SAD0
SAD1
SAD2
GND
N/C
VPC
N/C
N/C
N/C
PRES
I/O
AUX2
AUX1
GND
AUX2
AUX1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
INT
GND
VDD
SDA
SCL
VDD_ADJ
VCC
RST
CLK
HEADER 2 x 4
TP25
GND
VDD
SDA
SCL
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
C18
VDD
1uF
0
73S8010R
TSM_110_01_L_SV
SMARTCARD
SLOT #2
J9
1
2
3
4
5
6
7
8
R6
VCC
RST
CLK
C4
GND
VPP
I/O
C8
9
10
AUX2
USR5
22pF
J7
SW-1
SW-2
Smart Card Connector
C15
C14
CARD DET
U4
JP2
HEADER 2
JP10
200k
12.000MHz
8010 VPC
SELECT
HEADER 8
USR7
HEADER 2
TP24
OSC_IN_12
C16
TP18
SW-1
SW-2
Smart Card Connector
J10
1
2
TP27
HEADER 2
S28
1
3
1
SW_MOM
COL2
2
SW
R8
10
COL3
1
VDD
VDD
3
F
ROW5
SW_MOM
C43
1000pF
R10
10uF
JP9
JP21
VP
INT2
TP3
INT3
1
2
3
10uH
OFF_REQ
DB5
DB3
DB4
11
10
DB0
E
DB1
DB2
9
7
8
R/W*
RS
VO
3
14
RV1
10K
2
USR3
0.1uF
13
C30
1uF
12
C29 +
1
2
3
LCD
BRIGHTNESS
ADJUST
HEADER 2
10k
COL4
U6
69
VDD
C1+
C1C2+
V-
C2-
13
14
ENB
SHDNB
R1OUTBF
R1OUT
R2OUT
R3OUT
15
1
R1IN
R2IN
R3IN
SLUG
TP32
VDD
R12
R13
3k
3k
VBAT
10k
R25
10k
16
21
20
18
RXD
1217/10
TEST
TBUS0
INT2
INT3
SIO
TBUS1
SCLK
TBUS2
RXTX
GND
TBUS3
VDD
TCLK
ERST
ROW5
ROW4
USR0
R17
R16
R15
DNI
DNI
DNI
INT2
INT3
SIO
SCLK
R11
R14
10k
VDD
R19
ROW5
ROW4
USR0
R20
R22
J11
62
ISY NC/BRKRQ
TBUS[0]
TBUS[1]
TBUS[2]
TBUS[3]
RXTX
TCLK
RST_EMUL
62
62
R23
62
C37
Place R11, R14, R18,
R19, R20, R21, R22
and R23 close to U6
G1 G2 G3 G4 G5 G6 G7 G8 G9
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
Emulator IF
DNI
SY M1
C38
22pF
C39
22pF
C40
22pF
C41
22pF
C42
22pF
1
MOUNT HOLES FOR STAND OFFS
1
1
1
1
1
1
1
1
VDD
PROTO TY PE AREA
62
62
R21
JP6
J12
62
62
VDD
R18
TXD
U7
MAX3237CAI
3
2
1
R24
JP20
R26
RESET
SEC
ISBR
LED0
SCL
SDA
NC/X32OUT
NC/X32IN
GND
X12IN
X12OUT
COL0
COL1
COL2
ANAIN
COL3
RXD
1
TP35
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
8
9
11
ANALOG SELECT ANALOG IN
C35
0.1uF
3
24
23
22
19
17
SCL
SDA
GND
VDD
TP2
T1IN
T2IN
T3IN
T4IN
T5IN
T1OUT
T2OUT
T3OUT
T4OUT
T5OUT
MBAUD
5
6
7
10
12
2
5
9
4
8
3
7
2
6
1
1
HEADER 2
D4
Unpopulated
& unlabled
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
P1
4
LED0
LED
USR5
USR4
USR3
USR2
ROW3
USR1
C34
0.1uF
C33
0.1uF
25
1
SEC
2
3
4
5
6
OSC_OUT_32 7
OSC_IN_32
8
9
OSC_IN_12 10
OSC_OUT_12 11
COL0
12
COL1
13
COL2
14
15
COL3
16
17
DPLUS
DMINUS
DB9_RS232
28
1
2
3
V+
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
27
VCC
C32
0.1uF
2
1
26
JP12
1
2
1
HEADER 2
C31
0.1uF
SERIAL
PORT
8010R INT
1
L1
JP4
JP3
VDD
SHUTDOWN
TP1
+ C2
USR2
S27
USR1
C2 should be as
close as possible
to pin 66
RESET
1
+ C27
10uF
VPC
5V
JP16
USR0
VDD
3
E
ROW4
SW_MOM
S32
3
Z
Y
SW_MOM
COL1
1
SW_MOM
S31
1
TP4
S26
3
ENTER
S30
3
X
SW_MOM
COL0
1
3
VPC
680
C28 should
be as close
as possible
to pin 55
S33
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
3
W
SW_MOM
3
/
SW_MOM
S29
1
S25
1
SW_MOM
3
D
ROW3
SW_MOM
C3, C4 and C5
should be as
close as possible
to VDD pins on U6
6
S24
3
0
SW_MOM
1
R35
USR4
1
3
CLR
SW_MOM
4.7uF
5
S23
3
.
SW_MOM
1
MDL-16265
C28
CW
S22
1
3
9
SW_MOM
+
4
1
JP7
8010 VPC
SELECT
TP6
USR5
3
8
SW_MOM
C5
USR6
1
ON_OFF
S21
VDD
GND
LIN
VPC
VBAT
ON_OFF
VBUS
I/O
C4/AUX1
C8/AUX2
VCC
RST
GND
CLK
VP
PRES
OFF_REQ
3
7
SW_MOM
INT2
INT3
1
2
C4
0.1uF 0.1uF 0.1uF
LED
TXD
COL4
USR7
ROW0
ROW1
USR6
ROW2
GND
NC/DP
NC/DM
VDD
USR5
USR4
USR3
USR2
ROW3
USR1
1
C3
D8
POWER
U5
1
2
DNI
TP30
INT2
INT3
ROW2
SW_MOM
SW_MOM
S20
5.1V
HEADER 3_0
C
DOWN
0
1
2
3
SEC
VDD
S19
TXD
RXD
1
2
3
GND
SW_MOM
S18
SIM/SAM Connector
OPTIONAL LCD DISPLAY SYSTEM
16 CHARACTER BY 2 LINES
2
SW_MOM
1
VDD
1
6
5
SW_MOM
S17
TXD
RXD
S16
3
VDD
D5
3
1
JP15
1
4
3
R27
TP31
ROW1
SW_MOM
S15
1
HEADER 5
C1
C2
C3
C5
C6
C7
SW1
SW2
VDD
3
B
SW_MOM
S14
3
1
27p
HEADER 6
S11
3
UP
+5V
1
1
SW_MOM
S13
3
3
3
SW_MOM
S12
S10
1
VP
SW_MOM
1
3
A
ROW0
SW_MOM
1
2
3
S9
3
2
1
SW_MOM
VBUS
1
3
ON/CE
1
2
3
S8
3
1
1
PWR_ON
S7
1
3
F3
SW_MOM
1
2
3
4
5
6
7
8
C21
27p
1
2
3
4
5
VBAT
1
1
2
3
4
5
6
ON_OFF
3
F2
SW_MOM
S6
1
1
F1
SW_MOM
S5
COL4
USR7
ROW0
ROW1
USR6
ROW2
3
S4
1
S3
C20
TP29
COL0
COL1
COL2
COL3
COL4
2
1
S2
1
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
JP14
30-SWITCH
KEYPAD
NC
VBUS
1
6
9
10
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
1
2
3
4
5
6
7
8
DB7
4
3
2
VCC
RST
CLK
C4
GND
VPP
I/O
C8
2
4
6
8
10
12
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
SIM/SAM Connector
J4
TP21
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
SMARTCARD
SLOT #1
C1
C2
C3
C5
C6
C7
SW1
SW2
1
2
3
4
5
6
7
8
1
3
5
7
9
11
D-
USB_CONN_4
Y1
VDD
C4
CLK
RST
VCC
C8
IO
VCC
GND
5
2
4
1
1
3
VP
+5VDC
SCx_CLK and Vcc tracksC14, C15, C16, C18,
should be routed away C20 and C21 should be
from other Smart card located close to the
signalsand should be Smart Card Connector
surrounded by GND.
GND GND GND GND GND GND GND
GND
+5V
D-
1
2
3
4
5
6
7
8
0
1
2
3
D+
J1
GND
1
1
1
TP22
1
D+
DNI
10uF
2
1
GND
D+
D-
TXD
1
2
GND
GND
680
TP11 TP12 TP13 TP14 TP15 TP16 TP17
1
VBAT
SELECT
3
2
1
JP8
J6
GND
R9
D3
HEADER 2 x 4
TP10
VCC tracks should be
wider than 0.5mm.
(BLK)
5V
RXD
VBAT
GND
J5
Banana
5V
680
R1
(RED)
EXTERNAL POWER
SUPPLY
GND
LED
1
2
3
EXT
VPC
+5VDC
UnReg
VBAT
EXT
J3
Banana
VBAT (4.0 - 6.5VDC)
JP5
R7
D2
DB6
(RED)
1
VPC (2.7-6.5VDC)
Layout TP10 & TP25 as 8x2 header and TP23 and TP26 as 4x2
header. Populate 2pin header to every other rows such as
pin1-2, pin5-6, pin9-10 and pin13-14 for TP10 and TP25.
STATUS INDICATOR
VDD
2
MBR0520L
2
4
6
8
10
12
1
1
2
3
1
2
3
1
3
5
7
9
11
D1
PJ1
+5VDC
VBUS
1
2
3
+5VDC
UnReg
C4
CLK
RST
VCC
C8
IO
5 VDC
UnReg
15
4.3
73S1217F Evaluation Board User’s Guide
Logo
TERIDIAN LOGO
Figure 7: 73S1217F Evaluation Board Electrical Schematic
Rev. 2.4
19
73S1217F Evaluation Board User’s Guide
4.4
UG_1217F_040
PCB Layouts
Figure 8: 73S1217F Evaluation Board Top View (Silkscreen)
20
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User’s Guide
Figure 9: 73S1217F Evaluation Board Bottom View (Silkscreen)
Rev. 2.4
21
73S1217F Evaluation Board User’s Guide
UG_1217F_040
Figure 10: 73S1217F Evaluation Board Top Signal Layer
22
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User’s Guide
Figure 11: 73S1217F Evaluation Board Middle Layer 1 – Ground Plane
Rev. 2.4
23
73S1217F Evaluation Board User’s Guide
UG_1217F_040
Figure 12: 73S1217F Evaluation Board Middle Layer 2 – Supply Plane
24
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User’s Guide
Figure 13: 73S1217F Evaluation Board Bottom Signal Layer
Rev. 2.4
25
73S1217F Evaluation Board User’s Guide
4.5
UG_1217F_040
Bill of Materials
Table 4 provides the bill of materials for the 73S1217F Evaluation Board schematic provided in Figure 12.
Table 4: 73S1217F Evaluation Board Bill of Materials
Part Number
Manufacturer
3528-21 (EIA)
0805
603
Digi-key Part
Number
478-1672-1-ND
PCC2225CT-ND
PCC1762CT-ND
TAJB106K010R
ECJ-2FB0J106M
ECJ-1VB1C104K
AVX Corporation
Panasonic
TDK Corporation
4.7 µF
0603
PCC2396CT-ND
ECJ-1VB0J475K
Panasonic
C16
C14,C15,C20,C21
C18,C29
0.47 µF
27 pF
1 µF
0603
603
603
PCC2275CT-ND
ECJ-1VB1A474K
Panasonic
PCC270ACVCT-ND ECJ-1VC1H270J
Panasonic
PCC2174CT-ND
C1608X5R1A105K TDK Corporation
9
1
1
C22-C25, C38-42
C43
D1
22 pF
1000 pF
MBR0520L
603
603
SOD-123
PCC220ACVCT-ND ECJ-1VC1H220J
PCC2151CT-ND
ECJ-1VC1H102J
MBR0520LCT-ND MBR0520L
Panasonic
Panasonic
Fairchild
11
12
4
13
LED
HEADER 3
805
1 x 3 pin
160-1414-1-ND
S1011E-36-ND
LTST-C170FKT
PBC36SAAN
LITE-ON INC
Sullins Electronics
13
6
HEADER 2
1 x 2 pin
S1011E-36-ND
PBC36SAAN
Sullins Electronics
14
2
D2,D3,D4,D8
JP1,JP2,JP5,JP6,JP7,
JP8,JP9,JP11,JP13,
JP15, JP16, JP20, JP21
JP3,JP4,JP10,JP12,
JP14, JP23
J1,J10
ITT_CCM003_3754
CCM03-3754
C&K
15
16
17
2
1
2
J2,J3
J5
J4,J9
Banana
Banana
ITT_CCM002-2504
16BJ381
16BJ382
CCM02-2504LFT
Mouser
Mouser
C&K
18
1
J6
SIM/SAM
Connector
Banana (red)
Banana (black)
Smart Card
Connector
USB_CONN_4
19
2
J8,J7
TSM_110_01_L_SV TSM_110_01_L_SV
20
1
J11
Emulator IF
21
1
L1
10 µH
Item
Qty. Reference
Part
PCB Footprint
1
2
3
1
2
11
10 µF
10 µF
0.1 µF
4
1
C27
C1,C2
C3,C4,C5,C17,C26,C30,
C31,C32,C33, C34,C35
C28
5
6
7
1
4
2
8
9
10
26
USB_AU_Y1007
ED90064-ND
897-43-004-90Mill-Max
000000
TSM_110_01_L_SV Samtec
10 X 2 pin
A3210-ND
104068-1
1210
490-4059-1-ND
AMP/Tyco
Electronics
LQH32CN100K53L Murata
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User’s Guide
Part Number
Manufacturer
RAPC712
AMP_745781
Digi-key Part
Number
SC1152-ND
A2100-ND
RAPC712
745781-4
10 kΩ
0Ω
24 Ω
100 kΩ
200 kΩ
680 Ω
10 Ω
10 kΩ
62 Ω
3266W
603
603
603
603
603
603
603
603
3266W-103-ND
P0.0GCT-ND
P24GCT-ND
P100KGCT-ND
P200KGCT-ND
P680GCT-ND
P10GCT-ND
P10KGCT-ND
P62GCT-ND
3266W-1-103
ERJ-3GEY0R00V
ERJ-3GEYJ240V
ERJ-3GEYJ104V
ERJ-3GEYJ204V
ERJ-3GEYJ681V
ERJ-3GEYJ100V
ERJ-3GEYJ103V
ERJ-3GEYJ620V
Switchcraft
AMP/Tyco
Electronics
Bourns
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
3 kΩ
1 MΩ
SW_MOM
603
603
Pushbutton SW
P3.0KGCT-ND
P1.0MGCT-ND
401-1885-ND
ERJ-3GEYJ302V
ERJ-3GEYJ106V
D6 C 10LFS
Panasonic
Panasonic
ITT Industries
SW
TP
Panasonic EVQ
1 pin
P8051SCT
S1011-36-ND
EVQ-PJX05M
PZC36SAAN
Panasonic
Sullins Electronics
TP2, TP18
TP
1 Pin White
5012K-ND
5012
1
TP4
TP
1 pin Red
5010K-ND
5010
40
3
TP11,TP12,TP17
TP
1 pin Black
5011K-ND
5011
41
42
43
44
3
2
1
1
TP6,TP30,TP31
TP10,TP25
TP21
TP22
TP2
HEADER 2 x 6
HEADER 8
HEADER 2X2
1
6
1
2
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
PBC36SAAN
PBC36SAAN
PBC36SAAN
PBC36SAAN
Keystone
Electronics
Keystone
Electronics
Keystone
Electronics
Sullins Electronics
Sullins Electronics
Sullins Electronics
Sullins Electronics
Item
Qty. Reference
Part
PCB Footprint
22
23
1
1
PJ1
P1
+5 VDC
DB9_RS232
24
25
26
27
28
29
30
31
32
1
2
2
1
1
3
1
4
8
33
34
35
2
1
31
36
37
1
3
RV1
R1,R6,R27
R2,R3
R4
R5
R7,R9,R35
R8
R10, R24, R25, R26
R11,R14,R18,R19,R20,
R21, R22,R23
R12,R13
R34
S2,S3,S4,S5,S6,S7,S8,
S9,S10,S11,S12,S13,S14,
S15,S16,S17,S18,S19,
S20,S21,S22,S23,S24,
S25,S26,S28,S29,S30,
S31,S32,S33
S27
TP18, TP24, TP32
38
2
39
Rev. 2.4
x 2 pin
x 2 pin
x 8 pin
x 2 pin
27
73S1217F Evaluation Board User’s Guide
UG_1217F_040
Digi-key Part
Number
S1011E-36-ND
S1011E-36-ND
Item
Qty. Reference
Part
PCB Footprint
45
46
1
1
TP27
TP29
HEADER 6
HEADER 5
6 x 1 pin
5 x 1 pin
47
1
U4
73S8010R
73S8010R
48
49
1
1
U5
U6
MDL-16265
73S1217F
153-1078-ND
50
51
52
1
1
1
U7
Y1
Y2
MAX3237CAI
12.000 MHz
32.768 kHz
28
68 QFN
MAX3237CAI-ND
X1116-ND
XC1195CT-ND
Part Number
Manufacturer
PBC36SAAN
PBC36SAAN
Sullins Electronics
Sullins Electronics
Teridian
Semiconductor
MDL-16265-SS-LV Varitronix
73S1217F
Teridian
Semiconductor
MAX3237CAI
Maxim
ECS-120-20-4XDN ECS
ECS-.327-12.5ECS
17X-TR
Rev. 2.4
UG_1217F_040
4.6
73S1217F Evaluation Board User Guide
Schematic Information
This section provides recommendations on proper schematic design that will help in designing circuits
that are functional and compatible with the software library APIs.
4.6.1 Reset Circuit
The 73S1217F Evaluation Board provides a reset pushbutton that can be used when prototyping and
debugging software. The RESET pin should be supported by the external components shown in Figure 6.
R8 should be around 10 Ω. The capacitor C27 should be 10 µF. R8 and C27 should be mounted as
close as possible to the IC.
C43 (1000 pF) is shown for EFT protection and is optional.
3.3V
RESET
S27
2
1
+ C27
10uF
SW
R8
10
RESET
R10
10k
C43
1000pF
Figure 14: External Components for RESET
4.6.2 Oscillators
The 73S1217F offers two oscillators (see Figure 7); one for the primary system clock and the other for an
RTC (32 kHz). The system clock should use a 12 MHz crystal to provide the proper system clock rates
for the USB, serial and smart card interfaces. The system oscillator requires a 1 MΩ parallel resistor to
insure proper oscillator startup.
The RTC oscillator drives a standard 32.768 kHz watch crystal. Crystals of this type are accurate and do
not require a high current oscillator circuit. The oscillator in the 73S1217F has been designed specifically to
handle watch crystals and is compatible with their high impedance and limited power handling capability.
The 32 kHz oscillator does not require a parallel startup resistor.
73S1217F
Figure 15: Oscillator Circuit
Rev. 2.4
29
73S1217F Evaluation Board User’s Guide
UG_1217F_040
4.6.3 LCD
The 73S1217F does not contain an on-chip LCD controller. However, an LCD module (with built-in
controller) can be used with the 73S1217F via use of specific USR (GPIO) pins. The LCD API libraries
support up to a 2 line/16 character display. Figure 8 shows the basic connection for this type of LCD. The
LCD module must connect to the USR pins as shown and it requires an external brightness adjust circuit.
73S1217F
Figure 16: LCD Connections
4.6.4 USB Interface
The USB interface on the 73S1217F requires few external components for proper operation. Two serial
resistors of 24 Ω ± 1% are needed to provide proper impedance matching for the USB data signals D+
and D-.
For self-powered USB applications, a connection must be made between the VBUS power input and
USR7 for proper operation with the provided API libraries. A direct connection cannot be made as the
VBUS voltage exceeds the digital power supply running at 3.3 V. As a result, a resistor divider is required
to scale the VBUS voltage down to 3.3 V. Figure 9 shows the basic USB connections.
73S1217F
Figure 17: USB Connections
30
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User Guide
4.6.5 Smart Card Interface
The smart card interface on the 73S1217F requires few external components for proper operation.
Figure 10 shows the recommended smart card interface connections.
•
•
•
•
•
The RST and CLK signals should have 27 pF capacitors at the smart card connector.
It is recommended that a 0 Ω resistor be added in series with the CLK signal. If necessary, in noisy
environments, this resistor can be replaced with a small resistor to create a RC filter on the CLK
signal to reduce CLK noise. This filter is used to soften the clock edges and provide a cleaner clock
for those environments where this could be problematic.
The VCC output must have a 1.0 µF capacitor at the smart card connector for proper operation.
The VPC input is the power supply input for the smart card power. It is recommended that both a
10µF and a 0.1 µF capacitor are connected to provide proper decoupling for this input.
The PRES input on the 73S1217F contains a very weak pull down resistor. As a result, an additional
external pull down resistor is recommended to prevent any system noise from triggering a false card
event. The same holds true for the PRES input, except a pull up resistor is utilized as the logic is
inverted from the PRES input.
The smart card interface layout is important. The following guidelines should be followed to provide the
optimum smart card interface operation:
•
•
•
•
•
•
•
Route auxiliary signals away from card interface signals
Keep CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to
one layer (avoid vias to other plane). Keep CLK trace away from other traces especially RST and
VCC. Filtering of the CLK trace is allowed for noise purpose. Up to 30 pF to ground is allowed at the
CLK pin of the smart card connector. Also, the zero ohm series resistor, R7, can be replaced for
additional filtering (no more than 100 Ω).
Keep VCC trace as short as possible. Make trace a minimum of 0.5 mm thick. Also, keep VCC away
from other traces especially RST and CLK.
Keep CLK trace away from VCC and RST traces. Up to 30 pF to ground is allowed for filtering
Keep 0.1 µF close to VDD pin of the device and directly take other end to ground
Keep 10 µF and 0.1 µF capacitors close to VPC pin of the device and directly take other end to
ground
Keep 1.0 µF close to VCC pin of the smart card connector and directly take other end to ground
1215
Figure 18: Smart Card Connections
Rev. 2.4
31
73S1217F Evaluation Board User’s Guide
UG_1217F_040
5 Ordering Information
Part Description
Order Number
73S1217F 68-Pin QFN Evaluation Board
73S1217F-EB
6 Related Documentation
The following 73S1217F documents are available from Teridian Semiconductor Corporation:
73S1217F Data Sheet
73S1217F Evaluation Board Quick Start Guide
TSC Flash Programmer Model TFP2 User’s Manual
7 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S1217F
contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: scr.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
32
Rev. 2.4
UG_1217F_040
73S1217F Evaluation Board User Guide
Revision History
Revision
Date
Description
1.0
September 25, 2007
First Publication.
2.0
November 29, 2007
Updated to Rev B PWB and added emulator usage and Schematic
descriptions.
2.1
January 3, 2007
Removed pull up resistors and 1000 pF capacitor from ICE interface
and added LED0 jumper description.
2.2
February 12, 2007
Changed 5.1 V zener diode part number and value of limiting
resistor R27.
2.3
January 8, 2009
Updated BOM parts to remove bad or obsolete part numbers.
Removed Zener and current limiting resistor.
2.4
August 17, 2009
Removed LAPIE references.
Added information from the Quick Start Guide.
Miscellaneous editorial modifications.
Rev. 2.4
33
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