DS1238A-10N+

DS1238A MicroManager www.dalsemi.com FEATURES














PIN ASSIGNMENT Holds microprocessor in check during power transients Halts and restarts an out-of-control microprocessor Warns microprocessor of an impending power failure Converts CMOS SRAM into nonvolatile memory Unconditionally write protects memory when power supply is out of tolerance Delays write protection until completion of the current memory cycle Consumes less than 200 nA of battery current Controls external power switch for high current applications Debounces pushbutton reset Accurate 10% power supply monitoring Optional 5% power supply monitoring designated DS1238A-5 Provides orderly shutdown in microprocessor applications Pin-for-pin compatible with MAX691 Standard 16-pin DIP or space-saving 16-pin SOIC Optional industrial temperature range -40°C to +85°C VBAT 1 16 RST VCCO 2 15 RST VCC 3 14 WDS GND 4 13 CEI PF 5 12 CEO RVT 6 11 ST OSCIN 7 10 NMI OSCSEL 8 9 IN VBAT VCCO VCC GND PF RVT OSCIN OSCSEL 16-Pin DIP (300-mil) See Mech. Drawings Section 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RST RST WDS CEI CEO ST NMI IN 16-Pin SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION VBAT VCCO VCC GND PF RVT OSCIN OSCSEL IN NMI ST CEO CEI WDS RST RST - +3-Volt Battery Input - Switched SRAM Supply Output - +5-Volt Power Supply Input - Ground - Power-Fail - Reset Voltage Threshold - Oscillator In - Oscillator Select - Early Warning Input - Non-Maskable Interrupt - Strobe Input - Chip Enable Output - Chip Enable Input - Watchdog Status - Reset Output (active low) - Reset Output (active high) DESCRIPTION The DS1238A MicroManager provides all the necessary functions for power supply monitoring, reset control, and memory backup in microprocessor-based systems. A precise internal voltage reference and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally write protects external memory. The DS1238A also provides early warning detection of a user-defined threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset 1 of 13 111899 DS1238A debounce circuit connected to the RST pin. An internal watchdog timer can also force the reset outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Oscillator control pins OSCSEL and OSCIN provide either external or internal clock timing for both the reset pulse width and the watchdog timeout period. The Watchdog Status and Reset Voltage Threshold are provided via WDS and RVT , respectively. A block diagram of the DS1238A is shown in NO TAG. PIN DESCRIPTION PIN NAME VBAT DESCRIPTION +3V battery input provides nonvolatile operation of control functions. VCCO VCC output for nonvolatile SRAM applications. VCC +5V primary power input. PF Power-fail indicator, active high, used for external power switching as shown in NO TAG. RVT Reset Voltage Threshold. Indicates that VCC is below the reset voltage threshold. OSCIN Oscillator input or timing capacitor. See NO TAG. OSCSEL Oscillator Select. Selects internal or external clock functions. See NO TAG. IN Early warning power-fail input. This voltage sense point can be tied (via resistor divider) to a user-selected voltage. NMI Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending power failure. ST Strobe input. A high-to-low transition will reset the watchdog timer, indicating that software is still in control. CEO Chip enable output. Used with nonvolatile SRAM applications. CEI Chip enable input. WDS Watchdog Status. Indicates that a watchdog timeout has occurred. RST Active low reset output. RST Active high reset output. POWER MONITOR The DS1238A employs a bandgap voltage reference and a precision comparator to monitor the 5-volt supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RVT , RST, and RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation so that the RVT , RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical). The VCCTP for the 5% operation option (DS1238A-5) is set for 4.75 volts (4.62 typical). The RST and RST signals are excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-tolerance VCC. On power-up, RVT will become inactive as soon as VCC rises above VCCTP. However, the RST and RST signals remain active for a minimum of 50 ms (100 ms typical) after VCCTP is reached to allow the power supply and microprocessor to stabilize. 2 of 13 DS1238A DS1238A FUNCTIONAL BLOCK DIAGRAM Figure 1 WATCHDOG TIMER The DS1238A provides a watchdog timer function which forces the WDS , RST, and RST signals to the active state when the strobe input ( ST ) is not stimulated for a predetermined time period. This time period is described below in NO TAG. The watchdog timeout period begins as soon as RST and RST are inactive. If a high-to-low transition occurs at the ST input prior to timeout, the watchdog timer is reset and begins to timeout again. The ST input timing is shown in NO TAG. In order to guarantee that the watchdog timer does not timeout, a high-to-low transition on ST must occur at or less than the minimum timeout of the watchdog as described in the AC Electrical Characteristics. If the watchdog timer is allowed to time out, the WDS , RST, and RST outputs are driven to the active state. WDS is a latched signal which indicates the watchdog status, and is activated as soon as the watchdog timer completes a 3 of 13 DS1238A full period as outlined in NO TAG. The WDS pin will remain low until one of three operations occurs. The first is to strobe the ST pin with a falling edge, which will both set the WDS as well as the watchdog timer count. The second is to leave the ST pin open, which disables the watchdog. Lastly, the WDS pin is active low whenever VCC falls below VCCTP and activates the RVT signal. The ST input can be derived from microprocessor address, data, or control signals, as well as microcontroller port pins. Under normal operating conditions, these signals would routinely reset the watchdog timer prior to timeout. The watchdog is disabled by leaving the ST input open, or as soon as VCC falls to VCCTP. NON-MASKABLE INTERRUPT The DS1238A generates a non-maskable interrupt ( NMI ) for early warning of a power failure to the microprocessor. A precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated by an internal band gap. The IN pin is a high-impedance input allowing for a userdefined sense point. An external resistor voltage divider network (NO TAG) is used to interface with high voltage signals. This sense point may be derived from the regulated 5-volt supply, or from a higher DC voltage level closer to the main system power input. Since the IN trip point VTP is 1.27 volts, the proper values for R1 and R2 can be determined by the equation as shown in NO TAG. Proper operation of the DS1238A requires that the voltage at the IN pin be limited to VIH. Therefore, the maximum allowable voltage at the supply being monitored (VMAX) can also be derived as shown in NO TAG. A simple approach to solving this equation is to select a value for R2 of high enough value to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for microprocessor shutdown between NMI and RST or RST . When the supply being monitored decays to the voltage sense point, the DS1238A will force the NMI output to an active state. Noise is removed from the NMI power-fail detection circuitry using built-in time domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an internal ring oscillator running at approximately 30 kHz (33 µs/cycle). Three consecutive samplings of out-of-tolerance supply (below VSENSE) must occur at the IN pin to active NMI . Therefore, the supply must be below the voltage sense point for approximately 100 µs or the comparator will reset. In this way, power supply noise is removed from the monitoring function preventing false trips. During a power-up, any IN pin levels below VTP detected by the comparator are disabled from reaching the NMI pin until VCC rises to VCCTP. As a result, any potential active NMI will not be initiated until VCC reaches VCCTP. Removal of an active low level on the NMI pin is controlled by the subsequent rise of the IN pin above VTP. The initiation and removal of the NMI signal during power up depends on the relative voltage relationship between VCC and the IN pin voltage. Note that a fast-slewing power supply may cause the NMI to be virtually nonexistent on power-up. This is of no consequence, however, since an RST will be active. The NMI voltage will follow VCC down until VCC decays to VBAT. Once VCC decays to V BAT , the NMI pin will enter a tri-state mode. ST INPUT TIMING Figure 2 4 of 13 DS1238A OSCILLATOR CONTROLS Table 1 Watchdog Timeout Period (typ) External Internal OSCIN OSCSEL First Period Following a Reset Other Timeout Reset Active Duration Ext Clk Low 20480 Clks 5120 Clocks 641 Clks Ext Cap Low Low Hi/Open 2.7 sec 170 ms 85 ms Hi/Open Hi/Open 2.7 sec 2.7 sec 85 ms ≅ 2.2 sec X Cpf 47 pf ≅ 550 ms X Cpf 47 pf ≅ 69 ms X Cpf 47 pf Note that the OSCIN and OSCSEL pins are tri-stated when VCC is below VBAT. POWER MONITOR, WATCHDOG TIMER, AND PUSHBUTTON RESET Figure 3 PUSHBUTTON RESET TIMING Figure 4 5 of 13 DS1238A NON-MASKABLE INTERRUPT Figure 5 VSENSE = R1 +R2 x 1.27 R2 MAXVOLTAGE = VSENSE x 5.0 = VMAX 1.27 Example 2: 12-Volt Supply, R2 = 10k Ohms, VSENSE = 9.0 Volts Example 1: 5-Volt Supply, R2 = 10k Ohms, VSENSE = 4.8 Volts 4.8 = R1 + 10k x 1.27 ≥ R1 = 27.8k Ohm 10k 9.0 = R1 + 10k x 1.27 ≥ R1 = 60.9k Ohm 10k VMAX = NMI FROM IN INPUT Figure 6 6 of 13 9.00 x 5.0 = 35.4 Volts 1.27 DS1238A MEMORY BACKUP The DS1238A provides all of the necessary functions required to battery back a static RAM. First, an internal switch is provided to supply SRAM power from the primary 5-volt supply (VCC) or from an external battery (VBAT), whichever is greater. Second, the same power-fail detection described in the power monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of VCC or to within 0.7 volts of VBAT. The output voltage diode drop from VBAT (0.7V) is necessary to prevent charging of the battery in violation of UL standards. Write protection occurs as VCC falls below VCCTP as specified. If CEI is low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high, or the period tCE expires. This delay of write protection until the current memory cycle is completed prevents the corruption of data. If CEO is in an inactive state at the time of VCC fail detection, CEO will be unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application. FRESHNESS SEAL In order to conserve battery capacity during initial construction of an end system, the DS1238A provides a freshness seal that electrically disconnects the battery. This means that upon battery attachment, the VCCO output will remain inactive until VCC is applied. This prevents VCCO from powering other devices when the battery is first attached, and VCC is not present. Once VCC is applied, the freshness seal is broken and cannot be invoked again without subsequent removal and reattachment of the battery. POWER SWITCHING When larger operating currents are required in a battery-backed system, the internal switching devices of the DS1238A may be too small to support the required load through VCCO with a reasonable voltage drop. For these applications, the PF output is provided to gate external power switching devices. As shown in Figure 8, power to the load is switched from VCC to battery on power-down, and from battery to VCC on power-up. The DS1336 is designed to use the PF output to switch between VBAT and VCC. It provides better leakage and switchover performance than currently available discrete components. The transition threshold for PF is set to the external battery voltage VBAT, allowing a smooth transition between sources. Any load applied to the PF pin by an external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should be taken into consideration when sizing the battery. NONVOLATILE SRAM Figure 7 7 of 13 DS1238A POWER SWITCHING Figure 8 Note: If freshness on the DS1238A is not used, and VBAT01 for system use. PF on the DS1336 may be tied to OUT1. This will free IN4, OUT4, TIMING DIAGRAMS This section provides a description of the timing diagrams shown in Figure 9 and Figure 10. Figure 9 illustrates the relationship for power down. As VCC falls, the IN pin voltage drops below VTP. As a result, the processor is notified of an impending power failure via an active NMI . This gives the processor time to save critical data in nonvolatile SRAM. As the power falls further, VCC crosses VCCTP, the power monitor trip point. When VCC reaches VCCTP, and active RST and RST are given. At this time, CEO is brought high to write-protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF pin. Figure 10 shows the power-up sequence. As VCC slews above VBAT, the PF pin is deactivated. An active reset occurs as well as an NMI . Although the NMI may be short due to slew rates, reset will be maintained for the standard tRPU timeout period . At a later time, if the IN pin falls below VTP, a new NMI will occur. If the processor does not issue an ST , a watchdog reset will also occur. The second NMI and RST are provided to illustrate these possibilities. 8 of 13 DS1238A POWER-DOWN TIMING Figure 9 9 of 13 DS1238A POWER-UP TIMING Figure 10 10 of 13 DS1238A ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to Ground Voltage on I/O Relative to Ground Operating Temperature Operating Temperature (Industrial Version) Storage Temperature Soldering Temperature -0.5V to +7.0V -0.5V to VCC + 0.5V 0°C to 70°C -40°C to +85°C -55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC 4.5 5.0 5.5 V 1 Supply Voltage (5% Option) VCC 4.75 5.0 5.5 V 1 Input High Level VIH 2.0 VCC+0.3 V 1 Input Low Level VIL -0.3 +0.8 V 1 IN Input Pin VIN 0 VCC V 1 Battery Input VBAT 0 4.0 V 1 (0°C to 70°C; VDD= 5V ± 10%) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Current ICC Battery Current IBAT Supply Output Current (VCCO = VCC - 0.3V) MAX UNITS NOTES 4 mA 2 200 nA 2, 12 ICC01 100 mA 3 Supply Out Current (VCC < VBAT) ICC02 1 mA 4 Supply Output Voltage VCCO V 1 Battery Back Voltage VCCO V 6 Low Level @ RST VOL V 1 Output Voltage @ -500 µA VOH VCC-0.5V VCC-0.1V V 1 VOHL VBAT-0.8 V 6 CEO and PF Output MIN TYP 0 VCC-0.3 VBAT-0.8 0.4 Input Leakage Current ILI -1.0 +1.0 µA 2 Output Leakage Current ILO -1.0 +1.0 µA 11 Output Current @ 0.4V IOL 4.0 mA 9 Output Current @ 2.4V IOH -1.0 mA 10 Power Sup. Trip Point VCCTP 4.25 4.37 4.50 V 1 Power Supply Trip (5% Option) VCCTP 4.50 4.62 4.75 V IN Input Pin Current ICCIN -1.0 +1.0 µA IN Input Trip Point VTP 1.15 1.35 V 11 of 13 1.27 1 DS1238A (0°C to 70°C; VCC= 5V ± 10%) AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL tRPD MIN 40 TYP 100 MAX 175 UNITS VTP to NMI tIPD 40 100 175 µs RESET Active OSCSEL=high tRST 40 85 150 ms tST 20 ns PBRST @ VIL tPB 30 ms VCC Slew Rate 4.75 to 4.25 tF 300 µs Chip Enable Prop Delay tPD VCC Fail to Chip Enable High tCF VCC Valid to RST (RC=1) tFPU VCC Valid to RST tRPU 40 VCC Slew to 4.25 to VBAT tFB1 10 µs Chip Enable Output Recovery Time tREC 0.1 µs VCC Slew 4.25 to 4.75 tR 0 µs Chip Enable Pulse Width tCE Watchdog Time Delay Int Clock Long period tTD VCC Fail Detect to RST, RST ST Pulse Width Short period Watchdog Time Delay, Ext Clock, after Reset 7 OSC IN Frequency fOSC ns 144 µs 100 ns 150 ms Input Capacitance Output Capacitance 11 5 7 µs 8 2.7 s 110 170 ms 20480 clocks 5120 clocks 0 2 µs 250 kHz CAPACITANCE PARAMETER 13 1.7 Normal tPPF 100 µs 20 5 tTD VBAT Detect to PF 12 NOTES (tA=25°C) SYMBOL MIN MAX UNITS CIN 5 pF COUT 7 pF 12 of 13 TYP NOTES DS1238A NOTES: 1. All voltages referenced to ground. 2. Measured with VCCO, CEO , PF, ST , RST, RST , and NMI pin open. 3. ICCO1 is the maximum average load which the DS1238A can supply at VCC-.3V through the VCCO pin during normal 5-volt operation. 4. ICCO2 is the maximum average load which the DS1238A can supply through the VCCO pin during data retention battery supply operation, with a maximum drop of 0.8 volts for commercial, 1.0V for industrial. 5. With tR = 5 µs. 6. VCCO is approximately VBAT-0.5V at 1 µA load. 7. tREC is the minimum time required before CEI / CEO memory access is allowed. 8. tCE maximum must be met to insure data integrity on power loss. 9. All outputs except RST which is 25 µA max. 10. All outputs except RST , RTV , and NMI which is 25 µA min. 11. The ST pin will sink ±50 µA in normal operation. The OSCIN pin will sink ±5 µA in normal operation. The OSCSEL pin will sink ±10 µA in normal operation. 12. IBAT is measured with VBAT=3.0V. 13. ST should be active low before the watchdog is disabled (i.e., before the ST input is tristated). 13 of 13