Rev 2; 2/06
KIT
ATION
EVALU
E
L
B
AVAILA
LDMOS RF Power-Amplifier Bias
Controller
Features
The DS1870 is a dual-channel bias controller targeted
toward class AB LDMOS RF power-amplifier applications. It uses lookup tables (LUTs) to control 256-position potentiometers based on the amplifier’s
temperature and drain voltage or current (or other
external monitored signal). With its internal temperature
sensor and multichannel A/D converter (ADC), the
DS1870 provides a cost-effective solution that improves
the amplifier’s efficiency by using nonlinear compensation schemes that are not possible with conventional
biasing solutions.
♦ Two-Channel Solution for Programmable RF Bias
Control
♦ The Potentiometer’s Position is Automatically
Updated to Compensate for the Ambient
Temperature and the Drain Voltage or Current
♦ A Five-Channel, 13-Bit ADC Continuously
Monitors the Ambient Temperature, VCC, VD, ID1,
and ID2
♦ Hi/Lo Alarms for Each ADC Channel can Trigger a
Fault Output
♦ Nonvolatile Memory for the Device Settings,
Lookup Tables, and 32-Bytes of User Memory
♦ I2C-Compatible Serial Interface with Up to Eight
Devices on the Same Serial Bus
♦ Single 5V Power Supply
♦ Small 16-Pin TSSOP Package
♦ -40°C to +95°C Operational Temperature Range
Applications
Cellular Base Stations
Medical Equipment
Industrial Controls
Optical Transceivers
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS1870E-010
-40°C to +95°C
16 TSSOP
(173 mils)
DS1870E-010+
-40°C to +95°C
16 TSSOP
(173 mils)
+Denotes lead-free package.
Typical Operating Circuit appears at end of data sheet.
Pin Configuration
TOP VIEW
1
L1
VCC
16
2
W1
HCOM
15
3
W2
SDA
14
4
L2
SCL
13
5
ID1
A2
12
6
ID2
A1
11
7
VD
A0
10
8
GND
DS1870
FAULT
9
TSSOP (173 mils)
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS1870
General Description
DS1870
LDMOS RF Power-Amplifier Bias
Controller
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ...........................-40°C to +95°C
EEPROM Programming Temperature Range .........0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020A Specification
Voltage Range on VCC, HCOM, SDA, and SCL Pins Relative to
Ground ...............................................................-0.5V to +6.0V
Voltage Range on A0, A1, A2, FAULT, VD, ID1, ID2 Relative to
Ground. ...................-0.5V to VCC + 0.5V, not to exceed +6.0V
Voltage Range on L0, L1, W0, and W1 Relative to
Ground .................-0.5V to HCOM + 0.5V, not to exceed +6.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +95°C)
PARAMETER
SYMBOL
MAX
UNITS
4.5
5.5
V
VIH
0.7 x
VCC
VCC +
0.3
V
VIL
-0.3
+0.3 x
VCC
V
HCOM Voltage
4.5
5.5
V
LX and WX Voltage
-0.3
HCOM
+ 0.3
V
-1
+1
mA
MAX
2
UNITS
mA
Supply Voltage
VCC
Input Logic 1
(SDA, SCL, A2, A1, A0)
Input Logic 0
(SDA, SCL, A2, A1, A0)
CONDITIONS
(Note 1)
Wiper Current
MIN
TYP
DC ELECTRICAL CHARACTERISTICS
(VCC = +4.5 to 5.5V, TA = -40°C to +95°C.)
PARAMETER
Supply Current
Input Leakage
SYMBOL
ICC
CONDITIONS
MIN
(Note 2)
+200
nA
Low-Level Output Voltage
(SDA, FAULT)
VOL1
3mA sink current
0.4
V
VOL2
6mA sink current
0.6
V
I/O Capacitance
CI/O
10
pF
Digital Power-On Reset
VPOD
1.0
2.2
V
Analog Power-On Reset
VPOA
2.0
2.8
V
2
ILI
-200
TYP
1
_____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
(VCC = +4.5 to 5.5V, TA = -40°C to +95°C.)
PARAMETER
MIN
TYP
MAX
UNITS
Code FFF8h
2.488
2.500
2.513
V
VCC Monitor FactoryCalibrated FS
Code FFF8h
6.521
6.553
6.587
V
ID1 and ID2 Monitor FactoryCalibrated FS
Code FFF8h
0.4975
0.5000
0.5025
V
VD Monitor FactoryCalibrated FS
SYMBOL
CONDITIONS
Resolution
(VCC, VD, ID1, ID2)
0.0122
Accuracy
(VCC, VD, ID1, ID2)
0.25
Update Rate for
VCC, VD, ID1, ID2
tframe
%FS
0.5
50
%FS
ms
DIGITAL THERMOMETER CHARACTERISTICS
(VCC = +4.5 to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
Thermometer Error
TERR
Update Rate
tframe
CONDITIONS
-40°C to 95°C
MIN
TYP
-3
MAX
+3
50
UNITS
°C
ms
ANALOG POTENTIOMETER CHARACTERISTICS
(VCC = +4.5 to 5.5V, TA = -40°C to +95°C.)
PARAMETER
Wiper Resistance
Potentiometer
End-to-End Resistance
SYMBOL
CONDITIONS
MIN
TYP
500
MAX
1000
UNITS
Ω
10.0
13
16.8
kΩ
+25°C
RPOT
+25°C
Resolution
0.4
%FS
Absolute Linearity
(Note 3)
-1
+1
LSB
Relative Linearity
(Note 4)
-0.5
+0.5
LSB
Ratiometric Temperature
Coefficient
5
ppm/°C
End-to-End Temperature
Coefficient
70
ppm/°C
1
MHz
-3dB Cutoff Frequency
Series Resistors from L1, L2 to
GND
VHCOM/VLX
(Note 5)
RS
+25°C
15.1
19.5
25.2
0.5975
0.6
0.6025
kΩ
_____________________________________________________________________
3
DS1870
ANALOG VOLTAGE-MONITORING CHARACTERISTICS
DS1870
LDMOS RF Power-Amplifier Bias
Controller
LOOKUP TABLE CHARACTERISTICS
(VCC = +4.5 to 5.5V, TA = -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
POT1 and POT2 Temp LUT Size
-40
Temp Step
(Note 6)
POT1 and POT2 Drain LUT Size
POT1 and POT2 Drain LUT VD
Index Range
(Note 6)
POT1 and POT2 Drain LUT IDX
Index Range
POT1 and POT2 Drain LUT IDX
Hysteresis
4
(Note 6)
_____________________________________________________________________
°C
2
°C
1
°C
64
Bytes
each
FE00
Hex
0200
Hex
0100
Hex
0000
POT1 and POT2 Drain LUT IDX
Step
UNITS
Bytes
each
+102
8000
POT1 and POT2 Drain LUT VD
Step
POT1 and POT2 Drain LUT VD
Hysteresis
MAX
72
POT1 and POT2 Temp LUT Index
Range
Temp Hysteresis
TYP
7E00
Hex
0200
Hex
0100
Hex
LDMOS RF Power-Amplifier Bias
Controller
(VCC = +4.5V to 5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 3)
PARAMETER
SCL Clock Frequency
Bus Free Time Between Stop and
Start Conditions
Hold Time (Repeated) Start
Condition
Low Period of SCL
High Period of SCL
Data Hold Time
Data Setup Time
Start Setup Time
SYMBOL
fSCL
CONDITIONS
(Note 7)
TYP
MAX
400
UNITS
kHz
tBUF
1.3
µs
tHD:STA
0.6
µs
tLOW
tHIGH
1.3
0.6
0
100
0.6
20 +
0.1CB
20 +
0.1CB
0.6
0.9
µs
µs
µs
ns
µs
300
ns
300
ns
tHD:DAT
tSU:DAT
tSU:STA
SDA and SCL Rise Time
tR
(Note 8)
SDA and SCL Fall Time
tF
(Note 8)
Stop Setup Time
SDA and SCL Capacitive
Loading
EEPROM Write Time
MIN
0
tSU:STO
CB
(Note 8)
tW
(Note 9)
µs
400
pF
10
20
ms
TYP
MAX
UNITS
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +4.5V to 5.5V, TA = 0°C to +70°C.)
PARAMETER
Writes
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
SYMBOL
CONDITIONS
+70°C (Note 5)
MIN
50,000
All voltages referenced to ground.
Supply current is measured with all logic inputs at their inactive state (SDA = SCL = VCC) and driven to well-defined logic
levels. All outputs are disconnected.
Absolute linearity is the difference of measured value from expected value at the DAC position. Expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. Expected LSB change is
the slope of the straight line from measured minimum position to measured maximum position.
This parameter is guaranteed by design.
See Figure 1.
I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
CB—total capacitance of one bus line in picofarads.
EEPROM write begins after a stop condition occurs.
_____________________________________________________________________
5
DS1870
AC ELECTRICAL CHARACTERISTICS
Typical Operating Characteristics
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
850
800
740
720
700
680
660
VCC = 5.0V
600
VCC = 4.5V
550
0.35
0.30
0.25
0.20
0.15
500
0.10
620
450
0.05
400
4.5
4.7
4.9
5.1
5.3
5.5
0
-40
-20
0
20
40
60
80
100
4.5
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
HCOM VOLTAGE (V)
POTENTIOMETER 1 AND 2 OUTPUT VOLTAGE
vs. POSITON
POTENTIOMETER 1 DIFFERENTIAL
NONLINEARITY vs. WIPER POSITION
POTENTIOMETER 2 DIFFERENTIAL
NONLINEARITY vs. WIPER POSITION
3
HCOM = 5V
L1 AND L2
NOT CONNECTED
2
1
0
64
128
192
0.10
0.05
0
-0.05
-0.10
-0.15
0.25
0.20
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.20
-0.25
-0.25
256
0
64
128
192
0
256
64
128
256
192
WIPER POSITION (DEC)
WIPER POSITION (DEC)
POTENTIOMETER 1 INTEGRAL
NONLINEARITY vs. WIPER POSITION
POTENTIOMETER 2 INTEGRAL
NONLINEARITY vs. WIPER POSITION
POTENTIOMETER 1 AND 2
WIPER RESISTANCE vs. WIPER VOLTAGE
0.2
0.1
0
-0.1
-0.2
0.4
1000
0.3
0.2
0.1
0
-0.1
-0.2
900
800
700
600
500
400
300
-0.3
200
-0.4
-0.4
100
-0.5
-0.5
0
-0.3
64
128
192
WIPER POSITION (DEC)
256
0
64
128
192
DS1870 toc09
0.3
0.5
WIPER RESISTANCE (Ω)
0.4
DS1870 toc08
DS1870 toc07
0.5
0
DS1870 toc06
0.15
5.5
WIPER POSITION (DEC)
INTEGRAL NONLINEARITY (LSB)
0
0.20
DIFFERENTIAL NONLINEARITY (LSB)
4
DS1870 toc05
5
0.25
DIFFERENTIAL NONLINEARITY (LSB)
DS1870 toc04
6
WIPER VOLTAGE (V)
700
650
0.40
640
600
6
VCC = 5.5V
750
0.45
HCOM CURRENT (mA)
SUPPLY CURRENT (μA)
760
HCOM CURRENT vs. HCOM VOLTAGE
0.50
DS1870 toc02
DS1870 toc01
780
SUPPLY CURRENT (μA)
SUPPLY CURRENT vs. TEMPERATURE
900
DS1870 toc03
SUPPLY CURRENT vs. SUPPLY VOLTAGE
800
INTEGRAL NONLINEARITY (LSB)
DS1870
LDMOS RF Power-Amplifier Bias
Controller
256
WIPER POSITION (DEC)
_____________________________________________________________________
HCOM = 5.0V
0
1
2
3
WIPER VOLTAGE (V)
4
5
LDMOS RF Power-Amplifier Bias
Controller
700
600
500
400
300
200
HCOM = 5.0V
100
800
700
600
500
400
300
200
HCOM = 5V
WIPER VOLTAGE = 4V
100
1
2
3
5
4
150
100
RPOT2 + RS2
50
0
RPOT1 + RS1
-50
-100
-150
-200
0
0
200
DS1870 toc11
900
0
-40
-20
0
20
40
60
-40
100
80
-20
0
20
40
60
80
WIPER VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
POTENTIOMETER LOW TERMINAL VOLTAGE
vs. TEMPERATURE
VCC CONVERSION ERROR
vs. SUPPLY VOLTAGE
VD CONVERSION ERROR
vs. INPUT VOLTAGE
0.3
10
0.4
0.3
0.2
L1
0
-5
ERROR (% FS)
ERROR (% FS)
0.2
5
0.1
0
-0.1
L2
DEFAULT VCC
CALIBRATION
-0.3
HCOM = 5.0V
-15
-0.4
-20
0
20
40
60
80
3.0
100
DEFAULT VD
CALIBRATION
-0.4
-0.5
3.5
TEMPERATURE (°C)
4.0
4.5
0
5.5
5.0
0.5
0.3
2.0
2.5
0.5
DS1870 toc16
0.4
1.5
ID2 CONVERSION ERROR
vs. INPUT VOLTAGE
DS1870 toc15
0.5
1.0
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
ID1 CONVERSION ERROR
vs. INPUT VOLTAGE
0.4
0.3
0.2
ERROR (% FS)
0.2
ERROR (% FS)
-20
0
-0.1
-0.3
-0.5
-40
0.1
-0.2
-0.2
-10
DS1870 toc14
15
0.4
100
0.5
DS1870 toc13
0.5
DS1870 toc12
20
OUTPUT DRIFT (PPM/C)
DS1870 toc10
800
RESISTANCE CHANGE FROM 25°C (PPM/C)
900
WIPER RESISTANCE (Ω)
1000
DS1870 toc09
1000
POTENTIOMETER END-TO-END RESISTANCE
vs. TEMPERATURE
POTENTIOMETER 1 AND 2
WIPER RESISTANCE vs. TEMPERATURE
CHANGE FROM RESISTANCE AT 25°C (PPM/C)
POTENTIOMETER 1 AND 2
WIPER RESISTANCE vs. WIPER VOLTAGE
0.1
0
-0.1
-0.2
0.1
0
-0.1
-0.2
DEFAULT ID1
CALIBRATION
-0.3
DEFAULT ID2
CALIBRATION
-0.3
-0.4
-0.4
-0.5
-0.5
0
0.1
0.2
0.3
INPUT VOLTAGE (V)
0.4
0.5
0
0.1
0.2
0.3
0.4
0.5
INPUT VOLTAGE (V)
_____________________________________________________________________
7
DS1870
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
LDMOS RF Power-Amplifier Bias
Controller
DS1870
Pin Description
8
PIN
NAME
1
L1
Potentiometer 1 Low Terminal
FUNCTION
2
W1
Potentiometer 1 Wiper Terminal
3
W2
Potentiometer 2 Wiper Terminal
4
L2
Potentiometer 2 Low Terminal
5
ID1
Drain Current 1 Monitor Input
6
ID2
Drain Current 2 Monitor Input
7
VD
Drain Voltage Monitor Input
8
GND
9
FAULT
10
A0
11
A1
Ground
Fault Output. This open-collector output is active high when one of the enabled alarms is outside its
programmable limit value.
I2C Address Inputs. These inputs determine the slave address of the device. The slave address in
binary is 1010A2A1A0.
12
A2
13
SCL
Serial Clock Input. I2C clock input.
14
SDA
Serial Data Input/Output. Bidirectional I2C data pin.
15
HCOM
16
VCC
Potentiometer High Terminal. Common to potentiometers 1 and 2.
Power Input
_____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
VCC
ON-CHIP
TEMP SENSOR
VCC
SDA
SCL
I2C INTERFACE
CONTROL
GAIN
CALIBRATION
REGISTERS
OFFSET
CALIBRATION
REGISTERS
A0
A1
+
∑
+
13-BIT
ADC
VCC
MUX
32 BYTES
USER
MEMORY
VD
ID1
ADDRESS
GENERATION
ID2
A2
I2C DATA BUS
VD
ID1
VD
ID2
INDEX
LOAD
POT1
DRAIN
LUT
TABLE 4
(64 BYTES)
TEMP
INDEX
MEASURED
VALUES FOR
TEMP, VCC,
VD, ID0, ID1
VD2
VD1
INDEX
POT2
DRAIN
LUT
TABLE 5
(64 BYTES)
LIMIT FLAG
REGISTERS
FAULT
HI AND LO
LIMITS FOR
TEMP, VCC,
VD, ID1, ID2
LIMIT
COMPARATOR
FAULT
MASK
INDEX
LOAD
POT1
TEMP
LUT
TABLE 2
(72 BYTES)
POT2
TEMP
LUT
TABLE 3
(72 BYTES)
HCOM
DS1870
+
+
∑
POT2
RPOT
W2
L2
RS
+
GND
+
∑
RS
POT1
RPOT
W1
L1
_____________________________________________________________________
9
DS1870
Functional Diagram
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Table 1. Voltage-Monitor Factory Default
Calibration
Table 2. Voltage-Monitor Conversion
Examples
SIGNAL
+FS SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)
SIGNAL
LSB
WEIGHT (µV)
VCC
6.553V
FFF8
0V
0000
VCC
VD
2.5V
FFF8
0V
0000
VCC
ID1
0.5V
FFF8
0V
0000
ID2
0.5V
FFF8
0V
0000
Detailed Description
The DS1870 is a dual-channel LDMOS bias controller.
It is intended to replace traditional bias control solutions that are limited by a constant temperature-coefficient correction. This IC offers lookup table correction
that is programmable as a function of temperature as
well as drain supply voltage or current. The flexibility to
use a nonlinear bias correction improves efficiency significantly. This is a direct consequence of the ability to
lower the bias current, particularly in class AB operation, since the bias correction no longer requires a constant temperature coefficient. In addition, correcting the
bias as a function of drain supply voltage, or drain current in class AB, assists in distortion reduction and gain
management.
Two outputs (W1 and W2), each controlled by a dedicated two-dimensional lookup table as shown in the
functional diagram, drive two LDMOS gates. The two
degrees of freedom are temperature and either drain
supply voltage or drain current. The lookup tables are
programmed during power-amplifier assembly and
test. After calibration, the IC automatically recalls the
proper control setting for each output, based on temperature and drain characteristics.
A 13-bit ADC samples and digitizes the chip temperature, VCC, the drain supply voltage, and two drain currents. These digitized signals are stored in memory
ready to be accessed by the look up table controls.
The digitized values are also compared to alarm
thresholds generating high or low alarm flags. The
FAULT output can be configured to assert high based
any alarm’s assertion, or the alarms can be masked to
prevent unwanted fault assertions. The ADC readings
as well as the alarm flags and fault status are accessible through the I2C-compatible interface.
REGISTER
VALUE (hex)
INPUT
VOLTAGE (V)
100.00
8080
3.29
100.00
C0F8
4.94
VD
38.152
C000
1.875
VD
38.152
8080
1.255
ID1
7.6303
8000
0.2500
ID2
7.6303
1328
0.0374
The three least significant bits of the ADC result registers
are masked to zero. The round-robin time is specified by
tframe in the analog voltage-monitoring characteristics.
The default factory-calibrated values for the voltage
monitors are shown in Table 1.
To calculate the voltage measured from the register
value, first calculate the LSB weight of the 16-bit register that is equal to the full-scale voltage span divided
by 65,528. Next, convert the hexadecimal register
value to decimal and multiply it times the LSB weight.
Example: Using the factory default VCC trim, what voltage is measured if the VCC register value is C347h?
The LSB for VCC is equal to (6.553V - 0V) / 65,528 =
100.00µV. C347h is equal to 49,991 decimal, which
yields a supply voltage equal to 49,991 x 100.00µV =
4.999V. Table 2 shows more conversion examples
based on the factory trimmed ADC settings.
By using the internal gain and offset calibration registers, the +FS and -FS signal values shown in Table 1
can be modified to meet customer needs. For more
information on calibration, see the Voltage-Monitor
Calibration section.
Note: The method shown above for determining the
input voltage level only works when the offset register is
set to zero.
Voltage/Current Monitor Operation
The DS1870 monitors four voltages (VCC, VD, ID1, and
ID2) plus the temperature in a round-robin fashion using
its 13-bit ADC. The converted voltage values are stored
in memory addresses 62h–69h as 16-bit unsigned
numbers with the ADC result left justified in the register.
10
____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
Table 4. Temperature Conversion Values
MSB
(bin)
LSB
(bin)
01000000
00000000
+64
01000000
00001111
+64.059
Temperature-Monitor Operation
01011111
00000000
+95
The internal temperature monitor values are stored as
16-bit 2’s complement numbers at memory addresses
60h to 61h. The round-robin update time (tframe) for the
temperature register is the same as the voltage monitors. The factory default calibration values for the temperature monitor are shown in Table 3.
11110110
00000000
-10
11011000
00000000
-40
SIGNAL
+FS
SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)
Temp
+127.97°C
7FF8
-128.00°C
8000
To convert the 2’s complement register value to the
temperature it represents, first convert the 2-byte hexadecimal value to a decimal value as if it is an unsigned
value, then divide the result by 256. Finally, subtract
256 if the result of the division is greater than or equal
to +128. Table 4 shows example converted values.
The offset of the temperature sensor can be adjusted
using the internal calibration registers to account for
differences between the ambient temperature at the
location of the DS1870 and the temperature of the
device it is biasing. When offsets are applied to the
temperature measurement, the value converted will be
off by a fixed value from the DS1870’s ambient temperature. For more information, see the Temperature
Monitor Offset Calibration section.
TEMPERATURE
(°C)
Table 5. LUT Addresses for
Corresponding Temperature Values
LUT ADDRESS (hex)
CORRESPONDING
TEMPERATURE (°C)
80
≤ -40°C
81
-38°C
82
-36°C
…
…
C6
+100°C
C7
≥ +102°C
table 3) and the POT2 Drain LUT (memory table 5) control potentiometer 2. In the event that two table values
are summed and the result is greater than 255 or less
than 0, the potentiometer’s position is set to 255 or 0,
respectively.
Potentiometer Operation
Both of the DS1870’s potentiometers are 256 positions
with their high terminals connected to the high common
pin, HCOM. The low terminals of the potentiometers are
internally shunted to GND by resistors such that the
output voltage is 3V to 5V when HCOM is connected to
a 5V source. The internal shunt resistors and the potentiometer’s end-to-end resistance feature matching temperature coefficients that prevent the output voltage
from drifting over temperature.
External resistors can be placed from HCOM to LX and/or
from LX to GND to modify the typical output voltage.
Normal Operation
During normal operation, each potentiometer’s position
is automatically adjusted to the sum of its temperature
and drain LUT values after each round of conversions.
The potentiometer setting is applied after both the base
and offset LUT values are recalled from memory. The
sum of the currently indexed values in the POT1 Temp
LUT (memory table 2) and the POT1 Drain LUT (memory table 4) control potentiometer 1. The sum of the currently indexed values in the POT2 Temp LUT (memory
____________________________________________________________________
11
DS1870
Table 3. Internal Temperature-Monitor
Factory Default Calibration
99h
9Ah
DECREASING
TEMPERATURE
98h
97h
INCREASING
TEMPERATURE
96h
95h
99h
9Ah
DECREASING
DRAIN VOLTAGE
98h
97h
INCREASING
DRAIN VOLTAGE
96h
MEMORY LOCATION
MEMORY LOCATION
9Ah
MEMORY LOCATION
DS1870
LDMOS RF Power-Amplifier Bias
Controller
95h
2
4
6
8
10
TEMPERATURE (°C)
12
99h
DECREASING
DRAIN CURRENT
98h
97h
96h
INCREASING
DRAIN CURRENT
95h
AA00 AC00 AEOO B000 B200 B400
DRAIN VOLTAGE CONVERSION (HEX)
2A00 2C00 2E00 3000 3200 3400
DRAIN CURRENT CONVERSION (HEX)
Figure 1. LUT Hysteresis
The temperature tables (LUT 2 and LUT 3) are 72 bytes
each. This allows the biasing to be adjusted every 2°C
between -40°C and +102°C. Temperatures less than
-40°C or greater than +102°C use the -40°C or +102°C
values, respectively. The values in the temperature
tables are 8-bit unsigned values (0 to 255 decimal) that
allow the potentiometer to be set to any position as a
function of the temperature. The temperature LUTs
have 1°C hysteresis (Figure 1) to prevent the potentiometer’s position from chattering in the event the temperature remains near a LUT switching point. Table 5
shows how the DS1870 determines the temperature
tables index as a function of temperature.
The drain tables (LUT 4 and LUT5) are 64 bytes each,
and they can be indexed either by the drain voltage or
the drain current corresponding to the potentiometer.
The VD1 control bit determines if the voltage sensed on
VD or ID1 adjusts the POT1 Drain LUT, and the VD2
control bit determines if the voltage sensed on VD or
ID2 controls the POT2 Drain LUT. The VD1 and VD2
control bits are located in register 85h of memory table
1. The drain tables are programmed with an 8-bit
signed value (-128 to +127 decimal) that allow a relative offset from the temperature LUT values determined
by the amplifier’s drain characteristics.
Table 6. LUT Addresses for V D or I DX
Values
LUT ADDRESS
(hex)
VD VALUE
(hex)
80
≤ 8000
0000
81
8200
0200
82
8400
0400
12
IDX VALUE
(hex)
…
…
…
BE
FC00
7C00
BF
≥ FE00
≥ 7E00
The drain LUTs are indexed either by the upper half of
the VD range or the lower half of its corresponding IDX
range. Table 6 shows how the index is determined
based on the V D or I DX values. Hysteresis equal to
0100h is also implemented on the drain monitor
(Figure 1) to ensure that voltages close to a switching
point do not cause the potentiometer position to chatter
between two LUT values. The drain LUT index values are
specified in hexadecimal because the hexadecimal values are applicable regardless of the gain and offset calibration of the DS1870.
Manual Mode
During normal operation, the potentiometer position is
automatically modified once per conversion cycle
based on the ADC results. The DS1870 can either stop
the update function all together by using the B/O_en
bit, or the temperature and drain LUT indexes can be
manually controlled by using the Index_en bit. These
bits are located in the Man DAC register located in
memory table 1, byte AFh. More information about
these bits is in the Register Description section.
Voltage-Monitor Calibration
The DS1870 can scale each analog voltage’s gain and
offset to produce the desired digital result. Each of the
inputs (VCC, VD, ID1, ID2) has a unique register for the
gain and offset (in memory table 1) allowing them to be
individually calibrated. Additionally, the DS1870 offers
the ability to provide a temperature offset to allow the
temperature measurement to be compensated to
account for the difference in temperature between the
DS1870 and the device it is biasing.
To scale the gain and offset of the converter for a specific input, you must first know the relationship between
the analog input and the expected digital result. The
input that would produce a digital result of all zeros is
the null value (normally this input is GND). The input
that would produce a digital result of all ones (FFF8h) is
____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
/* Assume that the null input is 0.5V */
/* Assume that the requirement for the LSB is 50µV */
FS = 65528 * 50e-6;
/*3.2764V */
CNT1 = 0.5 / 50e-6;
/* 1000 */
CNT2 = 0.9 X FS / 50e-6;
/* 58981.5 */
/* So the null input is 0.5V and 90% of FS is 2.949V */
Set the input’s offset register to zero
gain_result = 0h;
/* Working register for gain
calculation */
CLAMP = FFF8h;
/* This is the max ADC value*/
For n = 15 down to 0
begin
gain_result = gain_result + 2n;
Write gain_result to the input’s
gain register;
Force the 90% FS input (2.949V);
Meas2= ADC result from DS1870;
If Meas2 ≥ CLAMP
Then
gain_result = gain_result - 2n;
Else
Force the null input (0.5V)
Meas1 = ADC result from DS1870
If [(Meas2-Meas1)>(CNT2-CNT1)]
Then
gain_result = gain_result - 2n;
end;
Write gain_result to the input’s gain
register;
The gain register is now set and the resolution of the
conversion matches the expected LSB. Customers
requiring non-zero null values (e.g., 0.5V) must next
calibrate the input’s offset. If the desired null value is
0V, leave the offset register programmed to 0000h and
skip this step.
To calibrate the offset register, program the gain register with the gain_result value determined above. Next,
force the null input voltage (0.5V for the example) and
read the digital result from the part (Meas1). The offset
value can be calculated using the following formula:
⎛ Meas1⎞
Offset = − 1 × ⎜
⎟
⎝ 4 ⎠
Temperature-Monitor Offset Calibration
The DS1870’s temperature sensor comes precalibrated
and requires no further adjustment by the customer for
proper operation. However, it is possible for customers
to characterize their system and add a fixed offset to
the DS1870’s temperature reading so it is reflective of
another location’s temperature. This is not required for
biasing because the temperature offset can be
accounted for by adjusting the data’s location in the
LUTs, but this feature is available for customers who
see application benefits.
To change the temperature sensor’s offset: write the
temperature offset register to 0000h, measure the
source reference temperature (Tref), and read the temperature from the DS1870 (TDS1870). Then, the following formula can be used to calculate the value for the
temperature offset register.
(
)
TempOffset = 64 × ( −275 + Tref − TDS1870 ) XORbitwise BB40h
Once the value is calculated, write it to the temperature
offset register.
Power-Up and Low-Voltage Operation
During power-up, the device is inactive until V CC
exceeds the digital power-on-reset voltage (VPOD). At
this voltage, the digital circuitry, which includes the I2Ccompatible interface, becomes functional. However,
EEPROM-backed registers/settings cannot be internally
read (recalled) until VCC exceeds the analog power-on
reset (VPOA), at which time the remainder or the device
becomes fully functional. Once VCC exceeds VPOA, the
Rdyb bit in byte 74h is timed to go from a 1 to a 0 and
indicates when ADC conversions begin. If VCC ever
dips below VPOA, the Rdyb bit reads as a 1 again.
Once a device exceeds V POA and the EEPROM is
recalled, the values remain active (recalled) until VCC
falls below VPOD.
____________________________________________________________________
13
DS1870
the full-scale (FS) value. The expected FS value is also
found by multiplying an all-ones digital answer by the
LSB weight.
Example: Since the FS digital reading is 65,528 (FFF8
hex) LSBs, if the LSB’s weight is 50µV, then the FS
value is 65,528 x 50µV = 3.2764V.
A binary search is used to calibrate the gain of the converter. This requires forcing two known voltages to the
input pin. It is preferred that one of the forced voltages
is the null input and the other is 90% of FS. Since the
LSB of the least significant bit in the digital reading register is known, the expected digital results can be calculated for both the null input and the 90% of full scale
value.
An explanation of the binary search used to scale the
gain is best served with the following example pseudocode:
DS1870
LDMOS RF Power-Amplifier Bias
Controller
As the device powers up, the V CC Lo alarm flag
defaults to a 1 until the first V CC ADC conversion
occurs and sets or clears the flag accordingly. The
FAULT output is active when VCC < VPOA.
Memory Description
The DS1870 memory map is divided into six sections
that include the lower memory (addresses 00h to 7Fh)
and five memory tables (Figure 2). The memory tables
are addressed by setting the table-select byte (7Fh) to
the desired table number and accessing the upper
memory locations (80h to FFh). The lower memory can
be addressed at any time regardless of the state of the
table-select byte. The lower memory and memory table
1 are used to configure the DS1870 and read the status
of the monitors. The lower memory also contains the 32
bytes of user memory. Memory tables 2 and 3 contain
the base potentiometer positions that are used for biasing based on the reading of the internal temperature
sensor. Memory tables 4 and 5 contain the relative offsets that are added to the base number as a function of
either the drain voltage or the individual drain current
monitors. See the Memory Map for a complete listing of
registers and the Register Description section for
details about each register.
Password Memory Protection
The DS1870 contains a 2-byte password that allows all
of its EE memory to be write protected until the proper
password is entered into the password entry (PWE)
word (address 78h). This allows factory calibration data
for the bias settings, alarm thresholds, and all the other
EEPROM information to be write protected. The password is set by writing to the Password register, which is
the first two bytes of memory table 1.
The factory default value for the password is FFFFh,
which is also the factory default value for PWE on
power-up. This means that parts are unlocked at
00h
power-up when they are first received by customers.
The password should be programmed to a value other
than FFFFh to ensure the calibration data is write protected. The PWE register always reads 0000h regardless of its programmed value.
EEPROM Write Disable
Memory locations 20h to 3Fh and Table 1 locations 80h
to A7h are SRAM-shadowed EEPROM. By default
(SEE = 0) these locations act as ordinary EEPROM. By
setting SEE = 1, these locations begin to function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time. Because changes made with SEE = 1 do not
affect the EEPROM, these changes are not retained
through power cycles. The power-up value is the last
value written with SEE = 0. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during
normal operation without wearing out the EEPROM. The
SEE bit resides in memory table 1, byte AFh.
Memory Map
The upper part of the memory map is organized into
8-byte or 4-word (2-byte) rows. The beginning address
of the row is shown in the left-most column of the map,
and is equal to the byte 0 or word 0 memory address.
The next byte (Byte 1) is located at the next highest
memory address, and the next word (Word 1) is two
memory addresses greater than the row’s beginning
address. The lower part of the memory map expands
the bytes or the words to show the names of the bits
within the byte/word, or their bit weights (2X) for registers that contain numerical information. Numerical registers that contain an “S” in the most significant bit are
showing sign extension for 2’s complement numbers.
Descriptions of each byte/bit follow in the Register
Description section.
MAIN MEMORY
80h
TABLE 1
80h
USER MEMORY;
CONFIGURATION
HI/LO ALARM
THRESHOLDS;
SEL
ADC RESULTS; AFh
C7h
CONFIGURATION
TABLE-SELECT
BYTE (7Fh)
7Fh
TABLE 2
80h
POT1
TEMP
LUT
SEL
TABLE 3
80h
POT2
TEMP
LUT
C7h
SEL
BFh
TABLE 4
POT1
DRAIN
LUT
SEL
Figure 2. Memory Organization
14
____________________________________________________________________
80h
BFh
TABLE 5
POT2
DRAIN
LUT
SEL
LDMOS RF Power-Amplifier Bias
Controller
WORD 1
WORD 2
WORD 3
ROW
NAME
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
00
User Row0
User EE
User EE
User EE
User EE
User EE
User EE
User EE
User EE
08
User Row1
User EE
User EE
User EE
User EE
User EE
User EE
User EE
User EE
10
User Row2
User EE
User EE
User EE
User EE
User EE
User EE
User EE
User EE
18
User Row3
User EE
User EE
User EE
User EE
User EE
User EE
User EE
User EE
20
Threshold0
28
Threshold1
ID2 Hi Alarm
Reserved
Reserved
Reserved
30
Threshold2
Temp Lo Alarm
VCC Lo Alarm
VD Lo Alarm
ID1 Lo Alarm
38
Threshold3
ID2 Lo Alarm
Reserved
Reserved
Reserved
Temp Hi Alarm
VCC Hi Alarm
VD Hi Alarm
ID1 Hi Alarm
40
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
48
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
50
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
58
60
A2D Value0
Temp Value
VCC Value
VD Value
ID1 Value
68
A2D Value1
ID2 Value
Reserved
Reserved
Reserved
70
Status
78
Table Select
Hi Alarm
Lo Alarm
PWE
Reserved
Reserved
I/O Status
A2D Status
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tbl Sel
BIT 3
BIT 2
BIT 1
BIT 0
EXPANDED BYTES
BYTE
(HEX)
BYTE
NAME
00-1F
User EE
20
22
Temp Hi Alrm
VCC Hi Alrm
BIT 7
BIT 6
BIT 5
BIT 4
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8
EE
EE
6
S
2
15
2
15
2
14
14
2
5
2
13
2
13
EE
2
4
2
12
2
12
2
3
EE
2
2
11
2
11
BIT7
2
2
10
2
10
2
1
2
9
2
9
BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
EE
2
0
2
8
2
8
2
-1
2
7
2
7
EE
2
-2
2
6
2
6
2
-3
2
5
2
5
EE
2
-4
2
4
2
4
2
-5
2
3
2
3
EE
2
-6
2
2
2
2
-7
2-8
2
1
20
2
1
20
2
24
VD Hi Alrm
2
2
26
ID1 Hi Alrm
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
28
ID2 Hi Alrm
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
30
Temp Lo Alrm
32
VCC Lo Alrm
2
2
S
26
2
15
15
2
14
2
14
2
2
25
2
13
2
13
24
2
12
2
12
2
2
23
2
11
2
11
2
2
2
2
2
2
2
2
2
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
20
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
20
34
VD Lo Alrm
2
36
ID1 Lo Alrm
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
ID2 Lo Alrm
15
14
13
12
11
10
2
9
2
8
7
6
5
4
3
2
1
20
2
1
2
0
-7
2-8
38
2
2
6
2
2
5
2
2
2
2
2
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
20
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
20
21
20
ID2 Value
215
214
213
212
211
210
29
28
27
26
25
24
2
-6
215
68
2
2
-5
VCC Value
2
2
-4
62
ID1 Value
2
2
-3
2
66
2
-2
2
15
2
2
-1
S
2
2
2
Temp Value
VD Value
2
2
3
60
64
2
4
23
22
2
70
Hi Alarm
Temp Hi
VCC Hi
VD Hi
ID1 Hi
ID2 Hi
Reserved
Reserved
Reserved
71
Lo Alarm
Temp Lo
VCC Lo
VD Lo
ID1 Lo
ID2 Lo
Reserved
Reserved
Reserved
74
I/O Status
Reserved
Reserved
Reserved
Reserved
Fault
Mint
Reserved
Rdyb
75
A2D Status
Temp Rdy
VCC Rdy
VD Rdy
ID1 Rdy
ID2 Rdy
Reserved
Reserved
Reserved
78
PWE
215
213
29
27
7F
Tbl Sel
214
27
212
26
211
210
25
28
24
26
23
25
24
22
23
22
21
21
20
20
____________________________________________________________________
15
DS1870
LOWER MEMORY
WORD 0
ROW
(HEX)
DS1870
LDMOS RF Power-Amplifier Bias
Controller
TABLE 1 ( CONFIGURATION )
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
80
Config
88
Scale0
Reserved
Vcc Scale
VD Scale
ID1 Scale
90
Scale1
ID2 Scale
Reserved
Reserved
Reserved
98
Offset0
Reserved
Vcc Offset
VD Offset
ID1 offset
A0
Offset1
ID2 Offset
Reserved
Reserved
Temp Offset
A8
LUT
Index
BYTE
(HEX)
BYTE
NAME
80
Password
85
LUT Sel
Reserved
86
Fault Ena
Temp Ena
8A
Vcc
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Password
T Index
O1 Index
O2 Index
BIT 7
BIT 6
BIT 5
POT1 base
BYTE 5
BYTE 6
BYTE 7
LUT Sel
Fault Ena
Reserved
POT1 off
POT2
base
POT2 off
Man Dac
BIT 3
BIT 2
BIT 1
BIT 0
EXPANDED BYTES
BIT 4
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10
215
214
213
212
Reserved
211
210
Reserved
28
Reserved
27
26
25
24
Reserved
Reserved
Reserved
BIT3
BIT2
BIT1
BIT0
23
22
21
20
VD2
VD1
ID1 Ena
ID2 Ena
Reserved
Reserved
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
8C
VD Scale
2
8E
ID1 Scale
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
90
ID2 Scale
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
9A
Vcc
Offset
2
2
2
2
2
VD Ena
29
215
2
Vcc Ena
BIT9 BIT8 BIT7 BIT6 BIT5 BIT4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
S
S
215
214
213
212
211
210
29
28
27
26
25
24
23
22
S
S
215
214
213
212
211
210
29
28
27
26
25
24
23
22
9E
VD Offset
ID1
S
S
15
2
2
14
13
12
11
10
9
8
7
6
5
4
3
22
A0
ID2
S
S
215
214
213
212
211
210
29
28
27
26
25
24
23
22
A6
Temp
Offset
S
28
27
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
A8
T Index
9C
A9
O1 Index
2
2
2
2
2
2
2
2
2
2
2
27
26
25
24
23
22
21
20
7
2
6
2
5
2
4
2
3
2
2
2
1
20
6
2
5
2
4
2
3
2
2
2
1
20
2
7
AA
O2 Index
2
2
AB
POT1
base
27
26
25
24
23
22
21
20
AC
POT1 off
S
26
25
24
23
22
21
20
AD
POT2
base
27
26
25
24
23
22
21
20
AE
POT2 off
S
26
25
24
23
22
21
20
AF
Man DAC
Reserved
Reserved
Reserved
Reserved
Reserved
SEE
B/O_en
index_en
16
____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
80
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
88
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
90
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
98
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
A0
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
A8
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
B0
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
B8
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
C0
LUT
POT1
POT1
POT1
POT1
POT1
POT1
POT1
POT1
C8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
F0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
F8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EXPANDED BYTES
BYTE
(HEX)
BYTE
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
80-C7
POT1
27
26
25
24
23
22
21
20
____________________________________________________________________
17
DS1870
TABLE 2 (POT1 TEMP LUT)
DS1870
LDMOS RF Power-Amplifier Bias
Controller
WORD 0
BYTE 0
BYTE 1
POT2
POT2
TABLE 3 ( POT2 TEMP LUT)
WORD 1
WORD 2
BYTE 2
BYTE 3
BYTE 4
BYTE 5
POT2
POT2
POT2
POT2
WORD 3
BYTE 6
BYTE 7
POT2
POT2
ROW
(HEX)
ROW
NAME
80
LUT
88
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
90
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
98
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
A0
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
A8
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
B0
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
B8
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
C0
LUT
POT2
POT2
POT2
POT2
POT2
POT2
POT2
POT2
C8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
F0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
F8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EXPANDED BYTES
BYTE
(HEX)
BYTE
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
80-C7
POT2
27
26
25
24
23
22
21
20
18
____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
TABLE 4 ( POT1 DRAIN LUT)
WORD 1
WORD 2
BYTE 2
BYTE 3
BYTE 4
BYTE 5
POT1 Off
POT1 Off
POT1 Off
POT1 Off
WORD 3
BYTE 6
BYTE 7
POT1 Off
POT1 Off
88
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
90
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
98
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
A0
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
A8
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
B0
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
B8
LUT
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
POT1 Off
ROW
NAME
80
EXPANDED BYTES
BYTE
(HEX)
BYTE
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
80-BF
POT1 Off
S
26
25
24
23
22
21
20
ROW
(HEX)
ROW
NAME
80
88
LUT
WORD 0
BYTE 0
BYTE 1
POT2 Off
POT2 Off
TABLE 5 (POT2 DRAIN LUT)
WORD 1
WORD 2
BYTE 2
BYTE 3
BYTE 4
BYTE 5
POT2 Off
POT2 Off
POT2 Off
POT2 Off
WORD 3
BYTE 6
BYTE 7
POT2 Off
POT2 Off
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
90
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
98
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
A0
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
A8
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
B0
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
B8
LUT
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
POT2 Off
BYTE
(HEX)
BYTE
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
80-BF
POT2 Off
S
26
25
24
23
22
21
20
EXPANDED BYTES
____________________________________________________________________
19
DS1870
LUT
WORD 0
BYTE 0
BYTE 1
POT1 Off
POT1 Off
ROW
(HEX)
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Register Description
The register descriptions are organized by the register’s row address starting with the lower memory, then proceeding through each lookup table in order. The format of the register description is shown below.
TABLE NAME
Name of Row
Name of Byte Description
of the byte’s function
a) bit X
bit X description
b) bit Y
bit Y description
The Access value following each byte’s name defines the read/write access for the register. Possible values are
read-only (R), write-only (W), and read-write (R/W). The Volatility parameter defines if the memory is volatile (V) or
nonvolatile (NV). Some registers correspond to values measured or detected by the DS1870. These parameters are
read-only and listed as NA since their values are indeterminate. Power-On values are the default states of the
volatile register, and the Factory Default values are the values the EEPROM memory is programmed to by the
factory before they are shipped from Dallas Semiconductor.
LOWER MEMORY
User Row
User EE
NV EEPROM user memory.
Threshold0
Temp Hi Alarm Temperature measurements above this 2’s complement threshold set its
corresponding alarm bit. Measurements below this threshold clear the alarm bit.
VCC Hi Alarm Voltage measurements of the VCC input above this unsigned threshold
set its corresponding alarm bit. Measurements below this threshold clear the alarm bit.
VD Hi Alarm Voltage measurements of the VD input above this unsigned threshold
set its corresponding alarm bit. Measurements below this threshold clear the alarm bit.
ID1 Hi Alarm Voltage measurements of the ID1 input above this unsigned threshold set
its corresponding alarm bit. Measurements below this threshold clear the alarm bit.
Threshold1
ID2 Hi Alarm Voltage measurements of the ID2 input above this unsigned threshold set
its corresponding alarm bit. Measurements below this threshold clear the alarm bit.
Threshold2
Temp Lo Alarm Temperature measurements below this 2’s complement threshold set its
corresponding alarm bit. Measurements above this threshold clear the alarm bit.
VCC Lo Alarm Voltage measurements of the VCC below above this unsigned threshold
set its corresponding alarm bit. Measurements above this threshold clear the alarm bit.
VD Lo Alarm Voltage measurements of the VD input below this unsigned threshold set
its corresponding alarm bit. Measurements above this threshold clear the alarm bit.
ID1 Lo Alarm Voltage measurements of the ID1 input below this unsigned threshold set
its corresponding alarm bit. Measurements above this threshold clear the alarm bit.
Threshold3
ID1 Lo Alarm Voltage measurements of the ID2 input below this unsigned threshold set
its corresponding alarm bit. Measurements above this threshold clear the alarm bit.
20
____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
Temp Value The signed 2’s complement direct-to-temperature measurement.
VCC Value
Unsigned VCC voltage measurement.
VD Value
Unsigned VD voltage measurement.
ID1 Value
Unsigned ID1 voltage measurement.
A2D Value1
ID2 Value
Unsigned ID2 voltage measurement.
Status
Hi Alarm
High-Alarm Status bits.
a) Temp Hi
High-alarm status for temperature measurement.
b) VCC Hi
High-alarm status for VCC measurement.
c) VD Hi
High-alarm status for VD measurement.
d) ID1 Hi
High-alarm status for ID1 measurement.
e) ID2 HI
High-alarm status for ID2 measurement.
Lo Alarm
Low-Alarm Status bits.
a) Temp Lo
Low-alarm status for temperature measurement.
b) VCC Lo
Low-alarm status for VCC measurement. This bit is set when the VCC supply is below
the POR trip-point value. It clears itself when a VCC measurement is completed and
the value is above the low threshold.
c) VD Lo
Low-alarm status for VD measurement.
d) ID1 Lo
Low-alarm status for ID1 measurement.
e) ID2 Lo
Low-alarm status for ID2 measurement.
I/O Status
Status of the FAULT pin.
a) Fault
Logical value of the FAULT pin. Fault is logic HIGH during power-on.
b) Mint
Maskable Interrupt. FAULT is an open-drain output. In case FAULT was pulled low
externally or was missing the external pullup resistor, this bit reflects the logical value
the DS1870 is trying to output on the FAULT pin. If any ‘Hi Alarm’ or ‘Lo Alarm’ is
active and its corresponding ‘Fault Ena’ bit is enabled, or ‘RDBY’ is a 1, then this bit is
active high. Otherwise, this bit is a zero.
c) Rdyb
Ready Bar. When the supply is above the power-on-analog (VPOA) trip point, this bit is
active low. Thus, this bit reads a logic 1 if the supply is below VPOA or too low to communicate over the I2C bus.
A2D Status
Status of completed conversions. At power-on, these bits are cleared and are
set as each conversion is completed. These bits can be cleared so that completion
of new conversions may be verified.
a) Temp Rdy
Temperature conversion is ready.
b) VCC Rdy
VCC conversion is ready.
c) VD Rdy
VD conversion is ready.
d) ID1 Rdy
ID1 conversion is ready.
e) ID2 Rdy
ID2 conversion is ready.
____________________________________________________________________
21
DS1870
A2D Value0
DS1870
LDMOS RF Power-Amplifier Bias
Controller
PWE
PWE
TBL Sel
Password Entry. Until the correct password is written to this location, the only
memory that can be written are addresses 78h to 7Fh. This includes the PWE and Table_Select
locations. All memory is readable regardless of the PWE value.
Table Select. The DS1870 contains four tables (1 to 5). Writing a (1 to 5) value
to this register grants access to the corresponding table.
TABLE 1 (CONFIGURATION)
Config
Password
The PWE value is compared against the value written to this location. All
EEPROM memory is write-protected when PWE does not match thisregister.
LUT Sel
Selects which inputs are used to control the lookup tables.
a) VD2
b) VD1
A one selects the VD input to control the drain LUT indexing for POT2 (Table 5). A zero
selects the ID2 input.
A one selects the VD input to control the drain LUT indexing for POT1 (Table 4). A zero
selects the ID1 input.
Configures the maskable interrupt for the FAULT pin.
Fault Ena
a) Temp Ena
b) VCC Ena
c) VD Ena
d) ID1 Ena
e) ID2 Ena
Temperature measurements, outside the threshold limits, are enabled to create an
active interrupt on the FAULT pin.
VCC measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
VD measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
ID1 measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
ID2 measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
Scale0
VCC Scale
VD Scale
ID1 Scale
Controls the scaling or gain of the VCC measurements. The VCC gain is
factory trimmed to 6.5535V FS.
Controls the scaling or gain of the VD measurements. The VD gain is
factory trimmed to 2.500V FS.
Controls the scaling or gain of the ID1 measurements. The ID1 gain is
factory trimmed to 0.5V FS.
Scale1
ID2 Scale
Offset0
VCC Offset
VD Offset
ID1 Offset
Offset1
ID2 Offset
Temp Offset
LUT Index
22
Controls the scaling or gain of the ID2 measurements. The ID2 gain is
factory trimmed to 0.5V FS.
Allows for offset control of VCC measurement
Allows for offset control of VD measurement.
Allows for offset control of ID1 measurement.
Allows for offset control of ID2 measurement.
Allows for offset control of temperature measurement.
____________________________________________________________________
LDMOS RF Power-Amplifier Bias
Controller
Holds the calculated index based on the temperature measurement. This
index is used to address LUTs 2 and 3.
O1 Index
Holds the calculated index based on the VD or ID1 measurement (dependant
on ‘LUT Sel’ byte). This index is used to address LUT 4.
O2 Index
Holds the calculated index based on the VD or ID2 measurement (dependant
on ‘LUT Sel’ byte). This index is used to address LUT 5.
The base value used for POT1 and recalled from Table 2 at the memory
address found in ‘T Index.’ This register is updated at the end of the temperature conversion.
POT1 is not updated with this value until the end of ID2 conversion to ensure that both the base
and the offset are known for POT1 and POT2 and they are updated simultaneously.
POT1 base
POT1 off
POT2 base
The offset value used for POT1 and recalled from Table 4 at the memory
address found in ‘O1 Index.’ Depending on the value written to ‘LUT Sel’ byte, this register is
updated at the end of the VD or ID1 conversion. POT1 is not updated with this value until the end
of ID2 conversion to ensure that both the base and the offset are known for POT1 and POT2 and
they are updated simultaneously.
The base value used for POT2 and recalled from Table 3 at the memory
address found in ‘T Index.’ This register is updated at the end of the temperature conversion.
POT2 is not updated with this value until the end of ID2 conversion to ensure that both the base
and the offset are known for POT1 and POT2 and they are updated simultaneously.
POT2 off
The Offset value used for POT2 and recalled from Table 5 at the memory
address found in ‘O2 Index.’ Depending on the value written to ‘LUT Sel’ byte, this register is
updated at the end of the VD or ID2 conversion. POT2 is not updated with this value until the end
of ID2 conversion to ensure that both the base and the offset are known for POT1 and POT2 and
they are updated simultaneously.
MAN Dac
Allows user to control either the LUT Index or the base and offset values
used to calculate the potentiometer positions.
a) SEE
Shadow EE bar. At power-on this bit is low, which enables EE writes to all shadowed
EE locations. If written to a one, this bit allows for trimming and/or configuring the part
without changing the NV-shadowed EE memory and not having to wait for the EE
cycle time to complete. Writing this bit to a zero does not cause a write from the SRAM
to copy into the EE. Shadow EE locations are addresses 20h to 3Fh and Table 180h
to A7h.
b) B/O_en
At power-on this bit is high, which enables auto control of the LUT. If this bit is written
to a zero, then the POT base and offset are writeable by the user and the LUT recalls
are disabled. This allows the user to interactively test their modules by writing the
base and/or offsets for the POTs. The POTs update with the new value at the end of
the write cycle. Thus, all four registers (‘POT1 Base,’ ‘POT1 OFF,’ ‘POT2 Base,’ and
‘POT2 OFF’) should be written in the same write cycle. The I2C stop condition is the
end of the write cycle.
c) Index_en
At power-on this bit is high, which enables auto control of the LUT. If this bit is cleared
to a zero, then the three index values (‘T index,’ ‘O1 Index,’ and ‘O2 Index’) are writeable by the user and the updates of calculated indexes are disabled. This allows the
user to interactively test their modules by controlling the indexing for the lookup
tables. All three index values should be written in the same write cycle. The recalled
values from the LUTs appear in the base and offset register after each corresponding
conversion (just like it would happen in auto mode). To ensure the recalled base and
offset values from the LUT are updated, the base and offset calculation will not update
the potentiometers until the completion of the next temperature and ID2 conversion.
Both pots update at the same time (just like it would happen in auto mode).
____________________________________________________________________
23
DS1870
T Index
DS1870
LDMOS RF Power-Amplifier Bias
Controller
TABLE 2 (TEMP LUT FOR POT 1)
Bytes 80h–C7h
POT1
The unsigned base value for POT1.
TABLE 3 (TEMP LUT FOR POT 2)
Bytes 80h–C7h
POT2
The unsigned base value for POT2.
TABLE 4 (DRAIN LUT FOR POT 1)
Bytes 80h–B8h
POT1 Off
The signed 2’s complement offset value for POT1.
TABLE 5 (DRAIN LUT FOR POT 2)
Bytes 80h–B8h
POT2 Off
The signed 2’s complement offset value for POT2.
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, and start and stop conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic high states. When the bus is idle, it often initiates a low-power mode for slave devices.
Start condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing diagram for applicable timing.
Stop condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for
applicable timing.
Repeated start condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a normal start condition. See the timing diagram for applicable timing.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
SDA
tBUF
tHD:STA
tLOW
tR
tSP
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tHD:DAT
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C Timing Diagram
24
____________________________________________________________________
tSU:STO
LDMOS RF Power-Amplifier Bias
Controller
1
0
1
0
MOST
SIGNIFICANT BIT
A2 A1 A0 R/W
A2, A1, AND A0
PIN VALUES
DETERMINES
READ OR WRITE
Figure 4. Slave Address Byte
setup and hold time requirements (Figure 3). Data is
shifted into the device during the rising edge of the SCL.
Bit read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (Figure 3) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on
SDA at the falling edge of the previous SCL pulse and
the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.
Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always
the 9th bit transmitted during a byte transfer. The
device receiving data (the master during a read or the
slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit.
Timing (Figure 3) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to terminated communication so the slave will return control
of SDA to the master.
Slave address byte: Each slave on the I 2 C bus
responds to a slave addressing byte sent immediately
I2C Communication
Writing a single byte to a slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and generates a stop condition.
The DS1870 writes 1 to 8 bytes (1 page or row) with a
single write transaction. This is internally controlled by
an address counter that allows data to be written to
consecutive addresses without transmitting a memory
address before each data byte is sent. The address
counter limits the write to one 8-byte page (one row of
the memory map). Attempts to write to additional pages
of memory without sending a stop condition between
pages results in the address counter wrapping around
to the beginning of the present row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respectively,
and the third data byte, 33h, would be written to
address 00h.
To prevent address wrapping from occurring, the master must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new start con-
____________________________________________________________________
25
DS1870
7-BIT SLAVE ADDRESS
following a start condition. The slave address byte
(Figure 4) contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit.
The DS1870’s slave address is 1010A2A1A0 (binary),
where A2, A1, and A0 are the values of the address
pins. The address pins allow the device to respond to
one of eight possible slave addresses. By writing the
correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master will read data from the slave. If an incorrect slave
address is written, the DS1870 assumes the master is
communicating with another I2C device and ignores the
communications until the next start condition is sent.
Memory address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte transmitted during a write operation following the slave
address byte.
DS1870
LDMOS RF Power-Amplifier Bias
Controller
dition, and write the slave address byte (R/W = 0) and
the first memory address of the next memory row
before continuing to write data.
Acknowledge polling: Any time an EEPROM page is
written, the DS1870 requires the EEPROM write time
(tW) after the stop condition to write the contents of the
page to EEPROM. During the EEPROM write time, the
DS1870 will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS1870, which allows the next page to be written as
soon as the DS1870 is ready to receive the data. The
alternative to acknowledge polling is to wait for maximum period of tW to elapse before attempting to write
again to the DS1870.
EEPROM write cycles: When EEPROM writes occur,
the DS1870 writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This
can result in a whole page being worn out over time by
writing a single byte repeatedly. Writing a page one
byte at a time wears the EEPROM out eight times faster
than writing the entire page at once. The DS1870’s
EEPROM write cycles are specified in the Nonvolatile
Memory Characteristics table. The specification shown
is at the worst-case temperature. It can handle approximately 10x that many writes at room temperature.
Writing to SRAM-shadowed EEPROM memory with SEE
= 1 does not count as an EEPROM write cycle when
evaluating the EEPROM’s estimated lifetime.
Reading a single byte from a slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation occurs
at the present value of the memory address counter. To
read a single byte from the slave, the master generates a
start condition, writes the slave address byte with
R/W = 1, reads the data byte with a NACK to indicate the
end of the transfer, and generates a stop condition.
Manipulating the address counter for reads: A dummy
write cycle can be used to force the address counter to
a particular value. To do this, the master generates a
start condition, writes the slave address byte (R/W = 0),
writes the memory address where it desires to read, generates a repeated start condition, writes the slave
address byte (R/W = 1), reads data with ACK or NACK
as applicable, and generates a stop condition.
COMMUNICATIONS KEY
S
START
A
ACK
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
P
STOP
N
NOT
ACK
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
Sr
REPEATED
START
X X
X X
X X
X X
NOTES:
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
2) THE FIRST BYTE SENT AFTER A START
CONDITION IS ALWAYS THE SLAVE ADDRESS,
FOLLOWED BY THE READ/WRITE BIT.
8 BITS ADDRESS OR DATA
WRITE A SINGLE BYTE
S
1
0
1
0 A2 A1 A 0 0
MEMORY ADDRESS
A
A
DATA
A
A
DATA
A
P
WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION
S
1
0
1
0 A2 A1 A0 0
MEMORY ADDRESS
A
DATA
A
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER
S
1
0
1
0 A2 A1 A0 0
A
MEMORY ADDRESS
A
Sr
1 0
1
0 A2 A1 A0 1
A
DATA
N
1 0
1
0 A2 A1 A0 1
A
DATA
A
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER
S
1
0
1
0 A2 A1 A0 0
DATA
A
MEMORY ADDRESS
A
A
DATA
Sr
A
DATA
Figure 5. I2C Communications Examples
26
____________________________________________________________________
N
P
P
P
LDMOS RF Power-Amplifier Bias
Controller
5V
4.7kΩ
3 PLACES
28V
VCC
FAULT
49.9kΩ
DS1870
SDA
FACTORY-CALIBRATED 13-BIT ADC
(CUSTOMER ADJUSTABLE FULLSCALE AND OFFSET VALUES)
SCL
4.22kΩ
A2
A1
VD
A0
N.C.
N.C.
ID2
N.C.
W1
RPOT1
RS1
L1
RS2
L2
W2
GND
HCOM
RPOT2
ID1
N.C.
MAX6165B
5V REFERENCE
RF
POWER
AMP
RFIN
RFOUT
NOTES:
1) IN THIS CONFIGURATION, THE VOLTAGE RANGE OF W1 AND W2 IS
3V-5V. THIS RANGE CAN BE EXTENDED USING EXTERNAL RESISTORS.
2) ONE MAX6156B CAN BE USED WITH MULTIPLE DS1870s.
See Figure 5 for a read example using the repeated
start condition to specify the starting memory location.
Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte it NACKs to indicate the end of the
transfer and generates a stop condition. This can be
done with or without modifying the address counter’s
location before the read cycle. The DS1870’s address
counter does not wrap on page boundaries during read
operations, but the counter will roll from its upper most
memory address FFh to 00h if the last memory location
is read during the read transaction.
Application Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors, and
mount the capacitors as close as possible to the VCC and
GND pins to minimize lead inductance.
____________________________________________________________________
27
DS1870
Typical Operating Circuit
Advanced Application
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS1870 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for SCL. Pullup resistor values should be chosen to
ensure that the rise and fall times listed in the AC electrical characteristics are within specification.
A circuit showing the implementaion of current sensing
using the DS1870 is shown under Advanced
Application with Current Sense.
Advanced Application with Current Sense
5V
4.7kΩ
3 PLACES
28V
49.9k
(1%)
VCC
FAULT
DS1870
4.22k
(1%)
SDA
SCL
VD
A2
A1
MAX4080
RS2
RPOT2
ID2
RPOT1
RS1
LOW
PASS
FILTER
N.C.
W1
L1
L2
MAX4080
W2
GND
LOW
PASS
FILTER
ID1
A0
HCOM
DS1870
LDMOS RF Power-Amplifier Bias
Controller
N.C.
MAX6165B
5V REFERENCE
RF
POWER
AMP
RFIN
RFOUT
NOTES:
1) IN THIS CONFIGURATION, THE VOLTAGE RANGE OF W1 AND W2 IS
3V-5V. THIS RANGE CAN BE EXTENDED USING EXTERNAL RESISTORS.
2) ONE MAX6156B CAN BE USED WITH MULTIPLE DS1870s.
Chip Information
TRANSISTOR COUNT: 52,353
SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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