DS4510U-5

Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile (NV) I/O pins. It is configured with an industry-standard I2C interface using either fast-mode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose I2Cto-parallel I/O expander with unlimited read/write capability. EEPROM registers allow the power-on value of the I/O pins to be adjusted to keep track of the system’s state through power cycles, and the CPU supervisor’s timer can be adjusted between 125ms and 1000ms to meet most any application need. Features ♦ Accurate 5%, 10%, or 15% 5V Power-Supply Monitoring ♦ Programmable Reset Timer Maintains Reset After VCC Returns to an In-Tolerance Condition ♦ Four Programmable, NV, Digital I/O Pins with Selectable Internal Pullup Resistor ♦ 64 Bytes of User EEPROM ♦ Reduces Need for Discrete Components ♦ I2C-Compatible Serial Interface ♦ 10-Pin µSOP Package Applications RAM-Based FPGA Bank Switching for Multiple Profiles Ordering Information Industrial Controls DS4510U-5 VCC TRIP POINT 5% Cellular Telephones DS4510U-10 10% -40°C to +85°C 10 µSOP PC Peripherals DS4510U-15 15% -40°C to +85°C 10 µSOP PDAs DS4510U-5/T&R 5% -40°C to +85°C 10 µSOP DS4510U-10/T&R 10% -40°C to +85°C 10 µSOP DS4510U-15/T&R 15% -40°C to +85°C 10 µSOP PART Pin Configuration PINPACKAGE -40°C to +85°C 10 µSOP TEMP RANGE Typical Operating Circuit 2.7V TO 5.5V TOP VIEW 4.7kΩ A0 1 SDA 2 SCL 3 VCC GND 10 RST DS4510 4 9 I/O0 8 I/O1 7 5 6 I/O2 I/O3 4.7kΩ FROM SYSTEM CONTROLLER VCC 4.7kΩ VCC RST RESET A0 I/O0 CONFIG0 SDA I/O1 CONFIG1 FPGA I/O2 CONFIG2 I/O3 CONFIG3 GND DS4510 SCL GND μSOP ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4510 General Description DS4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC, SDA, and SCL Pins Relative to Ground.....................................-0.5V to +6.0V Voltage Range on A0, I/O0, I/O1, I/O2, I/O3 Relative to Ground ..............-0.5V to VCC + 0.5V, not to exceed +6.0V. Operating Temperature Range ...........................-40°C to +85°C EEPROM Programming Temperature .....................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS Supply Voltage VCC (Notes 1) Input Logic 1 VIH (Note 2) Input Logic 0 VIL MIN TYP 2.7 0.7 x VCC -0.3 MAX UNITS 5.5 V VCC + 0.3 V +0.3 x VCC V DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER VCC Trip Point Standby Current Input Leakage SDA Low-Level Output Voltage SYMBOL VCCTP ISTBY DS4510U-5 CONDITIONS MIN 4.5 DS4510U-10 4.25 DS4510U-15 4.0 VCC = 5.0V (Note 3) IL VOL TYP 4.625 MAX 4.75 UNITS 4.375 4.49 V 4.125 4.24 50 -1.0 75 µA +1.0 µA 3mA sink current 0.4 6mA sink current 0.6 V I/OX Low-Level Output Voltage VOLIOX 4mA sink current 0.4 V RST Pin Low-Level Output VOLRST 10mA sink current (Note 4) 0.4 V 6.5 kΩ 10 pF I/OX Pullup Resistors I/O Capacitance 2 RP CI/O 4.0 (Note 5) _____________________________________________________________________ 5.0 CPU Supervisor with Nonvolatile Memory and Programmable I/O (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER RST Active Time SYMBOL tRST VCC Detect to RST tRPU VCC Fail to RST tRPD MIN TYP MAX TD1= 0, TD0 = 0 CONDITIONS 112 125 138 UNITS TD1= 0, TD0 = 1 225 250 275 TD1= 1, TD0 = 0 450 500 550 TD1= 1, TD0 = 1 900 1000 1100 TD1= 0, TD0 = 0 112 125 138 TD1= 0, TD0 = 1 225 250 275 TD1= 1, TD0 = 0 450 500 550 TD1= 1, TD0 = 1 900 1000 1100 4 10 µs TYP MAX 400 UNITS kHz ms ms AC ELECTRICAL CHARACTERISTICS (See Figure 5) (VCC = 2.7V to 5.5V, TA = -40°C to +85°C, timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions SYMBOL fSCL CONDITIONS (Note 6) MIN 0 tBUF 1.3 µs tHD:STA 0.6 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 Start Setup time tSU:STA 0.6 Hold Time (Repeated) Start Condition SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time µs 0.9 µs ns µs tR (Note 7) 20 + 0.1CB 300 ns tF (Note 7) 20 + 0.1CB 300 ns tSU:STO 0.6 SDA and SCL Capacitive Loading CB (Note 7) EEPROM Write Time tW (Note 7) µs 10 400 pF 20 ms _____________________________________________________________________ 3 DS4510 CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See Figure 1) NONVOLATILE MEMORY CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = 0°C to +70°C.) PARAMETER SYMBOL Writes Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: CONDITIONS MIN 50,000 +70°C (Note 5) TYP MAX UNITS All voltages referenced to ground. The DS4510 does not obstruct the SDA and SCL lines if VCC is switched off, as long as the voltages applied to these inputs do not violate their min and max input voltage levels. ISTBY specified with VCC equal to 5.0V, and control port-logic pins are driven to ground or VCC for the corresponding inactive state (SDA = SCL = VCC), does not include pullup resistor current. See Typical Operating Characteristics for the RST output voltage vs. supply voltage. This parameter is guaranteed by design. I2C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward compatible with I 2C standard-mode timing. CB—total capacitance of one bus line in picofarads. EEPROM write time applies to all the EEPROM memory and SEEPROM memory when SEE = 0. The EEPROM write time begins at the occurrence of a stop condition. Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) SDA = SCL = VCC I/O CONTROL BITS = 0 I/O PULLUPS DISABLED DS4510 toc02 60 40 30 20 10 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 40 30 20 SDA = VCC 10 0 0 3.0 50 SDA = SCL = VCC 30 4 SUPPLY CURRENT vs. SCL FREQUENCY 70 SUPPLY CURRENT (µA) 40 35 50 SUPPLY CURRENT (µA) 45 DS4510 toc01 VCC (10%) TRIP POINT SUPPLY CURRENT vs. TEMPERATURE 60 DS4510 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE 50 SUPPLY CURRENT (µA) DS4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O 5.0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) _____________________________________________________________________ 0 100 200 300 SCL FREQUENCY (kHz) 400 CPU Supervisor with Nonvolatile Memory and Programmable I/O RESET TRIP VOLTAGE (V) 4.7 4.6 4.5 4.4 4.3 4.2 4.1 5.0 4.5 5.6kΩ PULLUP RESISTOR ON RST SDA = SCL = VCC 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 0.5 0 4.0 DS4510 toc06 4.8 I/O PULLUP RESISTANCE vs. TEMPERATURE 5.25 I/O PULLUP RESISTANCE (kΩ) DS4510 toc04 4.9 VCC TRIP POINT (V) RST OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 6.0 5.5 DS4510 toc05 VCC TRIP POINT vs. TEMPERATURE 5.0 4.75 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 SUPPLY VOLTAGE (V) -20 0 20 40 60 80 TEMPERATURE (°C) Pin Description PIN NAME FUNCTION I2C Address Input. This input pin determines the chip address of the device. A0 = 0 sets the slave address to 1010000b, A0 = 1 sets the slave address to 1010001b. 1 A0 2 SDA Serial Data Input/Output. Bidirectional I2C data pin. 3 SCL Serial Clock Input. I2C clock input. 4 VCC Power Input 5 GND Ground 6 I/O3 Input/Output 3. I2C accessible bidirectional I/O pin. 7 I/O2 Input/Output 2. I2C accessible bidirectional I/O pin. 8 I/O1 Input/Output 1. I2C accessible bidirectional I/O pin. 9 I/O0 Input/Output 0. I2C accessible bidirectional I/O pin. 10 RST Active-Low Reset Output. Open-drain CPU supervisor reset output. _____________________________________________________________________ 5 DS4510 Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510 Functional Diagram VCC SDA SCL DS4510 2-WIRE INTERFACE RST A0 VCC VCC PROGRAMMABLE RESET TIMER INTERNAL VOLTAGE REFERENCE 4x GND EEPROM 64 BYTES USER MEMORY VCC 4 BIDIRECTIONAL NONVOLATILE I/O LATCHES RP PULLUP ENABLE (F0h) 4 NV I/O PINS I/OX CONTROL (F4h-F7h) I/O STATUS (F8h) Detailed Description The DS4510 contains a CPU supervisor, four programmable I/O pins, and a 64-byte EEPROM memory. All functions are configurable or controllable through an industry-standard I2C-compatible bus. DS4510 NV registers that are likely to require frequent modification are implemented using SRAM-shadowed EEPROM (SEEPROM) memory. This memory is configurable to act as volatile SRAM or NV EEPROM by adjusting the SEE bit in the Config register. Configuring the SEEPROM as SRAM eliminates the EEPROM write time and allows infinite write cycles to these registers. Configuring the registers as EEPROM allows the application to change the power-on values that are recalled during power-up. Programmable CPU Supervisor The timeout period is adjusted by writing the reset delay register (SEEPROM). The delay for each setting is shown in the CPU Supervisor AC Electrical Characteristics. If the SEE bit is set, changes are written to SRAM. On power-up the last value written to the EEPROM is recalled. The I2C bus is also used to activate the RST by setting the SWRST bit in the Config register. This bit automatically returns to zero after the timeout period. The Config register also contains the ready, trip point, and reset status bits. The ready bit 6 determines if the power-on reset level of the DS4510 is surpassed by VCC. The trip point bit determines if VCC is above VCCTP, and the reset status bit is set if RST is in its active state. Note: The RST pin is an open-drain output, therefore an external pullup resistor must be used to realize high logic levels. Programmable NV Digital I/O Pins Each programmable I/OX pin contains an input, opencollector output, and a selectable internal pullup resistor. The DS4510 stores changes to the I/O X pin in SEEPROM memory. Using the SEEPROM as SRAM is conducive to applications such as I/O expansion that generally require fast access times and frequent modification of the I/OX pin. Configuring the SEEPROM to behave as EEPROM allows the modification of the power-on state of the I/OX pin. During power-up the I/OX pins are high impedance until VCC exceeds 2.0V (typically), which is when the last value programmed is recalled from EEPROM. On power-down, the I/OX state is maintained until VCC drops below 1.9V (typically). The internal pullups for each I/OX pin are controlled by the pullup-enable register (F0h). Similarly, the individual I/OX control registers (F4h to F7h) adjust the pulldown _____________________________________________________________________ CPU Supervisor with Nonvolatile Memory and Programmable I/O tR User Memory Three types of memory are present in the DS4510 (EEPROM, SEEPROM, and SRAM). The main user memory is 64 bytes of EEPROM starting at address 00h. This memory is not SRAM shadowed, so all writes to these locations result in EEPROM write cycles regardless of the state of the SEE bit. Additional memory for storing application data includes 6 bytes of SRAM (FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer to the register memory map (Figure 3) for register addresses and memory types. Figure 4 shows the bit names for the memory-mapped I/O bytes and their factory default values. The higher-order bits of the I/O registers that are not used, such as the four most significant bits of the pullup-enable byte (address F0h), can be used as additional memory. It is the responsibility of the application to ensure that writes to these bytes do not adversely affect bits controlling special functions of the DS4510. VCCTP (MIN) DS4510 transistors. Read the I/O status register (F8h) to determine the logic levels present at the I/O pins. tF VCCTP (MAX) VCCTP VCCTP (MAX) VCCTP tRPU VCCTP (MIN) tRPD VOH VOL Figure 1. CPU Supervisor Power-Up and Power-Down Timing REGISTER ADDRESS (HEX) F8 MEMORY TYPE SRAM I/O STATUS REGISTER NAME Figure 2. How to Read the Memory Map 00 USER BYTE 08 USER BYTE 10 USER BYTE 18 USER BYTE 20 USER BYTE 28 USER BYTE 30 USER BYTE 38 USER BYTE 40 EE 02 User byte EE 0A USER BYTE EE 12 USER BYTE EE 1A USER BYTE EE 22 USER BYTE EE 2A USER BYTE EE 32 USER BYTE EE 3A USER BYTE 42 EE 03 USER BYTE EE 0B USER BYTE EE 13 USER BYTE EE 1B USER BYTE EE 23 USER BYTE EE 2B USER BYTE EE 33 USER BYTE EE 3B USER BYTE 43 E9 EA SEE F2 F1 RESET DELAY USER BYTE F9 SRAM FA CONFIG USER BYTE EB SEE F3 USER BYTE SRAM FB USER BYTE EE 01 USER BYTE EE 09 USER BYTE EE 11 USER BYTE EE 19 USER BYTE EE 21 USER BYTE EE 29 USER BYTE EE 31 USER BYTE EE 39 USER BYTE 41 EE 04 USER BYTE EE 0C USER BYTE EE 14 USER BYTE EE 1C USER BYTE EE 24 USER BYTE EE 2C USER BYTE EE 34 USER BYTE EE 3C USER BYTE 44 EE 05 USER BYTE EE 0D USER BYTE EE 15 USER BYTE EE 1D USER BYTE EE 25 USER BYTE EE 2D USER BYTE EE 35 USER BYTE EE 3D USER BYTE 45 EE 06 USER BYTE EE 0E USER BYTE EE 16 USER BYTE EE 1E USER BYTE EE 26 USER BYTE EE 2E USER BYTE EE 36 USER BYTE EE 3E USER BYTE 46 EE 07 USER BYTE EE 0F USER BYTE EE 17 USER BYTE EE 1F USER BYTE EE 27 USER BYTE EE 2F USER BYTE EE 37 USER BYTE EE 3F USER BYTE 47 EE EE EE EE EE EE EE EE RESERVED E8 F0 SEE PULLUP ENABLE F8 SRAM I/O STATUS EC SEE F4 SEE I/O3 CONTROL SRAM FC SRAM USER BYTE ED F5 SEE I/O2 CONTROL FD SRAM USER BYTE EE F6 SEE I/O1 CONTROL FE SRAM USER BYTE EF F7 SEE I/O0 CONTROL FF SRAM USER BYTE *ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3. Figure 3. Register Memory Map _____________________________________________________________________ 7 DS4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O REGISTER REGISTER LOCATION NAME (HEX) REGISTER BIT NAMES FACTORY OR POWER-ON DEFAULT (BIN) Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EE EE EE EE 00000000 User EEPROM 00-3F EE EE EE EE Reserved 40-EF n/a n/a n/a n/a n/a n/a n/a n/a n/a I/O2 pullup I/O1 pullup I/O0 pullup 00000000 Pullup Enable F0 SEE SEE SEE SEE I/O3 pullup RST Delay F1 SEE SEE SEE SEE SEE SEE TD1 TD0 00000011 User SEE F2 SEE SEE SEE SEE SEE SEE SEE SEE 00000000 User SEE F3 SEE SEE SEE SEE SEE SEE SEE SEE 00000000 I/O3 Control F4 SEE SEE SEE SEE SEE SEE SEE I/O3 00000001 I/O2 Control F5 SEE SEE SEE SEE SEE SEE SEE I/O2 00000001 I/O1 Control F6 SEE SEE SEE SEE SEE SEE SEE I/O1 00000001 I/O0 Control F7 SEE SEE SEE SEE SEE SEE SEE I/O0 00000001 I/O Status F8 0 0 0 0 I/O3 Status I/O2 Status I/O1 Status I/O0 Status n/a Config F9 ready trip point reset status SEE SWRST 0 0 0 XXX00000 User SRAM FA-FF SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM 00000000 Figure 4. Register Bit Names I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start, and stop conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning 8 SDA from low to high while SCL remains high generates a stop condition. See the I2C Timing Diagram for applicable timing. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the I2C Timing Diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL (see Figure 5) plus the setup and hold-time requirements. Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup _____________________________________________________________________ CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510 Table 1. Register Definitions REGISTER LOCATION (HEX) REGISTER NAME FUNCTION 00 to 3F User EEPROM 64 bytes of EEPROM memory. 40 to EF Reserved These memory locations are reserved for future products. F0 Pullup Enable The four least significant bits of this register each enable/disable one of the internal pullup resistors. Set the bit to enable the pullup, clear it to disable the pullup. F1 RST Delay The two LSBs of this register (TD1 and TD0) select the reset delay (tRST) as shown in the CPU Supervisor AC Timing Characteristics. F2 to F3 User SEEPROM SRAM Shadowed EEPROM user byte. F4 to F7 I/OX Control Clearing the LSB of the register enables the I/OX pulldown transistor; setting the bit disables the pulldown transistor. F8 I/O Status This register reflects the logic level of the I/OX pins. The upper four bits of this register always read zero. F9 Config This register contains 5 bits that read and control the behavior of the part as follows: FA to FF Bit Name Bit Function ready Reads zero when VCC is above the DS4510's power-on reset voltage. Trip Point Reads one when VCC below VCCTP. Reset Status Reads one when the RST pin is active. SEE When zero, writes to the SEEPROM registers behave like EEPROM. When one, writes to the SEEPROM registers behave like SRAM. SWRST Setting this bit activates the RST output. This bit automatically returns to zero during the RST active time. User SRAM 6 bytes of SRAM memory time (see Figure 5) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 5) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address and the R/W Bit: Each slave on the I2C bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte contains the slave address and the R/W bit. The slave address (see Figure 6) is the most significant 7 bits and the R/W bit is the least significant bit. The DS4510’s slave address is 101000A0 (binary), where A 0 is the value of the A 0 address pin. The _____________________________________________________________________ 9 DS4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O SDA tBUF tHD:STA tR tLOW tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START tHD:DAT REPEATED START tSU:STO NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN) Figure 5. I2C Timing Diagram address pin allows for the DS4510 to respond to one of two slave addresses (1010000X, or 1010001X). If the R/W bit is zero, the master writes data to the slave. If the R/W is one, the master reads data from the slave. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte (R/W = 0). 7-BIT SLAVE ADDRESS 1 0 MOST SIGNIFICANT BIT 1 0 0 0 A0 R/W A0 PIN VALUE DETERMINES READ OR WRITE Figure 6. DS4510’s Slave Address and the R/W Bit 10 I2C Communications Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address (R/W= 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. Writing a Multiple Bytes to a Slave: To write multiple bytes to a slave the master generates a start condition, writes the slave address (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. The DS4510 can write 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory table, see Figure 3). Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. Example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three “consecutive” addresses. The result would be addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. To prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. The master may then generate a new start con- ____________________________________________________________________ CPU Supervisor with Nonvolatile Memory and Programmable I/O Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave the master generates a start condition, writes the slave address with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 7 for a read example using the repeated start condition dummy write cycle. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter’s location before the read cycle. The DS4510 does not wrap on page boundaries during read operations, but the counter rolls from its upper-most memory address FFh to 00h if the last memory location is read during the read transaction. Example: The entire memory contents of the DS4510 can be read with a single transfer starting at address F0h that reads 80 bytes of data. Addresses F0h to FFh are read sequentially, the address counter rolls to 00h, and then addresses 00h to 3Fh can be read sequentially. This allows the entire memory contents to be read in a single operation without reading the undefined contents of the reserved area of the memory. Application Information Advantages of Using the SEE Bit to Disable EEPROM Writes The SEE bit allows EEPROM writes to be disabled for the SRAM-shadowed EEPROM bytes, allowing the SRAM of SEE registers to change without writing the EEPROM to the same value. This prevents write operations from changing the power-on value of the I/O pins, reduces the number of EEPROM write cycles, and speeds up I/O operations because the DS4510 does not require an internally timed EEPROM write cycle to complete the operation. Power-Supply Decoupling To achieve the best results when using the DS4510, decouple the power supply with a 0.01µF or a 0.1µF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins of the DS4510 to minimize lead inductance. SDA and SCL Pullup Resistors SDA is an open-collector output on the DS4510 that requires a pullup resistor to realize high logic levels. Because the DS4510 does not utilize clock cycle stretching, a master using either an open-collector output with a pullup resistor or a normal output driver can be utilized for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC Electrical Characteristics are within specification. ____________________________________________________________________ 11 DS4510 dition, write the slave address (R/W = 0), and the first memory address of the next page before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS4510 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the DS4510 does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeated addressing the DS4510, which allows the next page to be written as soon as the DS4510 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tW to elapse before attempting to write again to the DS4510. EEPROM Write Cycles: When EEPROM writes occur, the DS4510 writes the whole EEPROM memory page even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time wears the EEPROM out eight times faster than writing the entire page at once. The DS4510’s EEPROM memory is guaranteed to handle 50,000 write cycles at +70°C. Writing to SEEPROM memory with SEE = 1 does not count as an EEPROM write cycle when evaluating the EEPROM’s estimated lifetime. DS4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O COMMUNICATIONS KEY NOTES: S START A ACK WHITE BOXES INDICATED THE MASTER IS CONTROLLING SDA P STOP N NOT ACK SHADED BOXES INDICATED THE SLAVE IS CONTROLLING SDA Sr REPEATED START X X X X X X X X 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. 8-BITS ADDRESS OR DATA WRITE A SINGLE BYTE S 1 0 1 0 0 0 A0 0 MEMORY ADDRESS A A DATA A A DATA A P WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION S 1 0 1 0 0 0 A0 0 MEMORY ADDRESS A DATA A P READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER S 1 0 1 0 0 0 A0 0 MEMORY ADDRESS A A Sr 1 0 1 0 0 0 A0 1 A DATA N 1 0 0 0 A A DATA A P READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER S 1 0 1 0 0 0 A0 0 MEMORY ADDRESS A DATA A Sr DATA A 1 0 A 0 1 DATA N P Figure 7. I2C Communications Examples Chip Topology TRANSISTOR COUNT: 16559 SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Dallas Semiconductor Corporation. is a registered trademark of Maxim Integrated Products.