-
DS89C420
Ultra-High-Speed Microcontroller
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS89C420 offers the highest performance
available in 8051-compatible microcontrollers. It
features a redesigned processor core that executes
every 8051 instruction (depending on the instruction
type) up to 12 times faster than the original for the
same crystal speed. Typical applications see a speed
improvement of 10 times using the same code and
crystal. The DS89C420 offers a maximum crystal
speed of 33MHz, achieving execution rates up to 33
million instructions per second (MIPS).
§
80C52 Compatible
8051 Pin- and Instruction-Set Compatible
Four Bidirectional I/O Ports
Three 16-Bit Timer Counters
256 Bytes Scratchpad RAM
§
On-Chip Memory
16kB Flash Memory
In-System Programmable through Serial Port
1kB SRAM for MOVX
§
ROMSIZE Feature
Selects Internal Program Memory Size from
0 to 16k
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
§
High-Speed Architecture
1 Clock-Per-Machine Cycle
DC to 33MHz Operation
Single-Cycle Instruction in 30ns
Optional Variable Length MOVX to Access
Fast/Slow Peripherals
Dual Data Pointers with Auto
Increment/Decrement and Toggle Select
Supports Four Paged Modes
APPLICATIONS
Data Logging
Vending
Automotive Test Equipment
Motor Control
Magstripe Reader/Scanner
Consumer Electronics
Gaming Equipment
Appliances (Washers, Microwaves, etc.)
Telephones
HVAC
Building Security and Door Access Control
Building Energy Control and Management
Uninterruptible Power Supplies
Programmable Logic Controllers
Industrial Control and Automation
§ Power Management Mode
Programmable Clock Divider
Automatic Hardware and Software Exit
ORDERING INFORMATION
§
Two Full-Duplex Serial Ports
§
Programmable Watchdog Timer
§
13 Interrupt Sources (Six External)
§
Five Levels of Interrupt Priority
PART
TEMP RANGE
DS89C420-MNG
-40°C to +85°C
MAX
CLOCK
SPEED
(MHz)
25
DS89C420-QNG
-40°C to +85°C
25
44 PLCC
§
Power-Fail Reset
DS89C420-ENG
-40°C to +85°C
25
44 TQFP
§
Early Warning Power-Fail Interrupt
PINPACKAGE
40 PDIP
DS89C420-MCL
0°C to +70°C
33
40 PDIP
DS89C420-QCL
0°C to +70°C
33
44 PLCC
DS89C420-ECL
0°C to +70°C
33
44 TQFP
DS89C420-MNL
-40°C to +85°C
33
40 PDIP
DS89C420-QNL
-40°C to +85°C
33
44 PLCC
DS89C420-ENL
-40°C to +85°C
33
44 TQFP
Pin Configurations appear at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 102203
DS89C420 Ultra-High-Speed Microcontroller
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Voltage Range on VCC Relative to Ground
Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to (VCC + 0.5V)
-0.3V to +6.0V
-40°C to +85°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
Supply Voltage
VCC
CONDITIONS
(Notes 2, 13)
MIN
TYP
MAX
UNITS
4.5
5.0
5.5
V
Power-Fail Warning
VPFW
(Notes 2, 12)
4.2
4.375
4.6
V
Reset Trip Point
VRST
(Notes 2, 12, 13)
3.95
4.125
4.35
V
Supply Current Active Mode (Note 3)
ICC
33MHz
100
150
25MHz
Supply Current Idle Mode (Note 4)
IIDLE
33MHz
75
40
125
50
25MHz
40
50
Supply Current Stop Mode, Bandgap
Disabled
Supply Current Stop Mode, Bandgap
Enabled
Input Low Level
mA
mA
ISTOP
(Note 5)
40
mA
ISPBG
(Note 5)
40
mA
VIL
(Note 2)
-0.3
+0.8
V
Input High Level
VIH
(Note 2)
2.0
VCC +
0.3
V
Input High Level XTAL and RST
VIH2
(Note 2)
3.5
VCC +
0.3
V
Output Low Voltage; Port 1 and 3 at
IOL = 1.6mA
VOL1
(Note 2)
0.15
0.45
V
VOL2
(Note 2)
0.15
0.45
V
Output Low Voltage; Port 0 and 2,
ALE, PSEN at IOL = 3.2mA
Output High Voltage; Port 1, 2, and 3,
ALE, PSEN at IOH = -50mA
Output High Voltage; Port 1, 2, and 3
at IOH = -1.5mA
Output High Voltage; Port 0 and 2 in
Bus Mode at IOH = -8mA
Output High Voltage, RST at IOL = 0.4mA
VOH1
(Notes 2, 7)
2.4
V
VOH2
(Notes 2, 8)
2.4
V
VOH3
(Notes 2, 6)
2.4
V
VOH4
(Notes 2, 14)
2.4
V
Input Low Current; Port 1, 2, and 3 at
0.4V
IIL
-55
µA
Transition Current from 1 to 0; Port 1,
2, and 3 at 2V
ITL
(Note 9)
-650
µA
Input Leakage Current, Port 0 in I/O
Mode and EA
IL
(Note 11)
-10
+10
µA
Input Leakage Current, Port 0 in Bus
Mode
IL
(Note 10)
-300
+300
µA
RRST
(Note 11)
50
170
kW
RST Pulldown Resistance
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DS89C420 Ultra-High-Speed Microcontroller
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: Active current is measured with a 25MHz/33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins disconnected.
Note 4: Idle mode current measured with a 25MHz/33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins disconnected.
Note 5: Stop mode measured with XTAL and RST grounded, VCC = 5.5V. All other pins disconnected.
Note 6: When addressing external memory.
Note 7: RST = 5.5V. This condition mimics the operation of pins in I/O mode.
Note 8: During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition mode.
Note 9: Ports 1, 2, and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately 2V.
Note 10: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at
approximately 2V.
Note 11: RST = 5.5V. Port 0 floating during reset and when in the logic-high state during I/O mode.
Note 12: While the specifications for VPFW and VRST overlap, the design of the hardware makes it such that this is not possible. Within the ranges
given, there is a guaranteed separation between these two voltages.
Note 13: The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below that
point. This indicates that there is a range of voltages [VMIN to VRST (min)] where the processor’s operation is not guaranteed, but the
reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper
operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset.
Note 14: Guaranteed by design.
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DS89C420 Ultra-High-Speed Microcontroller
AC CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = -40°C to +85°C)* (Figure 1, Figure 2, and Figure 3)
(Note 1)
System Clock
PARAMETER
External Oscillator
(25MHz, 33MHz)
External Crystal
(25MHz, 33MHz)
SYMBOL
1 / tCLCL
1 CYCLE
2 CYCLE
4 CYCLE
PAGE MODE 1
PAGE MODE 1
PAGE MODE 1
PAGE MODE 2
NON-PAGE MODE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
0
25
0
25
0
25
0
25
0
25
0
33
0
33
0
33
0
33
0
33
1
25
1
25
1
25
1
25
1
25
1
33
1
33
1
33
1
33
1
33
0.5tCLCL - 2
+ tSTC3
tCLCL - 2 +
tSTC3
1.5tCLCL - 5 +
tSTC3
ns
tCLCL - 2
0.5tCLCL - 2
ns
0.5tCLCL - 2
tCLCL - 2
ns
tCLCL - 2 +
tSTC3
0.5tCLCL - 2 +
tSTC3
ns
2.5tCLCL - 8
0.5tCLCL - 8
0.5tCLCL - 8
ns
1.5tCLCL - 8
+ tSTC4
2.5tCLCL - 8
+ tSTC4
0.5tCLCL - 8 +
tSTC4
0.5tCLCL - 8 +
tSTC4
ns
1.5tCLCL - 8
+ tSTC4
2.5tCLCL - 8
+ tSTC4
0.5tCLCL - 8 +
tSTC4
0.5tCLCL - 8 +
tSTC4
ns
tLHLL
Port 0 Instruction Address
Valid to ALE Low
tAVLL
Port 2 Instruction Address
Valid to ALE Low
tAVLL2
Port 0 Data AddressValid to
ALE Low
tAVLL3
Program Address Hold
After ALE Low
tLLAX
0.5tCLCL - 8
1.5tCLCL - 8
Address Hold After ALE
Low MOVX Write
tLLAX2
0.5tCLCL - 8
+ tSTC4
Address Hold After ALE
Low MOVX Read
tLLAX3
0.5tCLCL - 8
+ tSTC4
ALE Low to Valid
Instruction In
tLLIV
ALE Low to PSEN Low
tLLPL
PSEN Pulse Width for
Program Fetch
tPLPH
0.5tCLCL - 4
0.5tCLCL - 4
1.5tCLCL - 5
2.5tCLCL 20
tCLCL - 5
MHz
1.5tCLCL - 5 +
tSTC3
ALE Pulse Width (Note 2)
2tCLCL - 4 +
tSTC3
UNITS
tCLCL - 5
2tCLCL - 5
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2.5tCLCL 20
ns
1.5tCLCL - 6
0.5tCLCL - 6
ns
tCLCL - 5
2tCLCL - 5
ns
DS89C420 Ultra-High-Speed Microcontroller
PARAMETER
SYMBOL
1 CYCLE
2 CYCLE
4 CYCLE
PAGE MODE 1
PAGE MODE 1
PAGE MODE 1
MIN
MAX
MIN
MAX
MIN
MAX
PAGE MODE 2
MIN
MAX
NON-PAGE MODE
MIN
UNITS
MAX
PSEN Low to Valid
Instruction In
tPLIV
Input Instruction Hold After
PSEN
tPXIX
Input Instruction Float After
PSEN
tPXIZ
tCLCL - 5
tCLCL - 5
ns
Port 0 Address to Valid
Instruction In
tAVIV0
1.5tCLCL 20
3tCLCL - 20
ns
Port 2 Address to Valid
Instruction In
tAVIV2
3tCLCL - 20
3.5tCLCL 20
ns
PSEN Low to Port 0
Address Float
tPLAZ
0
0
ns
RD Pulse Width (P3.7)
(Note 2)
tRLRH
tCLCL - 5 +
tSTC1
tCLCL - 5 +
tSTC1
2tCLCL - 5 +
tSTC1
2tCLCL - 5 +
tSTC1
2tCLCL - 5 +
tSTC1
ns
WR Pulse Width (P3.6)
(Note 2)
tWLWH
tCLCL - 5 +
tSTC1
tCLCL - 5 +
tSTC1
2tCLCL - 5 +
tSTC1
2tCLCL - 5 +
tSTC1
2tCLCL - 5 +
tSTC1
ns
RD (P3.7) Low to Valid
Data In (Note 2)
tRLDV
Data Hold After RD (P3.7)
tRHDX
Data Float After RD (P3.7)
tRHDZ
tCLCL - 5
tCLCL - 5
ns
MOVX ALE Low to Input
Data Valid (Note 2)
tLLDV
2.5tCLCL 20 + tSTC1
2.5tCLCL 20 + tSTC1
ns
Port 0 Address to Valid
Data In (Note 2)
tAVDV0
3tCLCL - 20
+ tSTC1
3tCLCL - 20
+ tSTC1
ns
tCLCL - 18
0
tCLCL - 18
0
0
1.5tCLCL 18
tCLCL - 18
tCLCL - 18
0
2.5tCLCL 18
tCLCL - 15 +
tSTC1
tCLCL - 15 +
tSTC1
0
2tCLCL - 18
0
2tCLCL - 15
+ tSTC1
0
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2tCLCL - 18
0
2tCLCL - 15
+ tSTC1
0
ns
ns
2tCLCL - 15
+ tSTC1
0
ns
ns
DS89C420 Ultra-High-Speed Microcontroller
PARAMETER
SYMBOL
1 CYCLE
2 CYCLE
4 CYCLE
PAGE MODE 1
PAGE MODE 1
PAGE MODE 1
MIN
Port 2 Address to Valid
Data In (Note 2)
tLLRL
(tLLWL)
Port 0 Address Valid to RD
or WR Low (Note 2)
(tAVWL0)
Port 2 Address Valid to RD
or WR Low (Note 2)
(tAVWL2)
MIN
0.5tCLCL - 8
+ tSTC2
0.5tCLCL + 1
+ tSTC2
MAX
MIN
1.5tCLCL 16 + tSTC1
tCLCL - 16 +
tSTC1
tAVDV2
ALE Low to RD or WR Low
(Note 2)
MAX
2tCLCL - 8 +
tSTC2
2tCLCL + 8 +
tSTC2
MAX
MIN
3.5tCLCL 16 + tSTC1
4tCLCL - 8 +
tSTC2
4tCLCL + 8 +
tSTC2
tAVRL0
tAVRL2
PAGE MODE 2
MAX
NON-PAGE MODE
MIN
3.0tCLCL 16 + tSTC1
0.5tCLCL - 8 +
tSTC2
0.5tCLCL + 4
+ tSTC2
0.5tCLCL - 8 +
tSTC2
UNITS
MAX
3.5tCLCL 20 + tSTC1
ns
0.5tCLCL + 4
+ tSTC2
ns
1.5tCLCL - 5 +
tSTC2
tCLCL - 5 +
tSTC2
ns
0 + tSTC5 - 5
0.5tCLCL - 5
+ tSTC5
1.5tCLCL - 5
+ tSTC5
tCLCL - 5 +
tSTC5
1.5tCLCL - 5 +
tSTC5
ns
Data Out Valid to WR
Transition (Note 1)
tQVWX
-5
-5
-5
-5
-5
ns
Data Hold After WR
(Note 1)
tWHQX
20
20
20
20
20
ns
RD or WR High to ALE High
(Note 1)
tRHLH
(tWHLH)
tSTC2 - 2
tSTC2 + 6
tSTC2 - 2
tSTC2 + 6
tSTC2 - 2
*Specifications to -40°C are guaranteed by design and not production tested.
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tSTC2 + 6
tSTC2 - 2
tSTC2 + 6
tSTC2 - 2
tSTC2 + 6
ns
DS89C420 Ultra-High-Speed Microcontroller
Note 1: The system clock frequency is dependent on the oscillator frequency and the setting of the clock-divide control bits (CD1 and CD0) and
the crystal multiplier control bits (4X/2X and CTM) in the PMR register. The term “1 / tCLCL” used in the variable timing table is calculated
through the use of the table given below.
4X/2X
CD1
CD0
1
0
X
X
X
0
0
0
1
1
0
0
1
0
1
NUMBER OF OSCILLATOR CYCLES PER
SYSTEM CLOCK (1 / tCLCL)
4 Oscillator Cycles
2 Oscillator Cycles
Reserved
1 Oscillator Cycle
1 / 1024 Oscillator Cycle
Note 2: External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in the clock control register. The terms
“tSTC1, tSTC2, tSTC3” used in the variable timing table are calculated through the use of the table given below.
MD2
MD1
MD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MOVX INSTRUCTION TIME
(MACHINE CYCLES)
2
3
4
5
9
10
11
12
tSTC1
(tCLCL)
0
2
6
10
14
18
22
26
tSTC2
(tCLCL)
0
1
1
1
5
5
5
5
tSTC3
(tCLCL)
0
0
0
0
4
4
4
4
tSTC4
(tCLCL)
0
0
0
0
1
1
1
1
tSTC5
(tCLCL)
0
1
1
1
1
1
1
1
Note 3: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
capacitance is dependent on the frequency of the selected crystal.
Figure 1. Non-Page Mode Timing
XTAL1
tCLCL
tLHLL
ALE
tAVLL2
tAVLL
PSEN
tLLPL
tPXIX
RD
WR
tPLPH
tRLRH
tPLIV
tLLIV
LSB
MOVX
tPXIZ
tAVIV0
tWHLH
tLLWL
tWLWH
LSB
MOVX
MSB
tAVWL0
tRHDX
tRLDV
tWHQX
tQVWX
tRHDZ
LSB
DATA
OPCODE
LSB
LSB
DATA
tAVWL2
tAVDV2
Port 2
tPLAZ
tLLDV
tAVDV0
tLLAX
Port 0
tLLAX2
tAVLL3
tLLAX3
MSB
MSB
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tAVIV2
MSB
MSB
DS89C420 Ultra-High-Speed Microcontroller
Figure 2. Page-Mode 1 Timing
XTAL1
tCLCL
tLHLL
ALE
tAVLL2
tPLPH
tLLAX
tLLAX3
tWHLH
tLLAX2
PSEN
tLLWL
RD
tRLRH
WR
tPXIX
tRHDX
tAVIV2
Port 0
MOVX
MOVX
tWLWH
tAVWL2
tPLIV
tRLDV
OPCODE
tWHQX
tQVWX
DATA
DATA
OPCODE
tAVDV2
Port 2
LSB
LSB
LSB
MSB
LSB
MSB
MSB
LSB
LSB
MSB
Figure 3. Page-Mode 2 Timing
XTAL1
tCLCL
tLHLL
ALE
tAVLL
tAVLL2
PSEN
tPLPH
tLLAX3
tLLPL
tPLIV
RD
tRLRH
tLLDV
WR
tAVIV0
tLLIV
tLLWL
LSB
LSB
LSB
OPCODE
MOVX
MOVX
MSB
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tWHQX
LSB
LSB
tRHDZ
tAVIV2
tAVDV2
tLLAX
MSB
tAVWL0
tRHDX
tPXIZ
Port 2
tWLWH
tRLDV
tAVDV0
LSB
tWHLH
tPLAZ
tAVWL2
tPXIX
Port 0
tLLAX2
tAVLL3
DATA
MSB
tQVWX
OPCODE
MSB
DATA
DS89C420 Ultra-High-Speed Microcontroller
EXTERNAL CLOCK CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = -40°C to +85°C.)*
PARAMETER
Clock High Time
SYMBOL
tCHCX
MIN
10
MAX
UNITS
ns
Clock Low Time
tCLCX
10
Clock Rise Time
tCLCH
5
ns
Clock Fall Time
tCHCL
5
ns
ns
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = -40°C to +85°C.)* (Figure 4)
PARAMETER
SYMBOL
Clock Cycle Time
tXLXL
Output Data Setup to
Clock Rising
tQVXH
Output Data Hold to Clock
Rising
tXHQX
Input Data Hold after
Clock Rising
tXHDX
Clock Rising Edge to Input
Data Valid
tXHDV
SM2 = 0
SM2 = 1
33MHz
MIN
MAX
360
120
SM2 = 0
200
SM2 = 1
40
SM2 = 0
50
SM2 = 1
20
SM2 = 0
SM2 = 1
0
0
CONDITIONS
SM2 = 0
200
SM2 = 1
40
VARIABLE
MIN
MAX
12tCLCL
4tCLCL
10tCLCL 100
3tCLCL 10
2tCLCL 10
tCLCL 100
0
0
10tCLCL 100
3tCLCL 50
UNITS
ns
ns
ns
ns
ns
Note: SM2 is the serial port 0, mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal
clocks in a serial-port clock cycle.
*Specifications to -40°C are guaranteed by design and not production tested.
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DS89C420 Ultra-High-Speed Microcontroller
Figure 4. Serial Port Timing
SERIAL PORT (SYNCHRONOUS MODE)
SM2 = 1 TDX CLOCK = XTAL FREQ/4
ALE
PSEN
tQVXH
WRITE TO SBUF
RXD DATA OUT
D0
tXHQX
DI
D2
D3
D4
D5
D6
D7
TRANSMIT
TXD CLOCK
tXLXL
TI
WRITE TO SCON
TO CLEAR RI
RXD DATA IN
D0
DI
D2
D3
D4
D5
D6
D7
RECEIVE
TXD CLOCK
tXHDV
tXHDX
R1
SERIAL PORT (SYNCHRONOUS MODE)
SM2 = 0 TDX CLOCK = XTAL FREQ/12
ALE
PSEN
1/(XTAL FREQ/12)
WRITE TO SBUF
D0
DI
D6
D7
TRANSMIT
RXD DATA OUT
TXD CLOCK
TI
WRITE
TO SCON
TXD CLOCK
TO CLEAR RI
D0
TXD CLOCK
R1
10 of 47
DI
D6
D7
RECEIVE
RXD DATA IN
DS89C420 Ultra-High-Speed Microcontroller
POWER CYCLE TIMING CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Crystal Startup Time
tCSU
(Note 2)
8
ms
Power-On Reset Delay
tPOR
(Note 3)
65,536
tCLCL
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Startup time for a crystal varies with load capacitance and manufacturer. Time shown is for a 11.0592MHz crystal manufactured by Fox
Electronics.
Note 3: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin
meets the VIH2 criteria. At 33MHz, this time is 1.99ms.
FLASH MEMORY PROGRAMMING CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = +21°C to +27°C.)
PARAMETER
Oscillator Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
6
MHz
100
ms
1 / tCLCL
4
Address Setup to PROG Low
tAVGL
48tCLCL
Address Hold After PROG
tGHAX
48tCLCL
Data Setup to PROG Low
tDVGL
48tCLCL
Data Hold After PROG
tGHDX
48tCLCL
PROG Pulse Width
tGLGH
85
Address to Data Valid
tAVQV
48tCLCL
Enable Low to Data Valid
tELQV
48tCLCL
Data Float After Enable
tEHQZ
0
PROG High to PROG Low
tGHGL
10
11 of 47
48tCLCL
ms
DS89C420 Ultra-High-Speed Microcontroller
PIN DESCRIPTION
DIP
PIN
PLCC
TQFP
40
12, 44
6, 38
VCC
20
1, 22, 23, 34
16, 17, 28,
39
GND
Logic Ground
External Reset. The RST input pin is bidirectional and contains a Schmitt
trigger to recognize external active-high reset inputs. The pin also employs
an internal pulldown resistor to allow for a combination of wire-ORed external
reset sources. An RC is not required for power-up, since the device provides
this function internally.
NAME
9
10
4
RST
19
21
15
XTAL1
18
20
14
XTAL2
29
32
26
PSEN
30
33
27
ALE/PROG
39
43
37
P0.0 (AD0)
38
42
36
P0.1 (AD1)
37
41
35
P0.2 (AD2)
36
40
34
P0.3 (AD3)
35
39
33
P0.4 (AD4)
34
38
32
P0.5 (AD5)
33
37
31
P0.6 (AD6)
32
36
30
P0.7 (AD7)
1–8
2–9
40–44, 1–
3
P1.0–P1.7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
FUNCTION
VCC - +5V
XTAL1, XTAL2. The crystal oscillator pins XTAL1 and XTAL2 provide support
for fundamental mode parallel resonant, AT cut crystals. XTAL1 also acts as
an input if there is an external clock source in place of a crystal. XTAL2
serves as the output of the crystal amplifier.
Program Store Enable. This signal is commonly connected to optional
external program memory as a chip enable. PSEN provides an active-low
pulse and is driven high when external program memory is not being
accessed. In 1-cycle page mode 1, PSEN remains low for consecutive page
hits.
Address Latch Enable. Functions as a clock to latch the external address LSB
from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. In
default mode, ALE has a pulse width of 1.5 XTAL1 cycles and a period of four
XTAL1 cycles. In page mode, the ALE pulse width is altered according to the
page mode selection. In traditional 8051 mode, ALE is high when using the
EMI reduction mode and during a reset condition. ALE can be enabled by
writing ALEON = 1 (PMR.2). Note that ALE operates independently of
ALEON during external memory accesses. As an alternate mode, this pin
(PROG) is used to execute the parallel program function.
Port 0 (AD0–7), I/O. Port 0 is an open-drain 8-bit, bidirectional I/O port. As an
alternate function, Port 0 can function as the multiplexed address/data bus to
access off-chip memory. During the time when ALE is high, the LSB of a
memory address is presented. When ALE falls to a logic 0, the port
transitions to a bidirectional data bus. This bus is used to read external
program memory and read/write external RAM or peripherals. When used as
a memory bus, the port provides weak pullups for logic 1 outputs. The reset
condition of Port 0 is three-state. Pullup resistors are required when using
Port 0 as an I/O port.
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an
alternate functional interface for timer 2 I/O, new external interrupts, and new
serial port 1. The reset condition of port 1 is with all bits at logic 1. In this
state, a weak pullup holds the port high. This condition also serves as an
input state, since any external circuit that writes to the port overcomes the
weak pullup. When software writes a 0 to any port pin, the DS89C420
activates a strong pulldown that remains on until either a 1 is written or a
reset occurs. Writing a 1 after the port has been at 0 causes a strong
transition driver to turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes the output high
(and input) state. The alternate functions of Port 1 are outlined below.
PORT
ALTERNATE
FUNCTION
P1.0
T2
External I/O for Timer/Counter 2
P1.1
T2EX
Timer 2 Capture/Reload Trigger
P1.2
RXD1
Serial Port 1 Receive
P1.3
TXD1
Serial Port 1 Transmit
P1.4
INT2
External Interrupt 2 (Positive Edge Detect)
P1.5
External Interrupt 3 (Negative Edge Detect)
INT3
P1.6
INT4
External Interrupt 4 (Positive Edge Detect)
P1.7
External Interrupt 5 (Negative Edge Detect)
INT5
12 of 47
DS89C420 Ultra-High-Speed Microcontroller
PIN DESCRIPTION (continued)
DIP
PIN
PLCC
PDIP
21
24
22
NAME
FUNCTION
18
P2.0 (A8)
25
19
P2.1 (A9)
23
26
20
P2.2 (A10)
24
27
21
P2.3 (A11)
25
28
22
P2.4 (A12)
26
29
23
P2.5 (A13)
27
30
24
P2.6 (A14)
28
31
25
P2.7 (A15)
Port 2 (A8–15), I/O. Port 2 is an 8-bit, bidirectional I/O port. The reset
condition of port 2 is logic high. In this state, a weak pullup holds the port high.
This condition also serves as an input mode, since any external circuit that
writes to the port overcomes the weak pullup. When software writes a 0 to any
port pin, the DS89C420 activates a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0
causes a strong transition driver to turn on, followed by a weaker sustaining
pullup. Once the momentary strong driver turns off, the port again becomes
both the output high and input state. As an alternate function, port 2 can
function as the MSB of the external address bus when reading external
program memory and read/write external RAM or peripherals. In page mode
1, port 2 provides both the MSB and LSB of the external address bus; in page
mode 2, it provides the MSB and data.
10–17
11, 13–19
5, 7–13
P3.0–P3.7
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
31
35
29
EA
Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an
alternate functional interface for external interrupts, serial port 0, timer 0 and 1
inputs, and RD and WR strobes. The reset condition of port 3 is with all bits at
logic 1. In this state, a weak pullup holds the port high. This condition also
serves as an input mode, since any external circuit that writes to the port
overcomes the weak pullup. When software writes a 0 to any port pin, the
DS89C420 activates a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0 causes a
strong transition driver to turn on, followed by a weaker sustaining pullup.
Once the momentary strong driver turns off, the port again becomes both the
output high and input state. The alternate modes of Port 3 are outlined below.
PORT
ALTERNATE
FUNCTION
P3.0
RXD0
Serial Port 0 Receive
P3.1
TXD0
Serial Port 0 Transmit
P3.2
External Interrupt 0
INT0
P3.3
External Interrupt 1
INT1
P3.4
T0
Timer 0 External Input
P3.5
T1
Timer 1 External Input
P3.6
External Data Memory Write Strobe
WR
P3.7
External Data Memory Read Strobe
RD
External Access. Allows selection of internal or external program memory.
Connect to ground to force the DS89C420 to use an external memoryprogram memory. The internal RAM is still accessible as determined by
register settings. Connect to VCC to use internal flash memory.
13 of 47
DS89C420 Ultra-High-Speed Microcontroller
Figure 5. Block Diagram
Control &
Sequencer
Interrupt
Internal
Registers
CPU
SFRs
PC
DPTR
AR Inc
DPTR1
AR
SP
Decoder
IR
Address Bus
Internal Control Bus
16K x 8
Flash
I/O Ports
ROM
Loader
ALE/PROG
PSEN
EA
Memory
Control
RST
Dallas Semiconductor
DS89C420
1Kx 8
RAM
Clock &
Reset
XTAL2
Watchdog Timer
&
Power Manager
Timer /
Counters
XTAL1
Serial I/O
P0 P1 P2 P3
DETAILED DESCRIPTION
The DS89C420 is pin compatible with all three packages of the standard 8051 and includes standard resources
such as three timer/counters, four 8-bit I/O ports, and a serial port. It features 16kB of in-system programmable
flash memory, which can be programmed in-system from an I/O port using a built-in program memory loader. It can
also be loaded externally using standard commercially available programmers.
Besides greater speed, the DS89C420 includes 1kB of data RAM, a second full-hardware serial port, seven
additional interrupts, two more levels of interrupt priority, programmable watchdog timer, brownout monitor, and
power-fail reset. The device also provides dual data pointers (DPTRs) to speed up block-data memory moves. This
feature is further enhanced with a new selectable automatic increment/decrement and toggle-select operation. The
speed of MOVX data memory access can be adjusted by adding stretch values up to 10 machine cycle times for
flexibility in selecting external memory and peripherals.
A power management mode (PMM) significantly consumes less power by slowing the CPU execution rate from 1
clock period per cycle to 1024 clock periods per cycle. A selectable switchback feature can automatically cancel
this mode to enable a normal speed response to interrupts.
The EMI reduction feature disables the ALE signal when the processor is not accessing external memory.
14 of 47
DS89C420 Ultra-High-Speed Microcontroller
COMPATIBILITY
The DS89C420 is a fully static CMOS 8051-compatible microcontroller similar to the DS87C520 in functional
features, but with much higher performance. In most cases the DS89C420 can drop into an existing socket for the
8xC51 family to improve the operation significantly. While remaining familiar to 8051 family users, it has many new
features. The DS89C420 runs the standard 8051 family instruction set and is pin compatible with DIP, PLCC, and
TQFP packages. In general, software written for existing 8051-based systems works without DS89C420
modification, with the exception of critical timing routines, since the DS89C420 performs its instructions much faster
than the original for any given crystal selection.
The DS89C420 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus
1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default to a 12 clock-percycle operation to keep their timing compatible with original 8051 family systems. However, timers are individually
programmable to run at the new 1 clock-per-cycle if desired. The DS89C420 provides several new hardware
features implemented by new SFRs.
PERFORMANCE OVERVIEW
The DS89C420 features a completely redesigned high-speed 8051-compatible core and allows operation at a
higher clock frequency, but the updated core does not have the dummy memory cycles that are present in a
standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS89C420, the same machine cycle takes 1 clock. Thus, the fastest instructions execute 12 times faster for the
same crystal frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that
this speed improvement reduces when using external memory access modes that require more than 1 clock per
cycle.
Improvement of individual programs depends on the actual instructions used. Speed-sensitive applications make
the most use of instructions that are 12 times faster. However, the sheer number of 12-to-1 improved op codes
makes dramatic speed improvements likely for any code. These architecture improvements produce instruction
cycle times as low as 30ns (33MIPs). The dual data pointer feature also allows the user to eliminate wasted
instructions when moving blocks of memory. The new page modes allow for increased efficiency in external
memory accesses.
INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status
functions is also identical. However, the timing of each instruction is different in both absolute and relative number
of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using information in the
“Instruction Set” table of the Ultra-High-Speed Flash Microcontroller User’s Guide. However, counter/timers default
to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with
software executing at higher speed. Timers optionally can run at lower numbers of clocks per increment to take
advantage of faster processor operation.
The relative time of some instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction
used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the
DS89C420, the MOVX instruction takes as little as two machine cycles or two oscillator cycles but the “MOV direct,
direct” uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts,
they now have different execution times. This is because the DS89C420 usually uses one machine cycle for each
instruction byte and requires one cycle for execution. The user concerned with precise program timing should
examine the timing of each instruction to become familiar with the changes.
SPECIAL FUNCTION REGISTERS (SFRS)
All peripherals and operations that are not explicit instructions in the DS89C420 are controlled through SFRs. The
most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC,
B, and PSW), data pointers (DPTRs), stack pointer, I/O ports, timer/counters, and serial ports. In many cases, an
SFR controls an individual function or reports the function’s status. The SFRs reside in register locations 80h–FFh
and are only accessible by direct addressing. SFRs whose addresses end in 0h or 8h are bit-addressable.
15 of 47
DS89C420 Ultra-High-Speed Microcontroller
All standard SFR locations from the 8051 are duplicated in the DS89C420 and several SFRs have been added for
the unique features of the DS89C420. Most of these features are controlled by bits in SFRs located in unused
locations in the 8051 SFR map. This allows for increased functionality while maintaining complete instruction set
compatibility. Table 1 summarizes the SFRs and their locations. Table 2 specifies the default reset condition for all
SFR bits.
DATA POINTERS
The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This
address can point to a MOVX RAM location (on-chip or off-chip), or a memory-mapped peripheral. Two pointers
are useful when moving data from one memory area to another, or when using a memory-mapped peripheral for
both source and destination addresses. The user selects the active pointer through a dedicated SFR bit (Sel =
DPS.0), or activates an automatic toggling feature for altering the pointer selection (TSL = DPS.5). An additional
feature, if selected, provides automatic incrementing or decrementing of the current DPTR.
STACK POINTER
The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can
place the stack anywhere in the scratchpad RAM by setting the stack pointer to the desired location, although the
lower bytes are normally used for working registers.
I/O PORTS
The DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be written or
read. The I/O port has a latch that contains the value written by software.
COUNTER/TIMERS
Three 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations that can
be read or written by software. The timers are controlled by other SFRs described in the “SFR Bit Description”
section of the Ultra-High-Speed Flash Microcontroller User’s Guide.
SERIAL PORTS
The DS89C420 provides two UARTs that are controlled and accessed by SFRs. Each UART has an address that
is used to read and write the UART. The same address is used for read and write operations, which are
distinguished by the instruction. Its own SFR control register controls each UART.
16 of 47
DS89C420 Ultra-High-Speed Microcontroller
Table 1. Special Function Registers
REGISTER
P0
SP
DPL
DPH
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P1
EXIF
CKMOD
ADDR
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
90h
91h
96h
BIT 7
P0.7
—
—
—
—
—
ID1
SMOD_0
TF1
GATE
—
—
—
—
WD1
P1.7/INT5
IE5
—
BIT 6
P0.6
—
—
—
—
—
ID0
SMOD0
TR1
C/T
—
—
—
—
WD0
P1.6/INT4
IE4
—
BIT 5
P0.5
—
—
—
—
—
TSL
OFDF
TF0
M1
—
—
—
—
T2M
P1.5/INT3
IE3
T2MH
BIT 4
P0.4
—
—
—
—
—
AID
OFDE
TR0
M0
—
—
—
—
T1M
P1.4/INT2
IE2
T1MH
BIT 3
P0.3
—
—
—
—
—
—
GF1
IE1
GATE
—
—
—
—
T0M
P1.3/TXD1
CKRY
T0MH
BIT 2
P0.2
—
—
—
—
—
—
GF0
IT1
C/T
—
—
—
—
MD2
P1.2/RXD1
RGMD
—
BIT 1
P0.1
—
—
—
—
—
—
STOP
IE0
M1
—
—
—
—
MD1
P1.1/T2EX
RGSL
—
BIT 0
P0.0
—
—
—
—
—
SEL
IDLE
IT0
M0
—
—
—
—
MD0
P1.0/T2
BGS
—
SCON0
98h
SM0/FE_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
SBUF0
ACON
P2
IE
SADDR0
SADDR1
P3
IP1
IP0
SADEN0
SADEN1
SCON1
SBUF1
ROMSIZE
PMR
STATUS
TA
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW
FCNTL
FDATA
WDCON
ACC
EIE
B
EIP1
EIP0
99h
9Dh
A0h
A8h
A9h
AAh
B0h
B1h
B8h
B9h
BAh
C0h
C1h
C2h
C4h
C5h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
D0h
D5h
D6h
D8h
E0h
E8h
F0h
F1h
F8h
—
PAGEE
P2.7
EA
—
—
P3.7/RD
—
—
—
—
SM0/FE_1
—
—
CD1
PIS2
—
TF2
—
—
—
—
—
CY
FBUSY
—
SMOD_1
—
—
—
—
—
—
PAGES1
P2.6
ES1
—
—
P3.6/WR
MPS1
LPS1
—
—
SM1_1
—
—
CD0
PIS1
—
EXF2
—
—
—
—
—
AC
FERR
—
POR
—
—
—
—
—
—
PAGES0
P2.5
ET2
—
—
P3.5/T1
MPT2
LPT2
—
—
SM2_1
—
—
SWB
PIS0
—
RCLK
—
—
—
—
—
F0
—
—
EPFI
—
—
—
—
—
—
—
P2.4
ES0
—
—
P3.4/T0
MPS0
LPS0
—
—
REN_1
—
—
CTM
—
—
TCLK
—
—
—
—
—
RS1
—
—
PFI
—
EWDI
—
MPWDI
LPWDI
—
—
P2.3
ET1
—
—
P3.3/INT1
MPT1
LPT1
—
—
TB8_1
—
PRAME
4X/2X
SPTA1
—
EXEN2
—
—
—
—
—
RS0
FC3
—
WDIF
—
EX5
—
MPX5
LPX5
—
—
P2.2
EX1
—
—
P3.2/INT0
MPX1
LPX1
—
—
RB8_1
—
RMS2
ALEON
SPRA1
—
TR2
—
—
—
—
—
OV
FC2
—
WTRF
—
EX4
—
MPX4
LPX4
—
—
P2.1
ET0
—
—
P3.1/TXD0
MPT0
LPT0
—
—
TI_1
—
RMS1
DME1
SPTA0
—
C/T2
T2OE
—
—
—
—
F1
FC1
—
EWT
—
EX3
—
MPX3
LPX3
—
—
P2.0
EX0
—
—
P3.0/RXD0
MPX0
LPX0
—
—
RI_1
—
RMS0
DME0
SPRA0
—
CP/RL2
DCEN
—
—
—
—
P
FC0
—
RWT
—
EX2
—
MPX2
LPX2
17 of 47
DS89C420 Ultra-High-Speed Microcontroller
Table 2. SFR Reset Value
REGISTER
P0
SP
DPL
DPH
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P1
EXIF
CKMOD
SCON0
SBUF0
ACON
P2
IE
SADDR0
SADDR1
P3
IP1
IP0
SADEN0
SADEN1
SCON1
SBUF1
ROMSIZE
PMR
STATUS
TA
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW
FCNTL
FDATA
WDCON
ACC
EIE
B
EIP1
EIP0
ADDR
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
90h
91h
96h
98h
99h
9Dh
A0h
A8h
A9h
AAh
B0h
B1h
B8h
B9h
BAh
C0h
C1h
C2h
C4h
C5h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
D0h
D5h
D6h
D8h
E0h
E8h
F0h
F1h
F8h
BIT 7
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
1
BIT 6
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
Special
0
1
0
1
1
BIT 5
1
0
0
0
0
0
0
Special
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
1
BIT 4
1
0
0
0
0
0
0
Special
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
Special
0
0
0
0
0
BIT 3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Special
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 2
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
Special
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
Special
0
0
0
0
0
BIT 1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Special
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Special
0
0
0
0
0
BIT 0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MEMORY ORGANIZATION
There are three distinct memory areas in the DS89C420: scratchpad registers, program memory, and data
memory. All registers are located on-chip but the program and data memory spaces can either be on-chip, off-chip,
or both. There are 16kB of on-chip program memory implemented in flash memory and 1kB of on-chip data
memory space that can be configured as program space using the PRAME bit in the ROMSIZE feature. The
DS89C420 uses a memory-addressing scheme that separates program memory from data memory. The program
and data segments can be overlapped since they are accessed in different ways. If the maximum address of onchip program or data memory is exceeded, the DS89C420 performs an external memory access using the
expanded memory bus. The PSEN signal goes active-low to serve as a chip enable or output enable when
performing a code fetch from external program memory. MOVX instructions activate the RD or WR signal for
18 of 47
DS89C420 Ultra-High-Speed Microcontroller
external MOVX data memory access. The lower 128 bytes of on-chip flash memory store reset and interrupt
vectors. The program memory ROMSIZE feature allows software to dynamically configure the maximum address of
on-chip program memory. This allows the DS89C420 to act as a bootloader for an external flash or NV SRAM. It
also enables the use of the overlapping external program spaces. 256 bytes of on-chip RAM serve as a register
area and program stack, which are separated from the data memory.
REGISTER SPACE
Registers are located in the 256 bytes of on-chip RAM, which can be divided into two subareas of 128 bytes each
as illustrated in Figure 6. Separate classes of instructions are used to access the registers and the program/data
memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory map. Indirect addressing
accesses the upper 128 bytes of scratchpad RAM, and direct addressing accesses the SFR area. Direct or indirect
addressing can access the lower 128 bytes.
There are four banks of eight individual working registers in the lower 128 bytes of scratchpad RAM. The working
registers are general-purpose RAM locations that can be addressed within the selected bank by any instructions
that use R0–R7. The register bank selection is controlled through the program status register in the SFR area. The
contents of the working registers can be used for indirectly addressing the upper 128 bytes of scratchpad RAM.
To support the Boolean operations, there are individually addressable bits in both the RAM and SFR areas. In the
scratchpad RAM area, registers 20h–2Fh are bit-addressable by software using Boolean operation instructions.
Another use of the scratchpad RAM area is for the stack. The stack pointer in the SFRs is used to select storage
locations for program variables and for return addresses of control operations.
MEMORY CONFIGURATION
As illustrated in Figure 6, the DS89C420 incorporates two 8kB flash memories for on-chip program memory and
1kB of SRAM for on-chip data memory or a particular range (400–7FF) of “alternate” program memory space. The
DS89C420 uses an address scheme that separates program memory from data memory, such that the 16-bit
address bus can address each memory area up to 64kB.
PROGRAM MEMORY ACCESS
On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding the
maximum address of on-chip program memory causes the device to access off-chip memory. However, the
maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the
DS89C420 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory
is used. The maximum memory size is dynamically variable. Thus, a portion of memory can be removed from the
memory map to access off-chip memory, then be restored to access on-chip memory. In fact, all of the on-chip
memory can be removed from the memory map allowing the full 64kB memory space to be addressed from off-chip
memory. Program memory addresses that are larger than the selected maximum are automatically fetched from
outside the part through ports 0 and 2 (Figure 6).
The ROMSIZE register is used to select the maximum on-chip decoded address for program memory. Bits RMS2,
RMS1, RMS0 have the following effect:
RMS2
RMS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
RMS0
ADDRESS
0
1
0
1
0
1
0
1
MAXIMUM ON-CHIP
PROGRAM MEMORY
0k
1k/03FFh
2k/07FFh
4k/0FFFh
8k/1FFFh
16k (default)/3FFFh
Invalid–Reserved
Invalid–Reserved
19 of 47
DS89C420 Ultra-High-Speed Microcontroller
Figure 6. Memory Map
FFFF
FFFF
INTERNAL
MEMORY
03FF
INTERNAL
REGISTERS
128 Bytes SFR
0000
128 Bytes
Indirect
Addressing
2000
80
7F
External
Data
Memory
4000
8K x 8
Flash
Memory
(Program)
1FFF
8K x 8
Flash
Memory
(Program)
Bit Addressable
Bank 3
Bank 2
Bank 1
00
External
Program
Memory
Data OR
prog mem
addr from
400 - 7FF
3FFF
FF
2F
20
1F
1K x 8
SRAM
Bank 0
0000
03FF
0000
0000
The reset default condition is a maximum on-chip program-memory address of 16kB. When accessing external
program memory, the first 16kB would be inaccessible. To select a smaller effective program memory size,
software must alter bits RMS2–RMS0. Altering these bits requires a timed access procedure as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For example,
assume that a DS89C420 is executing instructions from internal program memory near the 12kB boundary
(~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software
reconfigures the ROMSIZE register to 4kB (0000h–0FFFh) in the current state, the device immediately jumps to
external program execution because program code from 4kB to 16kB (1000h–3FFFh) is no longer located on-chip.
This could result in code misalignment and execution of an invalid instruction. The recommended method is to
modify the ROMSIZE register from a location in memory that is internal (or external) both before and after the
operation. In the above example, the instruction that modifies the ROMSIZE register should be located below the
20 of 47
DS89C420 Ultra-High-Speed Microcontroller
4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification.
The same precaution should be applied if the internal program memory size is modified while executing from
external program memory.
For non-page mode operations, off-chip memory is accessed using the multiplexed address/data bus on P0 and
the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the
standard 8051 method of expanding on-chip memory. Off-chip program memory access also occurs if the EA pin is
logic 0. EA overrides all bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable
when port 0 and port 2 fetch from external program memory.
The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX
instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the
address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointers
to move data over the entire 64kB external data memory space. Software selects the data pointer to be used by
writing to the SEL bit (DPS.0).
The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external
memory interface into page mode operation.
Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that
of internal operations. This is due to the CPU being stalled for three out of four clocks waiting for the data fetch,
which takes four clocks. Page Mode 1 is the only external addressing mode where the CPU does not require stalls
for external memory access, but page misses result in reduced external access performance.
ON-CHIP PROGRAM MEMORY
The processor can fetch the full on-chip program memory range automatically. The reset routines and all interrupt
vectors are located in the lower 128 bytes of the on-chip program memory area.
On-chip program memory is logically divided into two 8kB flash memory banks and is designed to be programmed
with the standard 5V VCC supply by using a built-in program memory loader. It can also be programmed in standard
flash or EPROM programmers. The DS89C420 incorporates a memory management unit (MMU) and other
hardware to support any of the two programming methods. The MMU controls program and data memory access,
and provides sequencing and timing controls for programming the on-chip program memory. There is also a
separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and
other flash options.
SECURITY FEATURES
The DS89C420 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing
the data in encrypted form. The encryption array is implemented in a security flash memory block that has the
same electrical and timing characteristics as the on-chip program memory. Once the encryption array is
programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte of data is XNORed with a
byte in the encryption array during verification.
A three-level lock restricts viewing of the internal program and data memory contents. By programming the three
lock bits, the user can select a level of security as specified in Table 3. Once a security level is selected and
programmed, the setting of the lock bits remains. Only a mass erase can erase these bits to allow reprogramming
the security level to a less restricted protection.
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DS89C420 Ultra-High-Speed Microcontroller
Table 3. Flash Memory Lock Bits
LEVEL
1
LB1
1
LB2
1
LB3
1
2
0
1
1
3
X
0
1
4
X
X
0
PROTECTION
No program lock. Encrypted verify if encryption array is programmed.
Prevent MOVC in external memory from reading program code in internal
memory. EA is sampled and latched on reset. Allow no further parallel or
program memory loader programming.
Level 2 plus no verify operation. Also prevent MOVX in external memory
from reading internal SRAM.
Level 3 plus no external execution.
The DS89C420 provides user-selectable options that must be set before beginning software execution. The option
control register uses flash bits rather than SFRs, and is individually erasable and programmable as a byte-wide
register. Bit 3 of this register is defined as the watchdog POR default. Setting this bit to 1 disables the watchdogreset function on power-up, and clearing this bit to 0 enables the watchdog-reset function automatically. Other bits
of this register are undefined and are at logic 1 when read. The value of this register can be read at address FCh in
parallel programming mode or when executing a verify-option control-register instruction in ROM loader mode.
The signature bytes can be read in ROM loader mode or in parallel programming mode. Reading data from
addresses 30h, 31h, and 60h provides signature information about manufacturer, part, and extension as follows:
ADDRESS VALUE
FUNCTION
30h DAh
31h 42h
60h 01h
Manufacturer ID
DS89C420 Device ID
Device Extension
ROM LOADER
The full 16kB of on-chip flash program-memory space, security flash block, and external SRAM can be
programmed in-system from an external source through serial port 0 under the control of a built-in ROM loader.
The ROM loader also has an auto-baud feature that determines which baud rate frequencies are being used for
communication and sets up the baud rate generator for communication at that frequency.
When the DS89C420 is powered up and has entered its user operating mode, the ROM loader mode can be
invoked at any time by forcing RST = 1, EA = 0, and PSEN = 0. It remains in effect until power-down or when the
condition (RST = 1 and PSEN = EA = 0) is removed. Entering the ROM loader mode forces the processor to start
fetching from the 2kB internal ROM for program memory initialization and other loader functions.
The read/write accessibility is determined by the state of the lock bits, which can be verified directly by the ROM
loader. In the ROM loader mode, a mass-erase operation also erases the memory bank select and sets it to the
default state. Otherwise, the memory bank select cannot be altered in the ROM loader mode.
Flash programming is executed by a series of internal flash commands that are derived (by the built-in ROM
loader) from data transmitted over the serial interface from a host PC. PC-based software tools that configure and
load the microcontrollers are available at www.maxim-ic.com/micros/ftpinfo.html.
Full details of the ROM loader software and its implementation are given in the Ultra-High-Speed Flash
Microcontroller User’s Guide.
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DS89C420 Ultra-High-Speed Microcontroller
Figure 7. Interfacing the Bootloader to a PC
PARALLEL PROGRAMMING
The DS89C420 allows parallel programming of its internal flash memory compatible with standard flash or EPROM
programmers. In parallel programming mode, a mass-erase command is used to erase all memory locations in the
16kB program memory, the security block, and the memory bank select. Erasing the memory bank select sets it to
the default state; the memory bank select cannot be altered otherwise. If lock bit LB2 has not been programmed,
the program code can be read back for verification. The state of the lock bits can also be verified directly in the
parallel programming mode. One instruction is used to read signature information (at addresses 30, 31, and 60h).
Separate instructions are used for the option control register.
The following sequence can be used to program the flash memory in the parallel programming mode:
1) The DS89C420 is powered up and running at a clock speed between 4MHz and 6MHz.
2) Set RST = EA = 1 and PSEN = 0.
3) Apply the appropriate logic combination to pins P2.6, P2.7, P3.6, and P3.7 to select one of the flash
instructions shown in Table 7.
For program operation, apply the desired address to pins P1.7:0 and P2.5:0. Data is written to port 0.
For verify operation, apply the desired address to pins P1.7:0 and P2.5:0. Data is read at port 0.
4) Pulse ALE/PROG once to perform an erase/program operation.
5) Repeat steps 3 and 4 as necessary.
ON-CHIP MOVX DATA MEMORY
On-chip data memory is provided by the 1kB SRAM and occupies addresses 0000h through 03FFh. The internal
data memory is disabled after a power-on reset, and any MOVX instruction directs the data memory access to the
external data memory. To enable the internal data memory, software must configure the data memory enable bits
DME1 and DME0 (PMR.1-0). See “SFR Bit Descriptions” in the Ultra-High-Speed Flash Microcontroller User’s
Guide for data memory configurations. Once enabled, MOVX instructions with addresses inside the 1k range
access the on-chip data memory, and addresses exceeding the 1k range automatically access external data
memory.
An internal data memory cycle spans only one system clock period to support fast internal execution.
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DS89C420 Ultra-High-Speed Microcontroller
Table 4. Parallel Programming Instruction Set
INSTRUCTION
P2.5:0,
P1.7:0
P0.7:0
PROG
P2.6
P2.7
P3.6
P3.7
OPERATION
H
L
L
L
Mass erase the 16k x 8 program
memory, the security block and the bank
select. The contents of every memory
location is returned to FFh.
L
H
H
H
Program the 16k program memory.
L
L
H
H
Verify the 16k program memory.
Don’t care
Don’t care
PL
(1)
ADDR
DIN
PL
(3)
ADDR
DOUT
H
ADDR
DIN
PL
(3)
L
H
L
H
Program the 64 byte encryption array.
Write LB1
Don’t care
Don’t care
PL
(3)
H
H
H
H
Program LB1 to logic 0.
Write LB2
Don’t care
Don’t care
PL
(3)
H
H
L
L
Program LB2 and LB1 to 00b.
Write LB3
Don’t care
Don’t care
PL
(3)
H
L
H
L
Program LB3, LB2, and LB1 to 000b.
Mass Erase
Write Program
Memory
Read Program
Memory
Write Encryption
Array
(4)
(4)
Read Lock Bits
Don’t care
DOUT
H
Write Option
Control Register
Don’t care
DIN
PL
Erase Option
Control Register
Don’t care
Don’t care
PL
Read Address 30,
31, 60, FC
ADDR
DOUT
H
L
L
L
H
(3)
L
H
L
L
(2)
H
L
L
H
L
L
L
L
(4)
Verify the lock bits. The lock bits are at
address 40h and the three LSBs of the
DOUT are the logic value of the lock bits
LB3, LB2, and LB1, respectively.
Program the option control register. Bit 3
of the DIN represents the watchdog
POR default setting.
Erase the option control register. This
operation disables the watch-dog reset
function on power-up.
30h = Manufacturer ID
31h = Device ID
60h = Device extension
FCh = Verify the option control register.
Bit 3 of the DOUT is the logic value of
the watchdog POR.
1)
Mass erase requires an active-low PROG pulse width of 828ms.
Erase option control register requires an active-low PROG pulse width of 828ms.
3)
Byte program requires an active-low PROG pulse width of 100ms max.
4)
PROG is weakly pulled to a high internally.
2)
Note 1: P3.2 is pulled low during programming to indicate Busy. P3.2 is pulled high again when programming is completed to indicate Ready.
Note 2: P3.0 is pulled high during programming to indicate an error.
DATA POINTER INCREMENT/DECREMENT AND OPTIONS
The DS89C420 incorporates a hardware feature to assist applications that require data pointer
increment/decrement. Data pointer increment/decrement bits ID0 and ID1 (DPS.6 and DPS.7) define how the INC
DPTR instruction functions in relation to the active DPTR (selected by the SEL bit). Setting ID0 = 1 and SEL = 0
enables the decrement operation for DPTR, and execution of the INC DPTR instruction decrements the DPTR
contents by 1. Similarly, setting ID1 = 1 and SEL = 1 enables the decrement operation for DPTR1, and execution of
the INC DPTR instruction decrements the DPTR1 contents by 1. With this feature, the user can configure the data
pointers to operate in four ways for the INC DPTR instruction:
ID1
0
0
1
1
ID0
0
1
0
1
SEL = 0
Increment DPTR
Decrement DPTR
Increment DPTR
Decrement DPTR
24 of 47
SEL = 1
Increment DPTR1
Increment DPTR1
Decrement DPTR1
Decrement DPTR1
DS89C420 Ultra-High-Speed Microcontroller
The SEL (DPS.0) bit always selects the active data pointer. The DS89C420 offers a programmable option that
allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting
the toggle-select-enable bit (TSL-DPS.5) to logic 1. Once enabled, the SEL bit is automatically toggled after the
execution of one of the following five DPTR-related instructions:
INC DPTR
MOV DPTR #data16
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
The DS89C420 also offers a programmable option that automatically increases (or decreases) the contents of the
selected data pointer by 1 after the execution of a DPTR-related instruction. The actual function (increment or
decrement) is dependent upon the setting of the ID1 and ID0 bits. This option is enabled by setting the automatic
increment/decrement enable (AID-DPS.4) to a logic 1 and is affected by one of the following three instructions:
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
EXTERNAL MEMORY
The DS89C420 executes external memory cycles for code fetches and read/writes of external program and data
memory. A non-page external memory cycle is four times slower than the internal memory cycles (i.e., an external
memory cycle contains four system clocks). For this reason, although a DS89C420 can be substituted for a ROMless 8051 device (DS80C310, C320, etc.), there is no increase in execution speed.
However, a page mode external memory cycle can be completed in 1, 2, or 4 system clocks for a page hit and 2, 4,
or 8 system clocks for a page miss, depending on user selection. The DS89C420 also supports a second page
mode operation with a different external bus structure that provides for fast external code fetches but uses 4
system clock cycles for data memory access.
EXTERNAL PROGRAM MEMORY INTERFACE (NON-PAGE MODE)
Figure 8 shows the timing relationship for internal and external code fetches when CD1 and CD0 are set to 10b,
assuming the microcontroller is in non-page mode for external fetches. Note that an external program fetch takes 4
system clocks, and an internal program fetch requires only 1 system clock.
As illustrated in Figure 8, ALE is deasserted when executing an internal memory fetch. The DS89C420 provides a
programmable user option to turn on ALE during internal program memory operation. ALE is automatically enabled
for code fetch externally, independent of the setting of this option.
PSEN is only asserted for external code fetches, and is inactive during internal execution.
EXTERNAL DATA MEMORY INTERFACE IN NON-PAGE MODE OPERATION
Just like the program memory cycle, the external data memory cycle is four times slower than the internal data
memory cycle in non-page mode. A basic internal memory cycle contains one system clock and a basic external
memory cycle contains four system clocks for non-page mode operation.
The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus
cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. Software can change the
stretch value dynamically by changing the setting of CKCON.2–CKCON.0. Table 5 shows the data memory cycle
stretch values and their effects on the external MOVX-memory bus cycle and the control signal pulse width in terms
of the number of oscillator clocks. A stretch machine cycle always contains four system clocks.
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DS89C420 Ultra-High-Speed Microcontroller
Figure 8. External Program Memory Access (Non-Page Mode and CD1:CD0 = 10)
Internal Memory Cycles
Ext Memory Cycle
C1
C2
C3
C4
Ext Memory Cycle
C1
C2
C3
C4
XTAL1
ALE
PSEN
LSB Add
Data
LSB Add
Data
Port 0
MSB Add
Port 2
MSB Add
Table 5. Data Memory Cycle Stretch Values
MD2:MD0
STRETCH
CYCLES
000
001
010
011
100
101
110
111
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12288
4
8
16
16384
5
10
20
20480
6
12
24
24576
7
14
28
28672
As shown in Table 5, the stretch feature supports eight stretched external data-memory access cycles that can be
categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on external data
memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch value is set to
1, 2, or 3, the external data-memory access is extended by 1, 2, or 3 stretch machine cycles, respectively. Note
that the first stretch value does not result in adding four system clocks to the RD/WR control signals. This is
because the first stretch uses one system clock to create additional setup time and one system clock to create
additional address hold time. When using very slow RAM and peripherals, a larger stretch value (4–7) can be
selected. In this stretch category, one stretch machine cycle (4 system clocks) is used to stretch the ALE pulse
width, one stretch machine cycle is used to create additional setup, one stretch machine cycle is used to create
additional hold time, and one stretch machine cycle is added to the RD or WR strobes.
Figure 9 and Figure 10 illustrate the timing relationship for external data-memory access in full speed
(stretch value = 0), in the default stretch setting (stretch value = 1), and slow data-memory accessing
(stretch value = 4) when the system clock is in divide by one mode (CD1:CD0 = 10b).
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DS89C420 Ultra-High-Speed Microcontroller
Figure 9. Non-Page Mode, External Data-Memory Access (Stretch = 0, CD1:CD2 = 10)
MOVX Instruction
1st Machine Cycle
2nd Machine Cycle
XTAL1
ALE
PSEN
RD WR
Port 0
A
Port 2
MOVX
A
INST
A
A
DATA
A
MOVX
Instruction
Fetch
Memory
Access
Stretch = 0
Figure 10. Non-Page Mode, External Data-Memory Access (Stretch = 1, CD1:CD2 = 10)
MOVX Instruction
1st Machine Cycle
2nd Machine Cycle
3rd Machine Cycle
XTAL1
ALE
PSEN
RD WR
Port 0
Port 2
A
MOVX
A
MOVX
Instruction
Fetch
A
INST
A
DATA
A
Memory Access
Stretch = 1
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DS89C420 Ultra-High-Speed Microcontroller
PAGE MODE, EXTERNAL MEMORY CYCLE
Page mode retains the basic circuitry requirement for original 8051 external memory interface, but alters the
configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles.
Additionally, the functions of ALE and PSEN are altered to support this mode of operation.
Setting the PAGEE (ACON.7) bit to logic 1 enables page mode. Clearing the PAGEE bit to a logic 0 disables the
page mode and the external bus structure defaults to the original 8051 expanded bus configuration (non-page
mode). The DS89C420 supports page mode in two external bus structures. The logic value of the page mode
select bits in the ACON register determines the external bus structure and the basic memory cycle in the number of
system clocks. Table 6 summarizes this option. The first three selections use the same bus structure but with a
different memory cycle time. Setting the select bits to 11b selects another bus structure. Write access to the ACON
register requires a timed access.
Table 6. Page Mode Select
PAGES1:PAGES0
CLOCKS PER MEMORY CYCLE
PAGE HIT
PAGE MISS
00
1
2
01
2
4
10
4
8
11
2
4
EXTERNAL BUS STRUCTURE
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of the address.
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of the address.
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of the address.
P0: Lower address byte.
P2: The upper address byte is multiplexed with the data byte.
Note: This setting affects external code fetches only; accessing the
external data memory requires 4 clock cycles, regardless of page hit
or miss.
The first page mode (page mode 1) external bus structure uses P2 as the primary address bus, (multiplexing both
the most significant byte (MSB) and least significant byte (LSB) of the address for each external memory cycle) and
P0 is used as the primary data bus. During external code fetches, P0 is held in a high-impedance state by the
processor. Op codes are driven by the external memory onto P0 and latched at the end of the external fetch cycle
at the rising edge of PSEN. During external data read/write operations, P0 functions as the data I/O bus. It is held in
a high-impedance state for external reads from data memory, and driven with data during external writes to data
memory.
§
§
A page miss occurs when the MSB of the subsequent address is different from the last address. The external
memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.
A page hit occurs when the MSB of the subsequent address does not change from the last address. The
external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr0–7 of the 16-bit address while the most significant address byte is held in the
external address latches. PSEN, RD, and WR strobe accordingly for the appropriate operation on the P0 data bus.
There is no ALE assertion for page hits.
During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the first half of
the memory cycle to allow the external address latches to latch the new most significant address byte. ALE is
asserted to strobe the external address latches. During this operation, PSEN, RD, and WR are held in inactive
states and P0 is in a high-impedance state. The second half of the memory cycle is executed as a page-hit cycle
and the appropriate operation takes place.
A page miss can occur at set intervals or during external operations that require a memory access into a page of
memory that has not been accessed during the last external cycle. Generally, the first external memory access
causes a page miss. The new page address is stored internally, and is used to detect a page miss for the current
external memory cycle.
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DS89C420 Ultra-High-Speed Microcontroller
Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b:
§
§
§
PSEN is asserted for both page hit and page miss for a full clock cycle.
The execution of external MOVX instruction causes a page miss.
A page miss occurs when fetching the next external instruction following the execution of an external MOVX
instruction.
Figure 11 shows the external memory cycle for this bus structure. The first case illustrates a back-to-back
execution sequence for 1-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during page-hit
cycles, and page misses are forced during and after MOVX executions, independent of the most significant byte of
the subsequent addresses. The second case illustrates a MOVX execution sequence for 2-cycle page mode
(PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code fetches. Note that changing the MSB
of the data address causes the page misses in this sequence. The third case illustrates a MOVX execution
sequence for 4-cycle page mode (PAGES1 = 1 and PAGES0 = 0). There is no page miss in this execution cycle
because the most significant byte of the data address is assumed to match the last program address.
The second page mode (page mode 2) external bus structure multiplexes the most significant address byte with
data on P2, and uses P0 for the least significant address byte. This bus structure is used to speed up external code
fetches only. External data-memory access cycles are identical to the non-page mode except for the different
signals on P0 and P2. Figure 12 illustrates the memory cycle for external code fetches.
29 of 47
DS89C420 Ultra-High-Speed Microcontroller
Figure 11. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)
Internal Memory Cycles
External Memory Cycles
XTAL1
ALE
PSEN
RD / WR
PAGES=00
Port 0
Port 2
Inst
MSB
LSB
Inst
LSB
Page Miss
MOVX
LSB
MOVX
LSB
Page Hit
Inst
Data
MSB
LSB
MSB
Data Access
LSB
MSB
Page Miss
MOVX executed
Data
LSB
MSB
Data Access
MOVX executed
ALE
PSEN
RD / WR
PAGES=01
Port 0
Port 2
MOVX
MSBAdd
Page Miss
Inst
LSB Add
Data
LSB Add
MSBAdd
Page Hit
LSB Add
Data Access
MOVX executed
MSBAdd
Page Miss
next instruction
ALE
PSEN
RD / WR
PAGES=10
Port 0
Port 2
Inst
MSBAdd
LSB Add
Page Miss
Data
LSB Add
Data Access
30 of 47
DS89C420 Ultra-High-Speed Microcontroller
Figure 12. Page Mode 2, External Code Fetch Cycle (CD1:CD0 = 10)
Ext Code Fetches
Internal Memory Cycles
Page Miss
C1
C2
C3
Page Hit
C4
C1
C2
Page Hit
C1 C2
XTAL1
ALE
PSEN
Port 0
LSB Add
Port 2
MSB Add
LSB Add
Data
Data
LSB Add
Data
STRETCH EXTERNAL DATA MEMORY CYCLE IN PAGE MODE
The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus
cycle in page mode operation just like non-page mode operation. The following tables summarize the stretch
values and their effects on the external MOVX-memory bus cycle and the control signals’ pulse width in terms of
the number of oscillator clocks. A stretch machine cycle always contains four system clocks, independent of the
logic value of the page mode select bits.
Table 7. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 00)
MD2:MD0
STRETCH
CYCLES
000
001
010
011
100
101
110
111
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.25
0.5
1
1024
0.75
1.5
3
3072
1.75
3.5
7
7168
2.75
5.5
11
11,264
3.75
7.5
15
15,360
4.75
9.5
19
19,456
5.75
11.5
23
23,552
6.75
13.5
27
27,648
Table 8. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 01)
MD2:MD0
STRETCH
CYCLES
000
001
010
011
100
101
110
111
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.25
0.5
1
1024
0.75
1.5
3
3072
1.75
3.5
7
7168
2.75
5.5
11
11,264
3.75
7.5
15
15,360
4.75
9.5
19
19,456
5.75
11.5
23
23,552
6.75
13.5
27
27,648
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DS89C420 Ultra-High-Speed Microcontroller
Table 9. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 10)
MD2:MD0
STRETCH
CYCLES
000
001
010
011
100
101
110
111
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12,288
4
8
16
16,384
5
10
20
20,480
6
12
24
24,576
7
14
28
28,672
Table 10. Page Mode 2, Data Memory Cycle Stretch Values (Pages1:Pages0 = 11)
MD2:MD0
STRETCH
CYCLES
000
001
010
011
100
101
110
111
0
1
2
3
7
8
9
10
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
4X/2X, CD1,
CD0 = 100
CD0 = 000
CD0 = X10
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12,288
4
8
16
16,384
5
10
20
20,480
6
12
24
24,576
7
14
28
28,672
As shown in the previous tables, the stretch feature supports eight stretched external data-memory access cycles
that can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on
external data-memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch
value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch memory cycles,
respectively. Note that the first stretch value does not result in adding four system clocks to the control signals. This
is because the first stretch uses one system clock to create additional address setup and data bus float time, and
one system clock to create additional address and data hold time. When using very slow RAM and peripherals, a
larger stretch value (4–7) can be selected. In this stretch category, two stretch cycles are used to create additional
setup (the ALE pulse width is also stretched by one stretch cycle for page miss) and one stretch cycle is used to
create additional hold time. The following timing diagrams illustrate the external data-memory access at divide-by-1
system clock mode (CD1:CD0 = 10b).
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DS89C420 Ultra-High-Speed Microcontroller
Figure 13. Page Mode 1, External Data Memory Access (Pages = 01, Stretch = 1, CD = 10)
XTAL1
MOVX Instruction
ALE
PSEN
RD / WR
Port 0
Inst
Inst
Port 2
LSB Addr
LSB Addr
MOVX
MSB Addr
LSB Addr
Data
Inst
LSB Addr
LSB Addr
Inst
Inst
LSB Addr
LSB Addr
Memory Access (Stretch =1)
MOVX Instruction
ALE
PSEN
RD / WR
Port 0
Inst
Port 2
LSB Addr
MOVX
LSB Addr
Data
Inst
MSB Addr
LSB Addr
MOVX Inst
Fetch
LSB Addr
Inst
Inst
Inst
LSB Addr
LSB Addr
LSB Addr
Inst
Inst
Inst
LSB Addr
LSB Addr
LSB Addr
Memory Access (Stretch =1)
MOVX Instruction
ALE
PSEN
RD / WR
Port 0
Inst
Port 2
LSB Addr
MOVX
LSB Addr
MOVX Inst
Fetch
Inst
LSB Addr
Data
MSB Addr
LSB Addr
Memory Access (Stretch =1)
Figure 13 illustrates the external data-memory stretch cycle timing relationship when PAGEE = 1 and
PAGES1:PAGES0 = 01. The stretch cycle shown is for a stretch value of 1 and is coincident with a page miss.
Note that the first stretch value does not result in adding four system clocks to the RD/WR control signals. This is
because the first stretch uses one system clock to create additional setup and one system clock to create
additional hold time.
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DS89C420 Ultra-High-Speed Microcontroller
Figure 14. Page Mode 1, External Data Memory Access (Pages = 01, Stretch = 4, CD = 10)
MOVX Instruction (Page miss)
1st
Cycle
2nd
Cycle
3rd
Cycle
4th
Cycle
9th
Cycle
XTAL1
ALE
PSEN
RD / WR
Inst
Inst
Inst
Inst
Inst
Port 0
Port 2
Inst
Data
LSB
LSB
LSB
LSB
MSB
MOVX
Instruction
Fetch
LSB
LSB
LSB
Memory Access (Stretch = 4)
MOVX Instruction (Page hit)
1st
2nd
Cycle Cycle
ALE
3rd
Cycle
4th
Cycle
5th
Cycle
9th
Cycle
PSEN
RD / WR
Inst
Port 0
Port 2
Inst
Inst
Inst
Inst
Inst
Inst
Data
LSB
LSB
LSB
MOVX
Instruction
Fetch
LSB
LSB
LSB
LSB
LSB
Memory Access (Stretch = 4)
Figure 14 shows the timing relationship for a slow peripheral interface (stretch value = 4). Note that a page hit datamemory cycle is shorter than a page miss data-memory cycle. The ALE pulse width is also stretched by a stretch
cycle in the case of page miss.
The stretched data-memory bus-cycle timing relationship for PAGES = 11 is identical to non-page mode operation
since the basic data-memory cycle always contains four system clocks in this page mode operation.
INTERRUPTS
The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power-fail, are
controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt enable register
(IE.7). Setting EA to logic 1 allows individual interrupts to be enabled. Setting EA to a logic 0 disables all interrupts
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DS89C420 Ultra-High-Speed Microcontroller
regardless of the individual interrupt enable settings. The power-fail interrupt is controlled by its individual enable
only.
The interrupt enables and priorities are functionally identical to those of the 80C52, except that the DS89C420
supports five levels of interrupt priorities instead of the original two.
INTERRUPT PRIORITY
There are five levels of interrupt priority: level 4 to 0. The highest interrupt priority is level 4, which is reserved for
the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to allow each
interrupt to be assigned a priority level from 3 to 0. The power-fail interrupt always has the highest priority if it is
enabled. All interrupts also have a natural hierarchy. In this manner, when a set of interrupts has been assigned the
same priority, a second hierarchy determines which interrupt is allowed to take precedence. The natural hierarchy
is determined by analyzing potential interrupts in a sequential manner with the order listed in Table 11.
Table 11. Interrupt Summary
INTERRUPT
VECTOR
Power-Fail
33h
External Interrupt 0
03h
Timer 0 Overflow
NATURAL
ORDER
0
(Highest)
FLAG
ENABLE
PRIORITY CONTROL
PFI (WDCON.4)
EPFI(WDCON.5)
N/A
1
IE0 (TCON.1)**
EX0 (IE.0)
0Bh
2
TF0 (TCON.5)*
ET0 (IE.1)
External Interrupt 1
13h
3
IE1 (TCON.3)**
EX1 (IE.2)
Timer 1 Overflow
1Bh
4
TF1 (TCON.7)*
ET1 (IE.3)
Serial Port 0
23h
5
Timer 2 Overflow
2Bh
6
Serial Port 1
3Bh
7
External Interrupt 2
43h
8
IE2 (EXIF.4)
EX2 (EIE.0)
External Interrupt 3
4Bh
9
IE3 (EXIF.5)
EX3 (EIE.1)
External Interrupt 4
53h
10
IE4 (EXIF.6)
EX4 (EIE.2)
External Interrupt 5
5Bh
11
IE5 (EXIF.7)
EX5 (EIE.3)
Watchdog
63h
12
(Lowest)
WDIF (WDCON.3)
EWDI (EIE.4)
RI_0 (SCON0.0)
TI_0 (SCON0.1)
TF2 (T2CON.7)
EXF2 (T2CON.6)
RI_1 (SCON1.0)
TI_1 (SCON1.1)
ES0 (IE.4)
ET2 (IE.5)
ES1 (IE.6)
LPX0 (IP0.0)
MPX0 (IP1.0)
LPT0 (IP0.1)
MPT0 (IP1.1)
LPX1 (IP0.2)
MPX1 (IP1.2)
LPT1 (IP0.3)
MPT1 (IP1.3)
LPS0 (IP0.4)
MPS0 (IP1.4)
LPT2 (IP0.5)
MPT2 (IP1.5)
LPS1 (IP0.6)
MPS1 (IP1.6)
LPX2 (EIP0.0)
MPX2 (EIP1.0)
LPX3 (EIP0.1)
MPX3 (EIP1.1)
LPX4 (EIP0.2)
MPX4 (EIP1.2)
LPX5 (EIP0.3)
MPX5 (EIP1.3)
LPWDI (EIP0.4)
MPWDI (EIP1.4)
*Cleared automatically by hardware when the service routine is vectored to.
**If the interrupt is edge triggered, cleared automatically by hardware when the service routine is vectored to. If the interrupt is level triggered,
the flag follows the state of the pin.
The processor indicates that an interrupt condition occurred by setting the respective flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Unless marked in Table 11, all these flags must be
cleared by software.
TIMER/COUNTERS
Three 16-bit timers are incorporated in the DS89C420. All three timers can be used as either counters of external
events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles.
Table 12 summarizes the timer functions.
Timers 0 and 1 both have three modes of operations. They can each be used as a 13-bit timer/counter, a 16-bit
timer/counter, or an 8-bit timer/counter with auto-reload. Timer 0 has a fourth operating mode as two 8-bit
35 of 47
DS89C420 Ultra-High-Speed Microcontroller
timer/counters without auto-reload. Each timer can also be used as a counter of external pulses on the
corresponding T0/T1 pin for 1-to-0 transitions. The timer mode (TMOD) register controls the operation mode. Each
timer consists of a 16-bit register in 2 bytes, which can be found in the SFR map as TL0, TH0, TL1, and TH1. The
timer control (TCON) register enables Timers 0 and 1.
Table 12. Timer Functions
FUNCTIONS
Timer/Counter
Timer with Capture
External Control-Pulse Counter
Up/Down Auto-Reload Timer/Counter
Baud Rate Generator
Timer-Output Clock Generator
TIMER 0
*
13/16/8 /2 x 8 bit
No
Yes
No
No
No
TIMER 1
*
13/16/8 bit
No
Yes
No
Yes
No
TIMER 2
16 bit
Yes
No
Yes
Yes
Yes
*8-bit timer/counter includes auto-reload feature; 2- x 8-bit mode does not.
Timer 2 is a true 16-bit timer/counter that, with a 16-bit capture (RCAP2L and RCAP2H) register, is able to provide
some unique functions like up/down auto-reload timer/counter and timer-output clock generation. Timer 2 (registers
TL2 and TH2) is enabled by the T2CON register, and its mode of operation is selected by the T2MOD register.
Each timer has a selectable time base (Table 14). Following a reset, the timers default to divide-by-12 to maintain
drop-in compatible with the 8051. If Timer 2 is used as a baud rate generator or clock output, its time base is fixed
at divide by 2, regardless of the setting of its timer mode bits.
For details of operation, refer to “Programmable Timers” in the Ultra-High-Speed Flash Microcontroller User’s
Guide.
TIMED ACCESS
The timed access function provides control verification to system functions. The timed access function prevents an
errant CPU from making accidental changes to certain SFR bits that are considered vital to proper system
operation. This is achieved by using software control when accessing the following SFR control bits:
WDCON.0
RWT
Reset Watchdog Timer
WDCON.1
EWT
Watchdog Reset Enable
WDCON.3
WDIF
Watchdog Interrupt Flag
WDCON.6
POR
Power-On Reset Flag
EXIF.0
BGS
Bandgap Select
ACON.5
PAGES0
Page Mode Select Bit 0
ACON.6
PAGES1
Page Mode Select Bit 1
ACON.7
PAGEE
Page Mode Enable
ROMSIZE.0
RMS0
Program Memory Size Select Bit 0
ROMSIZE.1
RMS1
Program Memory Size Select Bit 1
ROMSIZE.2
RMS2
Program Memory Size Select Bit 2
ROMSIZE.3
PRAME
Program RAM Enable
FCNTL.0
FC0
Flash Command Bit 0
FCNTL.1
FC1
Flash Command Bit 1
FCNTL.2
FC2
Flash Command Bit 2
FCNTL.3
FC3
Flash Command Bit 3
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DS89C420 Ultra-High-Speed Microcontroller
Before these bits can be altered, the processor must execute the timed access sequence. This sequence consists
of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three
machine cycles. This timed sequence of steps then allows any of the timed-access-protected SFR bits to be altered
during the three machine cycles, following the writing of the 55h. Writing to a timed access-protected bit outside of
these three machine cycles has no effect on the bit.
The timed-access process is address-, data-, and time-dependent. A processor running out of control and not
executing system software cannot statistically perform this timed sequence of steps, and as such, will not
accidentally alter the protected bits. It should be noted that this method should be used in the main body of the
system software and never used in an interrupt routine in conjunction with the watchdog reset. Interrupt routines
using the timed-access watchdog-reset bit (RWT) can recover a lost system and allow the resetting of the
watchdog, but the system returns to a lost condition once the RETI is executed, unless the stack is modified. It is
advisable that interrupts be disabled (EA = 0) when executing the timed-access sequence, since an interrupt during
the sequence adds time, making the timed-access attempt fail.
POWER MANAGEMENT AND CLOCK-DIVIDE CONTROL
The DS89C420 incorporates power management features that monitor the power-supply voltage levels and
support low-power operation with three power-saving modes. Such features include a bandgap voltage monitor,
watchdog timer, selectable internal ring oscillator, and programmable system clock speed. The SFRs that provide
control and application software access are the watchdog control (WDCON, D8h), extended interrupt enable (EIE,
E8h), extended interrupt flag (EXIF, 91h), and power control (PCON, 87h) registers.
SYSTEM CLOCK-DIVIDE CONTROL
The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to adapt to
different crystals and also to slow the system clocks providing lower power operation when required. An on-chip
crystal multiplier allows the DS89C420 to operate at two or four times the crystal frequency by setting the 4X/2X bit
and is enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide-by-1024.
When used with a 7.372MHz crystal, for example, the processor executes machine cycle in times ranging from
33.9ns (divide-by-0.25) to 138.9ms (multiply-by-1024), and maintains a highly accurate serial port baud rate while
allowing the use of more cost-effective, lower-frequency crystals. Although the clock-divide control bits can be
written at any time, certain hardware features have been provided to enhance the use of these clock controls to
guarantee proper serial port operation, and also to allow for a high-speed response to an external interrupt. The
01b setting of CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock
into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset.
When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5:SWB) is also set, the system
forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has
detected externally enabled interrupts.
The oscillator divide ratios of 0.25, 0.5, and 1 are also used to provide standard baud-rate generation for the serial
ports through a forced divide-by-12 input clock (TxMH, TxM = 00b, x = 1, 2, or 3) to the timers.
When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system
uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. This
automatic switchback is only enabled during divide-by-1024 mode, and all other clock modes are unaffected by
interrupts and serial port activity. See Power Management Mode for more details.
Use of the divide-by-0.25 or 0.5 options through the clock-divide control bits requires that the crystal multiplier be
enabled and the specific system-clock-multiply value be established by the 4X/2X bit in the PMR register. The
multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically selected until a startup delay has
been established through the CKRY bit in the status register. The 4X/2X bit can only be altered when the CTM bit is
cleared to logic 0. This prevents the system from changing the multiplier until the system has moved back to the
divide-by-1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered when
the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to logic 1
from a previous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup
timeout in the multiplier startup counter. During the multiplier startup period the CKRY bit remains cleared and the
CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to logic 0 on all resets. Figure 15 gives a
37 of 47
DS89C420 Ultra-High-Speed Microcontroller
simplified diagram of the generation of the system clocks. Specifics of hardware restrictions associated with the
use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR description.
Figure 15. System Clock Sources
4X/2X
CTM
Clock
Multiplier
Crystal
Oscillator
MUX
Divide 1024
System
Clock
Ring
Oscillator
Ring
Enable
CD0
Selector
CD1
BANDGAP-MONITORED INTERRUPT AND RESET GENERATION
The power monitor in the DS89C420 monitors the VCC pin in relation to the on-chip bandgap voltage reference.
Whenever VCC falls below VPFW , an interrupt is generated if the corresponding power-fail interrupt-enable bit EPFI
(WDCON.5) is set, causing the device to vector to address 33h. The power-fail interrupt-status bit PFI (WDCON.4)
is set anytime VCC transitions below VPFW , and can only be cleared by software once set. Similarly, as VCC falls
below VRST, a reset is issued internally to halt program execution. Following power-up, a power-on reset initiates a
power-on reset timeout before starting program execution. When VCC is first applied to the DS89C420, the
processor is held in reset until VCC > VRST and a delay of 65,536 oscillator cycles has elapsed, to ensure that power
is within tolerance and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the
reset condition is removed automatically and software execution begins at the reset vector location of 0000h. The
power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be
cleared by software.
When the DS89C420 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are
automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This is the lowest power mode.
If BGS is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up,
although in a reduced fashion, while in stop mode.
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DS89C420 Ultra-High-Speed Microcontroller
WATCHDOG TIMER
The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock
divider is set to 10b, the interrupt timeout has a default divide ratio of 217 of the crystal oscillator clock, with the
watchdog reset set to timeout 512 system clock cycles later. This results in a 33MHz crystal oscillator producing an
interrupt timeout every 3.9718ms, followed 15.5µs later by a watchdog reset. The watchdog timer is reset to the
default divide ratio following any reset. Using the WD0 and WD1 bits in the clock control (CKCON.6 and 7) register,
other divide ratios can be selected for longer watchdog interrupt periods. Table 13 summarizes the watchdog bit
settings and the timeout values.
Note: All watchdog-timer reset timeouts follow the programmed interrupt timeouts by 512 system clock cycles,
which equates to varying numbers of oscillator cycles depending on the clock-divide (CD1:0) and crystal multiplier
settings.
Table 13. Watchdog Timeout Value (in Number of Oscillator Clocks)
WATCHDOG INTERRUPT TIMEOUT
WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11
4X/2X
CD1:0
1
0
x
x
00
00
01
10
2
16
2
17
2
17
2
x
11
2
15
2
19
2
20
2
20
2
18
2
22
2
23
2
23
2
27
2
21
2
25
2
26
2
26
2
30
2
33
2
WD1:0 = 00
24
36
15
WATCHDOG RESET TIMEOUT
WD1:0 = 01
WD1:0 = 10
2 + 128
16
2 + 256
17
2 + 512
17
2 + 512
2
27
+ 524,288 2
18
2 + 128
19
2 + 256
20
2 + 512
20
2 + 512
30
21
2 + 128
22
2 + 256
23
2 + 512
23
2 + 512
33
+ 524,288 2 + 524,288 2
WD1:0 = 11
24
2 + 128
25
2 + 256
26
2 + 512
26
2 + 512
36
+ 524,288
A watchdog control (WDCON) SFR is used for programming the functions. EWT (WDCON.1) is the enable for the
watchdog-timer reset function and RWT (WDCON.0) is the bit used to restart the watchdog timer. Setting the RWT
bit restarts the timer for another full interval. If the watchdog timer reset function is masked by the EWT bit and no
resets are issued to the timer through the RWT bit, the watchdog timer generates interrupt timeouts at a rate
determined by the programmed divide ratio. WDIF (WDCON.3) is the interrupt flag set at timer termination and
WTRF (WDCON.2) is the reset flag set following a watchdog-reset timeout. The watchdog interrupt is enabled by
the EWDI bit (EIE.4) when it is set to 1. The watchdog timer reset and interrupt timeouts are measured by counting
system clock cycles.
An independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock cycles before
allowing the crystal oscillator to function as the system clock. This warmup time is verified by the watchdog timer
following each power-up as well as each time the crystal is restarted following a stop mode. The watchdog is also
used to establish a startup time whenever the CTM in the PMR register is set to enable the crystal multiplier
(4X/2X).
One of the applications of the watchdog timer is for the watchdog to wake up the system from idle mode. The
watchdog interrupt can be programmed to allow a system to wake up periodically to sample the external world.
EXTERNAL RESET
If the RST input is taken to a logic 1, the device is forced into a reset state. An external reset is accomplished by
holding the RST pin high for at least 3 clock cycles while the oscillator is running. Once the reset state is invoked, it
is maintained as long as RST is pulled to logic 1. When the RST is removed, the processor exits the reset state
within 4 clock cycles and begins execution at address 0000h. If a RST is applied while the processor is in stop
mode, the RST causes the oscillator to begin running and forces the program counter to 0000h. There is a reset
delay of 65,536 clock cycles to allow the oscillator to stabilize.
The RST pin is a bidirectional I/O. If a reset is caused by a power-fail reset, a watchdog timer reset, or an internal
system reset, an output-reset pulse is also generated at the RST pin. This reset pulse is asserted as long as an
internal reset is asserted and may not be able to drive the reset signal out if the RST pin is connected to an RC
circuit. Connecting the RST pin to a capacitor does not affect the internal reset condition.
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DS89C420 Ultra-High-Speed Microcontroller
OSCILLATOR-FAIL DETECT
The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal
oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. Setting the
OFDE (PCON.4) bit to logic 1 enables the circuit. The OFDE bit is only cleared from logic 1 to logic 0 by a powerfail reset or by software. A reset caused by an oscillator failure also sets the OFDF (PCON.5) to logic 1. This flag is
cleared by software or power-on reset. Note that this circuit does not force a reset when the oscillator is stopped by
the software-enabled stop mode.
POWER MANAGEMENT MODE
Power management mode offers a software-controllable power-saving scheme by providing a reduced instruction
cycle speed, which allows the DS89C420 to continue to operate while using an internally divided version of the
clock source to save power. Power management mode is invoked by software setting the clock-divide control bits
CD1 and CD0 (PMR.7-6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for 1 machine cycle. On
all forms of reset, the clock-divide control bits default to 10b, which selects 1 oscillator cycle per machine cycle.
Since the clock speed choice affects all functional logic including timers, the DS89C420 implements several
hardware switchback features that allow the clock speed to automatically return to the divide-by-1 mode from a
reduced cycle rate. Setting the SWB (PMR.5) bit to a 1 in software enables this switchback function.
When CD1 and CD0 are programmed to the divide-by-1024 mode and the SWB bit is also enabled, the system
forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an
externally enabled (and allowed through nesting priorities) interrupt. The switchback occurs whenever one of the
two conditions occur. The first switchback condition is initiated by the detection of a low on either INT0, INT1, INT3
or INT5, or a high on INT2 or INT4 when the respective pin has been programmed and allowed (through nesting
priorities) to issue an interrupt. The second switchback condition occurs when either serial port is enabled to
receive data and is found to have an active-low transition on the respective receive input pin. Serial port transmit
activity also forces a switchback if the SWB is set. Note that the serial port activity, as related to the switchback, is
independent of the serial port interrupt relationship. Any attempt to change the clock divider to the divide-by-1024
mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by1 mode. Note also that the switchback interrupt relationship requires that the respective external interrupt source is
allowed to actually generate an interrupt as defined by the priority of the interrupt and the state of the nested
interrupts, before the switchback can actually occur. An interrupt by the serial port is not required, nor is the setting
of serial port enable. Disabling external interrupts and serial port receive/transmission mode disable the automatic
switchback mode. Clearing the SWB bit also disables the switchback, and all interrupt and serial port controls of
the clock divider are disabled. All other clock modes ignore the switchback relationship and are unaffected by
interrupts and serial port activity.
The basic divide-by-12 mode for the timers (TxMH, TxM = 00b), as well as the divide-by-32 and 64 for mode 2 on
the serial ports, are maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1. Serial
ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and
require the switchback function to automatically return to the divide-by-1 mode for proper operation when a
qualified event occurs. Table 14 summarizes the effect of clock mode on timer operation.
It is possible to enable a receive function on a serial port when incoming data is not present and then change to the
higher divide ratio. An inactive serial port receive/transmit mode requires the receive input pin to remain high and
all outgoing transmissions to be completed. During this inactive receive mode it is possible to change the clockdivide control bits from a divide-by-1 to a 1024 divide ratio. In the case when the serial port is being used to receive
or transmit data it is very important to validate an attempted change in the clock-divide control bits (read CD1 and
CD0 to verify write was allowed) before proceeding with low-power program functions.
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DS89C420 Ultra-High-Speed Microcontroller
Table 14. Effect of Clock Mode on Timer Operation (in Number of Oscillator Clocks)
OSC.
CYCLES
4X/2X, CD1, CD0
PER
MACHINE
CYCLE
OSC. CYCLES PER
TIMERS (0, 1, 2)
CLOCK
TxMH, TxM
=
00
01
1x
OSC. CYCLES
PER TIMER 2
CLOCK
OSC. CYCLES
PER SERIAL
PORT CLOCK
MODE 0
OSC. CYCLES PER
SERIAL PORT
CLOCK MODE 2
BAUD RATE
GENERATOR SM2 = 0 SM2 = 1 SMOD = 0 SMOD = 1
T2MH, T2M = xx
100
0.25
12
1
0.25
2
3
1
64
32
000
0.5
12
2
0.5
2
6
2
64
32
x01
1 (reserved)
x10
1 (default)
x11
1,024
—
12
4
—
1
12,288 4,096 1,024
—
—
2
12
4
64
32
2,048
12,288
4,096
65,536
32,768
x = don’t care
RING OSCILLATOR
A ring oscillator, which typically runs at 10MHz, allows the processor to recover instantly from the stop mode.
When the system is in stop mode the crystal is disabled. When stop mode is removed, the crystal requires a period
of time to start up and stabilize. To allow the system to begin immediate execution of software following the
removal of the stop mode, the ring oscillator is used to supply a system clock until the crystal startup time is
satisfied. Once this time has passed, the ring oscillator is switched off and the system clock is switched over to the
crystal oscillator. This function is programmable and is enabled by setting the RGSL bit (EXIF.1) to logic 1. When it
is logic 0, the processor delays software execution until after the 65,536 crystal clock periods. To allow the
processor to know whether it is being clocked by the ring or the crystal oscillator, an additional bit, termed the
RGMD bit, indicates which clock source is being used. When the processor is running from the ring, the clockdivide control bits (CD1 and CD0 in the PMR register) are locked into the divide-by-1 mode (CD1:CD0 = 10b). The
clock-divide control bits cannot be changed from this state until after the system clock transitions to the crystal
oscillator (RGMD = 0).
Note: The watchdog is permanently connected to the crystal oscillator and continues to run at the external clock
rate. The ring oscillator does not drive it.
IDLE MODE
Idle mode suspends the processor by holding the program counter in a static state. No instructions are fetched and
no processing occurs. Setting the IDLE bit (PCON.0) to logic 1 invokes idle mode. The instruction that executes
this step is the last instruction prior to freezing the program counter. Once in Idle mode, all resources are preserved
but all peripheral clocks remain active, and the timers, watchdog, serial ports, and power monitor functions
continue to operate, so that the processor can exit the idle mode using any interrupt sources that are enabled. The
oscillator-detect circuit also continues to function when enabled. The IDLE bit is cleared automatically once idle
mode is exited. On returning from the interrupt vector using the RETI instruction, the next address is the one that
immediately follows the instruction that invoked the idle mode. Any processor resets also remove the idle mode.
STOP MODE
The stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication
are stopped, and no processing is possible.
Stop mode is invoked by setting the STOP bit (PCON.1) to logic 1. The processor enters the stop mode on the
instruction that sets the bit. The processor can exit stop mode by using any of the six external interrupts that are
enabled.
41 of 47
DS89C420 Ultra-High-Speed Microcontroller
An external reset by the RST pin unconditionally exits the processor from stop mode. If the BGS bit is set to logic 1,
the bandgap provides a reset while in stop mode if VCC should drop below the VRST level. If BGS is 0, no reset is
generated if VCC drops below VRST.
When the stop mode is removed, the processor waits for 65,536 clock cycles for the internal flash memory to warm
up before starting normal execution. Also, the processor waits for the crystal warmup period if not using the ring
oscillator.
SERIAL I/O
The DS89C420 provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second
hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and
P1.3 (TXD1) and has duplicate control functions included in new SFR locations.
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The second
serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) as the original. The new serial port can
only use timer 1 for timer-generated baud rates.
Control for serial port 0 is provided by the SCON0 register while its I/O buffer is SBUF0. Registers SCON1 and
SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both
serial ports is in the Ultra-High-Speed Flash Microcontroller User’s Guide.
INSTRUCTION SET
The DS89C420 instructions are 100% binary compatible with the industry standard 8051, and are only different in
the number of machine cycles used for the instructions. Some special conditions and features should be
considered when analyzing the DS89C420 instruction set. Full details are given in the Ultra-High-Speed Flash
Microcontroller User’s Guide.
42 of 47
DS89C420 Ultra-High-Speed Microcontroller
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
PKG
DIM
A
A1
A2
b
c
D
E
E1
e
L
eB
40-PIN
MIN
—
0.015
0.140
0.014
0.008
1.980
0.600
0.530
0.090
0.115
0.600
MAX
0.200
—
0.160
0.022
0.012
2.085
0.625
0.555
0.110
0.145
0.700
56–G5000–000
Dimensions are in inches (in).
43 of 47
DS89C420 Ultra-High-Speed Microcontroller
Note 1: Pin 1 identifier to be located in zone indicated.
Note 2: Controlling dimensions are in inches (in).
44 of 47
DS89C420 Ultra-High-Speed Microcontroller
45 of 47
DS89C420 Ultra-High-Speed Microcontroller
PIN CONFIGURATIONS
TOP VIEW
TOP VIEW
33
6
1
23
40
7
39
34
22
Dallas
Semiconductor
DS89C420
Dallas
Semiconductor
DS89C420
44
17
12
29
18
28
1
PLCC
11
TQFP
TOP VIEW
P1.0/T2
P1.1/T2EX
P1.2/RXD1
P1.3/TXD1
P1.4/INT2
P1.5/INT3
P1.6/INT4
P1.7/INT5
RST
P3.0/RXD0
P3.1/TXD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10 DS89C420
11
12
13
14
15
16
17
18
19
20
DIP
46 of 47
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA/VPP
ALE/PROG
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DS89C420 Ultra-High-Speed Microcontroller
REVISION HISTORY
REVISION
DESCRIPTION
092200
Initial release
122601
Added errata (See www.maxim-ic.com/errata for details.)
042702
Official product introduction release
051302
Inserted AC Characteristics table
103102
Removed (Min Operating Voltage) from DC Electrical Characteristics;
inserted diagram of ROM loader interface circuit
032003
Added 25MHz variant information
102203
Modified Figure 7 to support programmer-only operation.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products · Printed USA
47 of 47
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