ICL7116CJL

EVALUATION KIT AVAILABLE ICL7116/ICL7117 3½ Digit ADCs with Display Hold General Description The Maxim ICL7116 and ICL7117 are 3½ digit monolithic analog-to-digital converters. They differ from the Maxim ICL7106 and ICL7107 in that the ICL7116 and ICL7117 have a Hold pin, which makes it possible to hold or “freeze” a reading. These integrating ADCs have very high input impedances and directly drive LCD (ICL7116) and LED (ICL7117) displays. Versatility and accuracy are inherent features of these converters. The dual-slope conversion technique auto­ matically rejects interference signals common in industrial environments. The true differential input is particularly useful when making ratiometric measurements (ohms or bridge transducers). Maxim has added a zero-integrator phase to the ICL7116 and ICL7117, eliminating overrange hangover and hysteresis effects. Finally, these devices offer high accuracy by lowering rollover error to less than one count and zero reading drift to less than 1µV/ºC. Features ●● Improved 2nd Source! ●● Hold Pin Allows Indefinite Display Hold ●● Guaranteed First Reading Recovery from Overrange ●● On-Board Display Drive Capability—No External Circuitry Required: LCD (ICL7116), LED (ICL7117) ●● High-Impedance CMOS Differential Inputs ●● Low Noise (< 15µVP-P) Without Hysteresis or Overrange Hangover ●● Clock and Reference On-Chip ●● Zero Input Gives Zero Reading ●● True Polarity Indication for Precision Null Applications Ordering Information appears at end of data sheet. Applications These devices can be used in a wide range of digital panel meter applications. Most applications, however, involve the measurement and display of analog data: ●● ●● ●● ●● Pressure Voltage Resistance Temperature ●● ●● ●● ●● Conductance Current Speed Material Thickness Typical Operating Circuit LCD DISPLAY ANALOG INPUT + CLOSED = HOLD OPEN = RUN ICL7116 9V VREF TO ANALOG COMMON PIN [PIN 32] Detailed Circuit Diagram - see Figure 1 19-0949; Rev 2; 1/17 Pin Configurations TOP VIEW 1 HOLD OSC1 40 2 D1 OSC2 39 3 C1 OSC3 38 4 B1 TEST 37 5 A1 REF HI 36 6 F1 V+ 35 7 G1 C+REF 34 8 E1 C-REF 33 9 D2 COMMON 32 10 C2 ON HI 31 11 B2 ON LO 30 12 A2 A/Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP/GND 21 ICL7116 ICL7117 PDIP Pin Configurations continued at end of data sheet ICL7116/ICL7117 3½ Digit ADCs with Display Hold Absolute Maximum Ratings Supply Voltage ICL7116, V+ to V-...................................................................15V ICL7117, V+ to GND..............................................................+6V ICL7117, V- to GND............................................................... -9V Analog Input Voltage (either input) (Note 1)...................V+ to VReference lnput Voltage (either input)............................V+ to VClock Input ICL7116.................................................................... Test to V+ ICL7117...................................................................GND to V+ Power Dissipation (Note 2) Ceramic Package...........................................................1000mW CERDIP Package.............................................................800mW Plastic Package................................................................800mW Operating Temperature Range................................ 0ºC to +70ºC Storage Temperature Range..............................-65ºC to +160ºC Lead Temperature (soldering, 60s).................................. +300ºC Note 1: Input voltage may exceed supply voltages, provided the input current is limited to 100µA. Note 2: Dissipation rating assumes device is mounted with all leads soldered to the PCB. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS -000.0 ±000.0 +000.0 Digital Reading Zero Input Reading VIN = 0V Full Scale = 200.00mV Ratiometric Reading VIN = VREF = 100mV 999 999/ 1000 1000 Digital Reading Rollover Error (Difference in Reading for Equal Positive and Negative Reading Near Full Scale) -VIN = +VIN = 200mV -1 ±0.2 +1 Counts Linearity (Max. Deviation from Best Straight Line Fit) Full Scale = 200mV or Full Scale = 2.00mV -1 ±0.2 +1 Counts Common-Mode Rejection Ratio (Note 4) VCM = 1V, VIN = 0V Full Scale = 200.00mV 50 Noise (Pk-Pk Value Not Exceeded 95% of the Time) VIN = 0V Full Scale = 200.00mV 15 Leakage Current at Input VIN = 0V 1 10 pA Zero Reading Drift VIN = 0V, 0°C < TA < 70°C 0.2 1 µV/°C Scale Factor Temperature Coefficient VIN = 199.0mV 0°C < TA < 70°C (Ext. Ref. 0ppm/°C) 1 5 ppm/°C V+ Supply Current (Does Not Include LED Current for ICL7117) VIN = 0V 0.8 1.8 mA 0.6 1.8 mA 2.8 3.2 V V- Supply Current for ICL7117 Only Analog Common Voltage (With Respect to Positive Supply) 25Ω Between Common and Positive Supply Temperature Coefficient of Analog Common (With Respect to Pos. Supply) 25Ω Between Common and Positive Supply Input Resistance, Pin 1 (Note 6) VIL, Pin 1 (ICL7116 Only) www.maximintegrated.com 2.4 30 µV/V µV 80 ppm/°C 70 kΩ TEST – 1.5 V Maxim Integrated │  2 ICL7116/ICL7117 3½ Digit ADCs with Display Hold Electrical Characteristics (continued) (Note 3) PARAMETER CONDITIONS MIN TYP VIL, Pin 1 (ICL7117 Only) MAX GND +1.5 VIH, Pin 1 (Both) V+ - 1.5 ICL7116 Only (Note 5) Pk-Pk Segment Drive Voltage, Pk-Pk Backplane Drive Voltage V+ to V- = 9V ICL7117 Only (Except Pin 19) Segment Sinking Current V+ = 5.0V Segment Voltage = 3V (Pin 19 Only) V V 4 5 6 4 5 6 5 8.0 10 16 V mA Note 3: Unless otherwise noted, specifications apply to both the ICL7116 and ICL7117 at TA = +25°C, fCLOCK = 48kHz. ICL7116 is tested in the circuit of Figure 1. ICL7117 is tested in the circuit of Figure 2. Note 4: Refer to “Differential input” discussion (see Maxim’s ICL7106/ICL7107 data sheet). Note 5: Backplane drive is in phase with segment drive for ‘off’ segment, 180º out of phase for on segment. Frequency is 20 times the conversion rate. Average DC component is less than 50mV. Note 6: The ICL7116 logic input has an internal pulldown resistor connected from HLDR, pin 1, to TEST, pin 37. The ICL7117 logic input has an internal pulldown resistor connected from HLDR. Pin 1, to GROUND, pin 21. Maxim Advantages ●● ●● ●● ●● Guaranteed Overload Recovery Time Significantly Improved ESD Protection (Note 8) Low Noise Key Parameters Guaranteed Over Temperature ●● Negligible Hysteresis ●● Maxim Quality and Reliability ●● Increased Maximum Rating for Input Current (Note 9) Absolute Maximum Ratings This device conforms to the Absolute Maximum Ratings on adjacent page. Electrical Characteristics (Specifications below satisfy or exceed all ‘tested’ parameters on adjacent page V+ = 9V, TA = +25ºC, fCLOCK = 48kHz; test circuit = Figure 1 (ICL7116), Figure 2 (ICL7117), unless otherwise noted.) PARAMETER Zero Input Reading Ratiometric Reading CONDITIONS MIN TYP MAX UNITS VIN = 0V Full Scale = 200.00mV TA = +25°C (Note 7) -000.0 ±000.0 +000.0 Digital Reading 0°C ≤ TA ≤ +70°C (Note 11) -000.0 ±000.0 +000.0 999 999/ 1000 1000 999 999/ 1000 1001 -1 ±0.2 +1 VIN = VREF = 100mV TA = +25°C (Note 7) 0°C ≤ TA ≤ +70°C (Note 11) Rollover Error (Difference in Reading for Equal Positive and Negative Reading Near Full Scale) -VIN = +VIN = 200mV TA = +25°C (Note 7) Linearity (Max. Deviation from Best Straight Line Fit) Full Scale = 200mV or Full Scale = 2.00mV www.maximintegrated.com 0°C ≤ TA ≤ +70°C (Note 11) Digital Reading Counts ±0.2 -1 ±0.2 +1 Counts Maxim Integrated │  3 ICL7116/ICL7117 3½ Digit ADCs with Display Hold Electrical Characteristics (continued) Specifications below satisfy or exceed all ‘tested’ parameters on adjacent page V+ = 9V, TA = +25ºC, fCLOCK = 48kHz; test circuit = Figure 1 (ICL7116), Figure 2 (ICL7117), unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Common-Mode Rejection Ratio (Note 4) VCM = ±1V, VIN = 0V Full Scale = 200.00mV 50 µV/V Noise (Pk-Pk Value Not Exceeded 95% of the Time) VIN = 0V Full Scale = 200.00mV 15 µV VIN = 0V, TA = +25°C (Note 7) 1 10 0°C ≤ TA ≤ +70°C 20 200 Zero Reading Drift VIN = 0V, 0°C ≤ TA ≤ +70°C 0.2 1 µV/°C Scale Factor Temperature Coefficient VIN = 199.0mV 0°C ≤ TA ≤ +70°C (Ext. Ref. 0ppm/°C) 1 5 ppm/°C 0.8 1.8 Input Leakage Current V+ Supply Current (Does Not Include LED Current for ICL7117) VIN = 0V, TA = +25°C 0°C ≤ TA ≤ +70°C 2 V- Supply Current for ICL7117 Only Analog Common Voltage (With Respect to Positive Supply) 25Ω Between Common and Positive Supply Temperature Coefficient of Analog Common (With Respect to Pos. Supply) 25Ω Between Common and Positive Supply Input Resistance, Pin 1 (Note 6) 2.4 30 pA mA 0.6 1.8 mA 2.8 3.2 V 80 ppm/°C 70 kΩ VIL, Pin 1 (ICL7116 Only) TEST + 1.5 V VIL, Pin 1 (ICL7117 Only) GND + 1.5 V VIH, Pin 1 (Both) V+ - 1.5 V ICL7116 Only (Note 5) Pk-Pk Segment Drive Voltage, Pk-Pk Backplane Drive Voltage V+ to V- = 9V 4 5 ICL7117 Only (Except Pin 19) Segment Sinking Current V+ = 5.0V Segment Voltage = 3V 5 8.0 10 16 4 5 6 V 0 1 Measurement Cycles (Pin 19 Only) ICL7116 Only – Test Pin Voltage With respect to V+ Overload Recovery Time (Note 10) VIN changing from ±10V to 0V 6 V mA Note 7: Test condition is VIN applied between pins IN HI and IN LO i.e., 1MΩ resistor in Figure 1 and Figure 2. Note 8: All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V (Test circuit per MIL. Std. 883C. Method 3015 2). Note 9: Input voltages may exceed the supply voltage provided the input current is limited to ±1mA (This revises Note 1 on the adjacent page). Note 10: Number of measurement cycles for display to give accurate reading. Note 11: 1MΩ resistor is removed in Figure 1 and Figure 2. www.maximintegrated.com Maxim Integrated │  4 ICL7116/ICL7117 3½ Digit ADCs with Display Hold Detailed Description input. When the Hold input is connected to V+, however, the display latch pulse is inhibited, and the the display latches are not updated. The Hold input has a 70kΩ pulldown resistor to Test (ICL7116) or Ground (ICL7117) and the Hold input will be pulled low if it is left open. When Hold is low the ICL7116/ICL7117 updates the display at the end of each conversion. The Hold input is CMOS compatible and can also be driven by a switch connected to V+ (Figure 1 and Figure 2) or by a PNP transistor. The Maxim ICL7116 and ICL7117 3½ digit ADCs are similar to the Maxim ICL7106 and ICL7107, except for the addition of a Hold pin. For a detailed product description, package dimensions, and applications information (other than the operation of the Hold pin described below) refer to Maxim’s ICL7106 and ICL7107 data sheet Hold Input The Hold input is a digital input with a logic threshold approximately midway between V+ and Test (ICL7116) or V+ and Ground (ICL7117). The ICL7116/ICL7117 continuously performs conversions, independent of the Hold Unlike the ICL7106 and the ICL7107, the ICL7116 and ICL7117 do not have a Reference Low input. Apply the reference voltage between Reference High (REF HI) and Common. 0.1µF 34 1MΩ ANALOG INPUT + - 0.01µF 31 30 32 C+REF C-REF IN HI IN LO 47kΩ 0.22µF 0.47µF 29 29 2–19 22–25 POL COMMON BP ICL7116 28 LCD DISPLAY 33 HOLD V+ BUFF SEGMENT DRIVE 20 21 MINUS SIGN BACKPLANE DRIVE CLOSED = HOLD OPEN = RUN 1 35 24kΩ 9V A-Z REF HI INT OSC2 OSC3 38 COSC 39 100pF ROSC 100kΩ OSC1 40 V- 36 VREF 10kΩ 26 TO ANALOG COMMON PIN [PIN 32] Figure 1. Maxim ICL7116 Typical Operating Circuit, 200mV Reference www.maximintegrated.com Maxim Integrated │  5 ICL7116/ICL7117 3½ Digit ADCs with Display Hold 0.1µF 34 1MΩ ANALOG INPUT + - 0.01µF 31 30 32 C+REF C-REF IN HI 47kΩ 0.22µF 0.47µF 29 29 2–19 22–25 IN LO POL COMMON BP ICL7117 28 LCD DISPLAY 33 BUFF SEGMENT DRIVE 20 21 BACKPLANE DRIVE CLOSED = HOLD OPEN = RUN 1 HOLD 35 + V +5V 24kΩ A-Z REF HI INT OSC2 OSC3 38 COSC 39 100pF OSC1 40 V- 36 VREF 10kΩ 26 ROSC 100kΩ +5V TO ANALOG COMMON PIN [PIN 32] Figure 2. Maxim ICL7117 Typical Operating Circuit, 200mV Reference Chip Topography D3 E2 F2 A2 B2 C2 D2 E1 G1 F1 B3 F3 E3 0.168" (4.27mm) A1 B1 C1 D1 HLDR OSC1 AB4 POL4 BP/GND [7116/7117] G3 A3 OSC2 OSC3 TEST REF HI C3 G2 V+ V- www.maximintegrated.com INT A/Z IN H1 C-REF BUFF IN LO COMMONC+REF 0.130" (3.30mm) Maxim Integrated │  6 ICL7116/ICL7117 3½ Digit ADCs with Display Hold INT V- 35 34 A-Z BUFF IN LO 37 36 COMMON IN HI 39 38 C+ REF C- REF 41 40 44 43 42 41 40 V+ 1 REF HI N.C. 2 TOP VIEW 44 43 42 HOLD 3 TEST D1 4 OSC3 C1 5 OSC2 B1 6 OSC1 A1 TOP VIEW REF HI Pin Configurations (continued) F1 7 39 V+ N.C. 1 33 N.C. G1 8 38 C+ REF N.C. 2 32 G2 E1 9 37 C- REF TEST 3 31 C3 D2 10 36 COMMON OSC3 4 30 A3 35 IN HI 29 G3 34 N.C. 28 BP/GND B2 13 33 IN LO POL A2 14 32 A/Z AB4 D1 9 25 E3 C1 10 24 F3 B1 11 23 B3 Ordering Information TEMP RANGE 21 22 E2 D3 20 F2 MQFP PLCC PART A2 18 19 B2 + 17 G2 C3 A3 G3 BP/GND N.C. POL AB4 E3 F3 B3 18 19 20 21 22 23 24 25 26 27 28 26 C2 V- 8 16 29 HOLD D2 D3 17 27 E1 INT 7 14 15 BUFF 30 OSC1 ICL7117 G1 31 6 13 F2 15 E2 16 5 12 N.C. 12 N.C. OSC2 F1 ICL7116 ICL7117 A1 C2 11 Chip Information PIN-PACKAGE ICL7116CPL 0°C to +70°C 40 PDIP ICL7116CJL 0°C to +70°C 40 CERDIP ICL7116CQ 0°C to +70°C 44 LPCC ICL7116C/D 0°C to +70°C Dice ICL7117CPL 0°C to +70°C 40 PDIP ICL7117CJL 0°C to +70°C 40 CERDIP ICL7117CMH+ 0°C to +70°C 44 MQFP ICL7117CQ 0°C to +70°C 44 LPCC ICL7117C/D 0°C to +70°C Dice PROCESS: CMOS +Denotes lead(Pb)-free/RoHS-compliant package. www.maximintegrated.com Maxim Integrated │  7 ICL7116/ICL7117 3½ Digit ADCs with Display Hold Revision History REVISION NUMBER REVISION DATE 0 9/85 Initial release 1 9/13 Added the 44 MQFP package to data sheet 1–8 2 1/17 Updated Figure 2 and Pin Configuration diagram 6, 7 DESCRIPTION PAGES CHANGED — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc. │  8