19-3158; Rev 1; 4/09
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
The MAX1274/MAX1275 low-power, high-speed, serialoutput, 12-bit, analog-to-digital converters (ADCs) operate at up to 1.8Msps. These devices feature true-differential inputs, offering better noise immunity, distortion
improvements, and a wider dynamic range over singleended inputs. A standard SPI™/QSPI™/MICROWIRE™
interface provides the clock necessary for conversion.
These devices easily interface with standard digital signal
processor (DSP) synchronous serial interfaces.
The MAX1274/MAX1275 operate from a single +4.75V to
+5.25V supply voltage and require an external reference.
The MAX1274 has a unipolar analog input, while the
MAX1275 has a bipolar analog input. These devices feature a partial power-down mode and a full power-down
mode for use between conversions, which lower the supply current to 1mA (typ) and 1µA (max), respectively. Also
featured is a separate power-supply input (VL), which
allows direct interfacing to +1.8V to VDD digital logic. The
fast conversion speed, low-power dissipation, excellent
AC performance, and DC accuracy (±1 LSB INL) make
the MAX1274/MAX1275 ideal for industrial process control, motor control, and base-station applications.
The MAX1274/MAX1275 come in a 12-pin TQFN package, and are available in the extended (-40°C to +85°C)
temperature range.
Applications
Data Acquisition
Communications
Bill Validation
Portable Instruments
Features
♦ 1.8Msps Sampling Rate
♦ Only 45mW (typ) Power Dissipation
♦ Only 1µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial Interface
♦ 70dB S/(N + D) at 525kHz Input Frequency
♦ Internal True-Differential Track/Hold (T/H)
♦ External Reference
♦ No Pipeline Delays
♦ Small 12-Pin TQFN Package
Ordering Information
PART
PINPACKAGE
TEMP RANGE
INPUT
MAX1274AETC+T
-40°C to +85°C 12 TQFN
Unipolar
MAX1274BETC+T
-40°C to +85°C 12 TQFN
Unipolar
MAX1275AETC+T
-40°C to +85°C 12 TQFN
Bipolar
MAX1275BETC+T
-40°C to +85°C 12 TQFN
Bipolar
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Motor Control
Pin Configuration
TOP VIEW
AIN+
N.C.
SCLK
12
11
10
Typical Operating Circuit
0.01μF
10μF
AIN-
1
REF
2
RGND
3
MAX1274
MAX1275
4
VDD
5
6
N.C.
GND
+1.8V TO VDD
+4.75V TO +5.25V
9
CNVST
8
DOUT
7
VL
TQFN
0.01μF
VDD
DIFFERENTIAL +
INPUT
VOLTAGE -
10μF
VL
DOUT
AIN+
AIN-
MAX1274
MAX1275
μC/DSP
CNVST
SCLK
REF
4.7μF
REF
0.01μF
RGND
GND
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1274/MAX1275
General Description
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VL to GND ...................-0.3V to the lower of (VDD + 0.3V) or +6V
Digital Inputs
to GND ....................-0.3V to the lower of (VDD + 0.3V) or +6V
Digital Output
to GND .......................-0.3V to the lower of (VL + 0.3V) or +6V
Analog Inputs and
REF to GND.............-0.3V to the lower of (VDD + 0.3V) or +6V
RGND to GND .......................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Range
MAX127_ ETC.................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
Relative Accuracy
INL
(Note 1)
Differential Nonlinearity
DNL
(Note 2)
Bits
MAX127_A
-1.0
+1.0
MAX127_B
-1.75
+1.75
MAX127_A
-1.0
+1.0
MAX127_B
-1.0
+1.75
Offset Error
±6.0
Offset-Error Temperature
Coefficient
±1
Gain Error
Offset nulled
LSB
LSB
ppm/°C
±6.0
Gain Temperature Coefficient
LSB
±2
LSB
ppm/°C
DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
MAX127_A
69
70
MAX127_B
67
70
fIN1 = 250kHz, fIN2 = 300kHz
dB
-80
-76
-83
-76
-78
dB
dB
dB
Full-Power Bandwidth
-3dB point, small-signal method
20
MHz
Full-Linear Bandwidth
S/(N + D) > 68dB, single ended
1.2
MHz
CONVERSION RATE
Minimum Conversion Time
tCONV
(Note 3)
Maximum Throughput Rate
Minimum Throughput Rate
Track-and-Hold Acquisition Time
(Note 4)
tACQ
(Note 5)
Aperture Delay
Aperture Jitter
External Clock Frequency
2
(Note 6)
0.556
µs
1.8
Msps
10
ksps
104
ns
5
ns
30
ps
fSCLK
_______________________________________________________________________________________
28.8
MHz
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (AIN+, AIN-)
Differential Input Voltage Range
VIN
AIN+ - AIN-, MAX1274
0
VREF
AIN+ - AIN-, MAX1275
-VREF/2
+VREF/2
0
VDD
V
±1
µA
Absolute Input Voltage Range
DC Leakage Current
V
Input Capacitance
Per input pin
16
pF
Input Current (Average)
Time averaged at maximum throughput rate
75
µA
REFERENCE INPUT (REF)
REF Input Voltage Range
VREF
VDD +
50mV
1.0
Input Capacitance
20
DC Leakage Current
pF
±1
Input Current (Average)
Time averaged at maximum throughput rate
V
400
µA
µA
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low
VIL
Input Voltage High
VIH
Input Leakage Current
IIL
0.3 x VL
V
±10
µA
0.7 x VL
V
0.05
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
For stated timing performance
30
pF
Output Voltage Low
COUT
VOL
ISINK = 5mA, VL ≥ 1.8V
0.4
V
Output Voltage High
VOH
ISOURCE = 1mA, VL ≥ 1.8V
Output Leakage Current
IOL
Output high impedance
±10
µA
VL - 0.5V
V
±0.2
POWER REQUIREMENTS
Analog Supply Voltage
VDD
4.75
5.25
V
Digital Supply Voltage
VL
1.8
VDD
V
Analog Supply Current,
Normal Mode
IDD
Analog Supply Current,
Partial Power-Down Mode
IDD
Analog Supply Current,
Full Power-Down Mode
IDD
Static, fSCLK = 28.8MHz
7
Static, no SCLK
4
5
Operational, 1.8Msps
9
11
fSCLK = 28.8MHz
1
No SCLK
1
fSCLK = 28.8MHz
1
No SCLK
Operational, full-scale input at 1.8Msps
Digital Supply Current (Note 7)
Positive-Supply Rejection
PSR
9
mA
mA
1
µA
1
2.5
Static, fSCLK = 28.8MHz
0.4
1
Partial/full power-down mode,
fSCLK = 28.8MHz
0.2
0.5
Static, no SCLK, all modes
0.1
1
µA
±0.2
±3.0
mV
VDD = 5V ±5%, full-scale input
mA
_______________________________________________________________________________________
3
MAX1274/MAX1275
ELECTRICAL CHARACTERISTICS (continued)
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Pulse-Width High
tCH
VL = 1.8V to VDD
15.6
ns
SCLK Pulse-Width Low
tCL
VL = 1.8V to VDD
15.6
ns
SCLK Rise to DOUT Transition
tDOUT
CL = 30pF, VL = 4.75V to VDD
14
CL = 30pF, VL = 2.7V to VDD
17
CL = 30pF, VL = 1.8V to VDD
24
ns
DOUT Remains Valid After SCLK
Rise
tDHOLD
VL = 1.8V to VDD
4
ns
CNVST Fall to SCLK Fall
tSETUP
VL = 1.8V to VDD
10
ns
tCSW
VL = 1.8V to VDD
20
ns
CNVST Pulse Width
Power-Up Time; Full Power-Down
tPWR-UP
2
ms
Restart Time; Partial Power-Down
tRCV
16
Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th rising edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
VL
CNVST
tCSW
tSETUP
tCL
tCH
SCLK
DOUT
tDHOLD
tDOUT
6kΩ
DOUT
DOUT
6kΩ
4
GND
GND
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
Figure 1. Detailed Serial-Interface Timing
CL
CL
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
Figure 2. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
0.6
0.2
0
0
-0.2
-0.2
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
0
5000
1000
2000
3000
4000
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1275)
OFFSET ERROR
vs. TEMPERATURE (MAX1274)
OFFSET ERROR
vs. TEMPERATURE (MAX1275)
OFFSET ERROR (LSB)
0.4
0.2
0
-0.2
0.2
0.1
0
-0.1
0.75
0.50
0.25
0
-0.25
-0.4
-0.2
-0.50
-0.6
-0.3
-0.75
-0.8
-0.4
1000
2000
3000
4000
5000
-1.00
-40
-15
10
35
60
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE (MAX1274)
GAIN ERROR
vs. TEMPERATURE (MAX1275)
-1.5
-2.0
-15
10
35
85
60
FFT PLOT (MAX1274)
0
-1.5
-2.0
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN = 100kHz
SINAD = 70.74dB
SNR = 70.82dB
THD = -88.63dB
SFDR = 87.07dB
-20
AMPLITUDE (dB)
-1.0
GAIN ERROR (LSB)
-1.0
-40
TEMPERATURE (°C)
-0.5
MAX1274 toc07
-0.5
85
MAX1274 toc08
0
MAX1274 toc06
0.3
OFFSET ERROR (LSB)
0.6
1.00
MAX1274 toc05
0.4
MAX1274 toc04
0.8
5000
-40
-60
MAX1274 toc09
0
DNL (LSB)
0.4
0.2
INL (LSB)
0.4
0.2
0
DNL (LSB)
0.6
0.4
-0.8
GAIN ERROR (LSB)
0.8
MAX1274 toc02
0.6
INL (LSB)
0.8
MAX1274 toc01
0.8
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1274)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1275)
MAX1274 toc03
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1274)
-80
-100
-2.5
-3.0
-40
-2.5
-15
10
35
TEMPERATURE (°C)
60
85
-3.0
-40
-120
-140
-15
10
35
TEMPERATURE (°C)
60
85
0
200
400
600
800
1000
ANALOG INPUT FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX1274/MAX1275
Typical Operating Characteristics
(VDD = +5V, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured
at TA = +25°C)
Typical Operating Characteristics (continued)
(VDD = +5V, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured
at TA = +25°C)
FFT PLOT (MAX1275)
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
-140
-140
200
400
600
800
1000
0
ANALOG INPUT FREQUENCY (kHz)
-60
800
1000
-80
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN = 500kHz
SINAD = 70.84dB
SNR = 71.11dB
THD = -83.05dB
SFDR = 84.68dB
-20
AMPLITUDE (dB)
-40
-60
-80
-100
-100
-120
-120
-140
-140
200
400
600
800
0
1000
200
400
600
800
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
FFT PLOT (MAX1275)
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN = 500kHz
SINAD = 70.55dB
SNR = 70.73dB
THD = -84.43dB
SFDR = 85.16dB
-20
-40
-60
-60
-80
-65
1000
-70
THD (dB)
0
MAX1274 toc14
0
MAX1274 toc15
AMPLITUDE (dB)
-40
600
0
MAX1274 toc12
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN = 300kHz
SINAD = 70.66dB
SNR = 71.09dB
THD = -80.85dB
SFDR = 81.26dB
-20
400
FFT PLOT (MAX1274)
FFT PLOT (MAX1275)
0
200
ANALOG INPUT FREQUENCY (kHz)
MAX1274 toc13
0
fIN = 500kHz
-75
-80
-85
-100
fIN = 100kHz
-90
-120
-95
-140
-100
0
200
400
600
800
ANALOG INPUT FREQUENCY (kHz)
6
MAX1274 toc11
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN = 300kHz
SINAD = 70.88dB
SNR = 71.24dB
THD = -81.96dB
SFDR = 83.65dB
-20
AMPLITUDE (dB)
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN = 100kHz
SINAD = 70.41dB
SNR = 70.53dB
THD = -85.92dB
SFDR = 87.56dB
-20
AMPLITUDE (dB)
FFT PLOT (MAX1274)
0
MAX1274 toc10
0
AMPLITUDE (dB)
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
1000
10
100
1000
SOURCE IMPEDANCE (Ω)
_______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
fIN2
-60
-80
-120
-140
200
400
600
800
1000
0
200
400
600
800
1000
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
VDD/VL FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
VL PARTIAL/FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
0.6
VDD, fSCLK = 28.8MHz
0.4
VDD, fSCLK = 0
0.2
VL = 5V, fSCLK = 28.8MHz
VL SUPPLY CURRENT (μA)
0.8
MAX1274 toc19
200
MAX1274 toc18
1.0
150
100
VL = 3V, fSCLK = 28.8MHz
50
VL, fSCLK = 0
0
-15
10
35
60
-40
85
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
VDD SUPPLY CURRENT
vs. TEMPERATURE
VDD SUPPLY CURRENT
vs. CONVERSION RATE
MAX1274 toc20
12
CONVERTING
fSCLK = 28.8MHz
9
6
PARTIAL POWER-DOWN
fSCLK = 28.8MHz
12
85
MAX1274 toc21
0
-40
VDD SUPPLY CURRENT (mA)
VDD/VL SUPPLY CURRENT (μA)
-80
-120
0
VDD SUPPLY CURRENT (mA)
fIN2
-60
-100
-140
fIN1
-40
-100
3
fSAMPLE = 2Msps
fSCLK = 32MHz
fIN1 = 250.039kHz
fIN2 = 300.059kHz
IMD = -81.82dB
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
fIN1
MAX1274 toc16
fSAMPLE
= 2Msps
SCLK = 32MHz
32MHz
fSCLK
IN1 = =250.039kHz
fIN1
300.059kHz
IN2 = 250.039kHz
fIN2 = 300.059kHz
IMD = -84.23dB
-20
-40
TWO-TONE IMD PLOT (MAX1275)
0
MAX1274 toc17
TWO-TONE IMD PLOT (MAX1274)
0
9
6
3
0
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
0
500
1000
1500
2000
fSAMPLE (kHz)
_______________________________________________________________________________________
7
MAX1274/MAX1275
Typical Operating Characteristics (continued)
(VDD = +5V, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured
at TA = +25°C)
Typical Operating Characteristics (continued)
(VDD = +5V, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured
at TA = +25°C)
VL SUPPLY CURRENT
vs. TEMPERATURE
VL SUPPLY CURRENT
vs. CONVERSION RATE
VL SUPPLY CURRENT (mA)
0.6
FULL/PARTIAL
POWER-DOWN
fSCLK = 28.8MHz
0.4
0.2
0
-40
MAX1274 toc23
CONVERTING
fSCLK = 28.8MHz
0.8
1.0
MAX1274 toc22
1.0
VL SUPPLY CURRENT (mA)
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
0.8
VL = 5V
0.5
VL = 3V
VL = 1.8V
0.3
0
-15
10
35
60
85
0
500
TEMPERATURE (°C)
1000
1500
2000
fSAMPLE (kHz)
Pin Description
8
PIN
NAME
1
AIN-
Negative Analog Input
FUNCTION
2
REF
External Reference Voltage Input. VREF sets the analog input range. Bypass REF with a 0.01µF
capacitor and a 4.7µF capacitor to RGND.
3
RGND
4
VDD
Positive Analog Supply Voltage (+4.75V to +5.25V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
5, 11
N.C.
No Connection
6
GND
Ground. GND is internally connected to EP.
7
VL
8
DOUT
Serial Data Output. Data is clocked out on the rising edge of SCLK.
9
CNVST
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
10
SCLK
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
12
AIN+
Positive Analog Input
—
EP
Reference Ground. Connect RGND to GND.
Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.
Exposed Paddle. EP is internally connected to GND.
_______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
VL
MAX1274/MAX1275
VDD
CAPACITIVE
DAC
REF
CIN+
RIN+
AIN+
AIN+
12-BIT
SAR
ADC
T/H
AIN-
OUTPUT
BUFFER
VAZ
DOUT
COMP
CONTROL
LOGIC
AINCINCONTROL
LOGIC AND
TIMING
RIN-
ACQUISITION MODE
CAPACITIVE
DAC
CNVST
SCLK
CIN+
RIN+
AIN+
MAX1274
MAX1275
VAZ
RGND
GND
Figure 3. Functional Diagram
Detailed Description
The MAX1274/MAX1275 use an input T/H and successive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1274/MAX1275.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input architecture of the MAX1274/MAX1275, which is composed
of a T/H, a comparator, and a switched-capacitor digital-to-analog converter (DAC). The T/H enters its tracking mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is connected to AIN+. The negative input capacitor is connected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input
signal is determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens. The
acquisition time, tACQ, is the minimum time needed for
COMP
CONTROL
LOGIC
AINCIN-
RIN-
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
the signal to be acquired. It is calculated by the following equation:
tACQ ≥ 9 × (RS + RIN) × 16pF
where RIN = 200Ω, and RS is the source impedance of
the input signal.
Note: tACQ is never less than 104ns and any source
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 20MHz smallsignal bandwidth, making it is possible to digitize highspeed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to VDD and GND allow the analog input pins to swing
from GND - 0.3V to VDD + 0.3V without damage. Both
inputs must not exceed VDD or be lower than GND for
accurate conversions.
_______________________________________________________________________________________
9
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Serial Interface
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conversion is determined.
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1274/MAX1275 require a
complete conversion cycle to initialize the internal calibration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conversion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t DOUT after each
SCLK’s rising edge and remains valid 4ns (tDHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
Timing and Control
Conversion-start and data-read operations are controlled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serialinterface operation.
CNVST
tSETUP
1
SCLK
tACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
16
POWER-MODE SELECTION WINDOW
2
3
HIGH IMPEDANCE
4
8
D11
DOUT
D10
D9
D8
14
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Interface-Timing Sequence
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
CNVST
ONE 8-BIT TRANSFER
SCLK
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
DOUT
MODE
0
0
0
D11
D10
NORMAL
D9
D8
D7
PPD
Figure 6. SPI Interface—Partial Power-Down Mode
10
______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
External Reference
Power consumption can be reduced significantly by placing the MAX1274/MAX1275 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wakeup time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 1mA. Drive CNVST
low and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit partial power-down mode.
Full power-down mode is ideal for infrequent data sampling and very low supply current applications. The
MAX1274/MAX1275 have to be in partial power-down
mode in order to enter full power-down mode. Perform
the SCLK/CNVST sequence described above to enter
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full powerdown mode. In partial/full power-down mode, maintain
a logic low or a logic high on SCLK to minimize power
consumption.
An external reference is required for the MAX1274/
MAX1275. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to VDD.
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high impedance on the next rising edge of CNVST or SCLK,
enabling the serial interface to be shared by multiple
devices. If CNVST returns high after the 14th, but before
the 16th SCLK rising edge, DOUT remains active so continuous conversions can be sustained. The highest
throughput is achieved when performing continuous conversions. Figure 10 illustrates a conversion using a typical
serial interface.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1274. Figure 9 shows the bipolar transfer function for
the MAX1275. The MAX1274 output is straight binary,
while the MAX1275 output is two’s complement.
EXECUTE PARTIAL POWER-DOWN TWICE
CNVST
FIRST 8-BIT TRANSFER
SECOND 8-BIT TRANSFER
SCLK
1ST SCLK RISING EDGE
DOUT
MODE
0
0
0
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
D11
D10
NORMAL
D9
D8
0
D7
PPD
0
0
0
0
RECOVERY
0
0
0
FPD
Figure 7. SPI Interface—Full Power-Down Mode
______________________________________________________________________________________
11
MAX1274/MAX1275
Applications Information
Partial Power-Down and
Full Power-Down Modes
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Connection to
Standard Interfaces
OUTPUT CODE
The MAX1274/MAX1275 serial interface is fully compatible with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
FULL-SCALE
TRANSITION
111...111
111...110
111...101
SPI and MICROWIRE
FS = VREF
ZS = 0
V
1 LSB = REF
4096
000...011
000...010
000...001
000...000
0
1
2
3
FS
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function (MAX1274 Only)
When using SPI or MICROWIRE, the MAX1274/MAX1275
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid tDOUT later and
remains valid until tDHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0, or CPOL =
1 and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1, or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
QSPI
OUTPUT CODE
FULL-SCALE
TRANSITION
V
FS = REF
2
ZS = 0
-V
- FS = REF
2
V
1 LSB = REF
4096
011...111
011...110
000...010
000...001
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the
data. The MAX1274/MAX1275 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSBfirst format.
000...000
DSP Interface to the TMS320C54_
111...111
The MAX1274/MAX1275 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1274/MAX1275 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
For continuous conversion, set the serial port to transmit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port configuration (SPC) register should be set up with internal
111...110
111...101
100...001
100...000
-FS
0
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 9. Bipolar Transfer Function (MAX1275 Only)
12
______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
MAX1274/MAX1275
CNVST
SCLK
1
14
16
1
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 10. Continuous Conversion with Burst/Continuous Clock
I/O
SCK
MISO
+3V TO +5V
CNVST
SCLK
DOUT
MAX1274
MAX1275
SS
A) SPI
CS
SCK
MISO
+3V TO +5V
CNVST
SCLK
DOUT
MAX1274
MAX1275
SS
B) QSPI
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1274
MAX1275
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1274/MAX1275
______________________________________________________________________________________
13
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
CNVST
8
1
9
16
SCLK
DOUT
HIGH-Z
D11
D10
D7
D8
D9
D6
D5
D4
D3
D1
D2
HIGH-Z
D0
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
14
1
0
DOUT
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
16
D1
D0
1
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
DOUT
16
2
SCLK
HIGH-Z
HIGH-Z
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without CPU intervention. Connect the VL
pin to the TMS320C54_ supply voltage when the
MAX1274/MAX1275 are operating with an analog supply voltage higher than the DSP supply voltage. The
14
word length can be set to 8 bits with FO = 1 to implement the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
Another method of connecting the MAX1274/MAX1275
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16, where serial clock (CLOCK) drives the
CLKR, and SCLK and the convert signal (CONVERT)
drive the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
VL
DSP Interface to the ADSP21_ _ _
DVDD
MAX1274 SCLK
MAX1275
The MAX1274/MAX1275 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1274/MAX1275 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1274/MAX1275. For continuous conversions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conversions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL registers should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the VL pin to the ADSP21_ _ _ supply voltage
when the MAX1274/MAX1275 are operating with a supply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
CLKX TMS320C54_
CLKR
CNVST
FSX
FSR
DOUT
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
VL
DVDD
MAX1274
MAX1275 SCLK
CLKR
TMS320C54_
CNVST
FSR
DOUT
DR
intervention. Connect the VL pin to the TMS320C54_
supply
voltage
when
the
MAX1274/
MAX1275 are operating with an analog supply voltage
higher than the DSP supply voltage.
The MAX1274/MAX1275 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
CNVST
SCLK
DOUT
1
D0
0
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface—Continuous Conversion
______________________________________________________________________________________
15
MAX1274/MAX1275
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
CNVST
SCLK
1
DOUT
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
VL
VDDINT
MAX1274 SCLK
MAX1275
TCLK
ADSP21_ _ _
RCLK
CNVST
TFS
RFS
DOUT
DR
Figure 19. Interfacing to the ADSP21_ _ _
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the V DD power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
SUPPLIES
GND
VL
10μF
10μF
0.1μF
0.1μF
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1274/MAX1275 are measured using the end-points method.
Differential Nonlinearity
VDD
GND RGND
VL
MAX1274
MAX1275
DGND
VL
DIGITAL
CIRCUITRY
Figure 20. Power-Supply Grounding Condition
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
16
Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
______________________________________________________________________________________
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
(SINAD − 1.76)
ENOB =
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V 1 is the fundamental amplitude, and V 2
through V5 are the amplitudes of the 2nd- through 5thorder harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distortion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the
input signal amplitude attenuates by 3dB for a full-scale
input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal to noise plus distortion (SINAD) is equal to 68dB.
Intermodulation Distortion (IMD)
Any device with nonlinearities creates distortion products when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.
The intermodulation products are as follows:
• 2nd-order intermodulation products (IM2): f1 + f2,
f2 - f1
• 3rd-order intermodulation products (IM3): 2f1 - f2,
2f2 - f1, 2f1 + f2, 2f2 + f1
• 4th-order intermodulation products (IM4): 3f1 - f2,
3f2 - f1, 3f1 + f2, 3f2 + f1
• 5th-order intermodulation products (IM5): 3f1 - 2f2,
3f2 - 2f1, 3f1 + 2f2, 3f2 + 2f1
⎛
⎞
V22 + V32 + V42 + V52
⎜
⎟
THD = 20 x log
⎜
⎟
V
1
⎜
⎟
⎝
⎠
Package Information
Chip Information
TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
12 TQFN
T1244+3
21-0139
______________________________________________________________________________________
17
MAX1274/MAX1275
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-todigital noise is caused by quantization error, and results
directly from the ADC’s resolution (N bits):
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/04
Initial release
1
4/09
Removed commercial temperature grade parts from data sheet
DESCRIPTION
PAGES
CHANGED
—
1–8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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