19-3365; Rev 1; 4/09
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
The MAX1277/MAX1279 are low-power, high-speed, serial-output, 12-bit, analog-to-digital converters (ADCs) with
an internal reference that operates at up to 1.5Msps.
These devices feature true-differential inputs, offering better noise immunity, distortion improvements, and a wider
dynamic range over single-ended inputs. A standard
SPI™/QSPI™/MICROWIRE™ interface provides the clock
necessary for conversion. These devices easily interface
with standard digital signal processor (DSP) synchronous
serial interfaces.
The MAX1277/MAX1279 operate from a single +2.7V to
+3.6V supply voltage. The MAX1277/MAX1279 include a
2.048V internal reference. The MAX1277 has a unipolar
analog input, while the MAX1279 has a bipolar analog
input. These devices feature a partial power-down mode
and a full power-down mode for use between conversions, which lower the supply current to 2mA (typ) and
1µA (max), respectively. Also featured is a separate
power-supply input (VL), which allows direct interfacing to
+1.8V to VDD digital logic. The fast conversion speed,
low-power dissipation, excellent AC performance, and DC
accuracy (±1 LSB INL) make the MAX1277/MAX1279
ideal for industrial process control, motor control, and
base-station applications.
The MAX1277/MAX1279 come in a 12-pin TQFN package, and are available in the extended (-40°C to +85°C)
temperature range.
Applications
Data Acquisition
Communications
Bill Validation
Portable Instruments
Features
o 1.5Msps Sampling Rate
o Only 22mW (typ) Power Dissipation
o Only 1µA (max) Shutdown Current
o High-Speed, SPI-Compatible, 3-Wire Serial Interface
o 68.5dB S/(N + D) at 525kHz Input Frequency
o Internal True-Differential Track/Hold (T/H)
o Internal 2.048V Reference
o No Pipeline Delays
o Small 12-Pin TQFN Package
Ordering Information
PART
PINPACKAGE
TEMP RANGE
INPUT
MAX1277AETC-T
-40°C to +85°C 12 TQFN
Unipolar
MAX1277BETC-T
-40°C to +85°C 12 TQFN
Unipolar
MAX1279AETC-T
-40°C to +85°C 12 TQFN
Bipolar
MAX1279BETC-T
-40°C to +85°C 12 TQFN
Bipolar
Motor Control
Typical Operating Circuit
Pin Configuration
+1.8V TO VDD
+2.7V TO +3.6V
TOP VIEW
AIN+
N.C.
SCLK
12
11
10
0.01μF
10μF
0.01μF
VDD
AIN-
1
REF
2
RGND
3
9
MAX1277
MAX1279
CNVST
8
DOUT
7
VL
DIFFERENTIAL +
INPUT
VOLTAGE -
10μF
VL
DOUT
AIN+
AIN-
MAX1277
MAX1279
μC/DSP
CNVST
SCLK
4
VDD
5
6
N.C.
GND
REF
4.7μF
0.01μF
RGND
GND
TQFN
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1277/MAX1279
General Description
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VL to GND ................-0.3V to the lower of (VDD + 0.3V) and +6V
Digital Inputs
to GND .................-0.3V to the lower of (VDD + 0.3V) and +6V
Digital Output
to GND ....................-0.3V to the lower of (VL + 0.3V) and +6V
Analog Inputs and
REF to GND..........-0.3V to the lower of (VDD + 0.3V) and +6V
RGND to GND .......................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Range
MAX127_ _ ETC ..............................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, fSCLK = 24MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
Relative Accuracy (Note 1)
INL
Differential Nonlinearity (Note 2)
DNL
Bits
MAX127_A
-1.0
+1.0
MAX127_B
-1.5
+1.5
MAX127_A
-1.0
+1.0
MAX127_B
-1.0
+1.5
Offset Error
±8.0
Offset-Error Temperature
Coefficient
Offset nulled
±6.0
Gain Temperature Coefficient
LSB
LSB
ppm/°C
±1
Gain Error
LSB
LSB
±2
ppm/°C
68.5
dB
DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
66
Up to the 5th harmonic
fIN1 = 250kHz, fIN2 = 300kHz
-80
-76
-83
-76
dB
dB
-78
dB
Full-Power Bandwidth
-3dB point, small-signal method
15
MHz
Full-Linear Bandwidth
S/(N + D) > 68dB, single ended
1.2
MHz
CONVERSION RATE
Minimum Conversion Time
tCONV
(Note 3)
Maximum Throughput Rate
Minimum Throughput Rate
Track-and-Hold Acquisition Time
(Note 4)
tACQ
(Note 5)
Aperture Delay
Aperture Jitter
External Clock Frequency
2
(Note 6)
fSCLK
0.667
µs
1.5
Msps
10
ksps
125
ns
5
ns
30
ps
(Note 7)
_______________________________________________________________________________________
24
MHz
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
(VDD = +2.7V to +3.6V, VL = VDD, fSCLK = 24MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (AIN+, AIN-)
Differential Input Voltage Range
VIN
AIN+ - AIN-, MAX1277
0
VREF
AIN+ - AIN-, MAX1279
-VREF / 2
+VREF / 2
0
VDD
V
±1
µA
Absolute Input Voltage Range
DC Leakage Current
V
Input Capacitance
Per input pin
16
pF
Input Current (Average)
Time averaged at maximum throughput rate
75
µA
REFERENCE OUTPUT (REF)
REF Output Voltage Range
Static, TA = +25°C
2.038
Voltage Temperature Coefficient
2.048
2.058
±50
Load Regulation
Line Regulation
ISOURCE = 0 to 2mA
0.35
ISINK = 0 to 100µA
1.0
VDD = 2.7V to 3.6V, static
0.25
V
ppm/°C
mV/mA
mV/V
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low
VIL
Input Voltage High
VIH
Input Leakage Current
0.3 x VL
V
±10
µA
0.7 x VL
IIL
V
0.05
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
For stated timing performance
30
pF
Output Voltage Low
COUT
VOL
ISINK = 5mA, VL ≥ 1.8V
0.4
V
Output Voltage High
VOH
ISOURCE = 1mA, VL ≤ 1.8V
Output Leakage Current
IOL
Output high impedance
±10
µA
VL - 0.5V
V
±0.2
POWER REQUIREMENTS
Analog Supply Voltage
VDD
2.7
3.6
V
Digital Supply Voltage
VL
1.8
VDD
V
Analog Supply Current,
Normal Mode
IDD
Analog Supply Current,
Partial Power-Down Mode
IDD
Analog Supply Current,
Full Power-Down Mode
IDD
Digital Supply Current (Note 8)
Positive-Supply Rejection
PSR
Static, fSCLK = 24MHz
6
8
Static, no SCLK
5
7
Operational, 1.5Msps
7
9
fSCLK = 24MHz
2
No SCLK
2
fSCLK = 24MHz
1
No SCLK
0.3
mA
mA
1
µA
Operational, full-scale input at 1.5Msps
0.3
1
Static, fSCLK = 24MHz
0.15
0.5
Partial/full power-down mode,
fSCLK = 24MHz
0.1
0.3
Static, no SCLK, all modes
0.1
1
µA
±0.2
±3.0
mV
VDD = 3V +20% -10%, full-scale input
mA
_______________________________________________________________________________________
3
MAX1277/MAX1279
ELECTRICAL CHARACTERISTICS (continued)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, fSCLK = 24MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
VL = 2.7V to VDD
SCLK Pulse-Width High
tCH
VL = 1.8V to VDD, minimum recommended
(Note 7)
tCL
SCLK Rise to DOUT Transition
tDOUT
MAX
UNITS
ns
22.5
VL = 2.7V to VDD
SCLK Pulse-Width Low
TYP
18.7
18.7
VL = 1.8V to VDD, minimum recommended
(Note 7)
ns
22.5
CL = 30pF, VL = 2.7V to VDD
17
CL = 30pF, VL = 1.8V to VDD
24
ns
DOUT Remains Valid After SCLK
tDHOLD
VL = 1.8V to VDD
4
ns
CNVST Fall to SCLK Fall
tSETUP
VL = 1.8V to VDD
10
ns
tCSW
VL = 1.8V to VDD
20
CNVST Pulse Width
ns
Power-Up Time; Full Power-Down
tPWR-UP
2
ms
Restart Time; Partial Power-Down
tRCV
16
Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th rising edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for VL > 2.7V. See the Typical Operating Characteristics section for recommended sampling
speeds for VL < 2.7V.
Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
VL
CNVST
tCSW
tSETUP
tCL
tCH
SCLK
DOUT
tDHOLD
tDOUT
6kΩ
DOUT
DOUT
6kΩ
4
GND
GND
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
Figure 1. Detailed Serial-Interface Timing
CL
CL
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
Figure 2. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
0.50
19
0
1.8
2.1
2.4
2.7
3.0
3.3
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
0
3.6
1024
2048
3072
4096
-1.00
-2048
-1024
0
1024
VL (V)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
OFFSET ERROR
vs. TEMPERATURE (MAX1277)
DNL (LSB)
0.25
0
0.25
0
-0.25
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
0
1024
2048
3072
4096
-1.00
-2048
OFFSET ERROR
vs. TEMPERATURE (MAX1279)
-4
-5
1024
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE (MAX1277)
GAIN ERROR
vs. TEMPERATURE (MAX1279)
2
MAX1277/79 toc08
2
1
0
85
1
0
-1
-2
-3
-4
-2
-40
-4
DIGITAL OUTPUT CODE
-1
-6
-3
2048
GAIN ERROR (LSB)
-3
0
3
GAIN ERROR (LSB)
-2
-2
-6
-1024
4
MAX1277/79 toc07
-1
-1
-5
DIGITAL OUTPUT CODE
0
MAX1277/79 toc06
0.50
MAX1277/79 toc09
0.50
0.75
OFFSET ERROR (LSB)
0.75
2048
0
MAX1277/79 toc05
1.00
MAX1277/79 toc04
1.00
OFFSET ERROR (LSB)
0.50
-0.25
-1.00
17
DNL (LSB)
0.25
0.75
INL (LSB)
21
1.00
MAX1277/79 toc02
0.75
INL (LSB)
23
fSCLK (MHz)
1.00
MAX1277/79 toc01
25
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
MAX1277/79 toc03
MAXIMUM RECOMMENDED fSCLK vs. VL
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX1277/MAX1279
Typical Operating Characteristics
(VDD = +3V, VL = VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured at TA = +25°C.)
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured at TA = +25°C.)
DYNAMIC PERFORMANCE
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1279)
vs. INPUT FREQUENCY (MAX1277)
SNR
69.0
SINAD
68.5
SNR
69.5
69.0
SINAD
68.5
68.0
68.0
100
200
300
400
100
500
500
-88
MAX1277/79 toc13
90
SFDR (dB)
88
MAX1279
86
MAX1279
-92
MAX1277
84
82
-96
100
200
300
400
500
100
ANALOG INPUT FREQUENCY (kHz)
200
500
0
MAX1277/79 toc14
-60
-80
fIN = 500kHz
SINAD = 69.0dB
SNR = 69.1dB
THD = -88.9dB
SFDR = 85.9dB
-20
AMPLITUDE (dB)
fIN = 500kHz
SINAD = 68.7dB
SNR = 68.9dB
THD = -83.1dB
SFDR = 85.0dB
-40
400
FFT PLOT (MAX1279)
FFT PLOT (MAX1277)
0
-20
300
ANALOG INPUT FREQUENCY (kHz)
MAX1277/79 toc15
THD (dB)
400
92
MAX1277/79 toc12
MAX1277
-84
300
SFDR vs. INPUT FREQUENCY
THD vs. INPUT FREQUENCY
-80
200
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
-40
-60
-80
-100
-100
-120
-120
-140
-140
0
125
250
375
500
625
ANALOG INPUT FREQUENCY (kHz)
6
MAX1277/79 toc11
69.5
70.0
DYNAMIC PERFORMANCE (dB)
MAX1277/79 toc10
DYNAMIC PERFORMANCE (dB)
70.0
AMPLITUDE (dB)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
750
0
125
250
375
500
625
750
ANALOG INPUT FREQUENCY (kHz)
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
-80
fIN1 = 250.102kHz
fIN2 = 299.966kHz
IMD = -88.4dB
-20
-40
AMPLITUDE (dB)
fIN = 500kHz
-70
MAX1277/79 toc17
-60
THD (dB)
0
MAX1277/79 toc16
-50
fIN1
fIN2
-60
-80
-100
fIN = 100kHz
-90
-120
-100
-140
10
100
1000
125
250
375
500
625
750
ANALOG INPUT FREQUENCY (kHz)
TWO-TONE IMD PLOT (MAX1279)
VDD/VL FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
-20
-40
fIN1
fIN2
-60
-80
-100
1.00
MAX1277/79 toc19
fIN1 = 250.102kHz
fIN2 = 299.966kHz
IMD = -85.2dB
VDD/VL SUPPLY CURRENT (μA)
MAX1277/79 toc18
0
AMPLITUDE (dB)
0
SOURCE IMPEDANCE (Ω)
0.80
0.60
VL, NO SCLK
VDD, NO SCLK
0.40
VDD, SCLK = 24MHz
0.20
-120
0
-140
0
125
250
375
500
625
10
35
60
TEMPERATURE (°C)
VL PARTIAL/FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
VDD SUPPLY CURRENT
vs. TEMPERATURE
VL, = 1.8V, SCLK = 24MHz
VL, = 3V, SCLK = 24MHz
25
85
MAX1277/79 toc21
75
9.0
CONVERSION
VDD SUPPLY CURRENT (mA)
MAX1277/79 toc20
VL SUPPLY CURRENT (μA)
-15
ANALOG INPUT FREQUENCY (kHz)
100
50
-40
750
7.5
6.0
4.5
3.0
PARTIAL POWER-DOWN
1.5
0
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1277/MAX1279
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured at TA = +25°C.)
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
TWO-TONE IMD PLOT (MAX1277)
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = -40°C to +85°C, unless otherwise noted. Typical values are measured at TA = +25°C.)
VDD SUPPLY CURRENT
vs. CONVERSION RATE
VL SUPPLY CURRENT
vs. TEMPERATURE
4
2
0.30
CONVERSION, VL = 1.8V
0.20
0
250
500
750
1000
1250
1500
-40
-15
10
35
60
fSAMPLE (kHz)
TEMPERATURE (°C)
VL SUPPLY CURRENT
vs. CONVERSION RATE
REFERENCE VOLTAGE
vs. TEMPERATURE
200
VL = 3V
150
100
50
2.06
2.05
VL = 1.8V
85
MAX1277/79 toc25
MAX1277/79 toc24
250
REFERENCE VOLTAGE (V)
0
2.04
2.03
2.02
2.01
0
2.00
250
500
750
1000
1250
1500
-40
-15
10
35
60
fSAMPLE (kHz)
TEMPERATURE (°C)
REFERENCE VOLTAGE
vs. LOAD CURRENT (SOURCE)
REFERENCE VOLTAGE
vs. LOAD CURRENT (SINK)
MAX1277/79 toc26
2.05
2.04
2.03
2.02
2.01
2.08
REFERENCE VOLTAGE (V)
0
85
MAX1277/79 toc27
VL SUPPLY CURRENT (μA)
CONVERSION, VL = 3V
0.10
0
2.07
2.06
2.05
2.04
0
2
4
LOAD CURRENT (mA)
8
0.40
MAX1277/79 toc23
6
0.50
VL SUPPLY CURRENT (mA)
MAX1277/79 toc22
VDD SUPPLY CURRENT (mA)
8
REFERENCE VOLTAGE (V)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
6
8
0
50
100
150
200
LOAD CURRENT (μA)
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
PIN
NAME
FUNCTION
1
AIN-
Negative Analog Input
2
REF
Reference Voltage Output. Internal 2.048V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.
3
RGND
4
VDD
Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
5, 11
N.C.
No Connection
6
GND
Ground. GND is internally connected to EP.
7
VL
8
DOUT
Serial Data Output. Data is clocked out on the rising edge of SCLK.
9
CNVST
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
10
SCLK
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
12
AIN+
—
EP
Reference Ground. Connect RGND to GND.
Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
VDD
VL
CAPACITIVE
DAC
CIN+
REF
2.048V
REF
RIN+
AIN+
AIN +
12-BIT
SAR
ADC
TRACK AND
HOLD
AIN -
OUTPUT
BUFFER
VAZ
DOUT
COMP
CONTROL
LOGIC
AINCIN-
CONTROL
LOGIC AND
TIMING
RGND
RIN-
ACQUISITION MODE
CNVST
SCLK
MAX1277
MAX1279
CAPACITIVE
DAC
CIN+
RIN+
AIN+
GND
VAZ
COMP
CONTROL
LOGIC
Figure 3. Functional Diagram
Detailed Description
The MAX1277/MAX1279 use an input T/H and successive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1277/MAX1279.
AINCIN-
RINHOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
9
MAX1277/MAX1279
Pin Description
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
True-Differential Analog Input T/H
signal bandwidth, making it possible to digitize highspeed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
The equivalent circuit of Figure 4 shows the input architecture of the MAX1277/MAX1279, which is composed
of a T/H, a comparator, and a switched-capacitor digital-to-analog converter (DAC). The T/H enters its tracking mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is connected to AIN+. The negative input capacitor is connected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by the following equation:
tACQ ≥ 9 × (RS + RIN) × 16pF
where RIN = 200Ω, and RS is the source impedance of
the input signal.
Note: tACQ is never less than 125ns and any source
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
Analog Input Protection
Internal protection diodes that clamp the analog input
to VDD and GND allow the analog input pins to swing
from GND - 0.3V to VDD + 0.3V without damage. Both
inputs must not exceed VDD or be lower than GND for
accurate conversions.
Serial Interface
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1277/MAX1279 require a
complete conversion cycle to initialize the internal calibration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conversion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
Input Bandwidth
The ADC’s input-tracking circuitry has a 15MHz small-
CNVST
tSETUP
tACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
16
POWER-MODE SELECTION WINDOW
1
SCLK
2
3
4
HIGH IMPEDANCE
8
D11
DOUT
D10
D9
D8
14
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Interface-Timing Sequence
CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
CNVST
ONE 8-BIT TRANSFER
SCLK
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
DOUT
MODE
0
0
0
D11
D10
D9
D8
D7
NORMAL
REF
PPD
ENABLED (2.048V)
Figure 6. SPI Interface—Partial Power-Down Mode
10
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
Full power-down mode is ideal for infrequent data sampling and very low supply current applications. The
MAX1277/MAX1279 have to be in partial power-down
mode to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full powerdown mode. While in full power-down mode, the reference is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t DOUT after each
SCLK’s rising edge and remains valid 4ns (tDHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1277. Figure 9 shows the bipolar transfer function for
the MAX1279. The MAX1277 output is straight binary,
while the MAX1279 output is two’s complement.
Applications Information
Internal Reference
The MAX1277/MAX1279 have an on-chip voltage reference trimmed to 2.048V. The internal reference output
is connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to
2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF
capacitor to RGND.
The internal reference is continuously powered up during both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Be sure to allow at least 2ms recovery time after hardware power-up or exiting full power-down mode for the
reference to reach its intended value.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by placing the MAX1277/MAX1279 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wakeup time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 2mA. While in partial power-down mode, the reference remains enabled to
allow valid conversions once the IC is returned to normal
mode. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit partial
power-down mode.
EXECUTE PARTIAL POWER-DOWN TWICE
CNVST
FIRST 8-BIT TRANSFER
SECOND 8-BIT TRANSFER
SCLK
1ST SCLK RISING EDGE
DOUT
MODE
0
0
0
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
D11
NORMAL
REF
D10
D9
D8
0
D7
PPD
ENABLED (2.048V)
0
0
0
0
RECOVERY
0
0
0
FPD
DISABLED
Figure 7. SPI Interface—Full Power-Down Mode
______________________________________________________________________________________
11
MAX1277/MAX1279
Timing and Control
Conversion-start and data-read operations are controlled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serialinterface operation.
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conversion is determined.
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
How to Start a Conversion
OUTPUT CODE
FULL-SCALE
TRANSITION
111...111
111...110
111...101
FS = VREF
ZS = 0
V
1 LSB = REF
4096
000...011
000...010
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out on
DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high impedance on the next rising edge of CNVST or SCLK, enabling
the serial interface to be shared by multiple devices. If
CNVST returns high after the 14th, but before the 16th
SCLK rising edge, DOUT remains active so continuous
conversions can be sustained. The highest throughput is
achieved when performing continuous conversions. Figure
10 illustrates a conversion using a typical serial interface.
Connection to
Standard Interfaces
000...001
000...000
0
1
2
3
FS
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function (MAX1277 Only)
The MAX1277/MAX1279 serial interface is fully compatible with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 24MHz.
SPI and MICROWIRE
OUTPUT CODE
FULL-SCALE
TRANSITION
V
FS = REF
2
ZS = 0
-V
- FS = REF
2
V
1 LSB = REF
4096
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
QSPI
100...001
100...000
-FS
0
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 9. Bipolar Transfer Function (MAX1279 Only)
12
When using SPI or MICROWIRE, the MAX1277/ MAX1279
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid tDOUT later and
remains valid until tDHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0, or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the following rising edge. When using CPOL = 0 and CPHA = 1,
or CPOL = 1 and CPHA = 0, the data is clocked into the
µP on the next falling edge. See Figure 11 for connections
and Figures 12 and 13 for timing. See the Timing
Characteristics section to determine the best mode to use.
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the
data. The MAX1277/MAX1279 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSB-
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
MAX1277/MAX1279
CNVST
SCLK
1
14
16
1
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 10. Continuous Conversion with Burst/Continuous Clock
I/O
SCK
MISO
+3V TO +5V
CNVST
SCLK
DOUT
MAX1277
MAX1279
SS
A) SPI
CS
SCK
MISO
+3V TO +5V
CNVST
SCLK
DOUT
MAX1277
MAX1279
SS
B) QSPI
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1277
MAX1279
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1277/MAX1279
______________________________________________________________________________________
13
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
CNVST
8
1
9
16
SCLK
DOUT
HIGH-Z
D11
D10
D7
D8
D9
D6
D5
D4
D3
D1
D2
HIGH-Z
D0
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
14
1
0
DOUT
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
16
D1
D0
1
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
DOUT
16
2
SCLK
HIGH-Z
HIGH-Z
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
first format.
DSP Interface to the TMS320C54_
The MAX1277/MAX1279 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1277/MAX1279 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
14
For continuous conversion, set the serial port to transmit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port configuration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
VL
Figure 16, where serial clock (CLOCK) drives the
CLKR, and SCLK and the convert signal (CONVERT)
drive the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
intervention. Connect the VL pin to the TMS320C54_
supply voltage when the MAX1277/MAX1279 are operating with an analog supply voltage higher than the
DSP supply voltage.
DVDD
MAX1277 SCLK
MAX1279
CLKX TMS320C54_
CLKR
CNVST
FSX
FSR
DOUT
The MAX1277/MAX1279 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
VL
DVDD
MAX1277
MAX1279 SCLK
CLKR
TMS320C54_
CNVST
FSR
DOUT
DR
DSP Interface to the ADSP21_ _ _
The MAX1277/MAX1279 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1277/MAX1279 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1277/MAX1279. For continuous conversions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
CNVST
SCLK
DOUT
1
D0
0
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface—Continuous Conversion
______________________________________________________________________________________
15
MAX1277/MAX1279
read the data without CPU intervention. Connect the VL
pin to the TMS320C54_ supply voltage when the
MAX1277/MAX1279 are operating with an analog supply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to implement the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
Another method of connecting the MAX1277/MAX1279
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
CNVST
SCLK
1
DOUT
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
VL
VDDINT
MAX1277 SCLK
MAX1279
TCLK
ADSP21_ _ _
RCLK
CNVST
TFS
RFS
DOUT
DR
Layout, Grounding, and Bypassing
Figure 19. Interfacing to the ADSP21_ _ _
SUPPLIES
GND
VL
10μF
10μF
0.1μF
0.1μF
VDD
GND RGND
VL
MAX1277
MAX1279
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the VL pin to the ADSP21_ _ _ supply voltage
when the MAX1277/MAX1279 are operating with a supply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
DGND
VL
DIGITAL
CIRCUITRY
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the V DD power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
Figure 20. Power-Supply Grounding Condition
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conversions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis16
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1277/MAX1279 are measured using the end-points method.
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-todigital noise is caused by quantization error, and results
directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
ENOB =
(SINAD − 1.76)
6.02
⎛
⎞
V22 + V32 + V42 + V52
⎜
⎟
THD = 20 x log
⎜
⎟
V1
⎜
⎟
⎝
⎠
where V 1 is the fundamental amplitude, and V 2
through V5 are the amplitudes of the 2nd- through 5thorder harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distortion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the
input signal amplitude attenuates by 3dB for a full-scale
input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal to noise plus distortion (SINAD) is equal to 68dB.
Intermodulation Distortion (IMD)
Any device with nonlinearities creates distortion products when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.
The intermodulation products are as follows:
• 2nd-order intermodulation products (IM2): f1 + f2,
f2 - f1
• 3rd-order intermodulation products (IM3): 2f1 - f2,
2f2 - f1, 2f1 + f2, 2f2 + f1
• 4th-order intermodulation products (IM4): 3f1 - f2,
3f2 - f1, 3f1 + f2, 3f2 + f1
• 5th-order intermodulation products (IM5): 3f1 - 2f2,
3f2 - 2f1, 3f1 + 2f2, 3f2 + 2f1
Package Information
Chip Information
TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
12 TQFN
T1244+3
21-0139
______________________________________________________________________________________
17
MAX1277/MAX1279
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, TrueDifferential, 12-Bit ADCs with Internal Reference
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
8/04
Initial release
1
4/09
Removed commercial temperature grade parts from data sheet
PAGES
CHANGED
—
1–8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
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